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| author | Tanya Lattner <tonic@nondot.org> | 2011-04-07 15:24:20 +0000 |
|---|---|---|
| committer | Tanya Lattner <tonic@nondot.org> | 2011-04-07 15:24:20 +0000 |
| commit | 0433b21c989e7d4817574b950387355fe05f59b5 (patch) | |
| tree | 6575a62e88e7e323f38ca9560685aa16677ed3e0 | |
| parent | 71001c97c6dda3df509ba4b9b37f979ea1aa8127 (diff) | |
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 6 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vector-DAGCombine.ll | 18 |
2 files changed, 24 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index d030f68528..330a7816f5 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -5390,6 +5390,9 @@ static SDValue PerformANDCombine(SDNode *N, EVT VT = N->getValueType(0); SelectionDAG &DAG = DCI.DAG; + if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) + return SDValue(); + APInt SplatBits, SplatUndef; unsigned SplatBitSize; bool HasAnyUndefs; @@ -5423,6 +5426,9 @@ static SDValue PerformORCombine(SDNode *N, EVT VT = N->getValueType(0); SelectionDAG &DAG = DCI.DAG; + if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) + return SDValue(); + APInt SplatBits, SplatUndef; unsigned SplatBitSize; bool HasAnyUndefs; diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll index 3ab0cfcbbc..81bdc44863 100644 --- a/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -105,3 +105,21 @@ define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind { store i64 %t1, i64* %ptr ret void } + +; Test trying to do a AND Combine on illegal types. +define void @andVec(<3 x i8>* %A) nounwind { + %tmp = load <3 x i8>* %A, align 4 + %and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7> + store <3 x i8> %and, <3 x i8>* %A + ret void +} + + +; Test trying to do an OR Combine on illegal types. +define void @orVec(<3 x i8>* %A) nounwind { + %tmp = load <3 x i8>* %A, align 4 + %or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7> + store <3 x i8> %or, <3 x i8>* %A + ret void +} + |