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path: root/scripts/diffconfig
blob: b91f3e34d44d5d39907b8bbef3de4fb6f37fbb69 (plain)
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#!/usr/bin/python
#
# diffconfig - a tool to compare .config files.
#
# originally written in 2006 by Matt Mackall
#  (at least, this was in his bloatwatch source code)
# last worked on 2008 by Tim Bird
#

import sys, os

def usage():
    print """Usage: diffconfig [-h] [-m] [<config1> <config2>]

Diffconfig is a simple utility for comparing two .config files.
Using standard diff to compare .config files often includes extraneous and
distracting information.  This utility produces sorted output with only the
changes in configuration values between the two files.

Added and removed items are shown with a leading plus or minus, respectively.
Changed items show the old and new values on a single line.

If -m is specified, then output will be in "merge" style, which has the
changed and new values in kernel config option format.

If no config files are specified, .config and .config.old are used.

Example usage:
 $ diffconfig .config config-with-some-changes
-EXT2_FS_XATTR  n
-EXT2_FS_XIP  n
 CRAMFS  n -> y
 EXT2_FS  y -> n
 LOG_BUF_SHIFT  14 -> 16
 PRINTK_TIME  n -> y
"""
    sys.exit(0)

# returns a dictionary of name/value pairs for config items in the file
def readconfig(config_file):
    d = {}
    for line in config_file:
        line = line[:-1]
        if line[:7] == "CONFIG_":
            name, val = line[7:].split("=", 1)
            d[name] = val
        if line[-11:] == " is not set":
            d[line[9:-11]] = "n"
    return d

def print_config(op, config, value, new_value):
    global merge_style

    if merge_style:
        if new_value:
            if new_value=="n":
                print "# CONFIG_%s is not set" % config
            else:
                print "CONFIG_%s=%s" % (config, new_value)
    else:
        if op=="-":
            print "-%s %s" % (config, value)
        elif op=="+":
            print "+%s %s" % (config, new_value)
        else:
            print " %s %s -> %s" % (config, value, new_value)

def main():
    global merge_style

    # parse command line args
    if ("-h" in sys.argv or "--help" in sys.argv):
	usage()

    merge_style = 0
    if "-m" in sys.argv:
        merge_style = 1
        sys.argv.remove("-m")

    argc = len(sys.argv)
    if not (argc==1 or argc == 3):
        print "Error: incorrect number of arguments or unrecognized option"
        usage()

    if argc == 1:
        # if no filenames given, assume .config and .config.old
        build_dir=""
        if os.environ.has_key("KBUILD_OUTPUT"):
            build_dir = os.environ["KBUILD_OUTPUT"]+"/"

        configa_filename = build_dir + ".config.old"
        configb_filename = build_dir + ".config"
    else:
        configa_filename = sys.argv[1]
        configb_filename = sys.argv[2]

    a = readconfig(file(configa_filename))
    b = readconfig(file(configb_filename))

    # print items in a but not b (accumulate, sort and print)
    old = []
    for config in a:
        if config not in b:
            old.append(config)
    old.sort()
    for config in old:
        print_config("-", config, a[config], None)
        del a[config]

    # print items that changed (accumulate, sort, and print)
    changed = []
    for config in a:
        if a[config] != b[config]:
            changed.append(config)
        else:
            del b[config]
    changed.sort()
    for config in changed:
        print_config("->", config, a[config], b[config])
        del b[config]

    # now print items in b but not in a
    # (items from b that were in a were removed above)
    new = b.keys()
    new.sort()
    for config in new:
        print_config("+", config, None, b[config])

main()
'>280
-rw-r--r--drivers/media/dvb/frontends/drxd.h73
-rw-r--r--drivers/media/dvb/frontends/drxd_firm.c929
-rw-r--r--drivers/media/dvb/frontends/drxd_firm.h115
-rw-r--r--drivers/media/dvb/frontends/drxd_hard.c2992
-rw-r--r--drivers/media/dvb/frontends/drxd_map_firm.h1013
-rw-r--r--drivers/media/dvb/frontends/drxk.h66
-rw-r--r--drivers/media/dvb/frontends/drxk_hard.c6637
-rw-r--r--drivers/media/dvb/frontends/drxk_hard.h364
-rw-r--r--drivers/media/dvb/frontends/drxk_map.h451
-rw-r--r--drivers/media/dvb/frontends/ds3000.c1312
-rw-r--r--drivers/media/dvb/frontends/ds3000.h48
-rw-r--r--drivers/media/dvb/frontends/dvb-pll.c820
-rw-r--r--drivers/media/dvb/frontends/dvb-pll.h57
-rw-r--r--drivers/media/dvb/frontends/dvb_dummy_fe.c276
-rw-r--r--drivers/media/dvb/frontends/dvb_dummy_fe.h51
-rw-r--r--drivers/media/dvb/frontends/ec100.c335
-rw-r--r--drivers/media/dvb/frontends/ec100.h46
-rw-r--r--drivers/media/dvb/frontends/ec100_priv.h39
-rw-r--r--drivers/media/dvb/frontends/eds1547.h133
-rw-r--r--drivers/media/dvb/frontends/hd29l2.c861
-rw-r--r--drivers/media/dvb/frontends/hd29l2.h66
-rw-r--r--drivers/media/dvb/frontends/hd29l2_priv.h314
-rw-r--r--drivers/media/dvb/frontends/isl6405.c164
-rw-r--r--drivers/media/dvb/frontends/isl6405.h74
-rw-r--r--drivers/media/dvb/frontends/isl6421.c141
-rw-r--r--drivers/media/dvb/frontends/isl6421.h55
-rw-r--r--drivers/media/dvb/frontends/isl6423.c308
-rw-r--r--drivers/media/dvb/frontends/isl6423.h63
-rw-r--r--drivers/media/dvb/frontends/it913x-fe-priv.h1051
-rw-r--r--drivers/media/dvb/frontends/it913x-fe.c1045
-rw-r--r--drivers/media/dvb/frontends/it913x-fe.h237
-rw-r--r--drivers/media/dvb/frontends/itd1000.c399
-rw-r--r--drivers/media/dvb/frontends/itd1000.h42
-rw-r--r--drivers/media/dvb/frontends/itd1000_priv.h88
-rw-r--r--drivers/media/dvb/frontends/ix2505v.c325
-rw-r--r--drivers/media/dvb/frontends/ix2505v.h64
-rw-r--r--drivers/media/dvb/frontends/l64781.c609
-rw-r--r--drivers/media/dvb/frontends/l64781.h46
-rw-r--r--drivers/media/dvb/frontends/lg2160.c1468
-rw-r--r--drivers/media/dvb/frontends/lg2160.h84
-rw-r--r--drivers/media/dvb/frontends/lgdt3305.c1222
-rw-r--r--drivers/media/dvb/frontends/lgdt3305.h91
-rw-r--r--drivers/media/dvb/frontends/lgdt330x.c831
-rw-r--r--drivers/media/dvb/frontends/lgdt330x.h73
-rw-r--r--drivers/media/dvb/frontends/lgdt330x_priv.h77
-rw-r--r--drivers/media/dvb/frontends/lgs8gl5.c453
-rw-r--r--drivers/media/dvb/frontends/lgs8gl5.h45
-rw-r--r--drivers/media/dvb/frontends/lgs8gxx.c1075
-rw-r--r--drivers/media/dvb/frontends/lgs8gxx.h95
-rw-r--r--drivers/media/dvb/frontends/lgs8gxx_priv.h70
-rw-r--r--drivers/media/dvb/frontends/lnbh24.h55
-rw-r--r--drivers/media/dvb/frontends/lnbp21.c188
-rw-r--r--drivers/media/dvb/frontends/lnbp21.h75
-rw-r--r--drivers/media/dvb/frontends/lnbp22.c148
-rw-r--r--drivers/media/dvb/frontends/lnbp22.h57
-rw-r--r--drivers/media/dvb/frontends/m88rs2000.c919
-rw-r--r--drivers/media/dvb/frontends/m88rs2000.h66
-rw-r--r--drivers/media/dvb/frontends/mb86a16.c1878
-rw-r--r--drivers/media/dvb/frontends/mb86a16.h52
-rw-r--r--drivers/media/dvb/frontends/mb86a16_priv.h151
-rw-r--r--drivers/media/dvb/frontends/mb86a20s.c701
-rw-r--r--drivers/media/dvb/frontends/mb86a20s.h52
-rw-r--r--drivers/media/dvb/frontends/mt312.c839
-rw-r--r--drivers/media/dvb/frontends/mt312.h51
-rw-r--r--drivers/media/dvb/frontends/mt312_priv.h165
-rw-r--r--drivers/media/dvb/frontends/mt352.c610
-rw-r--r--drivers/media/dvb/frontends/mt352.h73
-rw-r--r--drivers/media/dvb/frontends/mt352_priv.h127
-rw-r--r--drivers/media/dvb/frontends/nxt200x.c1242
-rw-r--r--drivers/media/dvb/frontends/nxt200x.h63
-rw-r--r--drivers/media/dvb/frontends/nxt6000.c616
-rw-r--r--drivers/media/dvb/frontends/nxt6000.h48
-rw-r--r--drivers/media/dvb/frontends/nxt6000_priv.h286
-rw-r--r--drivers/media/dvb/frontends/or51132.c631
-rw-r--r--drivers/media/dvb/frontends/or51132.h55
-rw-r--r--drivers/media/dvb/frontends/or51211.c581
-rw-r--r--drivers/media/dvb/frontends/or51211.h53
-rw-r--r--drivers/media/dvb/frontends/rtl2830.c757
-rw-r--r--drivers/media/dvb/frontends/rtl2830.h97
-rw-r--r--drivers/media/dvb/frontends/rtl2830_priv.h58
-rw-r--r--drivers/media/dvb/frontends/rtl2832.c789
-rw-r--r--drivers/media/dvb/frontends/rtl2832.h74
-rw-r--r--drivers/media/dvb/frontends/rtl2832_priv.h260
-rw-r--r--drivers/media/dvb/frontends/s5h1409.c1029
-rw-r--r--drivers/media/dvb/frontends/s5h1409.h88
-rw-r--r--drivers/media/dvb/frontends/s5h1411.c951
-rw-r--r--drivers/media/dvb/frontends/s5h1411.h90
-rw-r--r--drivers/media/dvb/frontends/s5h1420.c960
-rw-r--r--drivers/media/dvb/frontends/s5h1420.h61
-rw-r--r--drivers/media/dvb/frontends/s5h1420_priv.h102
-rw-r--r--drivers/media/dvb/frontends/s5h1432.c407
-rw-r--r--drivers/media/dvb/frontends/s5h1432.h91
-rw-r--r--drivers/media/dvb/frontends/s921.c549
-rw-r--r--drivers/media/dvb/frontends/s921.h47
-rw-r--r--drivers/media/dvb/frontends/si21xx.c951
-rw-r--r--drivers/media/dvb/frontends/si21xx.h37
-rw-r--r--drivers/media/dvb/frontends/sp8870.c620
-rw-r--r--drivers/media/dvb/frontends/sp8870.h50
-rw-r--r--drivers/media/dvb/frontends/sp887x.c629
-rw-r--r--drivers/media/dvb/frontends/sp887x.h32
-rw-r--r--drivers/media/dvb/frontends/stb0899_algo.c1525
-rw-r--r--drivers/media/dvb/frontends/stb0899_cfg.h287
-rw-r--r--drivers/media/dvb/frontends/stb0899_drv.c1651
-rw-r--r--drivers/media/dvb/frontends/stb0899_drv.h162
-rw-r--r--drivers/media/dvb/frontends/stb0899_priv.h263
-rw-r--r--drivers/media/dvb/frontends/stb0899_reg.h2027
-rw-r--r--drivers/media/dvb/frontends/stb6000.c256
-rw-r--r--drivers/media/dvb/frontends/stb6000.h51
-rw-r--r--drivers/media/dvb/frontends/stb6100.c611
-rw-r--r--drivers/media/dvb/frontends/stb6100.h115
-rw-r--r--drivers/media/dvb/frontends/stb6100_cfg.h104
-rw-r--r--drivers/media/dvb/frontends/stb6100_proc.h138
-rw-r--r--drivers/media/dvb/frontends/stv0288.c626
-rw-r--r--drivers/media/dvb/frontends/stv0288.h67
-rw-r--r--drivers/media/dvb/frontends/stv0297.c722
-rw-r--r--drivers/media/dvb/frontends/stv0297.h57
-rw-r--r--drivers/media/dvb/frontends/stv0299.c762
-rw-r--r--drivers/media/dvb/frontends/stv0299.h118
-rw-r--r--drivers/media/dvb/frontends/stv0367.c3450
-rw-r--r--drivers/media/dvb/frontends/stv0367.h66
-rw-r--r--drivers/media/dvb/frontends/stv0367_priv.h212
-rw-r--r--drivers/media/dvb/frontends/stv0367_regs.h3614
-rw-r--r--drivers/media/dvb/frontends/stv0900.h74
-rw-r--r--drivers/media/dvb/frontends/stv0900_core.c1959
-rw-r--r--drivers/media/dvb/frontends/stv0900_init.h584
-rw-r--r--drivers/media/dvb/frontends/stv0900_priv.h408
-rw-r--r--drivers/media/dvb/frontends/stv0900_reg.h3981
-rw-r--r--drivers/media/dvb/frontends/stv0900_sw.c2032
-rw-r--r--drivers/media/dvb/frontends/stv090x.c4823
-rw-r--r--drivers/media/dvb/frontends/stv090x.h134
-rw-r--r--drivers/media/dvb/frontends/stv090x_priv.h279
-rw-r--r--drivers/media/dvb/frontends/stv090x_reg.h2371
-rw-r--r--drivers/media/dvb/frontends/stv6110.c451
-rw-r--r--drivers/media/dvb/frontends/stv6110.h63
-rw-r--r--drivers/media/dvb/frontends/stv6110x.c405
-rw-r--r--drivers/media/dvb/frontends/stv6110x.h73
-rw-r--r--drivers/media/dvb/frontends/stv6110x_priv.h76
-rw-r--r--drivers/media/dvb/frontends/stv6110x_reg.h82
-rw-r--r--drivers/media/dvb/frontends/tda10021.c528
-rw-r--r--drivers/media/dvb/frontends/tda10023.c610
-rw-r--r--drivers/media/dvb/frontends/tda1002x.h87
-rw-r--r--drivers/media/dvb/frontends/tda10048.c1191
-rw-r--r--drivers/media/dvb/frontends/tda10048.h90
-rw-r--r--drivers/media/dvb/frontends/tda1004x.c1381
-rw-r--r--drivers/media/dvb/frontends/tda1004x.h149
-rw-r--r--drivers/media/dvb/frontends/tda10071.c1284
-rw-r--r--drivers/media/dvb/frontends/tda10071.h81
-rw-r--r--drivers/media/dvb/frontends/tda10071_priv.h109
-rw-r--r--drivers/media/dvb/frontends/tda10086.c777
-rw-r--r--drivers/media/dvb/frontends/tda10086.h61
-rw-r--r--drivers/media/dvb/frontends/tda18271c2dd.c1246
-rw-r--r--drivers/media/dvb/frontends/tda18271c2dd.h16
-rw-r--r--drivers/media/dvb/frontends/tda18271c2dd_maps.h814
-rw-r--r--drivers/media/dvb/frontends/tda665x.c258
-rw-r--r--drivers/media/dvb/frontends/tda665x.h52
-rw-r--r--drivers/media/dvb/frontends/tda8083.c487
-rw-r--r--drivers/media/dvb/frontends/tda8083.h50
-rw-r--r--drivers/media/dvb/frontends/tda8261.c230
-rw-r--r--drivers/media/dvb/frontends/tda8261.h55
-rw-r--r--drivers/media/dvb/frontends/tda8261_cfg.h84
-rw-r--r--drivers/media/dvb/frontends/tda826x.c188
-rw-r--r--drivers/media/dvb/frontends/tda826x.h53
-rw-r--r--drivers/media/dvb/frontends/tdhd1.h74
-rw-r--r--drivers/media/dvb/frontends/tua6100.c206
-rw-r--r--drivers/media/dvb/frontends/tua6100.h47
-rw-r--r--drivers/media/dvb/frontends/ves1820.c447
-rw-r--r--drivers/media/dvb/frontends/ves1820.h56
-rw-r--r--drivers/media/dvb/frontends/ves1x93.c553
-rw-r--r--drivers/media/dvb/frontends/ves1x93.h55
-rw-r--r--drivers/media/dvb/frontends/z0194a.h85
-rw-r--r--drivers/media/dvb/frontends/zl10036.c520
-rw-r--r--drivers/media/dvb/frontends/zl10036.h53
-rw-r--r--drivers/media/dvb/frontends/zl10039.c307
-rw-r--r--drivers/media/dvb/frontends/zl10039.h40
-rw-r--r--drivers/media/dvb/frontends/zl10353.c684
-rw-r--r--drivers/media/dvb/frontends/zl10353.h62
-rw-r--r--drivers/media/dvb/frontends/zl10353_priv.h79
238 files changed, 0 insertions, 128830 deletions
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
deleted file mode 100644
index a08c2152d0e..00000000000
--- a/drivers/media/dvb/frontends/Kconfig
+++ /dev/null
@@ -1,756 +0,0 @@
-config DVB_FE_CUSTOMISE
- bool "Customise the frontend modules to build"
- depends on DVB_CORE
- depends on EXPERT
- default y if EXPERT
- help
- This allows the user to select/deselect frontend drivers for their
- hardware from the build.
-
- Use this option with care as deselecting frontends which are in fact
- necessary will result in DVB devices which cannot be tuned due to lack
- of driver support.
-
- If unsure say N.
-
-menu "Customise DVB Frontends"
- visible if DVB_FE_CUSTOMISE
-
-comment "Multistandard (satellite) frontends"
- depends on DVB_CORE
-
-config DVB_STB0899
- tristate "STB0899 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S/S2/DSS Multistandard demodulator. Say Y when you want
- to support this demodulator based frontends
-
-config DVB_STB6100
- tristate "STB6100 based tuners"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A Silicon tuner from ST used in conjunction with the STB0899
- demodulator. Say Y when you want to support this tuner.
-
-config DVB_STV090x
- tristate "STV0900/STV0903(A/B) based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- DVB-S/S2/DSS Multistandard Professional/Broadcast demodulators.
- Say Y when you want to support these frontends.
-
-config DVB_STV6110x
- tristate "STV6110/(A) based tuners"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A Silicon tuner that supports DVB-S and DVB-S2 modes
-
-comment "Multistandard (cable + terrestrial) frontends"
- depends on DVB_CORE
-
-config DVB_DRXK
- tristate "Micronas DRXK based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- Micronas DRX-K DVB-C/T demodulator.
-
- Say Y when you want to support this frontend.
-
-config DVB_TDA18271C2DD
- tristate "NXP TDA18271C2 silicon tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- NXP TDA18271 silicon tuner.
-
- Say Y when you want to support this tuner.
-
-comment "DVB-S (satellite) frontends"
- depends on DVB_CORE
-
-config DVB_CX24110
- tristate "Conexant CX24110 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_CX24123
- tristate "Conexant CX24123 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_MT312
- tristate "Zarlink VP310/MT312/ZL10313 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_ZL10036
- tristate "Zarlink ZL10036 silicon tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_ZL10039
- tristate "Zarlink ZL10039 silicon tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_S5H1420
- tristate "Samsung S5H1420 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_STV0288
- tristate "ST STV0288 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_STB6000
- tristate "ST STB6000 silicon tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S silicon tuner module. Say Y when you want to support this tuner.
-
-config DVB_STV0299
- tristate "ST STV0299 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_STV6110
- tristate "ST STV6110 silicon tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S silicon tuner module. Say Y when you want to support this tuner.
-
-config DVB_STV0900
- tristate "ST STV0900 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S/S2 demodulator. Say Y when you want to support this frontend.
-
-config DVB_TDA8083
- tristate "Philips TDA8083 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_TDA10086
- tristate "Philips TDA10086 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_TDA8261
- tristate "Philips TDA8261 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_VES1X93
- tristate "VLSI VES1893 or VES1993 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_TUNER_ITD1000
- tristate "Integrant ITD1000 Zero IF tuner for DVB-S/DSS"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_TUNER_CX24113
- tristate "Conexant CX24113/CX24128 tuner for DVB-S/DSS"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-
-config DVB_TDA826X
- tristate "Philips TDA826X silicon tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S silicon tuner module. Say Y when you want to support this tuner.
-
-config DVB_TUA6100
- tristate "Infineon TUA6100 PLL"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S PLL chip.
-
-config DVB_CX24116
- tristate "Conexant CX24116 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S/S2 tuner module. Say Y when you want to support this frontend.
-
-config DVB_SI21XX
- tristate "Silicon Labs SI21XX based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_DS3000
- tristate "Montage Tehnology DS3000 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S/S2 tuner module. Say Y when you want to support this frontend.
-
-config DVB_MB86A16
- tristate "Fujitsu MB86A16 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S/DSS Direct Conversion reveiver.
- Say Y when you want to support this frontend.
-
-config DVB_TDA10071
- tristate "NXP TDA10071"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- Say Y when you want to support this frontend.
-
-comment "DVB-T (terrestrial) frontends"
- depends on DVB_CORE
-
-config DVB_SP8870
- tristate "Spase sp8870 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
- This driver needs external firmware. Please use the command
- "<kerneldir>/Documentation/dvb/get_dvb_firmware sp8870" to
- download/extract it, and then copy it to /usr/lib/hotplug/firmware
- or /lib/firmware (depending on configuration of firmware hotplug).
-
-config DVB_SP887X
- tristate "Spase sp887x based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
- This driver needs external firmware. Please use the command
- "<kerneldir>/Documentation/dvb/get_dvb_firmware sp887x" to
- download/extract it, and then copy it to /usr/lib/hotplug/firmware
- or /lib/firmware (depending on configuration of firmware hotplug).
-
-config DVB_CX22700
- tristate "Conexant CX22700 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
-config DVB_CX22702
- tristate "Conexant cx22702 demodulator (OFDM)"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
-config DVB_S5H1432
- tristate "Samsung s5h1432 demodulator (OFDM)"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
-config DVB_DRXD
- tristate "Micronas DRXD driver"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
- Note: this driver was based on vendor driver reference code (released
- under the GPL) as opposed to the existing drx397xd driver, which
- was written via reverse engineering.
-
-config DVB_L64781
- tristate "LSI L64781"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
-config DVB_TDA1004X
- tristate "Philips TDA10045H/TDA10046H based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
- This driver needs external firmware. Please use the commands
- "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
- "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
- download/extract them, and then copy them to /usr/lib/hotplug/firmware
- or /lib/firmware (depending on configuration of firmware hotplug).
-
-config DVB_NXT6000
- tristate "NxtWave Communications NXT6000 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
-config DVB_MT352
- tristate "Zarlink MT352 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
-config DVB_ZL10353
- tristate "Zarlink ZL10353 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
-config DVB_DIB3000MB
- tristate "DiBcom 3000M-B"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Designed for mobile usage. Say Y when you want
- to support this frontend.
-
-config DVB_DIB3000MC
- tristate "DiBcom 3000P/M-C"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Designed for mobile usage. Say Y when you want
- to support this frontend.
-
-config DVB_DIB7000M
- tristate "DiBcom 7000MA/MB/PA/PB/MC"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Designed for mobile usage. Say Y when you want
- to support this frontend.
-
-config DVB_DIB7000P
- tristate "DiBcom 7000PC"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Designed for mobile usage. Say Y when you want
- to support this frontend.
-
-config DVB_DIB9000
- tristate "DiBcom 9000"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Designed for mobile usage. Say Y when you want
- to support this frontend.
-
-config DVB_TDA10048
- tristate "Philips TDA10048HN based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module. Say Y when you want to support this frontend.
-
-config DVB_AF9013
- tristate "Afatech AF9013 demodulator"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- Say Y when you want to support this frontend.
-
-config DVB_EC100
- tristate "E3C EC100"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- Say Y when you want to support this frontend.
-
-config DVB_HD29L2
- tristate "HDIC HD29L2"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- Say Y when you want to support this frontend.
-
-config DVB_STV0367
- tristate "ST STV0367 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T/C tuner module. Say Y when you want to support this frontend.
-
-config DVB_CXD2820R
- tristate "Sony CXD2820R"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- Say Y when you want to support this frontend.
-
-config DVB_RTL2830
- tristate "Realtek RTL2830 DVB-T"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- Say Y when you want to support this frontend.
-
-config DVB_RTL2832
- tristate "Realtek RTL2832 DVB-T"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- Say Y when you want to support this frontend.
-
-comment "DVB-C (cable) frontends"
- depends on DVB_CORE
-
-config DVB_VES1820
- tristate "VLSI VES1820 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-C tuner module. Say Y when you want to support this frontend.
-
-config DVB_TDA10021
- tristate "Philips TDA10021 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-C tuner module. Say Y when you want to support this frontend.
-
-config DVB_TDA10023
- tristate "Philips TDA10023 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-C tuner module. Say Y when you want to support this frontend.
-
-config DVB_STV0297
- tristate "ST STV0297 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-C tuner module. Say Y when you want to support this frontend.
-
-comment "ATSC (North American/Korean Terrestrial/Cable DTV) frontends"
- depends on DVB_CORE
-
-config DVB_NXT200X
- tristate "NxtWave Communications NXT2002/NXT2004 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
- to support this frontend.
-
- This driver needs external firmware. Please use the commands
- "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2002" and
- "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2004" to
- download/extract them, and then copy them to /usr/lib/hotplug/firmware
- or /lib/firmware (depending on configuration of firmware hotplug).
-
-config DVB_OR51211
- tristate "Oren OR51211 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB tuner module. Say Y when you want to support this frontend.
-
- This driver needs external firmware. Please use the command
- "<kerneldir>/Documentation/dvb/get_dvb_firmware or51211" to
- download it, and then copy it to /usr/lib/hotplug/firmware
- or /lib/firmware (depending on configuration of firmware hotplug).
-
-config DVB_OR51132
- tristate "Oren OR51132 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
- to support this frontend.
-
- This driver needs external firmware. Please use the commands
- "<kerneldir>/Documentation/dvb/get_dvb_firmware or51132_vsb" and/or
- "<kerneldir>/Documentation/dvb/get_dvb_firmware or51132_qam" to
- download firmwares for 8VSB and QAM64/256, respectively. Copy them to
- /usr/lib/hotplug/firmware or /lib/firmware (depending on
- configuration of firmware hotplug).
-
-config DVB_BCM3510
- tristate "Broadcom BCM3510"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB/16VSB and QAM64/256 tuner module. Say Y when you want to
- support this frontend.
-
-config DVB_LGDT330X
- tristate "LG Electronics LGDT3302/LGDT3303 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
- to support this frontend.
-
-config DVB_LGDT3305
- tristate "LG Electronics LGDT3304 and LGDT3305 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
- to support this frontend.
-
-config DVB_LG2160
- tristate "LG Electronics LG216x based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC/MH demodulator module. Say Y when you want
- to support this frontend.
-
-config DVB_S5H1409
- tristate "Samsung S5H1409 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
- to support this frontend.
-
-config DVB_AU8522
- depends on I2C
- tristate
-
-config DVB_AU8522_DTV
- tristate "Auvitek AU8522 based DTV demod"
- depends on DVB_CORE && I2C
- select DVB_AU8522
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB, QAM64/256 & NTSC demodulator module. Say Y when
- you want to enable DTV demodulation support for this frontend.
-
-config DVB_AU8522_V4L
- tristate "Auvitek AU8522 based ATV demod"
- depends on VIDEO_V4L2 && I2C
- select DVB_AU8522
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB, QAM64/256 & NTSC demodulator module. Say Y when
- you want to enable ATV demodulation support for this frontend.
-
-config DVB_S5H1411
- tristate "Samsung S5H1411 based"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
- to support this frontend.
-
-comment "ISDB-T (terrestrial) frontends"
- depends on DVB_CORE
-
-config DVB_S921
- tristate "Sharp S921 frontend"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- AN ISDB-T DQPSK, QPSK, 16QAM and 64QAM 1seg tuner module.
- Say Y when you want to support this frontend.
-
-config DVB_DIB8000
- tristate "DiBcom 8000MB/MC"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A driver for DiBcom's DiB8000 ISDB-T/ISDB-Tsb demodulator.
- Say Y when you want to support this frontend.
-
-config DVB_MB86A20S
- tristate "Fujitsu mb86a20s"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A driver for Fujitsu mb86a20s ISDB-T/ISDB-Tsb demodulator.
- Say Y when you want to support this frontend.
-
-comment "Digital terrestrial only tuners/PLL"
- depends on DVB_CORE
-
-config DVB_PLL
- tristate "Generic I2C PLL based tuners"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- This module drives a number of tuners based on PLL chips with a
- common I2C interface. Say Y when you want to support these tuners.
-
-config DVB_TUNER_DIB0070
- tristate "DiBcom DiB0070 silicon base-band tuner"
- depends on I2C
- default m if DVB_FE_CUSTOMISE
- help
- A driver for the silicon baseband tuner DiB0070 from DiBcom.
- This device is only used inside a SiP called together with a
- demodulator for now.
-
-config DVB_TUNER_DIB0090
- tristate "DiBcom DiB0090 silicon base-band tuner"
- depends on I2C
- default m if DVB_FE_CUSTOMISE
- help
- A driver for the silicon baseband tuner DiB0090 from DiBcom.
- This device is only used inside a SiP called together with a
- demodulator for now.
-
-comment "SEC control devices for DVB-S"
- depends on DVB_CORE
-
-config DVB_LNBP21
- tristate "LNBP21/LNBH24 SEC controllers"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An SEC control chips.
-
-config DVB_LNBP22
- tristate "LNBP22 SEC controllers"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- LNB power supply and control voltage
- regulator chip with step-up converter
- and I2C interface.
- Say Y when you want to support this chip.
-
-config DVB_ISL6405
- tristate "ISL6405 SEC controller"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An SEC control chip.
-
-config DVB_ISL6421
- tristate "ISL6421 SEC controller"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- An SEC control chip.
-
-config DVB_ISL6423
- tristate "ISL6423 SEC controller"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A SEC controller chip from Intersil
-
-config DVB_A8293
- tristate "Allegro A8293"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
-
-config DVB_LGS8GL5
- tristate "Silicon Legend LGS-8GL5 demodulator (OFDM)"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DMB-TH tuner module. Say Y when you want to support this frontend.
-
-config DVB_LGS8GXX
- tristate "Legend Silicon LGS8913/LGS8GL5/LGS8GXX DMB-TH demodulator"
- depends on DVB_CORE && I2C
- select FW_LOADER
- default m if DVB_FE_CUSTOMISE
- help
- A DMB-TH tuner module. Say Y when you want to support this frontend.
-
-config DVB_ATBM8830
- tristate "AltoBeam ATBM8830/8831 DMB-TH demodulator"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DMB-TH tuner module. Say Y when you want to support this frontend.
-
-config DVB_TDA665x
- tristate "TDA665x tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- Support for tuner modules based on Philips TDA6650/TDA6651 chips.
- Say Y when you want to support this chip.
-
- Currently supported tuners:
- * Panasonic ENV57H12D5 (ET-50DT)
-
-config DVB_IX2505V
- tristate "Sharp IX2505V silicon tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module. Say Y when you want to support this frontend.
-
-config DVB_IT913X_FE
- tristate "it913x frontend and it9137 tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-T tuner module.
- Say Y when you want to support this frontend.
-
-config DVB_M88RS2000
- tristate "M88RS2000 DVB-S demodulator and tuner"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
- help
- A DVB-S tuner module.
- Say Y when you want to support this frontend.
-
-config DVB_AF9033
- tristate "Afatech AF9033 DVB-T demodulator"
- depends on DVB_CORE && I2C
- default m if DVB_FE_CUSTOMISE
-
-comment "Tools to develop new frontends"
-
-config DVB_DUMMY_FE
- tristate "Dummy frontend driver"
- default n
-endmenu
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
deleted file mode 100644
index a378c529376..00000000000
--- a/drivers/media/dvb/frontends/Makefile
+++ /dev/null
@@ -1,105 +0,0 @@
-#
-# Makefile for the kernel DVB frontend device drivers.
-#
-
-ccflags-y += -I$(srctree)/drivers/media/dvb-core/
-ccflags-y += -I$(srctree)/drivers/media/common/tuners/
-
-stb0899-objs = stb0899_drv.o stb0899_algo.o
-stv0900-objs = stv0900_core.o stv0900_sw.o
-drxd-objs = drxd_firm.o drxd_hard.o
-cxd2820r-objs = cxd2820r_core.o cxd2820r_c.o cxd2820r_t.o cxd2820r_t2.o
-drxk-objs := drxk_hard.o
-
-obj-$(CONFIG_DVB_PLL) += dvb-pll.o
-obj-$(CONFIG_DVB_STV0299) += stv0299.o
-obj-$(CONFIG_DVB_STB0899) += stb0899.o
-obj-$(CONFIG_DVB_STB6100) += stb6100.o
-obj-$(CONFIG_DVB_SP8870) += sp8870.o
-obj-$(CONFIG_DVB_CX22700) += cx22700.o
-obj-$(CONFIG_DVB_S5H1432) += s5h1432.o
-obj-$(CONFIG_DVB_CX24110) += cx24110.o
-obj-$(CONFIG_DVB_TDA8083) += tda8083.o
-obj-$(CONFIG_DVB_L64781) += l64781.o
-obj-$(CONFIG_DVB_DIB3000MB) += dib3000mb.o
-obj-$(CONFIG_DVB_DIB3000MC) += dib3000mc.o dibx000_common.o
-obj-$(CONFIG_DVB_DIB7000M) += dib7000m.o dibx000_common.o
-obj-$(CONFIG_DVB_DIB7000P) += dib7000p.o dibx000_common.o
-obj-$(CONFIG_DVB_DIB8000) += dib8000.o dibx000_common.o
-obj-$(CONFIG_DVB_DIB9000) += dib9000.o dibx000_common.o
-obj-$(CONFIG_DVB_MT312) += mt312.o
-obj-$(CONFIG_DVB_VES1820) += ves1820.o
-obj-$(CONFIG_DVB_VES1X93) += ves1x93.o
-obj-$(CONFIG_DVB_TDA1004X) += tda1004x.o
-obj-$(CONFIG_DVB_SP887X) += sp887x.o
-obj-$(CONFIG_DVB_NXT6000) += nxt6000.o
-obj-$(CONFIG_DVB_MT352) += mt352.o
-obj-$(CONFIG_DVB_ZL10036) += zl10036.o
-obj-$(CONFIG_DVB_ZL10039) += zl10039.o
-obj-$(CONFIG_DVB_ZL10353) += zl10353.o
-obj-$(CONFIG_DVB_CX22702) += cx22702.o
-obj-$(CONFIG_DVB_DRXD) += drxd.o
-obj-$(CONFIG_DVB_TDA10021) += tda10021.o
-obj-$(CONFIG_DVB_TDA10023) += tda10023.o
-obj-$(CONFIG_DVB_STV0297) += stv0297.o
-obj-$(CONFIG_DVB_NXT200X) += nxt200x.o
-obj-$(CONFIG_DVB_OR51211) += or51211.o
-obj-$(CONFIG_DVB_OR51132) += or51132.o
-obj-$(CONFIG_DVB_BCM3510) += bcm3510.o
-obj-$(CONFIG_DVB_S5H1420) += s5h1420.o
-obj-$(CONFIG_DVB_LGDT330X) += lgdt330x.o
-obj-$(CONFIG_DVB_LGDT3305) += lgdt3305.o
-obj-$(CONFIG_DVB_LG2160) += lg2160.o
-obj-$(CONFIG_DVB_CX24123) += cx24123.o
-obj-$(CONFIG_DVB_LNBP21) += lnbp21.o
-obj-$(CONFIG_DVB_LNBP22) += lnbp22.o
-obj-$(CONFIG_DVB_ISL6405) += isl6405.o
-obj-$(CONFIG_DVB_ISL6421) += isl6421.o
-obj-$(CONFIG_DVB_TDA10086) += tda10086.o
-obj-$(CONFIG_DVB_TDA826X) += tda826x.o
-obj-$(CONFIG_DVB_TDA8261) += tda8261.o
-obj-$(CONFIG_DVB_TUNER_DIB0070) += dib0070.o
-obj-$(CONFIG_DVB_TUNER_DIB0090) += dib0090.o
-obj-$(CONFIG_DVB_TUA6100) += tua6100.o
-obj-$(CONFIG_DVB_S5H1409) += s5h1409.o
-obj-$(CONFIG_DVB_TUNER_ITD1000) += itd1000.o
-obj-$(CONFIG_DVB_AU8522) += au8522_common.o
-obj-$(CONFIG_DVB_AU8522_DTV) += au8522_dig.o
-obj-$(CONFIG_DVB_AU8522_V4L) += au8522_decoder.o
-obj-$(CONFIG_DVB_TDA10048) += tda10048.o
-obj-$(CONFIG_DVB_TUNER_CX24113) += cx24113.o
-obj-$(CONFIG_DVB_S5H1411) += s5h1411.o
-obj-$(CONFIG_DVB_LGS8GL5) += lgs8gl5.o
-obj-$(CONFIG_DVB_TDA665x) += tda665x.o
-obj-$(CONFIG_DVB_LGS8GXX) += lgs8gxx.o
-obj-$(CONFIG_DVB_ATBM8830) += atbm8830.o
-obj-$(CONFIG_DVB_DUMMY_FE) += dvb_dummy_fe.o
-obj-$(CONFIG_DVB_AF9013) += af9013.o
-obj-$(CONFIG_DVB_CX24116) += cx24116.o
-obj-$(CONFIG_DVB_SI21XX) += si21xx.o
-obj-$(CONFIG_DVB_STV0288) += stv0288.o
-obj-$(CONFIG_DVB_STB6000) += stb6000.o
-obj-$(CONFIG_DVB_S921) += s921.o
-obj-$(CONFIG_DVB_STV6110) += stv6110.o
-obj-$(CONFIG_DVB_STV0900) += stv0900.o
-obj-$(CONFIG_DVB_STV090x) += stv090x.o
-obj-$(CONFIG_DVB_STV6110x) += stv6110x.o
-obj-$(CONFIG_DVB_ISL6423) += isl6423.o
-obj-$(CONFIG_DVB_EC100) += ec100.o
-obj-$(CONFIG_DVB_HD29L2) += hd29l2.o
-obj-$(CONFIG_DVB_DS3000) += ds3000.o
-obj-$(CONFIG_DVB_MB86A16) += mb86a16.o
-obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o
-obj-$(CONFIG_DVB_IX2505V) += ix2505v.o
-obj-$(CONFIG_DVB_STV0367) += stv0367.o
-obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o
-obj-$(CONFIG_DVB_DRXK) += drxk.o
-obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o
-obj-$(CONFIG_DVB_IT913X_FE) += it913x-fe.o
-obj-$(CONFIG_DVB_A8293) += a8293.o
-obj-$(CONFIG_DVB_TDA10071) += tda10071.o
-obj-$(CONFIG_DVB_RTL2830) += rtl2830.o
-obj-$(CONFIG_DVB_RTL2832) += rtl2832.o
-obj-$(CONFIG_DVB_M88RS2000) += m88rs2000.o
-obj-$(CONFIG_DVB_AF9033) += af9033.o
-
diff --git a/drivers/media/dvb/frontends/a8293.c b/drivers/media/dvb/frontends/a8293.c
deleted file mode 100644
index cff44a389b4..00000000000
--- a/drivers/media/dvb/frontends/a8293.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Allegro A8293 SEC driver
- *
- * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include "dvb_frontend.h"
-#include "a8293.h"
-
-struct a8293_priv {
- struct i2c_adapter *i2c;
- const struct a8293_config *cfg;
- u8 reg[2];
-};
-
-static int a8293_i2c(struct a8293_priv *priv, u8 *val, int len, bool rd)
-{
- int ret;
- struct i2c_msg msg[1] = {
- {
- .addr = priv->cfg->i2c_addr,
- .len = len,
- .buf = val,
- }
- };
-
- if (rd)
- msg[0].flags = I2C_M_RD;
- else
- msg[0].flags = 0;
-
- ret = i2c_transfer(priv->i2c, msg, 1);
- if (ret == 1) {
- ret = 0;
- } else {
- dev_warn(&priv->i2c->dev, "%s: i2c failed=%d rd=%d\n",
- KBUILD_MODNAME, ret, rd);
- ret = -EREMOTEIO;
- }
-
- return ret;
-}
-
-static int a8293_wr(struct a8293_priv *priv, u8 *val, int len)
-{
- return a8293_i2c(priv, val, len, 0);
-}
-
-static int a8293_rd(struct a8293_priv *priv, u8 *val, int len)
-{
- return a8293_i2c(priv, val, len, 1);
-}
-
-static int a8293_set_voltage(struct dvb_frontend *fe,
- fe_sec_voltage_t fe_sec_voltage)
-{
- struct a8293_priv *priv = fe->sec_priv;
- int ret;
-
- dev_dbg(&priv->i2c->dev, "%s: fe_sec_voltage=%d\n", __func__,
- fe_sec_voltage);
-
- switch (fe_sec_voltage) {
- case SEC_VOLTAGE_OFF:
- /* ENB=0 */
- priv->reg[0] = 0x10;
- break;
- case SEC_VOLTAGE_13:
- /* VSEL0=1, VSEL1=0, VSEL2=0, VSEL3=0, ENB=1*/
- priv->reg[0] = 0x31;
- break;
- case SEC_VOLTAGE_18:
- /* VSEL0=0, VSEL1=0, VSEL2=0, VSEL3=1, ENB=1*/
- priv->reg[0] = 0x38;
- break;
- default:
- ret = -EINVAL;
- goto err;
- };
-
- ret = a8293_wr(priv, &priv->reg[0], 1);
- if (ret)
- goto err;
-
- return ret;
-err:
- dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
- return ret;
-}
-
-static void a8293_release_sec(struct dvb_frontend *fe)
-{
- a8293_set_voltage(fe, SEC_VOLTAGE_OFF);
-
- kfree(fe->sec_priv);
- fe->sec_priv = NULL;
-}
-
-struct dvb_frontend *a8293_attach(struct dvb_frontend *fe,
- struct i2c_adapter *i2c, const struct a8293_config *cfg)
-{
- int ret;
- struct a8293_priv *priv = NULL;
- u8 buf[2];
-
- /* allocate memory for the internal priv */
- priv = kzalloc(sizeof(struct a8293_priv), GFP_KERNEL);
- if (priv == NULL) {
- ret = -ENOMEM;
- goto err;
- }
-
- /* setup the priv */
- priv->i2c = i2c;
- priv->cfg = cfg;
- fe->sec_priv = priv;
-
- /* check if the SEC is there */
- ret = a8293_rd(priv, buf, 2);
- if (ret)
- goto err;
-
- /* ENB=0 */
- priv->reg[0] = 0x10;
- ret = a8293_wr(priv, &priv->reg[0], 1);
- if (ret)
- goto err;
-
- /* TMODE=0, TGATE=1 */
- priv->reg[1] = 0x82;
- ret = a8293_wr(priv, &priv->reg[1], 1);
- if (ret)
- goto err;
-
- fe->ops.release_sec = a8293_release_sec;
-
- /* override frontend ops */
- fe->ops.set_voltage = a8293_set_voltage;
-
- dev_info(&priv->i2c->dev, "%s: Allegro A8293 SEC attached\n",
- KBUILD_MODNAME);
-
- return fe;
-err:
- dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
- kfree(priv);
- return NULL;
-}
-EXPORT_SYMBOL(a8293_attach);
-
-MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
-MODULE_DESCRIPTION("Allegro A8293 SEC driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/a8293.h b/drivers/media/dvb/frontends/a8293.h
deleted file mode 100644
index ed29e5504f7..00000000000
--- a/drivers/media/dvb/frontends/a8293.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Allegro A8293 SEC driver
- *
- * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef A8293_H
-#define A8293_H
-
-struct a8293_config {
- u8 i2c_addr;
-};
-
-#if defined(CONFIG_DVB_A8293) || \
- (defined(CONFIG_DVB_A8293_MODULE) && defined(MODULE))
-extern struct dvb_frontend *a8293_attach(struct dvb_frontend *fe,
- struct i2c_adapter *i2c, const struct a8293_config *cfg);
-#else
-static inline struct dvb_frontend *a8293_attach(struct dvb_frontend *fe,
- struct i2c_adapter *i2c, const struct a8293_config *cfg)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif /* A8293_H */
diff --git a/drivers/media/dvb/frontends/af9013.c b/drivers/media/dvb/frontends/af9013.c
deleted file mode 100644
index 5bc570d7784..00000000000
--- a/drivers/media/dvb/frontends/af9013.c
+++ /dev/null
@@ -1,1524 +0,0 @@
-/*
- * Afatech AF9013 demodulator driver
- *
- * Copyright (C) 2007 Antti Palosaari <crope@iki.fi>
- * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
- *
- * Thanks to Afatech who kindly provided information.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include "af9013_priv.h"
-
-int af9013_debug;
-module_param_named(debug, af9013_debug, int, 0644);
-MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-
-struct af9013_state {
- struct i2c_adapter *i2c;
- struct dvb_frontend fe;
- struct af9013_config config;
-
- /* tuner/demod RF and IF AGC limits used for signal strength calc */
- u8 signal_strength_en, rf_50, rf_80, if_50, if_80;
- u16 signal_strength;
- u32 ber;
- u32 ucblocks;
- u16 snr;
- u32 bandwidth_hz;
- fe_status_t fe_status;
- unsigned long set_frontend_jiffies;
- unsigned long read_status_jiffies;
- bool first_tune;
- bool i2c_gate_state;
- unsigned int statistics_step:3;
- struct delayed_work statistics_work;
-};
-
-/* write multiple registers */
-static int af9013_wr_regs_i2c(struct af9013_state *priv, u8 mbox, u16 reg,
- const u8 *val, int len)
-{
- int ret;
- u8 buf[3+len];
- struct i2c_msg msg[1] = {
- {
- .addr = priv->config.i2c_addr,
- .flags = 0,
- .len = sizeof(buf),
- .buf = buf,
- }
- };
-
- buf[0] = (reg >> 8) & 0xff;
- buf[1] = (reg >> 0) & 0xff;
- buf[2] = mbox;
- memcpy(&buf[3], val, len);
-
- ret = i2c_transfer(priv->i2c, msg, 1);
- if (ret == 1) {
- ret = 0;
- } else {
- warn("i2c wr failed=%d reg=%04x len=%d", ret, reg, len);
- ret = -EREMOTEIO;
- }
- return ret;
-}
-
-/* read multiple registers */
-static int af9013_rd_regs_i2c(struct af9013_state *priv, u8 mbox, u16 reg,
- u8 *val, int len)
-{
- int ret;
- u8 buf[3];
- struct i2c_msg msg[2] = {
- {
- .addr = priv->config.i2c_addr,
- .flags = 0,
- .len = 3,
- .buf = buf,
- }, {
- .addr = priv->config.i2c_addr,
- .flags = I2C_M_RD,
- .len = len,
- .buf = val,
- }
- };
-
- buf[0] = (reg >> 8) & 0xff;
- buf[1] = (reg >> 0) & 0xff;
- buf[2] = mbox;
-
- ret = i2c_transfer(priv->i2c, msg, 2);
- if (ret == 2) {
- ret = 0;
- } else {
- warn("i2c rd failed=%d reg=%04x len=%d", ret, reg, len);
- ret = -EREMOTEIO;
- }
- return ret;
-}
-
-/* write multiple registers */
-static int af9013_wr_regs(struct af9013_state *priv, u16 reg, const u8 *val,
- int len)
-{
- int ret, i;
- u8 mbox = (0 << 7)|(0 << 6)|(1 << 1)|(1 << 0);
-
- if ((priv->config.ts_mode == AF9013_TS_USB) &&
- ((reg & 0xff00) != 0xff00) && ((reg & 0xff00) != 0xae00)) {
- mbox |= ((len - 1) << 2);
- ret = af9013_wr_regs_i2c(priv, mbox, reg, val, len);
- } else {
- for (i = 0; i < len; i++) {
- ret = af9013_wr_regs_i2c(priv, mbox, reg+i, val+i, 1);
- if (ret)
- goto err;
- }
- }
-
-err:
- return 0;
-}
-
-/* read multiple registers */
-static int af9013_rd_regs(struct af9013_state *priv, u16 reg, u8 *val, int len)
-{
- int ret, i;
- u8 mbox = (0 << 7)|(0 << 6)|(1 << 1)|(0 << 0);
-
- if ((priv->config.ts_mode == AF9013_TS_USB) &&
- ((reg & 0xff00) != 0xff00) && ((reg & 0xff00) != 0xae00)) {
- mbox |= ((len - 1) << 2);
- ret = af9013_rd_regs_i2c(priv, mbox, reg, val, len);
- } else {
- for (i = 0; i < len; i++) {
- ret = af9013_rd_regs_i2c(priv, mbox, reg+i, val+i, 1);
- if (ret)
- goto err;
- }
- }
-
-err:
- return 0;
-}
-
-/* write single register */
-static int af9013_wr_reg(struct af9013_state *priv, u16 reg, u8 val)
-{
- return af9013_wr_regs(priv, reg, &val, 1);
-}
-
-/* read single register */
-static int af9013_rd_reg(struct af9013_state *priv, u16 reg, u8 *val)
-{
- return af9013_rd_regs(priv, reg, val, 1);
-}
-
-static int af9013_write_ofsm_regs(struct af9013_state *state, u16 reg, u8 *val,
- u8 len)
-{
- u8 mbox = (1 << 7)|(1 << 6)|((len - 1) << 2)|(1 << 1)|(1 << 0);
- return af9013_wr_regs_i2c(state, mbox, reg, val, len);
-}
-
-static int af9013_wr_reg_bits(struct af9013_state *state, u16 reg, int pos,
- int len, u8 val)
-{
- int ret;
- u8 tmp, mask;
-
- /* no need for read if whole reg is written */
- if (len != 8) {
- ret = af9013_rd_reg(state, reg, &tmp);
- if (ret)
- return ret;
-
- mask = (0xff >> (8 - len)) << pos;
- val <<= pos;
- tmp &= ~mask;
- val |= tmp;
- }
-
- return af9013_wr_reg(state, reg, val);
-}
-
-static int af9013_rd_reg_bits(struct af9013_state *state, u16 reg, int pos,
- int len, u8 *val)
-{
- int ret;
- u8 tmp;
-
- ret = af9013_rd_reg(state, reg, &tmp);
- if (ret)
- return ret;
-
- *val = (tmp >> pos);
- *val &= (0xff >> (8 - len));
-
- return 0;
-}
-
-static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval)
-{
- int ret;
- u8 pos;
- u16 addr;
-
- dbg("%s: gpio=%d gpioval=%02x", __func__, gpio, gpioval);
-
- /*
- * GPIO0 & GPIO1 0xd735
- * GPIO2 & GPIO3 0xd736
- */
-
- switch (gpio) {
- case 0:
- case 1:
- addr = 0xd735;
- break;
- case 2:
- case 3:
- addr = 0xd736;
- break;
-
- default:
- err("invalid gpio:%d\n", gpio);
- ret = -EINVAL;
- goto err;
- };
-
- switch (gpio) {
- case 0:
- case 2:
- pos = 0;
- break;
- case 1:
- case 3:
- default:
- pos = 4;
- break;
- };
-
- ret = af9013_wr_reg_bits(state, addr, pos, 4, gpioval);
- if (ret)
- goto err;
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static u32 af913_div(u32 a, u32 b, u32 x)
-{
- u32 r = 0, c = 0, i;
-
- dbg("%s: a=%d b=%d x=%d", __func__, a, b, x);
-
- if (a > b) {
- c = a / b;
- a = a - c * b;
- }
-
- for (i = 0; i < x; i++) {
- if (a >= b) {
- r += 1;
- a -= b;
- }
- a <<= 1;
- r <<= 1;
- }
- r = (c << (u32)x) + r;
-
- dbg("%s: a=%d b=%d x=%d r=%x", __func__, a, b, x, r);
- return r;
-}
-
-static int af9013_power_ctrl(struct af9013_state *state, u8 onoff)
-{
- int ret, i;
- u8 tmp;
-
- dbg("%s: onoff=%d", __func__, onoff);
-
- /* enable reset */
- ret = af9013_wr_reg_bits(state, 0xd417, 4, 1, 1);
- if (ret)
- goto err;
-
- /* start reset mechanism */
- ret = af9013_wr_reg(state, 0xaeff, 1);
- if (ret)
- goto err;
-
- /* wait reset performs */
- for (i = 0; i < 150; i++) {
- ret = af9013_rd_reg_bits(state, 0xd417, 1, 1, &tmp);
- if (ret)
- goto err;
-
- if (tmp)
- break; /* reset done */
-
- usleep_range(5000, 25000);
- }
-
- if (!tmp)
- return -ETIMEDOUT;
-
- if (onoff) {
- /* clear reset */
- ret = af9013_wr_reg_bits(state, 0xd417, 1, 1, 0);
- if (ret)
- goto err;
-
- /* disable reset */
- ret = af9013_wr_reg_bits(state, 0xd417, 4, 1, 0);
-
- /* power on */
- ret = af9013_wr_reg_bits(state, 0xd73a, 3, 1, 0);
- } else {
- /* power off */
- ret = af9013_wr_reg_bits(state, 0xd73a, 3, 1, 1);
- }
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_statistics_ber_unc_start(struct dvb_frontend *fe)
-{
- struct af9013_state *state = fe->demodulator_priv;
- int ret;
-
- dbg("%s", __func__);
-
- /* reset and start BER counter */
- ret = af9013_wr_reg_bits(state, 0xd391, 4, 1, 1);
- if (ret)
- goto err;
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_statistics_ber_unc_result(struct dvb_frontend *fe)
-{
- struct af9013_state *state = fe->demodulator_priv;
- int ret;
- u8 buf[5];
-
- dbg("%s", __func__);
-
- /* check if error bit count is ready */
- ret = af9013_rd_reg_bits(state, 0xd391, 4, 1, &buf[0]);
- if (ret)
- goto err;
-
- if (!buf[0]) {
- dbg("%s: not ready", __func__);
- return 0;
- }
-
- ret = af9013_rd_regs(state, 0xd387, buf, 5);
- if (ret)
- goto err;
-
- state->ber = (buf[2] << 16) | (buf[1] << 8) | buf[0];
- state->ucblocks += (buf[4] << 8) | buf[3];
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_statistics_snr_start(struct dvb_frontend *fe)
-{
- struct af9013_state *state = fe->demodulator_priv;
- int ret;
-
- dbg("%s", __func__);
-
- /* start SNR meas */
- ret = af9013_wr_reg_bits(state, 0xd2e1, 3, 1, 1);
- if (ret)
- goto err;
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_statistics_snr_result(struct dvb_frontend *fe)
-{
- struct af9013_state *state = fe->demodulator_priv;
- int ret, i, len;
- u8 buf[3], tmp;
- u32 snr_val;
- const struct af9013_snr *uninitialized_var(snr_lut);
-
- dbg("%s", __func__);
-
- /* check if SNR ready */
- ret = af9013_rd_reg_bits(state, 0xd2e1, 3, 1, &tmp);
- if (ret)
- goto err;
-
- if (!tmp) {
- dbg("%s: not ready", __func__);
- return 0;
- }
-
- /* read value */
- ret = af9013_rd_regs(state, 0xd2e3, buf, 3);
- if (ret)
- goto err;
-
- snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0];
-
- /* read current modulation */
- ret = af9013_rd_reg(state, 0xd3c1, &tmp);
- if (ret)
- goto err;
-
- switch ((tmp >> 6) & 3) {
- case 0:
- len = ARRAY_SIZE(qpsk_snr_lut);
- snr_lut = qpsk_snr_lut;
- break;
- case 1:
- len = ARRAY_SIZE(qam16_snr_lut);
- snr_lut = qam16_snr_lut;
- break;
- case 2:
- len = ARRAY_SIZE(qam64_snr_lut);
- snr_lut = qam64_snr_lut;
- break;
- default:
- goto err;
- break;
- }
-
- for (i = 0; i < len; i++) {
- tmp = snr_lut[i].snr;
-
- if (snr_val < snr_lut[i].val)
- break;
- }
- state->snr = tmp * 10; /* dB/10 */
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_statistics_signal_strength(struct dvb_frontend *fe)
-{
- struct af9013_state *state = fe->demodulator_priv;
- int ret = 0;
- u8 buf[2], rf_gain, if_gain;
- int signal_strength;
-
- dbg("%s", __func__);
-
- if (!state->signal_strength_en)
- return 0;
-
- ret = af9013_rd_regs(state, 0xd07c, buf, 2);
- if (ret)
- goto err;
-
- rf_gain = buf[0];
- if_gain = buf[1];
-
- signal_strength = (0xffff / \
- (9 * (state->rf_50 + state->if_50) - \
- 11 * (state->rf_80 + state->if_80))) * \
- (10 * (rf_gain + if_gain) - \
- 11 * (state->rf_80 + state->if_80));
- if (signal_strength < 0)
- signal_strength = 0;
- else if (signal_strength > 0xffff)
- signal_strength = 0xffff;
-
- state->signal_strength = signal_strength;
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static void af9013_statistics_work(struct work_struct *work)
-{
- struct af9013_state *state = container_of(work,
- struct af9013_state, statistics_work.work);
- unsigned int next_msec;
-
- /* update only signal strength when demod is not locked */
- if (!(state->fe_status & FE_HAS_LOCK)) {
- state->statistics_step = 0;
- state->ber = 0;
- state->snr = 0;
- }
-
- switch (state->statistics_step) {
- default:
- state->statistics_step = 0;
- case 0:
- af9013_statistics_signal_strength(&state->fe);
- state->statistics_step++;
- next_msec = 300;
- break;
- case 1:
- af9013_statistics_snr_start(&state->fe);
- state->statistics_step++;
- next_msec = 200;
- break;
- case 2:
- af9013_statistics_ber_unc_start(&state->fe);
- state->statistics_step++;
- next_msec = 1000;
- break;
- case 3:
- af9013_statistics_snr_result(&state->fe);
- state->statistics_step++;
- next_msec = 400;
- break;
- case 4:
- af9013_statistics_ber_unc_result(&state->fe);
- state->statistics_step++;
- next_msec = 100;
- break;
- }
-
- schedule_delayed_work(&state->statistics_work,
- msecs_to_jiffies(next_msec));
-}
-
-static int af9013_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *fesettings)
-{
- fesettings->min_delay_ms = 800;
- fesettings->step_size = 0;
- fesettings->max_drift = 0;
-
- return 0;
-}
-
-static int af9013_set_frontend(struct dvb_frontend *fe)
-{
- struct af9013_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret, i, sampling_freq;
- bool auto_mode, spec_inv;
- u8 buf[6];
- u32 if_frequency, freq_cw;
-
- dbg("%s: frequency=%d bandwidth_hz=%d", __func__,
- c->frequency, c->bandwidth_hz);
-
- /* program tuner */
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
-
- /* program CFOE coefficients */
- if (c->bandwidth_hz != state->bandwidth_hz) {
- for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
- if (coeff_lut[i].clock == state->config.clock &&
- coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
- break;
- }
- }
-
- ret = af9013_wr_regs(state, 0xae00, coeff_lut[i].val,
- sizeof(coeff_lut[i].val));
- }
-
- /* program frequency control */
- if (c->bandwidth_hz != state->bandwidth_hz || state->first_tune) {
- /* get used IF frequency */
- if (fe->ops.tuner_ops.get_if_frequency)
- fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
- else
- if_frequency = state->config.if_frequency;
-
- sampling_freq = if_frequency;
-
- while (sampling_freq > (state->config.clock / 2))
- sampling_freq -= state->config.clock;
-
- if (sampling_freq < 0) {
- sampling_freq *= -1;
- spec_inv = state->config.spec_inv;
- } else {
- spec_inv = !state->config.spec_inv;
- }
-
- freq_cw = af913_div(sampling_freq, state->config.clock, 23);
-
- if (spec_inv)
- freq_cw = 0x800000 - freq_cw;
-
- buf[0] = (freq_cw >> 0) & 0xff;
- buf[1] = (freq_cw >> 8) & 0xff;
- buf[2] = (freq_cw >> 16) & 0x7f;
-
- freq_cw = 0x800000 - freq_cw;
-
- buf[3] = (freq_cw >> 0) & 0xff;
- buf[4] = (freq_cw >> 8) & 0xff;
- buf[5] = (freq_cw >> 16) & 0x7f;
-
- ret = af9013_wr_regs(state, 0xd140, buf, 3);
- if (ret)
- goto err;
-
- ret = af9013_wr_regs(state, 0x9be7, buf, 6);
- if (ret)
- goto err;
- }
-
- /* clear TPS lock flag */
- ret = af9013_wr_reg_bits(state, 0xd330, 3, 1, 1);
- if (ret)
- goto err;
-
- /* clear MPEG2 lock flag */
- ret = af9013_wr_reg_bits(state, 0xd507, 6, 1, 0);
- if (ret)
- goto err;
-
- /* empty channel function */
- ret = af9013_wr_reg_bits(state, 0x9bfe, 0, 1, 0);
- if (ret)
- goto err;
-
- /* empty DVB-T channel function */
- ret = af9013_wr_reg_bits(state, 0x9bc2, 0, 1, 0);
- if (ret)
- goto err;
-
- /* transmission parameters */
- auto_mode = false;
- memset(buf, 0, 3);
-
- switch (c->transmission_mode) {
- case TRANSMISSION_MODE_AUTO:
- auto_mode = 1;
- break;
- case TRANSMISSION_MODE_2K:
- break;
- case TRANSMISSION_MODE_8K:
- buf[0] |= (1 << 0);
- break;
- default:
- dbg("%s: invalid transmission_mode", __func__);
- auto_mode = 1;
- }
-
- switch (c->guard_interval) {
- case GUARD_INTERVAL_AUTO:
- auto_mode = 1;
- break;
- case GUARD_INTERVAL_1_32:
- break;
- case GUARD_INTERVAL_1_16:
- buf[0] |= (1 << 2);
- break;
- case GUARD_INTERVAL_1_8:
- buf[0] |= (2 << 2);
- break;
- case GUARD_INTERVAL_1_4:
- buf[0] |= (3 << 2);
- break;
- default:
- dbg("%s: invalid guard_interval", __func__);
- auto_mode = 1;
- }
-
- switch (c->hierarchy) {
- case HIERARCHY_AUTO:
- auto_mode = 1;
- break;
- case HIERARCHY_NONE:
- break;
- case HIERARCHY_1:
- buf[0] |= (1 << 4);
- break;
- case HIERARCHY_2:
- buf[0] |= (2 << 4);
- break;
- case HIERARCHY_4:
- buf[0] |= (3 << 4);
- break;
- default:
- dbg("%s: invalid hierarchy", __func__);
- auto_mode = 1;
- };
-
- switch (c->modulation) {
- case QAM_AUTO:
- auto_mode = 1;
- break;
- case QPSK:
- break;
- case QAM_16:
- buf[1] |= (1 << 6);
- break;
- case QAM_64:
- buf[1] |= (2 << 6);
- break;
- default:
- dbg("%s: invalid modulation", __func__);
- auto_mode = 1;
- }
-
- /* Use HP. How and which case we can switch to LP? */
- buf[1] |= (1 << 4);
-
- switch (c->code_rate_HP) {
- case FEC_AUTO:
- auto_mode = 1;
- break;
- case FEC_1_2:
- break;
- case FEC_2_3:
- buf[2] |= (1 << 0);
- break;
- case FEC_3_4:
- buf[2] |= (2 << 0);
- break;
- case FEC_5_6:
- buf[2] |= (3 << 0);
- break;
- case FEC_7_8:
- buf[2] |= (4 << 0);
- break;
- default:
- dbg("%s: invalid code_rate_HP", __func__);
- auto_mode = 1;
- }
-
- switch (c->code_rate_LP) {
- case FEC_AUTO:
- auto_mode = 1;
- break;
- case FEC_1_2:
- break;
- case FEC_2_3:
- buf[2] |= (1 << 3);
- break;
- case FEC_3_4:
- buf[2] |= (2 << 3);
- break;
- case FEC_5_6:
- buf[2] |= (3 << 3);
- break;
- case FEC_7_8:
- buf[2] |= (4 << 3);
- break;
- case FEC_NONE:
- break;
- default:
- dbg("%s: invalid code_rate_LP", __func__);
- auto_mode = 1;
- }
-
- switch (c->bandwidth_hz) {
- case 6000000:
- break;
- case 7000000:
- buf[1] |= (1 << 2);
- break;
- case 8000000:
- buf[1] |= (2 << 2);
- break;
- default:
- dbg("%s: invalid bandwidth_hz", __func__);
- ret = -EINVAL;
- goto err;
- }
-
- ret = af9013_wr_regs(state, 0xd3c0, buf, 3);
- if (ret)
- goto err;
-
- if (auto_mode) {
- /* clear easy mode flag */
- ret = af9013_wr_reg(state, 0xaefd, 0);
- if (ret)
- goto err;
-
- dbg("%s: auto params", __func__);
- } else {
- /* set easy mode flag */
- ret = af9013_wr_reg(state, 0xaefd, 1);
- if (ret)
- goto err;
-
- ret = af9013_wr_reg(state, 0xaefe, 0);
- if (ret)
- goto err;
-
- dbg("%s: manual params", __func__);
- }
-
- /* tune */
- ret = af9013_wr_reg(state, 0xffff, 0);
- if (ret)
- goto err;
-
- state->bandwidth_hz = c->bandwidth_hz;
- state->set_frontend_jiffies = jiffies;
- state->first_tune = false;
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_get_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct af9013_state *state = fe->demodulator_priv;
- int ret;
- u8 buf[3];
-
- dbg("%s", __func__);
-
- ret = af9013_rd_regs(state, 0xd3c0, buf, 3);
- if (ret)
- goto err;
-
- switch ((buf[1] >> 6) & 3) {
- case 0:
- c->modulation = QPSK;
- break;
- case 1:
- c->modulation = QAM_16;
- break;
- case 2:
- c->modulation = QAM_64;
- break;
- }
-
- switch ((buf[0] >> 0) & 3) {
- case 0:
- c->transmission_mode = TRANSMISSION_MODE_2K;
- break;
- case 1:
- c->transmission_mode = TRANSMISSION_MODE_8K;
- }
-
- switch ((buf[0] >> 2) & 3) {
- case 0:
- c->guard_interval = GUARD_INTERVAL_1_32;
- break;
- case 1:
- c->guard_interval = GUARD_INTERVAL_1_16;
- break;
- case 2:
- c->guard_interval = GUARD_INTERVAL_1_8;
- break;
- case 3:
- c->guard_interval = GUARD_INTERVAL_1_4;
- break;
- }
-
- switch ((buf[0] >> 4) & 7) {
- case 0:
- c->hierarchy = HIERARCHY_NONE;
- break;
- case 1:
- c->hierarchy = HIERARCHY_1;
- break;
- case 2:
- c->hierarchy = HIERARCHY_2;
- break;
- case 3:
- c->hierarchy = HIERARCHY_4;
- break;
- }
-
- switch ((buf[2] >> 0) & 7) {
- case 0:
- c->code_rate_HP = FEC_1_2;
- break;
- case 1:
- c->code_rate_HP = FEC_2_3;
- break;
- case 2:
- c->code_rate_HP = FEC_3_4;
- break;
- case 3:
- c->code_rate_HP = FEC_5_6;
- break;
- case 4:
- c->code_rate_HP = FEC_7_8;
- break;
- }
-
- switch ((buf[2] >> 3) & 7) {
- case 0:
- c->code_rate_LP = FEC_1_2;
- break;
- case 1:
- c->code_rate_LP = FEC_2_3;
- break;
- case 2:
- c->code_rate_LP = FEC_3_4;
- break;
- case 3:
- c->code_rate_LP = FEC_5_6;
- break;
- case 4:
- c->code_rate_LP = FEC_7_8;
- break;
- }
-
- switch ((buf[1] >> 2) & 3) {
- case 0:
- c->bandwidth_hz = 6000000;
- break;
- case 1:
- c->bandwidth_hz = 7000000;
- break;
- case 2:
- c->bandwidth_hz = 8000000;
- break;
- }
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct af9013_state *state = fe->demodulator_priv;
- int ret;
- u8 tmp;
-
- /*
- * Return status from the cache if it is younger than 2000ms with the
- * exception of last tune is done during 4000ms.
- */
- if (time_is_after_jiffies(
- state->read_status_jiffies + msecs_to_jiffies(2000)) &&
- time_is_before_jiffies(
- state->set_frontend_jiffies + msecs_to_jiffies(4000))
- ) {
- *status = state->fe_status;
- return 0;
- } else {
- *status = 0;
- }
-
- /* MPEG2 lock */
- ret = af9013_rd_reg_bits(state, 0xd507, 6, 1, &tmp);
- if (ret)
- goto err;
-
- if (tmp)
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
- FE_HAS_SYNC | FE_HAS_LOCK;
-
- if (!*status) {
- /* TPS lock */
- ret = af9013_rd_reg_bits(state, 0xd330, 3, 1, &tmp);
- if (ret)
- goto err;
-
- if (tmp)
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI;
- }
-
- state->fe_status = *status;
- state->read_status_jiffies = jiffies;
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- struct af9013_state *state = fe->demodulator_priv;
- *snr = state->snr;
- return 0;
-}
-
-static int af9013_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
-{
- struct af9013_state *state = fe->demodulator_priv;
- *strength = state->signal_strength;
- return 0;
-}
-
-static int af9013_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct af9013_state *state = fe->demodulator_priv;
- *ber = state->ber;
- return 0;
-}
-
-static int af9013_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- struct af9013_state *state = fe->demodulator_priv;
- *ucblocks = state->ucblocks;
- return 0;
-}
-
-static int af9013_init(struct dvb_frontend *fe)
-{
- struct af9013_state *state = fe->demodulator_priv;
- int ret, i, len;
- u8 buf[3], tmp;
- u32 adc_cw;
- const struct af9013_reg_bit *init;
-
- dbg("%s", __func__);
-
- /* power on */
- ret = af9013_power_ctrl(state, 1);
- if (ret)
- goto err;
-
- /* enable ADC */
- ret = af9013_wr_reg(state, 0xd73a, 0xa4);
- if (ret)
- goto err;
-
- /* write API version to firmware */
- ret = af9013_wr_regs(state, 0x9bf2, state->config.api_version, 4);
- if (ret)
- goto err;
-
- /* program ADC control */
- switch (state->config.clock) {
- case 28800000: /* 28.800 MHz */
- tmp = 0;
- break;
- case 20480000: /* 20.480 MHz */
- tmp = 1;
- break;
- case 28000000: /* 28.000 MHz */
- tmp = 2;
- break;
- case 25000000: /* 25.000 MHz */
- tmp = 3;
- break;
- default:
- err("invalid clock");
- return -EINVAL;
- }
-
- adc_cw = af913_div(state->config.clock, 1000000ul, 19);
- buf[0] = (adc_cw >> 0) & 0xff;
- buf[1] = (adc_cw >> 8) & 0xff;
- buf[2] = (adc_cw >> 16) & 0xff;
-
- ret = af9013_wr_regs(state, 0xd180, buf, 3);
- if (ret)
- goto err;
-
- ret = af9013_wr_reg_bits(state, 0x9bd2, 0, 4, tmp);
- if (ret)
- goto err;
-
- /* set I2C master clock */
- ret = af9013_wr_reg(state, 0xd416, 0x14);
- if (ret)
- goto err;
-
- /* set 16 embx */
- ret = af9013_wr_reg_bits(state, 0xd700, 1, 1, 1);
- if (ret)
- goto err;
-
- /* set no trigger */
- ret = af9013_wr_reg_bits(state, 0xd700, 2, 1, 0);
- if (ret)
- goto err;
-
- /* set read-update bit for constellation */
- ret = af9013_wr_reg_bits(state, 0xd371, 1, 1, 1);
- if (ret)
- goto err;
-
- /* settings for mp2if */
- if (state->config.ts_mode == AF9013_TS_USB) {
- /* AF9015 split PSB to 1.5k + 0.5k */
- ret = af9013_wr_reg_bits(state, 0xd50b, 2, 1, 1);
- if (ret)
- goto err;
- } else {
- /* AF9013 change the output bit to data7 */
- ret = af9013_wr_reg_bits(state, 0xd500, 3, 1, 1);
- if (ret)
- goto err;
-
- /* AF9013 set mpeg to full speed */
- ret = af9013_wr_reg_bits(state, 0xd502, 4, 1, 1);
- if (ret)
- goto err;
- }
-
- ret = af9013_wr_reg_bits(state, 0xd520, 4, 1, 1);
- if (ret)
- goto err;
-
- /* load OFSM settings */
- dbg("%s: load ofsm settings", __func__);
- len = ARRAY_SIZE(ofsm_init);
- init = ofsm_init;
- for (i = 0; i < len; i++) {
- ret = af9013_wr_reg_bits(state, init[i].addr, init[i].pos,
- init[i].len, init[i].val);
- if (ret)
- goto err;
- }
-
- /* load tuner specific settings */
- dbg("%s: load tuner specific settings", __func__);
- switch (state->config.tuner) {
- case AF9013_TUNER_MXL5003D:
- len = ARRAY_SIZE(tuner_init_mxl5003d);
- init = tuner_init_mxl5003d;
- break;
- case AF9013_TUNER_MXL5005D:
- case AF9013_TUNER_MXL5005R:
- case AF9013_TUNER_MXL5007T:
- len = ARRAY_SIZE(tuner_init_mxl5005);
- init = tuner_init_mxl5005;
- break;
- case AF9013_TUNER_ENV77H11D5:
- len = ARRAY_SIZE(tuner_init_env77h11d5);
- init = tuner_init_env77h11d5;
- break;
- case AF9013_TUNER_MT2060:
- len = ARRAY_SIZE(tuner_init_mt2060);
- init = tuner_init_mt2060;
- break;
- case AF9013_TUNER_MC44S803:
- len = ARRAY_SIZE(tuner_init_mc44s803);
- init = tuner_init_mc44s803;
- break;
- case AF9013_TUNER_QT1010:
- case AF9013_TUNER_QT1010A:
- len = ARRAY_SIZE(tuner_init_qt1010);
- init = tuner_init_qt1010;
- break;
- case AF9013_TUNER_MT2060_2:
- len = ARRAY_SIZE(tuner_init_mt2060_2);
- init = tuner_init_mt2060_2;
- break;
- case AF9013_TUNER_TDA18271:
- case AF9013_TUNER_TDA18218:
- len = ARRAY_SIZE(tuner_init_tda18271);
- init = tuner_init_tda18271;
- break;
- case AF9013_TUNER_UNKNOWN:
- default:
- len = ARRAY_SIZE(tuner_init_unknown);
- init = tuner_init_unknown;
- break;
- }
-
- for (i = 0; i < len; i++) {
- ret = af9013_wr_reg_bits(state, init[i].addr, init[i].pos,
- init[i].len, init[i].val);
- if (ret)
- goto err;
- }
-
- /* TS mode */
- ret = af9013_wr_reg_bits(state, 0xd500, 1, 2, state->config.ts_mode);
- if (ret)
- goto err;
-
- /* enable lock led */
- ret = af9013_wr_reg_bits(state, 0xd730, 0, 1, 1);
- if (ret)
- goto err;
-
- /* check if we support signal strength */
- if (!state->signal_strength_en) {
- ret = af9013_rd_reg_bits(state, 0x9bee, 0, 1,
- &state->signal_strength_en);
- if (ret)
- goto err;
- }
-
- /* read values needed for signal strength calculation */
- if (state->signal_strength_en && !state->rf_50) {
- ret = af9013_rd_reg(state, 0x9bbd, &state->rf_50);
- if (ret)
- goto err;
-
- ret = af9013_rd_reg(state, 0x9bd0, &state->rf_80);
- if (ret)
- goto err;
-
- ret = af9013_rd_reg(state, 0x9be2, &state->if_50);
- if (ret)
- goto err;
-
- ret = af9013_rd_reg(state, 0x9be4, &state->if_80);
- if (ret)
- goto err;
- }
-
- /* SNR */
- ret = af9013_wr_reg(state, 0xd2e2, 1);
- if (ret)
- goto err;
-
- /* BER / UCB */
- buf[0] = (10000 >> 0) & 0xff;
- buf[1] = (10000 >> 8) & 0xff;
- ret = af9013_wr_regs(state, 0xd385, buf, 2);
- if (ret)
- goto err;
-
- /* enable FEC monitor */
- ret = af9013_wr_reg_bits(state, 0xd392, 1, 1, 1);
- if (ret)
- goto err;
-
- state->first_tune = true;
- schedule_delayed_work(&state->statistics_work, msecs_to_jiffies(400));
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_sleep(struct dvb_frontend *fe)
-{
- struct af9013_state *state = fe->demodulator_priv;
- int ret;
-
- dbg("%s", __func__);
-
- /* stop statistics polling */
- cancel_delayed_work_sync(&state->statistics_work);
-
- /* disable lock led */
- ret = af9013_wr_reg_bits(state, 0xd730, 0, 1, 0);
- if (ret)
- goto err;
-
- /* power off */
- ret = af9013_power_ctrl(state, 0);
- if (ret)
- goto err;
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int af9013_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- int ret;
- struct af9013_state *state = fe->demodulator_priv;
-
- dbg("%s: enable=%d", __func__, enable);
-
- /* gate already open or close */
- if (state->i2c_gate_state == enable)
- return 0;
-
- if (state->config.ts_mode == AF9013_TS_USB)
- ret = af9013_wr_reg_bits(state, 0xd417, 3, 1, enable);
- else
- ret = af9013_wr_reg_bits(state, 0xd607, 2, 1, enable);
- if (ret)
- goto err;
-
- state->i2c_gate_state = enable;
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static void af9013_release(struct dvb_frontend *fe)
-{
- struct af9013_state *state = fe->demodulator_priv;
- kfree(state);
-}
-
-static struct dvb_frontend_ops af9013_ops;
-
-static int af9013_download_firmware(struct af9013_state *state)
-{
- int i, len, remaining, ret;
- const struct firmware *fw;
- u16 checksum = 0;
- u8 val;
- u8 fw_params[4];
- u8 *fw_file = AF9013_DEFAULT_FIRMWARE;
-
- msleep(100);
- /* check whether firmware is already running */
- ret = af9013_rd_reg(state, 0x98be, &val);
- if (ret)
- goto err;
- else
- dbg("%s: firmware status=%02x", __func__, val);
-
- if (val == 0x0c) /* fw is running, no need for download */
- goto exit;
-
- info("found a '%s' in cold state, will try to load a firmware",
- af9013_ops.info.name);
-
- /* request the firmware, this will block and timeout */
- ret = request_firmware(&fw, fw_file, state->i2c->dev.parent);
- if (ret) {
- err("did not find the firmware file. (%s) "
- "Please see linux/Documentation/dvb/ for more details" \
- " on firmware-problems. (%d)",
- fw_file, ret);
- goto err;
- }
-
- info("downloading firmware from file '%s'", fw_file);
-
- /* calc checksum */
- for (i = 0; i < fw->size; i++)
- checksum += fw->data[i];
-
- fw_params[0] = checksum >> 8;
- fw_params[1] = checksum & 0xff;
- fw_params[2] = fw->size >> 8;
- fw_params[3] = fw->size & 0xff;
-
- /* write fw checksum & size */
- ret = af9013_write_ofsm_regs(state, 0x50fc,
- fw_params, sizeof(fw_params));
- if (ret)
- goto err_release;
-
- #define FW_ADDR 0x5100 /* firmware start address */
- #define LEN_MAX 16 /* max packet size */
- for (remaining = fw->size; remaining > 0; remaining -= LEN_MAX) {
- len = remaining;
- if (len > LEN_MAX)
- len = LEN_MAX;
-
- ret = af9013_write_ofsm_regs(state,
- FW_ADDR + fw->size - remaining,
- (u8 *) &fw->data[fw->size - remaining], len);
- if (ret) {
- err("firmware download failed:%d", ret);
- goto err_release;
- }
- }
-
- /* request boot firmware */
- ret = af9013_wr_reg(state, 0xe205, 1);
- if (ret)
- goto err_release;
-
- for (i = 0; i < 15; i++) {
- msleep(100);
-
- /* check firmware status */
- ret = af9013_rd_reg(state, 0x98be, &val);
- if (ret)
- goto err_release;
-
- dbg("%s: firmware status=%02x", __func__, val);
-
- if (val == 0x0c || val == 0x04) /* success or fail */
- break;
- }
-
- if (val == 0x04) {
- err("firmware did not run");
- ret = -ENODEV;
- } else if (val != 0x0c) {
- err("firmware boot timeout");
- ret = -ENODEV;
- }
-
-err_release:
- release_firmware(fw);
-err:
-exit:
- if (!ret)
- info("found a '%s' in warm state.", af9013_ops.info.name);
- return ret;
-}
-
-struct dvb_frontend *af9013_attach(const struct af9013_config *config,
- struct i2c_adapter *i2c)
-{
- int ret;
- struct af9013_state *state = NULL;
- u8 buf[4], i;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct af9013_state), GFP_KERNEL);
- if (state == NULL)
- goto err;
-
- /* setup the state */
- state->i2c = i2c;
- memcpy(&state->config, config, sizeof(struct af9013_config));
-
- /* download firmware */
- if (state->config.ts_mode != AF9013_TS_USB) {
- ret = af9013_download_firmware(state);
- if (ret)
- goto err;
- }
-
- /* firmware version */
- ret = af9013_rd_regs(state, 0x5103, buf, 4);
- if (ret)
- goto err;
-
- info("firmware version %d.%d.%d.%d", buf[0], buf[1], buf[2], buf[3]);
-
- /* set GPIOs */
- for (i = 0; i < sizeof(state->config.gpio); i++) {
- ret = af9013_set_gpio(state, i, state->config.gpio[i]);
- if (ret)
- goto err;
- }
-
- /* create dvb_frontend */
- memcpy(&state->fe.ops, &af9013_ops,
- sizeof(struct dvb_frontend_ops));
- state->fe.demodulator_priv = state;
-
- INIT_DELAYED_WORK(&state->statistics_work, af9013_statistics_work);
-
- return &state->fe;
-err:
- kfree(state);
- return NULL;
-}
-EXPORT_SYMBOL(af9013_attach);
-
-static struct dvb_frontend_ops af9013_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "Afatech AF9013",
- .frequency_min = 174000000,
- .frequency_max = 862000000,
- .frequency_stepsize = 250000,
- .frequency_tolerance = 0,
- .caps = FE_CAN_FEC_1_2 |
- FE_CAN_FEC_2_3 |
- FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 |
- FE_CAN_FEC_7_8 |
- FE_CAN_FEC_AUTO |
- FE_CAN_QPSK |
- FE_CAN_QAM_16 |
- FE_CAN_QAM_64 |
- FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_HIERARCHY_AUTO |
- FE_CAN_RECOVER |
- FE_CAN_MUTE_TS
- },
-
- .release = af9013_release,
-
- .init = af9013_init,
- .sleep = af9013_sleep,
-
- .get_tune_settings = af9013_get_tune_settings,
- .set_frontend = af9013_set_frontend,
- .get_frontend = af9013_get_frontend,
-
- .read_status = af9013_read_status,
- .read_snr = af9013_read_snr,
- .read_signal_strength = af9013_read_signal_strength,
- .read_ber = af9013_read_ber,
- .read_ucblocks = af9013_read_ucblocks,
-
- .i2c_gate_ctrl = af9013_i2c_gate_ctrl,
-};
-
-MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
-MODULE_DESCRIPTION("Afatech AF9013 DVB-T demodulator driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/af9013.h b/drivers/media/dvb/frontends/af9013.h
deleted file mode 100644
index b973fc5a038..00000000000
--- a/drivers/media/dvb/frontends/af9013.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Afatech AF9013 demodulator driver
- *
- * Copyright (C) 2007 Antti Palosaari <crope@iki.fi>
- * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
- *
- * Thanks to Afatech who kindly provided information.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef AF9013_H
-#define AF9013_H
-
-#include <linux/dvb/frontend.h>
-
-/* AF9013/5 GPIOs (mostly guessed)
- demod#1-gpio#0 - set demod#2 i2c-addr for dual devices
- demod#1-gpio#1 - xtal setting (?)
- demod#1-gpio#3 - tuner#1
- demod#2-gpio#0 - tuner#2
- demod#2-gpio#1 - xtal setting (?)
-*/
-
-struct af9013_config {
- /*
- * I2C address
- */
- u8 i2c_addr;
-
- /*
- * clock
- * 20480000, 25000000, 28000000, 28800000
- */
- u32 clock;
-
- /*
- * tuner
- */
-#define AF9013_TUNER_MXL5003D 3 /* MaxLinear */
-#define AF9013_TUNER_MXL5005D 13 /* MaxLinear */
-#define AF9013_TUNER_MXL5005R 30 /* MaxLinear */
-#define AF9013_TUNER_ENV77H11D5 129 /* Panasonic */
-#define AF9013_TUNER_MT2060 130 /* Microtune */
-#define AF9013_TUNER_MC44S803 133 /* Freescale */
-#define AF9013_TUNER_QT1010 134 /* Quantek */
-#define AF9013_TUNER_UNKNOWN 140 /* for can tuners ? */
-#define AF9013_TUNER_MT2060_2 147 /* Microtune */
-#define AF9013_TUNER_TDA18271 156 /* NXP */
-#define AF9013_TUNER_QT1010A 162 /* Quantek */
-#define AF9013_TUNER_MXL5007T 177 /* MaxLinear */
-#define AF9013_TUNER_TDA18218 179 /* NXP */
- u8 tuner;
-
- /*
- * IF frequency
- */
- u32 if_frequency;
-
- /*
- * TS settings
- */
-#define AF9013_TS_USB 0
-#define AF9013_TS_PARALLEL 1
-#define AF9013_TS_SERIAL 2
- u8 ts_mode:2;
-
- /*
- * input spectrum inversion
- */
- bool spec_inv;
-
- /*
- * firmware API version
- */
- u8 api_version[4];
-
- /*
- * GPIOs
- */
-#define AF9013_GPIO_ON (1 << 0)
-#define AF9013_GPIO_EN (1 << 1)
-#define AF9013_GPIO_O (1 << 2)
-#define AF9013_GPIO_I (1 << 3)
-#define AF9013_GPIO_LO (AF9013_GPIO_ON|AF9013_GPIO_EN)
-#define AF9013_GPIO_HI (AF9013_GPIO_ON|AF9013_GPIO_EN|AF9013_GPIO_O)
-#define AF9013_GPIO_TUNER_ON (AF9013_GPIO_ON|AF9013_GPIO_EN)
-#define AF9013_GPIO_TUNER_OFF (AF9013_GPIO_ON|AF9013_GPIO_EN|AF9013_GPIO_O)
- u8 gpio[4];
-};
-
-#if defined(CONFIG_DVB_AF9013) || \
- (defined(CONFIG_DVB_AF9013_MODULE) && defined(MODULE))
-extern struct dvb_frontend *af9013_attach(const struct af9013_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline struct dvb_frontend *af9013_attach(
-const struct af9013_config *config, struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif /* CONFIG_DVB_AF9013 */
-
-#endif /* AF9013_H */
diff --git a/drivers/media/dvb/frontends/af9013_priv.h b/drivers/media/dvb/frontends/af9013_priv.h
deleted file mode 100644
index fa848af6e9b..00000000000
--- a/drivers/media/dvb/frontends/af9013_priv.h
+++ /dev/null
@@ -1,922 +0,0 @@
-/*
- * Afatech AF9013 demodulator driver
- *
- * Copyright (C) 2007 Antti Palosaari <crope@iki.fi>
- * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
- *
- * Thanks to Afatech who kindly provided information.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef AF9013_PRIV_H
-#define AF9013_PRIV_H
-
-#include "dvb_frontend.h"
-#include "af9013.h"
-#include <linux/firmware.h>
-
-#define LOG_PREFIX "af9013"
-
-#undef dbg
-#define dbg(f, arg...) \
- if (af9013_debug) \
- printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
-#undef err
-#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
-#undef info
-#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
-#undef warn
-#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
-
-#define AF9013_DEFAULT_FIRMWARE "dvb-fe-af9013.fw"
-
-struct af9013_reg_bit {
- u16 addr;
- u8 pos:4;
- u8 len:4;
- u8 val;
-};
-
-struct af9013_snr {
- u32 val;
- u8 snr;
-};
-
-struct af9013_coeff {
- u32 clock;
- u32 bandwidth_hz;
- u8 val[24];
-};
-
-/* pre-calculated coeff lookup table */
-static const struct af9013_coeff coeff_lut[] = {
- /* 28.800 MHz */
- { 28800000, 8000000, { 0x02, 0x8a, 0x28, 0xa3, 0x05, 0x14,
- 0x51, 0x11, 0x00, 0xa2, 0x8f, 0x3d, 0x00, 0xa2, 0x8a,
- 0x29, 0x00, 0xa2, 0x85, 0x14, 0x01, 0x45, 0x14, 0x14 } },
- { 28800000, 7000000, { 0x02, 0x38, 0xe3, 0x8e, 0x04, 0x71,
- 0xc7, 0x07, 0x00, 0x8e, 0x3d, 0x55, 0x00, 0x8e, 0x38,
- 0xe4, 0x00, 0x8e, 0x34, 0x72, 0x01, 0x1c, 0x71, 0x32 } },
- { 28800000, 6000000, { 0x01, 0xe7, 0x9e, 0x7a, 0x03, 0xcf,
- 0x3c, 0x3d, 0x00, 0x79, 0xeb, 0x6e, 0x00, 0x79, 0xe7,
- 0x9e, 0x00, 0x79, 0xe3, 0xcf, 0x00, 0xf3, 0xcf, 0x0f } },
- /* 20.480 MHz */
- { 20480000, 8000000, { 0x03, 0x92, 0x49, 0x26, 0x07, 0x24,
- 0x92, 0x13, 0x00, 0xe4, 0x99, 0x6e, 0x00, 0xe4, 0x92,
- 0x49, 0x00, 0xe4, 0x8b, 0x25, 0x01, 0xc9, 0x24, 0x25 } },
- { 20480000, 7000000, { 0x03, 0x20, 0x00, 0x01, 0x06, 0x40,
- 0x00, 0x00, 0x00, 0xc8, 0x06, 0x40, 0x00, 0xc8, 0x00,
- 0x00, 0x00, 0xc7, 0xf9, 0xc0, 0x01, 0x90, 0x00, 0x00 } },
- { 20480000, 6000000, { 0x02, 0xad, 0xb6, 0xdc, 0x05, 0x5b,
- 0x6d, 0x2e, 0x00, 0xab, 0x73, 0x13, 0x00, 0xab, 0x6d,
- 0xb7, 0x00, 0xab, 0x68, 0x5c, 0x01, 0x56, 0xdb, 0x1c } },
- /* 28.000 MHz */
- { 28000000, 8000000, { 0x02, 0x9c, 0xbc, 0x15, 0x05, 0x39,
- 0x78, 0x0a, 0x00, 0xa7, 0x34, 0x3f, 0x00, 0xa7, 0x2f,
- 0x05, 0x00, 0xa7, 0x29, 0xcc, 0x01, 0x4e, 0x5e, 0x03 } },
- { 28000000, 7000000, { 0x02, 0x49, 0x24, 0x92, 0x04, 0x92,
- 0x49, 0x09, 0x00, 0x92, 0x4d, 0xb7, 0x00, 0x92, 0x49,
- 0x25, 0x00, 0x92, 0x44, 0x92, 0x01, 0x24, 0x92, 0x12 } },
- { 28000000, 6000000, { 0x01, 0xf5, 0x8d, 0x10, 0x03, 0xeb,
- 0x1a, 0x08, 0x00, 0x7d, 0x67, 0x2f, 0x00, 0x7d, 0x63,
- 0x44, 0x00, 0x7d, 0x5f, 0x59, 0x00, 0xfa, 0xc6, 0x22 } },
- /* 25.000 MHz */
- { 25000000, 8000000, { 0x02, 0xec, 0xfb, 0x9d, 0x05, 0xd9,
- 0xf7, 0x0e, 0x00, 0xbb, 0x44, 0xc1, 0x00, 0xbb, 0x3e,
- 0xe7, 0x00, 0xbb, 0x39, 0x0d, 0x01, 0x76, 0x7d, 0x34 } },
- { 25000000, 7000000, { 0x02, 0x8f, 0x5c, 0x29, 0x05, 0x1e,
- 0xb8, 0x14, 0x00, 0xa3, 0xdc, 0x29, 0x00, 0xa3, 0xd7,
- 0x0a, 0x00, 0xa3, 0xd1, 0xec, 0x01, 0x47, 0xae, 0x05 } },
- { 25000000, 6000000, { 0x02, 0x31, 0xbc, 0xb5, 0x04, 0x63,
- 0x79, 0x1b, 0x00, 0x8c, 0x73, 0x91, 0x00, 0x8c, 0x6f,
- 0x2d, 0x00, 0x8c, 0x6a, 0xca, 0x01, 0x18, 0xde, 0x17 } },
-};
-
-/* QPSK SNR lookup table */
-static const struct af9013_snr qpsk_snr_lut[] = {
- { 0x000000, 0 },
- { 0x0b4771, 0 },
- { 0x0c1aed, 1 },
- { 0x0d0d27, 2 },
- { 0x0e4d19, 3 },
- { 0x0e5da8, 4 },
- { 0x107097, 5 },
- { 0x116975, 6 },
- { 0x1252d9, 7 },
- { 0x131fa4, 8 },
- { 0x13d5e1, 9 },
- { 0x148e53, 10 },
- { 0x15358b, 11 },
- { 0x15dd29, 12 },
- { 0x168112, 13 },
- { 0x170b61, 14 },
- { 0xffffff, 15 },
-};
-
-/* QAM16 SNR lookup table */
-static const struct af9013_snr qam16_snr_lut[] = {
- { 0x000000, 0 },
- { 0x05eb62, 5 },
- { 0x05fecf, 6 },
- { 0x060b80, 7 },
- { 0x062501, 8 },
- { 0x064865, 9 },
- { 0x069604, 10 },
- { 0x06f356, 11 },
- { 0x07706a, 12 },
- { 0x0804d3, 13 },
- { 0x089d1a, 14 },
- { 0x093e3d, 15 },
- { 0x09e35d, 16 },
- { 0x0a7c3c, 17 },
- { 0x0afaf8, 18 },
- { 0x0b719d, 19 },
- { 0xffffff, 20 },
-};
-
-/* QAM64 SNR lookup table */
-static const struct af9013_snr qam64_snr_lut[] = {
- { 0x000000, 0 },
- { 0x03109b, 12 },
- { 0x0310d4, 13 },
- { 0x031920, 14 },
- { 0x0322d0, 15 },
- { 0x0339fc, 16 },
- { 0x0364a1, 17 },
- { 0x038bcc, 18 },
- { 0x03c7d3, 19 },
- { 0x0408cc, 20 },
- { 0x043bed, 21 },
- { 0x048061, 22 },
- { 0x04be95, 23 },
- { 0x04fa7d, 24 },
- { 0x052405, 25 },
- { 0x05570d, 26 },
- { 0xffffff, 27 },
-};
-
-static const struct af9013_reg_bit ofsm_init[] = {
- { 0xd73a, 0, 8, 0xa1 },
- { 0xd73b, 0, 8, 0x1f },
- { 0xd73c, 4, 4, 0x0a },
- { 0xd732, 3, 1, 0x00 },
- { 0xd731, 4, 2, 0x03 },
- { 0xd73d, 7, 1, 0x01 },
- { 0xd740, 0, 1, 0x00 },
- { 0xd740, 1, 1, 0x00 },
- { 0xd740, 2, 1, 0x00 },
- { 0xd740, 3, 1, 0x01 },
- { 0xd3c1, 4, 1, 0x01 },
- { 0x9124, 0, 8, 0x58 },
- { 0x9125, 0, 2, 0x02 },
- { 0xd3a2, 0, 8, 0x00 },
- { 0xd3a3, 0, 8, 0x04 },
- { 0xd305, 0, 8, 0x32 },
- { 0xd306, 0, 8, 0x10 },
- { 0xd304, 0, 8, 0x04 },
- { 0x9112, 0, 1, 0x01 },
- { 0x911d, 0, 1, 0x01 },
- { 0x911a, 0, 1, 0x01 },
- { 0x911b, 0, 1, 0x01 },
- { 0x9bce, 0, 4, 0x02 },
- { 0x9116, 0, 1, 0x01 },
- { 0x9122, 0, 8, 0xd0 },
- { 0xd2e0, 0, 8, 0xd0 },
- { 0xd2e9, 0, 4, 0x0d },
- { 0xd38c, 0, 8, 0xfc },
- { 0xd38d, 0, 8, 0x00 },
- { 0xd38e, 0, 8, 0x7e },
- { 0xd38f, 0, 8, 0x00 },
- { 0xd390, 0, 8, 0x2f },
- { 0xd145, 4, 1, 0x01 },
- { 0xd1a9, 4, 1, 0x01 },
- { 0xd158, 5, 3, 0x01 },
- { 0xd159, 0, 6, 0x06 },
- { 0xd167, 0, 8, 0x00 },
- { 0xd168, 0, 4, 0x07 },
- { 0xd1c3, 5, 3, 0x00 },
- { 0xd1c4, 0, 6, 0x00 },
- { 0xd1c5, 0, 7, 0x10 },
- { 0xd1c6, 0, 3, 0x02 },
- { 0xd080, 2, 5, 0x03 },
- { 0xd081, 4, 4, 0x09 },
- { 0xd098, 4, 4, 0x0f },
- { 0xd098, 0, 4, 0x03 },
- { 0xdbc0, 4, 1, 0x01 },
- { 0xdbc7, 0, 8, 0x08 },
- { 0xdbc8, 4, 4, 0x00 },
- { 0xdbc9, 0, 5, 0x01 },
- { 0xd280, 0, 8, 0xe0 },
- { 0xd281, 0, 8, 0xff },
- { 0xd282, 0, 8, 0xff },
- { 0xd283, 0, 8, 0xc3 },
- { 0xd284, 0, 8, 0xff },
- { 0xd285, 0, 4, 0x01 },
- { 0xd0f0, 0, 7, 0x1a },
- { 0xd0f1, 4, 1, 0x01 },
- { 0xd0f2, 0, 8, 0x0c },
- { 0xd101, 5, 3, 0x06 },
- { 0xd103, 0, 4, 0x08 },
- { 0xd0f8, 0, 7, 0x20 },
- { 0xd111, 5, 1, 0x00 },
- { 0xd111, 6, 1, 0x00 },
- { 0x910b, 0, 8, 0x0a },
- { 0x9115, 0, 8, 0x02 },
- { 0x910c, 0, 8, 0x02 },
- { 0x910d, 0, 8, 0x08 },
- { 0x910e, 0, 8, 0x0a },
- { 0x9bf6, 0, 8, 0x06 },
- { 0x9bf8, 0, 8, 0x02 },
- { 0x9bf7, 0, 8, 0x05 },
- { 0x9bf9, 0, 8, 0x0f },
- { 0x9bfc, 0, 8, 0x13 },
- { 0x9bd3, 0, 8, 0xff },
- { 0x9bbe, 0, 1, 0x01 },
- { 0x9bcc, 0, 1, 0x01 },
-};
-
-/* Panasonic ENV77H11D5 tuner init
- AF9013_TUNER_ENV77H11D5 = 129 */
-static const struct af9013_reg_bit tuner_init_env77h11d5[] = {
- { 0x9bd5, 0, 8, 0x01 },
- { 0x9bd6, 0, 8, 0x03 },
- { 0x9bbe, 0, 8, 0x01 },
- { 0xd1a0, 1, 1, 0x01 },
- { 0xd000, 0, 1, 0x01 },
- { 0xd000, 1, 1, 0x00 },
- { 0xd001, 1, 1, 0x01 },
- { 0xd001, 0, 1, 0x00 },
- { 0xd001, 5, 1, 0x00 },
- { 0xd002, 0, 5, 0x19 },
- { 0xd003, 0, 5, 0x1a },
- { 0xd004, 0, 5, 0x19 },
- { 0xd005, 0, 5, 0x1a },
- { 0xd00e, 0, 5, 0x10 },
- { 0xd00f, 0, 3, 0x04 },
- { 0xd00f, 3, 3, 0x05 },
- { 0xd010, 0, 3, 0x04 },
- { 0xd010, 3, 3, 0x05 },
- { 0xd016, 4, 4, 0x03 },
- { 0xd01f, 0, 6, 0x0a },
- { 0xd020, 0, 6, 0x0a },
- { 0x9bda, 0, 8, 0x00 },
- { 0x9be3, 0, 8, 0x00 },
- { 0xd015, 0, 8, 0x50 },
- { 0xd016, 0, 1, 0x00 },
- { 0xd044, 0, 8, 0x46 },
- { 0xd045, 0, 1, 0x00 },
- { 0xd008, 0, 8, 0xdf },
- { 0xd009, 0, 2, 0x02 },
- { 0xd006, 0, 8, 0x44 },
- { 0xd007, 0, 2, 0x01 },
- { 0xd00c, 0, 8, 0xeb },
- { 0xd00d, 0, 2, 0x02 },
- { 0xd00a, 0, 8, 0xf4 },
- { 0xd00b, 0, 2, 0x01 },
- { 0x9bba, 0, 8, 0xf9 },
- { 0x9bc3, 0, 8, 0xdf },
- { 0x9bc4, 0, 8, 0x02 },
- { 0x9bc5, 0, 8, 0xeb },
- { 0x9bc6, 0, 8, 0x02 },
- { 0x9bc9, 0, 8, 0x52 },
- { 0xd011, 0, 8, 0x3c },
- { 0xd012, 0, 2, 0x01 },
- { 0xd013, 0, 8, 0xf7 },
- { 0xd014, 0, 2, 0x02 },
- { 0xd040, 0, 8, 0x0b },
- { 0xd041, 0, 2, 0x02 },
- { 0xd042, 0, 8, 0x4d },
- { 0xd043, 0, 2, 0x00 },
- { 0xd045, 1, 1, 0x00 },
- { 0x9bcf, 0, 1, 0x01 },
- { 0xd045, 2, 1, 0x01 },
- { 0xd04f, 0, 8, 0x9a },
- { 0xd050, 0, 1, 0x01 },
- { 0xd051, 0, 8, 0x5a },
- { 0xd052, 0, 1, 0x01 },
- { 0xd053, 0, 8, 0x50 },
- { 0xd054, 0, 8, 0x46 },
- { 0x9bd7, 0, 8, 0x0a },
- { 0x9bd8, 0, 8, 0x14 },
- { 0x9bd9, 0, 8, 0x08 },
-};
-
-/* Microtune MT2060 tuner init
- AF9013_TUNER_MT2060 = 130 */
-static const struct af9013_reg_bit tuner_init_mt2060[] = {
- { 0x9bd5, 0, 8, 0x01 },
- { 0x9bd6, 0, 8, 0x07 },
- { 0xd1a0, 1, 1, 0x01 },
- { 0xd000, 0, 1, 0x01 },
- { 0xd000, 1, 1, 0x00 },
- { 0xd001, 1, 1, 0x01 },
- { 0xd001, 0, 1, 0x00 },
- { 0xd001, 5, 1, 0x00 },
- { 0xd002, 0, 5, 0x19 },
- { 0xd003, 0, 5, 0x1a },
- { 0xd004, 0, 5, 0x19 },
- { 0xd005, 0, 5, 0x1a },
- { 0xd00e, 0, 5, 0x10 },
- { 0xd00f, 0, 3, 0x04 },
- { 0xd00f, 3, 3, 0x05 },
- { 0xd010, 0, 3, 0x04 },
- { 0xd010, 3, 3, 0x05 },
- { 0xd016, 4, 4, 0x03 },
- { 0xd01f, 0, 6, 0x0a },
- { 0xd020, 0, 6, 0x0a },
- { 0x9bda, 0, 8, 0x00 },
- { 0x9be3, 0, 8, 0x00 },
- { 0x9bbe, 0, 1, 0x00 },
- { 0x9bcc, 0, 1, 0x00 },
- { 0x9bb9, 0, 8, 0x75 },
- { 0x9bcd, 0, 8, 0x24 },
- { 0x9bff, 0, 8, 0x30 },
- { 0xd015, 0, 8, 0x46 },
- { 0xd016, 0, 1, 0x00 },
- { 0xd044, 0, 8, 0x46 },
- { 0xd045, 0, 1, 0x00 },
- { 0xd008, 0, 8, 0x0f },
- { 0xd009, 0, 2, 0x02 },
- { 0xd006, 0, 8, 0x32 },
- { 0xd007, 0, 2, 0x01 },
- { 0xd00c, 0, 8, 0x36 },
- { 0xd00d, 0, 2, 0x03 },
- { 0xd00a, 0, 8, 0x35 },
- { 0xd00b, 0, 2, 0x01 },
- { 0x9bc7, 0, 8, 0x07 },
- { 0x9bc8, 0, 8, 0x90 },
- { 0x9bc3, 0, 8, 0x0f },
- { 0x9bc4, 0, 8, 0x02 },
- { 0x9bc5, 0, 8, 0x36 },
- { 0x9bc6, 0, 8, 0x03 },
- { 0x9bba, 0, 8, 0xc9 },
- { 0x9bc9, 0, 8, 0x79 },
- { 0xd011, 0, 8, 0x10 },
- { 0xd012, 0, 2, 0x01 },
- { 0xd013, 0, 8, 0x45 },
- { 0xd014, 0, 2, 0x03 },
- { 0xd040, 0, 8, 0x98 },
- { 0xd041, 0, 2, 0x00 },
- { 0xd042, 0, 8, 0xcf },
- { 0xd043, 0, 2, 0x03 },
- { 0xd045, 1, 1, 0x00 },
- { 0x9bcf, 0, 1, 0x01 },
- { 0xd045, 2, 1, 0x01 },
- { 0xd04f, 0, 8, 0x9a },
- { 0xd050, 0, 1, 0x01 },
- { 0xd051, 0, 8, 0x5a },
- { 0xd052, 0, 1, 0x01 },
- { 0xd053, 0, 8, 0x50 },
- { 0xd054, 0, 8, 0x46 },
- { 0x9bd7, 0, 8, 0x0a },
- { 0x9bd8, 0, 8, 0x14 },
- { 0x9bd9, 0, 8, 0x08 },
- { 0x9bd0, 0, 8, 0xcc },
- { 0x9be4, 0, 8, 0xa0 },
- { 0x9bbd, 0, 8, 0x8e },
- { 0x9be2, 0, 8, 0x4d },
- { 0x9bee, 0, 1, 0x01 },
-};
-
-/* Microtune MT2060 tuner init
- AF9013_TUNER_MT2060_2 = 147 */
-static const struct af9013_reg_bit tuner_init_mt2060_2[] = {
- { 0x9bd5, 0, 8, 0x01 },
- { 0x9bd6, 0, 8, 0x06 },
- { 0x9bbe, 0, 8, 0x01 },
- { 0xd1a0, 1, 1, 0x01 },
- { 0xd000, 0, 1, 0x01 },
- { 0xd000, 1, 1, 0x00 },
- { 0xd001, 1, 1, 0x01 },
- { 0xd001, 0, 1, 0x00 },
- { 0xd001, 5, 1, 0x00 },
- { 0xd002, 0, 5, 0x19 },
- { 0xd003, 0, 5, 0x1a },
- { 0xd004, 0, 5, 0x19 },
- { 0xd005, 0, 5, 0x1a },
- { 0xd00e, 0, 5, 0x10 },
- { 0xd00f, 0, 3, 0x04 },
- { 0xd00f, 3, 3, 0x05 },
- { 0xd010, 0, 3, 0x04 },
- { 0xd010, 3, 3, 0x05 },
- { 0xd016, 4, 4, 0x03 },
- { 0xd01f, 0, 6, 0x0a },
- { 0xd020, 0, 6, 0x0a },
- { 0xd015, 0, 8, 0x46 },
- { 0xd016, 0, 1, 0x00 },
- { 0xd044, 0, 8, 0x46 },
- { 0xd045, 0, 1, 0x00 },
- { 0xd008, 0, 8, 0x0f },
- { 0xd009, 0, 2, 0x02 },
- { 0xd006, 0, 8, 0x32 },
- { 0xd007, 0, 2, 0x01 },
- { 0xd00c, 0, 8, 0x36 },
- { 0xd00d, 0, 2, 0x03 },
- { 0xd00a, 0, 8, 0x35 },
- { 0xd00b, 0, 2, 0x01 },
- { 0x9bc7, 0, 8, 0x07 },
- { 0x9bc8, 0, 8, 0x90 },
- { 0x9bc3, 0, 8, 0x0f },
- { 0x9bc4, 0, 8, 0x02 },
- { 0x9bc5, 0, 8, 0x36 },
- { 0x9bc6, 0, 8, 0x03 },
- { 0x9bba, 0, 8, 0xc9 },
- { 0x9bc9, 0, 8, 0x79 },
- { 0xd011, 0, 8, 0x10 },
- { 0xd012, 0, 2, 0x01 },
- { 0xd013, 0, 8, 0x45 },
- { 0xd014, 0, 2, 0x03 },
- { 0xd040, 0, 8, 0x98 },
- { 0xd041, 0, 2, 0x00 },
- { 0xd042, 0, 8, 0xcf },
- { 0xd043, 0, 2, 0x03 },
- { 0xd045, 1, 1, 0x00 },
- { 0x9bcf, 0, 8, 0x01 },
- { 0xd045, 2, 1, 0x01 },
- { 0xd04f, 0, 8, 0x9a },
- { 0xd050, 0, 1, 0x01 },
- { 0xd051, 0, 8, 0x5a },
- { 0xd052, 0, 1, 0x01 },
- { 0xd053, 0, 8, 0x96 },
- { 0xd054, 0, 8, 0x46 },
- { 0xd045, 7, 1, 0x00 },
- { 0x9bd7, 0, 8, 0x0a },
- { 0x9bd8, 0, 8, 0x14 },
- { 0x9bd9, 0, 8, 0x08 },
-};
-
-/* MaxLinear MXL5003 tuner init
- AF9013_TUNER_MXL5003D = 3 */
-static const struct af9013_reg_bit tuner_init_mxl5003d[] = {
- { 0x9bd5, 0, 8, 0x01 },
- { 0x9bd6, 0, 8, 0x09 },
- { 0xd1a0, 1, 1, 0x01 },
- { 0xd000, 0, 1, 0x01 },
- { 0xd000, 1, 1, 0x00 },
- { 0xd001, 1, 1, 0x01 },
- { 0xd001, 0, 1, 0x00 },
- { 0xd001, 5, 1, 0x00 },
- { 0xd002, 0, 5, 0x19 },
- { 0xd003, 0, 5, 0x1a },
- { 0xd004, 0, 5, 0x19 },
- { 0xd005, 0, 5, 0x1a },
- { 0xd00e, 0, 5, 0x10 },
- { 0xd00f, 0, 3, 0x04 },
- { 0xd00f, 3, 3, 0x05 },
- { 0xd010, 0, 3, 0x04 },
- { 0xd010, 3, 3, 0x05 },
- { 0xd016, 4, 4, 0x03 },
- { 0xd01f, 0, 6, 0x0a },
- { 0xd020, 0, 6, 0x0a },
- { 0x9bda, 0, 8, 0x00 },
- { 0x9be3, 0, 8, 0x00 },
- { 0x9bfc, 0, 8, 0x0f },
- { 0x9bf6, 0, 8, 0x01 },
- { 0x9bbe, 0, 1, 0x01 },
- { 0xd015, 0, 8, 0x33 },
- { 0xd016, 0, 1, 0x00 },
- { 0xd044, 0, 8, 0x40 },
- { 0xd045, 0, 1, 0x00 },
- { 0xd008, 0, 8, 0x0f },
- { 0xd009, 0, 2, 0x02 },
- { 0xd006, 0, 8, 0x6c },
- { 0xd007, 0, 2, 0x00 },
- { 0xd00c, 0, 8, 0x3d },
- { 0xd00d, 0, 2, 0x00 },
- { 0xd00a, 0, 8, 0x45 },
- { 0xd00b, 0, 2, 0x01 },
- { 0x9bc7, 0, 8, 0x07 },
- { 0x9bc8, 0, 8, 0x52 },
- { 0x9bc3, 0, 8, 0x0f },
- { 0x9bc4, 0, 8, 0x02 },
- { 0x9bc5, 0, 8, 0x3d },
- { 0x9bc6, 0, 8, 0x00 },
- { 0x9bba, 0, 8, 0xa2 },
- { 0x9bc9, 0, 8, 0xa0 },
- { 0xd011, 0, 8, 0x56 },
- { 0xd012, 0, 2, 0x00 },
- { 0xd013, 0, 8, 0x50 },
- { 0xd014, 0, 2, 0x00 },
- { 0xd040, 0, 8, 0x56 },
- { 0xd041, 0, 2, 0x00 },
- { 0xd042, 0, 8, 0x50 },
- { 0xd043, 0, 2, 0x00 },
- { 0xd045, 1, 1, 0x00 },
- { 0x9bcf, 0, 8, 0x01 },
- { 0xd045, 2, 1, 0x01 },
- { 0xd04f, 0, 8, 0x9a },
- { 0xd050, 0, 1, 0x01 },
- { 0xd051, 0, 8, 0x5a },
- { 0xd052, 0, 1, 0x01 },
- { 0xd053, 0, 8, 0x50 },
- { 0xd054, 0, 8, 0x46 },
- { 0x9bd7, 0, 8, 0x0a },
- { 0x9bd8, 0, 8, 0x14 },
- { 0x9bd9, 0, 8, 0x08 },
-};
-
-/* MaxLinear MXL5005S & MXL5007T tuner init
- AF9013_TUNER_MXL5005D = 13
- AF9013_TUNER_MXL5005R = 30
- AF9013_TUNER_MXL5007T = 177 */
-static const struct af9013_reg_bit tuner_init_mxl5005[] = {
- { 0x9bd5, 0, 8, 0x01 },
- { 0x9bd6, 0, 8, 0x07 },
- { 0xd1a0, 1, 1, 0x01 },
- { 0xd000, 0, 1, 0x01 },
- { 0xd000, 1, 1, 0x00 },
- { 0xd001, 1, 1, 0x01 },
- { 0xd001, 0, 1, 0x00 },
- { 0xd001, 5, 1, 0x00 },
- { 0xd002, 0, 5, 0x19 },
- { 0xd003, 0, 5, 0x1a },
- { 0xd004, 0, 5, 0x19 },
- { 0xd005, 0, 5, 0x1a },
- { 0xd00e, 0, 5, 0x10 },
- { 0xd00f, 0, 3, 0x04 },
- { 0xd00f, 3, 3, 0x05 },
- { 0xd010, 0, 3, 0x04 },
- { 0xd010, 3, 3, 0x05 },
- { 0xd016, 4, 4, 0x03 },
- { 0xd01f, 0, 6, 0x0a },
- { 0xd020, 0, 6, 0x0a },
- { 0x9bda, 0, 8, 0x01 },
- { 0x9be3, 0, 8, 0x01 },
- { 0x9bbe, 0, 1, 0x01 },
- { 0x9bcc, 0, 1, 0x01 },
- { 0x9bb9, 0, 8, 0x00 },
- { 0x9bcd, 0, 8, 0x28 },
- { 0x9bff, 0, 8, 0x24 },
- { 0xd015, 0, 8, 0x40 },
- { 0xd016, 0, 1, 0x00 },
- { 0xd044, 0, 8, 0x40 },
- { 0xd045, 0, 1, 0x00 },
- { 0xd008, 0, 8, 0x0f },
- { 0xd009, 0, 2, 0x02 },
- { 0xd006, 0, 8, 0x73 },
- { 0xd007, 0, 2, 0x01 },
- { 0xd00c, 0, 8, 0xfa },
- { 0xd00d, 0, 2, 0x01 },
- { 0xd00a, 0, 8, 0xff },
- { 0xd00b, 0, 2, 0x01 },
- { 0x9bc7, 0, 8, 0x23 },
- { 0x9bc8, 0, 8, 0x55 },
- { 0x9bc3, 0, 8, 0x01 },
- { 0x9bc4, 0, 8, 0x02 },
- { 0x9bc5, 0, 8, 0xfa },
- { 0x9bc6, 0, 8, 0x01 },
- { 0x9bba, 0, 8, 0xff },
- { 0x9bc9, 0, 8, 0xff },
- { 0x9bd3, 0, 8, 0x95 },
- { 0xd011, 0, 8, 0x70 },
- { 0xd012, 0, 2, 0x01 },
- { 0xd013, 0, 8, 0xfb },
- { 0xd014, 0, 2, 0x01 },
- { 0xd040, 0, 8, 0x70 },
- { 0xd041, 0, 2, 0x01 },
- { 0xd042, 0, 8, 0xfb },
- { 0xd043, 0, 2, 0x01 },
- { 0xd045, 1, 1, 0x00 },
- { 0x9bcf, 0, 1, 0x01 },
- { 0xd045, 2, 1, 0x01 },
- { 0xd04f, 0, 8, 0x9a },
- { 0xd050, 0, 1, 0x01 },
- { 0xd051, 0, 8, 0x5a },
- { 0xd052, 0, 1, 0x01 },
- { 0xd053, 0, 8, 0x50 },
- { 0xd054, 0, 8, 0x46 },
- { 0x9bd7, 0, 8, 0x0a },
- { 0x9bd8, 0, 8, 0x14 },
- { 0x9bd9, 0, 8, 0x08 },
- { 0x9bd0, 0, 8, 0x93 },
- { 0x9be4, 0, 8, 0xfe },
- { 0x9bbd, 0, 8, 0x63 },
- { 0x9be2, 0, 8, 0xfe },
- { 0x9bee, 0, 1, 0x01 },
-};
-
-/* Quantek QT1010 tuner init
- AF9013_TUNER_QT1010 = 134
- AF9013_TUNER_QT1010A = 162 */
-static const struct af9013_reg_bit tuner_init_qt1010[] = {
- { 0x9bd5, 0, 8, 0x01 },
- { 0x9bd6, 0, 8, 0x09 },
- { 0xd1a0, 1, 1, 0x01 },
- { 0xd000, 0, 1, 0x01 },
- { 0xd000, 1, 1, 0x00 },
- { 0xd001, 1, 1, 0x01 },
- { 0xd001, 0, 1, 0x00 },
- { 0xd001, 5, 1, 0x00 },
- { 0xd002, 0, 5, 0x19 },
- { 0xd003, 0, 5, 0x1a },
- { 0xd004, 0, 5, 0x19 },
- { 0xd005, 0, 5, 0x1a },
- { 0xd00e, 0, 5, 0x10 },
- { 0xd00f, 0, 3, 0x04 },
- { 0xd00f, 3, 3, 0x05 },
- { 0xd010, 0, 3, 0x04 },
- { 0xd010, 3, 3, 0x05 },
- { 0xd016, 4, 4, 0x03 },
- { 0xd01f, 0, 6, 0x0a },
- { 0xd020, 0, 6, 0x0a },
- { 0x9bda, 0, 8, 0x01 },
- { 0x9be3, 0, 8, 0x01 },
- { 0xd015, 0, 8, 0x46 },
- { 0xd016, 0, 1, 0x00 },
- { 0xd044, 0, 8, 0x46 },
- { 0xd045, 0, 1, 0x00 },
- { 0x9bbe, 0, 1, 0x01 },
- { 0x9bcc, 0, 1, 0x01 },
- { 0x9bb9, 0, 8, 0x00 },
- { 0x9bcd, 0, 8, 0x28 },
- { 0x9bff, 0, 8, 0x20 },
- { 0xd008, 0, 8, 0x0f },
- { 0xd009, 0, 2, 0x02 },
- { 0xd006, 0, 8, 0x99 },
- { 0xd007, 0, 2, 0x01 },
- { 0xd00c, 0, 8, 0x0f },
- { 0xd00d, 0, 2, 0x02 },
- { 0xd00a, 0, 8, 0x50 },
- { 0xd00b, 0, 2, 0x01 },
- { 0x9bc7, 0, 8, 0x00 },
- { 0x9bc8, 0, 8, 0x00 },
- { 0x9bc3, 0, 8, 0x0f },
- { 0x9bc4, 0, 8, 0x02 },
- { 0x9bc5, 0, 8, 0x0f },
- { 0x9bc6, 0, 8, 0x02 },
- { 0x9bba, 0, 8, 0xc5 },
- { 0x9bc9, 0, 8, 0xff },
- { 0xd011, 0, 8, 0x58 },
- { 0xd012, 0, 2, 0x02 },
- { 0xd013, 0, 8, 0x89 },
- { 0xd014, 0, 2, 0x01 },
- { 0xd040, 0, 8, 0x58 },
- { 0xd041, 0, 2, 0x02 },
- { 0xd042, 0, 8, 0x89 },
- { 0xd043, 0, 2, 0x01 },
- { 0xd045, 1, 1, 0x00 },
- { 0x9bcf, 0, 1, 0x01 },
- { 0xd045, 2, 1, 0x01 },
- { 0xd04f, 0, 8, 0x9a },
- { 0xd050, 0, 1, 0x01 },
- { 0xd051, 0, 8, 0x5a },
- { 0xd052, 0, 1, 0x01 },
- { 0xd053, 0, 8, 0x50 },
- { 0xd054, 0, 8, 0x46 },
- { 0x9bd7, 0, 8, 0x0a },
- { 0x9bd8, 0, 8, 0x14 },
- { 0x9bd9, 0, 8, 0x08 },
- { 0x9bd0, 0, 8, 0xcd },
- { 0x9be4, 0, 8, 0xbb },
- { 0x9bbd, 0, 8, 0x93 },
- { 0x9be2, 0, 8, 0x80 },
- { 0x9bee, 0, 1, 0x01 },
-};
-
-/* Freescale MC44S803 tuner init
- AF9013_TUNER_MC44S803 = 133 */
-static const struct af9013_reg_bit tuner_init_mc44s803[] = {
- { 0x9bd5, 0, 8, 0x01 },
- { 0x9bd6, 0, 8, 0x06 },
- { 0xd1a0, 1, 1, 0x01 },
- { 0xd000, 0, 1, 0x01 },
- { 0xd000, 1, 1, 0x00 },
- { 0xd001, 1, 1, 0x01 },
- { 0xd001, 0, 1, 0x00 },
- { 0xd001, 5, 1, 0x00 },
- { 0xd002, 0, 5, 0x19 },
- { 0xd003, 0, 5, 0x1a },
- { 0xd004, 0, 5, 0x19 },
- { 0xd005, 0, 5, 0x1a },
- { 0xd00e, 0, 5, 0x10 },
- { 0xd00f, 0, 3, 0x04 },
- { 0xd00f, 3, 3, 0x05 },
- { 0xd010, 0, 3, 0x04 },
- { 0xd010, 3, 3, 0x05 },
- { 0xd016, 4, 4, 0x03 },
- { 0xd01f, 0, 6, 0x0a },
- { 0xd020, 0, 6, 0x0a },
- { 0x9bda, 0, 8, 0x00 },
- { 0x9be3, 0, 8, 0x00 },
- { 0x9bf6, 0, 8, 0x01 },
- { 0x9bf8, 0, 8, 0x02 },
- { 0x9bf9, 0, 8, 0x02 },
- { 0x9bfc, 0, 8, 0x1f },
- { 0x9bbe, 0, 1, 0x01 },
- { 0x9bcc, 0, 1, 0x01 },
- { 0x9bb9, 0, 8, 0x00 },
- { 0x9bcd, 0, 8, 0x24 },
- { 0x9bff, 0, 8, 0x24 },
- { 0xd015, 0, 8, 0x46 },
- { 0xd016, 0, 1, 0x00 },
- { 0xd044, 0, 8, 0x46 },
- { 0xd045, 0, 1, 0x00 },
- { 0xd008, 0, 8, 0x01 },
- { 0xd009, 0, 2, 0x02 },
- { 0xd006, 0, 8, 0x7b },
- { 0xd007, 0, 2, 0x00 },
- { 0xd00c, 0, 8, 0x7c },
- { 0xd00d, 0, 2, 0x02 },
- { 0xd00a, 0, 8, 0xfe },
- { 0xd00b, 0, 2, 0x01 },
- { 0x9bc7, 0, 8, 0x08 },
- { 0x9bc8, 0, 8, 0x9a },
- { 0x9bc3, 0, 8, 0x01 },
- { 0x9bc4, 0, 8, 0x02 },
- { 0x9bc5, 0, 8, 0x7c },
- { 0x9bc6, 0, 8, 0x02 },
- { 0x9bba, 0, 8, 0xfc },
- { 0x9bc9, 0, 8, 0xaa },
- { 0xd011, 0, 8, 0x6b },
- { 0xd012, 0, 2, 0x00 },
- { 0xd013, 0, 8, 0x88 },
- { 0xd014, 0, 2, 0x02 },
- { 0xd040, 0, 8, 0x6b },
- { 0xd041, 0, 2, 0x00 },
- { 0xd042, 0, 8, 0x7c },
- { 0xd043, 0, 2, 0x02 },
- { 0xd045, 1, 1, 0x00 },
- { 0x9bcf, 0, 1, 0x01 },
- { 0xd045, 2, 1, 0x01 },
- { 0xd04f, 0, 8, 0x9a },
- { 0xd050, 0, 1, 0x01 },
- { 0xd051, 0, 8, 0x5a },
- { 0xd052, 0, 1, 0x01 },
- { 0xd053, 0, 8, 0x50 },
- { 0xd054, 0, 8, 0x46 },
- { 0x9bd7, 0, 8, 0x0a },
- { 0x9bd8, 0, 8, 0x14 },
- { 0x9bd9, 0, 8, 0x08 },
- { 0x9bd0, 0, 8, 0x9e },
- { 0x9be4, 0, 8, 0xff },
- { 0x9bbd, 0, 8, 0x9e },
- { 0x9be2, 0, 8, 0x25 },
- { 0x9bee, 0, 1, 0x01 },
- { 0xd73b, 3, 1, 0x00 },
-};
-
-/* unknown, probably for tin can tuner, tuner init
- AF9013_TUNER_UNKNOWN = 140 */
-static const struct af9013_reg_bit tuner_init_unknown[] = {
- { 0x9bd5, 0, 8, 0x01 },
- { 0x9bd6, 0, 8, 0x02 },
- { 0xd1a0, 1, 1, 0x01 },
- { 0xd000, 0, 1, 0x01 },
- { 0xd000, 1, 1, 0x00 },
- { 0xd001, 1, 1, 0x01 },
- { 0xd001, 0, 1, 0x00 },
- { 0xd001, 5, 1, 0x00 },
- { 0xd002, 0, 5, 0x19 },
- { 0xd003, 0, 5, 0x1a },
- { 0xd004, 0, 5, 0x19 },
- { 0xd005, 0, 5, 0x1a },
- { 0xd00e, 0, 5, 0x10 },
- { 0xd00f, 0, 3, 0x04 },
- { 0xd00f, 3, 3, 0x05 },
- { 0xd010, 0, 3, 0x04 },
- { 0xd010, 3, 3, 0x05 },
- { 0xd016, 4, 4, 0x03 },
- { 0xd01f, 0, 6, 0x0a },
- { 0xd020, 0, 6, 0x0a },
- { 0x9bda, 0, 8, 0x01 },
- { 0x9be3, 0, 8, 0x01 },
- { 0xd1a0, 1, 1, 0x00 },
- { 0x9bbe, 0, 1, 0x01 },
- { 0x9bcc, 0, 1, 0x01 },
- { 0x9bb9, 0, 8, 0x00 },
- { 0x9bcd, 0, 8, 0x18 },
- { 0x9bff, 0, 8, 0x2c },
- { 0xd015, 0, 8, 0x46 },
- { 0xd016, 0, 1, 0x00 },
- { 0xd044, 0, 8, 0x46 },
- { 0xd045, 0, 1, 0x00 },
- { 0xd008, 0, 8, 0xdf },
- { 0xd009, 0, 2, 0x02 },
- { 0xd006, 0, 8, 0x44 },
- { 0xd007, 0, 2, 0x01 },
- { 0xd00c, 0, 8, 0x00 },
- { 0xd00d, 0, 2, 0x02 },
- { 0xd00a, 0, 8, 0xf6 },
- { 0xd00b, 0, 2, 0x01 },
- { 0x9bba, 0, 8, 0xf9 },
- { 0x9bc8, 0, 8, 0xaa },
- { 0x9bc3, 0, 8, 0xdf },
- { 0x9bc4, 0, 8, 0x02 },
- { 0x9bc5, 0, 8, 0x00 },
- { 0x9bc6, 0, 8, 0x02 },
- { 0x9bc9, 0, 8, 0xf0 },
- { 0xd011, 0, 8, 0x3c },
- { 0xd012, 0, 2, 0x01 },
- { 0xd013, 0, 8, 0xf7 },
- { 0xd014, 0, 2, 0x02 },
- { 0xd040, 0, 8, 0x0b },
- { 0xd041, 0, 2, 0x02 },
- { 0xd042, 0, 8, 0x4d },
- { 0xd043, 0, 2, 0x00 },
- { 0xd045, 1, 1, 0x00 },
- { 0x9bcf, 0, 1, 0x01 },
- { 0xd045, 2, 1, 0x01 },
- { 0xd04f, 0, 8, 0x9a },
- { 0xd050, 0, 1, 0x01 },
- { 0xd051, 0, 8, 0x5a },
- { 0xd052, 0, 1, 0x01 },
- { 0xd053, 0, 8, 0x50 },
- { 0xd054, 0, 8, 0x46 },
- { 0x9bd7, 0, 8, 0x0a },
- { 0x9bd8, 0, 8, 0x14 },
- { 0x9bd9, 0, 8, 0x08 },
-};
-
-/* NXP TDA18271 & TDA18218 tuner init
- AF9013_TUNER_TDA18271 = 156
- AF9013_TUNER_TDA18218 = 179 */
-static const struct af9013_reg_bit tuner_init_tda18271[] = {
- { 0x9bd5, 0, 8, 0x01 },
- { 0x9bd6, 0, 8, 0x04 },
- { 0xd1a0, 1, 1, 0x01 },
- { 0xd000, 0, 1, 0x01 },
- { 0xd000, 1, 1, 0x00 },
- { 0xd001, 1, 1, 0x01 },
- { 0xd001, 0, 1, 0x00 },
- { 0xd001, 5, 1, 0x00 },
- { 0xd002, 0, 5, 0x19 },
- { 0xd003, 0, 5, 0x1a },
- { 0xd004, 0, 5, 0x19 },
- { 0xd005, 0, 5, 0x1a },
- { 0xd00e, 0, 5, 0x10 },
- { 0xd00f, 0, 3, 0x04 },
- { 0xd00f, 3, 3, 0x05 },
- { 0xd010, 0, 3, 0x04 },
- { 0xd010, 3, 3, 0x05 },
- { 0xd016, 4, 4, 0x03 },
- { 0xd01f, 0, 6, 0x0a },
- { 0xd020, 0, 6, 0x0a },
- { 0x9bda, 0, 8, 0x01 },
- { 0x9be3, 0, 8, 0x01 },
- { 0xd1a0, 1, 1, 0x00 },
- { 0x9bbe, 0, 1, 0x01 },
- { 0x9bcc, 0, 1, 0x01 },
- { 0x9bb9, 0, 8, 0x00 },
- { 0x9bcd, 0, 8, 0x18 },
- { 0x9bff, 0, 8, 0x2c },
- { 0xd015, 0, 8, 0x46 },
- { 0xd016, 0, 1, 0x00 },
- { 0xd044, 0, 8, 0x46 },
- { 0xd045, 0, 1, 0x00 },
- { 0xd008, 0, 8, 0xdf },
- { 0xd009, 0, 2, 0x02 },
- { 0xd006, 0, 8, 0x44 },
- { 0xd007, 0, 2, 0x01 },
- { 0xd00c, 0, 8, 0x00 },
- { 0xd00d, 0, 2, 0x02 },
- { 0xd00a, 0, 8, 0xf6 },
- { 0xd00b, 0, 2, 0x01 },
- { 0x9bba, 0, 8, 0xf9 },
- { 0x9bc8, 0, 8, 0xaa },
- { 0x9bc3, 0, 8, 0xdf },
- { 0x9bc4, 0, 8, 0x02 },
- { 0x9bc5, 0, 8, 0x00 },
- { 0x9bc6, 0, 8, 0x02 },
- { 0x9bc9, 0, 8, 0xf0 },
- { 0xd011, 0, 8, 0x3c },
- { 0xd012, 0, 2, 0x01 },
- { 0xd013, 0, 8, 0xf7 },
- { 0xd014, 0, 2, 0x02 },
- { 0xd040, 0, 8, 0x0b },
- { 0xd041, 0, 2, 0x02 },
- { 0xd042, 0, 8, 0x4d },
- { 0xd043, 0, 2, 0x00 },
- { 0xd045, 1, 1, 0x00 },
- { 0x9bcf, 0, 1, 0x01 },
- { 0xd045, 2, 1, 0x01 },
- { 0xd04f, 0, 8, 0x9a },
- { 0xd050, 0, 1, 0x01 },
- { 0xd051, 0, 8, 0x5a },
- { 0xd052, 0, 1, 0x01 },
- { 0xd053, 0, 8, 0x50 },
- { 0xd054, 0, 8, 0x46 },
- { 0x9bd7, 0, 8, 0x0a },
- { 0x9bd8, 0, 8, 0x14 },
- { 0x9bd9, 0, 8, 0x08 },
- { 0x9bd0, 0, 8, 0xa8 },
- { 0x9be4, 0, 8, 0x7f },
- { 0x9bbd, 0, 8, 0xa8 },
- { 0x9be2, 0, 8, 0x20 },
- { 0x9bee, 0, 1, 0x01 },
-};
-
-#endif /* AF9013_PRIV_H */
diff --git a/drivers/media/dvb/frontends/af9033.c b/drivers/media/dvb/frontends/af9033.c
deleted file mode 100644
index a3899828626..00000000000
--- a/drivers/media/dvb/frontends/af9033.c
+++ /dev/null
@@ -1,980 +0,0 @@
-/*
- * Afatech AF9033 demodulator driver
- *
- * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
- * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include "af9033_priv.h"
-
-struct af9033_state {
- struct i2c_adapter *i2c;
- struct dvb_frontend fe;
- struct af9033_config cfg;
-
- u32 bandwidth_hz;
- bool ts_mode_parallel;
- bool ts_mode_serial;
-
- u32 ber;
- u32 ucb;
- unsigned long last_stat_check;
-};
-
-/* write multiple registers */
-static int af9033_wr_regs(struct af9033_state *state, u32 reg, const u8 *val,
- int len)
-{
- int ret;
- u8 buf[3 + len];
- struct i2c_msg msg[1] = {
- {
- .addr = state->cfg.i2c_addr,
- .flags = 0,
- .len = sizeof(buf),
- .buf = buf,
- }
- };
-
- buf[0] = (reg >> 16) & 0xff;
- buf[1] = (reg >> 8) & 0xff;
- buf[2] = (reg >> 0) & 0xff;
- memcpy(&buf[3], val, len);
-
- ret = i2c_transfer(state->i2c, msg, 1);
- if (ret == 1) {
- ret = 0;
- } else {
- printk(KERN_WARNING "%s: i2c wr failed=%d reg=%06x len=%d\n",
- __func__, ret, reg, len);
- ret = -EREMOTEIO;
- }
-
- return ret;
-}
-
-/* read multiple registers */
-static int af9033_rd_regs(struct af9033_state *state, u32 reg, u8 *val, int len)
-{
- int ret;
- u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff,
- (reg >> 0) & 0xff };
- struct i2c_msg msg[2] = {
- {
- .addr = state->cfg.i2c_addr,
- .flags = 0,
- .len = sizeof(buf),
- .buf = buf
- }, {
- .addr = state->cfg.i2c_addr,
- .flags = I2C_M_RD,
- .len = len,
- .buf = val
- }
- };
-
- ret = i2c_transfer(state->i2c, msg, 2);
- if (ret == 2) {
- ret = 0;
- } else {
- printk(KERN_WARNING "%s: i2c rd failed=%d reg=%06x len=%d\n",
- __func__, ret, reg, len);
- ret = -EREMOTEIO;
- }
-
- return ret;
-}
-
-
-/* write single register */
-static int af9033_wr_reg(struct af9033_state *state, u32 reg, u8 val)
-{
- return af9033_wr_regs(state, reg, &val, 1);
-}
-
-/* read single register */
-static int af9033_rd_reg(struct af9033_state *state, u32 reg, u8 *val)
-{
- return af9033_rd_regs(state, reg, val, 1);
-}
-
-/* write single register with mask */
-static int af9033_wr_reg_mask(struct af9033_state *state, u32 reg, u8 val,
- u8 mask)
-{
- int ret;
- u8 tmp;
-
- /* no need for read if whole reg is written */
- if (mask != 0xff) {
- ret = af9033_rd_regs(state, reg, &tmp, 1);
- if (ret)
- return ret;
-
- val &= mask;
- tmp &= ~mask;
- val |= tmp;
- }
-
- return af9033_wr_regs(state, reg, &val, 1);
-}
-
-/* read single register with mask */
-static int af9033_rd_reg_mask(struct af9033_state *state, u32 reg, u8 *val,
- u8 mask)
-{
- int ret, i;
- u8 tmp;
-
- ret = af9033_rd_regs(state, reg, &tmp, 1);
- if (ret)
- return ret;
-
- tmp &= mask;
-
- /* find position of the first bit */
- for (i = 0; i < 8; i++) {
- if ((mask >> i) & 0x01)
- break;
- }
- *val = tmp >> i;
-
- return 0;
-}
-
-static u32 af9033_div(u32 a, u32 b, u32 x)
-{
- u32 r = 0, c = 0, i;
-
- pr_debug("%s: a=%d b=%d x=%d\n", __func__, a, b, x);
-
- if (a > b) {
- c = a / b;
- a = a - c * b;
- }
-
- for (i = 0; i < x; i++) {
- if (a >= b) {
- r += 1;
- a -= b;
- }
- a <<= 1;
- r <<= 1;
- }
- r = (c << (u32)x) + r;
-
- pr_debug("%s: a=%d b=%d x=%d r=%d r=%x\n", __func__, a, b, x, r, r);
-
- return r;
-}
-
-static void af9033_release(struct dvb_frontend *fe)
-{
- struct af9033_state *state = fe->demodulator_priv;
-
- kfree(state);
-}
-
-static int af9033_init(struct dvb_frontend *fe)
-{
- struct af9033_state *state = fe->demodulator_priv;
- int ret, i, len;
- const struct reg_val *init;
- u8 buf[4];
- u32 adc_cw, clock_cw;
- struct reg_val_mask tab[] = {
- { 0x80fb24, 0x00, 0x08 },
- { 0x80004c, 0x00, 0xff },
- { 0x00f641, state->cfg.tuner, 0xff },
- { 0x80f5ca, 0x01, 0x01 },
- { 0x80f715, 0x01, 0x01 },
- { 0x00f41f, 0x04, 0x04 },
- { 0x00f41a, 0x01, 0x01 },
- { 0x80f731, 0x00, 0x01 },
- { 0x00d91e, 0x00, 0x01 },
- { 0x00d919, 0x00, 0x01 },
- { 0x80f732, 0x00, 0x01 },
- { 0x00d91f, 0x00, 0x01 },
- { 0x00d91a, 0x00, 0x01 },
- { 0x80f730, 0x00, 0x01 },
- { 0x80f778, 0x00, 0xff },
- { 0x80f73c, 0x01, 0x01 },
- { 0x80f776, 0x00, 0x01 },
- { 0x00d8fd, 0x01, 0xff },
- { 0x00d830, 0x01, 0xff },
- { 0x00d831, 0x00, 0xff },
- { 0x00d832, 0x00, 0xff },
- { 0x80f985, state->ts_mode_serial, 0x01 },
- { 0x80f986, state->ts_mode_parallel, 0x01 },
- { 0x00d827, 0x00, 0xff },
- { 0x00d829, 0x00, 0xff },
- };
-
- /* program clock control */
- clock_cw = af9033_div(state->cfg.clock, 1000000ul, 19ul);
- buf[0] = (clock_cw >> 0) & 0xff;
- buf[1] = (clock_cw >> 8) & 0xff;
- buf[2] = (clock_cw >> 16) & 0xff;
- buf[3] = (clock_cw >> 24) & 0xff;
-
- pr_debug("%s: clock=%d clock_cw=%08x\n", __func__, state->cfg.clock,
- clock_cw);
-
- ret = af9033_wr_regs(state, 0x800025, buf, 4);
- if (ret < 0)
- goto err;
-
- /* program ADC control */
- for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
- if (clock_adc_lut[i].clock == state->cfg.clock)
- break;
- }
-
- adc_cw = af9033_div(clock_adc_lut[i].adc, 1000000ul, 19ul);
- buf[0] = (adc_cw >> 0) & 0xff;
- buf[1] = (adc_cw >> 8) & 0xff;
- buf[2] = (adc_cw >> 16) & 0xff;
-
- pr_debug("%s: adc=%d adc_cw=%06x\n", __func__, clock_adc_lut[i].adc,
- adc_cw);
-
- ret = af9033_wr_regs(state, 0x80f1cd, buf, 3);
- if (ret < 0)
- goto err;
-
- /* program register table */
- for (i = 0; i < ARRAY_SIZE(tab); i++) {
- ret = af9033_wr_reg_mask(state, tab[i].reg, tab[i].val,
- tab[i].mask);
- if (ret < 0)
- goto err;
- }
-
- /* settings for TS interface */
- if (state->cfg.ts_mode == AF9033_TS_MODE_USB) {
- ret = af9033_wr_reg_mask(state, 0x80f9a5, 0x00, 0x01);
- if (ret < 0)
- goto err;
-
- ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x01, 0x01);
- if (ret < 0)
- goto err;
- } else {
- ret = af9033_wr_reg_mask(state, 0x80f990, 0x00, 0x01);
- if (ret < 0)
- goto err;
-
- ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x00, 0x01);
- if (ret < 0)
- goto err;
- }
-
- /* load OFSM settings */
- pr_debug("%s: load ofsm settings\n", __func__);
- len = ARRAY_SIZE(ofsm_init);
- init = ofsm_init;
- for (i = 0; i < len; i++) {
- ret = af9033_wr_reg(state, init[i].reg, init[i].val);
- if (ret < 0)
- goto err;
- }
-
- /* load tuner specific settings */
- pr_debug("%s: load tuner specific settings\n",
- __func__);
- switch (state->cfg.tuner) {
- case AF9033_TUNER_TUA9001:
- len = ARRAY_SIZE(tuner_init_tua9001);
- init = tuner_init_tua9001;
- break;
- case AF9033_TUNER_FC0011:
- len = ARRAY_SIZE(tuner_init_fc0011);
- init = tuner_init_fc0011;
- break;
- case AF9033_TUNER_MXL5007T:
- len = ARRAY_SIZE(tuner_init_mxl5007t);
- init = tuner_init_mxl5007t;
- break;
- case AF9033_TUNER_TDA18218:
- len = ARRAY_SIZE(tuner_init_tda18218);
- init = tuner_init_tda18218;
- break;
- default:
- pr_debug("%s: unsupported tuner ID=%d\n", __func__,
- state->cfg.tuner);
- ret = -ENODEV;
- goto err;
- }
-
- for (i = 0; i < len; i++) {
- ret = af9033_wr_reg(state, init[i].reg, init[i].val);
- if (ret < 0)
- goto err;
- }
-
- state->bandwidth_hz = 0; /* force to program all parameters */
-
- return 0;
-
-err:
- pr_debug("%s: failed=%d\n", __func__, ret);
-
- return ret;
-}
-
-static int af9033_sleep(struct dvb_frontend *fe)
-{
- struct af9033_state *state = fe->demodulator_priv;
- int ret, i;
- u8 tmp;
-
- ret = af9033_wr_reg(state, 0x80004c, 1);
- if (ret < 0)
- goto err;
-
- ret = af9033_wr_reg(state, 0x800000, 0);
- if (ret < 0)
- goto err;
-
- for (i = 100, tmp = 1; i && tmp; i--) {
- ret = af9033_rd_reg(state, 0x80004c, &tmp);
- if (ret < 0)
- goto err;
-
- usleep_range(200, 10000);
- }
-
- pr_debug("%s: loop=%d\n", __func__, i);
-
- if (i == 0) {
- ret = -ETIMEDOUT;
- goto err;
- }
-
- ret = af9033_wr_reg_mask(state, 0x80fb24, 0x08, 0x08);
- if (ret < 0)
- goto err;
-
- /* prevent current leak (?) */
- if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
- /* enable parallel TS */
- ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01);
- if (ret < 0)
- goto err;
-
- ret = af9033_wr_reg_mask(state, 0x00d916, 0x01, 0x01);
- if (ret < 0)
- goto err;
- }
-
- return 0;
-
-err:
- pr_debug("%s: failed=%d\n", __func__, ret);
-
- return ret;
-}
-
-static int af9033_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *fesettings)
-{
- fesettings->min_delay_ms = 800;
- fesettings->step_size = 0;
- fesettings->max_drift = 0;
-
- return 0;
-}
-
-static int af9033_set_frontend(struct dvb_frontend *fe)
-{
- struct af9033_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret, i, spec_inv;
- u8 tmp, buf[3], bandwidth_reg_val;
- u32 if_frequency, freq_cw, adc_freq;
-
- pr_debug("%s: frequency=%d bandwidth_hz=%d\n", __func__, c->frequency,
- c->bandwidth_hz);
-
- /* check bandwidth */
- switch (c->bandwidth_hz) {
- case 6000000:
- bandwidth_reg_val = 0x00;
- break;
- case 7000000:
- bandwidth_reg_val = 0x01;
- break;
- case 8000000:
- bandwidth_reg_val = 0x02;
- break;
- default:
- pr_debug("%s: invalid bandwidth_hz\n", __func__);
- ret = -EINVAL;
- goto err;
- }
-
- /* program tuner */
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
-
- /* program CFOE coefficients */
- if (c->bandwidth_hz != state->bandwidth_hz) {
- for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
- if (coeff_lut[i].clock == state->cfg.clock &&
- coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
- break;
- }
- }
- ret = af9033_wr_regs(state, 0x800001,
- coeff_lut[i].val, sizeof(coeff_lut[i].val));
- }
-
- /* program frequency control */
- if (c->bandwidth_hz != state->bandwidth_hz) {
- spec_inv = state->cfg.spec_inv ? -1 : 1;
-
- for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
- if (clock_adc_lut[i].clock == state->cfg.clock)
- break;
- }
- adc_freq = clock_adc_lut[i].adc;
-
- /* get used IF frequency */
- if (fe->ops.tuner_ops.get_if_frequency)
- fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
- else
- if_frequency = 0;
-
- while (if_frequency > (adc_freq / 2))
- if_frequency -= adc_freq;
-
- if (if_frequency >= 0)
- spec_inv *= -1;
- else
- if_frequency *= -1;
-
- freq_cw = af9033_div(if_frequency, adc_freq, 23ul);
-
- if (spec_inv == -1)
- freq_cw *= -1;
-
- /* get adc multiplies */
- ret = af9033_rd_reg(state, 0x800045, &tmp);
- if (ret < 0)
- goto err;
-
- if (tmp == 1)
- freq_cw /= 2;
-
- buf[0] = (freq_cw >> 0) & 0xff;
- buf[1] = (freq_cw >> 8) & 0xff;
- buf[2] = (freq_cw >> 16) & 0x7f;
- ret = af9033_wr_regs(state, 0x800029, buf, 3);
- if (ret < 0)
- goto err;
-
- state->bandwidth_hz = c->bandwidth_hz;
- }
-
- ret = af9033_wr_reg_mask(state, 0x80f904, bandwidth_reg_val, 0x03);
- if (ret < 0)
- goto err;
-
- ret = af9033_wr_reg(state, 0x800040, 0x00);
- if (ret < 0)
- goto err;
-
- ret = af9033_wr_reg(state, 0x800047, 0x00);
- if (ret < 0)
- goto err;
-
- ret = af9033_wr_reg_mask(state, 0x80f999, 0x00, 0x01);
- if (ret < 0)
- goto err;
-
- if (c->frequency <= 230000000)
- tmp = 0x00; /* VHF */
- else
- tmp = 0x01; /* UHF */
-
- ret = af9033_wr_reg(state, 0x80004b, tmp);
- if (ret < 0)
- goto err;
-
- ret = af9033_wr_reg(state, 0x800000, 0x00);
- if (ret < 0)
- goto err;
-
- return 0;
-
-err:
- pr_debug("%s: failed=%d\n", __func__, ret);
-
- return ret;
-}
-
-static int af9033_get_frontend(struct dvb_frontend *fe)
-{
- struct af9033_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret;
- u8 buf[8];
-
- pr_debug("%s\n", __func__);
-
- /* read all needed registers */
- ret = af9033_rd_regs(state, 0x80f900, buf, sizeof(buf));
- if (ret < 0)
- goto err;
-
- switch ((buf[0] >> 0) & 3) {
- case 0:
- c->transmission_mode = TRANSMISSION_MODE_2K;
- break;
- case 1:
- c->transmission_mode = TRANSMISSION_MODE_8K;
- break;
- }
-
- switch ((buf[1] >> 0) & 3) {
- case 0:
- c->guard_interval = GUARD_INTERVAL_1_32;
- break;
- case 1:
- c->guard_interval = GUARD_INTERVAL_1_16;
- break;
- case 2:
- c->guard_interval = GUARD_INTERVAL_1_8;
- break;
- case 3:
- c->guard_interval = GUARD_INTERVAL_1_4;
- break;
- }
-
- switch ((buf[2] >> 0) & 7) {
- case 0:
- c->hierarchy = HIERARCHY_NONE;
- break;
- case 1:
- c->hierarchy = HIERARCHY_1;
- break;
- case 2:
- c->hierarchy = HIERARCHY_2;
- break;
- case 3:
- c->hierarchy = HIERARCHY_4;
- break;
- }
-
- switch ((buf[3] >> 0) & 3) {
- case 0:
- c->modulation = QPSK;
- break;
- case 1:
- c->modulation = QAM_16;
- break;
- case 2:
- c->modulation = QAM_64;
- break;
- }
-
- switch ((buf[4] >> 0) & 3) {
- case 0:
- c->bandwidth_hz = 6000000;
- break;
- case 1:
- c->bandwidth_hz = 7000000;
- break;
- case 2:
- c->bandwidth_hz = 8000000;
- break;
- }
-
- switch ((buf[6] >> 0) & 7) {
- case 0:
- c->code_rate_HP = FEC_1_2;
- break;
- case 1:
- c->code_rate_HP = FEC_2_3;
- break;
- case 2:
- c->code_rate_HP = FEC_3_4;
- break;
- case 3:
- c->code_rate_HP = FEC_5_6;
- break;
- case 4:
- c->code_rate_HP = FEC_7_8;
- break;
- case 5:
- c->code_rate_HP = FEC_NONE;
- break;
- }
-
- switch ((buf[7] >> 0) & 7) {
- case 0:
- c->code_rate_LP = FEC_1_2;
- break;
- case 1:
- c->code_rate_LP = FEC_2_3;
- break;
- case 2:
- c->code_rate_LP = FEC_3_4;
- break;
- case 3:
- c->code_rate_LP = FEC_5_6;
- break;
- case 4:
- c->code_rate_LP = FEC_7_8;
- break;
- case 5:
- c->code_rate_LP = FEC_NONE;
- break;
- }
-
- return 0;
-
-err:
- pr_debug("%s: failed=%d\n", __func__, ret);
-
- return ret;
-}
-
-static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct af9033_state *state = fe->demodulator_priv;
- int ret;
- u8 tmp;
-
- *status = 0;
-
- /* radio channel status, 0=no result, 1=has signal, 2=no signal */
- ret = af9033_rd_reg(state, 0x800047, &tmp);
- if (ret < 0)
- goto err;
-
- /* has signal */
- if (tmp == 0x01)
- *status |= FE_HAS_SIGNAL;
-
- if (tmp != 0x02) {
- /* TPS lock */
- ret = af9033_rd_reg_mask(state, 0x80f5a9, &tmp, 0x01);
- if (ret < 0)
- goto err;
-
- if (tmp)
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI;
-
- /* full lock */
- ret = af9033_rd_reg_mask(state, 0x80f999, &tmp, 0x01);
- if (ret < 0)
- goto err;
-
- if (tmp)
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC |
- FE_HAS_LOCK;
- }
-
- return 0;
-
-err:
- pr_debug("%s: failed=%d\n", __func__, ret);
-
- return ret;
-}
-
-static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- struct af9033_state *state = fe->demodulator_priv;
- int ret, i, len;
- u8 buf[3], tmp;
- u32 snr_val;
- const struct val_snr *uninitialized_var(snr_lut);
-
- /* read value */
- ret = af9033_rd_regs(state, 0x80002c, buf, 3);
- if (ret < 0)
- goto err;
-
- snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0];
-
- /* read current modulation */
- ret = af9033_rd_reg(state, 0x80f903, &tmp);
- if (ret < 0)
- goto err;
-
- switch ((tmp >> 0) & 3) {
- case 0:
- len = ARRAY_SIZE(qpsk_snr_lut);
- snr_lut = qpsk_snr_lut;
- break;
- case 1:
- len = ARRAY_SIZE(qam16_snr_lut);
- snr_lut = qam16_snr_lut;
- break;
- case 2:
- len = ARRAY_SIZE(qam64_snr_lut);
- snr_lut = qam64_snr_lut;
- break;
- default:
- goto err;
- }
-
- for (i = 0; i < len; i++) {
- tmp = snr_lut[i].snr;
-
- if (snr_val < snr_lut[i].val)
- break;
- }
-
- *snr = tmp * 10; /* dB/10 */
-
- return 0;
-
-err:
- pr_debug("%s: failed=%d\n", __func__, ret);
-
- return ret;
-}
-
-static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
-{
- struct af9033_state *state = fe->demodulator_priv;
- int ret;
- u8 strength2;
-
- /* read signal strength of 0-100 scale */
- ret = af9033_rd_reg(state, 0x800048, &strength2);
- if (ret < 0)
- goto err;
-
- /* scale value to 0x0000-0xffff */
- *strength = strength2 * 0xffff / 100;
-
- return 0;
-
-err:
- pr_debug("%s: failed=%d\n", __func__, ret);
-
- return ret;
-}
-
-static int af9033_update_ch_stat(struct af9033_state *state)
-{
- int ret = 0;
- u32 err_cnt, bit_cnt;
- u16 abort_cnt;
- u8 buf[7];
-
- /* only update data every half second */
- if (time_after(jiffies, state->last_stat_check + msecs_to_jiffies(500))) {
- ret = af9033_rd_regs(state, 0x800032, buf, sizeof(buf));
- if (ret < 0)
- goto err;
- /* in 8 byte packets? */
- abort_cnt = (buf[1] << 8) + buf[0];
- /* in bits */
- err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2];
- /* in 8 byte packets? always(?) 0x2710 = 10000 */
- bit_cnt = (buf[6] << 8) + buf[5];
-
- if (bit_cnt < abort_cnt) {
- abort_cnt = 1000;
- state->ber = 0xffffffff;
- } else {
- /* 8 byte packets, that have not been rejected already */
- bit_cnt -= (u32)abort_cnt;
- if (bit_cnt == 0) {
- state->ber = 0xffffffff;
- } else {
- err_cnt -= (u32)abort_cnt * 8 * 8;
- bit_cnt *= 8 * 8;
- state->ber = err_cnt * (0xffffffff / bit_cnt);
- }
- }
- state->ucb += abort_cnt;
- state->last_stat_check = jiffies;
- }
-
- return 0;
-err:
- pr_debug("%s: failed=%d\n", __func__, ret);
- return ret;
-}
-
-static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct af9033_state *state = fe->demodulator_priv;
- int ret;
-
- ret = af9033_update_ch_stat(state);
- if (ret < 0)
- return ret;
-
- *ber = state->ber;
-
- return 0;
-}
-
-static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- struct af9033_state *state = fe->demodulator_priv;
- int ret;
-
- ret = af9033_update_ch_stat(state);
- if (ret < 0)
- return ret;
-
- *ucblocks = state->ucb;
-
- return 0;
-}
-
-static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- struct af9033_state *state = fe->demodulator_priv;
- int ret;
-
- pr_debug("%s: enable=%d\n", __func__, enable);
-
- ret = af9033_wr_reg_mask(state, 0x00fa04, enable, 0x01);
- if (ret < 0)
- goto err;
-
- return 0;
-
-err:
- pr_debug("%s: failed=%d\n", __func__, ret);
-
- return ret;
-}
-
-static struct dvb_frontend_ops af9033_ops;
-
-struct dvb_frontend *af9033_attach(const struct af9033_config *config,
- struct i2c_adapter *i2c)
-{
- int ret;
- struct af9033_state *state;
- u8 buf[8];
-
- pr_debug("%s:\n", __func__);
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL);
- if (state == NULL)
- goto err;
-
- /* setup the state */
- state->i2c = i2c;
- memcpy(&state->cfg, config, sizeof(struct af9033_config));
-
- if (state->cfg.clock != 12000000) {
- printk(KERN_INFO "af9033: unsupported clock=%d, only " \
- "12000000 Hz is supported currently\n",
- state->cfg.clock);
- goto err;
- }
-
- /* firmware version */
- ret = af9033_rd_regs(state, 0x0083e9, &buf[0], 4);
- if (ret < 0)
- goto err;
-
- ret = af9033_rd_regs(state, 0x804191, &buf[4], 4);
- if (ret < 0)
- goto err;
-
- printk(KERN_INFO "af9033: firmware version: LINK=%d.%d.%d.%d " \
- "OFDM=%d.%d.%d.%d\n", buf[0], buf[1], buf[2], buf[3],
- buf[4], buf[5], buf[6], buf[7]);
-
- /* configure internal TS mode */
- switch (state->cfg.ts_mode) {
- case AF9033_TS_MODE_PARALLEL:
- state->ts_mode_parallel = true;
- break;
- case AF9033_TS_MODE_SERIAL:
- state->ts_mode_serial = true;
- break;
- case AF9033_TS_MODE_USB:
- /* usb mode for AF9035 */
- default:
- break;
- }
-
- /* create dvb_frontend */
- memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops));
- state->fe.demodulator_priv = state;
-
- return &state->fe;
-
-err:
- kfree(state);
- return NULL;
-}
-EXPORT_SYMBOL(af9033_attach);
-
-static struct dvb_frontend_ops af9033_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "Afatech AF9033 (DVB-T)",
- .frequency_min = 174000000,
- .frequency_max = 862000000,
- .frequency_stepsize = 250000,
- .frequency_tolerance = 0,
- .caps = FE_CAN_FEC_1_2 |
- FE_CAN_FEC_2_3 |
- FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 |
- FE_CAN_FEC_7_8 |
- FE_CAN_FEC_AUTO |
- FE_CAN_QPSK |
- FE_CAN_QAM_16 |
- FE_CAN_QAM_64 |
- FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_HIERARCHY_AUTO |
- FE_CAN_RECOVER |
- FE_CAN_MUTE_TS
- },
-
- .release = af9033_release,
-
- .init = af9033_init,
- .sleep = af9033_sleep,
-
- .get_tune_settings = af9033_get_tune_settings,
- .set_frontend = af9033_set_frontend,
- .get_frontend = af9033_get_frontend,
-
- .read_status = af9033_read_status,
- .read_snr = af9033_read_snr,
- .read_signal_strength = af9033_read_signal_strength,
- .read_ber = af9033_read_ber,
- .read_ucblocks = af9033_read_ucblocks,
-
- .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
-};
-
-MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
-MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/af9033.h b/drivers/media/dvb/frontends/af9033.h
deleted file mode 100644
index 9e302c3f0f7..00000000000
--- a/drivers/media/dvb/frontends/af9033.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Afatech AF9033 demodulator driver
- *
- * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
- * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef AF9033_H
-#define AF9033_H
-
-struct af9033_config {
- /*
- * I2C address
- */
- u8 i2c_addr;
-
- /*
- * clock Hz
- * 12000000, 22000000, 24000000, 34000000, 32000000, 28000000, 26000000,
- * 30000000, 36000000, 20480000, 16384000
- */
- u32 clock;
-
- /*
- * tuner
- */
-#define AF9033_TUNER_TUA9001 0x27 /* Infineon TUA 9001 */
-#define AF9033_TUNER_FC0011 0x28 /* Fitipower FC0011 */
-#define AF9033_TUNER_MXL5007T 0xa0 /* MaxLinear MxL5007T */
-#define AF9033_TUNER_TDA18218 0xa1 /* NXP TDA 18218HN */
- u8 tuner;
-
- /*
- * TS settings
- */
-#define AF9033_TS_MODE_USB 0
-#define AF9033_TS_MODE_PARALLEL 1
-#define AF9033_TS_MODE_SERIAL 2
- u8 ts_mode:2;
-
- /*
- * input spectrum inversion
- */
- bool spec_inv;
-};
-
-
-#if defined(CONFIG_DVB_AF9033) || \
- (defined(CONFIG_DVB_AF9033_MODULE) && defined(MODULE))
-extern struct dvb_frontend *af9033_attach(const struct af9033_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline struct dvb_frontend *af9033_attach(
- const struct af9033_config *config, struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif /* AF9033_H */
diff --git a/drivers/media/dvb/frontends/af9033_priv.h b/drivers/media/dvb/frontends/af9033_priv.h
deleted file mode 100644
index 0b783b9ed75..00000000000
--- a/drivers/media/dvb/frontends/af9033_priv.h
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * Afatech AF9033 demodulator driver
- *
- * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
- * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef AF9033_PRIV_H
-#define AF9033_PRIV_H
-
-#include "dvb_frontend.h"
-#include "af9033.h"
-
-struct reg_val {
- u32 reg;
- u8 val;
-};
-
-struct reg_val_mask {
- u32 reg;
- u8 val;
- u8 mask;
-};
-
-struct coeff {
- u32 clock;
- u32 bandwidth_hz;
- u8 val[36];
-};
-
-struct clock_adc {
- u32 clock;
- u32 adc;
-};
-
-struct val_snr {
- u32 val;
- u8 snr;
-};
-
-/* Xtal clock vs. ADC clock lookup table */
-static const struct clock_adc clock_adc_lut[] = {
- { 16384000, 20480000 },
- { 20480000, 20480000 },
- { 36000000, 20250000 },
- { 30000000, 20156250 },
- { 26000000, 20583333 },
- { 28000000, 20416667 },
- { 32000000, 20500000 },
- { 34000000, 20187500 },
- { 24000000, 20500000 },
- { 22000000, 20625000 },
- { 12000000, 20250000 },
-};
-
-/* pre-calculated coeff lookup table */
-static const struct coeff coeff_lut[] = {
- /* 12.000 MHz */
- { 12000000, 8000000, {
- 0x01, 0xce, 0x55, 0xc9, 0x00, 0xe7, 0x2a, 0xe4, 0x00, 0x73,
- 0x99, 0x0f, 0x00, 0x73, 0x95, 0x72, 0x00, 0x73, 0x91, 0xd5,
- 0x00, 0x39, 0xca, 0xb9, 0x00, 0xe7, 0x2a, 0xe4, 0x00, 0x73,
- 0x95, 0x72, 0x37, 0x02, 0xce, 0x01 }
- },
- { 12000000, 7000000, {
- 0x01, 0x94, 0x8b, 0x10, 0x00, 0xca, 0x45, 0x88, 0x00, 0x65,
- 0x25, 0xed, 0x00, 0x65, 0x22, 0xc4, 0x00, 0x65, 0x1f, 0x9b,
- 0x00, 0x32, 0x91, 0x62, 0x00, 0xca, 0x45, 0x88, 0x00, 0x65,
- 0x22, 0xc4, 0x88, 0x02, 0x95, 0x01 }
- },
- { 12000000, 6000000, {
- 0x01, 0x5a, 0xc0, 0x56, 0x00, 0xad, 0x60, 0x2b, 0x00, 0x56,
- 0xb2, 0xcb, 0x00, 0x56, 0xb0, 0x15, 0x00, 0x56, 0xad, 0x60,
- 0x00, 0x2b, 0x58, 0x0b, 0x00, 0xad, 0x60, 0x2b, 0x00, 0x56,
- 0xb0, 0x15, 0xf4, 0x02, 0x5b, 0x01 }
- },
-};
-
-/* QPSK SNR lookup table */
-static const struct val_snr qpsk_snr_lut[] = {
- { 0x0b4771, 0 },
- { 0x0c1aed, 1 },
- { 0x0d0d27, 2 },
- { 0x0e4d19, 3 },
- { 0x0e5da8, 4 },
- { 0x107097, 5 },
- { 0x116975, 6 },
- { 0x1252d9, 7 },
- { 0x131fa4, 8 },
- { 0x13d5e1, 9 },
- { 0x148e53, 10 },
- { 0x15358b, 11 },
- { 0x15dd29, 12 },
- { 0x168112, 13 },
- { 0x170b61, 14 },
- { 0x17a532, 15 },
- { 0x180f94, 16 },
- { 0x186ed2, 17 },
- { 0x18b271, 18 },
- { 0x18e118, 19 },
- { 0x18ff4b, 20 },
- { 0x190af1, 21 },
- { 0x191451, 22 },
- { 0xffffff, 23 },
-};
-
-/* QAM16 SNR lookup table */
-static const struct val_snr qam16_snr_lut[] = {
- { 0x04f0d5, 0 },
- { 0x05387a, 1 },
- { 0x0573a4, 2 },
- { 0x05a99e, 3 },
- { 0x05cc80, 4 },
- { 0x05eb62, 5 },
- { 0x05fecf, 6 },
- { 0x060b80, 7 },
- { 0x062501, 8 },
- { 0x064865, 9 },
- { 0x069604, 10 },
- { 0x06f356, 11 },
- { 0x07706a, 12 },
- { 0x0804d3, 13 },
- { 0x089d1a, 14 },
- { 0x093e3d, 15 },
- { 0x09e35d, 16 },
- { 0x0a7c3c, 17 },
- { 0x0afaf8, 18 },
- { 0x0b719d, 19 },
- { 0x0bda6a, 20 },
- { 0x0c0c75, 21 },
- { 0x0c3f7d, 22 },
- { 0x0c5e62, 23 },
- { 0x0c6c31, 24 },
- { 0x0c7925, 25 },
- { 0xffffff, 26 },
-};
-
-/* QAM64 SNR lookup table */
-static const struct val_snr qam64_snr_lut[] = {
- { 0x0256d0, 0 },
- { 0x027a65, 1 },
- { 0x029873, 2 },
- { 0x02b7fe, 3 },
- { 0x02cf1e, 4 },
- { 0x02e234, 5 },
- { 0x02f409, 6 },
- { 0x030046, 7 },
- { 0x030844, 8 },
- { 0x030a02, 9 },
- { 0x030cde, 10 },
- { 0x031031, 11 },
- { 0x03144c, 12 },
- { 0x0315dd, 13 },
- { 0x031920, 14 },
- { 0x0322d0, 15 },
- { 0x0339fc, 16 },
- { 0x0364a1, 17 },
- { 0x038bcc, 18 },
- { 0x03c7d3, 19 },
- { 0x0408cc, 20 },
- { 0x043bed, 21 },
- { 0x048061, 22 },
- { 0x04be95, 23 },
- { 0x04fa7d, 24 },
- { 0x052405, 25 },
- { 0x05570d, 26 },
- { 0x059feb, 27 },
- { 0x05bf38, 28 },
- { 0xffffff, 29 },
-};
-
-static const struct reg_val ofsm_init[] = {
- { 0x800051, 0x01 },
- { 0x800070, 0x0a },
- { 0x80007e, 0x04 },
- { 0x800081, 0x0a },
- { 0x80008a, 0x01 },
- { 0x80008e, 0x01 },
- { 0x800092, 0x06 },
- { 0x800099, 0x01 },
- { 0x80009f, 0xe1 },
- { 0x8000a0, 0xcf },
- { 0x8000a3, 0x01 },
- { 0x8000a5, 0x01 },
- { 0x8000a6, 0x01 },
- { 0x8000a9, 0x00 },
- { 0x8000aa, 0x01 },
- { 0x8000ab, 0x01 },
- { 0x8000b0, 0x01 },
- { 0x8000c0, 0x05 },
- { 0x8000c4, 0x19 },
- { 0x80f000, 0x0f },
- { 0x80f016, 0x10 },
- { 0x80f017, 0x04 },
- { 0x80f018, 0x05 },
- { 0x80f019, 0x04 },
- { 0x80f01a, 0x05 },
- { 0x80f021, 0x03 },
- { 0x80f022, 0x0a },
- { 0x80f023, 0x0a },
- { 0x80f02b, 0x00 },
- { 0x80f02c, 0x01 },
- { 0x80f064, 0x03 },
- { 0x80f065, 0xf9 },
- { 0x80f066, 0x03 },
- { 0x80f067, 0x01 },
- { 0x80f06f, 0xe0 },
- { 0x80f070, 0x03 },
- { 0x80f072, 0x0f },
- { 0x80f073, 0x03 },
- { 0x80f078, 0x00 },
- { 0x80f087, 0x00 },
- { 0x80f09b, 0x3f },
- { 0x80f09c, 0x00 },
- { 0x80f09d, 0x20 },
- { 0x80f09e, 0x00 },
- { 0x80f09f, 0x0c },
- { 0x80f0a0, 0x00 },
- { 0x80f130, 0x04 },
- { 0x80f132, 0x04 },
- { 0x80f144, 0x1a },
- { 0x80f146, 0x00 },
- { 0x80f14a, 0x01 },
- { 0x80f14c, 0x00 },
- { 0x80f14d, 0x00 },
- { 0x80f14f, 0x04 },
- { 0x80f158, 0x7f },
- { 0x80f15a, 0x00 },
- { 0x80f15b, 0x08 },
- { 0x80f15d, 0x03 },
- { 0x80f15e, 0x05 },
- { 0x80f163, 0x05 },
- { 0x80f166, 0x01 },
- { 0x80f167, 0x40 },
- { 0x80f168, 0x0f },
- { 0x80f17a, 0x00 },
- { 0x80f17b, 0x00 },
- { 0x80f183, 0x01 },
- { 0x80f19d, 0x40 },
- { 0x80f1bc, 0x36 },
- { 0x80f1bd, 0x00 },
- { 0x80f1cb, 0xa0 },
- { 0x80f1cc, 0x01 },
- { 0x80f204, 0x10 },
- { 0x80f214, 0x00 },
- { 0x80f40e, 0x0a },
- { 0x80f40f, 0x40 },
- { 0x80f410, 0x08 },
- { 0x80f55f, 0x0a },
- { 0x80f561, 0x15 },
- { 0x80f562, 0x20 },
- { 0x80f5df, 0xfb },
- { 0x80f5e0, 0x00 },
- { 0x80f5e3, 0x09 },
- { 0x80f5e4, 0x01 },
- { 0x80f5e5, 0x01 },
- { 0x80f5f8, 0x01 },
- { 0x80f5fd, 0x01 },
- { 0x80f600, 0x05 },
- { 0x80f601, 0x08 },
- { 0x80f602, 0x0b },
- { 0x80f603, 0x0e },
- { 0x80f604, 0x11 },
- { 0x80f605, 0x14 },
- { 0x80f606, 0x17 },
- { 0x80f607, 0x1f },
- { 0x80f60e, 0x00 },
- { 0x80f60f, 0x04 },
- { 0x80f610, 0x32 },
- { 0x80f611, 0x10 },
- { 0x80f707, 0xfc },
- { 0x80f708, 0x00 },
- { 0x80f709, 0x37 },
- { 0x80f70a, 0x00 },
- { 0x80f78b, 0x01 },
- { 0x80f80f, 0x40 },
- { 0x80f810, 0x54 },
- { 0x80f811, 0x5a },
- { 0x80f905, 0x01 },
- { 0x80fb06, 0x03 },
- { 0x80fd8b, 0x00 },
-};
-
-/* Infineon TUA 9001 tuner init
- AF9033_TUNER_TUA9001 = 0x27 */
-static const struct reg_val tuner_init_tua9001[] = {
- { 0x800046, 0x27 },
- { 0x800057, 0x00 },
- { 0x800058, 0x01 },
- { 0x80005f, 0x00 },
- { 0x800060, 0x00 },
- { 0x80006d, 0x00 },
- { 0x800071, 0x05 },
- { 0x800072, 0x02 },
- { 0x800074, 0x01 },
- { 0x800075, 0x03 },
- { 0x800076, 0x02 },
- { 0x800077, 0x00 },
- { 0x800078, 0x01 },
- { 0x800079, 0x00 },
- { 0x80007a, 0x7e },
- { 0x80007b, 0x3e },
- { 0x800093, 0x00 },
- { 0x800094, 0x01 },
- { 0x800095, 0x02 },
- { 0x800096, 0x01 },
- { 0x800098, 0x0a },
- { 0x80009b, 0x05 },
- { 0x80009c, 0x80 },
- { 0x8000b3, 0x00 },
- { 0x8000c1, 0x01 },
- { 0x8000c2, 0x00 },
- { 0x80f007, 0x00 },
- { 0x80f01f, 0x82 },
- { 0x80f020, 0x00 },
- { 0x80f029, 0x82 },
- { 0x80f02a, 0x00 },
- { 0x80f047, 0x00 },
- { 0x80f054, 0x00 },
- { 0x80f055, 0x00 },
- { 0x80f077, 0x01 },
- { 0x80f1e6, 0x00 },
-};
-
-/* Fitipower fc0011 tuner init
- AF9033_TUNER_FC0011 = 0x28 */
-static const struct reg_val tuner_init_fc0011[] = {
- { 0x800046, AF9033_TUNER_FC0011 },
- { 0x800057, 0x00 },
- { 0x800058, 0x01 },
- { 0x80005f, 0x00 },
- { 0x800060, 0x00 },
- { 0x800068, 0xa5 },
- { 0x80006e, 0x01 },
- { 0x800071, 0x0A },
- { 0x800072, 0x02 },
- { 0x800074, 0x01 },
- { 0x800079, 0x01 },
- { 0x800093, 0x00 },
- { 0x800094, 0x00 },
- { 0x800095, 0x00 },
- { 0x800096, 0x00 },
- { 0x80009b, 0x2D },
- { 0x80009c, 0x60 },
- { 0x80009d, 0x23 },
- { 0x8000a4, 0x50 },
- { 0x8000ad, 0x50 },
- { 0x8000b3, 0x01 },
- { 0x8000b7, 0x88 },
- { 0x8000b8, 0xa6 },
- { 0x8000c3, 0x01 },
- { 0x8000c4, 0x01 },
- { 0x8000c7, 0x69 },
- { 0x80F007, 0x00 },
- { 0x80F00A, 0x1B },
- { 0x80F00B, 0x1B },
- { 0x80F00C, 0x1B },
- { 0x80F00D, 0x1B },
- { 0x80F00E, 0xFF },
- { 0x80F00F, 0x01 },
- { 0x80F010, 0x00 },
- { 0x80F011, 0x02 },
- { 0x80F012, 0xFF },
- { 0x80F013, 0x01 },
- { 0x80F014, 0x00 },
- { 0x80F015, 0x02 },
- { 0x80F01B, 0xEF },
- { 0x80F01C, 0x01 },
- { 0x80F01D, 0x0f },
- { 0x80F01E, 0x02 },
- { 0x80F01F, 0x6E },
- { 0x80F020, 0x00 },
- { 0x80F025, 0xDE },
- { 0x80F026, 0x00 },
- { 0x80F027, 0x0A },
- { 0x80F028, 0x03 },
- { 0x80F029, 0x6E },
- { 0x80F02A, 0x00 },
- { 0x80F047, 0x00 },
- { 0x80F054, 0x00 },
- { 0x80F055, 0x00 },
- { 0x80F077, 0x01 },
- { 0x80F1E6, 0x00 },
-};
-
-/* MaxLinear MxL5007T tuner init
- AF9033_TUNER_MXL5007T = 0xa0 */
-static const struct reg_val tuner_init_mxl5007t[] = {
- { 0x800046, 0x1b },
- { 0x800057, 0x01 },
- { 0x800058, 0x01 },
- { 0x80005f, 0x00 },
- { 0x800060, 0x00 },
- { 0x800068, 0x96 },
- { 0x800071, 0x05 },
- { 0x800072, 0x02 },
- { 0x800074, 0x01 },
- { 0x800079, 0x01 },
- { 0x800093, 0x00 },
- { 0x800094, 0x00 },
- { 0x800095, 0x00 },
- { 0x800096, 0x00 },
- { 0x8000b3, 0x01 },
- { 0x8000c1, 0x01 },
- { 0x8000c2, 0x00 },
- { 0x80f007, 0x00 },
- { 0x80f00c, 0x19 },
- { 0x80f00d, 0x1a },
- { 0x80f012, 0xda },
- { 0x80f013, 0x00 },
- { 0x80f014, 0x00 },
- { 0x80f015, 0x02 },
- { 0x80f01f, 0x82 },
- { 0x80f020, 0x00 },
- { 0x80f029, 0x82 },
- { 0x80f02a, 0x00 },
- { 0x80f077, 0x02 },
- { 0x80f1e6, 0x00 },
-};
-
-/* NXP TDA 18218HN tuner init
- AF9033_TUNER_TDA18218 = 0xa1 */
-static const struct reg_val tuner_init_tda18218[] = {
- {0x800046, 0xa1},
- {0x800057, 0x01},
- {0x800058, 0x01},
- {0x80005f, 0x00},
- {0x800060, 0x00},
- {0x800071, 0x05},
- {0x800072, 0x02},
- {0x800074, 0x01},
- {0x800079, 0x01},
- {0x800093, 0x00},
- {0x800094, 0x00},
- {0x800095, 0x00},
- {0x800096, 0x00},
- {0x8000b3, 0x01},
- {0x8000c3, 0x01},
- {0x8000c4, 0x00},
- {0x80f007, 0x00},
- {0x80f00c, 0x19},
- {0x80f00d, 0x1a},
- {0x80f012, 0xda},
- {0x80f013, 0x00},
- {0x80f014, 0x00},
- {0x80f015, 0x02},
- {0x80f01f, 0x82},
- {0x80f020, 0x00},
- {0x80f029, 0x82},
- {0x80f02a, 0x00},
- {0x80f077, 0x02},
- {0x80f1e6, 0x00},
-};
-
-#endif /* AF9033_PRIV_H */
-
diff --git a/drivers/media/dvb/frontends/atbm8830.c b/drivers/media/dvb/frontends/atbm8830.c
deleted file mode 100644
index 4e11dc4b133..00000000000
--- a/drivers/media/dvb/frontends/atbm8830.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/*
- * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
- * ATBM8830, ATBM8831
- *
- * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/div64.h>
-#include "dvb_frontend.h"
-
-#include "atbm8830.h"
-#include "atbm8830_priv.h"
-
-#define dprintk(args...) \
- do { \
- if (debug) \
- printk(KERN_DEBUG "atbm8830: " args); \
- } while (0)
-
-static int debug;
-
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-
-static int atbm8830_write_reg(struct atbm_state *priv, u16 reg, u8 data)
-{
- int ret = 0;
- u8 dev_addr;
- u8 buf1[] = { reg >> 8, reg & 0xFF };
- u8 buf2[] = { data };
- struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
- struct i2c_msg msg2 = { .flags = 0, .buf = buf2, .len = 1 };
-
- dev_addr = priv->config->demod_address;
- msg1.addr = dev_addr;
- msg2.addr = dev_addr;
-
- if (debug >= 2)
- dprintk("%s: reg=0x%04X, data=0x%02X\n", __func__, reg, data);
-
- ret = i2c_transfer(priv->i2c, &msg1, 1);
- if (ret != 1)
- return -EIO;
-
- ret = i2c_transfer(priv->i2c, &msg2, 1);
- return (ret != 1) ? -EIO : 0;
-}
-
-static int atbm8830_read_reg(struct atbm_state *priv, u16 reg, u8 *p_data)
-{
- int ret;
- u8 dev_addr;
-
- u8 buf1[] = { reg >> 8, reg & 0xFF };
- u8 buf2[] = { 0 };
- struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
- struct i2c_msg msg2 = { .flags = I2C_M_RD, .buf = buf2, .len = 1 };
-
- dev_addr = priv->config->demod_address;
- msg1.addr = dev_addr;
- msg2.addr = dev_addr;
-
- ret = i2c_transfer(priv->i2c, &msg1, 1);
- if (ret != 1) {
- dprintk("%s: error reg=0x%04x, ret=%i\n", __func__, reg, ret);
- return -EIO;
- }
-
- ret = i2c_transfer(priv->i2c, &msg2, 1);
- if (ret != 1)
- return -EIO;
-
- *p_data = buf2[0];
- if (debug >= 2)
- dprintk("%s: reg=0x%04X, data=0x%02X\n",
- __func__, reg, buf2[0]);
-
- return 0;
-}
-
-/* Lock register latch so that multi-register read is atomic */
-static inline int atbm8830_reglatch_lock(struct atbm_state *priv, int lock)
-{
- return atbm8830_write_reg(priv, REG_READ_LATCH, lock ? 1 : 0);
-}
-
-static int set_osc_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
-{
- u32 val;
- u64 t;
-
- /* 0x100000 * freq / 30.4MHz */
- t = (u64)0x100000 * freq;
- do_div(t, 30400);
- val = t;
-
- atbm8830_write_reg(priv, REG_OSC_CLK, val);
- atbm8830_write_reg(priv, REG_OSC_CLK + 1, val >> 8);
- atbm8830_write_reg(priv, REG_OSC_CLK + 2, val >> 16);
-
- return 0;
-}
-
-static int set_if_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
-{
-
- u32 fs = priv->config->osc_clk_freq;
- u64 t;
- u32 val;
- u8 dat;
-
- if (freq != 0) {
- /* 2 * PI * (freq - fs) / fs * (2 ^ 22) */
- t = (u64) 2 * 31416 * (freq - fs);
- t <<= 22;
- do_div(t, fs);
- do_div(t, 1000);
- val = t;
-
- atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 1);
- atbm8830_write_reg(priv, REG_IF_FREQ, val);
- atbm8830_write_reg(priv, REG_IF_FREQ+1, val >> 8);
- atbm8830_write_reg(priv, REG_IF_FREQ+2, val >> 16);
-
- atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
- dat &= 0xFC;
- atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
- } else {
- /* Zero IF */
- atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 0);
-
- atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
- dat &= 0xFC;
- dat |= 0x02;
- atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
-
- if (priv->config->zif_swap_iq)
- atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x03);
- else
- atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x01);
- }
-
- return 0;
-}
-
-static int is_locked(struct atbm_state *priv, u8 *locked)
-{
- u8 status;
-
- atbm8830_read_reg(priv, REG_LOCK_STATUS, &status);
-
- if (locked != NULL)
- *locked = (status == 1);
- return 0;
-}
-
-static int set_agc_config(struct atbm_state *priv,
- u8 min, u8 max, u8 hold_loop)
-{
- /* no effect if both min and max are zero */
- if (!min && !max)
- return 0;
-
- atbm8830_write_reg(priv, REG_AGC_MIN, min);
- atbm8830_write_reg(priv, REG_AGC_MAX, max);
- atbm8830_write_reg(priv, REG_AGC_HOLD_LOOP, hold_loop);
-
- return 0;
-}
-
-static int set_static_channel_mode(struct atbm_state *priv)
-{
- int i;
-
- for (i = 0; i < 5; i++)
- atbm8830_write_reg(priv, 0x099B + i, 0x08);
-
- atbm8830_write_reg(priv, 0x095B, 0x7F);
- atbm8830_write_reg(priv, 0x09CB, 0x01);
- atbm8830_write_reg(priv, 0x09CC, 0x7F);
- atbm8830_write_reg(priv, 0x09CD, 0x7F);
- atbm8830_write_reg(priv, 0x0E01, 0x20);
-
- /* For single carrier */
- atbm8830_write_reg(priv, 0x0B03, 0x0A);
- atbm8830_write_reg(priv, 0x0935, 0x10);
- atbm8830_write_reg(priv, 0x0936, 0x08);
- atbm8830_write_reg(priv, 0x093E, 0x08);
- atbm8830_write_reg(priv, 0x096E, 0x06);
-
- /* frame_count_max0 */
- atbm8830_write_reg(priv, 0x0B09, 0x00);
- /* frame_count_max1 */
- atbm8830_write_reg(priv, 0x0B0A, 0x08);
-
- return 0;
-}
-
-static int set_ts_config(struct atbm_state *priv)
-{
- const struct atbm8830_config *cfg = priv->config;
-
- /*Set parallel/serial ts mode*/
- atbm8830_write_reg(priv, REG_TS_SERIAL, cfg->serial_ts ? 1 : 0);
- atbm8830_write_reg(priv, REG_TS_CLK_MODE, cfg->serial_ts ? 1 : 0);
- /*Set ts sampling edge*/
- atbm8830_write_reg(priv, REG_TS_SAMPLE_EDGE,
- cfg->ts_sampling_edge ? 1 : 0);
- /*Set ts clock freerun*/
- atbm8830_write_reg(priv, REG_TS_CLK_FREERUN,
- cfg->ts_clk_gated ? 0 : 1);
-
- return 0;
-}
-
-static int atbm8830_init(struct dvb_frontend *fe)
-{
- struct atbm_state *priv = fe->demodulator_priv;
- const struct atbm8830_config *cfg = priv->config;
-
- /*Set oscillator frequency*/
- set_osc_freq(priv, cfg->osc_clk_freq);
-
- /*Set IF frequency*/
- set_if_freq(priv, cfg->if_freq);
-
- /*Set AGC Config*/
- set_agc_config(priv, cfg->agc_min, cfg->agc_max,
- cfg->agc_hold_loop);
-
- /*Set static channel mode*/
- set_static_channel_mode(priv);
-
- set_ts_config(priv);
- /*Turn off DSP reset*/
- atbm8830_write_reg(priv, 0x000A, 0);
-
- /*SW version test*/
- atbm8830_write_reg(priv, 0x020C, 11);
-
- /* Run */
- atbm8830_write_reg(priv, REG_DEMOD_RUN, 1);
-
- return 0;
-}
-
-
-static void atbm8830_release(struct dvb_frontend *fe)
-{
- struct atbm_state *state = fe->demodulator_priv;
- dprintk("%s\n", __func__);
-
- kfree(state);
-}
-
-static int atbm8830_set_fe(struct dvb_frontend *fe)
-{
- struct atbm_state *priv = fe->demodulator_priv;
- int i;
- u8 locked = 0;
- dprintk("%s\n", __func__);
-
- /* set frequency */
- if (fe->ops.tuner_ops.set_params) {
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
- fe->ops.tuner_ops.set_params(fe);
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 0);
- }
-
- /* start auto lock */
- for (i = 0; i < 10; i++) {
- mdelay(100);
- dprintk("Try %d\n", i);
- is_locked(priv, &locked);
- if (locked != 0) {
- dprintk("ATBM8830 locked!\n");
- break;
- }
- }
-
- return 0;
-}
-
-static int atbm8830_get_fe(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- dprintk("%s\n", __func__);
-
- /* TODO: get real readings from device */
- /* inversion status */
- c->inversion = INVERSION_OFF;
-
- /* bandwidth */
- c->bandwidth_hz = 8000000;
-
- c->code_rate_HP = FEC_AUTO;
- c->code_rate_LP = FEC_AUTO;
-
- c->modulation = QAM_AUTO;
-
- /* transmission mode */
- c->transmission_mode = TRANSMISSION_MODE_AUTO;
-
- /* guard interval */
- c->guard_interval = GUARD_INTERVAL_AUTO;
-
- /* hierarchy */
- c->hierarchy = HIERARCHY_NONE;
-
- return 0;
-}
-
-static int atbm8830_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *fesettings)
-{
- fesettings->min_delay_ms = 0;
- fesettings->step_size = 0;
- fesettings->max_drift = 0;
- return 0;
-}
-
-static int atbm8830_read_status(struct dvb_frontend *fe, fe_status_t *fe_status)
-{
- struct atbm_state *priv = fe->demodulator_priv;
- u8 locked = 0;
- u8 agc_locked = 0;
-
- dprintk("%s\n", __func__);
- *fe_status = 0;
-
- is_locked(priv, &locked);
- if (locked) {
- *fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
- }
- dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
-
- atbm8830_read_reg(priv, REG_AGC_LOCK, &agc_locked);
- dprintk("AGC Lock: %d\n", agc_locked);
-
- return 0;
-}
-
-static int atbm8830_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct atbm_state *priv = fe->demodulator_priv;
- u32 frame_err;
- u8 t;
-
- dprintk("%s\n", __func__);
-
- atbm8830_reglatch_lock(priv, 1);
-
- atbm8830_read_reg(priv, REG_FRAME_ERR_CNT + 1, &t);
- frame_err = t & 0x7F;
- frame_err <<= 8;
- atbm8830_read_reg(priv, REG_FRAME_ERR_CNT, &t);
- frame_err |= t;
-
- atbm8830_reglatch_lock(priv, 0);
-
- *ber = frame_err * 100 / 32767;
-
- dprintk("%s: ber=0x%x\n", __func__, *ber);
- return 0;
-}
-
-static int atbm8830_read_signal_strength(struct dvb_frontend *fe, u16 *signal)
-{
- struct atbm_state *priv = fe->demodulator_priv;
- u32 pwm;
- u8 t;
-
- dprintk("%s\n", __func__);
- atbm8830_reglatch_lock(priv, 1);
-
- atbm8830_read_reg(priv, REG_AGC_PWM_VAL + 1, &t);
- pwm = t & 0x03;
- pwm <<= 8;
- atbm8830_read_reg(priv, REG_AGC_PWM_VAL, &t);
- pwm |= t;
-
- atbm8830_reglatch_lock(priv, 0);
-
- dprintk("AGC PWM = 0x%02X\n", pwm);
- pwm = 0x400 - pwm;
-
- *signal = pwm * 0x10000 / 0x400;
-
- return 0;
-}
-
-static int atbm8830_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- dprintk("%s\n", __func__);
- *snr = 0;
- return 0;
-}
-
-static int atbm8830_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- dprintk("%s\n", __func__);
- *ucblocks = 0;
- return 0;
-}
-
-static int atbm8830_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- struct atbm_state *priv = fe->demodulator_priv;
-
- return atbm8830_write_reg(priv, REG_I2C_GATE, enable ? 1 : 0);
-}
-
-static struct dvb_frontend_ops atbm8830_ops = {
- .delsys = { SYS_DTMB },
- .info = {
- .name = "AltoBeam ATBM8830/8831 DMB-TH",
- .frequency_min = 474000000,
- .frequency_max = 858000000,
- .frequency_stepsize = 10000,
- .caps =
- FE_CAN_FEC_AUTO |
- FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO
- },
-
- .release = atbm8830_release,
-
- .init = atbm8830_init,
- .sleep = NULL,
- .write = NULL,
- .i2c_gate_ctrl = atbm8830_i2c_gate_ctrl,
-
- .set_frontend = atbm8830_set_fe,
- .get_frontend = atbm8830_get_fe,
- .get_tune_settings = atbm8830_get_tune_settings,
-
- .read_status = atbm8830_read_status,
- .read_ber = atbm8830_read_ber,
- .read_signal_strength = atbm8830_read_signal_strength,
- .read_snr = atbm8830_read_snr,
- .read_ucblocks = atbm8830_read_ucblocks,
-};
-
-struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
- struct i2c_adapter *i2c)
-{
- struct atbm_state *priv = NULL;
- u8 data = 0;
-
- dprintk("%s()\n", __func__);
-
- if (config == NULL || i2c == NULL)
- return NULL;
-
- priv = kzalloc(sizeof(struct atbm_state), GFP_KERNEL);
- if (priv == NULL)
- goto error_out;
-
- priv->config = config;
- priv->i2c = i2c;
-
- /* check if the demod is there */
- if (atbm8830_read_reg(priv, REG_CHIP_ID, &data) != 0) {
- dprintk("%s atbm8830/8831 not found at i2c addr 0x%02X\n",
- __func__, priv->config->demod_address);
- goto error_out;
- }
- dprintk("atbm8830 chip id: 0x%02X\n", data);
-
- memcpy(&priv->frontend.ops, &atbm8830_ops,
- sizeof(struct dvb_frontend_ops));
- priv->frontend.demodulator_priv = priv;
-
- atbm8830_init(&priv->frontend);
-
- atbm8830_i2c_gate_ctrl(&priv->frontend, 1);
-
- return &priv->frontend;
-
-error_out:
- dprintk("%s() error_out\n", __func__);
- kfree(priv);
- return NULL;
-
-}
-EXPORT_SYMBOL(atbm8830_attach);
-
-MODULE_DESCRIPTION("AltoBeam ATBM8830/8831 GB20600 demodulator driver");
-MODULE_AUTHOR("David T. L. Wong <davidtlwong@gmail.com>");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/atbm8830.h b/drivers/media/dvb/frontends/atbm8830.h
deleted file mode 100644
index 024273374bd..00000000000
--- a/drivers/media/dvb/frontends/atbm8830.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
- * ATBM8830, ATBM8831
- *
- * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ATBM8830_H__
-#define __ATBM8830_H__
-
-#include <linux/dvb/frontend.h>
-#include <linux/i2c.h>
-
-#define ATBM8830_PROD_8830 0
-#define ATBM8830_PROD_8831 1
-
-struct atbm8830_config {
-
- /* product type */
- u8 prod;
-
- /* the demodulator's i2c address */
- u8 demod_address;
-
- /* parallel or serial transport stream */
- u8 serial_ts;
-
- /* transport stream clock output only when receiving valid stream */
- u8 ts_clk_gated;
-
- /* Decoder sample TS data at rising edge of clock */
- u8 ts_sampling_edge;
-
- /* Oscillator clock frequency */
- u32 osc_clk_freq; /* in kHz */
-
- /* IF frequency */
- u32 if_freq; /* in kHz */
-
- /* Swap I/Q for zero IF */
- u8 zif_swap_iq;
-
- /* Tuner AGC settings */
- u8 agc_min;
- u8 agc_max;
- u8 agc_hold_loop;
-};
-
-#if defined(CONFIG_DVB_ATBM8830) || \
- (defined(CONFIG_DVB_ATBM8830_MODULE) && defined(MODULE))
-extern struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline
-struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
- struct i2c_adapter *i2c) {
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif /* CONFIG_DVB_ATBM8830 */
-
-#endif /* __ATBM8830_H__ */
diff --git a/drivers/media/dvb/frontends/atbm8830_priv.h b/drivers/media/dvb/frontends/atbm8830_priv.h
deleted file mode 100644
index d460058d497..00000000000
--- a/drivers/media/dvb/frontends/atbm8830_priv.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
- * ATBM8830, ATBM8831
- *
- * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ATBM8830_PRIV_H
-#define __ATBM8830_PRIV_H
-
-struct atbm_state {
- struct i2c_adapter *i2c;
- /* configuration settings */
- const struct atbm8830_config *config;
- struct dvb_frontend frontend;
-};
-
-#define REG_CHIP_ID 0x0000
-#define REG_TUNER_BASEBAND 0x0001
-#define REG_DEMOD_RUN 0x0004
-#define REG_DSP_RESET 0x0005
-#define REG_RAM_RESET 0x0006
-#define REG_ADC_RESET 0x0007
-#define REG_TSPORT_RESET 0x0008
-#define REG_BLKERR_POL 0x000C
-#define REG_I2C_GATE 0x0103
-#define REG_TS_SAMPLE_EDGE 0x0301
-#define REG_TS_PKT_LEN_204 0x0302
-#define REG_TS_PKT_LEN_AUTO 0x0303
-#define REG_TS_SERIAL 0x0305
-#define REG_TS_CLK_FREERUN 0x0306
-#define REG_TS_VALID_MODE 0x0307
-#define REG_TS_CLK_MODE 0x030B /* 1 for serial, 0 for parallel */
-
-#define REG_TS_ERRBIT_USE 0x030C
-#define REG_LOCK_STATUS 0x030D
-#define REG_ADC_CONFIG 0x0602
-#define REG_CARRIER_OFFSET 0x0827 /* 0x0827-0x0829 little endian */
-#define REG_DETECTED_PN_MODE 0x082D
-#define REG_READ_LATCH 0x084D
-#define REG_IF_FREQ 0x0A00 /* 0x0A00-0x0A02 little endian */
-#define REG_OSC_CLK 0x0A03 /* 0x0A03-0x0A05 little endian */
-#define REG_BYPASS_CCI 0x0A06
-#define REG_ANALOG_LUMA_DETECTED 0x0A25
-#define REG_ANALOG_AUDIO_DETECTED 0x0A26
-#define REG_ANALOG_CHROMA_DETECTED 0x0A39
-#define REG_FRAME_ERR_CNT 0x0B04
-#define REG_USE_EXT_ADC 0x0C00
-#define REG_SWAP_I_Q 0x0C01
-#define REG_TPS_MANUAL 0x0D01
-#define REG_TPS_CONFIG 0x0D02
-#define REG_BYPASS_DEINTERLEAVER 0x0E00
-#define REG_AGC_TARGET 0x1003 /* 0x1003-0x1005 little endian */
-#define REG_AGC_MIN 0x1020
-#define REG_AGC_MAX 0x1023
-#define REG_AGC_LOCK 0x1027
-#define REG_AGC_PWM_VAL 0x1028 /* 0x1028-0x1029 little endian */
-#define REG_AGC_HOLD_LOOP 0x1031
-
-#endif
-
diff --git a/drivers/media/dvb/frontends/au8522.h b/drivers/media/dvb/frontends/au8522.h
deleted file mode 100644
index 565dcf31af5..00000000000
--- a/drivers/media/dvb/frontends/au8522.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- Auvitek AU8522 QAM/8VSB demodulator driver
-
- Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#ifndef __AU8522_H__
-#define __AU8522_H__
-
-#include <linux/dvb/frontend.h>
-
-enum au8522_if_freq {
- AU8522_IF_6MHZ = 0,
- AU8522_IF_4MHZ,
- AU8522_IF_3_25MHZ,
-};
-
-struct au8522_led_config {
- u16 vsb8_strong;
- u16 qam64_strong;
- u16 qam256_strong;
-
- u16 gpio_output;
- /* unset hi bits, set low bits */
- u16 gpio_output_enable;
- u16 gpio_output_disable;
-
- u16 gpio_leds;
- u8 *led_states;
- unsigned int num_led_states;
-};
-
-struct au8522_config {
- /* the demodulator's i2c address */
- u8 demod_address;
-
- /* Return lock status based on tuner lock, or demod lock */
-#define AU8522_TUNERLOCKING 0
-#define AU8522_DEMODLOCKING 1
- u8 status_mode;
-
- struct au8522_led_config *led_cfg;
-
- enum au8522_if_freq vsb_if;
- enum au8522_if_freq qam_if;
-};
-
-#if defined(CONFIG_DVB_AU8522) || \
- (defined(CONFIG_DVB_AU8522_MODULE) && defined(MODULE))
-extern struct dvb_frontend *au8522_attach(const struct au8522_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline
-struct dvb_frontend *au8522_attach(const struct au8522_config *config,
- struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif /* CONFIG_DVB_AU8522 */
-
-/* Other modes may need to be added later */
-enum au8522_video_input {
- AU8522_COMPOSITE_CH1 = 1,
- AU8522_COMPOSITE_CH2,
- AU8522_COMPOSITE_CH3,
- AU8522_COMPOSITE_CH4,
- AU8522_COMPOSITE_CH4_SIF,
- AU8522_SVIDEO_CH13,
- AU8522_SVIDEO_CH24,
-};
-
-enum au8522_audio_input {
- AU8522_AUDIO_NONE,
- AU8522_AUDIO_SIF,
-};
-
-#endif /* __AU8522_H__ */
-
-/*
- * Local variables:
- * c-basic-offset: 8
- */
diff --git a/drivers/media/dvb/frontends/au8522_common.c b/drivers/media/dvb/frontends/au8522_common.c
deleted file mode 100644
index 3559ff23004..00000000000
--- a/drivers/media/dvb/frontends/au8522_common.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- Auvitek AU8522 QAM/8VSB demodulator driver
-
- Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
- Copyright (C) 2008 Devin Heitmueller <dheitmueller@linuxtv.org>
- Copyright (C) 2005-2008 Auvitek International, Ltd.
- Copyright (C) 2012 Michael Krufky <mkrufky@linuxtv.org>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#include <linux/i2c.h>
-#include "dvb_frontend.h"
-#include "au8522_priv.h"
-
-static int debug;
-
-#define dprintk(arg...)\
- do { if (debug)\
- printk(arg);\
- } while (0)
-
-/* Despite the name "hybrid_tuner", the framework works just as well for
- hybrid demodulators as well... */
-static LIST_HEAD(hybrid_tuner_instance_list);
-static DEFINE_MUTEX(au8522_list_mutex);
-
-/* 16 bit registers, 8 bit values */
-int au8522_writereg(struct au8522_state *state, u16 reg, u8 data)
-{
- int ret;
- u8 buf[] = { (reg >> 8) | 0x80, reg & 0xff, data };
-
- struct i2c_msg msg = { .addr = state->config->demod_address,
- .flags = 0, .buf = buf, .len = 3 };
-
- ret = i2c_transfer(state->i2c, &msg, 1);
-
- if (ret != 1)
- printk("%s: writereg error (reg == 0x%02x, val == 0x%04x, "
- "ret == %i)\n", __func__, reg, data, ret);
-
- return (ret != 1) ? -1 : 0;
-}
-EXPORT_SYMBOL(au8522_writereg);
-
-u8 au8522_readreg(struct au8522_state *state, u16 reg)
-{
- int ret;
- u8 b0[] = { (reg >> 8) | 0x40, reg & 0xff };
- u8 b1[] = { 0 };
-
- struct i2c_msg msg[] = {
- { .addr = state->config->demod_address, .flags = 0,
- .buf = b0, .len = 2 },
- { .addr = state->config->demod_address, .flags = I2C_M_RD,
- .buf = b1, .len = 1 } };
-
- ret = i2c_transfer(state->i2c, msg, 2);
-
- if (ret != 2)
- printk(KERN_ERR "%s: readreg error (ret == %i)\n",
- __func__, ret);
- return b1[0];
-}
-EXPORT_SYMBOL(au8522_readreg);
-
-int au8522_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- struct au8522_state *state = fe->demodulator_priv;
-
- dprintk("%s(%d)\n", __func__, enable);
-
- if (state->operational_mode == AU8522_ANALOG_MODE) {
- /* We're being asked to manage the gate even though we're
- not in digital mode. This can occur if we get switched
- over to analog mode before the dvb_frontend kernel thread
- has completely shutdown */
- return 0;
- }
-
- if (enable)
- return au8522_writereg(state, 0x106, 1);
- else
- return au8522_writereg(state, 0x106, 0);
-}
-EXPORT_SYMBOL(au8522_i2c_gate_ctrl);
-
-int au8522_analog_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- struct au8522_state *state = fe->demodulator_priv;
-
- dprintk("%s(%d)\n", __func__, enable);
-
- if (enable)
- return au8522_writereg(state, 0x106, 1);
- else
- return au8522_writereg(state, 0x106, 0);
-}
-EXPORT_SYMBOL(au8522_analog_i2c_gate_ctrl);
-
-/* Reset the demod hardware and reset all of the configuration registers
- to a default state. */
-int au8522_get_state(struct au8522_state **state, struct i2c_adapter *i2c,
- u8 client_address)
-{
- int ret;
-
- mutex_lock(&au8522_list_mutex);
- ret = hybrid_tuner_request_state(struct au8522_state, (*state),
- hybrid_tuner_instance_list,
- i2c, client_address, "au8522");
- mutex_unlock(&au8522_list_mutex);
-
- return ret;
-}
-EXPORT_SYMBOL(au8522_get_state);
-
-void au8522_release_state(struct au8522_state *state)
-{
- mutex_lock(&au8522_list_mutex);
- if (state != NULL)
- hybrid_tuner_release_state(state);
- mutex_unlock(&au8522_list_mutex);
-}
-EXPORT_SYMBOL(au8522_release_state);
-
-static int au8522_led_gpio_enable(struct au8522_state *state, int onoff)
-{
- struct au8522_led_config *led_config = state->config->led_cfg;
- u8 val;
-
- /* bail out if we can't control an LED */
- if (!led_config || !led_config->gpio_output ||
- !led_config->gpio_output_enable || !led_config->gpio_output_disable)
- return 0;
-
- val = au8522_readreg(state, 0x4000 |
- (led_config->gpio_output & ~0xc000));
- if (onoff) {
- /* enable GPIO output */
- val &= ~((led_config->gpio_output_enable >> 8) & 0xff);
- val |= (led_config->gpio_output_enable & 0xff);
- } else {
- /* disable GPIO output */
- val &= ~((led_config->gpio_output_disable >> 8) & 0xff);
- val |= (led_config->gpio_output_disable & 0xff);
- }
- return au8522_writereg(state, 0x8000 |
- (led_config->gpio_output & ~0xc000), val);
-}
-
-/* led = 0 | off
- * led = 1 | signal ok
- * led = 2 | signal strong
- * led < 0 | only light led if leds are currently off
- */
-int au8522_led_ctrl(struct au8522_state *state, int led)
-{
- struct au8522_led_config *led_config = state->config->led_cfg;
- int i, ret = 0;
-
- /* bail out if we can't control an LED */
- if (!led_config || !led_config->gpio_leds ||
- !led_config->num_led_states || !led_config->led_states)
- return 0;
-
- if (led < 0) {
- /* if LED is already lit, then leave it as-is */
- if (state->led_state)
- return 0;
- else
- led *= -1;
- }
-
- /* toggle LED if changing state */
- if (state->led_state != led) {
- u8 val;
-
- dprintk("%s: %d\n", __func__, led);
-
- au8522_led_gpio_enable(state, 1);
-
- val = au8522_readreg(state, 0x4000 |
- (led_config->gpio_leds & ~0xc000));
-
- /* start with all leds off */
- for (i = 0; i < led_config->num_led_states; i++)
- val &= ~led_config->led_states[i];
-
- /* set selected LED state */
- if (led < led_config->num_led_states)
- val |= led_config->led_states[led];
- else if (led_config->num_led_states)
- val |=
- led_config->led_states[led_config->num_led_states - 1];
-
- ret = au8522_writereg(state, 0x8000 |
- (led_config->gpio_leds & ~0xc000), val);
- if (ret < 0)
- return ret;
-
- state->led_state = led;
-
- if (led == 0)
- au8522_led_gpio_enable(state, 0);
- }
-
- return 0;
-}
-EXPORT_SYMBOL(au8522_led_ctrl);
-
-int au8522_init(struct dvb_frontend *fe)
-{
- struct au8522_state *state = fe->demodulator_priv;
- dprintk("%s()\n", __func__);
-
- state->operational_mode = AU8522_DIGITAL_MODE;
-
- /* Clear out any state associated with the digital side of the
- chip, so that when it gets powered back up it won't think
- that it is already tuned */
- state->current_frequency = 0;
-
- au8522_writereg(state, 0xa4, 1 << 5);
-
- au8522_i2c_gate_ctrl(fe, 1);
-
- return 0;
-}
-EXPORT_SYMBOL(au8522_init);
-
-int au8522_sleep(struct dvb_frontend *fe)
-{
- struct au8522_state *state = fe->demodulator_priv;
- dprintk("%s()\n", __func__);
-
- /* Only power down if the digital side is currently using the chip */
- if (state->operational_mode == AU8522_ANALOG_MODE) {
- /* We're not in one of the expected power modes, which means
- that the DVB thread is probably telling us to go to sleep
- even though the analog frontend has already started using
- the chip. So ignore the request */
- return 0;
- }
-
- /* turn off led */
- au8522_led_ctrl(state, 0);
-
- /* Power down the chip */
- au8522_writereg(state, 0xa4, 1 << 5);
-
- state->current_frequency = 0;
-
- return 0;
-}
-EXPORT_SYMBOL(au8522_sleep);
-
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Enable verbose debug messages");
-
-MODULE_DESCRIPTION("Auvitek AU8522 QAM-B/ATSC Demodulator driver");
-MODULE_AUTHOR("Steven Toth");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/au8522_decoder.c b/drivers/media/dvb/frontends/au8522_decoder.c
deleted file mode 100644
index 5243ba6295c..00000000000
--- a/drivers/media/dvb/frontends/au8522_decoder.c
+++ /dev/null
@@ -1,839 +0,0 @@
-/*
- * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
- *
- * Copyright (C) 2009 Devin Heitmueller <dheitmueller@linuxtv.org>
- * Copyright (C) 2005-2008 Auvitek International, Ltd.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * As published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-/* Developer notes:
- *
- * VBI support is not yet working
- * Enough is implemented here for CVBS and S-Video inputs, but the actual
- * analog demodulator code isn't implemented (not needed for xc5000 since it
- * has its own demodulator and outputs CVBS)
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/videodev2.h>
-#include <linux/i2c.h>
-#include <linux/delay.h>
-#include <media/v4l2-common.h>
-#include <media/v4l2-chip-ident.h>
-#include <media/v4l2-device.h>
-#include "au8522.h"
-#include "au8522_priv.h"
-
-MODULE_AUTHOR("Devin Heitmueller");
-MODULE_LICENSE("GPL");
-
-static int au8522_analog_debug;
-
-
-module_param_named(analog_debug, au8522_analog_debug, int, 0644);
-
-MODULE_PARM_DESC(analog_debug,
- "Analog debugging messages [0=Off (default) 1=On]");
-
-struct au8522_register_config {
- u16 reg_name;
- u8 reg_val[8];
-};
-
-
-/* Video Decoder Filter Coefficients
- The values are as follows from left to right
- 0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
-*/
-static const struct au8522_register_config filter_coef[] = {
- {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
- {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
- {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
- {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
- {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
- {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
- {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
- {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
- {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
- {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
- {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
- {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
- {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
- {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
- {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
- {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
- {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
- {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
- {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
- {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
- {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
- {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
- {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
- {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
- {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
- {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
- {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
- {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
- {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
- {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
-
-};
-#define NUM_FILTER_COEF (sizeof(filter_coef)\
- / sizeof(struct au8522_register_config))
-
-
-/* Registers 0x060b through 0x0652 are the LP Filter coefficients
- The values are as follows from left to right
- 0="SIF" 1="ATVRF/ATVRF13"
- Note: the "ATVRF/ATVRF13" mode has never been tested
-*/
-static const struct au8522_register_config lpfilter_coef[] = {
- {0x060b, {0x21, 0x0b} },
- {0x060c, {0xad, 0xad} },
- {0x060d, {0x70, 0xf0} },
- {0x060e, {0xea, 0xe9} },
- {0x060f, {0xdd, 0xdd} },
- {0x0610, {0x08, 0x64} },
- {0x0611, {0x60, 0x60} },
- {0x0612, {0xf8, 0xb2} },
- {0x0613, {0x01, 0x02} },
- {0x0614, {0xe4, 0xb4} },
- {0x0615, {0x19, 0x02} },
- {0x0616, {0xae, 0x2e} },
- {0x0617, {0xee, 0xc5} },
- {0x0618, {0x56, 0x56} },
- {0x0619, {0x30, 0x58} },
- {0x061a, {0xf9, 0xf8} },
- {0x061b, {0x24, 0x64} },
- {0x061c, {0x07, 0x07} },
- {0x061d, {0x30, 0x30} },
- {0x061e, {0xa9, 0xed} },
- {0x061f, {0x09, 0x0b} },
- {0x0620, {0x42, 0xc2} },
- {0x0621, {0x1d, 0x2a} },
- {0x0622, {0xd6, 0x56} },
- {0x0623, {0x95, 0x8b} },
- {0x0624, {0x2b, 0x2b} },
- {0x0625, {0x30, 0x24} },
- {0x0626, {0x3e, 0x3e} },
- {0x0627, {0x62, 0xe2} },
- {0x0628, {0xe9, 0xf5} },
- {0x0629, {0x99, 0x19} },
- {0x062a, {0xd4, 0x11} },
- {0x062b, {0x03, 0x04} },
- {0x062c, {0xb5, 0x85} },
- {0x062d, {0x1e, 0x20} },
- {0x062e, {0x2a, 0xea} },
- {0x062f, {0xd7, 0xd2} },
- {0x0630, {0x15, 0x15} },
- {0x0631, {0xa3, 0xa9} },
- {0x0632, {0x1f, 0x1f} },
- {0x0633, {0xf9, 0xd1} },
- {0x0634, {0xc0, 0xc3} },
- {0x0635, {0x4d, 0x8d} },
- {0x0636, {0x21, 0x31} },
- {0x0637, {0x83, 0x83} },
- {0x0638, {0x08, 0x8c} },
- {0x0639, {0x19, 0x19} },
- {0x063a, {0x45, 0xa5} },
- {0x063b, {0xef, 0xec} },
- {0x063c, {0x8a, 0x8a} },
- {0x063d, {0xf4, 0xf6} },
- {0x063e, {0x8f, 0x8f} },
- {0x063f, {0x44, 0x0c} },
- {0x0640, {0xef, 0xf0} },
- {0x0641, {0x66, 0x66} },
- {0x0642, {0xcc, 0xd2} },
- {0x0643, {0x41, 0x41} },
- {0x0644, {0x63, 0x93} },
- {0x0645, {0x8e, 0x8e} },
- {0x0646, {0xa2, 0x42} },
- {0x0647, {0x7b, 0x7b} },
- {0x0648, {0x04, 0x04} },
- {0x0649, {0x00, 0x00} },
- {0x064a, {0x40, 0x40} },
- {0x064b, {0x8c, 0x98} },
- {0x064c, {0x00, 0x00} },
- {0x064d, {0x63, 0xc3} },
- {0x064e, {0x04, 0x04} },
- {0x064f, {0x20, 0x20} },
- {0x0650, {0x00, 0x00} },
- {0x0651, {0x40, 0x40} },
- {0x0652, {0x01, 0x01} },
-};
-#define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
- / sizeof(struct au8522_register_config))
-
-static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
-{
- return container_of(sd, struct au8522_state, sd);
-}
-
-static void setup_vbi(struct au8522_state *state, int aud_input)
-{
- int i;
-
- /* These are set to zero regardless of what mode we're in */
- au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H, 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_L_REG018H, 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H, 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH, 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH, 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_THRESH1_REG01CH, 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH, 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH, 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H, 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H,
- 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H,
- 0x00);
- au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H,
- 0x00);
-
- /* Setup the VBI registers */
- for (i = 0x30; i < 0x60; i++)
- au8522_writereg(state, i, 0x40);
-
- /* For some reason, every register is 0x40 except register 0x44
- (confirmed via the HVR-950q USB capture) */
- au8522_writereg(state, 0x44, 0x60);
-
- /* Enable VBI (we always do this regardless of whether the user is
- viewing closed caption info) */
- au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H,
- AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON);
-
-}
-
-static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode)
-{
- int i;
- int filter_coef_type;
-
- /* Provide reasonable defaults for picture tuning values */
- au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
- au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
- state->brightness = 0xed - 128;
- au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
- state->contrast = 0x79;
- au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
- au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
- state->saturation = 0x80;
- au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
- au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
- state->hue = 0x00;
-
- /* Other decoder registers */
- au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
-
- if (input_mode == 0x23) {
- /* S-Video input mapping */
- au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
- } else {
- /* All other modes (CVBS/ATVRF etc.) */
- au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
- }
-
- au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
- AU8522_TVDEC_PGA_REG012H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
- AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
- au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
- AU8522_TVDED_DBG_MODE_REG060H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
- au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
- AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
- au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
- AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
- AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
- AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
- AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
- AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
- AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
- AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
- AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
- AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
- if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||
- input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {
- au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
- AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
- au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
- AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
- } else {
- au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
- AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
- AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
- }
- au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
- AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
- au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
- AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
- AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
- au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
- au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
- AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
- au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
- au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
- AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
- AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
- AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
- au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
- AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
- au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
- AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
- au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
- AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
- au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
- AU8522_TOREGAAGC_REG0E5H_CVBS);
- au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
-
- setup_vbi(state, 0);
-
- if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||
- input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {
- /* Despite what the table says, for the HVR-950q we still need
- to be in CVBS mode for the S-Video input (reason unknown). */
- /* filter_coef_type = 3; */
- filter_coef_type = 5;
- } else {
- filter_coef_type = 5;
- }
-
- /* Load the Video Decoder Filter Coefficients */
- for (i = 0; i < NUM_FILTER_COEF; i++) {
- au8522_writereg(state, filter_coef[i].reg_name,
- filter_coef[i].reg_val[filter_coef_type]);
- }
-
- /* It's not clear what these registers are for, but they are always
- set to the same value regardless of what mode we're in */
- au8522_writereg(state, AU8522_REG42EH, 0x87);
- au8522_writereg(state, AU8522_REG42FH, 0xa2);
- au8522_writereg(state, AU8522_REG430H, 0xbf);
- au8522_writereg(state, AU8522_REG431H, 0xcb);
- au8522_writereg(state, AU8522_REG432H, 0xa1);
- au8522_writereg(state, AU8522_REG433H, 0x41);
- au8522_writereg(state, AU8522_REG434H, 0x88);
- au8522_writereg(state, AU8522_REG435H, 0xc2);
- au8522_writereg(state, AU8522_REG436H, 0x3c);
-}
-
-static void au8522_setup_cvbs_mode(struct au8522_state *state)
-{
- /* here we're going to try the pre-programmed route */
- au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
-
- /* PGA in automatic mode */
- au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
-
- /* Enable clamping control */
- au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
-
- au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
- AU8522_INPUT_CONTROL_REG081H_CVBS_CH1);
-
- setup_decoder_defaults(state, AU8522_INPUT_CONTROL_REG081H_CVBS_CH1);
-
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
-}
-
-static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state)
-{
- /* here we're going to try the pre-programmed route */
- au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
-
- /* It's not clear why we have to have the PGA in automatic mode while
- enabling clamp control, but it's what Windows does */
- au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
-
- /* Enable clamping control */
- au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
-
- /* Disable automatic PGA (since the CVBS is coming from the tuner) */
- au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
-
- /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
- au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
- AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF);
-
- setup_decoder_defaults(state,
- AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF);
-
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
-}
-
-static void au8522_setup_svideo_mode(struct au8522_state *state)
-{
- au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
-
- /* Set input to Y on Channe1, C on Channel 3 */
- au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
- AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13);
-
- /* PGA in automatic mode */
- au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
-
- /* Enable clamping control */
- au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
-
- setup_decoder_defaults(state,
- AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13);
-
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
-}
-
-/* ----------------------------------------------------------------------- */
-
-static void disable_audio_input(struct au8522_state *state)
-{
- au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
- au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
- au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
-
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
- au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
-
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
-}
-
-/* 0=disable, 1=SIF */
-static void set_audio_input(struct au8522_state *state, int aud_input)
-{
- int i;
-
- /* Note that this function needs to be used in conjunction with setting
- the input routing via register 0x81 */
-
- if (aud_input == AU8522_AUDIO_NONE) {
- disable_audio_input(state);
- return;
- }
-
- if (aud_input != AU8522_AUDIO_SIF) {
- /* The caller asked for a mode we don't currently support */
- printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
- aud_input);
- return;
- }
-
- /* Load the Audio Decoder Filter Coefficients */
- for (i = 0; i < NUM_LPFILTER_COEF; i++) {
- au8522_writereg(state, lpfilter_coef[i].reg_name,
- lpfilter_coef[i].reg_val[0]);
- }
-
- /* Setup audio */
- au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
- au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
- au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
- au8522_writereg(state, AU8522_I2C_CONTROL_REG1_REG091H, 0x80);
- au8522_writereg(state, AU8522_I2C_CONTROL_REG0_REG090H, 0x84);
- msleep(150);
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x00);
- msleep(1);
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
- msleep(50);
- au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
- au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
- au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
- msleep(80);
- au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
- au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
- au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
- au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
- msleep(70);
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
- au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
- au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
-}
-
-/* ----------------------------------------------------------------------- */
-
-static int au8522_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
-{
- struct au8522_state *state = to_state(sd);
-
- switch (ctrl->id) {
- case V4L2_CID_BRIGHTNESS:
- state->brightness = ctrl->value;
- au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
- ctrl->value - 128);
- break;
- case V4L2_CID_CONTRAST:
- state->contrast = ctrl->value;
- au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
- ctrl->value);
- break;
- case V4L2_CID_SATURATION:
- state->saturation = ctrl->value;
- au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
- ctrl->value);
- au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
- ctrl->value);
- break;
- case V4L2_CID_HUE:
- state->hue = ctrl->value;
- au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
- ctrl->value >> 8);
- au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
- ctrl->value & 0xFF);
- break;
- case V4L2_CID_AUDIO_VOLUME:
- case V4L2_CID_AUDIO_BASS:
- case V4L2_CID_AUDIO_TREBLE:
- case V4L2_CID_AUDIO_BALANCE:
- case V4L2_CID_AUDIO_MUTE:
- /* Not yet implemented */
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int au8522_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
-{
- struct au8522_state *state = to_state(sd);
-
- /* Note that we are using values cached in the state structure instead
- of reading the registers due to issues with i2c reads not working
- properly/consistently yet on the HVR-950q */
-
- switch (ctrl->id) {
- case V4L2_CID_BRIGHTNESS:
- ctrl->value = state->brightness;
- break;
- case V4L2_CID_CONTRAST:
- ctrl->value = state->contrast;
- break;
- case V4L2_CID_SATURATION:
- ctrl->value = state->saturation;
- break;
- case V4L2_CID_HUE:
- ctrl->value = state->hue;
- break;
- case V4L2_CID_AUDIO_VOLUME:
- case V4L2_CID_AUDIO_BASS:
- case V4L2_CID_AUDIO_TREBLE:
- case V4L2_CID_AUDIO_BALANCE:
- case V4L2_CID_AUDIO_MUTE:
- /* Not yet supported */
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* ----------------------------------------------------------------------- */
-
-#ifdef CONFIG_VIDEO_ADV_DEBUG
-static int au8522_g_register(struct v4l2_subdev *sd,
- struct v4l2_dbg_register *reg)
-{
- struct i2c_client *client = v4l2_get_subdevdata(sd);
- struct au8522_state *state = to_state(sd);
-
- if (!v4l2_chip_match_i2c_client(client, &reg->match))
- return -EINVAL;
- if (!capable(CAP_SYS_ADMIN))
- return -EPERM;
- reg->val = au8522_readreg(state, reg->reg & 0xffff);
- return 0;
-}
-
-static int au8522_s_register(struct v4l2_subdev *sd,
- struct v4l2_dbg_register *reg)
-{
- struct i2c_client *client = v4l2_get_subdevdata(sd);
- struct au8522_state *state = to_state(sd);
-
- if (!v4l2_chip_match_i2c_client(client, &reg->match))
- return -EINVAL;
- if (!capable(CAP_SYS_ADMIN))
- return -EPERM;
- au8522_writereg(state, reg->reg, reg->val & 0xff);
- return 0;
-}
-#endif
-
-static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
-{
- struct au8522_state *state = to_state(sd);
-
- if (enable) {
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
- 0x01);
- msleep(1);
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
- } else {
- /* This does not completely power down the device
- (it only reduces it from around 140ma to 80ma) */
- au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
- 1 << 5);
- }
- return 0;
-}
-
-static int au8522_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
-{
- switch (qc->id) {
- case V4L2_CID_CONTRAST:
- return v4l2_ctrl_query_fill(qc, 0, 255, 1,
- AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
- case V4L2_CID_BRIGHTNESS:
- return v4l2_ctrl_query_fill(qc, 0, 255, 1, 109);
- case V4L2_CID_SATURATION:
- return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
- case V4L2_CID_HUE:
- return v4l2_ctrl_query_fill(qc, -32768, 32768, 1, 0);
- default:
- break;
- }
-
- qc->type = 0;
- return -EINVAL;
-}
-
-static int au8522_reset(struct v4l2_subdev *sd, u32 val)
-{
- struct au8522_state *state = to_state(sd);
-
- state->operational_mode = AU8522_ANALOG_MODE;
-
- /* Clear out any state associated with the digital side of the
- chip, so that when it gets powered back up it won't think
- that it is already tuned */
- state->current_frequency = 0;
-
- au8522_writereg(state, 0xa4, 1 << 5);
-
- return 0;
-}
-
-static int au8522_s_video_routing(struct v4l2_subdev *sd,
- u32 input, u32 output, u32 config)
-{
- struct au8522_state *state = to_state(sd);
-
- au8522_reset(sd, 0);
-
- if (input == AU8522_COMPOSITE_CH1) {
- au8522_setup_cvbs_mode(state);
- } else if (input == AU8522_SVIDEO_CH13) {
- au8522_setup_svideo_mode(state);
- } else if (input == AU8522_COMPOSITE_CH4_SIF) {
- au8522_setup_cvbs_tuner_mode(state);
- } else {
- printk(KERN_ERR "au8522 mode not currently supported\n");
- return -EINVAL;
- }
- return 0;
-}
-
-static int au8522_s_audio_routing(struct v4l2_subdev *sd,
- u32 input, u32 output, u32 config)
-{
- struct au8522_state *state = to_state(sd);
- set_audio_input(state, input);
- return 0;
-}
-
-static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
-{
- int val = 0;
- struct au8522_state *state = to_state(sd);
- u8 lock_status;
-
- /* Interrogate the decoder to see if we are getting a real signal */
- lock_status = au8522_readreg(state, 0x00);
- if (lock_status == 0xa2)
- vt->signal = 0xffff;
- else
- vt->signal = 0x00;
-
- vt->capability |=
- V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
- V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
-
- val = V4L2_TUNER_SUB_MONO;
- vt->rxsubchans = val;
- vt->audmode = V4L2_TUNER_MODE_STEREO;
- return 0;
-}
-
-static int au8522_g_chip_ident(struct v4l2_subdev *sd,
- struct v4l2_dbg_chip_ident *chip)
-{
- struct au8522_state *state = to_state(sd);
- struct i2c_client *client = v4l2_get_subdevdata(sd);
-
- return v4l2_chip_ident_i2c_client(client, chip, state->id, state->rev);
-}
-
-static int au8522_log_status(struct v4l2_subdev *sd)
-{
- /* FIXME: Add some status info here */
- return 0;
-}
-
-/* ----------------------------------------------------------------------- */
-
-static const struct v4l2_subdev_core_ops au8522_core_ops = {
- .log_status = au8522_log_status,
- .g_chip_ident = au8522_g_chip_ident,
- .g_ctrl = au8522_g_ctrl,
- .s_ctrl = au8522_s_ctrl,
- .queryctrl = au8522_queryctrl,
- .reset = au8522_reset,
-#ifdef CONFIG_VIDEO_ADV_DEBUG
- .g_register = au8522_g_register,
- .s_register = au8522_s_register,
-#endif
-};
-
-static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
- .g_tuner = au8522_g_tuner,
-};
-
-static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
- .s_routing = au8522_s_audio_routing,
-};
-
-static const struct v4l2_subdev_video_ops au8522_video_ops = {
- .s_routing = au8522_s_video_routing,
- .s_stream = au8522_s_stream,
-};
-
-static const struct v4l2_subdev_ops au8522_ops = {
- .core = &au8522_core_ops,
- .tuner = &au8522_tuner_ops,
- .audio = &au8522_audio_ops,
- .video = &au8522_video_ops,
-};
-
-/* ----------------------------------------------------------------------- */
-
-static int au8522_probe(struct i2c_client *client,
- const struct i2c_device_id *did)
-{
- struct au8522_state *state;
- struct v4l2_subdev *sd;
- int instance;
- struct au8522_config *demod_config;
-
- /* Check if the adapter supports the needed features */
- if (!i2c_check_functionality(client->adapter,
- I2C_FUNC_SMBUS_BYTE_DATA)) {
- return -EIO;
- }
-
- /* allocate memory for the internal state */
- instance = au8522_get_state(&state, client->adapter, client->addr);
- switch (instance) {
- case 0:
- printk(KERN_ERR "au8522_decoder allocation failed\n");
- return -EIO;
- case 1:
- /* new demod instance */
- printk(KERN_INFO "au8522_decoder creating new instance...\n");
- break;
- default:
- /* existing demod instance */
- printk(KERN_INFO "au8522_decoder attach existing instance.\n");
- break;
- }
-
- demod_config = kzalloc(sizeof(struct au8522_config), GFP_KERNEL);
- if (demod_config == NULL) {
- if (instance == 1)
- kfree(state);
- return -ENOMEM;
- }
- demod_config->demod_address = 0x8e >> 1;
-
- state->config = demod_config;
- state->i2c = client->adapter;
-
- sd = &state->sd;
- v4l2_i2c_subdev_init(sd, client, &au8522_ops);
-
- state->c = client;
- state->vid_input = AU8522_COMPOSITE_CH1;
- state->aud_input = AU8522_AUDIO_NONE;
- state->id = 8522;
- state->rev = 0;
-
- /* Jam open the i2c gate to the tuner */
- au8522_writereg(state, 0x106, 1);
-
- return 0;
-}
-
-static int au8522_remove(struct i2c_client *client)
-{
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
- v4l2_device_unregister_subdev(sd);
- au8522_release_state(to_state(sd));
- return 0;
-}
-
-static const struct i2c_device_id au8522_id[] = {
- {"au8522", 0},
- {}
-};
-
-MODULE_DEVICE_TABLE(i2c, au8522_id);
-
-static struct i2c_driver au8522_driver = {
- .driver = {
- .owner = THIS_MODULE,
- .name = "au8522",
- },
- .probe = au8522_probe,
- .remove = au8522_remove,
- .id_table = au8522_id,
-};
-
-module_i2c_driver(au8522_driver);
diff --git a/drivers/media/dvb/frontends/au8522_dig.c b/drivers/media/dvb/frontends/au8522_dig.c
deleted file mode 100644
index a68974f6d70..00000000000
--- a/drivers/media/dvb/frontends/au8522_dig.c
+++ /dev/null
@@ -1,828 +0,0 @@
-/*
- Auvitek AU8522 QAM/8VSB demodulator driver
-
- Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include "dvb_frontend.h"
-#include "au8522.h"
-#include "au8522_priv.h"
-
-static int debug;
-
-#define dprintk(arg...)\
- do { if (debug)\
- printk(arg);\
- } while (0)
-
-struct mse2snr_tab {
- u16 val;
- u16 data;
-};
-
-/* VSB SNR lookup table */
-static struct mse2snr_tab vsb_mse2snr_tab[] = {
- { 0, 270 },
- { 2, 250 },
- { 3, 240 },
- { 5, 230 },
- { 7, 220 },
- { 9, 210 },
- { 12, 200 },
- { 13, 195 },
- { 15, 190 },
- { 17, 185 },
- { 19, 180 },
- { 21, 175 },
- { 24, 170 },
- { 27, 165 },
- { 31, 160 },
- { 32, 158 },
- { 33, 156 },
- { 36, 152 },
- { 37, 150 },
- { 39, 148 },
- { 40, 146 },
- { 41, 144 },
- { 43, 142 },
- { 44, 140 },
- { 48, 135 },
- { 50, 130 },
- { 43, 142 },
- { 53, 125 },
- { 56, 120 },
- { 256, 115 },
-};
-
-/* QAM64 SNR lookup table */
-static struct mse2snr_tab qam64_mse2snr_tab[] = {
- { 15, 0 },
- { 16, 290 },
- { 17, 288 },
- { 18, 286 },
- { 19, 284 },
- { 20, 282 },
- { 21, 281 },
- { 22, 279 },
- { 23, 277 },
- { 24, 275 },
- { 25, 273 },
- { 26, 271 },
- { 27, 269 },
- { 28, 268 },
- { 29, 266 },
- { 30, 264 },
- { 31, 262 },
- { 32, 260 },
- { 33, 259 },
- { 34, 258 },
- { 35, 256 },
- { 36, 255 },
- { 37, 254 },
- { 38, 252 },
- { 39, 251 },
- { 40, 250 },
- { 41, 249 },
- { 42, 248 },
- { 43, 246 },
- { 44, 245 },
- { 45, 244 },
- { 46, 242 },
- { 47, 241 },
- { 48, 240 },
- { 50, 239 },
- { 51, 238 },
- { 53, 237 },
- { 54, 236 },
- { 56, 235 },
- { 57, 234 },
- { 59, 233 },
- { 60, 232 },
- { 62, 231 },
- { 63, 230 },
- { 65, 229 },
- { 67, 228 },
- { 68, 227 },
- { 70, 226 },
- { 71, 225 },
- { 73, 224 },
- { 74, 223 },
- { 76, 222 },
- { 78, 221 },
- { 80, 220 },
- { 82, 219 },
- { 85, 218 },
- { 88, 217 },
- { 90, 216 },
- { 92, 215 },
- { 93, 214 },
- { 94, 212 },
- { 95, 211 },
- { 97, 210 },
- { 99, 209 },
- { 101, 208 },
- { 102, 207 },
- { 104, 206 },
- { 107, 205 },
- { 111, 204 },
- { 114, 203 },
- { 118, 202 },
- { 122, 201 },
- { 125, 200 },
- { 128, 199 },
- { 130, 198 },
- { 132, 197 },
- { 256, 190 },
-};
-
-/* QAM256 SNR lookup table */
-static struct mse2snr_tab qam256_mse2snr_tab[] = {
- { 15, 0 },
- { 16, 400 },
- { 17, 398 },
- { 18, 396 },
- { 19, 394 },
- { 20, 392 },
- { 21, 390 },
- { 22, 388 },
- { 23, 386 },
- { 24, 384 },
- { 25, 382 },
- { 26, 380 },
- { 27, 379 },
- { 28, 378 },
- { 29, 377 },
- { 30, 376 },
- { 31, 375 },
- { 32, 374 },
- { 33, 373 },
- { 34, 372 },
- { 35, 371 },
- { 36, 370 },
- { 37, 362 },
- { 38, 354 },
- { 39, 346 },
- { 40, 338 },
- { 41, 330 },
- { 42, 328 },
- { 43, 326 },
- { 44, 324 },
- { 45, 322 },
- { 46, 320 },
- { 47, 319 },
- { 48, 318 },
- { 49, 317 },
- { 50, 316 },
- { 51, 315 },
- { 52, 314 },
- { 53, 313 },
- { 54, 312 },
- { 55, 311 },
- { 56, 310 },
- { 57, 308 },
- { 58, 306 },
- { 59, 304 },
- { 60, 302 },
- { 61, 300 },
- { 62, 298 },
- { 65, 295 },
- { 68, 294 },
- { 70, 293 },
- { 73, 292 },
- { 76, 291 },
- { 78, 290 },
- { 79, 289 },
- { 81, 288 },
- { 82, 287 },
- { 83, 286 },
- { 84, 285 },
- { 85, 284 },
- { 86, 283 },
- { 88, 282 },
- { 89, 281 },
- { 256, 280 },
-};
-
-static int au8522_mse2snr_lookup(struct mse2snr_tab *tab, int sz, int mse,
- u16 *snr)
-{
- int i, ret = -EINVAL;
- dprintk("%s()\n", __func__);
-
- for (i = 0; i < sz; i++) {
- if (mse < tab[i].val) {
- *snr = tab[i].data;
- ret = 0;
- break;
- }
- }
- dprintk("%s() snr=%d\n", __func__, *snr);
- return ret;
-}
-
-static int au8522_set_if(struct dvb_frontend *fe, enum au8522_if_freq if_freq)
-{
- struct au8522_state *state = fe->demodulator_priv;
- u8 r0b5, r0b6, r0b7;
- char *ifmhz;
-
- switch (if_freq) {
- case AU8522_IF_3_25MHZ:
- ifmhz = "3.25";
- r0b5 = 0x00;
- r0b6 = 0x3d;
- r0b7 = 0xa0;
- break;
- case AU8522_IF_4MHZ:
- ifmhz = "4.00";
- r0b5 = 0x00;
- r0b6 = 0x4b;
- r0b7 = 0xd9;
- break;
- case AU8522_IF_6MHZ:
- ifmhz = "6.00";
- r0b5 = 0xfb;
- r0b6 = 0x8e;
- r0b7 = 0x39;
- break;
- default:
- dprintk("%s() IF Frequency not supported\n", __func__);
- return -EINVAL;
- }
- dprintk("%s() %s MHz\n", __func__, ifmhz);
- au8522_writereg(state, 0x80b5, r0b5);
- au8522_writereg(state, 0x80b6, r0b6);
- au8522_writereg(state, 0x80b7, r0b7);
-
- return 0;
-}
-
-/* VSB Modulation table */
-static struct {
- u16 reg;
- u16 data;
-} VSB_mod_tab[] = {
- { 0x8090, 0x84 },
- { 0x4092, 0x11 },
- { 0x2005, 0x00 },
- { 0x8091, 0x80 },
- { 0x80a3, 0x0c },
- { 0x80a4, 0xe8 },
- { 0x8081, 0xc4 },
- { 0x80a5, 0x40 },
- { 0x80a7, 0x40 },
- { 0x80a6, 0x67 },
- { 0x8262, 0x20 },
- { 0x821c, 0x30 },
- { 0x80d8, 0x1a },
- { 0x8227, 0xa0 },
- { 0x8121, 0xff },
- { 0x80a8, 0xf0 },
- { 0x80a9, 0x05 },
- { 0x80aa, 0x77 },
- { 0x80ab, 0xf0 },
- { 0x80ac, 0x05 },
- { 0x80ad, 0x77 },
- { 0x80ae, 0x41 },
- { 0x80af, 0x66 },
- { 0x821b, 0xcc },
- { 0x821d, 0x80 },
- { 0x80a4, 0xe8 },
- { 0x8231, 0x13 },
-};
-
-/* QAM64 Modulation table */
-static struct {
- u16 reg;
- u16 data;
-} QAM64_mod_tab[] = {
- { 0x00a3, 0x09 },
- { 0x00a4, 0x00 },
- { 0x0081, 0xc4 },
- { 0x00a5, 0x40 },
- { 0x00aa, 0x77 },
- { 0x00ad, 0x77 },
- { 0x00a6, 0x67 },
- { 0x0262, 0x20 },
- { 0x021c, 0x30 },
- { 0x00b8, 0x3e },
- { 0x00b9, 0xf0 },
- { 0x00ba, 0x01 },
- { 0x00bb, 0x18 },
- { 0x00bc, 0x50 },
- { 0x00bd, 0x00 },
- { 0x00be, 0xea },
- { 0x00bf, 0xef },
- { 0x00c0, 0xfc },
- { 0x00c1, 0xbd },
- { 0x00c2, 0x1f },
- { 0x00c3, 0xfc },
- { 0x00c4, 0xdd },
- { 0x00c5, 0xaf },
- { 0x00c6, 0x00 },
- { 0x00c7, 0x38 },
- { 0x00c8, 0x30 },
- { 0x00c9, 0x05 },
- { 0x00ca, 0x4a },
- { 0x00cb, 0xd0 },
- { 0x00cc, 0x01 },
- { 0x00cd, 0xd9 },
- { 0x00ce, 0x6f },
- { 0x00cf, 0xf9 },
- { 0x00d0, 0x70 },
- { 0x00d1, 0xdf },
- { 0x00d2, 0xf7 },
- { 0x00d3, 0xc2 },
- { 0x00d4, 0xdf },
- { 0x00d5, 0x02 },
- { 0x00d6, 0x9a },
- { 0x00d7, 0xd0 },
- { 0x0250, 0x0d },
- { 0x0251, 0xcd },
- { 0x0252, 0xe0 },
- { 0x0253, 0x05 },
- { 0x0254, 0xa7 },
- { 0x0255, 0xff },
- { 0x0256, 0xed },
- { 0x0257, 0x5b },
- { 0x0258, 0xae },
- { 0x0259, 0xe6 },
- { 0x025a, 0x3d },
- { 0x025b, 0x0f },
- { 0x025c, 0x0d },
- { 0x025d, 0xea },
- { 0x025e, 0xf2 },
- { 0x025f, 0x51 },
- { 0x0260, 0xf5 },
- { 0x0261, 0x06 },
- { 0x021a, 0x00 },
- { 0x0546, 0x40 },
- { 0x0210, 0xc7 },
- { 0x0211, 0xaa },
- { 0x0212, 0xab },
- { 0x0213, 0x02 },
- { 0x0502, 0x00 },
- { 0x0121, 0x04 },
- { 0x0122, 0x04 },
- { 0x052e, 0x10 },
- { 0x00a4, 0xca },
- { 0x00a7, 0x40 },
- { 0x0526, 0x01 },
-};
-
-/* QAM256 Modulation table */
-static struct {
- u16 reg;
- u16 data;
-} QAM256_mod_tab[] = {
- { 0x80a3, 0x09 },
- { 0x80a4, 0x00 },
- { 0x8081, 0xc4 },
- { 0x80a5, 0x40 },
- { 0x80aa, 0x77 },
- { 0x80ad, 0x77 },
- { 0x80a6, 0x67 },
- { 0x8262, 0x20 },
- { 0x821c, 0x30 },
- { 0x80b8, 0x3e },
- { 0x80b9, 0xf0 },
- { 0x80ba, 0x01 },
- { 0x80bb, 0x18 },
- { 0x80bc, 0x50 },
- { 0x80bd, 0x00 },
- { 0x80be, 0xea },
- { 0x80bf, 0xef },
- { 0x80c0, 0xfc },
- { 0x80c1, 0xbd },
- { 0x80c2, 0x1f },
- { 0x80c3, 0xfc },
- { 0x80c4, 0xdd },
- { 0x80c5, 0xaf },
- { 0x80c6, 0x00 },
- { 0x80c7, 0x38 },
- { 0x80c8, 0x30 },
- { 0x80c9, 0x05 },
- { 0x80ca, 0x4a },
- { 0x80cb, 0xd0 },
- { 0x80cc, 0x01 },
- { 0x80cd, 0xd9 },
- { 0x80ce, 0x6f },
- { 0x80cf, 0xf9 },
- { 0x80d0, 0x70 },
- { 0x80d1, 0xdf },
- { 0x80d2, 0xf7 },
- { 0x80d3, 0xc2 },
- { 0x80d4, 0xdf },
- { 0x80d5, 0x02 },
- { 0x80d6, 0x9a },
- { 0x80d7, 0xd0 },
- { 0x8250, 0x0d },
- { 0x8251, 0xcd },
- { 0x8252, 0xe0 },
- { 0x8253, 0x05 },
- { 0x8254, 0xa7 },
- { 0x8255, 0xff },
- { 0x8256, 0xed },
- { 0x8257, 0x5b },
- { 0x8258, 0xae },
- { 0x8259, 0xe6 },
- { 0x825a, 0x3d },
- { 0x825b, 0x0f },
- { 0x825c, 0x0d },
- { 0x825d, 0xea },
- { 0x825e, 0xf2 },
- { 0x825f, 0x51 },
- { 0x8260, 0xf5 },
- { 0x8261, 0x06 },
- { 0x821a, 0x00 },
- { 0x8546, 0x40 },
- { 0x8210, 0x26 },
- { 0x8211, 0xf6 },
- { 0x8212, 0x84 },
- { 0x8213, 0x02 },
- { 0x8502, 0x01 },
- { 0x8121, 0x04 },
- { 0x8122, 0x04 },
- { 0x852e, 0x10 },
- { 0x80a4, 0xca },
- { 0x80a7, 0x40 },
- { 0x8526, 0x01 },
-};
-
-static int au8522_enable_modulation(struct dvb_frontend *fe,
- fe_modulation_t m)
-{
- struct au8522_state *state = fe->demodulator_priv;
- int i;
-
- dprintk("%s(0x%08x)\n", __func__, m);
-
- switch (m) {
- case VSB_8:
- dprintk("%s() VSB_8\n", __func__);
- for (i = 0; i < ARRAY_SIZE(VSB_mod_tab); i++)
- au8522_writereg(state,
- VSB_mod_tab[i].reg,
- VSB_mod_tab[i].data);
- au8522_set_if(fe, state->config->vsb_if);
- break;
- case QAM_64:
- dprintk("%s() QAM 64\n", __func__);
- for (i = 0; i < ARRAY_SIZE(QAM64_mod_tab); i++)
- au8522_writereg(state,
- QAM64_mod_tab[i].reg,
- QAM64_mod_tab[i].data);
- au8522_set_if(fe, state->config->qam_if);
- break;
- case QAM_256:
- dprintk("%s() QAM 256\n", __func__);
- for (i = 0; i < ARRAY_SIZE(QAM256_mod_tab); i++)
- au8522_writereg(state,
- QAM256_mod_tab[i].reg,
- QAM256_mod_tab[i].data);
- au8522_set_if(fe, state->config->qam_if);
- break;
- default:
- dprintk("%s() Invalid modulation\n", __func__);
- return -EINVAL;
- }
-
- state->current_modulation = m;
-
- return 0;
-}
-
-/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
-static int au8522_set_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct au8522_state *state = fe->demodulator_priv;
- int ret = -EINVAL;
-
- dprintk("%s(frequency=%d)\n", __func__, c->frequency);
-
- if ((state->current_frequency == c->frequency) &&
- (state->current_modulation == c->modulation))
- return 0;
-
- if (fe->ops.tuner_ops.set_params) {
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
- ret = fe->ops.tuner_ops.set_params(fe);
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 0);
- }
-
- if (ret < 0)
- return ret;
-
- /* Allow the tuner to settle */
- msleep(100);
-
- au8522_enable_modulation(fe, c->modulation);
-
- state->current_frequency = c->frequency;
-
- return 0;
-}
-
-static int au8522_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct au8522_state *state = fe->demodulator_priv;
- u8 reg;
- u32 tuner_status = 0;
-
- *status = 0;
-
- if (state->current_modulation == VSB_8) {
- dprintk("%s() Checking VSB_8\n", __func__);
- reg = au8522_readreg(state, 0x4088);
- if ((reg & 0x03) == 0x03)
- *status |= FE_HAS_LOCK | FE_HAS_SYNC | FE_HAS_VITERBI;
- } else {
- dprintk("%s() Checking QAM\n", __func__);
- reg = au8522_readreg(state, 0x4541);
- if (reg & 0x80)
- *status |= FE_HAS_VITERBI;
- if (reg & 0x20)
- *status |= FE_HAS_LOCK | FE_HAS_SYNC;
- }
-
- switch (state->config->status_mode) {
- case AU8522_DEMODLOCKING:
- dprintk("%s() DEMODLOCKING\n", __func__);
- if (*status & FE_HAS_VITERBI)
- *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
- break;
- case AU8522_TUNERLOCKING:
- /* Get the tuner status */
- dprintk("%s() TUNERLOCKING\n", __func__);
- if (fe->ops.tuner_ops.get_status) {
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
-
- fe->ops.tuner_ops.get_status(fe, &tuner_status);
-
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 0);
- }
- if (tuner_status)
- *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
- break;
- }
- state->fe_status = *status;
-
- if (*status & FE_HAS_LOCK)
- /* turn on LED, if it isn't on already */
- au8522_led_ctrl(state, -1);
- else
- /* turn off LED */
- au8522_led_ctrl(state, 0);
-
- dprintk("%s() status 0x%08x\n", __func__, *status);
-
- return 0;
-}
-
-static int au8522_led_status(struct au8522_state *state, const u16 *snr)
-{
- struct au8522_led_config *led_config = state->config->led_cfg;
- int led;
- u16 strong;
-
- /* bail out if we can't control an LED */
- if (!led_config)
- return 0;
-
- if (0 == (state->fe_status & FE_HAS_LOCK))
- return au8522_led_ctrl(state, 0);
- else if (state->current_modulation == QAM_256)
- strong = led_config->qam256_strong;
- else if (state->current_modulation == QAM_64)
- strong = led_config->qam64_strong;
- else /* (state->current_modulation == VSB_8) */
- strong = led_config->vsb8_strong;
-
- if (*snr >= strong)
- led = 2;
- else
- led = 1;
-
- if ((state->led_state) &&
- (((strong < *snr) ? (*snr - strong) : (strong - *snr)) <= 10))
- /* snr didn't change enough to bother
- * changing the color of the led */
- return 0;
-
- return au8522_led_ctrl(state, led);
-}
-
-static int au8522_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- struct au8522_state *state = fe->demodulator_priv;
- int ret = -EINVAL;
-
- dprintk("%s()\n", __func__);
-
- if (state->current_modulation == QAM_256)
- ret = au8522_mse2snr_lookup(qam256_mse2snr_tab,
- ARRAY_SIZE(qam256_mse2snr_tab),
- au8522_readreg(state, 0x4522),
- snr);
- else if (state->current_modulation == QAM_64)
- ret = au8522_mse2snr_lookup(qam64_mse2snr_tab,
- ARRAY_SIZE(qam64_mse2snr_tab),
- au8522_readreg(state, 0x4522),
- snr);
- else /* VSB_8 */
- ret = au8522_mse2snr_lookup(vsb_mse2snr_tab,
- ARRAY_SIZE(vsb_mse2snr_tab),
- au8522_readreg(state, 0x4311),
- snr);
-
- if (state->config->led_cfg)
- au8522_led_status(state, snr);
-
- return ret;
-}
-
-static int au8522_read_signal_strength(struct dvb_frontend *fe,
- u16 *signal_strength)
-{
- /* borrowed from lgdt330x.c
- *
- * Calculate strength from SNR up to 35dB
- * Even though the SNR can go higher than 35dB,
- * there is some comfort factor in having a range of
- * strong signals that can show at 100%
- */
- u16 snr;
- u32 tmp;
- int ret = au8522_read_snr(fe, &snr);
-
- *signal_strength = 0;
-
- if (0 == ret) {
- /* The following calculation method was chosen
- * purely for the sake of code re-use from the
- * other demod drivers that use this method */
-
- /* Convert from SNR in dB * 10 to 8.24 fixed-point */
- tmp = (snr * ((1 << 24) / 10));
-
- /* Convert from 8.24 fixed-point to
- * scale the range 0 - 35*2^24 into 0 - 65535*/
- if (tmp >= 8960 * 0x10000)
- *signal_strength = 0xffff;
- else
- *signal_strength = tmp / 8960;
- }
-
- return ret;
-}
-
-static int au8522_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- struct au8522_state *state = fe->demodulator_priv;
-
- if (state->current_modulation == VSB_8)
- *ucblocks = au8522_readreg(state, 0x4087);
- else
- *ucblocks = au8522_readreg(state, 0x4543);
-
- return 0;
-}
-
-static int au8522_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- return au8522_read_ucblocks(fe, ber);
-}
-
-static int au8522_get_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct au8522_state *state = fe->demodulator_priv;
-
- c->frequency = state->current_frequency;
- c->modulation = state->current_modulation;
-
- return 0;
-}
-
-static int au8522_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *tune)
-{
- tune->min_delay_ms = 1000;
- return 0;
-}
-
-static struct dvb_frontend_ops au8522_ops;
-
-
-static void au8522_release(struct dvb_frontend *fe)
-{
- struct au8522_state *state = fe->demodulator_priv;
- au8522_release_state(state);
-}
-
-struct dvb_frontend *au8522_attach(const struct au8522_config *config,
- struct i2c_adapter *i2c)
-{
- struct au8522_state *state = NULL;
- int instance;
-
- /* allocate memory for the internal state */
- instance = au8522_get_state(&state, i2c, config->demod_address);
- switch (instance) {
- case 0:
- dprintk("%s state allocation failed\n", __func__);
- break;
- case 1:
- /* new demod instance */
- dprintk("%s using new instance\n", __func__);
- break;
- default:
- /* existing demod instance */
- dprintk("%s using existing instance\n", __func__);
- break;
- }
-
- /* setup the state */
- state->config = config;
- state->i2c = i2c;
- state->operational_mode = AU8522_DIGITAL_MODE;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &au8522_ops,
- sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
-
- state->frontend.ops.analog_ops.i2c_gate_ctrl = au8522_analog_i2c_gate_ctrl;
-
- if (au8522_init(&state->frontend) != 0) {
- printk(KERN_ERR "%s: Failed to initialize correctly\n",
- __func__);
- goto error;
- }
-
- /* Note: Leaving the I2C gate open here. */
- au8522_i2c_gate_ctrl(&state->frontend, 1);
-
- return &state->frontend;
-
-error:
- au8522_release_state(state);
- return NULL;
-}
-EXPORT_SYMBOL(au8522_attach);
-
-static struct dvb_frontend_ops au8522_ops = {
- .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
- .info = {
- .name = "Auvitek AU8522 QAM/8VSB Frontend",
- .frequency_min = 54000000,
- .frequency_max = 858000000,
- .frequency_stepsize = 62500,
- .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
- },
-
- .init = au8522_init,
- .sleep = au8522_sleep,
- .i2c_gate_ctrl = au8522_i2c_gate_ctrl,
- .set_frontend = au8522_set_frontend,
- .get_frontend = au8522_get_frontend,
- .get_tune_settings = au8522_get_tune_settings,
- .read_status = au8522_read_status,
- .read_ber = au8522_read_ber,
- .read_signal_strength = au8522_read_signal_strength,
- .read_snr = au8522_read_snr,
- .read_ucblocks = au8522_read_ucblocks,
- .release = au8522_release,
-};
-
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Enable verbose debug messages");
-
-MODULE_DESCRIPTION("Auvitek AU8522 QAM-B/ATSC Demodulator driver");
-MODULE_AUTHOR("Steven Toth");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/au8522_priv.h b/drivers/media/dvb/frontends/au8522_priv.h
deleted file mode 100644
index 0529699a27b..00000000000
--- a/drivers/media/dvb/frontends/au8522_priv.h
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- Auvitek AU8522 QAM/8VSB demodulator driver
-
- Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
- Copyright (C) 2008 Devin Heitmueller <dheitmueller@linuxtv.org>
- Copyright (C) 2005-2008 Auvitek International, Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/videodev2.h>
-#include <media/v4l2-device.h>
-#include <linux/i2c.h>
-#include "dvb_frontend.h"
-#include "au8522.h"
-#include "tuner-i2c.h"
-
-#define AU8522_ANALOG_MODE 0
-#define AU8522_DIGITAL_MODE 1
-
-struct au8522_state {
- struct i2c_client *c;
- struct i2c_adapter *i2c;
-
- u8 operational_mode;
-
- /* Used for sharing of the state between analog and digital mode */
- struct tuner_i2c_props i2c_props;
- struct list_head hybrid_tuner_instance_list;
-
- /* configuration settings */
- const struct au8522_config *config;
-
- struct dvb_frontend frontend;
-
- u32 current_frequency;
- fe_modulation_t current_modulation;
-
- u32 fe_status;
- unsigned int led_state;
-
- /* Analog settings */
- struct v4l2_subdev sd;
- v4l2_std_id std;
- int vid_input;
- int aud_input;
- u32 id;
- u32 rev;
- u8 brightness;
- u8 contrast;
- u8 saturation;
- s16 hue;
-};
-
-/* These are routines shared by both the VSB/QAM demodulator and the analog
- decoder */
-int au8522_writereg(struct au8522_state *state, u16 reg, u8 data);
-u8 au8522_readreg(struct au8522_state *state, u16 reg);
-int au8522_init(struct dvb_frontend *fe);
-int au8522_sleep(struct dvb_frontend *fe);
-
-int au8522_get_state(struct au8522_state **state, struct i2c_adapter *i2c,
- u8 client_address);
-void au8522_release_state(struct au8522_state *state);
-int au8522_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
-int au8522_analog_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
-int au8522_led_ctrl(struct au8522_state *state, int led);
-
-/* REGISTERS */
-#define AU8522_INPUT_CONTROL_REG081H 0x081
-#define AU8522_PGA_CONTROL_REG082H 0x082
-#define AU8522_CLAMPING_CONTROL_REG083H 0x083
-
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H 0x0A3
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H 0x0A4
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5
-#define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6
-#define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7
-#define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8
-#define AU8522_TUNER_AGC_RF_START_REG0A9H 0x0A9
-#define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH 0x0AA
-#define AU8522_TUNER_AGC_IF_STOP_REG0ABH 0x0AB
-#define AU8522_TUNER_AGC_IF_START_REG0ACH 0x0AC
-#define AU8522_TUNER_AGC_IF_DEFAULT_REG0ADH 0x0AD
-#define AU8522_TUNER_AGC_STEP_REG0AEH 0x0AE
-#define AU8522_TUNER_GAIN_STEP_REG0AFH 0x0AF
-
-/* Receiver registers */
-#define AU8522_FRMREGTHRD1_REG0B0H 0x0B0
-#define AU8522_FRMREGAGC1H_REG0B1H 0x0B1
-#define AU8522_FRMREGSHIFT1_REG0B2H 0x0B2
-#define AU8522_TOREGAGC1_REG0B3H 0x0B3
-#define AU8522_TOREGASHIFT1_REG0B4H 0x0B4
-#define AU8522_FRMREGBBH_REG0B5H 0x0B5
-#define AU8522_FRMREGBBM_REG0B6H 0x0B6
-#define AU8522_FRMREGBBL_REG0B7H 0x0B7
-/* 0xB8 TO 0xD7 are the filter coefficients */
-#define AU8522_FRMREGTHRD2_REG0D8H 0x0D8
-#define AU8522_FRMREGAGC2H_REG0D9H 0x0D9
-#define AU8522_TOREGAGC2_REG0DAH 0x0DA
-#define AU8522_TOREGSHIFT2_REG0DBH 0x0DB
-#define AU8522_FRMREGPILOTH_REG0DCH 0x0DC
-#define AU8522_FRMREGPILOTM_REG0DDH 0x0DD
-#define AU8522_FRMREGPILOTL_REG0DEH 0x0DE
-#define AU8522_TOREGFREQ_REG0DFH 0x0DF
-
-#define AU8522_RX_PGA_RFOUT_REG0EBH 0x0EB
-#define AU8522_RX_PGA_IFOUT_REG0ECH 0x0EC
-#define AU8522_RX_PGA_PGAOUT_REG0EDH 0x0ED
-
-#define AU8522_CHIP_MODE_REG0FEH 0x0FE
-
-/* I2C bus control registers */
-#define AU8522_I2C_CONTROL_REG0_REG090H 0x090
-#define AU8522_I2C_CONTROL_REG1_REG091H 0x091
-#define AU8522_I2C_STATUS_REG092H 0x092
-#define AU8522_I2C_WR_DATA0_REG093H 0x093
-#define AU8522_I2C_WR_DATA1_REG094H 0x094
-#define AU8522_I2C_WR_DATA2_REG095H 0x095
-#define AU8522_I2C_WR_DATA3_REG096H 0x096
-#define AU8522_I2C_WR_DATA4_REG097H 0x097
-#define AU8522_I2C_WR_DATA5_REG098H 0x098
-#define AU8522_I2C_WR_DATA6_REG099H 0x099
-#define AU8522_I2C_WR_DATA7_REG09AH 0x09A
-#define AU8522_I2C_RD_DATA0_REG09BH 0x09B
-#define AU8522_I2C_RD_DATA1_REG09CH 0x09C
-#define AU8522_I2C_RD_DATA2_REG09DH 0x09D
-#define AU8522_I2C_RD_DATA3_REG09EH 0x09E
-#define AU8522_I2C_RD_DATA4_REG09FH 0x09F
-#define AU8522_I2C_RD_DATA5_REG0A0H 0x0A0
-#define AU8522_I2C_RD_DATA6_REG0A1H 0x0A1
-#define AU8522_I2C_RD_DATA7_REG0A2H 0x0A2
-
-#define AU8522_ENA_USB_REG101H 0x101
-
-#define AU8522_I2S_CTRL_0_REG110H 0x110
-#define AU8522_I2S_CTRL_1_REG111H 0x111
-#define AU8522_I2S_CTRL_2_REG112H 0x112
-
-#define AU8522_FRMREGFFECONTROL_REG121H 0x121
-#define AU8522_FRMREGDFECONTROL_REG122H 0x122
-
-#define AU8522_CARRFREQOFFSET0_REG201H 0x201
-#define AU8522_CARRFREQOFFSET1_REG202H 0x202
-
-#define AU8522_DECIMATION_GAIN_REG21AH 0x21A
-#define AU8522_FRMREGIFSLP_REG21BH 0x21B
-#define AU8522_FRMREGTHRDL2_REG21CH 0x21C
-#define AU8522_FRMREGSTEP3DB_REG21DH 0x21D
-#define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH 0x21E
-#define AU8522_FRMREGPLLMODE_REG21FH 0x21F
-#define AU8522_FRMREGCSTHRD_REG220H 0x220
-#define AU8522_FRMREGCRLOCKDMAX_REG221H 0x221
-#define AU8522_FRMREGCRPERIODMASK_REG222H 0x222
-#define AU8522_FRMREGCRLOCK0THH_REG223H 0x223
-#define AU8522_FRMREGCRLOCK1THH_REG224H 0x224
-#define AU8522_FRMREGCRLOCK0THL_REG225H 0x225
-#define AU8522_FRMREGCRLOCK1THL_REG226H 0x226
-#define AU_FRMREGPLLACQPHASESCL_REG227H 0x227
-#define AU8522_FRMREGFREQFBCTRL_REG228H 0x228
-
-/* Analog TV Decoder */
-#define AU8522_TVDEC_STATUS_REG000H 0x000
-#define AU8522_TVDEC_INT_STATUS_REG001H 0x001
-#define AU8522_TVDEC_MACROVISION_STATUS_REG002H 0x002
-#define AU8522_TVDEC_SHARPNESSREG009H 0x009
-#define AU8522_TVDEC_BRIGHTNESS_REG00AH 0x00A
-#define AU8522_TVDEC_CONTRAST_REG00BH 0x00B
-#define AU8522_TVDEC_SATURATION_CB_REG00CH 0x00C
-#define AU8522_TVDEC_SATURATION_CR_REG00DH 0x00D
-#define AU8522_TVDEC_HUE_H_REG00EH 0x00E
-#define AU8522_TVDEC_HUE_L_REG00FH 0x00F
-#define AU8522_TVDEC_INT_MASK_REG010H 0x010
-#define AU8522_VIDEO_MODE_REG011H 0x011
-#define AU8522_TVDEC_PGA_REG012H 0x012
-#define AU8522_TVDEC_COMB_MODE_REG015H 0x015
-#define AU8522_REG016H 0x016
-#define AU8522_TVDED_DBG_MODE_REG060H 0x060
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H 0x061
-#define AU8522_TVDEC_FORMAT_CTRL2_REG062H 0x062
-#define AU8522_TVDEC_VCR_DET_LLIM_REG063H 0x063
-#define AU8522_TVDEC_VCR_DET_HLIM_REG064H 0x064
-#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H 0x065
-#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H 0x066
-#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H 0x067
-#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H 0x068
-#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H 0x069
-#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH 0x06A
-#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH 0x06B
-#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH 0x06C
-#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 0x06D
-#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH 0x06E
-#define AU8522_TVDEC_UV_SEP_THR_REG06FH 0x06F
-#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H 0x070
-#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H 0x073
-#define AU8522_TVDEC_DCAGC_CTRL_REG077H 0x077
-#define AU8522_TVDEC_PIC_START_ADJ_REG078H 0x078
-#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H 0x079
-#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH 0x07A
-#define AU8522_TVDEC_INTRP_CTRL_REG07BH 0x07B
-#define AU8522_TVDEC_PLL_STATUS_REG07EH 0x07E
-#define AU8522_TVDEC_FSC_FREQ_REG07FH 0x07F
-
-#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H 0x0E4
-#define AU8522_TOREGAAGC_REG0E5H 0x0E5
-
-#define AU8522_TVDEC_CHROMA_AGC_REG401H 0x401
-#define AU8522_TVDEC_CHROMA_SFT_REG402H 0x402
-#define AU8522_FILTER_COEF_R410 0x410
-#define AU8522_FILTER_COEF_R411 0x411
-#define AU8522_FILTER_COEF_R412 0x412
-#define AU8522_FILTER_COEF_R413 0x413
-#define AU8522_FILTER_COEF_R414 0x414
-#define AU8522_FILTER_COEF_R415 0x415
-#define AU8522_FILTER_COEF_R416 0x416
-#define AU8522_FILTER_COEF_R417 0x417
-#define AU8522_FILTER_COEF_R418 0x418
-#define AU8522_FILTER_COEF_R419 0x419
-#define AU8522_FILTER_COEF_R41A 0x41A
-#define AU8522_FILTER_COEF_R41B 0x41B
-#define AU8522_FILTER_COEF_R41C 0x41C
-#define AU8522_FILTER_COEF_R41D 0x41D
-#define AU8522_FILTER_COEF_R41E 0x41E
-#define AU8522_FILTER_COEF_R41F 0x41F
-#define AU8522_FILTER_COEF_R420 0x420
-#define AU8522_FILTER_COEF_R421 0x421
-#define AU8522_FILTER_COEF_R422 0x422
-#define AU8522_FILTER_COEF_R423 0x423
-#define AU8522_FILTER_COEF_R424 0x424
-#define AU8522_FILTER_COEF_R425 0x425
-#define AU8522_FILTER_COEF_R426 0x426
-#define AU8522_FILTER_COEF_R427 0x427
-#define AU8522_FILTER_COEF_R428 0x428
-#define AU8522_FILTER_COEF_R429 0x429
-#define AU8522_FILTER_COEF_R42A 0x42A
-#define AU8522_FILTER_COEF_R42B 0x42B
-#define AU8522_FILTER_COEF_R42C 0x42C
-#define AU8522_FILTER_COEF_R42D 0x42D
-
-/* VBI Control Registers */
-#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H 0x004
-#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H 0x005
-#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H 0x006
-#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H 0x007
-#define AU8522_TVDEC_VBI_CTRL_H_REG017H 0x017
-#define AU8522_TVDEC_VBI_CTRL_L_REG018H 0x018
-#define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H 0x019
-#define AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH 0x01A
-#define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH 0x01B
-#define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH 0x01C
-#define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH 0x01E
-#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH 0x01F
-#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H 0x020
-#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 0x021
-#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H 0x022
-#define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H 0x023
-
-#define AU8522_REG071H 0x071
-#define AU8522_REG072H 0x072
-#define AU8522_REG074H 0x074
-#define AU8522_REG075H 0x075
-
-/* Digital Demodulator Registers */
-#define AU8522_FRAME_COUNT0_REG084H 0x084
-#define AU8522_RS_STATUS_G0_REG085H 0x085
-#define AU8522_RS_STATUS_B0_REG086H 0x086
-#define AU8522_RS_STATUS_E_REG087H 0x087
-#define AU8522_DEMODULATION_STATUS_REG088H 0x088
-#define AU8522_TOREGTRESTATUS_REG0E6H 0x0E6
-#define AU8522_TSPORT_CONTROL_REG10BH 0x10B
-#define AU8522_TSTHES_REG10CH 0x10C
-#define AU8522_FRMREGDFEKEEP_REG301H 0x301
-#define AU8522_DFE_AVERAGE_REG302H 0x302
-#define AU8522_FRMREGEQLERRWIN_REG303H 0x303
-#define AU8522_FRMREGFFEKEEP_REG304H 0x304
-#define AU8522_FRMREGDFECONTROL1_REG305H 0x305
-#define AU8522_FRMREGEQLERRLOW_REG306H 0x306
-
-#define AU8522_REG42EH 0x42E
-#define AU8522_REG42FH 0x42F
-#define AU8522_REG430H 0x430
-#define AU8522_REG431H 0x431
-#define AU8522_REG432H 0x432
-#define AU8522_REG433H 0x433
-#define AU8522_REG434H 0x434
-#define AU8522_REG435H 0x435
-#define AU8522_REG436H 0x436
-
-/* GPIO Registers */
-#define AU8522_GPIO_CONTROL_REG0E0H 0x0E0
-#define AU8522_GPIO_STATUS_REG0E1H 0x0E1
-#define AU8522_GPIO_DATA_REG0E2H 0x0E2
-
-/* Audio Control Registers */
-#define AU8522_AUDIOAGC_REG0EEH 0x0EE
-#define AU8522_AUDIO_STATUS_REG0F0H 0x0F0
-#define AU8522_AUDIO_MODE_REG0F1H 0x0F1
-#define AU8522_AUDIO_VOLUME_L_REG0F2H 0x0F2
-#define AU8522_AUDIO_VOLUME_R_REG0F3H 0x0F3
-#define AU8522_AUDIO_VOLUME_REG0F4H 0x0F4
-#define AU8522_FRMREGAUPHASE_REG0F7H 0x0F7
-#define AU8522_REG0F9H 0x0F9
-
-#define AU8522_AUDIOAGC2_REG605H 0x605
-#define AU8522_AUDIOFREQ_REG606H 0x606
-
-
-/**************************************************************/
-
-/* Format control 1 */
-
-/* VCR Mode 7-6 */
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_YES 0x80
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_NO 0x40
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_AUTO 0x00
-/* Field len 5-4 */
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_625 0x20
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 0x10
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_AUTO 0x00
-/* Line len (us) 3-2 */
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_64_000 0x0b
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 0x08
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_556 0x04
-/* Subcarrier freq 1-0 */
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO 0x03
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_443 0x02
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN 0x01
-#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_50 0x00
-
-/* Format control 2 */
-#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_AUTODETECT 0x00
-#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC 0x01
-
-
-#define AU8522_INPUT_CONTROL_REG081H_ATSC 0xC4
-#define AU8522_INPUT_CONTROL_REG081H_ATVRF 0xC4
-#define AU8522_INPUT_CONTROL_REG081H_ATVRF13 0xC4
-#define AU8522_INPUT_CONTROL_REG081H_J83B64 0xC4
-#define AU8522_INPUT_CONTROL_REG081H_J83B256 0xC4
-#define AU8522_INPUT_CONTROL_REG081H_CVBS 0x20
-#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1 0xA2
-#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2 0xA0
-#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3 0x69
-#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4 0x68
-#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF 0x28
-/* CH1 AS Y,CH3 AS C */
-#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 0x23
-/* CH2 AS Y,CH4 AS C */
-#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24 0x20
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC 0x0C
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64 0x09
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256 0x09
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS 0x12
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF 0x1A
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13 0x1A
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO 0x02
-
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR 0x00
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO 0x9C
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS 0x9D
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC 0xE8
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 0xCA
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64 0xCA
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF 0xDD
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13 0xDD
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL 0xDD
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM 0xDD
-
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC 0x80
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 0x80
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64 0x80
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC 0x40
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256 0x40
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64 0x40
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR 0x00
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF 0x01
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13 0x01
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO 0x04
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS 0x01
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM 0x03
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS 0x09
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL 0x01
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM 0x01
-
-/* STILL NEED TO BE REFACTORED @@@@@@@@@@@@@@ */
-#define AU8522_TVDEC_CONTRAST_REG00BH_CVBS 0x79
-#define AU8522_TVDEC_SATURATION_CB_REG00CH_CVBS 0x80
-#define AU8522_TVDEC_SATURATION_CR_REG00DH_CVBS 0x80
-#define AU8522_TVDEC_HUE_H_REG00EH_CVBS 0x00
-#define AU8522_TVDEC_HUE_L_REG00FH_CVBS 0x00
-#define AU8522_TVDEC_PGA_REG012H_CVBS 0x0F
-#define AU8522_TVDEC_COMB_MODE_REG015H_CVBS 0x00
-#define AU8522_REG016H_CVBS 0x00
-#define AU8522_TVDED_DBG_MODE_REG060H_CVBS 0x00
-#define AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS 0x19
-#define AU8522_REG0F9H_AUDIO 0x20
-#define AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS 0xA7
-#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS 0x0A
-#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS 0x32
-#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS 0x19
-#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS 0x23
-#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS 0x41
-#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS 0x0A
-#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS 0x32
-#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS 0x34
-#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO 0x2a
-#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS 0x05
-#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO 0x15
-#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS 0x6E
-#define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS 0x0F
-#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS 0x80
-#define AU8522_REG071H_CVBS 0x18
-#define AU8522_REG072H_CVBS 0x30
-#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS 0xF0
-#define AU8522_REG074H_CVBS 0x80
-#define AU8522_REG075H_CVBS 0xF0
-#define AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS 0xFB
-#define AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS 0x04
-#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS 0x00
-#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS 0x00
-#define AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS 0xEE
-#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS 0xFE
-#define AU8522_TOREGAAGC_REG0E5H_CVBS 0x00
-#define AU8522_TVDEC_VBI6A_REG035H_CVBS 0x40
-
-/* Enables Closed captioning */
-#define AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON 0x21
diff --git a/drivers/media/dvb/frontends/bcm3510.c b/drivers/media/dvb/frontends/bcm3510.c
deleted file mode 100644
index 033cd7ad3ca..00000000000
--- a/drivers/media/dvb/frontends/bcm3510.c
+++ /dev/null
@@ -1,856 +0,0 @@
-/*
- * Support for the Broadcom BCM3510 ATSC demodulator (1st generation Air2PC)
- *
- * Copyright (C) 2001-5, B2C2 inc.
- *
- * GPL/Linux driver written by Patrick Boettcher <patrick.boettcher@desy.de>
- *
- * This driver is "hard-coded" to be used with the 1st generation of
- * Technisat/B2C2's Air2PC ATSC PCI/USB cards/boxes. The pll-programming
- * (Panasonic CT10S) is located here, which is actually wrong. Unless there is
- * another device with a BCM3510, this is no problem.
- *
- * The driver works also with QAM64 DVB-C, but had an unreasonable high
- * UNC. (Tested with the Air2PC ATSC 1st generation)
- *
- * You'll need a firmware for this driver in order to get it running. It is
- * called "dvb-fe-bcm3510-01.fw".
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 675 Mass
- * Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/firmware.h>
-#include <linux/jiffies.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/mutex.h>
-
-#include "dvb_frontend.h"
-#include "bcm3510.h"
-#include "bcm3510_priv.h"
-
-struct bcm3510_state {
-
- struct i2c_adapter* i2c;
- const struct bcm3510_config* config;
- struct dvb_frontend frontend;
-
- /* demodulator private data */
- struct mutex hab_mutex;
- u8 firmware_loaded:1;
-
- unsigned long next_status_check;
- unsigned long status_check_interval;
- struct bcm3510_hab_cmd_status1 status1;
- struct bcm3510_hab_cmd_status2 status2;
-};
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "set debugging level (1=info,2=i2c (|-able)).");
-
-#define dprintk(level,x...) if (level & debug) printk(x)
-#define dbufout(b,l,m) {\
- int i; \
- for (i = 0; i < l; i++) \
- m("%02x ",b[i]); \
-}
-#define deb_info(args...) dprintk(0x01,args)
-#define deb_i2c(args...) dprintk(0x02,args)
-#define deb_hab(args...) dprintk(0x04,args)
-
-/* transfer functions */
-static int bcm3510_writebytes (struct bcm3510_state *state, u8 reg, u8 *buf, u8 len)
-{
- u8 b[256];
- int err;
- struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = len + 1 };
-
- b[0] = reg;
- memcpy(&b[1],buf,len);
-
- deb_i2c("i2c wr %02x: ",reg);
- dbufout(buf,len,deb_i2c);
- deb_i2c("\n");
-
- if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
-
- deb_info("%s: i2c write error (addr %02x, reg %02x, err == %i)\n",
- __func__, state->config->demod_address, reg, err);
- return -EREMOTEIO;
- }
-
- return 0;
-}
-
-static int bcm3510_readbytes (struct bcm3510_state *state, u8 reg, u8 *buf, u8 len)
-{
- struct i2c_msg msg[] = {
- { .addr = state->config->demod_address, .flags = 0, .buf = &reg, .len = 1 },
- { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len }
- };
- int err;
-
- memset(buf,0,len);
-
- if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) {
- deb_info("%s: i2c read error (addr %02x, reg %02x, err == %i)\n",
- __func__, state->config->demod_address, reg, err);
- return -EREMOTEIO;
- }
- deb_i2c("i2c rd %02x: ",reg);
- dbufout(buf,len,deb_i2c);
- deb_i2c("\n");
-
- return 0;
-}
-
-static int bcm3510_writeB(struct bcm3510_state *state, u8 reg, bcm3510_register_value v)
-{
- return bcm3510_writebytes(state,reg,&v.raw,1);
-}
-
-static int bcm3510_readB(struct bcm3510_state *state, u8 reg, bcm3510_register_value *v)
-{
- return bcm3510_readbytes(state,reg,&v->raw,1);
-}
-
-/* Host Access Buffer transfers */
-static int bcm3510_hab_get_response(struct bcm3510_state *st, u8 *buf, int len)
-{
- bcm3510_register_value v;
- int ret,i;
-
- v.HABADR_a6.HABADR = 0;
- if ((ret = bcm3510_writeB(st,0xa6,v)) < 0)
- return ret;
-
- for (i = 0; i < len; i++) {
- if ((ret = bcm3510_readB(st,0xa7,&v)) < 0)
- return ret;
- buf[i] = v.HABDATA_a7;
- }
- return 0;
-}
-
-static int bcm3510_hab_send_request(struct bcm3510_state *st, u8 *buf, int len)
-{
- bcm3510_register_value v,hab;
- int ret,i;
- unsigned long t;
-
-/* Check if any previous HAB request still needs to be serviced by the
- * Acquisition Processor before sending new request */
- if ((ret = bcm3510_readB(st,0xa8,&v)) < 0)
- return ret;
- if (v.HABSTAT_a8.HABR) {
- deb_info("HAB is running already - clearing it.\n");
- v.HABSTAT_a8.HABR = 0;
- bcm3510_writeB(st,0xa8,v);
-// return -EBUSY;
- }
-
-/* Send the start HAB Address (automatically incremented after write of
- * HABDATA) and write the HAB Data */
- hab.HABADR_a6.HABADR = 0;
- if ((ret = bcm3510_writeB(st,0xa6,hab)) < 0)
- return ret;
-
- for (i = 0; i < len; i++) {
- hab.HABDATA_a7 = buf[i];
- if ((ret = bcm3510_writeB(st,0xa7,hab)) < 0)
- return ret;
- }
-
-/* Set the HABR bit to indicate AP request in progress (LBHABR allows HABR to
- * be written) */
- v.raw = 0; v.HABSTAT_a8.HABR = 1; v.HABSTAT_a8.LDHABR = 1;
- if ((ret = bcm3510_writeB(st,0xa8,v)) < 0)
- return ret;
-
-/* Polling method: Wait until the AP finishes processing the HAB request */
- t = jiffies + 1*HZ;
- while (time_before(jiffies, t)) {
- deb_info("waiting for HAB to complete\n");
- msleep(10);
- if ((ret = bcm3510_readB(st,0xa8,&v)) < 0)
- return ret;
-
- if (!v.HABSTAT_a8.HABR)
- return 0;
- }
-
- deb_info("send_request execution timed out.\n");
- return -ETIMEDOUT;
-}
-
-static int bcm3510_do_hab_cmd(struct bcm3510_state *st, u8 cmd, u8 msgid, u8 *obuf, u8 olen, u8 *ibuf, u8 ilen)
-{
- u8 ob[olen+2],ib[ilen+2];
- int ret = 0;
-
- ob[0] = cmd;
- ob[1] = msgid;
- memcpy(&ob[2],obuf,olen);
-
- deb_hab("hab snd: ");
- dbufout(ob,olen+2,deb_hab);
- deb_hab("\n");
-
- if (mutex_lock_interruptible(&st->hab_mutex) < 0)
- return -EAGAIN;
-
- if ((ret = bcm3510_hab_send_request(st, ob, olen+2)) < 0 ||
- (ret = bcm3510_hab_get_response(st, ib, ilen+2)) < 0)
- goto error;
-
- deb_hab("hab get: ");
- dbufout(ib,ilen+2,deb_hab);
- deb_hab("\n");
-
- memcpy(ibuf,&ib[2],ilen);
-error:
- mutex_unlock(&st->hab_mutex);
- return ret;
-}
-
-#if 0
-/* not needed, we use a semaphore to prevent HAB races */
-static int bcm3510_is_ap_ready(struct bcm3510_state *st)
-{
- bcm3510_register_value ap,hab;
- int ret;
-
- if ((ret = bcm3510_readB(st,0xa8,&hab)) < 0 ||
- (ret = bcm3510_readB(st,0xa2,&ap) < 0))
- return ret;
-
- if (ap.APSTAT1_a2.RESET || ap.APSTAT1_a2.IDLE || ap.APSTAT1_a2.STOP || hab.HABSTAT_a8.HABR) {
- deb_info("AP is busy\n");
- return -EBUSY;
- }
-
- return 0;
-}
-#endif
-
-static int bcm3510_bert_reset(struct bcm3510_state *st)
-{
- bcm3510_register_value b;
- int ret;
-
- if ((ret = bcm3510_readB(st,0xfa,&b)) < 0)
- return ret;
-
- b.BERCTL_fa.RESYNC = 0; bcm3510_writeB(st,0xfa,b);
- b.BERCTL_fa.RESYNC = 1; bcm3510_writeB(st,0xfa,b);
- b.BERCTL_fa.RESYNC = 0; bcm3510_writeB(st,0xfa,b);
- b.BERCTL_fa.CNTCTL = 1; b.BERCTL_fa.BITCNT = 1; bcm3510_writeB(st,0xfa,b);
-
- /* clear residual bit counter TODO */
- return 0;
-}
-
-static int bcm3510_refresh_state(struct bcm3510_state *st)
-{
- if (time_after(jiffies,st->next_status_check)) {
- bcm3510_do_hab_cmd(st, CMD_STATUS, MSGID_STATUS1, NULL,0, (u8 *)&st->status1, sizeof(st->status1));
- bcm3510_do_hab_cmd(st, CMD_STATUS, MSGID_STATUS2, NULL,0, (u8 *)&st->status2, sizeof(st->status2));
- st->next_status_check = jiffies + (st->status_check_interval*HZ)/1000;
- }
- return 0;
-}
-
-static int bcm3510_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct bcm3510_state* st = fe->demodulator_priv;
- bcm3510_refresh_state(st);
-
- *status = 0;
- if (st->status1.STATUS1.RECEIVER_LOCK)
- *status |= FE_HAS_LOCK | FE_HAS_SYNC;
-
- if (st->status1.STATUS1.FEC_LOCK)
- *status |= FE_HAS_VITERBI;
-
- if (st->status1.STATUS1.OUT_PLL_LOCK)
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
-
- if (*status & FE_HAS_LOCK)
- st->status_check_interval = 1500;
- else /* more frequently checks if no lock has been achieved yet */
- st->status_check_interval = 500;
-
- deb_info("real_status: %02x\n",*status);
- return 0;
-}
-
-static int bcm3510_read_ber(struct dvb_frontend* fe, u32* ber)
-{
- struct bcm3510_state* st = fe->demodulator_priv;
- bcm3510_refresh_state(st);
-
- *ber = (st->status2.LDBER0 << 16) | (st->status2.LDBER1 << 8) | st->status2.LDBER2;
- return 0;
-}
-
-static int bcm3510_read_unc(struct dvb_frontend* fe, u32* unc)
-{
- struct bcm3510_state* st = fe->demodulator_priv;
- bcm3510_refresh_state(st);
- *unc = (st->status2.LDUERC0 << 8) | st->status2.LDUERC1;
- return 0;
-}
-
-static int bcm3510_read_signal_strength(struct dvb_frontend* fe, u16* strength)
-{
- struct bcm3510_state* st = fe->demodulator_priv;
- s32 t;
-
- bcm3510_refresh_state(st);
- t = st->status2.SIGNAL;
-
- if (t > 190)
- t = 190;
- if (t < 90)
- t = 90;
-
- t -= 90;
- t = t * 0xff / 100;
- /* normalize if necessary */
- *strength = (t << 8) | t;
- return 0;
-}
-
-static int bcm3510_read_snr(struct dvb_frontend* fe, u16* snr)
-{
- struct bcm3510_state* st = fe->demodulator_priv;
- bcm3510_refresh_state(st);
-
- *snr = st->status1.SNR_EST0*1000 + ((st->status1.SNR_EST1*1000) >> 8);
- return 0;
-}
-
-/* tuner frontend programming */
-static int bcm3510_tuner_cmd(struct bcm3510_state* st,u8 bc, u16 n, u8 a)
-{
- struct bcm3510_hab_cmd_tune c;
- memset(&c,0,sizeof(struct bcm3510_hab_cmd_tune));
-
-/* I2C Mode disabled, set 16 control / Data pairs */
- c.length = 0x10;
- c.clock_width = 0;
-/* CS1, CS0, DATA, CLK bits control the tuner RF_AGC_SEL pin is set to
- * logic high (as Configuration) */
- c.misc = 0x10;
-/* Set duration of the initial state of TUNCTL = 3.34 micro Sec */
- c.TUNCTL_state = 0x40;
-
-/* PRESCALER DIVIDE RATIO | BC1_2_3_4; (band switch), 1stosc REFERENCE COUNTER REF_S12 and REF_S11 */
- c.ctl_dat[0].ctrl.size = BITS_8;
- c.ctl_dat[0].data = 0x80 | bc;
-
-/* Control DATA pin, 1stosc REFERENCE COUNTER REF_S10 to REF_S3 */
- c.ctl_dat[1].ctrl.size = BITS_8;
- c.ctl_dat[1].data = 4;
-
-/* set CONTROL BIT 1 to 1, 1stosc REFERENCE COUNTER REF_S2 to REF_S1 */
- c.ctl_dat[2].ctrl.size = BITS_3;
- c.ctl_dat[2].data = 0x20;
-
-/* control CS0 pin, pulse byte ? */
- c.ctl_dat[3].ctrl.size = BITS_3;
- c.ctl_dat[3].ctrl.clk_off = 1;
- c.ctl_dat[3].ctrl.cs0 = 1;
- c.ctl_dat[3].data = 0x40;
-
-/* PGM_S18 to PGM_S11 */
- c.ctl_dat[4].ctrl.size = BITS_8;
- c.ctl_dat[4].data = n >> 3;
-
-/* PGM_S10 to PGM_S8, SWL_S7 to SWL_S3 */
- c.ctl_dat[5].ctrl.size = BITS_8;
- c.ctl_dat[5].data = ((n & 0x7) << 5) | (a >> 2);
-
-/* SWL_S2 and SWL_S1, set CONTROL BIT 2 to 0 */
- c.ctl_dat[6].ctrl.size = BITS_3;
- c.ctl_dat[6].data = (a << 6) & 0xdf;
-
-/* control CS0 pin, pulse byte ? */
- c.ctl_dat[7].ctrl.size = BITS_3;
- c.ctl_dat[7].ctrl.clk_off = 1;
- c.ctl_dat[7].ctrl.cs0 = 1;
- c.ctl_dat[7].data = 0x40;
-
-/* PRESCALER DIVIDE RATIO, 2ndosc REFERENCE COUNTER REF_S12 and REF_S11 */
- c.ctl_dat[8].ctrl.size = BITS_8;
- c.ctl_dat[8].data = 0x80;
-
-/* 2ndosc REFERENCE COUNTER REF_S10 to REF_S3 */
- c.ctl_dat[9].ctrl.size = BITS_8;
- c.ctl_dat[9].data = 0x10;
-
-/* set CONTROL BIT 1 to 1, 2ndosc REFERENCE COUNTER REF_S2 to REF_S1 */
- c.ctl_dat[10].ctrl.size = BITS_3;
- c.ctl_dat[10].data = 0x20;
-
-/* pulse byte */
- c.ctl_dat[11].ctrl.size = BITS_3;
- c.ctl_dat[11].ctrl.clk_off = 1;
- c.ctl_dat[11].ctrl.cs1 = 1;
- c.ctl_dat[11].data = 0x40;
-
-/* PGM_S18 to PGM_S11 */
- c.ctl_dat[12].ctrl.size = BITS_8;
- c.ctl_dat[12].data = 0x2a;
-
-/* PGM_S10 to PGM_S8 and SWL_S7 to SWL_S3 */
- c.ctl_dat[13].ctrl.size = BITS_8;
- c.ctl_dat[13].data = 0x8e;
-
-/* SWL_S2 and SWL_S1 and set CONTROL BIT 2 to 0 */
- c.ctl_dat[14].ctrl.size = BITS_3;
- c.ctl_dat[14].data = 0;
-
-/* Pulse Byte */
- c.ctl_dat[15].ctrl.size = BITS_3;
- c.ctl_dat[15].ctrl.clk_off = 1;
- c.ctl_dat[15].ctrl.cs1 = 1;
- c.ctl_dat[15].data = 0x40;
-
- return bcm3510_do_hab_cmd(st,CMD_TUNE, MSGID_TUNE,(u8 *) &c,sizeof(c), NULL, 0);
-}
-
-static int bcm3510_set_freq(struct bcm3510_state* st,u32 freq)
-{
- u8 bc,a;
- u16 n;
- s32 YIntercept,Tfvco1;
-
- freq /= 1000;
-
- deb_info("%dkHz:",freq);
- /* set Band Switch */
- if (freq <= 168000)
- bc = 0x1c;
- else if (freq <= 378000)
- bc = 0x2c;
- else
- bc = 0x30;
-
- if (freq >= 470000) {
- freq -= 470001;
- YIntercept = 18805;
- } else if (freq >= 90000) {
- freq -= 90001;
- YIntercept = 15005;
- } else if (freq >= 76000){
- freq -= 76001;
- YIntercept = 14865;
- } else {
- freq -= 54001;
- YIntercept = 14645;
- }
-
- Tfvco1 = (((freq/6000)*60 + YIntercept)*4)/10;
-
- n = Tfvco1 >> 6;
- a = Tfvco1 & 0x3f;
-
- deb_info(" BC1_2_3_4: %x, N: %x A: %x\n", bc, n, a);
- if (n >= 16 && n <= 2047)
- return bcm3510_tuner_cmd(st,bc,n,a);
-
- return -EINVAL;
-}
-
-static int bcm3510_set_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct bcm3510_state* st = fe->demodulator_priv;
- struct bcm3510_hab_cmd_ext_acquire cmd;
- struct bcm3510_hab_cmd_bert_control bert;
- int ret;
-
- memset(&cmd,0,sizeof(cmd));
- switch (c->modulation) {
- case QAM_256:
- cmd.ACQUIRE0.MODE = 0x1;
- cmd.ACQUIRE1.SYM_RATE = 0x1;
- cmd.ACQUIRE1.IF_FREQ = 0x1;
- break;
- case QAM_64:
- cmd.ACQUIRE0.MODE = 0x2;
- cmd.ACQUIRE1.SYM_RATE = 0x2;
- cmd.ACQUIRE1.IF_FREQ = 0x1;
- break;
-#if 0
- case QAM_256:
- cmd.ACQUIRE0.MODE = 0x3;
- break;
- case QAM_128:
- cmd.ACQUIRE0.MODE = 0x4;
- break;
- case QAM_64:
- cmd.ACQUIRE0.MODE = 0x5;
- break;
- case QAM_32:
- cmd.ACQUIRE0.MODE = 0x6;
- break;
- case QAM_16:
- cmd.ACQUIRE0.MODE = 0x7;
- break;
-#endif
- case VSB_8:
- cmd.ACQUIRE0.MODE = 0x8;
- cmd.ACQUIRE1.SYM_RATE = 0x0;
- cmd.ACQUIRE1.IF_FREQ = 0x0;
- break;
- case VSB_16:
- cmd.ACQUIRE0.MODE = 0x9;
- cmd.ACQUIRE1.SYM_RATE = 0x0;
- cmd.ACQUIRE1.IF_FREQ = 0x0;
- default:
- return -EINVAL;
- };
- cmd.ACQUIRE0.OFFSET = 0;
- cmd.ACQUIRE0.NTSCSWEEP = 1;
- cmd.ACQUIRE0.FA = 1;
- cmd.ACQUIRE0.BW = 0;
-
-/* if (enableOffset) {
- cmd.IF_OFFSET0 = xx;
- cmd.IF_OFFSET1 = xx;
-
- cmd.SYM_OFFSET0 = xx;
- cmd.SYM_OFFSET1 = xx;
- if (enableNtscSweep) {
- cmd.NTSC_OFFSET0;
- cmd.NTSC_OFFSET1;
- }
- } */
- bcm3510_do_hab_cmd(st, CMD_ACQUIRE, MSGID_EXT_TUNER_ACQUIRE, (u8 *) &cmd, sizeof(cmd), NULL, 0);
-
-/* doing it with different MSGIDs, data book and source differs */
- bert.BE = 0;
- bert.unused = 0;
- bcm3510_do_hab_cmd(st, CMD_STATE_CONTROL, MSGID_BERT_CONTROL, (u8 *) &bert, sizeof(bert), NULL, 0);
- bcm3510_do_hab_cmd(st, CMD_STATE_CONTROL, MSGID_BERT_SET, (u8 *) &bert, sizeof(bert), NULL, 0);
-
- bcm3510_bert_reset(st);
-
- ret = bcm3510_set_freq(st, c->frequency);
- if (ret < 0)
- return ret;
-
- memset(&st->status1,0,sizeof(st->status1));
- memset(&st->status2,0,sizeof(st->status2));
- st->status_check_interval = 500;
-
-/* Give the AP some time */
- msleep(200);
-
- return 0;
-}
-
-static int bcm3510_sleep(struct dvb_frontend* fe)
-{
- return 0;
-}
-
-static int bcm3510_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *s)
-{
- s->min_delay_ms = 1000;
- s->step_size = 0;
- s->max_drift = 0;
- return 0;
-}
-
-static void bcm3510_release(struct dvb_frontend* fe)
-{
- struct bcm3510_state* state = fe->demodulator_priv;
- kfree(state);
-}
-
-/* firmware download:
- * firmware file is build up like this:
- * 16bit addr, 16bit length, 8byte of length
- */
-#define BCM3510_DEFAULT_FIRMWARE "dvb-fe-bcm3510-01.fw"
-
-static int bcm3510_write_ram(struct bcm3510_state *st, u16 addr, const u8 *b,
- u16 len)
-{
- int ret = 0,i;
- bcm3510_register_value vH, vL,vD;
-
- vH.MADRH_a9 = addr >> 8;
- vL.MADRL_aa = addr;
- if ((ret = bcm3510_writeB(st,0xa9,vH)) < 0) return ret;
- if ((ret = bcm3510_writeB(st,0xaa,vL)) < 0) return ret;
-
- for (i = 0; i < len; i++) {
- vD.MDATA_ab = b[i];
- if ((ret = bcm3510_writeB(st,0xab,vD)) < 0)
- return ret;
- }
-
- return 0;
-}
-
-static int bcm3510_download_firmware(struct dvb_frontend* fe)
-{
- struct bcm3510_state* st = fe->demodulator_priv;
- const struct firmware *fw;
- u16 addr,len;
- const u8 *b;
- int ret,i;
-
- deb_info("requesting firmware\n");
- if ((ret = st->config->request_firmware(fe, &fw, BCM3510_DEFAULT_FIRMWARE)) < 0) {
- err("could not load firmware (%s): %d",BCM3510_DEFAULT_FIRMWARE,ret);
- return ret;
- }
- deb_info("got firmware: %zd\n",fw->size);
-
- b = fw->data;
- for (i = 0; i < fw->size;) {
- addr = le16_to_cpu( *( (u16 *)&b[i] ) );
- len = le16_to_cpu( *( (u16 *)&b[i+2] ) );
- deb_info("firmware chunk, addr: 0x%04x, len: 0x%04x, total length: 0x%04zx\n",addr,len,fw->size);
- if ((ret = bcm3510_write_ram(st,addr,&b[i+4],len)) < 0) {
- err("firmware download failed: %d\n",ret);
- return ret;
- }
- i += 4 + len;
- }
- release_firmware(fw);
- deb_info("firmware download successfully completed\n");
- return 0;
-}
-
-static int bcm3510_check_firmware_version(struct bcm3510_state *st)
-{
- struct bcm3510_hab_cmd_get_version_info ver;
- bcm3510_do_hab_cmd(st,CMD_GET_VERSION_INFO,MSGID_GET_VERSION_INFO,NULL,0,(u8*)&ver,sizeof(ver));
-
- deb_info("Version information: 0x%02x 0x%02x 0x%02x 0x%02x\n",
- ver.microcode_version, ver.script_version, ver.config_version, ver.demod_version);
-
- if (ver.script_version == BCM3510_DEF_SCRIPT_VERSION &&
- ver.config_version == BCM3510_DEF_CONFIG_VERSION &&
- ver.demod_version == BCM3510_DEF_DEMOD_VERSION)
- return 0;
-
- deb_info("version check failed\n");
- return -ENODEV;
-}
-
-/* (un)resetting the AP */
-static int bcm3510_reset(struct bcm3510_state *st)
-{
- int ret;
- unsigned long t;
- bcm3510_register_value v;
-
- bcm3510_readB(st,0xa0,&v); v.HCTL1_a0.RESET = 1;
- if ((ret = bcm3510_writeB(st,0xa0,v)) < 0)
- return ret;
-
- t = jiffies + 3*HZ;
- while (time_before(jiffies, t)) {
- msleep(10);
- if ((ret = bcm3510_readB(st,0xa2,&v)) < 0)
- return ret;
-
- if (v.APSTAT1_a2.RESET)
- return 0;
- }
- deb_info("reset timed out\n");
- return -ETIMEDOUT;
-}
-
-static int bcm3510_clear_reset(struct bcm3510_state *st)
-{
- bcm3510_register_value v;
- int ret;
- unsigned long t;
-
- v.raw = 0;
- if ((ret = bcm3510_writeB(st,0xa0,v)) < 0)
- return ret;
-
- t = jiffies + 3*HZ;
- while (time_before(jiffies, t)) {
- msleep(10);
- if ((ret = bcm3510_readB(st,0xa2,&v)) < 0)
- return ret;
-
- /* verify that reset is cleared */
- if (!v.APSTAT1_a2.RESET)
- return 0;
- }
- deb_info("reset clear timed out\n");
- return -ETIMEDOUT;
-}
-
-static int bcm3510_init_cold(struct bcm3510_state *st)
-{
- int ret;
- bcm3510_register_value v;
-
- /* read Acquisation Processor status register and check it is not in RUN mode */
- if ((ret = bcm3510_readB(st,0xa2,&v)) < 0)
- return ret;
- if (v.APSTAT1_a2.RUN) {
- deb_info("AP is already running - firmware already loaded.\n");
- return 0;
- }
-
- deb_info("reset?\n");
- if ((ret = bcm3510_reset(st)) < 0)
- return ret;
-
- deb_info("tristate?\n");
- /* tri-state */
- v.TSTCTL_2e.CTL = 0;
- if ((ret = bcm3510_writeB(st,0x2e,v)) < 0)
- return ret;
-
- deb_info("firmware?\n");
- if ((ret = bcm3510_download_firmware(&st->frontend)) < 0 ||
- (ret = bcm3510_clear_reset(st)) < 0)
- return ret;
-
- /* anything left here to Let the acquisition processor begin execution at program counter 0000 ??? */
-
- return 0;
-}
-
-static int bcm3510_init(struct dvb_frontend* fe)
-{
- struct bcm3510_state* st = fe->demodulator_priv;
- bcm3510_register_value j;
- struct bcm3510_hab_cmd_set_agc c;
- int ret;
-
- if ((ret = bcm3510_readB(st,0xca,&j)) < 0)
- return ret;
-
- deb_info("JDEC: %02x\n",j.raw);
-
- switch (j.JDEC_ca.JDEC) {
- case JDEC_WAIT_AT_RAM:
- deb_info("attempting to download firmware\n");
- if ((ret = bcm3510_init_cold(st)) < 0)
- return ret;
- case JDEC_EEPROM_LOAD_WAIT: /* fall-through is wanted */
- deb_info("firmware is loaded\n");
- bcm3510_check_firmware_version(st);
- break;
- default:
- return -ENODEV;
- }
-
- memset(&c,0,1);
- c.SEL = 1;
- bcm3510_do_hab_cmd(st,CMD_AUTO_PARAM,MSGID_SET_RF_AGC_SEL,(u8 *)&c,sizeof(c),NULL,0);
-
- return 0;
-}
-
-
-static struct dvb_frontend_ops bcm3510_ops;
-
-struct dvb_frontend* bcm3510_attach(const struct bcm3510_config *config,
- struct i2c_adapter *i2c)
-{
- struct bcm3510_state* state = NULL;
- int ret;
- bcm3510_register_value v;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct bcm3510_state), GFP_KERNEL);
- if (state == NULL)
- goto error;
-
- /* setup the state */
-
- state->config = config;
- state->i2c = i2c;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &bcm3510_ops, sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
-
- mutex_init(&state->hab_mutex);
-
- if ((ret = bcm3510_readB(state,0xe0,&v)) < 0)
- goto error;
-
- deb_info("Revision: 0x%1x, Layer: 0x%1x.\n",v.REVID_e0.REV,v.REVID_e0.LAYER);
-
- if ((v.REVID_e0.REV != 0x1 && v.REVID_e0.LAYER != 0xb) && /* cold */
- (v.REVID_e0.REV != 0x8 && v.REVID_e0.LAYER != 0x0)) /* warm */
- goto error;
-
- info("Revision: 0x%1x, Layer: 0x%1x.",v.REVID_e0.REV,v.REVID_e0.LAYER);
-
- bcm3510_reset(state);
-
- return &state->frontend;
-
-error:
- kfree(state);
- return NULL;
-}
-EXPORT_SYMBOL(bcm3510_attach);
-
-static struct dvb_frontend_ops bcm3510_ops = {
- .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
- .info = {
- .name = "Broadcom BCM3510 VSB/QAM frontend",
- .frequency_min = 54000000,
- .frequency_max = 803000000,
- /* stepsize is just a guess */
- .frequency_stepsize = 0,
- .caps =
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_8VSB | FE_CAN_16VSB |
- FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_128 | FE_CAN_QAM_256
- },
-
- .release = bcm3510_release,
-
- .init = bcm3510_init,
- .sleep = bcm3510_sleep,
-
- .set_frontend = bcm3510_set_frontend,
- .get_tune_settings = bcm3510_get_tune_settings,
-
- .read_status = bcm3510_read_status,
- .read_ber = bcm3510_read_ber,
- .read_signal_strength = bcm3510_read_signal_strength,
- .read_snr = bcm3510_read_snr,
- .read_ucblocks = bcm3510_read_unc,
-};
-
-MODULE_DESCRIPTION("Broadcom BCM3510 ATSC (8VSB/16VSB & ITU J83 AnnexB FEC QAM64/256) demodulator driver");
-MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@desy.de>");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/bcm3510.h b/drivers/media/dvb/frontends/bcm3510.h
deleted file mode 100644
index f4575c0cc44..00000000000
--- a/drivers/media/dvb/frontends/bcm3510.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Support for the Broadcom BCM3510 ATSC demodulator (1st generation Air2PC)
- *
- * Copyright (C) 2001-5, B2C2 inc.
- *
- * GPL/Linux driver written by Patrick Boettcher <patrick.boettcher@desy.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef BCM3510_H
-#define BCM3510_H
-
-#include <linux/dvb/frontend.h>
-#include <linux/firmware.h>
-
-struct bcm3510_config
-{
- /* the demodulator's i2c address */
- u8 demod_address;
-
- /* request firmware for device */
- int (*request_firmware)(struct dvb_frontend* fe, const struct firmware **fw, char* name);
-};
-
-#if defined(CONFIG_DVB_BCM3510) || (defined(CONFIG_DVB_BCM3510_MODULE) && defined(MODULE))
-extern struct dvb_frontend* bcm3510_attach(const struct bcm3510_config* config,
- struct i2c_adapter* i2c);
-#else
-static inline struct dvb_frontend* bcm3510_attach(const struct bcm3510_config* config,
- struct i2c_adapter* i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif // CONFIG_DVB_BCM3510
-
-#endif
diff --git a/drivers/media/dvb/frontends/bcm3510_priv.h b/drivers/media/dvb/frontends/bcm3510_priv.h
deleted file mode 100644
index 3bb1bc2a04f..00000000000
--- a/drivers/media/dvb/frontends/bcm3510_priv.h
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * Support for the Broadcom BCM3510 ATSC demodulator (1st generation Air2PC)
- *
- * Copyright (C) 2001-5, B2C2 inc.
- *
- * GPL/Linux driver written by Patrick Boettcher <patrick.boettcher@desy.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __BCM3510_PRIV_H__
-#define __BCM3510_PRIV_H__
-
-#define PACKED __attribute__((packed))
-
-#undef err
-#define err(format, arg...) printk(KERN_ERR "bcm3510: " format "\n" , ## arg)
-#undef info
-#define info(format, arg...) printk(KERN_INFO "bcm3510: " format "\n" , ## arg)
-#undef warn
-#define warn(format, arg...) printk(KERN_WARNING "bcm3510: " format "\n" , ## arg)
-
-
-#define PANASONIC_FIRST_IF_BASE_IN_KHz 1407500
-#define BCM3510_SYMBOL_RATE 5381000
-
-typedef union {
- u8 raw;
-
- struct {
- u8 CTL :8;
- } TSTCTL_2e;
-
- u8 LDCERC_4e;
- u8 LDUERC_4f;
- u8 LD_BER0_65;
- u8 LD_BER1_66;
- u8 LD_BER2_67;
- u8 LD_BER3_68;
-
- struct {
- u8 RESET :1;
- u8 IDLE :1;
- u8 STOP :1;
- u8 HIRQ0 :1;
- u8 HIRQ1 :1;
- u8 na0 :1;
- u8 HABAV :1;
- u8 na1 :1;
- } HCTL1_a0;
-
- struct {
- u8 na0 :1;
- u8 IDLMSK :1;
- u8 STMSK :1;
- u8 I0MSK :1;
- u8 I1MSK :1;
- u8 na1 :1;
- u8 HABMSK :1;
- u8 na2 :1;
- } HCTLMSK_a1;
-
- struct {
- u8 RESET :1;
- u8 IDLE :1;
- u8 STOP :1;
- u8 RUN :1;
- u8 HABAV :1;
- u8 MEMAV :1;
- u8 ALDONE :1;
- u8 REIRQ :1;
- } APSTAT1_a2;
-
- struct {
- u8 RSTMSK :1;
- u8 IMSK :1;
- u8 SMSK :1;
- u8 RMSK :1;
- u8 HABMSK :1;
- u8 MAVMSK :1;
- u8 ALDMSK :1;
- u8 REMSK :1;
- } APMSK1_a3;
-
- u8 APSTAT2_a4;
- u8 APMSK2_a5;
-
- struct {
- u8 HABADR :7;
- u8 na :1;
- } HABADR_a6;
-
- u8 HABDATA_a7;
-
- struct {
- u8 HABR :1;
- u8 LDHABR :1;
- u8 APMSK :1;
- u8 HMSK :1;
- u8 LDMSK :1;
- u8 na :3;
- } HABSTAT_a8;
-
- u8 MADRH_a9;
- u8 MADRL_aa;
- u8 MDATA_ab;
-
- struct {
-#define JDEC_WAIT_AT_RAM 0x7
-#define JDEC_EEPROM_LOAD_WAIT 0x4
- u8 JDEC :3;
- u8 na :5;
- } JDEC_ca;
-
- struct {
- u8 REV :4;
- u8 LAYER :4;
- } REVID_e0;
-
- struct {
- u8 unk0 :1;
- u8 CNTCTL :1;
- u8 BITCNT :1;
- u8 unk1 :1;
- u8 RESYNC :1;
- u8 unk2 :3;
- } BERCTL_fa;
-
- struct {
- u8 CSEL0 :1;
- u8 CLKED0 :1;
- u8 CSEL1 :1;
- u8 CLKED1 :1;
- u8 CLKLEV :1;
- u8 SPIVAR :1;
- u8 na :2;
- } TUNSET_fc;
-
- struct {
- u8 CLK :1;
- u8 DATA :1;
- u8 CS0 :1;
- u8 CS1 :1;
- u8 AGCSEL :1;
- u8 na0 :1;
- u8 TUNSEL :1;
- u8 na1 :1;
- } TUNCTL_fd;
-
- u8 TUNSEL0_fe;
- u8 TUNSEL1_ff;
-
-} bcm3510_register_value;
-
-/* HAB commands */
-
-/* version */
-#define CMD_GET_VERSION_INFO 0x3D
-#define MSGID_GET_VERSION_INFO 0x15
-struct bcm3510_hab_cmd_get_version_info {
- u8 microcode_version;
- u8 script_version;
- u8 config_version;
- u8 demod_version;
-} PACKED;
-
-#define BCM3510_DEF_MICROCODE_VERSION 0x0E
-#define BCM3510_DEF_SCRIPT_VERSION 0x06
-#define BCM3510_DEF_CONFIG_VERSION 0x01
-#define BCM3510_DEF_DEMOD_VERSION 0xB1
-
-/* acquire */
-#define CMD_ACQUIRE 0x38
-
-#define MSGID_EXT_TUNER_ACQUIRE 0x0A
-struct bcm3510_hab_cmd_ext_acquire {
- struct {
- u8 MODE :4;
- u8 BW :1;
- u8 FA :1;
- u8 NTSCSWEEP :1;
- u8 OFFSET :1;
- } PACKED ACQUIRE0; /* control_byte */
-
- struct {
- u8 IF_FREQ :3;
- u8 zero0 :1;
- u8 SYM_RATE :3;
- u8 zero1 :1;
- } PACKED ACQUIRE1; /* sym_if */
-
- u8 IF_OFFSET0; /* IF_Offset_10hz */
- u8 IF_OFFSET1;
- u8 SYM_OFFSET0; /* SymbolRateOffset */
- u8 SYM_OFFSET1;
- u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */
- u8 NTSC_OFFSET1;
-} PACKED;
-
-#define MSGID_INT_TUNER_ACQUIRE 0x0B
-struct bcm3510_hab_cmd_int_acquire {
- struct {
- u8 MODE :4;
- u8 BW :1;
- u8 FA :1;
- u8 NTSCSWEEP :1;
- u8 OFFSET :1;
- } PACKED ACQUIRE0; /* control_byte */
-
- struct {
- u8 IF_FREQ :3;
- u8 zero0 :1;
- u8 SYM_RATE :3;
- u8 zero1 :1;
- } PACKED ACQUIRE1; /* sym_if */
-
- u8 TUNER_FREQ0;
- u8 TUNER_FREQ1;
- u8 TUNER_FREQ2;
- u8 TUNER_FREQ3;
- u8 IF_OFFSET0; /* IF_Offset_10hz */
- u8 IF_OFFSET1;
- u8 SYM_OFFSET0; /* SymbolRateOffset */
- u8 SYM_OFFSET1;
- u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */
- u8 NTSC_OFFSET1;
-} PACKED;
-
-/* modes */
-#define BCM3510_QAM16 = 0x01
-#define BCM3510_QAM32 = 0x02
-#define BCM3510_QAM64 = 0x03
-#define BCM3510_QAM128 = 0x04
-#define BCM3510_QAM256 = 0x05
-#define BCM3510_8VSB = 0x0B
-#define BCM3510_16VSB = 0x0D
-
-/* IF_FREQS */
-#define BCM3510_IF_TERRESTRIAL 0x0
-#define BCM3510_IF_CABLE 0x1
-#define BCM3510_IF_USE_CMD 0x7
-
-/* SYM_RATE */
-#define BCM3510_SR_8VSB 0x0 /* 5381119 s/sec */
-#define BCM3510_SR_256QAM 0x1 /* 5360537 s/sec */
-#define BCM3510_SR_16QAM 0x2 /* 5056971 s/sec */
-#define BCM3510_SR_MISC 0x3 /* 5000000 s/sec */
-#define BCM3510_SR_USE_CMD 0x7
-
-/* special symbol rate */
-#define CMD_SET_VALUE_NOT_LISTED 0x2d
-#define MSGID_SET_SYMBOL_RATE_NOT_LISTED 0x0c
-struct bcm3510_hab_cmd_set_sr_not_listed {
- u8 HOST_SYM_RATE0;
- u8 HOST_SYM_RATE1;
- u8 HOST_SYM_RATE2;
- u8 HOST_SYM_RATE3;
-} PACKED;
-
-/* special IF */
-#define MSGID_SET_IF_FREQ_NOT_LISTED 0x0d
-struct bcm3510_hab_cmd_set_if_freq_not_listed {
- u8 HOST_IF_FREQ0;
- u8 HOST_IF_FREQ1;
- u8 HOST_IF_FREQ2;
- u8 HOST_IF_FREQ3;
-} PACKED;
-
-/* auto reacquire */
-#define CMD_AUTO_PARAM 0x2a
-#define MSGID_AUTO_REACQUIRE 0x0e
-struct bcm3510_hab_cmd_auto_reacquire {
- u8 ACQ :1; /* on/off*/
- u8 unused :7;
-} PACKED;
-
-#define MSGID_SET_RF_AGC_SEL 0x12
-struct bcm3510_hab_cmd_set_agc {
- u8 LVL :1;
- u8 unused :6;
- u8 SEL :1;
-} PACKED;
-
-#define MSGID_SET_AUTO_INVERSION 0x14
-struct bcm3510_hab_cmd_auto_inversion {
- u8 AI :1;
- u8 unused :7;
-} PACKED;
-
-
-/* bert control */
-#define CMD_STATE_CONTROL 0x12
-#define MSGID_BERT_CONTROL 0x0e
-#define MSGID_BERT_SET 0xfa
-struct bcm3510_hab_cmd_bert_control {
- u8 BE :1;
- u8 unused :7;
-} PACKED;
-
-#define MSGID_TRI_STATE 0x2e
-struct bcm3510_hab_cmd_tri_state {
- u8 RE :1; /* a/d ram port pins */
- u8 PE :1; /* baud clock pin */
- u8 AC :1; /* a/d clock pin */
- u8 BE :1; /* baud clock pin */
- u8 unused :4;
-} PACKED;
-
-
-/* tune */
-#define CMD_TUNE 0x38
-#define MSGID_TUNE 0x16
-struct bcm3510_hab_cmd_tune_ctrl_data_pair {
- struct {
-#define BITS_8 0x07
-#define BITS_7 0x06
-#define BITS_6 0x05
-#define BITS_5 0x04
-#define BITS_4 0x03
-#define BITS_3 0x02
-#define BITS_2 0x01
-#define BITS_1 0x00
- u8 size :3;
- u8 unk :2;
- u8 clk_off :1;
- u8 cs0 :1;
- u8 cs1 :1;
-
- } PACKED ctrl;
-
- u8 data;
-} PACKED;
-
-struct bcm3510_hab_cmd_tune {
- u8 length;
- u8 clock_width;
- u8 misc;
- u8 TUNCTL_state;
-
- struct bcm3510_hab_cmd_tune_ctrl_data_pair ctl_dat[16];
-} PACKED;
-
-#define CMD_STATUS 0x38
-#define MSGID_STATUS1 0x08
-struct bcm3510_hab_cmd_status1 {
- struct {
- u8 EQ_MODE :4;
- u8 reserved :2;
- u8 QRE :1; /* if QSE and the spectrum is inversed */
- u8 QSE :1; /* automatic spectral inversion */
- } PACKED STATUS0;
-
- struct {
- u8 RECEIVER_LOCK :1;
- u8 FEC_LOCK :1;
- u8 OUT_PLL_LOCK :1;
- u8 reserved :5;
- } PACKED STATUS1;
-
- struct {
- u8 reserved :2;
- u8 BW :1;
- u8 NTE :1; /* NTSC filter sweep enabled */
- u8 AQI :1; /* currently acquiring */
- u8 FA :1; /* fast acquisition */
- u8 ARI :1; /* auto reacquire */
- u8 TI :1; /* programming the tuner */
- } PACKED STATUS2;
- u8 STATUS3;
- u8 SNR_EST0;
- u8 SNR_EST1;
- u8 TUNER_FREQ0;
- u8 TUNER_FREQ1;
- u8 TUNER_FREQ2;
- u8 TUNER_FREQ3;
- u8 SYM_RATE0;
- u8 SYM_RATE1;
- u8 SYM_RATE2;
- u8 SYM_RATE3;
- u8 SYM_OFFSET0;
- u8 SYM_OFFSET1;
- u8 SYM_ERROR0;
- u8 SYM_ERROR1;
- u8 IF_FREQ0;
- u8 IF_FREQ1;
- u8 IF_FREQ2;
- u8 IF_FREQ3;
- u8 IF_OFFSET0;
- u8 IF_OFFSET1;
- u8 IF_ERROR0;
- u8 IF_ERROR1;
- u8 NTSC_FILTER0;
- u8 NTSC_FILTER1;
- u8 NTSC_FILTER2;
- u8 NTSC_FILTER3;
- u8 NTSC_OFFSET0;
- u8 NTSC_OFFSET1;
- u8 NTSC_ERROR0;
- u8 NTSC_ERROR1;
- u8 INT_AGC_LEVEL0;
- u8 INT_AGC_LEVEL1;
- u8 EXT_AGC_LEVEL0;
- u8 EXT_AGC_LEVEL1;
-} PACKED;
-
-#define MSGID_STATUS2 0x14
-struct bcm3510_hab_cmd_status2 {
- struct {
- u8 EQ_MODE :4;
- u8 reserved :2;
- u8 QRE :1;
- u8 QSR :1;
- } PACKED STATUS0;
- struct {
- u8 RL :1;
- u8 FL :1;
- u8 OL :1;
- u8 reserved :5;
- } PACKED STATUS1;
- u8 SYMBOL_RATE0;
- u8 SYMBOL_RATE1;
- u8 SYMBOL_RATE2;
- u8 SYMBOL_RATE3;
- u8 LDCERC0;
- u8 LDCERC1;
- u8 LDCERC2;
- u8 LDCERC3;
- u8 LDUERC0;
- u8 LDUERC1;
- u8 LDUERC2;
- u8 LDUERC3;
- u8 LDBER0;
- u8 LDBER1;
- u8 LDBER2;
- u8 LDBER3;
- struct {
- u8 MODE_TYPE :4; /* acquire mode 0 */
- u8 reservd :4;
- } MODE_TYPE;
- u8 SNR_EST0;
- u8 SNR_EST1;
- u8 SIGNAL;
-} PACKED;
-
-#define CMD_SET_RF_BW_NOT_LISTED 0x3f
-#define MSGID_SET_RF_BW_NOT_LISTED 0x11
-/* TODO */
-
-#endif
diff --git a/drivers/media/dvb/frontends/bsbe1-d01a.h b/drivers/media/dvb/frontends/bsbe1-d01a.h
deleted file mode 100644
index 7ed3c424178..00000000000
--- a/drivers/media/dvb/frontends/bsbe1-d01a.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * bsbe1-d01a.h - ALPS BSBE1-D01A tuner support
- *
- * Copyright (C) 2011 Oliver Endriss <o.endriss@gmx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- *
- *
- * the project's page is at http://www.linuxtv.org
- */
-
-#ifndef BSBE1_D01A_H
-#define BSBE1_D01A_H
-
-#include "stb6000.h"
-#include "stv0288.h"
-
-static u8 stv0288_bsbe1_d01a_inittab[] = {
- 0x01, 0x15,
- 0x02, 0x20,
- 0x09, 0x0,
- 0x0a, 0x4,
- 0x0b, 0x0,
- 0x0c, 0x0,
- 0x0d, 0x0,
- 0x0e, 0xd4,
- 0x0f, 0x30,
- 0x11, 0x80,
- 0x12, 0x03,
- 0x13, 0x48,
- 0x14, 0x84,
- 0x15, 0x45,
- 0x16, 0xb7,
- 0x17, 0x9c,
- 0x18, 0x0,
- 0x19, 0xa6,
- 0x1a, 0x88,
- 0x1b, 0x8f,
- 0x1c, 0xf0,
- 0x20, 0x0b,
- 0x21, 0x54,
- 0x22, 0x0,
- 0x23, 0x0,
- 0x2b, 0xff,
- 0x2c, 0xf7,
- 0x30, 0x0,
- 0x31, 0x1e,
- 0x32, 0x14,
- 0x33, 0x0f,
- 0x34, 0x09,
- 0x35, 0x0c,
- 0x36, 0x05,
- 0x37, 0x2f,
- 0x38, 0x16,
- 0x39, 0xbd,
- 0x3a, 0x03,
- 0x3b, 0x13,
- 0x3c, 0x11,
- 0x3d, 0x30,
- 0x40, 0x63,
- 0x41, 0x04,
- 0x42, 0x60,
- 0x43, 0x00,
- 0x44, 0x00,
- 0x45, 0x00,
- 0x46, 0x00,
- 0x47, 0x00,
- 0x4a, 0x00,
- 0x50, 0x10,
- 0x51, 0x36,
- 0x52, 0x09,
- 0x53, 0x94,
- 0x54, 0x62,
- 0x55, 0x29,
- 0x56, 0x64,
- 0x57, 0x2b,
- 0x58, 0x54,
- 0x59, 0x86,
- 0x5a, 0x0,
- 0x5b, 0x9b,
- 0x5c, 0x08,
- 0x5d, 0x7f,
- 0x5e, 0x0,
- 0x5f, 0xff,
- 0x70, 0x0,
- 0x71, 0x0,
- 0x72, 0x0,
- 0x74, 0x0,
- 0x75, 0x0,
- 0x76, 0x0,
- 0x81, 0x0,
- 0x82, 0x3f,
- 0x83, 0x3f,
- 0x84, 0x0,
- 0x85, 0x0,
- 0x88, 0x0,
- 0x89, 0x0,
- 0x8a, 0x0,
- 0x8b, 0x0,
- 0x8c, 0x0,
- 0x90, 0x0,
- 0x91, 0x0,
- 0x92, 0x0,
- 0x93, 0x0,
- 0x94, 0x1c,
- 0x97, 0x0,
- 0xa0, 0x48,
- 0xa1, 0x0,
- 0xb0, 0xb8,
- 0xb1, 0x3a,
- 0xb2, 0x10,
- 0xb3, 0x82,
- 0xb4, 0x80,
- 0xb5, 0x82,
- 0xb6, 0x82,
- 0xb7, 0x82,
- 0xb8, 0x20,
- 0xb9, 0x0,
- 0xf0, 0x0,
- 0xf1, 0x0,
- 0xf2, 0xc0,
- 0xff, 0xff,
-};
-
-static struct stv0288_config stv0288_bsbe1_d01a_config = {
- .demod_address = 0x68,
- .min_delay_ms = 100,
- .inittab = stv0288_bsbe1_d01a_inittab,
-};
-
-#endif
diff --git a/drivers/media/dvb/frontends/bsbe1.h b/drivers/media/dvb/frontends/bsbe1.h
deleted file mode 100644
index 53e4d0dbb74..00000000000
--- a/drivers/media/dvb/frontends/bsbe1.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * bsbe1.h - ALPS BSBE1 tuner support
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- *
- *
- * the project's page is at http://www.linuxtv.org
- */
-
-#ifndef BSBE1_H
-#define BSBE1_H
-
-static u8 alps_bsbe1_inittab[] = {
- 0x01, 0x15, /* XTAL = 4MHz, VCO = 352 MHz */
- 0x02, 0x30, /* MCLK = 88 MHz */
- 0x03, 0x00, /* ACR output 0 */
- 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
- 0x05, 0x05, /* I2CT = 0, SCLT = 1, SDAT = 1 */
- 0x06, 0x00, /* DAC output 0 */
- 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
- 0x09, 0x00, /* FIFO */
- 0x0c, 0x51, /* OP1/OP0 normal, val = 1 (LNB power on) */
- 0x0d, 0x82, /* DC offset compensation = on, beta_agc1 = 2 */
- 0x0f, 0x92, /* AGC1R */
- 0x10, 0x34, /* AGC2O */
- 0x11, 0x84, /* TLSR */
- 0x12, 0xb9, /* CFD */
- 0x15, 0xc9, /* lock detector threshold */
- 0x28, 0x00, /* out imp: normal, type: parallel, FEC mode: QPSK */
- 0x33, 0xfc, /* RS control */
- 0x34, 0x93, /* count viterbi bit errors per 2E18 bytes */
- 0xff, 0xff
-};
-
-
-static int alps_bsbe1_set_symbol_rate(struct dvb_frontend* fe, u32 srate, u32 ratio)
-{
- u8 aclk = 0;
- u8 bclk = 0;
-
- if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; }
- else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; }
- else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; }
- else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; }
- else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; }
- else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; }
-
- stv0299_writereg(fe, 0x13, aclk);
- stv0299_writereg(fe, 0x14, bclk);
- stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
- stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
- stv0299_writereg(fe, 0x21, (ratio ) & 0xf0);
-
- return 0;
-}
-
-static int alps_bsbe1_tuner_set_params(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- int ret;
- u8 data[4];
- u32 div;
- struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };
- struct i2c_adapter *i2c = fe->tuner_priv;
-
- if ((p->frequency < 950000) || (p->frequency > 2150000))
- return -EINVAL;
-
- div = p->frequency / 1000;
- data[0] = (div >> 8) & 0x7f;
- data[1] = div & 0xff;
- data[2] = 0x80 | ((div & 0x18000) >> 10) | 0x1;
- data[3] = 0xe0;
-
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
- ret = i2c_transfer(i2c, &msg, 1);
- return (ret != 1) ? -EIO : 0;
-}
-
-static struct stv0299_config alps_bsbe1_config = {
- .demod_address = 0x68,
- .inittab = alps_bsbe1_inittab,
- .mclk = 88000000UL,
- .invert = 1,
- .skip_reinit = 0,
- .min_delay_ms = 100,
- .set_symbol_rate = alps_bsbe1_set_symbol_rate,
-};
-
-#endif
diff --git a/drivers/media/dvb/frontends/bsru6.h b/drivers/media/dvb/frontends/bsru6.h
deleted file mode 100644
index c2a578e1314..00000000000
--- a/drivers/media/dvb/frontends/bsru6.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * bsru6.h - ALPS BSRU6 tuner support (moved from budget-ci.c)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- *
- *
- * the project's page is at http://www.linuxtv.org
- */
-
-#ifndef BSRU6_H
-#define BSRU6_H
-
-static u8 alps_bsru6_inittab[] = {
- 0x01, 0x15,
- 0x02, 0x30,
- 0x03, 0x00,
- 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
- 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
- 0x06, 0x40, /* DAC not used, set to high impendance mode */
- 0x07, 0x00, /* DAC LSB */
- 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
- 0x09, 0x00, /* FIFO */
- 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
- 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
- 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
- 0x10, 0x3f, // AGC2 0x3d
- 0x11, 0x84,
- 0x12, 0xb9,
- 0x15, 0xc9, // lock detector threshold
- 0x16, 0x00,
- 0x17, 0x00,
- 0x18, 0x00,
- 0x19, 0x00,
- 0x1a, 0x00,
- 0x1f, 0x50,
- 0x20, 0x00,
- 0x21, 0x00,
- 0x22, 0x00,
- 0x23, 0x00,
- 0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
- 0x29, 0x1e, // 1/2 threshold
- 0x2a, 0x14, // 2/3 threshold
- 0x2b, 0x0f, // 3/4 threshold
- 0x2c, 0x09, // 5/6 threshold
- 0x2d, 0x05, // 7/8 threshold
- 0x2e, 0x01,
- 0x31, 0x1f, // test all FECs
- 0x32, 0x19, // viterbi and synchro search
- 0x33, 0xfc, // rs control
- 0x34, 0x93, // error control
- 0x0f, 0x52,
- 0xff, 0xff
-};
-
-static int alps_bsru6_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio)
-{
- u8 aclk = 0;
- u8 bclk = 0;
-
- if (srate < 1500000) {
- aclk = 0xb7;
- bclk = 0x47;
- } else if (srate < 3000000) {
- aclk = 0xb7;
- bclk = 0x4b;
- } else if (srate < 7000000) {
- aclk = 0xb7;
- bclk = 0x4f;
- } else if (srate < 14000000) {
- aclk = 0xb7;
- bclk = 0x53;
- } else if (srate < 30000000) {
- aclk = 0xb6;
- bclk = 0x53;
- } else if (srate < 45000000) {
- aclk = 0xb4;
- bclk = 0x51;
- }
-
- stv0299_writereg(fe, 0x13, aclk);
- stv0299_writereg(fe, 0x14, bclk);
- stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
- stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
- stv0299_writereg(fe, 0x21, ratio & 0xf0);
-
- return 0;
-}
-
-static int alps_bsru6_tuner_set_params(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- u8 buf[4];
- u32 div;
- struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
- struct i2c_adapter *i2c = fe->tuner_priv;
-
- if ((p->frequency < 950000) || (p->frequency > 2150000))
- return -EINVAL;
-
- div = (p->frequency + (125 - 1)) / 125; /* round correctly */
- buf[0] = (div >> 8) & 0x7f;
- buf[1] = div & 0xff;
- buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
- buf[3] = 0xC4;
-
- if (p->frequency > 1530000)
- buf[3] = 0xc0;
-
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
- if (i2c_transfer(i2c, &msg, 1) != 1)
- return -EIO;
- return 0;
-}
-
-static struct stv0299_config alps_bsru6_config = {
- .demod_address = 0x68,
- .inittab = alps_bsru6_inittab,
- .mclk = 88000000UL,
- .invert = 1,
- .skip_reinit = 0,
- .lock_output = STV0299_LOCKOUTPUT_1,
- .volt13_op0_op1 = STV0299_VOLT13_OP1,
- .min_delay_ms = 100,
- .set_symbol_rate = alps_bsru6_set_symbol_rate,
-};
-
-#endif
diff --git a/drivers/media/dvb/frontends/cx22700.c b/drivers/media/dvb/frontends/cx22700.c
deleted file mode 100644
index f2a90f990ce..00000000000
--- a/drivers/media/dvb/frontends/cx22700.c
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- Conexant cx22700 DVB OFDM demodulator driver
-
- Copyright (C) 2001-2002 Convergence Integrated Media GmbH
- Holger Waechtler <holger@convergence.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include "dvb_frontend.h"
-#include "cx22700.h"
-
-
-struct cx22700_state {
-
- struct i2c_adapter* i2c;
-
- const struct cx22700_config* config;
-
- struct dvb_frontend frontend;
-};
-
-
-static int debug;
-#define dprintk(args...) \
- do { \
- if (debug) printk(KERN_DEBUG "cx22700: " args); \
- } while (0)
-
-static u8 init_tab [] = {
- 0x04, 0x10,
- 0x05, 0x09,
- 0x06, 0x00,
- 0x08, 0x04,
- 0x09, 0x00,
- 0x0a, 0x01,
- 0x15, 0x40,
- 0x16, 0x10,
- 0x17, 0x87,
- 0x18, 0x17,
- 0x1a, 0x10,
- 0x25, 0x04,
- 0x2e, 0x00,
- 0x39, 0x00,
- 0x3a, 0x04,
- 0x45, 0x08,
- 0x46, 0x02,
- 0x47, 0x05,
-};
-
-
-static int cx22700_writereg (struct cx22700_state* state, u8 reg, u8 data)
-{
- int ret;
- u8 buf [] = { reg, data };
- struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
-
- dprintk ("%s\n", __func__);
-
- ret = i2c_transfer (state->i2c, &msg, 1);
-
- if (ret != 1)
- printk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
- __func__, reg, data, ret);
-
- return (ret != 1) ? -1 : 0;
-}
-
-static int cx22700_readreg (struct cx22700_state* state, u8 reg)
-{
- int ret;
- u8 b0 [] = { reg };
- u8 b1 [] = { 0 };
- struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
- { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
-
- dprintk ("%s\n", __func__);
-
- ret = i2c_transfer (state->i2c, msg, 2);
-
- if (ret != 2) return -EIO;
-
- return b1[0];
-}
-
-static int cx22700_set_inversion (struct cx22700_state* state, int inversion)
-{
- u8 val;
-
- dprintk ("%s\n", __func__);
-
- switch (inversion) {
- case INVERSION_AUTO:
- return -EOPNOTSUPP;
- case INVERSION_ON:
- val = cx22700_readreg (state, 0x09);
- return cx22700_writereg (state, 0x09, val | 0x01);
- case INVERSION_OFF:
- val = cx22700_readreg (state, 0x09);
- return cx22700_writereg (state, 0x09, val & 0xfe);
- default:
- return -EINVAL;
- }
-}
-
-static int cx22700_set_tps(struct cx22700_state *state,
- struct dtv_frontend_properties *p)
-{
- static const u8 qam_tab [4] = { 0, 1, 0, 2 };
- static const u8 fec_tab [6] = { 0, 1, 2, 0, 3, 4 };
- u8 val;
-
- dprintk ("%s\n", __func__);
-
- if (p->code_rate_HP < FEC_1_2 || p->code_rate_HP > FEC_7_8)
- return -EINVAL;
-
- if (p->code_rate_LP < FEC_1_2 || p->code_rate_LP > FEC_7_8)
- return -EINVAL;
-
- if (p->code_rate_HP == FEC_4_5 || p->code_rate_LP == FEC_4_5)
- return -EINVAL;
-
- if (p->guard_interval < GUARD_INTERVAL_1_32 ||
- p->guard_interval > GUARD_INTERVAL_1_4)
- return -EINVAL;
-
- if (p->transmission_mode != TRANSMISSION_MODE_2K &&
- p->transmission_mode != TRANSMISSION_MODE_8K)
- return -EINVAL;
-
- if (p->modulation != QPSK &&
- p->modulation != QAM_16 &&
- p->modulation != QAM_64)
- return -EINVAL;
-
- if (p->hierarchy < HIERARCHY_NONE ||
- p->hierarchy > HIERARCHY_4)
- return -EINVAL;
-
- if (p->bandwidth_hz > 8000000 || p->bandwidth_hz < 6000000)
- return -EINVAL;
-
- if (p->bandwidth_hz == 7000000)
- cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 | 0x10));
- else
- cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 & ~0x10));
-
- val = qam_tab[p->modulation - QPSK];
- val |= p->hierarchy - HIERARCHY_NONE;
-
- cx22700_writereg (state, 0x04, val);
-
- val = fec_tab[p->code_rate_HP - FEC_1_2] << 3;
- val |= fec_tab[p->code_rate_LP - FEC_1_2];
-
- cx22700_writereg (state, 0x05, val);
-
- val = (p->guard_interval - GUARD_INTERVAL_1_32) << 2;
- val |= p->transmission_mode - TRANSMISSION_MODE_2K;
-
- cx22700_writereg (state, 0x06, val);
-
- cx22700_writereg (state, 0x08, 0x04 | 0x02); /* use user tps parameters */
- cx22700_writereg (state, 0x08, 0x04); /* restart acquisition */
-
- return 0;
-}
-
-static int cx22700_get_tps(struct cx22700_state *state,
- struct dtv_frontend_properties *p)
-{
- static const fe_modulation_t qam_tab [3] = { QPSK, QAM_16, QAM_64 };
- static const fe_code_rate_t fec_tab [5] = { FEC_1_2, FEC_2_3, FEC_3_4,
- FEC_5_6, FEC_7_8 };
- u8 val;
-
- dprintk ("%s\n", __func__);
-
- if (!(cx22700_readreg(state, 0x07) & 0x20)) /* tps valid? */
- return -EAGAIN;
-
- val = cx22700_readreg (state, 0x01);
-
- if ((val & 0x7) > 4)
- p->hierarchy = HIERARCHY_AUTO;
- else
- p->hierarchy = HIERARCHY_NONE + (val & 0x7);
-
- if (((val >> 3) & 0x3) > 2)
- p->modulation = QAM_AUTO;
- else
- p->modulation = qam_tab[(val >> 3) & 0x3];
-
- val = cx22700_readreg (state, 0x02);
-
- if (((val >> 3) & 0x07) > 4)
- p->code_rate_HP = FEC_AUTO;
- else
- p->code_rate_HP = fec_tab[(val >> 3) & 0x07];
-
- if ((val & 0x07) > 4)
- p->code_rate_LP = FEC_AUTO;
- else
- p->code_rate_LP = fec_tab[val & 0x07];
-
- val = cx22700_readreg (state, 0x03);
-
- p->guard_interval = GUARD_INTERVAL_1_32 + ((val >> 6) & 0x3);
- p->transmission_mode = TRANSMISSION_MODE_2K + ((val >> 5) & 0x1);
-
- return 0;
-}
-
-static int cx22700_init (struct dvb_frontend* fe)
-
-{ struct cx22700_state* state = fe->demodulator_priv;
- int i;
-
- dprintk("cx22700_init: init chip\n");
-
- cx22700_writereg (state, 0x00, 0x02); /* soft reset */
- cx22700_writereg (state, 0x00, 0x00);
-
- msleep(10);
-
- for (i=0; i<sizeof(init_tab); i+=2)
- cx22700_writereg (state, init_tab[i], init_tab[i+1]);
-
- cx22700_writereg (state, 0x00, 0x01);
-
- return 0;
-}
-
-static int cx22700_read_status(struct dvb_frontend* fe, fe_status_t* status)
-{
- struct cx22700_state* state = fe->demodulator_priv;
-
- u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9)
- | (cx22700_readreg (state, 0x0e) << 1);
- u8 sync = cx22700_readreg (state, 0x07);
-
- *status = 0;
-
- if (rs_ber < 0xff00)
- *status |= FE_HAS_SIGNAL;
-
- if (sync & 0x20)
- *status |= FE_HAS_CARRIER;
-
- if (sync & 0x10)
- *status |= FE_HAS_VITERBI;
-
- if (sync & 0x10)
- *status |= FE_HAS_SYNC;
-
- if (*status == 0x0f)
- *status |= FE_HAS_LOCK;
-
- return 0;
-}
-
-static int cx22700_read_ber(struct dvb_frontend* fe, u32* ber)
-{
- struct cx22700_state* state = fe->demodulator_priv;
-
- *ber = cx22700_readreg (state, 0x0c) & 0x7f;
- cx22700_writereg (state, 0x0c, 0x00);
-
- return 0;
-}
-
-static int cx22700_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
-{
- struct cx22700_state* state = fe->demodulator_priv;
-
- u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9)
- | (cx22700_readreg (state, 0x0e) << 1);
- *signal_strength = ~rs_ber;
-
- return 0;
-}
-
-static int cx22700_read_snr(struct dvb_frontend* fe, u16* snr)
-{
- struct cx22700_state* state = fe->demodulator_priv;
-
- u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9)
- | (cx22700_readreg (state, 0x0e) << 1);
- *snr = ~rs_ber;
-
- return 0;
-}
-
-static int cx22700_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
-{
- struct cx22700_state* state = fe->demodulator_priv;
-
- *ucblocks = cx22700_readreg (state, 0x0f);
- cx22700_writereg (state, 0x0f, 0x00);
-
- return 0;
-}
-
-static int cx22700_set_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct cx22700_state* state = fe->demodulator_priv;
-
- cx22700_writereg (state, 0x00, 0x02); /* XXX CHECKME: soft reset*/
- cx22700_writereg (state, 0x00, 0x00);
-
- if (fe->ops.tuner_ops.set_params) {
- fe->ops.tuner_ops.set_params(fe);
- if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
- }
-
- cx22700_set_inversion(state, c->inversion);
- cx22700_set_tps(state, c);
- cx22700_writereg (state, 0x37, 0x01); /* PAL loop filter off */
- cx22700_writereg (state, 0x00, 0x01); /* restart acquire */
-
- return 0;
-}
-
-static int cx22700_get_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct cx22700_state* state = fe->demodulator_priv;
- u8 reg09 = cx22700_readreg (state, 0x09);
-
- c->inversion = reg09 & 0x1 ? INVERSION_ON : INVERSION_OFF;
- return cx22700_get_tps(state, c);
-}
-
-static int cx22700_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
-{
- struct cx22700_state* state = fe->demodulator_priv;
-
- if (enable) {
- return cx22700_writereg(state, 0x0a, 0x00);
- } else {
- return cx22700_writereg(state, 0x0a, 0x01);
- }
-}
-
-static int cx22700_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
-{
- fesettings->min_delay_ms = 150;
- fesettings->step_size = 166667;
- fesettings->max_drift = 166667*2;
- return 0;
-}
-
-static void cx22700_release(struct dvb_frontend* fe)
-{
- struct cx22700_state* state = fe->demodulator_priv;
- kfree(state);
-}
-
-static struct dvb_frontend_ops cx22700_ops;
-
-struct dvb_frontend* cx22700_attach(const struct cx22700_config* config,
- struct i2c_adapter* i2c)
-{
- struct cx22700_state* state = NULL;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct cx22700_state), GFP_KERNEL);
- if (state == NULL) goto error;
-
- /* setup the state */
- state->config = config;
- state->i2c = i2c;
-
- /* check if the demod is there */
- if (cx22700_readreg(state, 0x07) < 0) goto error;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &cx22700_ops, sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
- return &state->frontend;
-
-error:
- kfree(state);
- return NULL;
-}
-
-static struct dvb_frontend_ops cx22700_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "Conexant CX22700 DVB-T",
- .frequency_min = 470000000,
- .frequency_max = 860000000,
- .frequency_stepsize = 166667,
- .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
- FE_CAN_RECOVER
- },
-
- .release = cx22700_release,
-
- .init = cx22700_init,
- .i2c_gate_ctrl = cx22700_i2c_gate_ctrl,
-
- .set_frontend = cx22700_set_frontend,
- .get_frontend = cx22700_get_frontend,
- .get_tune_settings = cx22700_get_tune_settings,
-
- .read_status = cx22700_read_status,
- .read_ber = cx22700_read_ber,
- .read_signal_strength = cx22700_read_signal_strength,
- .read_snr = cx22700_read_snr,
- .read_ucblocks = cx22700_read_ucblocks,
-};
-
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-
-MODULE_DESCRIPTION("Conexant CX22700 DVB-T Demodulator driver");
-MODULE_AUTHOR("Holger Waechtler");
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(cx22700_attach);
diff --git a/drivers/media/dvb/frontends/cx22700.h b/drivers/media/dvb/frontends/cx22700.h
deleted file mode 100644
index 4757a930ca0..00000000000
--- a/drivers/media/dvb/frontends/cx22700.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- Conexant CX22700 DVB OFDM demodulator driver
-
- Copyright (C) 2001-2002 Convergence Integrated Media GmbH
- Holger Waechtler <holger@convergence.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#ifndef CX22700_H
-#define CX22700_H
-
-#include <linux/dvb/frontend.h>
-
-struct cx22700_config
-{
- /* the demodulator's i2c address */
- u8 demod_address;
-};
-
-#if defined(CONFIG_DVB_CX22700) || (defined(CONFIG_DVB_CX22700_MODULE) && defined(MODULE))
-extern struct dvb_frontend* cx22700_attach(const struct cx22700_config* config,
- struct i2c_adapter* i2c);
-#else
-static inline struct dvb_frontend* cx22700_attach(const struct cx22700_config* config,
- struct i2c_adapter* i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif // CONFIG_DVB_CX22700
-
-#endif // CX22700_H
diff --git a/drivers/media/dvb/frontends/cx22702.c b/drivers/media/dvb/frontends/cx22702.c
deleted file mode 100644
index edc8eafc5c0..00000000000
--- a/drivers/media/dvb/frontends/cx22702.c
+++ /dev/null
@@ -1,653 +0,0 @@
-/*
- Conexant 22702 DVB OFDM demodulator driver
-
- based on:
- Alps TDMB7 DVB OFDM demodulator driver
-
- Copyright (C) 2001-2002 Convergence Integrated Media GmbH
- Holger Waechtler <holger@convergence.de>
-
- Copyright (C) 2004 Steven Toth <stoth@linuxtv.org>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include "dvb_frontend.h"
-#include "cx22702.h"
-
-struct cx22702_state {
-
- struct i2c_adapter *i2c;
-
- /* configuration settings */
- const struct cx22702_config *config;
-
- struct dvb_frontend frontend;
-
- /* previous uncorrected block counter */
- u8 prevUCBlocks;
-};
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Enable verbose debug messages");
-
-#define dprintk if (debug) printk
-
-/* Register values to initialise the demod */
-static const u8 init_tab[] = {
- 0x00, 0x00, /* Stop acquisition */
- 0x0B, 0x06,
- 0x09, 0x01,
- 0x0D, 0x41,
- 0x16, 0x32,
- 0x20, 0x0A,
- 0x21, 0x17,
- 0x24, 0x3e,
- 0x26, 0xff,
- 0x27, 0x10,
- 0x28, 0x00,
- 0x29, 0x00,
- 0x2a, 0x10,
- 0x2b, 0x00,
- 0x2c, 0x10,
- 0x2d, 0x00,
- 0x48, 0xd4,
- 0x49, 0x56,
- 0x6b, 0x1e,
- 0xc8, 0x02,
- 0xf9, 0x00,
- 0xfa, 0x00,
- 0xfb, 0x00,
- 0xfc, 0x00,
- 0xfd, 0x00,
-};
-
-static int cx22702_writereg(struct cx22702_state *state, u8 reg, u8 data)
-{
- int ret;
- u8 buf[] = { reg, data };
- struct i2c_msg msg = {
- .addr = state->config->demod_address, .flags = 0,
- .buf = buf, .len = 2 };
-
- ret = i2c_transfer(state->i2c, &msg, 1);
-
- if (unlikely(ret != 1)) {
- printk(KERN_ERR
- "%s: error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
- __func__, reg, data, ret);
- return -1;
- }
-
- return 0;
-}
-
-static u8 cx22702_readreg(struct cx22702_state *state, u8 reg)
-{
- int ret;
- u8 data;
-
- struct i2c_msg msg[] = {
- { .addr = state->config->demod_address, .flags = 0,
- .buf = &reg, .len = 1 },
- { .addr = state->config->demod_address, .flags = I2C_M_RD,
- .buf = &data, .len = 1 } };
-
- ret = i2c_transfer(state->i2c, msg, 2);
-
- if (unlikely(ret != 2)) {
- printk(KERN_ERR "%s: error (reg == 0x%02x, ret == %i)\n",
- __func__, reg, ret);
- return 0;
- }
-
- return data;
-}
-
-static int cx22702_set_inversion(struct cx22702_state *state, int inversion)
-{
- u8 val;
-
- val = cx22702_readreg(state, 0x0C);
- switch (inversion) {
- case INVERSION_AUTO:
- return -EOPNOTSUPP;
- case INVERSION_ON:
- val |= 0x01;
- break;
- case INVERSION_OFF:
- val &= 0xfe;
- break;
- default:
- return -EINVAL;
- }
- return cx22702_writereg(state, 0x0C, val);
-}
-
-/* Retrieve the demod settings */
-static int cx22702_get_tps(struct cx22702_state *state,
- struct dtv_frontend_properties *p)
-{
- u8 val;
-
- /* Make sure the TPS regs are valid */
- if (!(cx22702_readreg(state, 0x0A) & 0x20))
- return -EAGAIN;
-
- val = cx22702_readreg(state, 0x01);
- switch ((val & 0x18) >> 3) {
- case 0:
- p->modulation = QPSK;
- break;
- case 1:
- p->modulation = QAM_16;
- break;
- case 2:
- p->modulation = QAM_64;
- break;
- }
- switch (val & 0x07) {
- case 0:
- p->hierarchy = HIERARCHY_NONE;
- break;
- case 1:
- p->hierarchy = HIERARCHY_1;
- break;
- case 2:
- p->hierarchy = HIERARCHY_2;
- break;
- case 3:
- p->hierarchy = HIERARCHY_4;
- break;
- }
-
-
- val = cx22702_readreg(state, 0x02);
- switch ((val & 0x38) >> 3) {
- case 0:
- p->code_rate_HP = FEC_1_2;
- break;
- case 1:
- p->code_rate_HP = FEC_2_3;
- break;
- case 2:
- p->code_rate_HP = FEC_3_4;
- break;
- case 3:
- p->code_rate_HP = FEC_5_6;
- break;
- case 4:
- p->code_rate_HP = FEC_7_8;
- break;
- }
- switch (val & 0x07) {
- case 0:
- p->code_rate_LP = FEC_1_2;
- break;
- case 1:
- p->code_rate_LP = FEC_2_3;
- break;
- case 2:
- p->code_rate_LP = FEC_3_4;
- break;
- case 3:
- p->code_rate_LP = FEC_5_6;
- break;
- case 4:
- p->code_rate_LP = FEC_7_8;
- break;
- }
-
- val = cx22702_readreg(state, 0x03);
- switch ((val & 0x0c) >> 2) {
- case 0:
- p->guard_interval = GUARD_INTERVAL_1_32;
- break;
- case 1:
- p->guard_interval = GUARD_INTERVAL_1_16;
- break;
- case 2:
- p->guard_interval = GUARD_INTERVAL_1_8;
- break;
- case 3:
- p->guard_interval = GUARD_INTERVAL_1_4;
- break;
- }
- switch (val & 0x03) {
- case 0:
- p->transmission_mode = TRANSMISSION_MODE_2K;
- break;
- case 1:
- p->transmission_mode = TRANSMISSION_MODE_8K;
- break;
- }
-
- return 0;
-}
-
-static int cx22702_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- struct cx22702_state *state = fe->demodulator_priv;
- u8 val;
-
- dprintk("%s(%d)\n", __func__, enable);
- val = cx22702_readreg(state, 0x0D);
- if (enable)
- val &= 0xfe;
- else
- val |= 0x01;
- return cx22702_writereg(state, 0x0D, val);
-}
-
-/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
-static int cx22702_set_tps(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- u8 val;
- struct cx22702_state *state = fe->demodulator_priv;
-
- if (fe->ops.tuner_ops.set_params) {
- fe->ops.tuner_ops.set_params(fe);
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 0);
- }
-
- /* set inversion */
- cx22702_set_inversion(state, p->inversion);
-
- /* set bandwidth */
- val = cx22702_readreg(state, 0x0C) & 0xcf;
- switch (p->bandwidth_hz) {
- case 6000000:
- val |= 0x20;
- break;
- case 7000000:
- val |= 0x10;
- break;
- case 8000000:
- break;
- default:
- dprintk("%s: invalid bandwidth\n", __func__);
- return -EINVAL;
- }
- cx22702_writereg(state, 0x0C, val);
-
- p->code_rate_LP = FEC_AUTO; /* temp hack as manual not working */
-
- /* use auto configuration? */
- if ((p->hierarchy == HIERARCHY_AUTO) ||
- (p->modulation == QAM_AUTO) ||
- (p->code_rate_HP == FEC_AUTO) ||
- (p->code_rate_LP == FEC_AUTO) ||
- (p->guard_interval == GUARD_INTERVAL_AUTO) ||
- (p->transmission_mode == TRANSMISSION_MODE_AUTO)) {
-
- /* TPS Source - use hardware driven values */
- cx22702_writereg(state, 0x06, 0x10);
- cx22702_writereg(state, 0x07, 0x9);
- cx22702_writereg(state, 0x08, 0xC1);
- cx22702_writereg(state, 0x0B, cx22702_readreg(state, 0x0B)
- & 0xfc);
- cx22702_writereg(state, 0x0C,
- (cx22702_readreg(state, 0x0C) & 0xBF) | 0x40);
- cx22702_writereg(state, 0x00, 0x01); /* Begin acquisition */
- dprintk("%s: Autodetecting\n", __func__);
- return 0;
- }
-
- /* manually programmed values */
- switch (p->modulation) { /* mask 0x18 */
- case QPSK:
- val = 0x00;
- break;
- case QAM_16:
- val = 0x08;
- break;
- case QAM_64:
- val = 0x10;
- break;
- default:
- dprintk("%s: invalid modulation\n", __func__);
- return -EINVAL;
- }
- switch (p->hierarchy) { /* mask 0x07 */
- case HIERARCHY_NONE:
- break;
- case HIERARCHY_1:
- val |= 0x01;
- break;
- case HIERARCHY_2:
- val |= 0x02;
- break;
- case HIERARCHY_4:
- val |= 0x03;
- break;
- default:
- dprintk("%s: invalid hierarchy\n", __func__);
- return -EINVAL;
- }
- cx22702_writereg(state, 0x06, val);
-
- switch (p->code_rate_HP) { /* mask 0x38 */
- case FEC_NONE:
- case FEC_1_2:
- val = 0x00;
- break;
- case FEC_2_3:
- val = 0x08;
- break;
- case FEC_3_4:
- val = 0x10;
- break;
- case FEC_5_6:
- val = 0x18;
- break;
- case FEC_7_8:
- val = 0x20;
- break;
- default:
- dprintk("%s: invalid code_rate_HP\n", __func__);
- return -EINVAL;
- }
- switch (p->code_rate_LP) { /* mask 0x07 */
- case FEC_NONE:
- case FEC_1_2:
- break;
- case FEC_2_3:
- val |= 0x01;
- break;
- case FEC_3_4:
- val |= 0x02;
- break;
- case FEC_5_6:
- val |= 0x03;
- break;
- case FEC_7_8:
- val |= 0x04;
- break;
- default:
- dprintk("%s: invalid code_rate_LP\n", __func__);
- return -EINVAL;
- }
- cx22702_writereg(state, 0x07, val);
-
- switch (p->guard_interval) { /* mask 0x0c */
- case GUARD_INTERVAL_1_32:
- val = 0x00;
- break;
- case GUARD_INTERVAL_1_16:
- val = 0x04;
- break;
- case GUARD_INTERVAL_1_8:
- val = 0x08;
- break;
- case GUARD_INTERVAL_1_4:
- val = 0x0c;
- break;
- default:
- dprintk("%s: invalid guard_interval\n", __func__);
- return -EINVAL;
- }
- switch (p->transmission_mode) { /* mask 0x03 */
- case TRANSMISSION_MODE_2K:
- break;
- case TRANSMISSION_MODE_8K:
- val |= 0x1;
- break;
- default:
- dprintk("%s: invalid transmission_mode\n", __func__);
- return -EINVAL;
- }
- cx22702_writereg(state, 0x08, val);
- cx22702_writereg(state, 0x0B,
- (cx22702_readreg(state, 0x0B) & 0xfc) | 0x02);
- cx22702_writereg(state, 0x0C,
- (cx22702_readreg(state, 0x0C) & 0xBF) | 0x40);
-
- /* Begin channel acquisition */
- cx22702_writereg(state, 0x00, 0x01);
-
- return 0;
-}
-
-/* Reset the demod hardware and reset all of the configuration registers
- to a default state. */
-static int cx22702_init(struct dvb_frontend *fe)
-{
- int i;
- struct cx22702_state *state = fe->demodulator_priv;
-
- cx22702_writereg(state, 0x00, 0x02);
-
- msleep(10);
-
- for (i = 0; i < ARRAY_SIZE(init_tab); i += 2)
- cx22702_writereg(state, init_tab[i], init_tab[i + 1]);
-
- cx22702_writereg(state, 0xf8, (state->config->output_mode << 1)
- & 0x02);
-
- cx22702_i2c_gate_ctrl(fe, 0);
-
- return 0;
-}
-
-static int cx22702_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct cx22702_state *state = fe->demodulator_priv;
- u8 reg0A;
- u8 reg23;
-
- *status = 0;
-
- reg0A = cx22702_readreg(state, 0x0A);
- reg23 = cx22702_readreg(state, 0x23);
-
- dprintk("%s: status demod=0x%02x agc=0x%02x\n"
- , __func__, reg0A, reg23);
-
- if (reg0A & 0x10) {
- *status |= FE_HAS_LOCK;
- *status |= FE_HAS_VITERBI;
- *status |= FE_HAS_SYNC;
- }
-
- if (reg0A & 0x20)
- *status |= FE_HAS_CARRIER;
-
- if (reg23 < 0xf0)
- *status |= FE_HAS_SIGNAL;
-
- return 0;
-}
-
-static int cx22702_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct cx22702_state *state = fe->demodulator_priv;
-
- if (cx22702_readreg(state, 0xE4) & 0x02) {
- /* Realtime statistics */
- *ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7
- | (cx22702_readreg(state, 0xDF) & 0x7F);
- } else {
- /* Averagtine statistics */
- *ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7
- | cx22702_readreg(state, 0xDF);
- }
-
- return 0;
-}
-
-static int cx22702_read_signal_strength(struct dvb_frontend *fe,
- u16 *signal_strength)
-{
- struct cx22702_state *state = fe->demodulator_priv;
- u8 reg23;
-
- /*
- * Experience suggests that the strength signal register works as
- * follows:
- * - In the absence of signal, value is 0xff.
- * - In the presence of a weak signal, bit 7 is set, not sure what
- * the lower 7 bits mean.
- * - In the presence of a strong signal, the register holds a 7-bit
- * value (bit 7 is cleared), with greater values standing for
- * weaker signals.
- */
- reg23 = cx22702_readreg(state, 0x23);
- if (reg23 & 0x80) {
- *signal_strength = 0;
- } else {
- reg23 = ~reg23 & 0x7f;
- /* Scale to 16 bit */
- *signal_strength = (reg23 << 9) | (reg23 << 2) | (reg23 >> 5);
- }
-
- return 0;
-}
-
-static int cx22702_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- struct cx22702_state *state = fe->demodulator_priv;
-
- u16 rs_ber;
- if (cx22702_readreg(state, 0xE4) & 0x02) {
- /* Realtime statistics */
- rs_ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7
- | (cx22702_readreg(state, 0xDF) & 0x7F);
- } else {
- /* Averagine statistics */
- rs_ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 8
- | cx22702_readreg(state, 0xDF);
- }
- *snr = ~rs_ber;
-
- return 0;
-}
-
-static int cx22702_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- struct cx22702_state *state = fe->demodulator_priv;
-
- u8 _ucblocks;
-
- /* RS Uncorrectable Packet Count then reset */
- _ucblocks = cx22702_readreg(state, 0xE3);
- if (state->prevUCBlocks < _ucblocks)
- *ucblocks = (_ucblocks - state->prevUCBlocks);
- else
- *ucblocks = state->prevUCBlocks - _ucblocks;
- state->prevUCBlocks = _ucblocks;
-
- return 0;
-}
-
-static int cx22702_get_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct cx22702_state *state = fe->demodulator_priv;
-
- u8 reg0C = cx22702_readreg(state, 0x0C);
-
- c->inversion = reg0C & 0x1 ? INVERSION_ON : INVERSION_OFF;
- return cx22702_get_tps(state, c);
-}
-
-static int cx22702_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *tune)
-{
- tune->min_delay_ms = 1000;
- return 0;
-}
-
-static void cx22702_release(struct dvb_frontend *fe)
-{
- struct cx22702_state *state = fe->demodulator_priv;
- kfree(state);
-}
-
-static const struct dvb_frontend_ops cx22702_ops;
-
-struct dvb_frontend *cx22702_attach(const struct cx22702_config *config,
- struct i2c_adapter *i2c)
-{
- struct cx22702_state *state = NULL;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct cx22702_state), GFP_KERNEL);
- if (state == NULL)
- goto error;
-
- /* setup the state */
- state->config = config;
- state->i2c = i2c;
-
- /* check if the demod is there */
- if (cx22702_readreg(state, 0x1f) != 0x3)
- goto error;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &cx22702_ops,
- sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
- return &state->frontend;
-
-error:
- kfree(state);
- return NULL;
-}
-EXPORT_SYMBOL(cx22702_attach);
-
-static const struct dvb_frontend_ops cx22702_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "Conexant CX22702 DVB-T",
- .frequency_min = 177000000,
- .frequency_max = 858000000,
- .frequency_stepsize = 166666,
- .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
- },
-
- .release = cx22702_release,
-
- .init = cx22702_init,
- .i2c_gate_ctrl = cx22702_i2c_gate_ctrl,
-
- .set_frontend = cx22702_set_tps,
- .get_frontend = cx22702_get_frontend,
- .get_tune_settings = cx22702_get_tune_settings,
-
- .read_status = cx22702_read_status,
- .read_ber = cx22702_read_ber,
- .read_signal_strength = cx22702_read_signal_strength,
- .read_snr = cx22702_read_snr,
- .read_ucblocks = cx22702_read_ucblocks,
-};
-
-MODULE_DESCRIPTION("Conexant CX22702 DVB-T Demodulator driver");
-MODULE_AUTHOR("Steven Toth");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/cx22702.h b/drivers/media/dvb/frontends/cx22702.h
deleted file mode 100644
index f154e1f428e..00000000000
--- a/drivers/media/dvb/frontends/cx22702.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- Conexant 22702 DVB OFDM demodulator driver
-
- based on:
- Alps TDMB7 DVB OFDM demodulator driver
-
- Copyright (C) 2001-2002 Convergence Integrated Media GmbH
- Holger Waechtler <holger@convergence.de>
-
- Copyright (C) 2004 Steven Toth <stoth@linuxtv.org>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#ifndef CX22702_H
-#define CX22702_H
-
-#include <linux/dvb/frontend.h>
-
-struct cx22702_config {
- /* the demodulator's i2c address */
- u8 demod_address;
-
- /* serial/parallel output */
-#define CX22702_PARALLEL_OUTPUT 0
-#define CX22702_SERIAL_OUTPUT 1
- u8 output_mode;
-};
-
-#if defined(CONFIG_DVB_CX22702) || (defined(CONFIG_DVB_CX22702_MODULE) \
- && defined(MODULE))
-extern struct dvb_frontend *cx22702_attach(
- const struct cx22702_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline struct dvb_frontend *cx22702_attach(
- const struct cx22702_config *config,
- struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif
diff --git a/drivers/media/dvb/frontends/cx24110.c b/drivers/media/dvb/frontends/cx24110.c
deleted file mode 100644
index 3180f5b2a6a..00000000000
--- a/drivers/media/dvb/frontends/cx24110.c
+++ /dev/null
@@ -1,666 +0,0 @@
-/*
- cx24110 - Single Chip Satellite Channel Receiver driver module
-
- Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
- work
- Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include "dvb_frontend.h"
-#include "cx24110.h"
-
-
-struct cx24110_state {
-
- struct i2c_adapter* i2c;
-
- const struct cx24110_config* config;
-
- struct dvb_frontend frontend;
-
- u32 lastber;
- u32 lastbler;
- u32 lastesn0;
-};
-
-static int debug;
-#define dprintk(args...) \
- do { \
- if (debug) printk(KERN_DEBUG "cx24110: " args); \
- } while (0)
-
-static struct {u8 reg; u8 data;} cx24110_regdata[]=
- /* Comments beginning with @ denote this value should
- be the default */
- {{0x09,0x01}, /* SoftResetAll */
- {0x09,0x00}, /* release reset */
- {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
- {0x02,0x17}, /* middle byte " */
- {0x03,0x29}, /* LSB " */
- {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
- {0x06,0xa5}, /* @ PLL 60MHz */
- {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
- {0x0a,0x00}, /* @ partial chip disables, do not set */
- {0x0b,0x01}, /* set output clock in gapped mode, start signal low
- active for first byte */
- {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
- {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
- {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
- to avoid starting the BER counter. Reset the
- CRC test bit. Finite counting selected */
- {0x15,0xff}, /* @ size of the limited time window for RS BER
- estimation. It is <value>*256 RS blocks, this
- gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
- {0x16,0x00}, /* @ enable all RS output ports */
- {0x17,0x04}, /* @ time window allowed for the RS to sync */
- {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
- for automatically */
- /* leave the current code rate and normalization
- registers as they are after reset... */
- {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
- only once */
- {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
- estimation. It is <value>*65536 channel bits, i.e.
- approx. 38ms at 27.5MS/s, rate 3/4 */
- {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
- /* leave front-end AGC parameters at default values */
- /* leave decimation AGC parameters at default values */
- {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
- {0x36,0xff}, /* clear all interrupt pending flags */
- {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
- {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
- /* leave the equalizer parameters on their default values */
- /* leave the final AGC parameters on their default values */
- {0x41,0x00}, /* @ MSB of front-end derotator frequency */
- {0x42,0x00}, /* @ middle bytes " */
- {0x43,0x00}, /* @ LSB " */
- /* leave the carrier tracking loop parameters on default */
- /* leave the bit timing loop parameters at default */
- {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
- /* the cx24108 data sheet for symbol rates above 15MS/s */
- {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
- {0x61,0x95}, /* GPIO pins 1-4 have special function */
- {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
- {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
- {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
- {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
- {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
- {0x73,0x00}, /* @ disable several demod bypasses */
- {0x74,0x00}, /* @ " */
- {0x75,0x00} /* @ " */
- /* the remaining registers are for SEC */
- };
-
-
-static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
-{
- u8 buf [] = { reg, data };
- struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
- int err;
-
- if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
- dprintk ("%s: writereg error (err == %i, reg == 0x%02x,"
- " data == 0x%02x)\n", __func__, err, reg, data);
- return -EREMOTEIO;
- }
-
- return 0;
-}
-
-static int cx24110_readreg (struct cx24110_state* state, u8 reg)
-{
- int ret;
- u8 b0 [] = { reg };
- u8 b1 [] = { 0 };
- struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
- { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
-
- ret = i2c_transfer(state->i2c, msg, 2);
-
- if (ret != 2) return ret;
-
- return b1[0];
-}
-
-static int cx24110_set_inversion (struct cx24110_state* state, fe_spectral_inversion_t inversion)
-{
-/* fixme (low): error handling */
-
- switch (inversion) {
- case INVERSION_OFF:
- cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
- /* AcqSpectrInvDis on. No idea why someone should want this */
- cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
- /* Initial value 0 at start of acq */
- cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
- /* current value 0 */
- /* The cx24110 manual tells us this reg is read-only.
- But what the heck... set it ayways */
- break;
- case INVERSION_ON:
- cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
- /* AcqSpectrInvDis on. No idea why someone should want this */
- cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
- /* Initial value 1 at start of acq */
- cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
- /* current value 1 */
- break;
- case INVERSION_AUTO:
- cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
- /* AcqSpectrInvDis off. Leave initial & current states as is */
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec)
-{
-/* fixme (low): error handling */
-
- static const int rate[]={-1,1,2,3,5,7,-1};
- static const int g1[]={-1,0x01,0x02,0x05,0x15,0x45,-1};
- static const int g2[]={-1,0x01,0x03,0x06,0x1a,0x7a,-1};
-
- /* Well, the AutoAcq engine of the cx24106 and 24110 automatically
- searches all enabled viterbi rates, and can handle non-standard
- rates as well. */
-
- if (fec>FEC_AUTO)
- fec=FEC_AUTO;
-
- if (fec==FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
- cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xdf);
- /* clear AcqVitDis bit */
- cx24110_writereg(state,0x18,0xae);
- /* allow all DVB standard code rates */
- cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|0x3);
- /* set nominal Viterbi rate 3/4 */
- cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|0x3);
- /* set current Viterbi rate 3/4 */
- cx24110_writereg(state,0x1a,0x05); cx24110_writereg(state,0x1b,0x06);
- /* set the puncture registers for code rate 3/4 */
- return 0;
- } else {
- cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x20);
- /* set AcqVitDis bit */
- if(rate[fec]>0) {
- cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|rate[fec]);
- /* set nominal Viterbi rate */
- cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|rate[fec]);
- /* set current Viterbi rate */
- cx24110_writereg(state,0x1a,g1[fec]);
- cx24110_writereg(state,0x1b,g2[fec]);
- /* not sure if this is the right way: I always used AutoAcq mode */
- } else
- return -EOPNOTSUPP;
-/* fixme (low): which is the correct return code? */
- };
- return 0;
-}
-
-static fe_code_rate_t cx24110_get_fec (struct cx24110_state* state)
-{
- int i;
-
- i=cx24110_readreg(state,0x22)&0x0f;
- if(!(i&0x08)) {
- return FEC_1_2 + i - 1;
- } else {
-/* fixme (low): a special code rate has been selected. In theory, we need to
- return a denominator value, a numerator value, and a pair of puncture
- maps to correctly describe this mode. But this should never happen in
- practice, because it cannot be set by cx24110_get_fec. */
- return FEC_NONE;
- }
-}
-
-static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
-{
-/* fixme (low): add error handling */
- u32 ratio;
- u32 tmp, fclk, BDRI;
-
- static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
- int i;
-
- dprintk("cx24110 debug: entering %s(%d)\n",__func__,srate);
- if (srate>90999000UL/2)
- srate=90999000UL/2;
- if (srate<500000)
- srate=500000;
-
- for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)
- ;
- /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
- and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
- R06[3:0] PLLphaseDetGain */
- tmp=cx24110_readreg(state,0x07)&0xfc;
- if(srate<90999000UL/4) { /* sample rate 45MHz*/
- cx24110_writereg(state,0x07,tmp);
- cx24110_writereg(state,0x06,0x78);
- fclk=90999000UL/2;
- } else if(srate<60666000UL/2) { /* sample rate 60MHz */
- cx24110_writereg(state,0x07,tmp|0x1);
- cx24110_writereg(state,0x06,0xa5);
- fclk=60666000UL;
- } else if(srate<80888000UL/2) { /* sample rate 80MHz */
- cx24110_writereg(state,0x07,tmp|0x2);
- cx24110_writereg(state,0x06,0x87);
- fclk=80888000UL;
- } else { /* sample rate 90MHz */
- cx24110_writereg(state,0x07,tmp|0x3);
- cx24110_writereg(state,0x06,0x78);
- fclk=90999000UL;
- };
- dprintk("cx24110 debug: fclk %d Hz\n",fclk);
- /* we need to divide two integers with approx. 27 bits in 32 bit
- arithmetic giving a 25 bit result */
- /* the maximum dividend is 90999000/2, 0x02b6446c, this number is
- also the most complex divisor. Hence, the dividend has,
- assuming 32bit unsigned arithmetic, 6 clear bits on top, the
- divisor 2 unused bits at the bottom. Also, the quotient is
- always less than 1/2. Borrowed from VES1893.c, of course */
-
- tmp=srate<<6;
- BDRI=fclk>>2;
- ratio=(tmp/BDRI);
-
- tmp=(tmp%BDRI)<<8;
- ratio=(ratio<<8)+(tmp/BDRI);
-
- tmp=(tmp%BDRI)<<8;
- ratio=(ratio<<8)+(tmp/BDRI);
-
- tmp=(tmp%BDRI)<<1;
- ratio=(ratio<<1)+(tmp/BDRI);
-
- dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
- dprintk("fclk = %d\n", fclk);
- dprintk("ratio= %08x\n", ratio);
-
- cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
- cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
- cx24110_writereg(state, 0x3, (ratio)&0xff);
-
- return 0;
-
-}
-
-static int _cx24110_pll_write (struct dvb_frontend* fe, const u8 buf[], int len)
-{
- struct cx24110_state *state = fe->demodulator_priv;
-
- if (len != 3)
- return -EINVAL;
-
-/* tuner data is 21 bits long, must be left-aligned in data */
-/* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
-/* FIXME (low): add error handling, avoid infinite loops if HW fails... */
-
- cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
- cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
-
- /* if the auto tuner writer is still busy, clear it out */
- while (cx24110_readreg(state,0x6d)&0x80)
- cx24110_writereg(state,0x72,0);
-
- /* write the topmost 8 bits */
- cx24110_writereg(state,0x72,buf[0]);
-
- /* wait for the send to be completed */
- while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
- ;
-
- /* send another 8 bytes */
- cx24110_writereg(state,0x72,buf[1]);
- while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
- ;
-
- /* and the topmost 5 bits of this byte */
- cx24110_writereg(state,0x72,buf[2]);
- while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
- ;
-
- /* now strobe the enable line once */
- cx24110_writereg(state,0x6d,0x32);
- cx24110_writereg(state,0x6d,0x30);
-
- return 0;
-}
-
-static int cx24110_initfe(struct dvb_frontend* fe)
-{
- struct cx24110_state *state = fe->demodulator_priv;
-/* fixme (low): error handling */
- int i;
-
- dprintk("%s: init chip\n", __func__);
-
- for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
- cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
- };
-
- return 0;
-}
-
-static int cx24110_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
-{
- struct cx24110_state *state = fe->demodulator_priv;
-
- switch (voltage) {
- case SEC_VOLTAGE_13:
- return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
- case SEC_VOLTAGE_18:
- return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
- default:
- return -EINVAL;
- };
-}
-
-static int cx24110_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
-{
- int rv, bit;
- struct cx24110_state *state = fe->demodulator_priv;
- unsigned long timeout;
-
- if (burst == SEC_MINI_A)
- bit = 0x00;
- else if (burst == SEC_MINI_B)
- bit = 0x08;
- else
- return -EINVAL;
-
- rv = cx24110_readreg(state, 0x77);
- if (!(rv & 0x04))
- cx24110_writereg(state, 0x77, rv | 0x04);
-
- rv = cx24110_readreg(state, 0x76);
- cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));
- timeout = jiffies + msecs_to_jiffies(100);
- while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
- ; /* wait for LNB ready */
-
- return 0;
-}
-
-static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
- struct dvb_diseqc_master_cmd *cmd)
-{
- int i, rv;
- struct cx24110_state *state = fe->demodulator_priv;
- unsigned long timeout;
-
- if (cmd->msg_len < 3 || cmd->msg_len > 6)
- return -EINVAL; /* not implemented */
-
- for (i = 0; i < cmd->msg_len; i++)
- cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
-
- rv = cx24110_readreg(state, 0x77);
- if (rv & 0x04) {
- cx24110_writereg(state, 0x77, rv & ~0x04);
- msleep(30); /* reportedly fixes switching problems */
- }
-
- rv = cx24110_readreg(state, 0x76);
-
- cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
- timeout = jiffies + msecs_to_jiffies(100);
- while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
- ; /* wait for LNB ready */
-
- return 0;
-}
-
-static int cx24110_read_status(struct dvb_frontend* fe, fe_status_t* status)
-{
- struct cx24110_state *state = fe->demodulator_priv;
-
- int sync = cx24110_readreg (state, 0x55);
-
- *status = 0;
-
- if (sync & 0x10)
- *status |= FE_HAS_SIGNAL;
-
- if (sync & 0x08)
- *status |= FE_HAS_CARRIER;
-
- sync = cx24110_readreg (state, 0x08);
-
- if (sync & 0x40)
- *status |= FE_HAS_VITERBI;
-
- if (sync & 0x20)
- *status |= FE_HAS_SYNC;
-
- if ((sync & 0x60) == 0x60)
- *status |= FE_HAS_LOCK;
-
- return 0;
-}
-
-static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
-{
- struct cx24110_state *state = fe->demodulator_priv;
-
- /* fixme (maybe): value range is 16 bit. Scale? */
- if(cx24110_readreg(state,0x24)&0x10) {
- /* the Viterbi error counter has finished one counting window */
- cx24110_writereg(state,0x24,0x04); /* select the ber reg */
- state->lastber=cx24110_readreg(state,0x25)|
- (cx24110_readreg(state,0x26)<<8);
- cx24110_writereg(state,0x24,0x04); /* start new count window */
- cx24110_writereg(state,0x24,0x14);
- }
- *ber = state->lastber;
-
- return 0;
-}
-
-static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
-{
- struct cx24110_state *state = fe->demodulator_priv;
-
-/* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
- u8 signal = cx24110_readreg (state, 0x27)+128;
- *signal_strength = (signal << 8) | signal;
-
- return 0;
-}
-
-static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
-{
- struct cx24110_state *state = fe->demodulator_priv;
-
- /* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
- if(cx24110_readreg(state,0x6a)&0x80) {
- /* the Es/N0 error counter has finished one counting window */
- state->lastesn0=cx24110_readreg(state,0x69)|
- (cx24110_readreg(state,0x68)<<8);
- cx24110_writereg(state,0x6a,0x84); /* start new count window */
- }
- *snr = state->lastesn0;
-
- return 0;
-}
-
-static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
-{
- struct cx24110_state *state = fe->demodulator_priv;
-
- if(cx24110_readreg(state,0x10)&0x40) {
- /* the RS error counter has finished one counting window */
- cx24110_writereg(state,0x10,0x60); /* select the byer reg */
- (void)(cx24110_readreg(state, 0x12) |
- (cx24110_readreg(state, 0x13) << 8) |
- (cx24110_readreg(state, 0x14) << 16));
- cx24110_writereg(state,0x10,0x70); /* select the bler reg */
- state->lastbler=cx24110_readreg(state,0x12)|
- (cx24110_readreg(state,0x13)<<8)|
- (cx24110_readreg(state,0x14)<<16);
- cx24110_writereg(state,0x10,0x20); /* start new count window */
- }
- *ucblocks = state->lastbler;
-
- return 0;
-}
-
-static int cx24110_set_frontend(struct dvb_frontend *fe)
-{
- struct cx24110_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-
- if (fe->ops.tuner_ops.set_params) {
- fe->ops.tuner_ops.set_params(fe);
- if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
- }
-
- cx24110_set_inversion(state, p->inversion);
- cx24110_set_fec(state, p->fec_inner);
- cx24110_set_symbolrate(state, p->symbol_rate);
- cx24110_writereg(state,0x04,0x05); /* start acquisition */
-
- return 0;
-}
-
-static int cx24110_get_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- struct cx24110_state *state = fe->demodulator_priv;
- s32 afc; unsigned sclk;
-
-/* cannot read back tuner settings (freq). Need to have some private storage */
-
- sclk = cx24110_readreg (state, 0x07) & 0x03;
-/* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
- * Need 64 bit arithmetic. Is thiss possible in the kernel? */
- if (sclk==0) sclk=90999000L/2L;
- else if (sclk==1) sclk=60666000L;
- else if (sclk==2) sclk=80888000L;
- else sclk=90999000L;
- sclk>>=8;
- afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
- ((sclk*cx24110_readreg (state, 0x45))>>8)+
- ((sclk*cx24110_readreg (state, 0x46))>>16);
-
- p->frequency += afc;
- p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
- INVERSION_ON : INVERSION_OFF;
- p->fec_inner = cx24110_get_fec(state);
-
- return 0;
-}
-
-static int cx24110_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
-{
- struct cx24110_state *state = fe->demodulator_priv;
-
- return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
-}
-
-static void cx24110_release(struct dvb_frontend* fe)
-{
- struct cx24110_state* state = fe->demodulator_priv;
- kfree(state);
-}
-
-static struct dvb_frontend_ops cx24110_ops;
-
-struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
- struct i2c_adapter* i2c)
-{
- struct cx24110_state* state = NULL;
- int ret;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct cx24110_state), GFP_KERNEL);
- if (state == NULL) goto error;
-
- /* setup the state */
- state->config = config;
- state->i2c = i2c;
- state->lastber = 0;
- state->lastbler = 0;
- state->lastesn0 = 0;
-
- /* check if the demod is there */
- ret = cx24110_readreg(state, 0x00);
- if ((ret != 0x5a) && (ret != 0x69)) goto error;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
- return &state->frontend;
-
-error:
- kfree(state);
- return NULL;
-}
-
-static struct dvb_frontend_ops cx24110_ops = {
- .delsys = { SYS_DVBS },
- .info = {
- .name = "Conexant CX24110 DVB-S",
- .frequency_min = 950000,
- .frequency_max = 2150000,
- .frequency_stepsize = 1011, /* kHz for QPSK frontends */
- .frequency_tolerance = 29500,
- .symbol_rate_min = 1000000,
- .symbol_rate_max = 45000000,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_RECOVER
- },
-
- .release = cx24110_release,
-
- .init = cx24110_initfe,
- .write = _cx24110_pll_write,
- .set_frontend = cx24110_set_frontend,
- .get_frontend = cx24110_get_frontend,
- .read_status = cx24110_read_status,
- .read_ber = cx24110_read_ber,
- .read_signal_strength = cx24110_read_signal_strength,
- .read_snr = cx24110_read_snr,
- .read_ucblocks = cx24110_read_ucblocks,
-
- .diseqc_send_master_cmd = cx24110_send_diseqc_msg,
- .set_tone = cx24110_set_tone,
- .set_voltage = cx24110_set_voltage,
- .diseqc_send_burst = cx24110_diseqc_send_burst,
-};
-
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-
-MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
-MODULE_AUTHOR("Peter Hettkamp");
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(cx24110_attach);
diff --git a/drivers/media/dvb/frontends/cx24110.h b/drivers/media/dvb/frontends/cx24110.h
deleted file mode 100644
index fdcceee91f3..00000000000
--- a/drivers/media/dvb/frontends/cx24110.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- cx24110 - Single Chip Satellite Channel Receiver driver module
-
- Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
- work
- Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#ifndef CX24110_H
-#define CX24110_H
-
-#include <linux/dvb/frontend.h>
-
-struct cx24110_config
-{
- /* the demodulator's i2c address */
- u8 demod_address;
-};
-
-static inline int cx24110_pll_write(struct dvb_frontend *fe, u32 val)
-{
- u8 buf[] = {
- (u8)((val >> 24) & 0xff),
- (u8)((val >> 16) & 0xff),
- (u8)((val >> 8) & 0xff)
- };
-
- if (fe->ops.write)
- return fe->ops.write(fe, buf, 3);
- return 0;
-}
-
-#if defined(CONFIG_DVB_CX24110) || (defined(CONFIG_DVB_CX24110_MODULE) && defined(MODULE))
-extern struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
- struct i2c_adapter* i2c);
-#else
-static inline struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
- struct i2c_adapter* i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif // CONFIG_DVB_CX24110
-
-#endif // CX24110_H
diff --git a/drivers/media/dvb/frontends/cx24113.c b/drivers/media/dvb/frontends/cx24113.c
deleted file mode 100644
index 3883c3b31ae..00000000000
--- a/drivers/media/dvb/frontends/cx24113.c
+++ /dev/null
@@ -1,618 +0,0 @@
-/*
- * Driver for Conexant CX24113/CX24128 Tuner (Satellite)
- *
- * Copyright (C) 2007-8 Patrick Boettcher <pb@linuxtv.org>
- *
- * Developed for BBTI / Technisat
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include "dvb_frontend.h"
-#include "cx24113.h"
-
-static int debug;
-
-#define cx_info(args...) do { printk(KERN_INFO "CX24113: " args); } while (0)
-#define cx_err(args...) do { printk(KERN_ERR "CX24113: " args); } while (0)
-
-#define dprintk(args...) \
- do { \
- if (debug) { \
- printk(KERN_DEBUG "CX24113: %s: ", __func__); \
- printk(args); \
- } \
- } while (0)
-
-struct cx24113_state {
- struct i2c_adapter *i2c;
- const struct cx24113_config *config;
-
-#define REV_CX24113 0x23
- u8 rev;
- u8 ver;
-
- u8 icp_mode:1;
-
-#define ICP_LEVEL1 0
-#define ICP_LEVEL2 1
-#define ICP_LEVEL3 2
-#define ICP_LEVEL4 3
- u8 icp_man:2;
- u8 icp_auto_low:2;
- u8 icp_auto_mlow:2;
- u8 icp_auto_mhi:2;
- u8 icp_auto_hi:2;
- u8 icp_dig;
-
-#define LNA_MIN_GAIN 0
-#define LNA_MID_GAIN 1
-#define LNA_MAX_GAIN 2
- u8 lna_gain:2;
-
- u8 acp_on:1;
-
- u8 vco_mode:2;
- u8 vco_shift:1;
-#define VCOBANDSEL_6 0x80
-#define VCOBANDSEL_5 0x01
-#define VCOBANDSEL_4 0x02
-#define VCOBANDSEL_3 0x04
-#define VCOBANDSEL_2 0x08
-#define VCOBANDSEL_1 0x10
- u8 vco_band;
-
-#define VCODIV4 4
-#define VCODIV2 2
- u8 vcodiv;
-
- u8 bs_delay:4;
- u16 bs_freqcnt:13;
- u16 bs_rdiv;
- u8 prescaler_mode:1;
-
- u8 rfvga_bias_ctrl;
-
- s16 tuner_gain_thres;
- u8 gain_level;
-
- u32 frequency;
-
- u8 refdiv;
-
- u8 Fwindow_enabled;
-};
-
-static int cx24113_writereg(struct cx24113_state *state, int reg, int data)
-{
- u8 buf[] = { reg, data };
- struct i2c_msg msg = { .addr = state->config->i2c_addr,
- .flags = 0, .buf = buf, .len = 2 };
- int err = i2c_transfer(state->i2c, &msg, 1);
- if (err != 1) {
- printk(KERN_DEBUG "%s: writereg error(err == %i, reg == 0x%02x,"
- " data == 0x%02x)\n", __func__, err, reg, data);
- return err;
- }
-
- return 0;
-}
-
-static int cx24113_readreg(struct cx24113_state *state, u8 reg)
-{
- int ret;
- u8 b;
- struct i2c_msg msg[] = {
- { .addr = state->config->i2c_addr,
- .flags = 0, .buf = &reg, .len = 1 },
- { .addr = state->config->i2c_addr,
- .flags = I2C_M_RD, .buf = &b, .len = 1 }
- };
-
- ret = i2c_transfer(state->i2c, msg, 2);
-
- if (ret != 2) {
- printk(KERN_DEBUG "%s: reg=0x%x (error=%d)\n",
- __func__, reg, ret);
- return ret;
- }
-
- return b;
-}
-
-static void cx24113_set_parameters(struct cx24113_state *state)
-{
- u8 r;
-
- r = cx24113_readreg(state, 0x10) & 0x82;
- r |= state->icp_mode;
- r |= state->icp_man << 4;
- r |= state->icp_dig << 2;
- r |= state->prescaler_mode << 5;
- cx24113_writereg(state, 0x10, r);
-
- r = (state->icp_auto_low << 0) | (state->icp_auto_mlow << 2)
- | (state->icp_auto_mhi << 4) | (state->icp_auto_hi << 6);
- cx24113_writereg(state, 0x11, r);
-
- if (state->rev == REV_CX24113) {
- r = cx24113_readreg(state, 0x20) & 0xec;
- r |= state->lna_gain;
- r |= state->rfvga_bias_ctrl << 4;
- cx24113_writereg(state, 0x20, r);
- }
-
- r = cx24113_readreg(state, 0x12) & 0x03;
- r |= state->acp_on << 2;
- r |= state->bs_delay << 4;
- cx24113_writereg(state, 0x12, r);
-
- r = cx24113_readreg(state, 0x18) & 0x40;
- r |= state->vco_shift;
- if (state->vco_band == VCOBANDSEL_6)
- r |= (1 << 7);
- else
- r |= (state->vco_band << 1);
- cx24113_writereg(state, 0x18, r);
-
- r = cx24113_readreg(state, 0x14) & 0x20;
- r |= (state->vco_mode << 6) | ((state->bs_freqcnt >> 8) & 0x1f);
- cx24113_writereg(state, 0x14, r);
- cx24113_writereg(state, 0x15, (state->bs_freqcnt & 0xff));
-
- cx24113_writereg(state, 0x16, (state->bs_rdiv >> 4) & 0xff);
- r = (cx24113_readreg(state, 0x17) & 0x0f) |
- ((state->bs_rdiv & 0x0f) << 4);
- cx24113_writereg(state, 0x17, r);
-}
-
-#define VGA_0 0x00
-#define VGA_1 0x04
-#define VGA_2 0x02
-#define VGA_3 0x06
-#define VGA_4 0x01
-#define VGA_5 0x05
-#define VGA_6 0x03
-#define VGA_7 0x07
-
-#define RFVGA_0 0x00
-#define RFVGA_1 0x01
-#define RFVGA_2 0x02
-#define RFVGA_3 0x03
-
-static int cx24113_set_gain_settings(struct cx24113_state *state,
- s16 power_estimation)
-{
- u8 ampout = cx24113_readreg(state, 0x1d) & 0xf0,
- vga = cx24113_readreg(state, 0x1f) & 0x3f,
- rfvga = cx24113_readreg(state, 0x20) & 0xf3;
- u8 gain_level = power_estimation >= state->tuner_gain_thres;
-
- dprintk("power estimation: %d, thres: %d, gain_level: %d/%d\n",
- power_estimation, state->tuner_gain_thres,
- state->gain_level, gain_level);
-
- if (gain_level == state->gain_level)
- return 0; /* nothing to be done */
-
- ampout |= 0xf;
-
- if (gain_level) {
- rfvga |= RFVGA_0 << 2;
- vga |= (VGA_7 << 3) | VGA_7;
- } else {
- rfvga |= RFVGA_2 << 2;
- vga |= (VGA_6 << 3) | VGA_2;
- }
- state->gain_level = gain_level;
-
- cx24113_writereg(state, 0x1d, ampout);
- cx24113_writereg(state, 0x1f, vga);
- cx24113_writereg(state, 0x20, rfvga);
-
- return 1; /* did something */
-}
-
-static int cx24113_set_Fref(struct cx24113_state *state, u8 high)
-{
- u8 xtal = cx24113_readreg(state, 0x02);
- if (state->rev == 0x43 && state->vcodiv == VCODIV4)
- high = 1;
-
- xtal &= ~0x2;
- if (high)
- xtal |= high << 1;
- return cx24113_writereg(state, 0x02, xtal);
-}
-
-static int cx24113_enable(struct cx24113_state *state, u8 enable)
-{
- u8 r21 = (cx24113_readreg(state, 0x21) & 0xc0) | enable;
- if (state->rev == REV_CX24113)
- r21 |= (1 << 1);
- return cx24113_writereg(state, 0x21, r21);
-}
-
-static int cx24113_set_bandwidth(struct cx24113_state *state, u32 bandwidth_khz)
-{
- u8 r;
-
- if (bandwidth_khz <= 19000)
- r = 0x03 << 6;
- else if (bandwidth_khz <= 25000)
- r = 0x02 << 6;
- else
- r = 0x01 << 6;
-
- dprintk("bandwidth to be set: %d\n", bandwidth_khz);
- bandwidth_khz *= 10;
- bandwidth_khz -= 10000;
- bandwidth_khz /= 1000;
- bandwidth_khz += 5;
- bandwidth_khz /= 10;
-
- dprintk("bandwidth: %d %d\n", r >> 6, bandwidth_khz);
-
- r |= bandwidth_khz & 0x3f;
-
- return cx24113_writereg(state, 0x1e, r);
-}
-
-static int cx24113_set_clk_inversion(struct cx24113_state *state, u8 on)
-{
- u8 r = (cx24113_readreg(state, 0x10) & 0x7f) | ((on & 0x1) << 7);
- return cx24113_writereg(state, 0x10, r);
-}
-
-static int cx24113_get_status(struct dvb_frontend *fe, u32 *status)
-{
- struct cx24113_state *state = fe->tuner_priv;
- u8 r = (cx24113_readreg(state, 0x10) & 0x02) >> 1;
- if (r)
- *status |= TUNER_STATUS_LOCKED;
- dprintk("PLL locked: %d\n", r);
- return 0;
-}
-
-static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv)
-{
- if (state->rev == 0x43 && state->vcodiv == VCODIV4)
- refdiv = 2;
- return state->refdiv = refdiv;
-}
-
-static void cx24113_calc_pll_nf(struct cx24113_state *state, u16 *n, s32 *f)
-{
- s32 N;
- s64 F;
- u64 dividend;
- u8 R, r;
- u8 vcodiv;
- u8 factor;
- s32 freq_hz = state->frequency * 1000;
-
- if (state->config->xtal_khz < 20000)
- factor = 1;
- else
- factor = 2;
-
- if (state->rev == REV_CX24113) {
- if (state->frequency >= 1100000)
- vcodiv = VCODIV2;
- else
- vcodiv = VCODIV4;
- } else {
- if (state->frequency >= 1165000)
- vcodiv = VCODIV2;
- else
- vcodiv = VCODIV4;
- }
- state->vcodiv = vcodiv;
-
- dprintk("calculating N/F for %dHz with vcodiv %d\n", freq_hz, vcodiv);
- R = 0;
- do {
- R = cx24113_set_ref_div(state, R + 1);
-
- /* calculate tuner PLL settings: */
- N = (freq_hz / 100 * vcodiv) * R;
- N /= (state->config->xtal_khz) * factor * 2;
- N += 5; /* For round up. */
- N /= 10;
- N -= 32;
- } while (N < 6 && R < 3);
-
- if (N < 6) {
- cx_err("strange frequency: N < 6\n");
- return;
- }
- F = freq_hz;
- F *= (u64) (R * vcodiv * 262144);
- dprintk("1 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
- /* do_div needs an u64 as first argument */
- dividend = F;
- do_div(dividend, state->config->xtal_khz * 1000 * factor * 2);
- F = dividend;
- dprintk("2 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
- F -= (N + 32) * 262144;
-
- dprintk("3 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
-
- if (state->Fwindow_enabled) {
- if (F > (262144 / 2 - 1638))
- F = 262144 / 2 - 1638;
- if (F < (-262144 / 2 + 1638))
- F = -262144 / 2 + 1638;
- if ((F < 3277 && F > 0) || (F > -3277 && F < 0)) {
- F = 0;
- r = cx24113_readreg(state, 0x10);
- cx24113_writereg(state, 0x10, r | (1 << 6));
- }
- }
- dprintk("4 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
-
- *n = (u16) N;
- *f = (s32) F;
-}
-
-
-static void cx24113_set_nfr(struct cx24113_state *state, u16 n, s32 f, u8 r)
-{
- u8 reg;
- cx24113_writereg(state, 0x19, (n >> 1) & 0xff);
-
- reg = ((n & 0x1) << 7) | ((f >> 11) & 0x7f);
- cx24113_writereg(state, 0x1a, reg);
-
- cx24113_writereg(state, 0x1b, (f >> 3) & 0xff);
-
- reg = cx24113_readreg(state, 0x1c) & 0x1f;
- cx24113_writereg(state, 0x1c, reg | ((f & 0x7) << 5));
-
- cx24113_set_Fref(state, r - 1);
-}
-
-static int cx24113_set_frequency(struct cx24113_state *state, u32 frequency)
-{
- u8 r = 1; /* or 2 */
- u16 n = 6;
- s32 f = 0;
-
- r = cx24113_readreg(state, 0x14);
- cx24113_writereg(state, 0x14, r & 0x3f);
-
- r = cx24113_readreg(state, 0x10);
- cx24113_writereg(state, 0x10, r & 0xbf);
-
- state->frequency = frequency;
-
- dprintk("tuning to frequency: %d\n", frequency);
-
- cx24113_calc_pll_nf(state, &n, &f);
- cx24113_set_nfr(state, n, f, state->refdiv);
-
- r = cx24113_readreg(state, 0x18) & 0xbf;
- if (state->vcodiv != VCODIV2)
- r |= 1 << 6;
- cx24113_writereg(state, 0x18, r);
-
- /* The need for this sleep is not clear. But helps in some cases */
- msleep(5);
-
- r = cx24113_readreg(state, 0x1c) & 0xef;
- cx24113_writereg(state, 0x1c, r | (1 << 4));
- return 0;
-}
-
-static int cx24113_init(struct dvb_frontend *fe)
-{
- struct cx24113_state *state = fe->tuner_priv;
- int ret;
-
- state->tuner_gain_thres = -50;
- state->gain_level = 255; /* to force a gain-setting initialization */
- state->icp_mode = 0;
-
- if (state->config->xtal_khz < 11000) {
- state->icp_auto_hi = ICP_LEVEL4;
- state->icp_auto_mhi = ICP_LEVEL4;
- state->icp_auto_mlow = ICP_LEVEL3;
- state->icp_auto_low = ICP_LEVEL3;
- } else {
- state->icp_auto_hi = ICP_LEVEL4;
- state->icp_auto_mhi = ICP_LEVEL4;
- state->icp_auto_mlow = ICP_LEVEL3;
- state->icp_auto_low = ICP_LEVEL2;
- }
-
- state->icp_dig = ICP_LEVEL3;
- state->icp_man = ICP_LEVEL1;
- state->acp_on = 1;
- state->vco_mode = 0;
- state->vco_shift = 0;
- state->vco_band = VCOBANDSEL_1;
- state->bs_delay = 8;
- state->bs_freqcnt = 0x0fff;
- state->bs_rdiv = 0x0fff;
- state->prescaler_mode = 0;
- state->lna_gain = LNA_MAX_GAIN;
- state->rfvga_bias_ctrl = 1;
- state->Fwindow_enabled = 1;
-
- cx24113_set_Fref(state, 0);
- cx24113_enable(state, 0x3d);
- cx24113_set_parameters(state);
-
- cx24113_set_gain_settings(state, -30);
-
- cx24113_set_bandwidth(state, 18025);
- cx24113_set_clk_inversion(state, 1);
-
- if (state->config->xtal_khz >= 40000)
- ret = cx24113_writereg(state, 0x02,
- (cx24113_readreg(state, 0x02) & 0xfb) | (1 << 2));
- else
- ret = cx24113_writereg(state, 0x02,
- (cx24113_readreg(state, 0x02) & 0xfb) | (0 << 2));
-
- return ret;
-}
-
-static int cx24113_set_params(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct cx24113_state *state = fe->tuner_priv;
- /* for a ROLL-OFF factor of 0.35, 0.2: 600, 0.25: 625 */
- u32 roll_off = 675;
- u32 bw;
-
- bw = ((c->symbol_rate/100) * roll_off) / 1000;
- bw += (10000000/100) + 5;
- bw /= 10;
- bw += 1000;
- cx24113_set_bandwidth(state, bw);
-
- cx24113_set_frequency(state, c->frequency);
- msleep(5);
- return cx24113_get_status(fe, &bw);
-}
-
-static s8 cx24113_agc_table[2][10] = {
- {-54, -41, -35, -30, -25, -21, -16, -10, -6, -2},
- {-39, -35, -30, -25, -19, -15, -11, -5, 1, 9},
-};
-
-void cx24113_agc_callback(struct dvb_frontend *fe)
-{
- struct cx24113_state *state = fe->tuner_priv;
- s16 s, i;
- if (!fe->ops.read_signal_strength)
- return;
-
- do {
- /* this only works with the current CX24123 implementation */
- fe->ops.read_signal_strength(fe, (u16 *) &s);
- s >>= 8;
- dprintk("signal strength: %d\n", s);
- for (i = 0; i < sizeof(cx24113_agc_table[0]); i++)
- if (cx24113_agc_table[state->gain_level][i] > s)
- break;
- s = -25 - i*5;
- } while (cx24113_set_gain_settings(state, s));
-}
-EXPORT_SYMBOL(cx24113_agc_callback);
-
-static int cx24113_get_frequency(struct dvb_frontend *fe, u32 *frequency)
-{
- struct cx24113_state *state = fe->tuner_priv;
- *frequency = state->frequency;
- return 0;
-}
-
-static int cx24113_release(struct dvb_frontend *fe)
-{
- struct cx24113_state *state = fe->tuner_priv;
- dprintk("\n");
- fe->tuner_priv = NULL;
- kfree(state);
- return 0;
-}
-
-static const struct dvb_tuner_ops cx24113_tuner_ops = {
- .info = {
- .name = "Conexant CX24113",
- .frequency_min = 950000,
- .frequency_max = 2150000,
- .frequency_step = 125,
- },
-
- .release = cx24113_release,
-
- .init = cx24113_init,
-
- .set_params = cx24113_set_params,
- .get_frequency = cx24113_get_frequency,
- .get_status = cx24113_get_status,
-};
-
-struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe,
- const struct cx24113_config *config, struct i2c_adapter *i2c)
-{
- /* allocate memory for the internal state */
- struct cx24113_state *state =
- kzalloc(sizeof(struct cx24113_state), GFP_KERNEL);
- int rc;
- if (state == NULL) {
- cx_err("Unable to kzalloc\n");
- goto error;
- }
-
- /* setup the state */
- state->config = config;
- state->i2c = i2c;
-
- cx_info("trying to detect myself\n");
-
- /* making a dummy read, because of some expected troubles
- * after power on */
- cx24113_readreg(state, 0x00);
-
- rc = cx24113_readreg(state, 0x00);
- if (rc < 0) {
- cx_info("CX24113 not found.\n");
- goto error;
- }
- state->rev = rc;
-
- switch (rc) {
- case 0x43:
- cx_info("detected CX24113 variant\n");
- break;
- case REV_CX24113:
- cx_info("successfully detected\n");
- break;
- default:
- cx_err("unsupported device id: %x\n", state->rev);
- goto error;
- }
- state->ver = cx24113_readreg(state, 0x01);
- cx_info("version: %x\n", state->ver);
-
- /* create dvb_frontend */
- memcpy(&fe->ops.tuner_ops, &cx24113_tuner_ops,
- sizeof(struct dvb_tuner_ops));
- fe->tuner_priv = state;
- return fe;
-
-error:
- kfree(state);
-
- return NULL;
-}
-EXPORT_SYMBOL(cx24113_attach);
-
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
-
-MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
-MODULE_DESCRIPTION("DVB Frontend module for Conexant CX24113/CX24128hardware");
-MODULE_LICENSE("GPL");
-
diff --git a/drivers/media/dvb/frontends/cx24113.h b/drivers/media/dvb/frontends/cx24113.h
deleted file mode 100644
index 01eb7b9c28f..00000000000
--- a/drivers/media/dvb/frontends/cx24113.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Driver for Conexant CX24113/CX24128 Tuner (Satellite)
- *
- * Copyright (C) 2007-8 Patrick Boettcher <pb@linuxtv.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef CX24113_H
-#define CX24113_H
-
-struct dvb_frontend;
-
-struct cx24113_config {
- u8 i2c_addr; /* 0x14 or 0x54 */
-
- u32 xtal_khz;
-};
-
-#if defined(CONFIG_DVB_TUNER_CX24113) || \
- (defined(CONFIG_DVB_TUNER_CX24113_MODULE) && defined(MODULE))
-extern struct dvb_frontend *cx24113_attach(struct dvb_frontend *,
- const struct cx24113_config *config, struct i2c_adapter *i2c);
-
-extern void cx24113_agc_callback(struct dvb_frontend *fe);
-#else
-static inline struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe,
- const struct cx24113_config *config, struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline void cx24113_agc_callback(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-}
-#endif
-
-#endif /* CX24113_H */
diff --git a/drivers/media/dvb/frontends/cx24116.c b/drivers/media/dvb/frontends/cx24116.c
deleted file mode 100644
index b4887918653..00000000000
--- a/drivers/media/dvb/frontends/cx24116.c
+++ /dev/null
@@ -1,1508 +0,0 @@
-/*
- Conexant cx24116/cx24118 - DVBS/S2 Satellite demod/tuner driver
-
- Copyright (C) 2006-2008 Steven Toth <stoth@hauppauge.com>
- Copyright (C) 2006-2007 Georg Acher
- Copyright (C) 2007-2008 Darron Broad
- March 2007
- Fixed some bugs.
- Added diseqc support.
- Added corrected signal strength support.
- August 2007
- Sync with legacy version.
- Some clean ups.
- Copyright (C) 2008 Igor Liplianin
- September, 9th 2008
- Fixed locking on high symbol rates (>30000).
- Implement MPEG initialization parameter.
- January, 17th 2009
- Fill set_voltage with actually control voltage code.
- Correct set tone to not affect voltage.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/firmware.h>
-
-#include "dvb_frontend.h"
-#include "cx24116.h"
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
-
-#define dprintk(args...) \
- do { \
- if (debug) \
- printk(KERN_INFO "cx24116: " args); \
- } while (0)
-
-#define CX24116_DEFAULT_FIRMWARE "dvb-fe-cx24116.fw"
-#define CX24116_SEARCH_RANGE_KHZ 5000
-
-/* known registers */
-#define CX24116_REG_COMMAND (0x00) /* command args 0x00..0x1e */
-#define CX24116_REG_EXECUTE (0x1f) /* execute command */
-#define CX24116_REG_MAILBOX (0x96) /* FW or multipurpose mailbox? */
-#define CX24116_REG_RESET (0x20) /* reset status > 0 */
-#define CX24116_REG_SIGNAL (0x9e) /* signal low */
-#define CX24116_REG_SSTATUS (0x9d) /* signal high / status */
-#define CX24116_REG_QUALITY8 (0xa3)
-#define CX24116_REG_QSTATUS (0xbc)
-#define CX24116_REG_QUALITY0 (0xd5)
-#define CX24116_REG_BER0 (0xc9)
-#define CX24116_REG_BER8 (0xc8)
-#define CX24116_REG_BER16 (0xc7)
-#define CX24116_REG_BER24 (0xc6)
-#define CX24116_REG_UCB0 (0xcb)
-#define CX24116_REG_UCB8 (0xca)
-#define CX24116_REG_CLKDIV (0xf3)
-#define CX24116_REG_RATEDIV (0xf9)
-
-/* configured fec (not tuned) or actual FEC (tuned) 1=1/2 2=2/3 etc */
-#define CX24116_REG_FECSTATUS (0x9c)
-
-/* FECSTATUS bits */
-/* mask to determine configured fec (not tuned) or actual fec (tuned) */
-#define CX24116_FEC_FECMASK (0x1f)
-
-/* Select DVB-S demodulator, else DVB-S2 */
-#define CX24116_FEC_DVBS (0x20)
-#define CX24116_FEC_UNKNOWN (0x40) /* Unknown/unused */
-
-/* Pilot mode requested when tuning else always reset when tuned */
-#define CX24116_FEC_PILOT (0x80)
-
-/* arg buffer size */
-#define CX24116_ARGLEN (0x1e)
-
-/* rolloff */
-#define CX24116_ROLLOFF_020 (0x00)
-#define CX24116_ROLLOFF_025 (0x01)
-#define CX24116_ROLLOFF_035 (0x02)
-
-/* pilot bit */
-#define CX24116_PILOT_OFF (0x00)
-#define CX24116_PILOT_ON (0x40)
-
-/* signal status */
-#define CX24116_HAS_SIGNAL (0x01)
-#define CX24116_HAS_CARRIER (0x02)
-#define CX24116_HAS_VITERBI (0x04)
-#define CX24116_HAS_SYNCLOCK (0x08)
-#define CX24116_HAS_UNKNOWN1 (0x10)
-#define CX24116_HAS_UNKNOWN2 (0x20)
-#define CX24116_STATUS_MASK (0x0f)
-#define CX24116_SIGNAL_MASK (0xc0)
-
-#define CX24116_DISEQC_TONEOFF (0) /* toneburst never sent */
-#define CX24116_DISEQC_TONECACHE (1) /* toneburst cached */
-#define CX24116_DISEQC_MESGCACHE (2) /* message cached */
-
-/* arg offset for DiSEqC */
-#define CX24116_DISEQC_BURST (1)
-#define CX24116_DISEQC_ARG2_2 (2) /* unknown value=2 */
-#define CX24116_DISEQC_ARG3_0 (3) /* unknown value=0 */
-#define CX24116_DISEQC_ARG4_0 (4) /* unknown value=0 */
-#define CX24116_DISEQC_MSGLEN (5)
-#define CX24116_DISEQC_MSGOFS (6)
-
-/* DiSEqC burst */
-#define CX24116_DISEQC_MINI_A (0)
-#define CX24116_DISEQC_MINI_B (1)
-
-/* DiSEqC tone burst */
-static int toneburst = 1;
-module_param(toneburst, int, 0644);
-MODULE_PARM_DESC(toneburst, "DiSEqC toneburst 0=OFF, 1=TONE CACHE, "\
- "2=MESSAGE CACHE (default:1)");
-
-/* SNR measurements */
-static int esno_snr;
-module_param(esno_snr, int, 0644);
-MODULE_PARM_DESC(esno_snr, "SNR return units, 0=PERCENTAGE 0-100, "\
- "1=ESNO(db * 10) (default:0)");
-
-enum cmds {
- CMD_SET_VCO = 0x10,
- CMD_TUNEREQUEST = 0x11,
- CMD_MPEGCONFIG = 0x13,
- CMD_TUNERINIT = 0x14,
- CMD_BANDWIDTH = 0x15,
- CMD_GETAGC = 0x19,
- CMD_LNBCONFIG = 0x20,
- CMD_LNBSEND = 0x21, /* Formerly CMD_SEND_DISEQC */
- CMD_LNBDCLEVEL = 0x22,
- CMD_SET_TONE = 0x23,
- CMD_UPDFWVERS = 0x35,
- CMD_TUNERSLEEP = 0x36,
- CMD_AGCCONTROL = 0x3b, /* Unknown */
-};
-
-/* The Demod/Tuner can't easily provide these, we cache them */
-struct cx24116_tuning {
- u32 frequency;
- u32 symbol_rate;
- fe_spectral_inversion_t inversion;
- fe_code_rate_t fec;
-
- fe_delivery_system_t delsys;
- fe_modulation_t modulation;
- fe_pilot_t pilot;
- fe_rolloff_t rolloff;
-
- /* Demod values */
- u8 fec_val;
- u8 fec_mask;
- u8 inversion_val;
- u8 pilot_val;
- u8 rolloff_val;
-};
-
-/* Basic commands that are sent to the firmware */
-struct cx24116_cmd {
- u8 len;
- u8 args[CX24116_ARGLEN];
-};
-
-struct cx24116_state {
- struct i2c_adapter *i2c;
- const struct cx24116_config *config;
-
- struct dvb_frontend frontend;
-
- struct cx24116_tuning dcur;
- struct cx24116_tuning dnxt;
-
- u8 skip_fw_load;
- u8 burst;
- struct cx24116_cmd dsec_cmd;
-};
-
-static int cx24116_writereg(struct cx24116_state *state, int reg, int data)
-{
- u8 buf[] = { reg, data };
- struct i2c_msg msg = { .addr = state->config->demod_address,
- .flags = 0, .buf = buf, .len = 2 };
- int err;
-
- if (debug > 1)
- printk("cx24116: %s: write reg 0x%02x, value 0x%02x\n",
- __func__, reg, data);
-
- err = i2c_transfer(state->i2c, &msg, 1);
- if (err != 1) {
- printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
- " value == 0x%02x)\n", __func__, err, reg, data);
- return -EREMOTEIO;
- }
-
- return 0;
-}
-
-/* Bulk byte writes to a single I2C address, for 32k firmware load */
-static int cx24116_writeregN(struct cx24116_state *state, int reg,
- const u8 *data, u16 len)
-{
- int ret = -EREMOTEIO;
- struct i2c_msg msg;
- u8 *buf;
-
- buf = kmalloc(len + 1, GFP_KERNEL);
- if (buf == NULL) {
- printk("Unable to kmalloc\n");
- ret = -ENOMEM;
- goto error;
- }
-
- *(buf) = reg;
- memcpy(buf + 1, data, len);
-
- msg.addr = state->config->demod_address;
- msg.flags = 0;
- msg.buf = buf;
- msg.len = len + 1;
-
- if (debug > 1)
- printk(KERN_INFO "cx24116: %s: write regN 0x%02x, len = %d\n",
- __func__, reg, len);
-
- ret = i2c_transfer(state->i2c, &msg, 1);
- if (ret != 1) {
- printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x\n",
- __func__, ret, reg);
- ret = -EREMOTEIO;
- }
-
-error:
- kfree(buf);
-
- return ret;
-}
-
-static int cx24116_readreg(struct cx24116_state *state, u8 reg)
-{
- int ret;
- u8 b0[] = { reg };
- u8 b1[] = { 0 };
- struct i2c_msg msg[] = {
- { .addr = state->config->demod_address, .flags = 0,
- .buf = b0, .len = 1 },
- { .addr = state->config->demod_address, .flags = I2C_M_RD,
- .buf = b1, .len = 1 }
- };
-
- ret = i2c_transfer(state->i2c, msg, 2);
-
- if (ret != 2) {
- printk(KERN_ERR "%s: reg=0x%x (error=%d)\n",
- __func__, reg, ret);
- return ret;
- }
-
- if (debug > 1)
- printk(KERN_INFO "cx24116: read reg 0x%02x, value 0x%02x\n",
- reg, b1[0]);
-
- return b1[0];
-}
-
-static int cx24116_set_inversion(struct cx24116_state *state,
- fe_spectral_inversion_t inversion)
-{
- dprintk("%s(%d)\n", __func__, inversion);
-
- switch (inversion) {
- case INVERSION_OFF:
- state->dnxt.inversion_val = 0x00;
- break;
- case INVERSION_ON:
- state->dnxt.inversion_val = 0x04;
- break;
- case INVERSION_AUTO:
- state->dnxt.inversion_val = 0x0C;
- break;
- default:
- return -EINVAL;
- }
-
- state->dnxt.inversion = inversion;
-
- return 0;
-}
-
-/*
- * modfec (modulation and FEC)
- * ===========================
- *
- * MOD FEC mask/val standard
- * ---- -------- ----------- --------
- * QPSK FEC_1_2 0x02 0x02+X DVB-S
- * QPSK FEC_2_3 0x04 0x02+X DVB-S
- * QPSK FEC_3_4 0x08 0x02+X DVB-S
- * QPSK FEC_4_5 0x10 0x02+X DVB-S (?)
- * QPSK FEC_5_6 0x20 0x02+X DVB-S
- * QPSK FEC_6_7 0x40 0x02+X DVB-S
- * QPSK FEC_7_8 0x80 0x02+X DVB-S
- * QPSK FEC_8_9 0x01 0x02+X DVB-S (?) (NOT SUPPORTED?)
- * QPSK AUTO 0xff 0x02+X DVB-S
- *
- * For DVB-S high byte probably represents FEC
- * and low byte selects the modulator. The high
- * byte is search range mask. Bit 5 may turn
- * on DVB-S and remaining bits represent some
- * kind of calibration (how/what i do not know).
- *
- * Eg.(2/3) szap "Zone Horror"
- *
- * mask/val = 0x04, 0x20
- * status 1f | signal c3c0 | snr a333 | ber 00000098 | unc 0 | FE_HAS_LOCK
- *
- * mask/val = 0x04, 0x30
- * status 1f | signal c3c0 | snr a333 | ber 00000000 | unc 0 | FE_HAS_LOCK
- *
- * After tuning FECSTATUS contains actual FEC
- * in use numbered 1 through to 8 for 1/2 .. 2/3 etc
- *
- * NBC=NOT/NON BACKWARD COMPATIBLE WITH DVB-S (DVB-S2 only)
- *
- * NBC-QPSK FEC_1_2 0x00, 0x04 DVB-S2
- * NBC-QPSK FEC_3_5 0x00, 0x05 DVB-S2
- * NBC-QPSK FEC_2_3 0x00, 0x06 DVB-S2
- * NBC-QPSK FEC_3_4 0x00, 0x07 DVB-S2
- * NBC-QPSK FEC_4_5 0x00, 0x08 DVB-S2
- * NBC-QPSK FEC_5_6 0x00, 0x09 DVB-S2
- * NBC-QPSK FEC_8_9 0x00, 0x0a DVB-S2
- * NBC-QPSK FEC_9_10 0x00, 0x0b DVB-S2
- *
- * NBC-8PSK FEC_3_5 0x00, 0x0c DVB-S2
- * NBC-8PSK FEC_2_3 0x00, 0x0d DVB-S2
- * NBC-8PSK FEC_3_4 0x00, 0x0e DVB-S2
- * NBC-8PSK FEC_5_6 0x00, 0x0f DVB-S2
- * NBC-8PSK FEC_8_9 0x00, 0x10 DVB-S2
- * NBC-8PSK FEC_9_10 0x00, 0x11 DVB-S2
- *
- * For DVB-S2 low bytes selects both modulator
- * and FEC. High byte is meaningless here. To
- * set pilot, bit 6 (0x40) is set. When inspecting
- * FECSTATUS bit 7 (0x80) represents the pilot
- * selection whilst not tuned. When tuned, actual FEC
- * in use is found in FECSTATUS as per above. Pilot
- * value is reset.
- */
-
-/* A table of modulation, fec and configuration bytes for the demod.
- * Not all S2 mmodulation schemes are support and not all rates with
- * a scheme are support. Especially, no auto detect when in S2 mode.
- */
-static struct cx24116_modfec {
- fe_delivery_system_t delivery_system;
- fe_modulation_t modulation;
- fe_code_rate_t fec;
- u8 mask; /* In DVBS mode this is used to autodetect */
- u8 val; /* Passed to the firmware to indicate mode selection */
-} CX24116_MODFEC_MODES[] = {
- /* QPSK. For unknown rates we set hardware to auto detect 0xfe 0x30 */
-
- /*mod fec mask val */
- { SYS_DVBS, QPSK, FEC_NONE, 0xfe, 0x30 },
- { SYS_DVBS, QPSK, FEC_1_2, 0x02, 0x2e }, /* 00000010 00101110 */
- { SYS_DVBS, QPSK, FEC_2_3, 0x04, 0x2f }, /* 00000100 00101111 */
- { SYS_DVBS, QPSK, FEC_3_4, 0x08, 0x30 }, /* 00001000 00110000 */
- { SYS_DVBS, QPSK, FEC_4_5, 0xfe, 0x30 }, /* 000?0000 ? */
- { SYS_DVBS, QPSK, FEC_5_6, 0x20, 0x31 }, /* 00100000 00110001 */
- { SYS_DVBS, QPSK, FEC_6_7, 0xfe, 0x30 }, /* 0?000000 ? */
- { SYS_DVBS, QPSK, FEC_7_8, 0x80, 0x32 }, /* 10000000 00110010 */
- { SYS_DVBS, QPSK, FEC_8_9, 0xfe, 0x30 }, /* 0000000? ? */
- { SYS_DVBS, QPSK, FEC_AUTO, 0xfe, 0x30 },
- /* NBC-QPSK */
- { SYS_DVBS2, QPSK, FEC_1_2, 0x00, 0x04 },
- { SYS_DVBS2, QPSK, FEC_3_5, 0x00, 0x05 },
- { SYS_DVBS2, QPSK, FEC_2_3, 0x00, 0x06 },
- { SYS_DVBS2, QPSK, FEC_3_4, 0x00, 0x07 },
- { SYS_DVBS2, QPSK, FEC_4_5, 0x00, 0x08 },
- { SYS_DVBS2, QPSK, FEC_5_6, 0x00, 0x09 },
- { SYS_DVBS2, QPSK, FEC_8_9, 0x00, 0x0a },
- { SYS_DVBS2, QPSK, FEC_9_10, 0x00, 0x0b },
- /* 8PSK */
- { SYS_DVBS2, PSK_8, FEC_3_5, 0x00, 0x0c },
- { SYS_DVBS2, PSK_8, FEC_2_3, 0x00, 0x0d },
- { SYS_DVBS2, PSK_8, FEC_3_4, 0x00, 0x0e },
- { SYS_DVBS2, PSK_8, FEC_5_6, 0x00, 0x0f },
- { SYS_DVBS2, PSK_8, FEC_8_9, 0x00, 0x10 },
- { SYS_DVBS2, PSK_8, FEC_9_10, 0x00, 0x11 },
- /*
- * `val' can be found in the FECSTATUS register when tuning.
- * FECSTATUS will give the actual FEC in use if tuning was successful.
- */
-};
-
-static int cx24116_lookup_fecmod(struct cx24116_state *state,
- fe_delivery_system_t d, fe_modulation_t m, fe_code_rate_t f)
-{
- int i, ret = -EOPNOTSUPP;
-
- dprintk("%s(0x%02x,0x%02x)\n", __func__, m, f);
-
- for (i = 0; i < ARRAY_SIZE(CX24116_MODFEC_MODES); i++) {
- if ((d == CX24116_MODFEC_MODES[i].delivery_system) &&
- (m == CX24116_MODFEC_MODES[i].modulation) &&
- (f == CX24116_MODFEC_MODES[i].fec)) {
- ret = i;
- break;
- }
- }
-
- return ret;
-}
-
-static int cx24116_set_fec(struct cx24116_state *state,
- fe_delivery_system_t delsys, fe_modulation_t mod, fe_code_rate_t fec)
-{
- int ret = 0;
-
- dprintk("%s(0x%02x,0x%02x)\n", __func__, mod, fec);
-
- ret = cx24116_lookup_fecmod(state, delsys, mod, fec);
-
- if (ret < 0)
- return ret;
-
- state->dnxt.fec = fec;
- state->dnxt.fec_val = CX24116_MODFEC_MODES[ret].val;
- state->dnxt.fec_mask = CX24116_MODFEC_MODES[ret].mask;
- dprintk("%s() mask/val = 0x%02x/0x%02x\n", __func__,
- state->dnxt.fec_mask, state->dnxt.fec_val);
-
- return 0;
-}
-
-static int cx24116_set_symbolrate(struct cx24116_state *state, u32 rate)
-{
- dprintk("%s(%d)\n", __func__, rate);
-
- /* check if symbol rate is within limits */
- if ((rate > state->frontend.ops.info.symbol_rate_max) ||
- (rate < state->frontend.ops.info.symbol_rate_min)) {
- dprintk("%s() unsupported symbol_rate = %d\n", __func__, rate);
- return -EOPNOTSUPP;
- }
-
- state->dnxt.symbol_rate = rate;
- dprintk("%s() symbol_rate = %d\n", __func__, rate);
-
- return 0;
-}
-
-static int cx24116_load_firmware(struct dvb_frontend *fe,
- const struct firmware *fw);
-
-static int cx24116_firmware_ondemand(struct dvb_frontend *fe)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- const struct firmware *fw;
- int ret = 0;
-
- dprintk("%s()\n", __func__);
-
- if (cx24116_readreg(state, 0x20) > 0) {
-
- if (state->skip_fw_load)
- return 0;
-
- /* Load firmware */
- /* request the firmware, this will block until loaded */
- printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n",
- __func__, CX24116_DEFAULT_FIRMWARE);
- ret = request_firmware(&fw, CX24116_DEFAULT_FIRMWARE,
- state->i2c->dev.parent);
- printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n",
- __func__);
- if (ret) {
- printk(KERN_ERR "%s: No firmware uploaded "
- "(timeout or file not found?)\n", __func__);
- return ret;
- }
-
- /* Make sure we don't recurse back through here
- * during loading */
- state->skip_fw_load = 1;
-
- ret = cx24116_load_firmware(fe, fw);
- if (ret)
- printk(KERN_ERR "%s: Writing firmware to device failed\n",
- __func__);
-
- release_firmware(fw);
-
- printk(KERN_INFO "%s: Firmware upload %s\n", __func__,
- ret == 0 ? "complete" : "failed");
-
- /* Ensure firmware is always loaded if required */
- state->skip_fw_load = 0;
- }
-
- return ret;
-}
-
-/* Take a basic firmware command structure, format it
- * and forward it for processing
- */
-static int cx24116_cmd_execute(struct dvb_frontend *fe, struct cx24116_cmd *cmd)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- int i, ret;
-
- dprintk("%s()\n", __func__);
-
- /* Load the firmware if required */
- ret = cx24116_firmware_ondemand(fe);
- if (ret != 0) {
- printk(KERN_ERR "%s(): Unable initialise the firmware\n",
- __func__);
- return ret;
- }
-
- /* Write the command */
- for (i = 0; i < cmd->len ; i++) {
- dprintk("%s: 0x%02x == 0x%02x\n", __func__, i, cmd->args[i]);
- cx24116_writereg(state, i, cmd->args[i]);
- }
-
- /* Start execution and wait for cmd to terminate */
- cx24116_writereg(state, CX24116_REG_EXECUTE, 0x01);
- while (cx24116_readreg(state, CX24116_REG_EXECUTE)) {
- msleep(10);
- if (i++ > 64) {
- /* Avoid looping forever if the firmware does
- not respond */
- printk(KERN_WARNING "%s() Firmware not responding\n",
- __func__);
- return -EREMOTEIO;
- }
- }
- return 0;
-}
-
-static int cx24116_load_firmware(struct dvb_frontend *fe,
- const struct firmware *fw)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- struct cx24116_cmd cmd;
- int i, ret, len, max, remaining;
- unsigned char vers[4];
-
- dprintk("%s\n", __func__);
- dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
- fw->size,
- fw->data[0],
- fw->data[1],
- fw->data[fw->size-2],
- fw->data[fw->size-1]);
-
- /* Toggle 88x SRST pin to reset demod */
- if (state->config->reset_device)
- state->config->reset_device(fe);
-
- /* Begin the firmware load process */
- /* Prepare the demod, load the firmware, cleanup after load */
-
- /* Init PLL */
- cx24116_writereg(state, 0xE5, 0x00);
- cx24116_writereg(state, 0xF1, 0x08);
- cx24116_writereg(state, 0xF2, 0x13);
-
- /* Start PLL */
- cx24116_writereg(state, 0xe0, 0x03);
- cx24116_writereg(state, 0xe0, 0x00);
-
- /* Unknown */
- cx24116_writereg(state, CX24116_REG_CLKDIV, 0x46);
- cx24116_writereg(state, CX24116_REG_RATEDIV, 0x00);
-
- /* Unknown */
- cx24116_writereg(state, 0xF0, 0x03);
- cx24116_writereg(state, 0xF4, 0x81);
- cx24116_writereg(state, 0xF5, 0x00);
- cx24116_writereg(state, 0xF6, 0x00);
-
- /* Split firmware to the max I2C write len and write.
- * Writes whole firmware as one write when i2c_wr_max is set to 0. */
- if (state->config->i2c_wr_max)
- max = state->config->i2c_wr_max;
- else
- max = INT_MAX; /* enough for 32k firmware */
-
- for (remaining = fw->size; remaining > 0; remaining -= max - 1) {
- len = remaining;
- if (len > max - 1)
- len = max - 1;
-
- cx24116_writeregN(state, 0xF7, &fw->data[fw->size - remaining],
- len);
- }
-
- cx24116_writereg(state, 0xF4, 0x10);
- cx24116_writereg(state, 0xF0, 0x00);
- cx24116_writereg(state, 0xF8, 0x06);
-
- /* Firmware CMD 10: VCO config */
- cmd.args[0x00] = CMD_SET_VCO;
- cmd.args[0x01] = 0x05;
- cmd.args[0x02] = 0xdc;
- cmd.args[0x03] = 0xda;
- cmd.args[0x04] = 0xae;
- cmd.args[0x05] = 0xaa;
- cmd.args[0x06] = 0x04;
- cmd.args[0x07] = 0x9d;
- cmd.args[0x08] = 0xfc;
- cmd.args[0x09] = 0x06;
- cmd.len = 0x0a;
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- return ret;
-
- cx24116_writereg(state, CX24116_REG_SSTATUS, 0x00);
-
- /* Firmware CMD 14: Tuner config */
- cmd.args[0x00] = CMD_TUNERINIT;
- cmd.args[0x01] = 0x00;
- cmd.args[0x02] = 0x00;
- cmd.len = 0x03;
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- return ret;
-
- cx24116_writereg(state, 0xe5, 0x00);
-
- /* Firmware CMD 13: MPEG config */
- cmd.args[0x00] = CMD_MPEGCONFIG;
- cmd.args[0x01] = 0x01;
- cmd.args[0x02] = 0x75;
- cmd.args[0x03] = 0x00;
- if (state->config->mpg_clk_pos_pol)
- cmd.args[0x04] = state->config->mpg_clk_pos_pol;
- else
- cmd.args[0x04] = 0x02;
- cmd.args[0x05] = 0x00;
- cmd.len = 0x06;
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- return ret;
-
- /* Firmware CMD 35: Get firmware version */
- cmd.args[0x00] = CMD_UPDFWVERS;
- cmd.len = 0x02;
- for (i = 0; i < 4; i++) {
- cmd.args[0x01] = i;
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- return ret;
- vers[i] = cx24116_readreg(state, CX24116_REG_MAILBOX);
- }
- printk(KERN_INFO "%s: FW version %i.%i.%i.%i\n", __func__,
- vers[0], vers[1], vers[2], vers[3]);
-
- return 0;
-}
-
-static int cx24116_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct cx24116_state *state = fe->demodulator_priv;
-
- int lock = cx24116_readreg(state, CX24116_REG_SSTATUS) &
- CX24116_STATUS_MASK;
-
- dprintk("%s: status = 0x%02x\n", __func__, lock);
-
- *status = 0;
-
- if (lock & CX24116_HAS_SIGNAL)
- *status |= FE_HAS_SIGNAL;
- if (lock & CX24116_HAS_CARRIER)
- *status |= FE_HAS_CARRIER;
- if (lock & CX24116_HAS_VITERBI)
- *status |= FE_HAS_VITERBI;
- if (lock & CX24116_HAS_SYNCLOCK)
- *status |= FE_HAS_SYNC | FE_HAS_LOCK;
-
- return 0;
-}
-
-static int cx24116_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct cx24116_state *state = fe->demodulator_priv;
-
- dprintk("%s()\n", __func__);
-
- *ber = (cx24116_readreg(state, CX24116_REG_BER24) << 24) |
- (cx24116_readreg(state, CX24116_REG_BER16) << 16) |
- (cx24116_readreg(state, CX24116_REG_BER8) << 8) |
- cx24116_readreg(state, CX24116_REG_BER0);
-
- return 0;
-}
-
-/* TODO Determine function and scale appropriately */
-static int cx24116_read_signal_strength(struct dvb_frontend *fe,
- u16 *signal_strength)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- struct cx24116_cmd cmd;
- int ret;
- u16 sig_reading;
-
- dprintk("%s()\n", __func__);
-
- /* Firmware CMD 19: Get AGC */
- cmd.args[0x00] = CMD_GETAGC;
- cmd.len = 0x01;
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- return ret;
-
- sig_reading =
- (cx24116_readreg(state,
- CX24116_REG_SSTATUS) & CX24116_SIGNAL_MASK) |
- (cx24116_readreg(state, CX24116_REG_SIGNAL) << 6);
- *signal_strength = 0 - sig_reading;
-
- dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n",
- __func__, sig_reading, *signal_strength);
-
- return 0;
-}
-
-/* SNR (0..100)% = (sig & 0xf0) * 10 + (sig & 0x0f) * 10 / 16 */
-static int cx24116_read_snr_pct(struct dvb_frontend *fe, u16 *snr)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- u8 snr_reading;
- static const u32 snr_tab[] = { /* 10 x Table (rounded up) */
- 0x00000, 0x0199A, 0x03333, 0x04ccD, 0x06667,
- 0x08000, 0x0999A, 0x0b333, 0x0cccD, 0x0e667,
- 0x10000, 0x1199A, 0x13333, 0x14ccD, 0x16667,
- 0x18000 };
-
- dprintk("%s()\n", __func__);
-
- snr_reading = cx24116_readreg(state, CX24116_REG_QUALITY0);
-
- if (snr_reading >= 0xa0 /* 100% */)
- *snr = 0xffff;
- else
- *snr = snr_tab[(snr_reading & 0xf0) >> 4] +
- (snr_tab[(snr_reading & 0x0f)] >> 4);
-
- dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
- snr_reading, *snr);
-
- return 0;
-}
-
-/* The reelbox patches show the value in the registers represents
- * ESNO, from 0->30db (values 0->300). We provide this value by
- * default.
- */
-static int cx24116_read_snr_esno(struct dvb_frontend *fe, u16 *snr)
-{
- struct cx24116_state *state = fe->demodulator_priv;
-
- dprintk("%s()\n", __func__);
-
- *snr = cx24116_readreg(state, CX24116_REG_QUALITY8) << 8 |
- cx24116_readreg(state, CX24116_REG_QUALITY0);
-
- dprintk("%s: raw 0x%04x\n", __func__, *snr);
-
- return 0;
-}
-
-static int cx24116_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- if (esno_snr == 1)
- return cx24116_read_snr_esno(fe, snr);
- else
- return cx24116_read_snr_pct(fe, snr);
-}
-
-static int cx24116_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- struct cx24116_state *state = fe->demodulator_priv;
-
- dprintk("%s()\n", __func__);
-
- *ucblocks = (cx24116_readreg(state, CX24116_REG_UCB8) << 8) |
- cx24116_readreg(state, CX24116_REG_UCB0);
-
- return 0;
-}
-
-/* Overwrite the current tuning params, we are about to tune */
-static void cx24116_clone_params(struct dvb_frontend *fe)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- memcpy(&state->dcur, &state->dnxt, sizeof(state->dcur));
-}
-
-/* Wait for LNB */
-static int cx24116_wait_for_lnb(struct dvb_frontend *fe)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- int i;
-
- dprintk("%s() qstatus = 0x%02x\n", __func__,
- cx24116_readreg(state, CX24116_REG_QSTATUS));
-
- /* Wait for up to 300 ms */
- for (i = 0; i < 30 ; i++) {
- if (cx24116_readreg(state, CX24116_REG_QSTATUS) & 0x20)
- return 0;
- msleep(10);
- }
-
- dprintk("%s(): LNB not ready\n", __func__);
-
- return -ETIMEDOUT; /* -EBUSY ? */
-}
-
-static int cx24116_set_voltage(struct dvb_frontend *fe,
- fe_sec_voltage_t voltage)
-{
- struct cx24116_cmd cmd;
- int ret;
-
- dprintk("%s: %s\n", __func__,
- voltage == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
- voltage == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" : "??");
-
- /* Wait for LNB ready */
- ret = cx24116_wait_for_lnb(fe);
- if (ret != 0)
- return ret;
-
- /* Wait for voltage/min repeat delay */
- msleep(100);
-
- cmd.args[0x00] = CMD_LNBDCLEVEL;
- cmd.args[0x01] = (voltage == SEC_VOLTAGE_18 ? 0x01 : 0x00);
- cmd.len = 0x02;
-
- /* Min delay time before DiSEqC send */
- msleep(15);
-
- return cx24116_cmd_execute(fe, &cmd);
-}
-
-static int cx24116_set_tone(struct dvb_frontend *fe,
- fe_sec_tone_mode_t tone)
-{
- struct cx24116_cmd cmd;
- int ret;
-
- dprintk("%s(%d)\n", __func__, tone);
- if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
- printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
- return -EINVAL;
- }
-
- /* Wait for LNB ready */
- ret = cx24116_wait_for_lnb(fe);
- if (ret != 0)
- return ret;
-
- /* Min delay time after DiSEqC send */
- msleep(15); /* XXX determine is FW does this, see send_diseqc/burst */
-
- /* Now we set the tone */
- cmd.args[0x00] = CMD_SET_TONE;
- cmd.args[0x01] = 0x00;
- cmd.args[0x02] = 0x00;
-
- switch (tone) {
- case SEC_TONE_ON:
- dprintk("%s: setting tone on\n", __func__);
- cmd.args[0x03] = 0x01;
- break;
- case SEC_TONE_OFF:
- dprintk("%s: setting tone off\n", __func__);
- cmd.args[0x03] = 0x00;
- break;
- }
- cmd.len = 0x04;
-
- /* Min delay time before DiSEqC send */
- msleep(15); /* XXX determine is FW does this, see send_diseqc/burst */
-
- return cx24116_cmd_execute(fe, &cmd);
-}
-
-/* Initialise DiSEqC */
-static int cx24116_diseqc_init(struct dvb_frontend *fe)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- struct cx24116_cmd cmd;
- int ret;
-
- /* Firmware CMD 20: LNB/DiSEqC config */
- cmd.args[0x00] = CMD_LNBCONFIG;
- cmd.args[0x01] = 0x00;
- cmd.args[0x02] = 0x10;
- cmd.args[0x03] = 0x00;
- cmd.args[0x04] = 0x8f;
- cmd.args[0x05] = 0x28;
- cmd.args[0x06] = (toneburst == CX24116_DISEQC_TONEOFF) ? 0x00 : 0x01;
- cmd.args[0x07] = 0x01;
- cmd.len = 0x08;
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- return ret;
-
- /* Prepare a DiSEqC command */
- state->dsec_cmd.args[0x00] = CMD_LNBSEND;
-
- /* DiSEqC burst */
- state->dsec_cmd.args[CX24116_DISEQC_BURST] = CX24116_DISEQC_MINI_A;
-
- /* Unknown */
- state->dsec_cmd.args[CX24116_DISEQC_ARG2_2] = 0x02;
- state->dsec_cmd.args[CX24116_DISEQC_ARG3_0] = 0x00;
- /* Continuation flag? */
- state->dsec_cmd.args[CX24116_DISEQC_ARG4_0] = 0x00;
-
- /* DiSEqC message length */
- state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] = 0x00;
-
- /* Command length */
- state->dsec_cmd.len = CX24116_DISEQC_MSGOFS;
-
- return 0;
-}
-
-/* Send DiSEqC message with derived burst (hack) || previous burst */
-static int cx24116_send_diseqc_msg(struct dvb_frontend *fe,
- struct dvb_diseqc_master_cmd *d)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- int i, ret;
-
- /* Dump DiSEqC message */
- if (debug) {
- printk(KERN_INFO "cx24116: %s(", __func__);
- for (i = 0 ; i < d->msg_len ;) {
- printk(KERN_INFO "0x%02x", d->msg[i]);
- if (++i < d->msg_len)
- printk(KERN_INFO ", ");
- }
- printk(") toneburst=%d\n", toneburst);
- }
-
- /* Validate length */
- if (d->msg_len > (CX24116_ARGLEN - CX24116_DISEQC_MSGOFS))
- return -EINVAL;
-
- /* DiSEqC message */
- for (i = 0; i < d->msg_len; i++)
- state->dsec_cmd.args[CX24116_DISEQC_MSGOFS + i] = d->msg[i];
-
- /* DiSEqC message length */
- state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] = d->msg_len;
-
- /* Command length */
- state->dsec_cmd.len = CX24116_DISEQC_MSGOFS +
- state->dsec_cmd.args[CX24116_DISEQC_MSGLEN];
-
- /* DiSEqC toneburst */
- if (toneburst == CX24116_DISEQC_MESGCACHE)
- /* Message is cached */
- return 0;
-
- else if (toneburst == CX24116_DISEQC_TONEOFF)
- /* Message is sent without burst */
- state->dsec_cmd.args[CX24116_DISEQC_BURST] = 0;
-
- else if (toneburst == CX24116_DISEQC_TONECACHE) {
- /*
- * Message is sent with derived else cached burst
- *
- * WRITE PORT GROUP COMMAND 38
- *
- * 0/A/A: E0 10 38 F0..F3
- * 1/B/B: E0 10 38 F4..F7
- * 2/C/A: E0 10 38 F8..FB
- * 3/D/B: E0 10 38 FC..FF
- *
- * databyte[3]= 8421:8421
- * ABCD:WXYZ
- * CLR :SET
- *
- * WX= PORT SELECT 0..3 (X=TONEBURST)
- * Y = VOLTAGE (0=13V, 1=18V)
- * Z = BAND (0=LOW, 1=HIGH(22K))
- */
- if (d->msg_len >= 4 && d->msg[2] == 0x38)
- state->dsec_cmd.args[CX24116_DISEQC_BURST] =
- ((d->msg[3] & 4) >> 2);
- if (debug)
- dprintk("%s burst=%d\n", __func__,
- state->dsec_cmd.args[CX24116_DISEQC_BURST]);
- }
-
- /* Wait for LNB ready */
- ret = cx24116_wait_for_lnb(fe);
- if (ret != 0)
- return ret;
-
- /* Wait for voltage/min repeat delay */
- msleep(100);
-
- /* Command */
- ret = cx24116_cmd_execute(fe, &state->dsec_cmd);
- if (ret != 0)
- return ret;
- /*
- * Wait for send
- *
- * Eutelsat spec:
- * >15ms delay + (XXX determine if FW does this, see set_tone)
- * 13.5ms per byte +
- * >15ms delay +
- * 12.5ms burst +
- * >15ms delay (XXX determine if FW does this, see set_tone)
- */
- msleep((state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] << 4) +
- ((toneburst == CX24116_DISEQC_TONEOFF) ? 30 : 60));
-
- return 0;
-}
-
-/* Send DiSEqC burst */
-static int cx24116_diseqc_send_burst(struct dvb_frontend *fe,
- fe_sec_mini_cmd_t burst)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- int ret;
-
- dprintk("%s(%d) toneburst=%d\n", __func__, burst, toneburst);
-
- /* DiSEqC burst */
- if (burst == SEC_MINI_A)
- state->dsec_cmd.args[CX24116_DISEQC_BURST] =
- CX24116_DISEQC_MINI_A;
- else if (burst == SEC_MINI_B)
- state->dsec_cmd.args[CX24116_DISEQC_BURST] =
- CX24116_DISEQC_MINI_B;
- else
- return -EINVAL;
-
- /* DiSEqC toneburst */
- if (toneburst != CX24116_DISEQC_MESGCACHE)
- /* Burst is cached */
- return 0;
-
- /* Burst is to be sent with cached message */
-
- /* Wait for LNB ready */
- ret = cx24116_wait_for_lnb(fe);
- if (ret != 0)
- return ret;
-
- /* Wait for voltage/min repeat delay */
- msleep(100);
-
- /* Command */
- ret = cx24116_cmd_execute(fe, &state->dsec_cmd);
- if (ret != 0)
- return ret;
-
- /*
- * Wait for send
- *
- * Eutelsat spec:
- * >15ms delay + (XXX determine if FW does this, see set_tone)
- * 13.5ms per byte +
- * >15ms delay +
- * 12.5ms burst +
- * >15ms delay (XXX determine if FW does this, see set_tone)
- */
- msleep((state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] << 4) + 60);
-
- return 0;
-}
-
-static void cx24116_release(struct dvb_frontend *fe)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- dprintk("%s\n", __func__);
- kfree(state);
-}
-
-static struct dvb_frontend_ops cx24116_ops;
-
-struct dvb_frontend *cx24116_attach(const struct cx24116_config *config,
- struct i2c_adapter *i2c)
-{
- struct cx24116_state *state = NULL;
- int ret;
-
- dprintk("%s\n", __func__);
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct cx24116_state), GFP_KERNEL);
- if (state == NULL)
- goto error1;
-
- state->config = config;
- state->i2c = i2c;
-
- /* check if the demod is present */
- ret = (cx24116_readreg(state, 0xFF) << 8) |
- cx24116_readreg(state, 0xFE);
- if (ret != 0x0501) {
- printk(KERN_INFO "Invalid probe, probably not a CX24116 device\n");
- goto error2;
- }
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &cx24116_ops,
- sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
- return &state->frontend;
-
-error2: kfree(state);
-error1: return NULL;
-}
-EXPORT_SYMBOL(cx24116_attach);
-
-/*
- * Initialise or wake up device
- *
- * Power config will reset and load initial firmware if required
- */
-static int cx24116_initfe(struct dvb_frontend *fe)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- struct cx24116_cmd cmd;
- int ret;
-
- dprintk("%s()\n", __func__);
-
- /* Power on */
- cx24116_writereg(state, 0xe0, 0);
- cx24116_writereg(state, 0xe1, 0);
- cx24116_writereg(state, 0xea, 0);
-
- /* Firmware CMD 36: Power config */
- cmd.args[0x00] = CMD_TUNERSLEEP;
- cmd.args[0x01] = 0;
- cmd.len = 0x02;
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- return ret;
-
- ret = cx24116_diseqc_init(fe);
- if (ret != 0)
- return ret;
-
- /* HVR-4000 needs this */
- return cx24116_set_voltage(fe, SEC_VOLTAGE_13);
-}
-
-/*
- * Put device to sleep
- */
-static int cx24116_sleep(struct dvb_frontend *fe)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- struct cx24116_cmd cmd;
- int ret;
-
- dprintk("%s()\n", __func__);
-
- /* Firmware CMD 36: Power config */
- cmd.args[0x00] = CMD_TUNERSLEEP;
- cmd.args[0x01] = 1;
- cmd.len = 0x02;
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- return ret;
-
- /* Power off (Shutdown clocks) */
- cx24116_writereg(state, 0xea, 0xff);
- cx24116_writereg(state, 0xe1, 1);
- cx24116_writereg(state, 0xe0, 1);
-
- return 0;
-}
-
-/* dvb-core told us to tune, the tv property cache will be complete,
- * it's safe for is to pull values and use them for tuning purposes.
- */
-static int cx24116_set_frontend(struct dvb_frontend *fe)
-{
- struct cx24116_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct cx24116_cmd cmd;
- fe_status_t tunerstat;
- int i, status, ret, retune = 1;
-
- dprintk("%s()\n", __func__);
-
- switch (c->delivery_system) {
- case SYS_DVBS:
- dprintk("%s: DVB-S delivery system selected\n", __func__);
-
- /* Only QPSK is supported for DVB-S */
- if (c->modulation != QPSK) {
- dprintk("%s: unsupported modulation selected (%d)\n",
- __func__, c->modulation);
- return -EOPNOTSUPP;
- }
-
- /* Pilot doesn't exist in DVB-S, turn bit off */
- state->dnxt.pilot_val = CX24116_PILOT_OFF;
-
- /* DVB-S only supports 0.35 */
- if (c->rolloff != ROLLOFF_35) {
- dprintk("%s: unsupported rolloff selected (%d)\n",
- __func__, c->rolloff);
- return -EOPNOTSUPP;
- }
- state->dnxt.rolloff_val = CX24116_ROLLOFF_035;
- break;
-
- case SYS_DVBS2:
- dprintk("%s: DVB-S2 delivery system selected\n", __func__);
-
- /*
- * NBC 8PSK/QPSK with DVB-S is supported for DVB-S2,
- * but not hardware auto detection
- */
- if (c->modulation != PSK_8 && c->modulation != QPSK) {
- dprintk("%s: unsupported modulation selected (%d)\n",
- __func__, c->modulation);
- return -EOPNOTSUPP;
- }
-
- switch (c->pilot) {
- case PILOT_AUTO: /* Not supported but emulated */
- state->dnxt.pilot_val = (c->modulation == QPSK)
- ? CX24116_PILOT_OFF : CX24116_PILOT_ON;
- retune++;
- break;
- case PILOT_OFF:
- state->dnxt.pilot_val = CX24116_PILOT_OFF;
- break;
- case PILOT_ON:
- state->dnxt.pilot_val = CX24116_PILOT_ON;
- break;
- default:
- dprintk("%s: unsupported pilot mode selected (%d)\n",
- __func__, c->pilot);
- return -EOPNOTSUPP;
- }
-
- switch (c->rolloff) {
- case ROLLOFF_20:
- state->dnxt.rolloff_val = CX24116_ROLLOFF_020;
- break;
- case ROLLOFF_25:
- state->dnxt.rolloff_val = CX24116_ROLLOFF_025;
- break;
- case ROLLOFF_35:
- state->dnxt.rolloff_val = CX24116_ROLLOFF_035;
- break;
- case ROLLOFF_AUTO: /* Rolloff must be explicit */
- default:
- dprintk("%s: unsupported rolloff selected (%d)\n",
- __func__, c->rolloff);
- return -EOPNOTSUPP;
- }
- break;
-
- default:
- dprintk("%s: unsupported delivery system selected (%d)\n",
- __func__, c->delivery_system);
- return -EOPNOTSUPP;
- }
- state->dnxt.delsys = c->delivery_system;
- state->dnxt.modulation = c->modulation;
- state->dnxt.frequency = c->frequency;
- state->dnxt.pilot = c->pilot;
- state->dnxt.rolloff = c->rolloff;
-
- ret = cx24116_set_inversion(state, c->inversion);
- if (ret != 0)
- return ret;
-
- /* FEC_NONE/AUTO for DVB-S2 is not supported and detected here */
- ret = cx24116_set_fec(state, c->delivery_system, c->modulation, c->fec_inner);
- if (ret != 0)
- return ret;
-
- ret = cx24116_set_symbolrate(state, c->symbol_rate);
- if (ret != 0)
- return ret;
-
- /* discard the 'current' tuning parameters and prepare to tune */
- cx24116_clone_params(fe);
-
- dprintk("%s: delsys = %d\n", __func__, state->dcur.delsys);
- dprintk("%s: modulation = %d\n", __func__, state->dcur.modulation);
- dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency);
- dprintk("%s: pilot = %d (val = 0x%02x)\n", __func__,
- state->dcur.pilot, state->dcur.pilot_val);
- dprintk("%s: retune = %d\n", __func__, retune);
- dprintk("%s: rolloff = %d (val = 0x%02x)\n", __func__,
- state->dcur.rolloff, state->dcur.rolloff_val);
- dprintk("%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
- dprintk("%s: FEC = %d (mask/val = 0x%02x/0x%02x)\n", __func__,
- state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val);
- dprintk("%s: Inversion = %d (val = 0x%02x)\n", __func__,
- state->dcur.inversion, state->dcur.inversion_val);
-
- /* This is also done in advise/acquire on HVR4000 but not on LITE */
- if (state->config->set_ts_params)
- state->config->set_ts_params(fe, 0);
-
- /* Set/Reset B/W */
- cmd.args[0x00] = CMD_BANDWIDTH;
- cmd.args[0x01] = 0x01;
- cmd.len = 0x02;
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- return ret;
-
- /* Prepare a tune request */
- cmd.args[0x00] = CMD_TUNEREQUEST;
-
- /* Frequency */
- cmd.args[0x01] = (state->dcur.frequency & 0xff0000) >> 16;
- cmd.args[0x02] = (state->dcur.frequency & 0x00ff00) >> 8;
- cmd.args[0x03] = (state->dcur.frequency & 0x0000ff);
-
- /* Symbol Rate */
- cmd.args[0x04] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8;
- cmd.args[0x05] = ((state->dcur.symbol_rate / 1000) & 0x00ff);
-
- /* Automatic Inversion */
- cmd.args[0x06] = state->dcur.inversion_val;
-
- /* Modulation / FEC / Pilot */
- cmd.args[0x07] = state->dcur.fec_val | state->dcur.pilot_val;
-
- cmd.args[0x08] = CX24116_SEARCH_RANGE_KHZ >> 8;
- cmd.args[0x09] = CX24116_SEARCH_RANGE_KHZ & 0xff;
- cmd.args[0x0a] = 0x00;
- cmd.args[0x0b] = 0x00;
- cmd.args[0x0c] = state->dcur.rolloff_val;
- cmd.args[0x0d] = state->dcur.fec_mask;
-
- if (state->dcur.symbol_rate > 30000000) {
- cmd.args[0x0e] = 0x04;
- cmd.args[0x0f] = 0x00;
- cmd.args[0x10] = 0x01;
- cmd.args[0x11] = 0x77;
- cmd.args[0x12] = 0x36;
- cx24116_writereg(state, CX24116_REG_CLKDIV, 0x44);
- cx24116_writereg(state, CX24116_REG_RATEDIV, 0x01);
- } else {
- cmd.args[0x0e] = 0x06;
- cmd.args[0x0f] = 0x00;
- cmd.args[0x10] = 0x00;
- cmd.args[0x11] = 0xFA;
- cmd.args[0x12] = 0x24;
- cx24116_writereg(state, CX24116_REG_CLKDIV, 0x46);
- cx24116_writereg(state, CX24116_REG_RATEDIV, 0x00);
- }
-
- cmd.len = 0x13;
-
- /* We need to support pilot and non-pilot tuning in the
- * driver automatically. This is a workaround for because
- * the demod does not support autodetect.
- */
- do {
- /* Reset status register */
- status = cx24116_readreg(state, CX24116_REG_SSTATUS)
- & CX24116_SIGNAL_MASK;
- cx24116_writereg(state, CX24116_REG_SSTATUS, status);
-
- /* Tune */
- ret = cx24116_cmd_execute(fe, &cmd);
- if (ret != 0)
- break;
-
- /*
- * Wait for up to 500 ms before retrying
- *
- * If we are able to tune then generally it occurs within 100ms.
- * If it takes longer, try a different toneburst setting.
- */
- for (i = 0; i < 50 ; i++) {
- cx24116_read_status(fe, &tunerstat);
- status = tunerstat & (FE_HAS_SIGNAL | FE_HAS_SYNC);
- if (status == (FE_HAS_SIGNAL | FE_HAS_SYNC)) {
- dprintk("%s: Tuned\n", __func__);
- goto tuned;
- }
- msleep(10);
- }
-
- dprintk("%s: Not tuned\n", __func__);
-
- /* Toggle pilot bit when in auto-pilot */
- if (state->dcur.pilot == PILOT_AUTO)
- cmd.args[0x07] ^= CX24116_PILOT_ON;
- } while (--retune);
-
-tuned: /* Set/Reset B/W */
- cmd.args[0x00] = CMD_BANDWIDTH;
- cmd.args[0x01] = 0x00;
- cmd.len = 0x02;
- return cx24116_cmd_execute(fe, &cmd);
-}
-
-static int cx24116_tune(struct dvb_frontend *fe, bool re_tune,
- unsigned int mode_flags, unsigned int *delay, fe_status_t *status)
-{
- /*
- * It is safe to discard "params" here, as the DVB core will sync
- * fe->dtv_property_cache with fepriv->parameters_in, where the
- * DVBv3 params are stored. The only practical usage for it indicate
- * that re-tuning is needed, e. g. (fepriv->state & FESTATE_RETUNE) is
- * true.
- */
-
- *delay = HZ / 5;
- if (re_tune) {
- int ret = cx24116_set_frontend(fe);
- if (ret)
- return ret;
- }
- return cx24116_read_status(fe, status);
-}
-
-static int cx24116_get_algo(struct dvb_frontend *fe)
-{
- return DVBFE_ALGO_HW;
-}
-
-static struct dvb_frontend_ops cx24116_ops = {
- .delsys = { SYS_DVBS, SYS_DVBS2 },
- .info = {
- .name = "Conexant CX24116/CX24118",
- .frequency_min = 950000,
- .frequency_max = 2150000,
- .frequency_stepsize = 1011, /* kHz for QPSK frontends */
- .frequency_tolerance = 5000,
- .symbol_rate_min = 1000000,
- .symbol_rate_max = 45000000,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
- FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_2G_MODULATION |
- FE_CAN_QPSK | FE_CAN_RECOVER
- },
-
- .release = cx24116_release,
-
- .init = cx24116_initfe,
- .sleep = cx24116_sleep,
- .read_status = cx24116_read_status,
- .read_ber = cx24116_read_ber,
- .read_signal_strength = cx24116_read_signal_strength,
- .read_snr = cx24116_read_snr,
- .read_ucblocks = cx24116_read_ucblocks,
- .set_tone = cx24116_set_tone,
- .set_voltage = cx24116_set_voltage,
- .diseqc_send_master_cmd = cx24116_send_diseqc_msg,
- .diseqc_send_burst = cx24116_diseqc_send_burst,
- .get_frontend_algo = cx24116_get_algo,
- .tune = cx24116_tune,
-
- .set_frontend = cx24116_set_frontend,
-};
-
-MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24116/cx24118 hardware");
-MODULE_AUTHOR("Steven Toth");
-MODULE_LICENSE("GPL");
-
diff --git a/drivers/media/dvb/frontends/cx24116.h b/drivers/media/dvb/frontends/cx24116.h
deleted file mode 100644
index 7d90ab949c0..00000000000
--- a/drivers/media/dvb/frontends/cx24116.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- Conexant cx24116/cx24118 - DVBS/S2 Satellite demod/tuner driver
-
- Copyright (C) 2006 Steven Toth <stoth@linuxtv.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-#ifndef CX24116_H
-#define CX24116_H
-
-#include <linux/dvb/frontend.h>
-
-struct cx24116_config {
- /* the demodulator's i2c address */
- u8 demod_address;
-
- /* Need to set device param for start_dma */
- int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
-
- /* Need to reset device during firmware loading */
- int (*reset_device)(struct dvb_frontend *fe);
-
- /* Need to set MPEG parameters */
- u8 mpg_clk_pos_pol:0x02;
-
- /* max bytes I2C provider can write at once */
- u16 i2c_wr_max;
-};
-
-#if defined(CONFIG_DVB_CX24116) || \
- (defined(CONFIG_DVB_CX24116_MODULE) && defined(MODULE))
-extern struct dvb_frontend *cx24116_attach(
- const struct cx24116_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline struct dvb_frontend *cx24116_attach(
- const struct cx24116_config *config,
- struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif /* CX24116_H */
diff --git a/drivers/media/dvb/frontends/cx24123.c b/drivers/media/dvb/frontends/cx24123.c
deleted file mode 100644
index 7e28b4ee7d4..00000000000
--- a/drivers/media/dvb/frontends/cx24123.c
+++ /dev/null
@@ -1,1165 +0,0 @@
-/*
- * Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
- *
- * Copyright (C) 2005 Steven Toth <stoth@linuxtv.org>
- *
- * Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
- *
- * Support for CX24123/CX24113-NIM by Patrick Boettcher <pb@linuxtv.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include "dvb_frontend.h"
-#include "cx24123.h"
-
-#define XTAL 10111000
-
-static int force_band;
-module_param(force_band, int, 0644);
-MODULE_PARM_DESC(force_band, "Force a specific band select "\
- "(1-9, default:off).");
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
-
-#define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0)
-#define err(args...) do { printk(KERN_ERR "CX24123: " args); } while (0)
-
-#define dprintk(args...) \
- do { \
- if (debug) { \
- printk(KERN_DEBUG "CX24123: %s: ", __func__); \
- printk(args); \
- } \
- } while (0)
-
-struct cx24123_state {
- struct i2c_adapter *i2c;
- const struct cx24123_config *config;
-
- struct dvb_frontend frontend;
-
- /* Some PLL specifics for tuning */
- u32 VCAarg;
- u32 VGAarg;
- u32 bandselectarg;
- u32 pllarg;
- u32 FILTune;
-
- struct i2c_adapter tuner_i2c_adapter;
-
- u8 demod_rev;
-
- /* The Demod/Tuner can't easily provide these, we cache them */
- u32 currentfreq;
- u32 currentsymbolrate;
-};
-
-/* Various tuner defaults need to be established for a given symbol rate Sps */
-static struct cx24123_AGC_val {
- u32 symbolrate_low;
- u32 symbolrate_high;
- u32 VCAprogdata;
- u32 VGAprogdata;
- u32 FILTune;
-} cx24123_AGC_vals[] =
-{
- {
- .symbolrate_low = 1000000,
- .symbolrate_high = 4999999,
- /* the specs recommend other values for VGA offsets,
- but tests show they are wrong */
- .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
- .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07,
- .FILTune = 0x27f /* 0.41 V */
- },
- {
- .symbolrate_low = 5000000,
- .symbolrate_high = 14999999,
- .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
- .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f,
- .FILTune = 0x317 /* 0.90 V */
- },
- {
- .symbolrate_low = 15000000,
- .symbolrate_high = 45000000,
- .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180,
- .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f,
- .FILTune = 0x145 /* 2.70 V */
- },
-};
-
-/*
- * Various tuner defaults need to be established for a given frequency kHz.
- * fixme: The bounds on the bands do not match the doc in real life.
- * fixme: Some of them have been moved, other might need adjustment.
- */
-static struct cx24123_bandselect_val {
- u32 freq_low;
- u32 freq_high;
- u32 VCOdivider;
- u32 progdata;
-} cx24123_bandselect_vals[] =
-{
- /* band 1 */
- {
- .freq_low = 950000,
- .freq_high = 1074999,
- .VCOdivider = 4,
- .progdata = (0 << 19) | (0 << 9) | 0x40,
- },
-
- /* band 2 */
- {
- .freq_low = 1075000,
- .freq_high = 1177999,
- .VCOdivider = 4,
- .progdata = (0 << 19) | (0 << 9) | 0x80,
- },
-
- /* band 3 */
- {
- .freq_low = 1178000,
- .freq_high = 1295999,
- .VCOdivider = 2,
- .progdata = (0 << 19) | (1 << 9) | 0x01,
- },
-
- /* band 4 */
- {
- .freq_low = 1296000,
- .freq_high = 1431999,
- .VCOdivider = 2,
- .progdata = (0 << 19) | (1 << 9) | 0x02,
- },
-
- /* band 5 */
- {
- .freq_low = 1432000,
- .freq_high = 1575999,
- .VCOdivider = 2,
- .progdata = (0 << 19) | (1 << 9) | 0x04,
- },
-
- /* band 6 */
- {
- .freq_low = 1576000,
- .freq_high = 1717999,
- .VCOdivider = 2,
- .progdata = (0 << 19) | (1 << 9) | 0x08,
- },
-
- /* band 7 */
- {
- .freq_low = 1718000,
- .freq_high = 1855999,
- .VCOdivider = 2,
- .progdata = (0 << 19) | (1 << 9) | 0x10,
- },
-
- /* band 8 */
- {
- .freq_low = 1856000,
- .freq_high = 2035999,
- .VCOdivider = 2,
- .progdata = (0 << 19) | (1 << 9) | 0x20,
- },
-
- /* band 9 */
- {
- .freq_low = 2036000,
- .freq_high = 2150000,
- .VCOdivider = 2,
- .progdata = (0 << 19) | (1 << 9) | 0x40,
- },
-};
-
-static struct {
- u8 reg;
- u8 data;
-} cx24123_regdata[] =
-{
- {0x00, 0x03}, /* Reset system */
- {0x00, 0x00}, /* Clear reset */
- {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
- {0x04, 0x10}, /* MPEG */
- {0x05, 0x04}, /* MPEG */
- {0x06, 0x31}, /* MPEG (default) */
- {0x0b, 0x00}, /* Freq search start point (default) */
- {0x0c, 0x00}, /* Demodulator sample gain (default) */
- {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */
- {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
- {0x0f, 0xfe}, /* FEC search mask (all supported codes) */
- {0x10, 0x01}, /* Default search inversion, no repeat (default) */
- {0x16, 0x00}, /* Enable reading of frequency */
- {0x17, 0x01}, /* Enable EsNO Ready Counter */
- {0x1c, 0x80}, /* Enable error counter */
- {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
- {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
- {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
- {0x29, 0x00}, /* DiSEqC LNB_DC off */
- {0x2a, 0xb0}, /* DiSEqC Parameters (default) */
- {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
- {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
- {0x2d, 0x00},
- {0x2e, 0x00},
- {0x2f, 0x00},
- {0x30, 0x00},
- {0x31, 0x00},
- {0x32, 0x8c}, /* DiSEqC Parameters (default) */
- {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
- {0x34, 0x00},
- {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
- {0x36, 0x02}, /* DiSEqC Parameters (default) */
- {0x37, 0x3a}, /* DiSEqC Parameters (default) */
- {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
- {0x44, 0x00}, /* Constellation (default) */
- {0x45, 0x00}, /* Symbol count (default) */
- {0x46, 0x0d}, /* Symbol rate estimator on (default) */
- {0x56, 0xc1}, /* Error Counter = Viterbi BER */
- {0x57, 0xff}, /* Error Counter Window (default) */
- {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */
- {0x67, 0x83}, /* Non-DCII symbol clock */
-};
-
-static int cx24123_i2c_writereg(struct cx24123_state *state,
- u8 i2c_addr, int reg, int data)
-{
- u8 buf[] = { reg, data };
- struct i2c_msg msg = {
- .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
- };
- int err;
-
- /* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */
-
- err = i2c_transfer(state->i2c, &msg, 1);
- if (err != 1) {
- printk("%s: writereg error(err == %i, reg == 0x%02x,"
- " data == 0x%02x)\n", __func__, err, reg, data);
- return err;
- }
-
- return 0;
-}
-
-static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg)
-{
- int ret;
- u8 b = 0;
- struct i2c_msg msg[] = {
- { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
- { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 }
- };
-
- ret = i2c_transfer(state->i2c, msg, 2);
-
- if (ret != 2) {
- err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret);
- return ret;
- }
-
- /* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */
-
- return b;
-}
-
-#define cx24123_readreg(state, reg) \
- cx24123_i2c_readreg(state, state->config->demod_address, reg)
-#define cx24123_writereg(state, reg, val) \
- cx24123_i2c_writereg(state, state->config->demod_address, reg, val)
-
-static int cx24123_set_inversion(struct cx24123_state *state,
- fe_spectral_inversion_t inversion)
-{
- u8 nom_reg = cx24123_readreg(state, 0x0e);
- u8 auto_reg = cx24123_readreg(state, 0x10);
-
- switch (inversion) {
- case INVERSION_OFF:
- dprintk("inversion off\n");
- cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
- cx24123_writereg(state, 0x10, auto_reg | 0x80);
- break;
- case INVERSION_ON:
- dprintk("inversion on\n");
- cx24123_writereg(state, 0x0e, nom_reg | 0x80);
- cx24123_writereg(state, 0x10, auto_reg | 0x80);
- break;
- case INVERSION_AUTO:
- dprintk("inversion auto\n");
- cx24123_writereg(state, 0x10, auto_reg & ~0x80);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int cx24123_get_inversion(struct cx24123_state *state,
- fe_spectral_inversion_t *inversion)
-{
- u8 val;
-
- val = cx24123_readreg(state, 0x1b) >> 7;
-
- if (val == 0) {
- dprintk("read inversion off\n");
- *inversion = INVERSION_OFF;
- } else {
- dprintk("read inversion on\n");
- *inversion = INVERSION_ON;
- }
-
- return 0;
-}
-
-static int cx24123_set_fec(struct cx24123_state *state, fe_code_rate_t fec)
-{
- u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
-
- if ((fec < FEC_NONE) || (fec > FEC_AUTO))
- fec = FEC_AUTO;
-
- /* Set the soft decision threshold */
- if (fec == FEC_1_2)
- cx24123_writereg(state, 0x43,
- cx24123_readreg(state, 0x43) | 0x01);
- else
- cx24123_writereg(state, 0x43,
- cx24123_readreg(state, 0x43) & ~0x01);
-
- switch (fec) {
- case FEC_1_2:
- dprintk("set FEC to 1/2\n");
- cx24123_writereg(state, 0x0e, nom_reg | 0x01);
- cx24123_writereg(state, 0x0f, 0x02);
- break;
- case FEC_2_3:
- dprintk("set FEC to 2/3\n");
- cx24123_writereg(state, 0x0e, nom_reg | 0x02);
- cx24123_writereg(state, 0x0f, 0x04);
- break;
- case FEC_3_4:
- dprintk("set FEC to 3/4\n");
- cx24123_writereg(state, 0x0e, nom_reg | 0x03);
- cx24123_writereg(state, 0x0f, 0x08);
- break;
- case FEC_4_5:
- dprintk("set FEC to 4/5\n");
- cx24123_writereg(state, 0x0e, nom_reg | 0x04);
- cx24123_writereg(state, 0x0f, 0x10);
- break;
- case FEC_5_6:
- dprintk("set FEC to 5/6\n");
- cx24123_writereg(state, 0x0e, nom_reg | 0x05);
- cx24123_writereg(state, 0x0f, 0x20);
- break;
- case FEC_6_7:
- dprintk("set FEC to 6/7\n");
- cx24123_writereg(state, 0x0e, nom_reg | 0x06);
- cx24123_writereg(state, 0x0f, 0x40);
- break;
- case FEC_7_8:
- dprintk("set FEC to 7/8\n");
- cx24123_writereg(state, 0x0e, nom_reg | 0x07);
- cx24123_writereg(state, 0x0f, 0x80);
- break;
- case FEC_AUTO:
- dprintk("set FEC to auto\n");
- cx24123_writereg(state, 0x0f, 0xfe);
- break;
- default:
- return -EOPNOTSUPP;
- }
-
- return 0;
-}
-
-static int cx24123_get_fec(struct cx24123_state *state, fe_code_rate_t *fec)
-{
- int ret;
-
- ret = cx24123_readreg(state, 0x1b);
- if (ret < 0)
- return ret;
- ret = ret & 0x07;
-
- switch (ret) {
- case 1:
- *fec = FEC_1_2;
- break;
- case 2:
- *fec = FEC_2_3;
- break;
- case 3:
- *fec = FEC_3_4;
- break;
- case 4:
- *fec = FEC_4_5;
- break;
- case 5:
- *fec = FEC_5_6;
- break;
- case 6:
- *fec = FEC_6_7;
- break;
- case 7:
- *fec = FEC_7_8;
- break;
- default:
- /* this can happen when there's no lock */
- *fec = FEC_NONE;
- }
-
- return 0;
-}
-
-/* Approximation of closest integer of log2(a/b). It actually gives the
- lowest integer i such that 2^i >= round(a/b) */
-static u32 cx24123_int_log2(u32 a, u32 b)
-{
- u32 exp, nearest = 0;
- u32 div = a / b;
- if (a % b >= b / 2)
- ++div;
- if (div < (1 << 31)) {
- for (exp = 1; div > exp; nearest++)
- exp += exp;
- }
- return nearest;
-}
-
-static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate)
-{
- u32 tmp, sample_rate, ratio, sample_gain;
- u8 pll_mult;
-
- /* check if symbol rate is within limits */
- if ((srate > state->frontend.ops.info.symbol_rate_max) ||
- (srate < state->frontend.ops.info.symbol_rate_min))
- return -EOPNOTSUPP;
-
- /* choose the sampling rate high enough for the required operation,
- while optimizing the power consumed by the demodulator */
- if (srate < (XTAL*2)/2)
- pll_mult = 2;
- else if (srate < (XTAL*3)/2)
- pll_mult = 3;
- else if (srate < (XTAL*4)/2)
- pll_mult = 4;
- else if (srate < (XTAL*5)/2)
- pll_mult = 5;
- else if (srate < (XTAL*6)/2)
- pll_mult = 6;
- else if (srate < (XTAL*7)/2)
- pll_mult = 7;
- else if (srate < (XTAL*8)/2)
- pll_mult = 8;
- else
- pll_mult = 9;
-
-
- sample_rate = pll_mult * XTAL;
-
- /*
- SYSSymbolRate[21:0] = (srate << 23) / sample_rate
-
- We have to use 32 bit unsigned arithmetic without precision loss.
- The maximum srate is 45000000 or 0x02AEA540. This number has
- only 6 clear bits on top, hence we can shift it left only 6 bits
- at a time. Borrowed from cx24110.c
- */
-
- tmp = srate << 6;
- ratio = tmp / sample_rate;
-
- tmp = (tmp % sample_rate) << 6;
- ratio = (ratio << 6) + (tmp / sample_rate);
-
- tmp = (tmp % sample_rate) << 6;
- ratio = (ratio << 6) + (tmp / sample_rate);
-
- tmp = (tmp % sample_rate) << 5;
- ratio = (ratio << 5) + (tmp / sample_rate);
-
-
- cx24123_writereg(state, 0x01, pll_mult * 6);
-
- cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f);
- cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff);
- cx24123_writereg(state, 0x0a, ratio & 0xff);
-
- /* also set the demodulator sample gain */
- sample_gain = cx24123_int_log2(sample_rate, srate);
- tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
- cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);
-
- dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n",
- srate, ratio, sample_rate, sample_gain);
-
- return 0;
-}
-
-/*
- * Based on the required frequency and symbolrate, the tuner AGC has
- * to be configured and the correct band selected.
- * Calculate those values.
- */
-static int cx24123_pll_calculate(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- struct cx24123_state *state = fe->demodulator_priv;
- u32 ndiv = 0, adiv = 0, vco_div = 0;
- int i = 0;
- int pump = 2;
- int band = 0;
- int num_bands = ARRAY_SIZE(cx24123_bandselect_vals);
- struct cx24123_bandselect_val *bsv = NULL;
- struct cx24123_AGC_val *agcv = NULL;
-
- /* Defaults for low freq, low rate */
- state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
- state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
- state->bandselectarg = cx24123_bandselect_vals[0].progdata;
- vco_div = cx24123_bandselect_vals[0].VCOdivider;
-
- /* For the given symbol rate, determine the VCA, VGA and
- * FILTUNE programming bits */
- for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) {
- agcv = &cx24123_AGC_vals[i];
- if ((agcv->symbolrate_low <= p->symbol_rate) &&
- (agcv->symbolrate_high >= p->symbol_rate)) {
- state->VCAarg = agcv->VCAprogdata;
- state->VGAarg = agcv->VGAprogdata;
- state->FILTune = agcv->FILTune;
- }
- }
-
- /* determine the band to use */
- if (force_band < 1 || force_band > num_bands) {
- for (i = 0; i < num_bands; i++) {
- bsv = &cx24123_bandselect_vals[i];
- if ((bsv->freq_low <= p->frequency) &&
- (bsv->freq_high >= p->frequency))
- band = i;
- }
- } else
- band = force_band - 1;
-
- state->bandselectarg = cx24123_bandselect_vals[band].progdata;
- vco_div = cx24123_bandselect_vals[band].VCOdivider;
-
- /* determine the charge pump current */
- if (p->frequency < (cx24123_bandselect_vals[band].freq_low +
- cx24123_bandselect_vals[band].freq_high) / 2)
- pump = 0x01;
- else
- pump = 0x02;
-
- /* Determine the N/A dividers for the requested lband freq (in kHz). */
- /* Note: the reference divider R=10, frequency is in KHz,
- * XTAL is in Hz */
- ndiv = (((p->frequency * vco_div * 10) /
- (2 * XTAL / 1000)) / 32) & 0x1ff;
- adiv = (((p->frequency * vco_div * 10) /
- (2 * XTAL / 1000)) % 32) & 0x1f;
-
- if (adiv == 0 && ndiv > 0)
- ndiv--;
-
- /* control bits 11, refdiv 11, charge pump polarity 1,
- * charge pump current, ndiv, adiv */
- state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) |
- (pump << 14) | (ndiv << 5) | adiv;
-
- return 0;
-}
-
-/*
- * Tuner data is 21 bits long, must be left-aligned in data.
- * Tuner cx24109 is written through a dedicated 3wire interface
- * on the demod chip.
- */
-static int cx24123_pll_writereg(struct dvb_frontend *fe, u32 data)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- unsigned long timeout;
-
- dprintk("pll writereg called, data=0x%08x\n", data);
-
- /* align the 21 bytes into to bit23 boundary */
- data = data << 3;
-
- /* Reset the demod pll word length to 0x15 bits */
- cx24123_writereg(state, 0x21, 0x15);
-
- /* write the msb 8 bits, wait for the send to be completed */
- timeout = jiffies + msecs_to_jiffies(40);
- cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
- while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
- if (time_after(jiffies, timeout)) {
- err("%s: demodulator is not responding, "\
- "possibly hung, aborting.\n", __func__);
- return -EREMOTEIO;
- }
- msleep(10);
- }
-
- /* send another 8 bytes, wait for the send to be completed */
- timeout = jiffies + msecs_to_jiffies(40);
- cx24123_writereg(state, 0x22, (data >> 8) & 0xff);
- while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
- if (time_after(jiffies, timeout)) {
- err("%s: demodulator is not responding, "\
- "possibly hung, aborting.\n", __func__);
- return -EREMOTEIO;
- }
- msleep(10);
- }
-
- /* send the lower 5 bits of this byte, padded with 3 LBB,
- * wait for the send to be completed */
- timeout = jiffies + msecs_to_jiffies(40);
- cx24123_writereg(state, 0x22, (data) & 0xff);
- while ((cx24123_readreg(state, 0x20) & 0x80)) {
- if (time_after(jiffies, timeout)) {
- err("%s: demodulator is not responding," \
- "possibly hung, aborting.\n", __func__);
- return -EREMOTEIO;
- }
- msleep(10);
- }
-
- /* Trigger the demod to configure the tuner */
- cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
- cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
-
- return 0;
-}
-
-static int cx24123_pll_tune(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- struct cx24123_state *state = fe->demodulator_priv;
- u8 val;
-
- dprintk("frequency=%i\n", p->frequency);
-
- if (cx24123_pll_calculate(fe) != 0) {
- err("%s: cx24123_pll_calcutate failed\n", __func__);
- return -EINVAL;
- }
-
- /* Write the new VCO/VGA */
- cx24123_pll_writereg(fe, state->VCAarg);
- cx24123_pll_writereg(fe, state->VGAarg);
-
- /* Write the new bandselect and pll args */
- cx24123_pll_writereg(fe, state->bandselectarg);
- cx24123_pll_writereg(fe, state->pllarg);
-
- /* set the FILTUNE voltage */
- val = cx24123_readreg(state, 0x28) & ~0x3;
- cx24123_writereg(state, 0x27, state->FILTune >> 2);
- cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
-
- dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg,
- state->bandselectarg, state->pllarg);
-
- return 0;
-}
-
-
-/*
- * 0x23:
- * [7:7] = BTI enabled
- * [6:6] = I2C repeater enabled
- * [5:5] = I2C repeater start
- * [0:0] = BTI start
- */
-
-/* mode == 1 -> i2c-repeater, 0 -> bti */
-static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start)
-{
- u8 r = cx24123_readreg(state, 0x23) & 0x1e;
- if (mode)
- r |= (1 << 6) | (start << 5);
- else
- r |= (1 << 7) | (start);
- return cx24123_writereg(state, 0x23, r);
-}
-
-static int cx24123_initfe(struct dvb_frontend *fe)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- int i;
-
- dprintk("init frontend\n");
-
- /* Configure the demod to a good set of defaults */
- for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++)
- cx24123_writereg(state, cx24123_regdata[i].reg,
- cx24123_regdata[i].data);
-
- /* Set the LNB polarity */
- if (state->config->lnb_polarity)
- cx24123_writereg(state, 0x32,
- cx24123_readreg(state, 0x32) | 0x02);
-
- if (state->config->dont_use_pll)
- cx24123_repeater_mode(state, 1, 0);
-
- return 0;
-}
-
-static int cx24123_set_voltage(struct dvb_frontend *fe,
- fe_sec_voltage_t voltage)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- u8 val;
-
- val = cx24123_readreg(state, 0x29) & ~0x40;
-
- switch (voltage) {
- case SEC_VOLTAGE_13:
- dprintk("setting voltage 13V\n");
- return cx24123_writereg(state, 0x29, val & 0x7f);
- case SEC_VOLTAGE_18:
- dprintk("setting voltage 18V\n");
- return cx24123_writereg(state, 0x29, val | 0x80);
- case SEC_VOLTAGE_OFF:
- /* already handled in cx88-dvb */
- return 0;
- default:
- return -EINVAL;
- };
-
- return 0;
-}
-
-/* wait for diseqc queue to become ready (or timeout) */
-static void cx24123_wait_for_diseqc(struct cx24123_state *state)
-{
- unsigned long timeout = jiffies + msecs_to_jiffies(200);
- while (!(cx24123_readreg(state, 0x29) & 0x40)) {
- if (time_after(jiffies, timeout)) {
- err("%s: diseqc queue not ready, " \
- "command may be lost.\n", __func__);
- break;
- }
- msleep(10);
- }
-}
-
-static int cx24123_send_diseqc_msg(struct dvb_frontend *fe,
- struct dvb_diseqc_master_cmd *cmd)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- int i, val, tone;
-
- dprintk("\n");
-
- /* stop continuous tone if enabled */
- tone = cx24123_readreg(state, 0x29);
- if (tone & 0x10)
- cx24123_writereg(state, 0x29, tone & ~0x50);
-
- /* wait for diseqc queue ready */
- cx24123_wait_for_diseqc(state);
-
- /* select tone mode */
- cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
-
- for (i = 0; i < cmd->msg_len; i++)
- cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
-
- val = cx24123_readreg(state, 0x29);
- cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) |
- ((cmd->msg_len-3) & 3));
-
- /* wait for diseqc message to finish sending */
- cx24123_wait_for_diseqc(state);
-
- /* restart continuous tone if enabled */
- if (tone & 0x10)
- cx24123_writereg(state, 0x29, tone & ~0x40);
-
- return 0;
-}
-
-static int cx24123_diseqc_send_burst(struct dvb_frontend *fe,
- fe_sec_mini_cmd_t burst)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- int val, tone;
-
- dprintk("\n");
-
- /* stop continuous tone if enabled */
- tone = cx24123_readreg(state, 0x29);
- if (tone & 0x10)
- cx24123_writereg(state, 0x29, tone & ~0x50);
-
- /* wait for diseqc queue ready */
- cx24123_wait_for_diseqc(state);
-
- /* select tone mode */
- cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
- msleep(30);
- val = cx24123_readreg(state, 0x29);
- if (burst == SEC_MINI_A)
- cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
- else if (burst == SEC_MINI_B)
- cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
- else
- return -EINVAL;
-
- cx24123_wait_for_diseqc(state);
- cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
-
- /* restart continuous tone if enabled */
- if (tone & 0x10)
- cx24123_writereg(state, 0x29, tone & ~0x40);
-
- return 0;
-}
-
-static int cx24123_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- int sync = cx24123_readreg(state, 0x14);
-
- *status = 0;
- if (state->config->dont_use_pll) {
- u32 tun_status = 0;
- if (fe->ops.tuner_ops.get_status)
- fe->ops.tuner_ops.get_status(fe, &tun_status);
- if (tun_status & TUNER_STATUS_LOCKED)
- *status |= FE_HAS_SIGNAL;
- } else {
- int lock = cx24123_readreg(state, 0x20);
- if (lock & 0x01)
- *status |= FE_HAS_SIGNAL;
- }
-
- if (sync & 0x02)
- *status |= FE_HAS_CARRIER; /* Phase locked */
- if (sync & 0x04)
- *status |= FE_HAS_VITERBI;
-
- /* Reed-Solomon Status */
- if (sync & 0x08)
- *status |= FE_HAS_SYNC;
- if (sync & 0x80)
- *status |= FE_HAS_LOCK; /*Full Sync */
-
- return 0;
-}
-
-/*
- * Configured to return the measurement of errors in blocks,
- * because no UCBLOCKS value is available, so this value doubles up
- * to satisfy both measurements.
- */
-static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct cx24123_state *state = fe->demodulator_priv;
-
- /* The true bit error rate is this value divided by
- the window size (set as 256 * 255) */
- *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
- (cx24123_readreg(state, 0x1d) << 8 |
- cx24123_readreg(state, 0x1e));
-
- dprintk("BER = %d\n", *ber);
-
- return 0;
-}
-
-static int cx24123_read_signal_strength(struct dvb_frontend *fe,
- u16 *signal_strength)
-{
- struct cx24123_state *state = fe->demodulator_priv;
-
- /* larger = better */
- *signal_strength = cx24123_readreg(state, 0x3b) << 8;
-
- dprintk("Signal strength = %d\n", *signal_strength);
-
- return 0;
-}
-
-static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- struct cx24123_state *state = fe->demodulator_priv;
-
- /* Inverted raw Es/N0 count, totally bogus but better than the
- BER threshold. */
- *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) |
- (u16)cx24123_readreg(state, 0x19));
-
- dprintk("read S/N index = %d\n", *snr);
-
- return 0;
-}
-
-static int cx24123_set_frontend(struct dvb_frontend *fe)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-
- dprintk("\n");
-
- if (state->config->set_ts_params)
- state->config->set_ts_params(fe, 0);
-
- state->currentfreq = p->frequency;
- state->currentsymbolrate = p->symbol_rate;
-
- cx24123_set_inversion(state, p->inversion);
- cx24123_set_fec(state, p->fec_inner);
- cx24123_set_symbolrate(state, p->symbol_rate);
-
- if (!state->config->dont_use_pll)
- cx24123_pll_tune(fe);
- else if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
- else
- err("it seems I don't have a tuner...");
-
- /* Enable automatic acquisition and reset cycle */
- cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
- cx24123_writereg(state, 0x00, 0x10);
- cx24123_writereg(state, 0x00, 0);
-
- if (state->config->agc_callback)
- state->config->agc_callback(fe);
-
- return 0;
-}
-
-static int cx24123_get_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- struct cx24123_state *state = fe->demodulator_priv;
-
- dprintk("\n");
-
- if (cx24123_get_inversion(state, &p->inversion) != 0) {
- err("%s: Failed to get inversion status\n", __func__);
- return -EREMOTEIO;
- }
- if (cx24123_get_fec(state, &p->fec_inner) != 0) {
- err("%s: Failed to get fec status\n", __func__);
- return -EREMOTEIO;
- }
- p->frequency = state->currentfreq;
- p->symbol_rate = state->currentsymbolrate;
-
- return 0;
-}
-
-static int cx24123_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- u8 val;
-
- /* wait for diseqc queue ready */
- cx24123_wait_for_diseqc(state);
-
- val = cx24123_readreg(state, 0x29) & ~0x40;
-
- switch (tone) {
- case SEC_TONE_ON:
- dprintk("setting tone on\n");
- return cx24123_writereg(state, 0x29, val | 0x10);
- case SEC_TONE_OFF:
- dprintk("setting tone off\n");
- return cx24123_writereg(state, 0x29, val & 0xef);
- default:
- err("CASE reached default with tone=%d\n", tone);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int cx24123_tune(struct dvb_frontend *fe,
- bool re_tune,
- unsigned int mode_flags,
- unsigned int *delay,
- fe_status_t *status)
-{
- int retval = 0;
-
- if (re_tune)
- retval = cx24123_set_frontend(fe);
-
- if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
- cx24123_read_status(fe, status);
- *delay = HZ/10;
-
- return retval;
-}
-
-static int cx24123_get_algo(struct dvb_frontend *fe)
-{
- return 1; /* FE_ALGO_HW */
-}
-
-static void cx24123_release(struct dvb_frontend *fe)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- dprintk("\n");
- i2c_del_adapter(&state->tuner_i2c_adapter);
- kfree(state);
-}
-
-static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap,
- struct i2c_msg msg[], int num)
-{
- struct cx24123_state *state = i2c_get_adapdata(i2c_adap);
- /* this repeater closes after the first stop */
- cx24123_repeater_mode(state, 1, 1);
- return i2c_transfer(state->i2c, msg, num);
-}
-
-static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter)
-{
- return I2C_FUNC_I2C;
-}
-
-static struct i2c_algorithm cx24123_tuner_i2c_algo = {
- .master_xfer = cx24123_tuner_i2c_tuner_xfer,
- .functionality = cx24123_tuner_i2c_func,
-};
-
-struct i2c_adapter *
- cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe)
-{
- struct cx24123_state *state = fe->demodulator_priv;
- return &state->tuner_i2c_adapter;
-}
-EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter);
-
-static struct dvb_frontend_ops cx24123_ops;
-
-struct dvb_frontend *cx24123_attach(const struct cx24123_config *config,
- struct i2c_adapter *i2c)
-{
- /* allocate memory for the internal state */
- struct cx24123_state *state =
- kzalloc(sizeof(struct cx24123_state), GFP_KERNEL);
-
- dprintk("\n");
- if (state == NULL) {
- err("Unable to kzalloc\n");
- goto error;
- }
-
- /* setup the state */
- state->config = config;
- state->i2c = i2c;
-
- /* check if the demod is there */
- state->demod_rev = cx24123_readreg(state, 0x00);
- switch (state->demod_rev) {
- case 0xe1:
- info("detected CX24123C\n");
- break;
- case 0xd1:
- info("detected CX24123\n");
- break;
- default:
- err("wrong demod revision: %x\n", state->demod_rev);
- goto error;
- }
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &cx24123_ops,
- sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
-
- /* create tuner i2c adapter */
- if (config->dont_use_pll)
- cx24123_repeater_mode(state, 1, 0);
-
- strlcpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus",
- sizeof(state->tuner_i2c_adapter.name));
- state->tuner_i2c_adapter.algo = &cx24123_tuner_i2c_algo;
- state->tuner_i2c_adapter.algo_data = NULL;
- i2c_set_adapdata(&state->tuner_i2c_adapter, state);
- if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
- err("tuner i2c bus could not be initialized\n");
- goto error;
- }
-
- return &state->frontend;
-
-error:
- kfree(state);
-
- return NULL;
-}
-EXPORT_SYMBOL(cx24123_attach);
-
-static struct dvb_frontend_ops cx24123_ops = {
- .delsys = { SYS_DVBS },
- .info = {
- .name = "Conexant CX24123/CX24109",
- .frequency_min = 950000,
- .frequency_max = 2150000,
- .frequency_stepsize = 1011, /* kHz for QPSK frontends */
- .frequency_tolerance = 5000,
- .symbol_rate_min = 1000000,
- .symbol_rate_max = 45000000,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
- FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_RECOVER
- },
-
- .release = cx24123_release,
-
- .init = cx24123_initfe,
- .set_frontend = cx24123_set_frontend,
- .get_frontend = cx24123_get_frontend,
- .read_status = cx24123_read_status,
- .read_ber = cx24123_read_ber,
- .read_signal_strength = cx24123_read_signal_strength,
- .read_snr = cx24123_read_snr,
- .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
- .diseqc_send_burst = cx24123_diseqc_send_burst,
- .set_tone = cx24123_set_tone,
- .set_voltage = cx24123_set_voltage,
- .tune = cx24123_tune,
- .get_frontend_algo = cx24123_get_algo,
-};
-
-MODULE_DESCRIPTION("DVB Frontend module for Conexant " \
- "CX24123/CX24109/CX24113 hardware");
-MODULE_AUTHOR("Steven Toth");
-MODULE_LICENSE("GPL");
-
diff --git a/drivers/media/dvb/frontends/cx24123.h b/drivers/media/dvb/frontends/cx24123.h
deleted file mode 100644
index 51ae866e9fe..00000000000
--- a/drivers/media/dvb/frontends/cx24123.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
-
- Copyright (C) 2005 Steven Toth <stoth@linuxtv.org>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-#ifndef CX24123_H
-#define CX24123_H
-
-#include <linux/dvb/frontend.h>
-
-struct cx24123_config {
- /* the demodulator's i2c address */
- u8 demod_address;
-
- /* Need to set device param for start_dma */
- int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
-
- /* 0 = LNB voltage normal, 1 = LNB voltage inverted */
- int lnb_polarity;
-
- /* this device has another tuner */
- u8 dont_use_pll;
- void (*agc_callback) (struct dvb_frontend *);
-};
-
-#if defined(CONFIG_DVB_CX24123) || (defined(CONFIG_DVB_CX24123_MODULE) \
- && defined(MODULE))
-extern struct dvb_frontend *cx24123_attach(const struct cx24123_config *config,
- struct i2c_adapter *i2c);
-extern struct i2c_adapter *cx24123_get_tuner_i2c_adapter(struct dvb_frontend *);
-#else
-static inline struct dvb_frontend *cx24123_attach(
- const struct cx24123_config *config, struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-static struct i2c_adapter *
- cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif /* CX24123_H */
diff --git a/drivers/media/dvb/frontends/cxd2820r.h b/drivers/media/dvb/frontends/cxd2820r.h
deleted file mode 100644
index 5aa306ebb7e..00000000000
--- a/drivers/media/dvb/frontends/cxd2820r.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Sony CXD2820R demodulator driver
- *
- * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-
-#ifndef CXD2820R_H
-#define CXD2820R_H
-
-#include <linux/dvb/frontend.h>
-
-#define CXD2820R_GPIO_D (0 << 0) /* disable */
-#define CXD2820R_GPIO_E (1 << 0) /* enable */
-#define CXD2820R_GPIO_O (0 << 1) /* output */
-#define CXD2820R_GPIO_I (1 << 1) /* input */
-#define CXD2820R_GPIO_L (0 << 2) /* output low */
-#define CXD2820R_GPIO_H (1 << 2) /* output high */
-
-#define CXD2820R_TS_SERIAL 0x08
-#define CXD2820R_TS_SERIAL_MSB 0x28
-#define CXD2820R_TS_PARALLEL 0x30
-#define CXD2820R_TS_PARALLEL_MSB 0x70
-
-struct cxd2820r_config {
- /* Demodulator I2C address.
- * Driver determines DVB-C slave I2C address automatically from master
- * address.
- * Default: none, must set
- * Values: 0x6c, 0x6d
- */
- u8 i2c_address;
-
- /* TS output mode.
- * Default: none, must set.
- * Values:
- */
- u8 ts_mode;
-
- /* IF AGC polarity.
- * Default: 0
- * Values: 0, 1
- */
- bool if_agc_polarity;
-
- /* Spectrum inversion.
- * Default: 0
- * Values: 0, 1
- */
- bool spec_inv;
-
- /* GPIOs for all used modes.
- * Default: none, disabled
- * Values: <see above>
- */
- u8 gpio_dvbt[3];
- u8 gpio_dvbt2[3];
- u8 gpio_dvbc[3];
-};
-
-
-#if defined(CONFIG_DVB_CXD2820R) || \
- (defined(CONFIG_DVB_CXD2820R_MODULE) && defined(MODULE))
-extern struct dvb_frontend *cxd2820r_attach(
- const struct cxd2820r_config *config,
- struct i2c_adapter *i2c
-);
-#else
-static inline struct dvb_frontend *cxd2820r_attach(
- const struct cxd2820r_config *config,
- struct i2c_adapter *i2c
-)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-#endif
-
-#endif /* CXD2820R_H */
diff --git a/drivers/media/dvb/frontends/cxd2820r_c.c b/drivers/media/dvb/frontends/cxd2820r_c.c
deleted file mode 100644
index ed3b0ba624d..00000000000
--- a/drivers/media/dvb/frontends/cxd2820r_c.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * Sony CXD2820R demodulator driver
- *
- * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-
-#include "cxd2820r_priv.h"
-
-int cxd2820r_set_frontend_c(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret, i;
- u8 buf[2];
- u32 if_freq;
- u16 if_ctl;
- u64 num;
- struct reg_val_mask tab[] = {
- { 0x00080, 0x01, 0xff },
- { 0x00081, 0x05, 0xff },
- { 0x00085, 0x07, 0xff },
- { 0x00088, 0x01, 0xff },
-
- { 0x00082, 0x20, 0x60 },
- { 0x1016a, 0x48, 0xff },
- { 0x100a5, 0x00, 0x01 },
- { 0x10020, 0x06, 0x07 },
- { 0x10059, 0x50, 0xff },
- { 0x10087, 0x0c, 0x3c },
- { 0x1008b, 0x07, 0xff },
- { 0x1001f, priv->cfg.if_agc_polarity << 7, 0x80 },
- { 0x10070, priv->cfg.ts_mode, 0xff },
- };
-
- dbg("%s: RF=%d SR=%d", __func__, c->frequency, c->symbol_rate);
-
- /* update GPIOs */
- ret = cxd2820r_gpio(fe);
- if (ret)
- goto error;
-
- /* program tuner */
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
-
- if (priv->delivery_system != SYS_DVBC_ANNEX_A) {
- for (i = 0; i < ARRAY_SIZE(tab); i++) {
- ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
- tab[i].val, tab[i].mask);
- if (ret)
- goto error;
- }
- }
-
- priv->delivery_system = SYS_DVBC_ANNEX_A;
- priv->ber_running = 0; /* tune stops BER counter */
-
- /* program IF frequency */
- if (fe->ops.tuner_ops.get_if_frequency) {
- ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
- if (ret)
- goto error;
- } else
- if_freq = 0;
-
- dbg("%s: if_freq=%d", __func__, if_freq);
-
- num = if_freq / 1000; /* Hz => kHz */
- num *= 0x4000;
- if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
- buf[0] = (if_ctl >> 8) & 0x3f;
- buf[1] = (if_ctl >> 0) & 0xff;
-
- ret = cxd2820r_wr_regs(priv, 0x10042, buf, 2);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
- if (ret)
- goto error;
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_get_frontend_c(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret;
- u8 buf[2];
-
- ret = cxd2820r_rd_regs(priv, 0x1001a, buf, 2);
- if (ret)
- goto error;
-
- c->symbol_rate = 2500 * ((buf[0] & 0x0f) << 8 | buf[1]);
-
- ret = cxd2820r_rd_reg(priv, 0x10019, &buf[0]);
- if (ret)
- goto error;
-
- switch ((buf[0] >> 0) & 0x07) {
- case 0:
- c->modulation = QAM_16;
- break;
- case 1:
- c->modulation = QAM_32;
- break;
- case 2:
- c->modulation = QAM_64;
- break;
- case 3:
- c->modulation = QAM_128;
- break;
- case 4:
- c->modulation = QAM_256;
- break;
- }
-
- switch ((buf[0] >> 7) & 0x01) {
- case 0:
- c->inversion = INVERSION_OFF;
- break;
- case 1:
- c->inversion = INVERSION_ON;
- break;
- }
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_ber_c(struct dvb_frontend *fe, u32 *ber)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[3], start_ber = 0;
- *ber = 0;
-
- if (priv->ber_running) {
- ret = cxd2820r_rd_regs(priv, 0x10076, buf, sizeof(buf));
- if (ret)
- goto error;
-
- if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) {
- *ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0];
- start_ber = 1;
- }
- } else {
- priv->ber_running = 1;
- start_ber = 1;
- }
-
- if (start_ber) {
- /* (re)start BER */
- ret = cxd2820r_wr_reg(priv, 0x10079, 0x01);
- if (ret)
- goto error;
- }
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_signal_strength_c(struct dvb_frontend *fe,
- u16 *strength)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[2];
- u16 tmp;
-
- ret = cxd2820r_rd_regs(priv, 0x10049, buf, sizeof(buf));
- if (ret)
- goto error;
-
- tmp = (buf[0] & 0x03) << 8 | buf[1];
- tmp = (~tmp & 0x03ff);
-
- if (tmp == 512)
- /* ~no signal */
- tmp = 0;
- else if (tmp > 350)
- tmp = 350;
-
- /* scale value to 0x0000-0xffff */
- *strength = tmp * 0xffff / (350-0);
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_snr_c(struct dvb_frontend *fe, u16 *snr)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 tmp;
- unsigned int A, B;
- /* report SNR in dB * 10 */
-
- ret = cxd2820r_rd_reg(priv, 0x10019, &tmp);
- if (ret)
- goto error;
-
- if (((tmp >> 0) & 0x03) % 2) {
- A = 875;
- B = 650;
- } else {
- A = 950;
- B = 760;
- }
-
- ret = cxd2820r_rd_reg(priv, 0x1004d, &tmp);
- if (ret)
- goto error;
-
- #define CXD2820R_LOG2_E_24 24204406 /* log2(e) << 24 */
- if (tmp)
- *snr = A * (intlog2(B / tmp) >> 5) / (CXD2820R_LOG2_E_24 >> 5)
- / 10;
- else
- *snr = 0;
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_ucblocks_c(struct dvb_frontend *fe, u32 *ucblocks)
-{
- *ucblocks = 0;
- /* no way to read ? */
- return 0;
-}
-
-int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[2];
- *status = 0;
-
- ret = cxd2820r_rd_regs(priv, 0x10088, buf, sizeof(buf));
- if (ret)
- goto error;
-
- if (((buf[0] >> 0) & 0x01) == 1) {
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC;
-
- if (((buf[1] >> 3) & 0x01) == 1) {
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
- }
- }
-
- dbg("%s: lock=%02x %02x", __func__, buf[0], buf[1]);
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_init_c(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
-
- ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
- if (ret)
- goto error;
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_sleep_c(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret, i;
- struct reg_val_mask tab[] = {
- { 0x000ff, 0x1f, 0xff },
- { 0x00085, 0x00, 0xff },
- { 0x00088, 0x01, 0xff },
- { 0x00081, 0x00, 0xff },
- { 0x00080, 0x00, 0xff },
- };
-
- dbg("%s", __func__);
-
- priv->delivery_system = SYS_UNDEFINED;
-
- for (i = 0; i < ARRAY_SIZE(tab); i++) {
- ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
- tab[i].mask);
- if (ret)
- goto error;
- }
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *s)
-{
- s->min_delay_ms = 500;
- s->step_size = 0; /* no zigzag */
- s->max_drift = 0;
-
- return 0;
-}
diff --git a/drivers/media/dvb/frontends/cxd2820r_core.c b/drivers/media/dvb/frontends/cxd2820r_core.c
deleted file mode 100644
index 3bba37d74f5..00000000000
--- a/drivers/media/dvb/frontends/cxd2820r_core.c
+++ /dev/null
@@ -1,646 +0,0 @@
-/*
- * Sony CXD2820R demodulator driver
- *
- * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-
-#include "cxd2820r_priv.h"
-
-int cxd2820r_debug;
-module_param_named(debug, cxd2820r_debug, int, 0644);
-MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-
-/* write multiple registers */
-static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg,
- u8 *val, int len)
-{
- int ret;
- u8 buf[len+1];
- struct i2c_msg msg[1] = {
- {
- .addr = i2c,
- .flags = 0,
- .len = sizeof(buf),
- .buf = buf,
- }
- };
-
- buf[0] = reg;
- memcpy(&buf[1], val, len);
-
- ret = i2c_transfer(priv->i2c, msg, 1);
- if (ret == 1) {
- ret = 0;
- } else {
- warn("i2c wr failed ret:%d reg:%02x len:%d", ret, reg, len);
- ret = -EREMOTEIO;
- }
- return ret;
-}
-
-/* read multiple registers */
-static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg,
- u8 *val, int len)
-{
- int ret;
- u8 buf[len];
- struct i2c_msg msg[2] = {
- {
- .addr = i2c,
- .flags = 0,
- .len = 1,
- .buf = &reg,
- }, {
- .addr = i2c,
- .flags = I2C_M_RD,
- .len = sizeof(buf),
- .buf = buf,
- }
- };
-
- ret = i2c_transfer(priv->i2c, msg, 2);
- if (ret == 2) {
- memcpy(val, buf, len);
- ret = 0;
- } else {
- warn("i2c rd failed ret:%d reg:%02x len:%d", ret, reg, len);
- ret = -EREMOTEIO;
- }
-
- return ret;
-}
-
-/* write multiple registers */
-int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
- int len)
-{
- int ret;
- u8 i2c_addr;
- u8 reg = (reginfo >> 0) & 0xff;
- u8 bank = (reginfo >> 8) & 0xff;
- u8 i2c = (reginfo >> 16) & 0x01;
-
- /* select I2C */
- if (i2c)
- i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */
- else
- i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */
-
- /* switch bank if needed */
- if (bank != priv->bank[i2c]) {
- ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1);
- if (ret)
- return ret;
- priv->bank[i2c] = bank;
- }
- return cxd2820r_wr_regs_i2c(priv, i2c_addr, reg, val, len);
-}
-
-/* read multiple registers */
-int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
- int len)
-{
- int ret;
- u8 i2c_addr;
- u8 reg = (reginfo >> 0) & 0xff;
- u8 bank = (reginfo >> 8) & 0xff;
- u8 i2c = (reginfo >> 16) & 0x01;
-
- /* select I2C */
- if (i2c)
- i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */
- else
- i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */
-
- /* switch bank if needed */
- if (bank != priv->bank[i2c]) {
- ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1);
- if (ret)
- return ret;
- priv->bank[i2c] = bank;
- }
- return cxd2820r_rd_regs_i2c(priv, i2c_addr, reg, val, len);
-}
-
-/* write single register */
-int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val)
-{
- return cxd2820r_wr_regs(priv, reg, &val, 1);
-}
-
-/* read single register */
-int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val)
-{
- return cxd2820r_rd_regs(priv, reg, val, 1);
-}
-
-/* write single register with mask */
-int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val,
- u8 mask)
-{
- int ret;
- u8 tmp;
-
- /* no need for read if whole reg is written */
- if (mask != 0xff) {
- ret = cxd2820r_rd_reg(priv, reg, &tmp);
- if (ret)
- return ret;
-
- val &= mask;
- tmp &= ~mask;
- val |= tmp;
- }
-
- return cxd2820r_wr_reg(priv, reg, val);
-}
-
-int cxd2820r_gpio(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret, i;
- u8 *gpio, tmp0, tmp1;
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
-
- switch (fe->dtv_property_cache.delivery_system) {
- case SYS_DVBT:
- gpio = priv->cfg.gpio_dvbt;
- break;
- case SYS_DVBT2:
- gpio = priv->cfg.gpio_dvbt2;
- break;
- case SYS_DVBC_ANNEX_AC:
- gpio = priv->cfg.gpio_dvbc;
- break;
- default:
- ret = -EINVAL;
- goto error;
- }
-
- /* update GPIOs only when needed */
- if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio)))
- return 0;
-
- tmp0 = 0x00;
- tmp1 = 0x00;
- for (i = 0; i < sizeof(priv->gpio); i++) {
- /* enable / disable */
- if (gpio[i] & CXD2820R_GPIO_E)
- tmp0 |= (2 << 6) >> (2 * i);
- else
- tmp0 |= (1 << 6) >> (2 * i);
-
- /* input / output */
- if (gpio[i] & CXD2820R_GPIO_I)
- tmp1 |= (1 << (3 + i));
- else
- tmp1 |= (0 << (3 + i));
-
- /* high / low */
- if (gpio[i] & CXD2820R_GPIO_H)
- tmp1 |= (1 << (0 + i));
- else
- tmp1 |= (0 << (0 + i));
-
- dbg("%s: GPIO i=%d %02x %02x", __func__, i, tmp0, tmp1);
- }
-
- dbg("%s: wr gpio=%02x %02x", __func__, tmp0, tmp1);
-
- /* write bits [7:2] */
- ret = cxd2820r_wr_reg_mask(priv, 0x00089, tmp0, 0xfc);
- if (ret)
- goto error;
-
- /* write bits [5:0] */
- ret = cxd2820r_wr_reg_mask(priv, 0x0008e, tmp1, 0x3f);
- if (ret)
- goto error;
-
- memcpy(priv->gpio, gpio, sizeof(priv->gpio));
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-/* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */
-u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor)
-{
- return div_u64(dividend + (divisor / 2), divisor);
-}
-
-static int cxd2820r_set_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret;
-
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
- switch (c->delivery_system) {
- case SYS_DVBT:
- ret = cxd2820r_init_t(fe);
- if (ret < 0)
- goto err;
- ret = cxd2820r_set_frontend_t(fe);
- if (ret < 0)
- goto err;
- break;
- case SYS_DVBT2:
- ret = cxd2820r_init_t(fe);
- if (ret < 0)
- goto err;
- ret = cxd2820r_set_frontend_t2(fe);
- if (ret < 0)
- goto err;
- break;
- case SYS_DVBC_ANNEX_A:
- ret = cxd2820r_init_c(fe);
- if (ret < 0)
- goto err;
- ret = cxd2820r_set_frontend_c(fe);
- if (ret < 0)
- goto err;
- break;
- default:
- dbg("%s: error state=%d", __func__, fe->dtv_property_cache.delivery_system);
- ret = -EINVAL;
- break;
- }
-err:
- return ret;
-}
-static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- int ret;
-
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
- switch (fe->dtv_property_cache.delivery_system) {
- case SYS_DVBT:
- ret = cxd2820r_read_status_t(fe, status);
- break;
- case SYS_DVBT2:
- ret = cxd2820r_read_status_t2(fe, status);
- break;
- case SYS_DVBC_ANNEX_A:
- ret = cxd2820r_read_status_c(fe, status);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static int cxd2820r_get_frontend(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
-
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
-
- if (priv->delivery_system == SYS_UNDEFINED)
- return 0;
-
- switch (fe->dtv_property_cache.delivery_system) {
- case SYS_DVBT:
- ret = cxd2820r_get_frontend_t(fe);
- break;
- case SYS_DVBT2:
- ret = cxd2820r_get_frontend_t2(fe);
- break;
- case SYS_DVBC_ANNEX_A:
- ret = cxd2820r_get_frontend_c(fe);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- int ret;
-
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
- switch (fe->dtv_property_cache.delivery_system) {
- case SYS_DVBT:
- ret = cxd2820r_read_ber_t(fe, ber);
- break;
- case SYS_DVBT2:
- ret = cxd2820r_read_ber_t2(fe, ber);
- break;
- case SYS_DVBC_ANNEX_A:
- ret = cxd2820r_read_ber_c(fe, ber);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
-{
- int ret;
-
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
- switch (fe->dtv_property_cache.delivery_system) {
- case SYS_DVBT:
- ret = cxd2820r_read_signal_strength_t(fe, strength);
- break;
- case SYS_DVBT2:
- ret = cxd2820r_read_signal_strength_t2(fe, strength);
- break;
- case SYS_DVBC_ANNEX_A:
- ret = cxd2820r_read_signal_strength_c(fe, strength);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- int ret;
-
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
- switch (fe->dtv_property_cache.delivery_system) {
- case SYS_DVBT:
- ret = cxd2820r_read_snr_t(fe, snr);
- break;
- case SYS_DVBT2:
- ret = cxd2820r_read_snr_t2(fe, snr);
- break;
- case SYS_DVBC_ANNEX_A:
- ret = cxd2820r_read_snr_c(fe, snr);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- int ret;
-
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
- switch (fe->dtv_property_cache.delivery_system) {
- case SYS_DVBT:
- ret = cxd2820r_read_ucblocks_t(fe, ucblocks);
- break;
- case SYS_DVBT2:
- ret = cxd2820r_read_ucblocks_t2(fe, ucblocks);
- break;
- case SYS_DVBC_ANNEX_A:
- ret = cxd2820r_read_ucblocks_c(fe, ucblocks);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static int cxd2820r_init(struct dvb_frontend *fe)
-{
- return 0;
-}
-
-static int cxd2820r_sleep(struct dvb_frontend *fe)
-{
- int ret;
-
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
- switch (fe->dtv_property_cache.delivery_system) {
- case SYS_DVBT:
- ret = cxd2820r_sleep_t(fe);
- break;
- case SYS_DVBT2:
- ret = cxd2820r_sleep_t2(fe);
- break;
- case SYS_DVBC_ANNEX_A:
- ret = cxd2820r_sleep_c(fe);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static int cxd2820r_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *s)
-{
- int ret;
-
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
- switch (fe->dtv_property_cache.delivery_system) {
- case SYS_DVBT:
- ret = cxd2820r_get_tune_settings_t(fe, s);
- break;
- case SYS_DVBT2:
- ret = cxd2820r_get_tune_settings_t2(fe, s);
- break;
- case SYS_DVBC_ANNEX_A:
- ret = cxd2820r_get_tune_settings_c(fe, s);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret, i;
- fe_status_t status = 0;
- dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
-
- /* switch between DVB-T and DVB-T2 when tune fails */
- if (priv->last_tune_failed) {
- if (priv->delivery_system == SYS_DVBT) {
- ret = cxd2820r_sleep_t(fe);
- if (ret)
- goto error;
-
- c->delivery_system = SYS_DVBT2;
- } else if (priv->delivery_system == SYS_DVBT2) {
- ret = cxd2820r_sleep_t2(fe);
- if (ret)
- goto error;
-
- c->delivery_system = SYS_DVBT;
- }
- }
-
- /* set frontend */
- ret = cxd2820r_set_frontend(fe);
- if (ret)
- goto error;
-
-
- /* frontend lock wait loop count */
- switch (priv->delivery_system) {
- case SYS_DVBT:
- case SYS_DVBC_ANNEX_A:
- i = 20;
- break;
- case SYS_DVBT2:
- i = 40;
- break;
- case SYS_UNDEFINED:
- default:
- i = 0;
- break;
- }
-
- /* wait frontend lock */
- for (; i > 0; i--) {
- dbg("%s: LOOP=%d", __func__, i);
- msleep(50);
- ret = cxd2820r_read_status(fe, &status);
- if (ret)
- goto error;
-
- if (status & FE_HAS_LOCK)
- break;
- }
-
- /* check if we have a valid signal */
- if (status & FE_HAS_LOCK) {
- priv->last_tune_failed = 0;
- return DVBFE_ALGO_SEARCH_SUCCESS;
- } else {
- priv->last_tune_failed = 1;
- return DVBFE_ALGO_SEARCH_AGAIN;
- }
-
-error:
- dbg("%s: failed:%d", __func__, ret);
- return DVBFE_ALGO_SEARCH_ERROR;
-}
-
-static int cxd2820r_get_frontend_algo(struct dvb_frontend *fe)
-{
- return DVBFE_ALGO_CUSTOM;
-}
-
-static void cxd2820r_release(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- dbg("%s", __func__);
-
- kfree(priv);
- return;
-}
-
-static int cxd2820r_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- dbg("%s: %d", __func__, enable);
-
- /* Bit 0 of reg 0xdb in bank 0x00 controls I2C repeater */
- return cxd2820r_wr_reg_mask(priv, 0xdb, enable ? 1 : 0, 0x1);
-}
-
-static const struct dvb_frontend_ops cxd2820r_ops = {
- .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
- /* default: DVB-T/T2 */
- .info = {
- .name = "Sony CXD2820R",
-
- .caps = FE_CAN_FEC_1_2 |
- FE_CAN_FEC_2_3 |
- FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 |
- FE_CAN_FEC_7_8 |
- FE_CAN_FEC_AUTO |
- FE_CAN_QPSK |
- FE_CAN_QAM_16 |
- FE_CAN_QAM_32 |
- FE_CAN_QAM_64 |
- FE_CAN_QAM_128 |
- FE_CAN_QAM_256 |
- FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_HIERARCHY_AUTO |
- FE_CAN_MUTE_TS |
- FE_CAN_2G_MODULATION
- },
-
- .release = cxd2820r_release,
- .init = cxd2820r_init,
- .sleep = cxd2820r_sleep,
-
- .get_tune_settings = cxd2820r_get_tune_settings,
- .i2c_gate_ctrl = cxd2820r_i2c_gate_ctrl,
-
- .get_frontend = cxd2820r_get_frontend,
-
- .get_frontend_algo = cxd2820r_get_frontend_algo,
- .search = cxd2820r_search,
-
- .read_status = cxd2820r_read_status,
- .read_snr = cxd2820r_read_snr,
- .read_ber = cxd2820r_read_ber,
- .read_ucblocks = cxd2820r_read_ucblocks,
- .read_signal_strength = cxd2820r_read_signal_strength,
-};
-
-struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg,
- struct i2c_adapter *i2c)
-{
- struct cxd2820r_priv *priv = NULL;
- int ret;
- u8 tmp;
-
- priv = kzalloc(sizeof (struct cxd2820r_priv), GFP_KERNEL);
- if (!priv)
- goto error;
-
- priv->i2c = i2c;
- memcpy(&priv->cfg, cfg, sizeof (struct cxd2820r_config));
-
- priv->bank[0] = priv->bank[1] = 0xff;
- ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp);
- dbg("%s: chip id=%02x", __func__, tmp);
- if (ret || tmp != 0xe1)
- goto error;
-
- memcpy(&priv->fe.ops, &cxd2820r_ops, sizeof (struct dvb_frontend_ops));
- priv->fe.demodulator_priv = priv;
- return &priv->fe;
-error:
- kfree(priv);
- return NULL;
-}
-EXPORT_SYMBOL(cxd2820r_attach);
-
-MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
-MODULE_DESCRIPTION("Sony CXD2820R demodulator driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/cxd2820r_priv.h b/drivers/media/dvb/frontends/cxd2820r_priv.h
deleted file mode 100644
index 9a9822cad9c..00000000000
--- a/drivers/media/dvb/frontends/cxd2820r_priv.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Sony CXD2820R demodulator driver
- *
- * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-
-#ifndef CXD2820R_PRIV_H
-#define CXD2820R_PRIV_H
-
-#include <linux/dvb/version.h>
-#include "dvb_frontend.h"
-#include "dvb_math.h"
-#include "cxd2820r.h"
-
-#define LOG_PREFIX "cxd2820r"
-
-#undef dbg
-#define dbg(f, arg...) \
- if (cxd2820r_debug) \
- printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
-#undef err
-#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
-#undef info
-#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
-#undef warn
-#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
-
-struct reg_val_mask {
- u32 reg;
- u8 val;
- u8 mask;
-};
-
-struct cxd2820r_priv {
- struct i2c_adapter *i2c;
- struct dvb_frontend fe;
- struct cxd2820r_config cfg;
-
- bool ber_running;
-
- u8 bank[2];
- u8 gpio[3];
-
- fe_delivery_system_t delivery_system;
- bool last_tune_failed; /* for switch between T and T2 tune */
-};
-
-/* cxd2820r_core.c */
-
-extern int cxd2820r_debug;
-
-int cxd2820r_gpio(struct dvb_frontend *fe);
-
-int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val,
- u8 mask);
-
-int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
- int len);
-
-u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor);
-
-int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
- int len);
-
-int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
- int len);
-
-int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val);
-
-int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val);
-
-/* cxd2820r_c.c */
-
-int cxd2820r_get_frontend_c(struct dvb_frontend *fe);
-
-int cxd2820r_set_frontend_c(struct dvb_frontend *fe);
-
-int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status);
-
-int cxd2820r_read_ber_c(struct dvb_frontend *fe, u32 *ber);
-
-int cxd2820r_read_signal_strength_c(struct dvb_frontend *fe, u16 *strength);
-
-int cxd2820r_read_snr_c(struct dvb_frontend *fe, u16 *snr);
-
-int cxd2820r_read_ucblocks_c(struct dvb_frontend *fe, u32 *ucblocks);
-
-int cxd2820r_init_c(struct dvb_frontend *fe);
-
-int cxd2820r_sleep_c(struct dvb_frontend *fe);
-
-int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *s);
-
-/* cxd2820r_t.c */
-
-int cxd2820r_get_frontend_t(struct dvb_frontend *fe);
-
-int cxd2820r_set_frontend_t(struct dvb_frontend *fe);
-
-int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status);
-
-int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber);
-
-int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe, u16 *strength);
-
-int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr);
-
-int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks);
-
-int cxd2820r_init_t(struct dvb_frontend *fe);
-
-int cxd2820r_sleep_t(struct dvb_frontend *fe);
-
-int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *s);
-
-/* cxd2820r_t2.c */
-
-int cxd2820r_get_frontend_t2(struct dvb_frontend *fe);
-
-int cxd2820r_set_frontend_t2(struct dvb_frontend *fe);
-
-int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status);
-
-int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber);
-
-int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe, u16 *strength);
-
-int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr);
-
-int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks);
-
-int cxd2820r_init_t2(struct dvb_frontend *fe);
-
-int cxd2820r_sleep_t2(struct dvb_frontend *fe);
-
-int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *s);
-
-#endif /* CXD2820R_PRIV_H */
diff --git a/drivers/media/dvb/frontends/cxd2820r_t.c b/drivers/media/dvb/frontends/cxd2820r_t.c
deleted file mode 100644
index e5dd22bc16b..00000000000
--- a/drivers/media/dvb/frontends/cxd2820r_t.c
+++ /dev/null
@@ -1,452 +0,0 @@
-/*
- * Sony CXD2820R demodulator driver
- *
- * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-
-#include "cxd2820r_priv.h"
-
-int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret, i, bw_i;
- u32 if_freq, if_ctl;
- u64 num;
- u8 buf[3], bw_param;
- u8 bw_params1[][5] = {
- { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
- { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
- { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
- };
- u8 bw_params2[][2] = {
- { 0x1f, 0xdc }, /* 6 MHz */
- { 0x12, 0xf8 }, /* 7 MHz */
- { 0x01, 0xe0 }, /* 8 MHz */
- };
- struct reg_val_mask tab[] = {
- { 0x00080, 0x00, 0xff },
- { 0x00081, 0x03, 0xff },
- { 0x00085, 0x07, 0xff },
- { 0x00088, 0x01, 0xff },
-
- { 0x00070, priv->cfg.ts_mode, 0xff },
- { 0x000cb, priv->cfg.if_agc_polarity << 6, 0x40 },
- { 0x000a5, 0x00, 0x01 },
- { 0x00082, 0x20, 0x60 },
- { 0x000c2, 0xc3, 0xff },
- { 0x0016a, 0x50, 0xff },
- { 0x00427, 0x41, 0xff },
- };
-
- dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);
-
- switch (c->bandwidth_hz) {
- case 6000000:
- bw_i = 0;
- bw_param = 2;
- break;
- case 7000000:
- bw_i = 1;
- bw_param = 1;
- break;
- case 8000000:
- bw_i = 2;
- bw_param = 0;
- break;
- default:
- return -EINVAL;
- }
-
- /* update GPIOs */
- ret = cxd2820r_gpio(fe);
- if (ret)
- goto error;
-
- /* program tuner */
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
-
- if (priv->delivery_system != SYS_DVBT) {
- for (i = 0; i < ARRAY_SIZE(tab); i++) {
- ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
- tab[i].val, tab[i].mask);
- if (ret)
- goto error;
- }
- }
-
- priv->delivery_system = SYS_DVBT;
- priv->ber_running = 0; /* tune stops BER counter */
-
- /* program IF frequency */
- if (fe->ops.tuner_ops.get_if_frequency) {
- ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
- if (ret)
- goto error;
- } else
- if_freq = 0;
-
- dbg("%s: if_freq=%d", __func__, if_freq);
-
- num = if_freq / 1000; /* Hz => kHz */
- num *= 0x1000000;
- if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
- buf[0] = ((if_ctl >> 16) & 0xff);
- buf[1] = ((if_ctl >> 8) & 0xff);
- buf[2] = ((if_ctl >> 0) & 0xff);
-
- ret = cxd2820r_wr_regs(priv, 0x000b6, buf, 3);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[bw_i], 5);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_reg_mask(priv, 0x000d7, bw_param << 6, 0xc0);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[bw_i], 2);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
- if (ret)
- goto error;
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_get_frontend_t(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret;
- u8 buf[2];
-
- ret = cxd2820r_rd_regs(priv, 0x0002f, buf, sizeof(buf));
- if (ret)
- goto error;
-
- switch ((buf[0] >> 6) & 0x03) {
- case 0:
- c->modulation = QPSK;
- break;
- case 1:
- c->modulation = QAM_16;
- break;
- case 2:
- c->modulation = QAM_64;
- break;
- }
-
- switch ((buf[1] >> 1) & 0x03) {
- case 0:
- c->transmission_mode = TRANSMISSION_MODE_2K;
- break;
- case 1:
- c->transmission_mode = TRANSMISSION_MODE_8K;
- break;
- }
-
- switch ((buf[1] >> 3) & 0x03) {
- case 0:
- c->guard_interval = GUARD_INTERVAL_1_32;
- break;
- case 1:
- c->guard_interval = GUARD_INTERVAL_1_16;
- break;
- case 2:
- c->guard_interval = GUARD_INTERVAL_1_8;
- break;
- case 3:
- c->guard_interval = GUARD_INTERVAL_1_4;
- break;
- }
-
- switch ((buf[0] >> 3) & 0x07) {
- case 0:
- c->hierarchy = HIERARCHY_NONE;
- break;
- case 1:
- c->hierarchy = HIERARCHY_1;
- break;
- case 2:
- c->hierarchy = HIERARCHY_2;
- break;
- case 3:
- c->hierarchy = HIERARCHY_4;
- break;
- }
-
- switch ((buf[0] >> 0) & 0x07) {
- case 0:
- c->code_rate_HP = FEC_1_2;
- break;
- case 1:
- c->code_rate_HP = FEC_2_3;
- break;
- case 2:
- c->code_rate_HP = FEC_3_4;
- break;
- case 3:
- c->code_rate_HP = FEC_5_6;
- break;
- case 4:
- c->code_rate_HP = FEC_7_8;
- break;
- }
-
- switch ((buf[1] >> 5) & 0x07) {
- case 0:
- c->code_rate_LP = FEC_1_2;
- break;
- case 1:
- c->code_rate_LP = FEC_2_3;
- break;
- case 2:
- c->code_rate_LP = FEC_3_4;
- break;
- case 3:
- c->code_rate_LP = FEC_5_6;
- break;
- case 4:
- c->code_rate_LP = FEC_7_8;
- break;
- }
-
- ret = cxd2820r_rd_reg(priv, 0x007c6, &buf[0]);
- if (ret)
- goto error;
-
- switch ((buf[0] >> 0) & 0x01) {
- case 0:
- c->inversion = INVERSION_OFF;
- break;
- case 1:
- c->inversion = INVERSION_ON;
- break;
- }
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[3], start_ber = 0;
- *ber = 0;
-
- if (priv->ber_running) {
- ret = cxd2820r_rd_regs(priv, 0x00076, buf, sizeof(buf));
- if (ret)
- goto error;
-
- if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) {
- *ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0];
- start_ber = 1;
- }
- } else {
- priv->ber_running = 1;
- start_ber = 1;
- }
-
- if (start_ber) {
- /* (re)start BER */
- ret = cxd2820r_wr_reg(priv, 0x00079, 0x01);
- if (ret)
- goto error;
- }
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe,
- u16 *strength)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[2];
- u16 tmp;
-
- ret = cxd2820r_rd_regs(priv, 0x00026, buf, sizeof(buf));
- if (ret)
- goto error;
-
- tmp = (buf[0] & 0x0f) << 8 | buf[1];
- tmp = ~tmp & 0x0fff;
-
- /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
- *strength = tmp * 0xffff / 0x0fff;
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[2];
- u16 tmp;
- /* report SNR in dB * 10 */
-
- ret = cxd2820r_rd_regs(priv, 0x00028, buf, sizeof(buf));
- if (ret)
- goto error;
-
- tmp = (buf[0] & 0x1f) << 8 | buf[1];
- #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
- if (tmp)
- *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
- / 100);
- else
- *snr = 0;
-
- dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp);
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks)
-{
- *ucblocks = 0;
- /* no way to read ? */
- return 0;
-}
-
-int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[4];
- *status = 0;
-
- ret = cxd2820r_rd_reg(priv, 0x00010, &buf[0]);
- if (ret)
- goto error;
-
- if ((buf[0] & 0x07) == 6) {
- ret = cxd2820r_rd_reg(priv, 0x00073, &buf[1]);
- if (ret)
- goto error;
-
- if (((buf[1] >> 3) & 0x01) == 1) {
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
- } else {
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC;
- }
- } else {
- ret = cxd2820r_rd_reg(priv, 0x00014, &buf[2]);
- if (ret)
- goto error;
-
- if ((buf[2] & 0x0f) >= 4) {
- ret = cxd2820r_rd_reg(priv, 0x00a14, &buf[3]);
- if (ret)
- goto error;
-
- if (((buf[3] >> 4) & 0x01) == 1)
- *status |= FE_HAS_SIGNAL;
- }
- }
-
- dbg("%s: lock=%*ph", __func__, 4, buf);
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_init_t(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
-
- ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
- if (ret)
- goto error;
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_sleep_t(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret, i;
- struct reg_val_mask tab[] = {
- { 0x000ff, 0x1f, 0xff },
- { 0x00085, 0x00, 0xff },
- { 0x00088, 0x01, 0xff },
- { 0x00081, 0x00, 0xff },
- { 0x00080, 0x00, 0xff },
- };
-
- dbg("%s", __func__);
-
- priv->delivery_system = SYS_UNDEFINED;
-
- for (i = 0; i < ARRAY_SIZE(tab); i++) {
- ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
- tab[i].mask);
- if (ret)
- goto error;
- }
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *s)
-{
- s->min_delay_ms = 500;
- s->step_size = fe->ops.info.frequency_stepsize * 2;
- s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
-
- return 0;
-}
diff --git a/drivers/media/dvb/frontends/cxd2820r_t2.c b/drivers/media/dvb/frontends/cxd2820r_t2.c
deleted file mode 100644
index 3a5759e0d23..00000000000
--- a/drivers/media/dvb/frontends/cxd2820r_t2.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/*
- * Sony CXD2820R demodulator driver
- *
- * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-
-#include "cxd2820r_priv.h"
-
-int cxd2820r_set_frontend_t2(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret, i, bw_i;
- u32 if_freq, if_ctl;
- u64 num;
- u8 buf[3], bw_param;
- u8 bw_params1[][5] = {
- { 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */
- { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
- { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
- { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
- };
- struct reg_val_mask tab[] = {
- { 0x00080, 0x02, 0xff },
- { 0x00081, 0x20, 0xff },
- { 0x00085, 0x07, 0xff },
- { 0x00088, 0x01, 0xff },
- { 0x02069, 0x01, 0xff },
-
- { 0x0207f, 0x2a, 0xff },
- { 0x02082, 0x0a, 0xff },
- { 0x02083, 0x0a, 0xff },
- { 0x020cb, priv->cfg.if_agc_polarity << 6, 0x40 },
- { 0x02070, priv->cfg.ts_mode, 0xff },
- { 0x020b5, priv->cfg.spec_inv << 4, 0x10 },
- { 0x02567, 0x07, 0x0f },
- { 0x02569, 0x03, 0x03 },
- { 0x02595, 0x1a, 0xff },
- { 0x02596, 0x50, 0xff },
- { 0x02a8c, 0x00, 0xff },
- { 0x02a8d, 0x34, 0xff },
- { 0x02a45, 0x06, 0x07 },
- { 0x03f10, 0x0d, 0xff },
- { 0x03f11, 0x02, 0xff },
- { 0x03f12, 0x01, 0xff },
- { 0x03f23, 0x2c, 0xff },
- { 0x03f51, 0x13, 0xff },
- { 0x03f52, 0x01, 0xff },
- { 0x03f53, 0x00, 0xff },
- { 0x027e6, 0x14, 0xff },
- { 0x02786, 0x02, 0x07 },
- { 0x02787, 0x40, 0xe0 },
- { 0x027ef, 0x10, 0x18 },
- };
-
- dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);
-
- switch (c->bandwidth_hz) {
- case 5000000:
- bw_i = 0;
- bw_param = 3;
- break;
- case 6000000:
- bw_i = 1;
- bw_param = 2;
- break;
- case 7000000:
- bw_i = 2;
- bw_param = 1;
- break;
- case 8000000:
- bw_i = 3;
- bw_param = 0;
- break;
- default:
- return -EINVAL;
- }
-
- /* update GPIOs */
- ret = cxd2820r_gpio(fe);
- if (ret)
- goto error;
-
- /* program tuner */
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
-
- if (priv->delivery_system != SYS_DVBT2) {
- for (i = 0; i < ARRAY_SIZE(tab); i++) {
- ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
- tab[i].val, tab[i].mask);
- if (ret)
- goto error;
- }
- }
-
- priv->delivery_system = SYS_DVBT2;
-
- /* program IF frequency */
- if (fe->ops.tuner_ops.get_if_frequency) {
- ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
- if (ret)
- goto error;
- } else
- if_freq = 0;
-
- dbg("%s: if_freq=%d", __func__, if_freq);
-
- num = if_freq / 1000; /* Hz => kHz */
- num *= 0x1000000;
- if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
- buf[0] = ((if_ctl >> 16) & 0xff);
- buf[1] = ((if_ctl >> 8) & 0xff);
- buf[2] = ((if_ctl >> 0) & 0xff);
-
- ret = cxd2820r_wr_regs(priv, 0x020b6, buf, 3);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[bw_i], 5);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_reg_mask(priv, 0x020d7, bw_param << 6, 0xc0);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
- if (ret)
- goto error;
-
- ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
- if (ret)
- goto error;
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-
-}
-
-int cxd2820r_get_frontend_t2(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret;
- u8 buf[2];
-
- ret = cxd2820r_rd_regs(priv, 0x0205c, buf, 2);
- if (ret)
- goto error;
-
- switch ((buf[0] >> 0) & 0x07) {
- case 0:
- c->transmission_mode = TRANSMISSION_MODE_2K;
- break;
- case 1:
- c->transmission_mode = TRANSMISSION_MODE_8K;
- break;
- case 2:
- c->transmission_mode = TRANSMISSION_MODE_4K;
- break;
- case 3:
- c->transmission_mode = TRANSMISSION_MODE_1K;
- break;
- case 4:
- c->transmission_mode = TRANSMISSION_MODE_16K;
- break;
- case 5:
- c->transmission_mode = TRANSMISSION_MODE_32K;
- break;
- }
-
- switch ((buf[1] >> 4) & 0x07) {
- case 0:
- c->guard_interval = GUARD_INTERVAL_1_32;
- break;
- case 1:
- c->guard_interval = GUARD_INTERVAL_1_16;
- break;
- case 2:
- c->guard_interval = GUARD_INTERVAL_1_8;
- break;
- case 3:
- c->guard_interval = GUARD_INTERVAL_1_4;
- break;
- case 4:
- c->guard_interval = GUARD_INTERVAL_1_128;
- break;
- case 5:
- c->guard_interval = GUARD_INTERVAL_19_128;
- break;
- case 6:
- c->guard_interval = GUARD_INTERVAL_19_256;
- break;
- }
-
- ret = cxd2820r_rd_regs(priv, 0x0225b, buf, 2);
- if (ret)
- goto error;
-
- switch ((buf[0] >> 0) & 0x07) {
- case 0:
- c->fec_inner = FEC_1_2;
- break;
- case 1:
- c->fec_inner = FEC_3_5;
- break;
- case 2:
- c->fec_inner = FEC_2_3;
- break;
- case 3:
- c->fec_inner = FEC_3_4;
- break;
- case 4:
- c->fec_inner = FEC_4_5;
- break;
- case 5:
- c->fec_inner = FEC_5_6;
- break;
- }
-
- switch ((buf[1] >> 0) & 0x07) {
- case 0:
- c->modulation = QPSK;
- break;
- case 1:
- c->modulation = QAM_16;
- break;
- case 2:
- c->modulation = QAM_64;
- break;
- case 3:
- c->modulation = QAM_256;
- break;
- }
-
- ret = cxd2820r_rd_reg(priv, 0x020b5, &buf[0]);
- if (ret)
- goto error;
-
- switch ((buf[0] >> 4) & 0x01) {
- case 0:
- c->inversion = INVERSION_OFF;
- break;
- case 1:
- c->inversion = INVERSION_ON;
- break;
- }
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[1];
- *status = 0;
-
- ret = cxd2820r_rd_reg(priv, 0x02010 , &buf[0]);
- if (ret)
- goto error;
-
- if ((buf[0] & 0x07) == 6) {
- if (((buf[0] >> 5) & 0x01) == 1) {
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
- } else {
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC;
- }
- }
-
- dbg("%s: lock=%02x", __func__, buf[0]);
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[4];
- unsigned int errbits;
- *ber = 0;
- /* FIXME: correct calculation */
-
- ret = cxd2820r_rd_regs(priv, 0x02039, buf, sizeof(buf));
- if (ret)
- goto error;
-
- if ((buf[0] >> 4) & 0x01) {
- errbits = (buf[0] & 0x0f) << 24 | buf[1] << 16 |
- buf[2] << 8 | buf[3];
-
- if (errbits)
- *ber = errbits * 64 / 16588800;
- }
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe,
- u16 *strength)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[2];
- u16 tmp;
-
- ret = cxd2820r_rd_regs(priv, 0x02026, buf, sizeof(buf));
- if (ret)
- goto error;
-
- tmp = (buf[0] & 0x0f) << 8 | buf[1];
- tmp = ~tmp & 0x0fff;
-
- /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
- *strength = tmp * 0xffff / 0x0fff;
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret;
- u8 buf[2];
- u16 tmp;
- /* report SNR in dB * 10 */
-
- ret = cxd2820r_rd_regs(priv, 0x02028, buf, sizeof(buf));
- if (ret)
- goto error;
-
- tmp = (buf[0] & 0x0f) << 8 | buf[1];
- #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
- if (tmp)
- *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
- / 100);
- else
- *snr = 0;
-
- dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp);
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks)
-{
- *ucblocks = 0;
- /* no way to read ? */
- return 0;
-}
-
-int cxd2820r_sleep_t2(struct dvb_frontend *fe)
-{
- struct cxd2820r_priv *priv = fe->demodulator_priv;
- int ret, i;
- struct reg_val_mask tab[] = {
- { 0x000ff, 0x1f, 0xff },
- { 0x00085, 0x00, 0xff },
- { 0x00088, 0x01, 0xff },
- { 0x02069, 0x00, 0xff },
- { 0x00081, 0x00, 0xff },
- { 0x00080, 0x00, 0xff },
- };
-
- dbg("%s", __func__);
-
- for (i = 0; i < ARRAY_SIZE(tab); i++) {
- ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
- tab[i].mask);
- if (ret)
- goto error;
- }
-
- priv->delivery_system = SYS_UNDEFINED;
-
- return ret;
-error:
- dbg("%s: failed:%d", __func__, ret);
- return ret;
-}
-
-int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *s)
-{
- s->min_delay_ms = 1500;
- s->step_size = fe->ops.info.frequency_stepsize * 2;
- s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
-
- return 0;
-}
diff --git a/drivers/media/dvb/frontends/dib0070.c b/drivers/media/dvb/frontends/dib0070.c
deleted file mode 100644
index 3b024bfe980..00000000000
--- a/drivers/media/dvb/frontends/dib0070.c
+++ /dev/null
@@ -1,780 +0,0 @@
-/*
- * Linux-DVB Driver for DiBcom's DiB0070 base-band RF Tuner.
- *
- * Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- * This code is more or less generated from another driver, please
- * excuse some codingstyle oddities.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/i2c.h>
-#include <linux/mutex.h>
-
-#include "dvb_frontend.h"
-
-#include "dib0070.h"
-#include "dibx000_common.h"
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
-
-#define dprintk(args...) do { \
- if (debug) { \
- printk(KERN_DEBUG "DiB0070: "); \
- printk(args); \
- printk("\n"); \
- } \
-} while (0)
-
-#define DIB0070_P1D 0x00
-#define DIB0070_P1F 0x01
-#define DIB0070_P1G 0x03
-#define DIB0070S_P1A 0x02
-
-struct dib0070_state {
- struct i2c_adapter *i2c;
- struct dvb_frontend *fe;
- const struct dib0070_config *cfg;
- u16 wbd_ff_offset;
- u8 revision;
-
- enum frontend_tune_state tune_state;
- u32 current_rf;
-
- /* for the captrim binary search */
- s8 step;
- u16 adc_diff;
-
- s8 captrim;
- s8 fcaptrim;
- u16 lo4;
-
- const struct dib0070_tuning *current_tune_table_index;
- const struct dib0070_lna_match *lna_match;
-
- u8 wbd_gain_current;
- u16 wbd_offset_3_3[2];
-
- /* for the I2C transfer */
- struct i2c_msg msg[2];
- u8 i2c_write_buffer[3];
- u8 i2c_read_buffer[2];
- struct mutex i2c_buffer_lock;
-};
-
-static u16 dib0070_read_reg(struct dib0070_state *state, u8 reg)
-{
- u16 ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return 0;
- }
-
- state->i2c_write_buffer[0] = reg;
-
- memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
- state->msg[0].addr = state->cfg->i2c_address;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 1;
- state->msg[1].addr = state->cfg->i2c_address;
- state->msg[1].flags = I2C_M_RD;
- state->msg[1].buf = state->i2c_read_buffer;
- state->msg[1].len = 2;
-
- if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
- printk(KERN_WARNING "DiB0070 I2C read failed\n");
- ret = 0;
- } else
- ret = (state->i2c_read_buffer[0] << 8)
- | state->i2c_read_buffer[1];
-
- mutex_unlock(&state->i2c_buffer_lock);
- return ret;
-}
-
-static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
-{
- int ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
- state->i2c_write_buffer[0] = reg;
- state->i2c_write_buffer[1] = val >> 8;
- state->i2c_write_buffer[2] = val & 0xff;
-
- memset(state->msg, 0, sizeof(struct i2c_msg));
- state->msg[0].addr = state->cfg->i2c_address;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 3;
-
- if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
- printk(KERN_WARNING "DiB0070 I2C write failed\n");
- ret = -EREMOTEIO;
- } else
- ret = 0;
-
- mutex_unlock(&state->i2c_buffer_lock);
- return ret;
-}
-
-#define HARD_RESET(state) do { \
- state->cfg->sleep(state->fe, 0); \
- if (state->cfg->reset) { \
- state->cfg->reset(state->fe,1); msleep(10); \
- state->cfg->reset(state->fe,0); msleep(10); \
- } \
-} while (0)
-
-static int dib0070_set_bandwidth(struct dvb_frontend *fe)
-{
- struct dib0070_state *state = fe->tuner_priv;
- u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
-
- if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 7000)
- tmp |= (0 << 14);
- else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 6000)
- tmp |= (1 << 14);
- else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 5000)
- tmp |= (2 << 14);
- else
- tmp |= (3 << 14);
-
- dib0070_write_reg(state, 0x02, tmp);
-
- /* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
- if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
- u16 value = dib0070_read_reg(state, 0x17);
-
- dib0070_write_reg(state, 0x17, value & 0xfffc);
- tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
- dib0070_write_reg(state, 0x01, tmp | (60 << 9));
-
- dib0070_write_reg(state, 0x17, value);
- }
- return 0;
-}
-
-static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state *tune_state)
-{
- int8_t step_sign;
- u16 adc;
- int ret = 0;
-
- if (*tune_state == CT_TUNER_STEP_0) {
-
- dib0070_write_reg(state, 0x0f, 0xed10);
- dib0070_write_reg(state, 0x17, 0x0034);
-
- dib0070_write_reg(state, 0x18, 0x0032);
- state->step = state->captrim = state->fcaptrim = 64;
- state->adc_diff = 3000;
- ret = 20;
-
- *tune_state = CT_TUNER_STEP_1;
- } else if (*tune_state == CT_TUNER_STEP_1) {
- state->step /= 2;
- dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
- ret = 15;
-
- *tune_state = CT_TUNER_STEP_2;
- } else if (*tune_state == CT_TUNER_STEP_2) {
-
- adc = dib0070_read_reg(state, 0x19);
-
- dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024);
-
- if (adc >= 400) {
- adc -= 400;
- step_sign = -1;
- } else {
- adc = 400 - adc;
- step_sign = 1;
- }
-
- if (adc < state->adc_diff) {
- dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff);
- state->adc_diff = adc;
- state->fcaptrim = state->captrim;
-
-
-
- }
- state->captrim += (step_sign * state->step);
-
- if (state->step >= 1)
- *tune_state = CT_TUNER_STEP_1;
- else
- *tune_state = CT_TUNER_STEP_3;
-
- } else if (*tune_state == CT_TUNER_STEP_3) {
- dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim);
- dib0070_write_reg(state, 0x18, 0x07ff);
- *tune_state = CT_TUNER_STEP_4;
- }
-
- return ret;
-}
-
-static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt)
-{
- struct dib0070_state *state = fe->tuner_priv;
- u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
- dprintk("CTRL_LO5: 0x%x", lo5);
- return dib0070_write_reg(state, 0x15, lo5);
-}
-
-void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
-{
- struct dib0070_state *state = fe->tuner_priv;
-
- if (open) {
- dib0070_write_reg(state, 0x1b, 0xff00);
- dib0070_write_reg(state, 0x1a, 0x0000);
- } else {
- dib0070_write_reg(state, 0x1b, 0x4112);
- if (state->cfg->vga_filter != 0) {
- dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
- dprintk("vga filter register is set to %x", state->cfg->vga_filter);
- } else
- dib0070_write_reg(state, 0x1a, 0x0009);
- }
-}
-
-EXPORT_SYMBOL(dib0070_ctrl_agc_filter);
-struct dib0070_tuning {
- u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
- u8 switch_trim;
- u8 vco_band;
- u8 hfdiv;
- u8 vco_multi;
- u8 presc;
- u8 wbdmux;
- u16 tuner_enable;
-};
-
-struct dib0070_lna_match {
- u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
- u8 lna_band;
-};
-
-static const struct dib0070_tuning dib0070s_tuning_table[] = {
- { 570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800 }, /* UHF */
- { 700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800 },
- { 863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800 },
- { 1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND */
- { 1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
- { 2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
- { 0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000 }, /* SBAND */
-};
-
-static const struct dib0070_tuning dib0070_tuning_table[] = {
- { 115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000 }, /* FM below 92MHz cannot be tuned */
- { 179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000 }, /* VHF */
- { 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
- { 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
- { 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
- { 699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800 },
- { 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 },
- { 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
-};
-
-static const struct dib0070_lna_match dib0070_lna_flip_chip[] = {
- { 180000, 0 }, /* VHF */
- { 188000, 1 },
- { 196400, 2 },
- { 250000, 3 },
- { 550000, 0 }, /* UHF */
- { 590000, 1 },
- { 666000, 3 },
- { 864000, 5 },
- { 1500000, 0 }, /* LBAND or everything higher than UHF */
- { 1600000, 1 },
- { 2000000, 3 },
- { 0xffffffff, 7 },
-};
-
-static const struct dib0070_lna_match dib0070_lna[] = {
- { 180000, 0 }, /* VHF */
- { 188000, 1 },
- { 196400, 2 },
- { 250000, 3 },
- { 550000, 2 }, /* UHF */
- { 650000, 3 },
- { 750000, 5 },
- { 850000, 6 },
- { 864000, 7 },
- { 1500000, 0 }, /* LBAND or everything higher than UHF */
- { 1600000, 1 },
- { 2000000, 3 },
- { 0xffffffff, 7 },
-};
-
-#define LPF 100
-static int dib0070_tune_digital(struct dvb_frontend *fe)
-{
- struct dib0070_state *state = fe->tuner_priv;
-
- const struct dib0070_tuning *tune;
- const struct dib0070_lna_match *lna_match;
-
- enum frontend_tune_state *tune_state = &state->tune_state;
- int ret = 10; /* 1ms is the default delay most of the time */
-
- u8 band = (u8)BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency/1000);
- u32 freq = fe->dtv_property_cache.frequency/1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
-
-#ifdef CONFIG_SYS_ISDBT
- if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
- if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2)
- && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
- || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
- && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
- || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
- && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
- freq += 850;
-#endif
- if (state->current_rf != freq) {
-
- switch (state->revision) {
- case DIB0070S_P1A:
- tune = dib0070s_tuning_table;
- lna_match = dib0070_lna;
- break;
- default:
- tune = dib0070_tuning_table;
- if (state->cfg->flip_chip)
- lna_match = dib0070_lna_flip_chip;
- else
- lna_match = dib0070_lna;
- break;
- }
- while (freq > tune->max_freq) /* find the right one */
- tune++;
- while (freq > lna_match->max_freq) /* find the right one */
- lna_match++;
-
- state->current_tune_table_index = tune;
- state->lna_match = lna_match;
- }
-
- if (*tune_state == CT_TUNER_START) {
- dprintk("Tuning for Band: %hd (%d kHz)", band, freq);
- if (state->current_rf != freq) {
- u8 REFDIV;
- u32 FBDiv, Rest, FREF, VCOF_kHz;
- u8 Den;
-
- state->current_rf = freq;
- state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
-
-
- dib0070_write_reg(state, 0x17, 0x30);
-
-
- VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
-
- switch (band) {
- case BAND_VHF:
- REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
- break;
- case BAND_FM:
- REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
- break;
- default:
- REFDIV = (u8) (state->cfg->clock_khz / 10000);
- break;
- }
- FREF = state->cfg->clock_khz / REFDIV;
-
-
-
- switch (state->revision) {
- case DIB0070S_P1A:
- FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
- Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
- break;
-
- case DIB0070_P1G:
- case DIB0070_P1F:
- default:
- FBDiv = (freq / (FREF / 2));
- Rest = 2 * freq - FBDiv * FREF;
- break;
- }
-
- if (Rest < LPF)
- Rest = 0;
- else if (Rest < 2 * LPF)
- Rest = 2 * LPF;
- else if (Rest > (FREF - LPF)) {
- Rest = 0;
- FBDiv += 1;
- } else if (Rest > (FREF - 2 * LPF))
- Rest = FREF - 2 * LPF;
- Rest = (Rest * 6528) / (FREF / 10);
-
- Den = 1;
- if (Rest > 0) {
- state->lo4 |= (1 << 14) | (1 << 12);
- Den = 255;
- }
-
-
- dib0070_write_reg(state, 0x11, (u16)FBDiv);
- dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
- dib0070_write_reg(state, 0x13, (u16) Rest);
-
- if (state->revision == DIB0070S_P1A) {
-
- if (band == BAND_SBAND) {
- dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
- dib0070_write_reg(state, 0x1d, 0xFFFF);
- } else
- dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
- }
-
- dib0070_write_reg(state, 0x20,
- 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
-
- dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF);
- dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest);
- dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
- dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv);
- dprintk("VCO = %hd", state->current_tune_table_index->vco_band);
- dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq);
-
- *tune_state = CT_TUNER_STEP_0;
- } else { /* we are already tuned to this frequency - the configuration is correct */
- ret = 50; /* wakeup time */
- *tune_state = CT_TUNER_STEP_5;
- }
- } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
-
- ret = dib0070_captrim(state, tune_state);
-
- } else if (*tune_state == CT_TUNER_STEP_4) {
- const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
- if (tmp != NULL) {
- while (freq/1000 > tmp->freq) /* find the right one */
- tmp++;
- dib0070_write_reg(state, 0x0f,
- (0 << 15) | (1 << 14) | (3 << 12)
- | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7)
- | (state->current_tune_table_index->wbdmux << 0));
- state->wbd_gain_current = tmp->wbd_gain_val;
- } else {
- dib0070_write_reg(state, 0x0f,
- (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index->
- wbdmux << 0));
- state->wbd_gain_current = 6;
- }
-
- dib0070_write_reg(state, 0x06, 0x3fff);
- dib0070_write_reg(state, 0x07,
- (state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0));
- dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
- dib0070_write_reg(state, 0x0d, 0x0d80);
-
-
- dib0070_write_reg(state, 0x18, 0x07ff);
- dib0070_write_reg(state, 0x17, 0x0033);
-
-
- *tune_state = CT_TUNER_STEP_5;
- } else if (*tune_state == CT_TUNER_STEP_5) {
- dib0070_set_bandwidth(fe);
- *tune_state = CT_TUNER_STOP;
- } else {
- ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
- }
- return ret;
-}
-
-
-static int dib0070_tune(struct dvb_frontend *fe)
-{
- struct dib0070_state *state = fe->tuner_priv;
- uint32_t ret;
-
- state->tune_state = CT_TUNER_START;
-
- do {
- ret = dib0070_tune_digital(fe);
- if (ret != FE_CALLBACK_TIME_NEVER)
- msleep(ret/10);
- else
- break;
- } while (state->tune_state != CT_TUNER_STOP);
-
- return 0;
-}
-
-static int dib0070_wakeup(struct dvb_frontend *fe)
-{
- struct dib0070_state *state = fe->tuner_priv;
- if (state->cfg->sleep)
- state->cfg->sleep(fe, 0);
- return 0;
-}
-
-static int dib0070_sleep(struct dvb_frontend *fe)
-{
- struct dib0070_state *state = fe->tuner_priv;
- if (state->cfg->sleep)
- state->cfg->sleep(fe, 1);
- return 0;
-}
-
-u8 dib0070_get_rf_output(struct dvb_frontend *fe)
-{
- struct dib0070_state *state = fe->tuner_priv;
- return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
-}
-EXPORT_SYMBOL(dib0070_get_rf_output);
-
-int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no)
-{
- struct dib0070_state *state = fe->tuner_priv;
- u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
- if (no > 3)
- no = 3;
- if (no < 1)
- no = 1;
- return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
-}
-EXPORT_SYMBOL(dib0070_set_rf_output);
-
-static const u16 dib0070_p1f_defaults[] =
-
-{
- 7, 0x02,
- 0x0008,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0002,
- 0x0100,
-
- 3, 0x0d,
- 0x0d80,
- 0x0001,
- 0x0000,
-
- 4, 0x11,
- 0x0000,
- 0x0103,
- 0x0000,
- 0x0000,
-
- 3, 0x16,
- 0x0004 | 0x0040,
- 0x0030,
- 0x07ff,
-
- 6, 0x1b,
- 0x4112,
- 0xff00,
- 0xc07f,
- 0x0000,
- 0x0180,
- 0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
-
- 0,
-};
-
-static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain)
-{
- u16 tuner_en = dib0070_read_reg(state, 0x20);
- u16 offset;
-
- dib0070_write_reg(state, 0x18, 0x07ff);
- dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
- dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
- msleep(9);
- offset = dib0070_read_reg(state, 0x19);
- dib0070_write_reg(state, 0x20, tuner_en);
- return offset;
-}
-
-static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
-{
- u8 gain;
- for (gain = 6; gain < 8; gain++) {
- state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
- dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]);
- }
-}
-
-u16 dib0070_wbd_offset(struct dvb_frontend *fe)
-{
- struct dib0070_state *state = fe->tuner_priv;
- const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
- u32 freq = fe->dtv_property_cache.frequency/1000;
-
- if (tmp != NULL) {
- while (freq/1000 > tmp->freq) /* find the right one */
- tmp++;
- state->wbd_gain_current = tmp->wbd_gain_val;
- } else
- state->wbd_gain_current = 6;
-
- return state->wbd_offset_3_3[state->wbd_gain_current - 6];
-}
-EXPORT_SYMBOL(dib0070_wbd_offset);
-
-#define pgm_read_word(w) (*w)
-static int dib0070_reset(struct dvb_frontend *fe)
-{
- struct dib0070_state *state = fe->tuner_priv;
- u16 l, r, *n;
-
- HARD_RESET(state);
-
-
-#ifndef FORCE_SBAND_TUNER
- if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
- state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
- else
-#else
-#warning forcing SBAND
-#endif
- state->revision = DIB0070S_P1A;
-
- /* P1F or not */
- dprintk("Revision: %x", state->revision);
-
- if (state->revision == DIB0070_P1D) {
- dprintk("Error: this driver is not to be used meant for P1D or earlier");
- return -EINVAL;
- }
-
- n = (u16 *) dib0070_p1f_defaults;
- l = pgm_read_word(n++);
- while (l) {
- r = pgm_read_word(n++);
- do {
- dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
- r++;
- } while (--l);
- l = pgm_read_word(n++);
- }
-
- if (state->cfg->force_crystal_mode != 0)
- r = state->cfg->force_crystal_mode;
- else if (state->cfg->clock_khz >= 24000)
- r = 1;
- else
- r = 2;
-
-
- r |= state->cfg->osc_buffer_state << 3;
-
- dib0070_write_reg(state, 0x10, r);
- dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5));
-
- if (state->cfg->invert_iq) {
- r = dib0070_read_reg(state, 0x02) & 0xffdf;
- dib0070_write_reg(state, 0x02, r | (1 << 5));
- }
-
- if (state->revision == DIB0070S_P1A)
- dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
- else
- dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump, state->cfg->enable_third_order_filter);
-
- dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
-
- dib0070_wbd_offset_calibration(state);
-
- return 0;
-}
-
-static int dib0070_get_frequency(struct dvb_frontend *fe, u32 *frequency)
-{
- struct dib0070_state *state = fe->tuner_priv;
-
- *frequency = 1000 * state->current_rf;
- return 0;
-}
-
-static int dib0070_release(struct dvb_frontend *fe)
-{
- kfree(fe->tuner_priv);
- fe->tuner_priv = NULL;
- return 0;
-}
-
-static const struct dvb_tuner_ops dib0070_ops = {
- .info = {
- .name = "DiBcom DiB0070",
- .frequency_min = 45000000,
- .frequency_max = 860000000,
- .frequency_step = 1000,
- },
- .release = dib0070_release,
-
- .init = dib0070_wakeup,
- .sleep = dib0070_sleep,
- .set_params = dib0070_tune,
-
- .get_frequency = dib0070_get_frequency,
-// .get_bandwidth = dib0070_get_bandwidth
-};
-
-struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
-{
- struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
- if (state == NULL)
- return NULL;
-
- state->cfg = cfg;
- state->i2c = i2c;
- state->fe = fe;
- mutex_init(&state->i2c_buffer_lock);
- fe->tuner_priv = state;
-
- if (dib0070_reset(fe) != 0)
- goto free_mem;
-
- printk(KERN_INFO "DiB0070: successfully identified\n");
- memcpy(&fe->ops.tuner_ops, &dib0070_ops, sizeof(struct dvb_tuner_ops));
-
- fe->tuner_priv = state;
- return fe;
-
-free_mem:
- kfree(state);
- fe->tuner_priv = NULL;
- return NULL;
-}
-EXPORT_SYMBOL(dib0070_attach);
-
-MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
-MODULE_DESCRIPTION("Driver for the DiBcom 0070 base-band RF Tuner");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib0070.h b/drivers/media/dvb/frontends/dib0070.h
deleted file mode 100644
index 45c31fae396..00000000000
--- a/drivers/media/dvb/frontends/dib0070.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Linux-DVB Driver for DiBcom's DiB0070 base-band RF Tuner.
- *
- * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- */
-#ifndef DIB0070_H
-#define DIB0070_H
-
-struct dvb_frontend;
-struct i2c_adapter;
-
-#define DEFAULT_DIB0070_I2C_ADDRESS 0x60
-
-struct dib0070_wbd_gain_cfg {
- u16 freq;
- u16 wbd_gain_val;
-};
-
-struct dib0070_config {
- u8 i2c_address;
-
- /* tuner pins controlled externally */
- int (*reset) (struct dvb_frontend *, int);
- int (*sleep) (struct dvb_frontend *, int);
-
- /* offset in kHz */
- int freq_offset_khz_uhf;
- int freq_offset_khz_vhf;
-
- u8 osc_buffer_state; /* 0= normal, 1= tri-state */
- u32 clock_khz;
- u8 clock_pad_drive; /* (Drive + 1) * 2mA */
-
- u8 invert_iq; /* invert Q - in case I or Q is inverted on the board */
-
- u8 force_crystal_mode; /* if == 0 -> decision is made in the driver default: <24 -> 2, >=24 -> 1 */
-
- u8 flip_chip;
- u8 enable_third_order_filter;
- u8 charge_pump;
-
- const struct dib0070_wbd_gain_cfg *wbd_gain;
-
- u8 vga_filter;
-};
-
-#if defined(CONFIG_DVB_TUNER_DIB0070) || (defined(CONFIG_DVB_TUNER_DIB0070_MODULE) && defined(MODULE))
-extern struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg);
-extern u16 dib0070_wbd_offset(struct dvb_frontend *);
-extern void dib0070_ctrl_agc_filter(struct dvb_frontend *, u8 open);
-extern u8 dib0070_get_rf_output(struct dvb_frontend *fe);
-extern int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no);
-#else
-static inline struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline u16 dib0070_wbd_offset(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return 0;
-}
-
-static inline void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-}
-#endif
-
-#endif
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
deleted file mode 100644
index d9fe60b4be4..00000000000
--- a/drivers/media/dvb/frontends/dib0090.c
+++ /dev/null
@@ -1,2686 +0,0 @@
-/*
- * Linux-DVB Driver for DiBcom's DiB0090 base-band RF Tuner.
- *
- * Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- * This code is more or less generated from another driver, please
- * excuse some codingstyle oddities.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/i2c.h>
-#include <linux/mutex.h>
-
-#include "dvb_frontend.h"
-
-#include "dib0090.h"
-#include "dibx000_common.h"
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
-
-#define dprintk(args...) do { \
- if (debug) { \
- printk(KERN_DEBUG "DiB0090: "); \
- printk(args); \
- printk("\n"); \
- } \
-} while (0)
-
-#define CONFIG_SYS_DVBT
-#define CONFIG_SYS_ISDBT
-#define CONFIG_BAND_CBAND
-#define CONFIG_BAND_VHF
-#define CONFIG_BAND_UHF
-#define CONFIG_DIB0090_USE_PWM_AGC
-
-#define EN_LNA0 0x8000
-#define EN_LNA1 0x4000
-#define EN_LNA2 0x2000
-#define EN_LNA3 0x1000
-#define EN_MIX0 0x0800
-#define EN_MIX1 0x0400
-#define EN_MIX2 0x0200
-#define EN_MIX3 0x0100
-#define EN_IQADC 0x0040
-#define EN_PLL 0x0020
-#define EN_TX 0x0010
-#define EN_BB 0x0008
-#define EN_LO 0x0004
-#define EN_BIAS 0x0001
-
-#define EN_IQANA 0x0002
-#define EN_DIGCLK 0x0080 /* not in the 0x24 reg, only in 0x1b */
-#define EN_CRYSTAL 0x0002
-
-#define EN_UHF 0x22E9
-#define EN_VHF 0x44E9
-#define EN_LBD 0x11E9
-#define EN_SBD 0x44E9
-#define EN_CAB 0x88E9
-
-/* Calibration defines */
-#define DC_CAL 0x1
-#define WBD_CAL 0x2
-#define TEMP_CAL 0x4
-#define CAPTRIM_CAL 0x8
-
-#define KROSUS_PLL_LOCKED 0x800
-#define KROSUS 0x2
-
-/* Use those defines to identify SOC version */
-#define SOC 0x02
-#define SOC_7090_P1G_11R1 0x82
-#define SOC_7090_P1G_21R1 0x8a
-#define SOC_8090_P1G_11R1 0x86
-#define SOC_8090_P1G_21R1 0x8e
-
-/* else use thos ones to check */
-#define P1A_B 0x0
-#define P1C 0x1
-#define P1D_E_F 0x3
-#define P1G 0x7
-#define P1G_21R2 0xf
-
-#define MP001 0x1 /* Single 9090/8096 */
-#define MP005 0x4 /* Single Sband */
-#define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
-#define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
-
-#define pgm_read_word(w) (*w)
-
-struct dc_calibration;
-
-struct dib0090_tuning {
- u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
- u8 switch_trim;
- u8 lna_tune;
- u16 lna_bias;
- u16 v2i;
- u16 mix;
- u16 load;
- u16 tuner_enable;
-};
-
-struct dib0090_pll {
- u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
- u8 vco_band;
- u8 hfdiv_code;
- u8 hfdiv;
- u8 topresc;
-};
-
-struct dib0090_identity {
- u8 version;
- u8 product;
- u8 p1g;
- u8 in_soc;
-};
-
-struct dib0090_state {
- struct i2c_adapter *i2c;
- struct dvb_frontend *fe;
- const struct dib0090_config *config;
-
- u8 current_band;
- enum frontend_tune_state tune_state;
- u32 current_rf;
-
- u16 wbd_offset;
- s16 wbd_target; /* in dB */
-
- s16 rf_gain_limit; /* take-over-point: where to split between bb and rf gain */
- s16 current_gain; /* keeps the currently programmed gain */
- u8 agc_step; /* new binary search */
-
- u16 gain[2]; /* for channel monitoring */
-
- const u16 *rf_ramp;
- const u16 *bb_ramp;
-
- /* for the software AGC ramps */
- u16 bb_1_def;
- u16 rf_lt_def;
- u16 gain_reg[4];
-
- /* for the captrim/dc-offset search */
- s8 step;
- s16 adc_diff;
- s16 min_adc_diff;
-
- s8 captrim;
- s8 fcaptrim;
-
- const struct dc_calibration *dc;
- u16 bb6, bb7;
-
- const struct dib0090_tuning *current_tune_table_index;
- const struct dib0090_pll *current_pll_table_index;
-
- u8 tuner_is_tuned;
- u8 agc_freeze;
-
- struct dib0090_identity identity;
-
- u32 rf_request;
- u8 current_standard;
-
- u8 calibrate;
- u32 rest;
- u16 bias;
- s16 temperature;
-
- u8 wbd_calibration_gain;
- const struct dib0090_wbd_slope *current_wbd_table;
- u16 wbdmux;
-
- /* for the I2C transfer */
- struct i2c_msg msg[2];
- u8 i2c_write_buffer[3];
- u8 i2c_read_buffer[2];
- struct mutex i2c_buffer_lock;
-};
-
-struct dib0090_fw_state {
- struct i2c_adapter *i2c;
- struct dvb_frontend *fe;
- struct dib0090_identity identity;
- const struct dib0090_config *config;
-
- /* for the I2C transfer */
- struct i2c_msg msg;
- u8 i2c_write_buffer[2];
- u8 i2c_read_buffer[2];
- struct mutex i2c_buffer_lock;
-};
-
-static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
-{
- u16 ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return 0;
- }
-
- state->i2c_write_buffer[0] = reg;
-
- memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
- state->msg[0].addr = state->config->i2c_address;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 1;
- state->msg[1].addr = state->config->i2c_address;
- state->msg[1].flags = I2C_M_RD;
- state->msg[1].buf = state->i2c_read_buffer;
- state->msg[1].len = 2;
-
- if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
- printk(KERN_WARNING "DiB0090 I2C read failed\n");
- ret = 0;
- } else
- ret = (state->i2c_read_buffer[0] << 8)
- | state->i2c_read_buffer[1];
-
- mutex_unlock(&state->i2c_buffer_lock);
- return ret;
-}
-
-static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
-{
- int ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
-
- state->i2c_write_buffer[0] = reg & 0xff;
- state->i2c_write_buffer[1] = val >> 8;
- state->i2c_write_buffer[2] = val & 0xff;
-
- memset(state->msg, 0, sizeof(struct i2c_msg));
- state->msg[0].addr = state->config->i2c_address;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 3;
-
- if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
- printk(KERN_WARNING "DiB0090 I2C write failed\n");
- ret = -EREMOTEIO;
- } else
- ret = 0;
-
- mutex_unlock(&state->i2c_buffer_lock);
- return ret;
-}
-
-static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
-{
- u16 ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return 0;
- }
-
- state->i2c_write_buffer[0] = reg;
-
- memset(&state->msg, 0, sizeof(struct i2c_msg));
- state->msg.addr = reg;
- state->msg.flags = I2C_M_RD;
- state->msg.buf = state->i2c_read_buffer;
- state->msg.len = 2;
- if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {
- printk(KERN_WARNING "DiB0090 I2C read failed\n");
- ret = 0;
- } else
- ret = (state->i2c_read_buffer[0] << 8)
- | state->i2c_read_buffer[1];
-
- mutex_unlock(&state->i2c_buffer_lock);
- return ret;
-}
-
-static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
-{
- int ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
-
- state->i2c_write_buffer[0] = val >> 8;
- state->i2c_write_buffer[1] = val & 0xff;
-
- memset(&state->msg, 0, sizeof(struct i2c_msg));
- state->msg.addr = reg;
- state->msg.flags = 0;
- state->msg.buf = state->i2c_write_buffer;
- state->msg.len = 2;
- if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {
- printk(KERN_WARNING "DiB0090 I2C write failed\n");
- ret = -EREMOTEIO;
- } else
- ret = 0;
-
- mutex_unlock(&state->i2c_buffer_lock);
- return ret;
-}
-
-#define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); msleep(10); } } while (0)
-#define ADC_TARGET -220
-#define GAIN_ALPHA 5
-#define WBD_ALPHA 6
-#define LPF 100
-static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, u8 c)
-{
- do {
- dib0090_write_reg(state, r++, *b++);
- } while (--c);
-}
-
-static int dib0090_identify(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- u16 v;
- struct dib0090_identity *identity = &state->identity;
-
- v = dib0090_read_reg(state, 0x1a);
-
- identity->p1g = 0;
- identity->in_soc = 0;
-
- dprintk("Tuner identification (Version = 0x%04x)", v);
-
- /* without PLL lock info */
- v &= ~KROSUS_PLL_LOCKED;
-
- identity->version = v & 0xff;
- identity->product = (v >> 8) & 0xf;
-
- if (identity->product != KROSUS)
- goto identification_error;
-
- if ((identity->version & 0x3) == SOC) {
- identity->in_soc = 1;
- switch (identity->version) {
- case SOC_8090_P1G_11R1:
- dprintk("SOC 8090 P1-G11R1 Has been detected");
- identity->p1g = 1;
- break;
- case SOC_8090_P1G_21R1:
- dprintk("SOC 8090 P1-G21R1 Has been detected");
- identity->p1g = 1;
- break;
- case SOC_7090_P1G_11R1:
- dprintk("SOC 7090 P1-G11R1 Has been detected");
- identity->p1g = 1;
- break;
- case SOC_7090_P1G_21R1:
- dprintk("SOC 7090 P1-G21R1 Has been detected");
- identity->p1g = 1;
- break;
- default:
- goto identification_error;
- }
- } else {
- switch ((identity->version >> 5) & 0x7) {
- case MP001:
- dprintk("MP001 : 9090/8096");
- break;
- case MP005:
- dprintk("MP005 : Single Sband");
- break;
- case MP008:
- dprintk("MP008 : diversity VHF-UHF-LBAND");
- break;
- case MP009:
- dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
- break;
- default:
- goto identification_error;
- }
-
- switch (identity->version & 0x1f) {
- case P1G_21R2:
- dprintk("P1G_21R2 detected");
- identity->p1g = 1;
- break;
- case P1G:
- dprintk("P1G detected");
- identity->p1g = 1;
- break;
- case P1D_E_F:
- dprintk("P1D/E/F detected");
- break;
- case P1C:
- dprintk("P1C detected");
- break;
- case P1A_B:
- dprintk("P1-A/B detected: driver is deactivated - not available");
- goto identification_error;
- break;
- default:
- goto identification_error;
- }
- }
-
- return 0;
-
-identification_error:
- return -EIO;
-}
-
-static int dib0090_fw_identify(struct dvb_frontend *fe)
-{
- struct dib0090_fw_state *state = fe->tuner_priv;
- struct dib0090_identity *identity = &state->identity;
-
- u16 v = dib0090_fw_read_reg(state, 0x1a);
- identity->p1g = 0;
- identity->in_soc = 0;
-
- dprintk("FE: Tuner identification (Version = 0x%04x)", v);
-
- /* without PLL lock info */
- v &= ~KROSUS_PLL_LOCKED;
-
- identity->version = v & 0xff;
- identity->product = (v >> 8) & 0xf;
-
- if (identity->product != KROSUS)
- goto identification_error;
-
- if ((identity->version & 0x3) == SOC) {
- identity->in_soc = 1;
- switch (identity->version) {
- case SOC_8090_P1G_11R1:
- dprintk("SOC 8090 P1-G11R1 Has been detected");
- identity->p1g = 1;
- break;
- case SOC_8090_P1G_21R1:
- dprintk("SOC 8090 P1-G21R1 Has been detected");
- identity->p1g = 1;
- break;
- case SOC_7090_P1G_11R1:
- dprintk("SOC 7090 P1-G11R1 Has been detected");
- identity->p1g = 1;
- break;
- case SOC_7090_P1G_21R1:
- dprintk("SOC 7090 P1-G21R1 Has been detected");
- identity->p1g = 1;
- break;
- default:
- goto identification_error;
- }
- } else {
- switch ((identity->version >> 5) & 0x7) {
- case MP001:
- dprintk("MP001 : 9090/8096");
- break;
- case MP005:
- dprintk("MP005 : Single Sband");
- break;
- case MP008:
- dprintk("MP008 : diversity VHF-UHF-LBAND");
- break;
- case MP009:
- dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
- break;
- default:
- goto identification_error;
- }
-
- switch (identity->version & 0x1f) {
- case P1G_21R2:
- dprintk("P1G_21R2 detected");
- identity->p1g = 1;
- break;
- case P1G:
- dprintk("P1G detected");
- identity->p1g = 1;
- break;
- case P1D_E_F:
- dprintk("P1D/E/F detected");
- break;
- case P1C:
- dprintk("P1C detected");
- break;
- case P1A_B:
- dprintk("P1-A/B detected: driver is deactivated - not available");
- goto identification_error;
- break;
- default:
- goto identification_error;
- }
- }
-
- return 0;
-
-identification_error:
- return -EIO;
-}
-
-static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
-{
- struct dib0090_state *state = fe->tuner_priv;
- u16 PllCfg, i, v;
-
- HARD_RESET(state);
-
- dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
- dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
-
- if (!cfg->in_soc) {
- /* adcClkOutRatio=8->7, release reset */
- dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
- if (cfg->clkoutdrive != 0)
- dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
- | (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
- else
- dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
- | (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
- }
-
- /* Read Pll current config * */
- PllCfg = dib0090_read_reg(state, 0x21);
-
- /** Reconfigure PLL if current setting is different from default setting **/
- if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_soc)
- && !cfg->io.pll_bypass) {
-
- /* Set Bypass mode */
- PllCfg |= (1 << 15);
- dib0090_write_reg(state, 0x21, PllCfg);
-
- /* Set Reset Pll */
- PllCfg &= ~(1 << 13);
- dib0090_write_reg(state, 0x21, PllCfg);
-
- /*** Set new Pll configuration in bypass and reset state ***/
- PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
- dib0090_write_reg(state, 0x21, PllCfg);
-
- /* Remove Reset Pll */
- PllCfg |= (1 << 13);
- dib0090_write_reg(state, 0x21, PllCfg);
-
- /*** Wait for PLL lock ***/
- i = 100;
- do {
- v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
- if (v)
- break;
- } while (--i);
-
- if (i == 0) {
- dprintk("Pll: Unable to lock Pll");
- return;
- }
-
- /* Finally Remove Bypass mode */
- PllCfg &= ~(1 << 15);
- dib0090_write_reg(state, 0x21, PllCfg);
- }
-
- if (cfg->io.pll_bypass) {
- PllCfg |= (cfg->io.pll_bypass << 15);
- dib0090_write_reg(state, 0x21, PllCfg);
- }
-}
-
-static int dib0090_fw_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
-{
- struct dib0090_fw_state *state = fe->tuner_priv;
- u16 PllCfg;
- u16 v;
- int i;
-
- dprintk("fw reset digital");
- HARD_RESET(state);
-
- dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
- dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
-
- dib0090_fw_write_reg(state, 0x20,
- ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) | cfg->ls_cfg_pad_drv);
-
- v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | (0 << 2) | (0);
- if (cfg->clkoutdrive != 0)
- v |= cfg->clkoutdrive << 5;
- else
- v |= 7 << 5;
-
- v |= 2 << 10;
- dib0090_fw_write_reg(state, 0x23, v);
-
- /* Read Pll current config * */
- PllCfg = dib0090_fw_read_reg(state, 0x21);
-
- /** Reconfigure PLL if current setting is different from default setting **/
- if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) {
-
- /* Set Bypass mode */
- PllCfg |= (1 << 15);
- dib0090_fw_write_reg(state, 0x21, PllCfg);
-
- /* Set Reset Pll */
- PllCfg &= ~(1 << 13);
- dib0090_fw_write_reg(state, 0x21, PllCfg);
-
- /*** Set new Pll configuration in bypass and reset state ***/
- PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
- dib0090_fw_write_reg(state, 0x21, PllCfg);
-
- /* Remove Reset Pll */
- PllCfg |= (1 << 13);
- dib0090_fw_write_reg(state, 0x21, PllCfg);
-
- /*** Wait for PLL lock ***/
- i = 100;
- do {
- v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);
- if (v)
- break;
- } while (--i);
-
- if (i == 0) {
- dprintk("Pll: Unable to lock Pll");
- return -EIO;
- }
-
- /* Finally Remove Bypass mode */
- PllCfg &= ~(1 << 15);
- dib0090_fw_write_reg(state, 0x21, PllCfg);
- }
-
- if (cfg->io.pll_bypass) {
- PllCfg |= (cfg->io.pll_bypass << 15);
- dib0090_fw_write_reg(state, 0x21, PllCfg);
- }
-
- return dib0090_fw_identify(fe);
-}
-
-static int dib0090_wakeup(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- if (state->config->sleep)
- state->config->sleep(fe, 0);
-
- /* enable dataTX in case we have been restarted in the wrong moment */
- dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
- return 0;
-}
-
-static int dib0090_sleep(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- if (state->config->sleep)
- state->config->sleep(fe, 1);
- return 0;
-}
-
-void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
-{
- struct dib0090_state *state = fe->tuner_priv;
- if (fast)
- dib0090_write_reg(state, 0x04, 0);
- else
- dib0090_write_reg(state, 0x04, 1);
-}
-
-EXPORT_SYMBOL(dib0090_dcc_freq);
-
-static const u16 bb_ramp_pwm_normal_socs[] = {
- 550, /* max BB gain in 10th of dB */
- (1 << 9) | 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
- 440,
- (4 << 9) | 0, /* BB_RAMP3 = 26dB */
- (0 << 9) | 208, /* BB_RAMP4 */
- (4 << 9) | 208, /* BB_RAMP5 = 29dB */
- (0 << 9) | 440, /* BB_RAMP6 */
-};
-
-static const u16 rf_ramp_pwm_cband_7090[] = {
- 280, /* max RF gain in 10th of dB */
- 18, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
- 504, /* ramp_max = maximum X used on the ramp */
- (29 << 10) | 364, /* RF_RAMP5, LNA 1 = 8dB */
- (0 << 10) | 504, /* RF_RAMP6, LNA 1 */
- (60 << 10) | 228, /* RF_RAMP7, LNA 2 = 7.7dB */
- (0 << 10) | 364, /* RF_RAMP8, LNA 2 */
- (34 << 10) | 109, /* GAIN_4_1, LNA 3 = 6.8dB */
- (0 << 10) | 228, /* GAIN_4_2, LNA 3 */
- (37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
- (0 << 10) | 109, /* RF_RAMP4, LNA 4 */
-};
-
-static const uint16_t rf_ramp_pwm_cband_7090e_sensitivity[] = {
- 186,
- 40,
- 746,
- (10 << 10) | 345,
- (0 << 10) | 746,
- (0 << 10) | 0,
- (0 << 10) | 0,
- (28 << 10) | 200,
- (0 << 10) | 345,
- (20 << 10) | 0,
- (0 << 10) | 200,
-};
-
-static const uint16_t rf_ramp_pwm_cband_7090e_aci[] = {
- 86,
- 40,
- 345,
- (0 << 10) | 0,
- (0 << 10) | 0,
- (0 << 10) | 0,
- (0 << 10) | 0,
- (28 << 10) | 200,
- (0 << 10) | 345,
- (20 << 10) | 0,
- (0 << 10) | 200,
-};
-
-static const u16 rf_ramp_pwm_cband_8090[] = {
- 345, /* max RF gain in 10th of dB */
- 29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
- 1000, /* ramp_max = maximum X used on the ramp */
- (35 << 10) | 772, /* RF_RAMP3, LNA 1 = 8dB */
- (0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
- (58 << 10) | 496, /* RF_RAMP5, LNA 2 = 9.5dB */
- (0 << 10) | 772, /* RF_RAMP6, LNA 2 */
- (27 << 10) | 200, /* RF_RAMP7, LNA 3 = 10.5dB */
- (0 << 10) | 496, /* RF_RAMP8, LNA 3 */
- (40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
- (0 << 10) | 200, /* GAIN_4_2, LNA 4 */
-};
-
-static const u16 rf_ramp_pwm_uhf_7090[] = {
- 407, /* max RF gain in 10th of dB */
- 13, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
- 529, /* ramp_max = maximum X used on the ramp */
- (23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
- (0 << 10) | 176, /* RF_RAMP4, LNA 1 */
- (63 << 10) | 400, /* RF_RAMP5, LNA 2 = 8dB */
- (0 << 10) | 529, /* RF_RAMP6, LNA 2 */
- (48 << 10) | 316, /* RF_RAMP7, LNA 3 = 6.8dB */
- (0 << 10) | 400, /* RF_RAMP8, LNA 3 */
- (29 << 10) | 176, /* GAIN_4_1, LNA 4 = 11.5dB */
- (0 << 10) | 316, /* GAIN_4_2, LNA 4 */
-};
-
-static const u16 rf_ramp_pwm_uhf_8090[] = {
- 388, /* max RF gain in 10th of dB */
- 26, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
- 1008, /* ramp_max = maximum X used on the ramp */
- (11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
- (0 << 10) | 369, /* RF_RAMP4, LNA 1 */
- (41 << 10) | 809, /* RF_RAMP5, LNA 2 = 8dB */
- (0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
- (27 << 10) | 659, /* RF_RAMP7, LNA 3 = 6dB */
- (0 << 10) | 809, /* RF_RAMP8, LNA 3 */
- (14 << 10) | 369, /* GAIN_4_1, LNA 4 = 11.5dB */
- (0 << 10) | 659, /* GAIN_4_2, LNA 4 */
-};
-
-static const u16 rf_ramp_pwm_cband[] = {
- 0, /* max RF gain in 10th of dB */
- 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
- 0, /* ramp_max = maximum X used on the ramp */
- (0 << 10) | 0, /* 0x2c, LNA 1 = 0dB */
- (0 << 10) | 0, /* 0x2d, LNA 1 */
- (0 << 10) | 0, /* 0x2e, LNA 2 = 0dB */
- (0 << 10) | 0, /* 0x2f, LNA 2 */
- (0 << 10) | 0, /* 0x30, LNA 3 = 0dB */
- (0 << 10) | 0, /* 0x31, LNA 3 */
- (0 << 10) | 0, /* GAIN_4_1, LNA 4 = 0dB */
- (0 << 10) | 0, /* GAIN_4_2, LNA 4 */
-};
-
-static const u16 rf_ramp_vhf[] = {
- 412, /* max RF gain in 10th of dB */
- 132, 307, 127, /* LNA1, 13.2dB */
- 105, 412, 255, /* LNA2, 10.5dB */
- 50, 50, 127, /* LNA3, 5dB */
- 125, 175, 127, /* LNA4, 12.5dB */
- 0, 0, 127, /* CBAND, 0dB */
-};
-
-static const u16 rf_ramp_uhf[] = {
- 412, /* max RF gain in 10th of dB */
- 132, 307, 127, /* LNA1 : total gain = 13.2dB, point on the ramp where this amp is full gain, value to write to get full gain */
- 105, 412, 255, /* LNA2 : 10.5 dB */
- 50, 50, 127, /* LNA3 : 5.0 dB */
- 125, 175, 127, /* LNA4 : 12.5 dB */
- 0, 0, 127, /* CBAND : 0.0 dB */
-};
-
-static const u16 rf_ramp_cband_broadmatching[] = /* for p1G only */
-{
- 314, /* Calibrated at 200MHz order has been changed g4-g3-g2-g1 */
- 84, 314, 127, /* LNA1 */
- 80, 230, 255, /* LNA2 */
- 80, 150, 127, /* LNA3 It was measured 12dB, do not lock if 120 */
- 70, 70, 127, /* LNA4 */
- 0, 0, 127, /* CBAND */
-};
-
-static const u16 rf_ramp_cband[] = {
- 332, /* max RF gain in 10th of dB */
- 132, 252, 127, /* LNA1, dB */
- 80, 332, 255, /* LNA2, dB */
- 0, 0, 127, /* LNA3, dB */
- 0, 0, 127, /* LNA4, dB */
- 120, 120, 127, /* LT1 CBAND */
-};
-
-static const u16 rf_ramp_pwm_vhf[] = {
- 404, /* max RF gain in 10th of dB */
- 25, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
- 1011, /* ramp_max = maximum X used on the ramp */
- (6 << 10) | 417, /* 0x2c, LNA 1 = 13.2dB */
- (0 << 10) | 756, /* 0x2d, LNA 1 */
- (16 << 10) | 756, /* 0x2e, LNA 2 = 10.5dB */
- (0 << 10) | 1011, /* 0x2f, LNA 2 */
- (16 << 10) | 290, /* 0x30, LNA 3 = 5dB */
- (0 << 10) | 417, /* 0x31, LNA 3 */
- (7 << 10) | 0, /* GAIN_4_1, LNA 4 = 12.5dB */
- (0 << 10) | 290, /* GAIN_4_2, LNA 4 */
-};
-
-static const u16 rf_ramp_pwm_uhf[] = {
- 404, /* max RF gain in 10th of dB */
- 25, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
- 1011, /* ramp_max = maximum X used on the ramp */
- (6 << 10) | 417, /* 0x2c, LNA 1 = 13.2dB */
- (0 << 10) | 756, /* 0x2d, LNA 1 */
- (16 << 10) | 756, /* 0x2e, LNA 2 = 10.5dB */
- (0 << 10) | 1011, /* 0x2f, LNA 2 */
- (16 << 10) | 0, /* 0x30, LNA 3 = 5dB */
- (0 << 10) | 127, /* 0x31, LNA 3 */
- (7 << 10) | 127, /* GAIN_4_1, LNA 4 = 12.5dB */
- (0 << 10) | 417, /* GAIN_4_2, LNA 4 */
-};
-
-static const u16 bb_ramp_boost[] = {
- 550, /* max BB gain in 10th of dB */
- 260, 260, 26, /* BB1, 26dB */
- 290, 550, 29, /* BB2, 29dB */
-};
-
-static const u16 bb_ramp_pwm_normal[] = {
- 500, /* max RF gain in 10th of dB */
- 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x34 */
- 400,
- (2 << 9) | 0, /* 0x35 = 21dB */
- (0 << 9) | 168, /* 0x36 */
- (2 << 9) | 168, /* 0x37 = 29dB */
- (0 << 9) | 400, /* 0x38 */
-};
-
-struct slope {
- s16 range;
- s16 slope;
-};
-static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
-{
- u8 i;
- u16 rest;
- u16 ret = 0;
- for (i = 0; i < num; i++) {
- if (val > slopes[i].range)
- rest = slopes[i].range;
- else
- rest = val;
- ret += (rest * slopes[i].slope) / slopes[i].range;
- val -= rest;
- }
- return ret;
-}
-
-static const struct slope dib0090_wbd_slopes[3] = {
- {66, 120}, /* -64,-52: offset - 65 */
- {600, 170}, /* -52,-35: 65 - 665 */
- {170, 250}, /* -45,-10: 665 - 835 */
-};
-
-static s16 dib0090_wbd_to_db(struct dib0090_state *state, u16 wbd)
-{
- wbd &= 0x3ff;
- if (wbd < state->wbd_offset)
- wbd = 0;
- else
- wbd -= state->wbd_offset;
- /* -64dB is the floor */
- return -640 + (s16) slopes_to_scale(dib0090_wbd_slopes, ARRAY_SIZE(dib0090_wbd_slopes), wbd);
-}
-
-static void dib0090_wbd_target(struct dib0090_state *state, u32 rf)
-{
- u16 offset = 250;
-
- /* TODO : DAB digital N+/-1 interferer perfs : offset = 10 */
-
- if (state->current_band == BAND_VHF)
- offset = 650;
-#ifndef FIRMWARE_FIREFLY
- if (state->current_band == BAND_VHF)
- offset = state->config->wbd_vhf_offset;
- if (state->current_band == BAND_CBAND)
- offset = state->config->wbd_cband_offset;
-#endif
-
- state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + offset);
- dprintk("wbd-target: %d dB", (u32) state->wbd_target);
-}
-
-static const int gain_reg_addr[4] = {
- 0x08, 0x0a, 0x0f, 0x01
-};
-
-static void dib0090_gain_apply(struct dib0090_state *state, s16 gain_delta, s16 top_delta, u8 force)
-{
- u16 rf, bb, ref;
- u16 i, v, gain_reg[4] = { 0 }, gain;
- const u16 *g;
-
- if (top_delta < -511)
- top_delta = -511;
- if (top_delta > 511)
- top_delta = 511;
-
- if (force) {
- top_delta *= (1 << WBD_ALPHA);
- gain_delta *= (1 << GAIN_ALPHA);
- }
-
- if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit)) /* overflow */
- state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
- else
- state->rf_gain_limit += top_delta;
-
- if (state->rf_gain_limit < 0) /*underflow */
- state->rf_gain_limit = 0;
-
- /* use gain as a temporary variable and correct current_gain */
- gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA;
- if (gain_delta >= ((s16) gain - state->current_gain)) /* overflow */
- state->current_gain = gain;
- else
- state->current_gain += gain_delta;
- /* cannot be less than 0 (only if gain_delta is less than 0 we can have current_gain < 0) */
- if (state->current_gain < 0)
- state->current_gain = 0;
-
- /* now split total gain to rf and bb gain */
- gain = state->current_gain >> GAIN_ALPHA;
-
- /* requested gain is bigger than rf gain limit - ACI/WBD adjustment */
- if (gain > (state->rf_gain_limit >> WBD_ALPHA)) {
- rf = state->rf_gain_limit >> WBD_ALPHA;
- bb = gain - rf;
- if (bb > state->bb_ramp[0])
- bb = state->bb_ramp[0];
- } else { /* high signal level -> all gains put on RF */
- rf = gain;
- bb = 0;
- }
-
- state->gain[0] = rf;
- state->gain[1] = bb;
-
- /* software ramp */
- /* Start with RF gains */
- g = state->rf_ramp + 1; /* point on RF LNA1 max gain */
- ref = rf;
- for (i = 0; i < 7; i++) { /* Go over all amplifiers => 5RF amps + 2 BB amps = 7 amps */
- if (g[0] == 0 || ref < (g[1] - g[0])) /* if total gain of the current amp is null or this amp is not concerned because it starts to work from an higher gain value */
- v = 0; /* force the gain to write for the current amp to be null */
- else if (ref >= g[1]) /* Gain to set is higher than the high working point of this amp */
- v = g[2]; /* force this amp to be full gain */
- else /* compute the value to set to this amp because we are somewhere in his range */
- v = ((ref - (g[1] - g[0])) * g[2]) / g[0];
-
- if (i == 0) /* LNA 1 reg mapping */
- gain_reg[0] = v;
- else if (i == 1) /* LNA 2 reg mapping */
- gain_reg[0] |= v << 7;
- else if (i == 2) /* LNA 3 reg mapping */
- gain_reg[1] = v;
- else if (i == 3) /* LNA 4 reg mapping */
- gain_reg[1] |= v << 7;
- else if (i == 4) /* CBAND LNA reg mapping */
- gain_reg[2] = v | state->rf_lt_def;
- else if (i == 5) /* BB gain 1 reg mapping */
- gain_reg[3] = v << 3;
- else if (i == 6) /* BB gain 2 reg mapping */
- gain_reg[3] |= v << 8;
-
- g += 3; /* go to next gain bloc */
-
- /* When RF is finished, start with BB */
- if (i == 4) {
- g = state->bb_ramp + 1; /* point on BB gain 1 max gain */
- ref = bb;
- }
- }
- gain_reg[3] |= state->bb_1_def;
- gain_reg[3] |= ((bb % 10) * 100) / 125;
-
-#ifdef DEBUG_AGC
- dprintk("GA CALC: DB: %3d(rf) + %3d(bb) = %3d gain_reg[0]=%04x gain_reg[1]=%04x gain_reg[2]=%04x gain_reg[0]=%04x", rf, bb, rf + bb,
- gain_reg[0], gain_reg[1], gain_reg[2], gain_reg[3]);
-#endif
-
- /* Write the amplifier regs */
- for (i = 0; i < 4; i++) {
- v = gain_reg[i];
- if (force || state->gain_reg[i] != v) {
- state->gain_reg[i] = v;
- dib0090_write_reg(state, gain_reg_addr[i], v);
- }
- }
-}
-
-static void dib0090_set_boost(struct dib0090_state *state, int onoff)
-{
- state->bb_1_def &= 0xdfff;
- state->bb_1_def |= onoff << 13;
-}
-
-static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg)
-{
- state->rf_ramp = cfg;
-}
-
-static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg)
-{
- state->rf_ramp = cfg;
-
- dib0090_write_reg(state, 0x2a, 0xffff);
-
- dprintk("total RF gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x2a));
-
- dib0090_write_regs(state, 0x2c, cfg + 3, 6);
- dib0090_write_regs(state, 0x3e, cfg + 9, 2);
-}
-
-static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg)
-{
- state->bb_ramp = cfg;
- dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
-}
-
-static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg)
-{
- state->bb_ramp = cfg;
-
- dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */
-
- dib0090_write_reg(state, 0x33, 0xffff);
- dprintk("total BB gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x33));
- dib0090_write_regs(state, 0x35, cfg + 3, 4);
-}
-
-void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- /* reset the AGC */
-
- if (state->config->use_pwm_agc) {
-#ifdef CONFIG_BAND_SBAND
- if (state->current_band == BAND_SBAND) {
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_sband);
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_boost);
- } else
-#endif
-#ifdef CONFIG_BAND_CBAND
- if (state->current_band == BAND_CBAND) {
- if (state->identity.in_soc) {
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
- if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_8090);
- else if (state->identity.version == SOC_7090_P1G_11R1
- || state->identity.version == SOC_7090_P1G_21R1) {
- if (state->config->is_dib7090e) {
- if (state->rf_ramp == NULL)
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090e_sensitivity);
- else
- dib0090_set_rframp_pwm(state, state->rf_ramp);
- } else
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090);
- }
- } else {
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
- }
- } else
-#endif
-#ifdef CONFIG_BAND_VHF
- if (state->current_band == BAND_VHF) {
- if (state->identity.in_soc) {
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
- } else {
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
- }
- } else
-#endif
- {
- if (state->identity.in_soc) {
- if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_8090);
- else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_7090);
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
- } else {
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf);
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
- }
- }
-
- if (state->rf_ramp[0] != 0)
- dib0090_write_reg(state, 0x32, (3 << 11));
- else
- dib0090_write_reg(state, 0x32, (0 << 11));
-
- dib0090_write_reg(state, 0x04, 0x03);
- dib0090_write_reg(state, 0x39, (1 << 10));
- }
-}
-
-EXPORT_SYMBOL(dib0090_pwm_gain_reset);
-
-void dib0090_set_dc_servo(struct dvb_frontend *fe, u8 DC_servo_cutoff)
-{
- struct dib0090_state *state = fe->tuner_priv;
- if (DC_servo_cutoff < 4)
- dib0090_write_reg(state, 0x04, DC_servo_cutoff);
-}
-EXPORT_SYMBOL(dib0090_set_dc_servo);
-
-static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
-{
- u16 adc_val = dib0090_read_reg(state, 0x1d);
- if (state->identity.in_soc)
- adc_val >>= 2;
- return adc_val;
-}
-
-int dib0090_gain_control(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- enum frontend_tune_state *tune_state = &state->tune_state;
- int ret = 10;
-
- u16 wbd_val = 0;
- u8 apply_gain_immediatly = 1;
- s16 wbd_error = 0, adc_error = 0;
-
- if (*tune_state == CT_AGC_START) {
- state->agc_freeze = 0;
- dib0090_write_reg(state, 0x04, 0x0);
-
-#ifdef CONFIG_BAND_SBAND
- if (state->current_band == BAND_SBAND) {
- dib0090_set_rframp(state, rf_ramp_sband);
- dib0090_set_bbramp(state, bb_ramp_boost);
- } else
-#endif
-#ifdef CONFIG_BAND_VHF
- if (state->current_band == BAND_VHF && !state->identity.p1g) {
- dib0090_set_rframp(state, rf_ramp_vhf);
- dib0090_set_bbramp(state, bb_ramp_boost);
- } else
-#endif
-#ifdef CONFIG_BAND_CBAND
- if (state->current_band == BAND_CBAND && !state->identity.p1g) {
- dib0090_set_rframp(state, rf_ramp_cband);
- dib0090_set_bbramp(state, bb_ramp_boost);
- } else
-#endif
- if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g) {
- dib0090_set_rframp(state, rf_ramp_cband_broadmatching);
- dib0090_set_bbramp(state, bb_ramp_boost);
- } else {
- dib0090_set_rframp(state, rf_ramp_uhf);
- dib0090_set_bbramp(state, bb_ramp_boost);
- }
-
- dib0090_write_reg(state, 0x32, 0);
- dib0090_write_reg(state, 0x39, 0);
-
- dib0090_wbd_target(state, state->current_rf);
-
- state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;
- state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA;
-
- *tune_state = CT_AGC_STEP_0;
- } else if (!state->agc_freeze) {
- s16 wbd = 0, i, cnt;
-
- int adc;
- wbd_val = dib0090_get_slow_adc_val(state);
-
- if (*tune_state == CT_AGC_STEP_0)
- cnt = 5;
- else
- cnt = 1;
-
- for (i = 0; i < cnt; i++) {
- wbd_val = dib0090_get_slow_adc_val(state);
- wbd += dib0090_wbd_to_db(state, wbd_val);
- }
- wbd /= cnt;
- wbd_error = state->wbd_target - wbd;
-
- if (*tune_state == CT_AGC_STEP_0) {
- if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) {
-#ifdef CONFIG_BAND_CBAND
- /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
- u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
- if (state->current_band == BAND_CBAND && ltg2) {
- ltg2 >>= 1;
- state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */
- }
-#endif
- } else {
- state->agc_step = 0;
- *tune_state = CT_AGC_STEP_1;
- }
- } else {
- /* calc the adc power */
- adc = state->config->get_adc_power(fe);
- adc = (adc * ((s32) 355774) + (((s32) 1) << 20)) >> 21; /* included in [0:-700] */
-
- adc_error = (s16) (((s32) ADC_TARGET) - adc);
-#ifdef CONFIG_STANDARD_DAB
- if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
- adc_error -= 10;
-#endif
-#ifdef CONFIG_STANDARD_DVBT
- if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
- (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
- adc_error += 60;
-#endif
-#ifdef CONFIG_SYS_ISDBT
- if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
- 0)
- &&
- ((state->fe->dtv_property_cache.layer[0].modulation ==
- QAM_64)
- || (state->fe->dtv_property_cache.
- layer[0].modulation == QAM_16)))
- ||
- ((state->fe->dtv_property_cache.layer[1].segment_count >
- 0)
- &&
- ((state->fe->dtv_property_cache.layer[1].modulation ==
- QAM_64)
- || (state->fe->dtv_property_cache.
- layer[1].modulation == QAM_16)))
- ||
- ((state->fe->dtv_property_cache.layer[2].segment_count >
- 0)
- &&
- ((state->fe->dtv_property_cache.layer[2].modulation ==
- QAM_64)
- || (state->fe->dtv_property_cache.
- layer[2].modulation == QAM_16)))
- )
- )
- adc_error += 60;
-#endif
-
- if (*tune_state == CT_AGC_STEP_1) { /* quickly go to the correct range of the ADC power */
- if (ABS(adc_error) < 50 || state->agc_step++ > 5) {
-
-#ifdef CONFIG_STANDARD_DAB
- if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) {
- dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : narrow BB filter : Fc = 1.8MHz */
- dib0090_write_reg(state, 0x04, 0x0);
- } else
-#endif
- {
- dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32));
- dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fast */
- }
-
- *tune_state = CT_AGC_STOP;
- }
- } else {
- /* everything higher than or equal to CT_AGC_STOP means tracking */
- ret = 100; /* 10ms interval */
- apply_gain_immediatly = 0;
- }
- }
-#ifdef DEBUG_AGC
- dprintk
- ("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
- (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
- (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
-#endif
- }
-
- /* apply gain */
- if (!state->agc_freeze)
- dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
- return ret;
-}
-
-EXPORT_SYMBOL(dib0090_gain_control);
-
-void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
-{
- struct dib0090_state *state = fe->tuner_priv;
- if (rf)
- *rf = state->gain[0];
- if (bb)
- *bb = state->gain[1];
- if (rf_gain_limit)
- *rf_gain_limit = state->rf_gain_limit;
- if (rflt)
- *rflt = (state->rf_lt_def >> 10) & 0x7;
-}
-
-EXPORT_SYMBOL(dib0090_get_current_gain);
-
-u16 dib0090_get_wbd_target(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;
- s32 current_temp = state->temperature;
- s32 wbd_thot, wbd_tcold;
- const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
-
- while (f_MHz > wbd->max_freq)
- wbd++;
-
- dprintk("using wbd-table-entry with max freq %d", wbd->max_freq);
-
- if (current_temp < 0)
- current_temp = 0;
- if (current_temp > 128)
- current_temp = 128;
-
- state->wbdmux &= ~(7 << 13);
- if (wbd->wbd_gain != 0)
- state->wbdmux |= (wbd->wbd_gain << 13);
- else
- state->wbdmux |= (4 << 13);
-
- dib0090_write_reg(state, 0x10, state->wbdmux);
-
- wbd_thot = wbd->offset_hot - (((u32) wbd->slope_hot * f_MHz) >> 6);
- wbd_tcold = wbd->offset_cold - (((u32) wbd->slope_cold * f_MHz) >> 6);
-
- wbd_tcold += ((wbd_thot - wbd_tcold) * current_temp) >> 7;
-
- state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold);
- dprintk("wbd-target: %d dB", (u32) state->wbd_target);
- dprintk("wbd offset applied is %d", wbd_tcold);
-
- return state->wbd_offset + wbd_tcold;
-}
-EXPORT_SYMBOL(dib0090_get_wbd_target);
-
-u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- return state->wbd_offset;
-}
-EXPORT_SYMBOL(dib0090_get_wbd_offset);
-
-int dib0090_set_switch(struct dvb_frontend *fe, u8 sw1, u8 sw2, u8 sw3)
-{
- struct dib0090_state *state = fe->tuner_priv;
-
- dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8)
- | ((sw3 & 1) << 2) | ((sw2 & 1) << 1) | (sw1 & 1));
-
- return 0;
-}
-EXPORT_SYMBOL(dib0090_set_switch);
-
-int dib0090_set_vga(struct dvb_frontend *fe, u8 onoff)
-{
- struct dib0090_state *state = fe->tuner_priv;
-
- dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff)
- | ((onoff & 1) << 15));
- return 0;
-}
-EXPORT_SYMBOL(dib0090_set_vga);
-
-int dib0090_update_rframp_7090(struct dvb_frontend *fe, u8 cfg_sensitivity)
-{
- struct dib0090_state *state = fe->tuner_priv;
-
- if ((!state->identity.p1g) || (!state->identity.in_soc)
- || ((state->identity.version != SOC_7090_P1G_21R1)
- && (state->identity.version != SOC_7090_P1G_11R1))) {
- dprintk("%s() function can only be used for dib7090P", __func__);
- return -ENODEV;
- }
-
- if (cfg_sensitivity)
- state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_sensitivity;
- else
- state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_aci;
- dib0090_pwm_gain_reset(fe);
-
- return 0;
-}
-EXPORT_SYMBOL(dib0090_update_rframp_7090);
-
-static const u16 dib0090_defaults[] = {
-
- 25, 0x01,
- 0x0000,
- 0x99a0,
- 0x6008,
- 0x0000,
- 0x8bcb,
- 0x0000,
- 0x0405,
- 0x0000,
- 0x0000,
- 0x0000,
- 0xb802,
- 0x0300,
- 0x2d12,
- 0xbac0,
- 0x7c00,
- 0xdbb9,
- 0x0954,
- 0x0743,
- 0x8000,
- 0x0001,
- 0x0040,
- 0x0100,
- 0x0000,
- 0xe910,
- 0x149e,
-
- 1, 0x1c,
- 0xff2d,
-
- 1, 0x39,
- 0x0000,
-
- 2, 0x1e,
- 0x07FF,
- 0x0007,
-
- 1, 0x24,
- EN_UHF | EN_CRYSTAL,
-
- 2, 0x3c,
- 0x3ff,
- 0x111,
- 0
-};
-
-static const u16 dib0090_p1g_additionnal_defaults[] = {
- 1, 0x05,
- 0xabcd,
-
- 1, 0x11,
- 0x00b4,
-
- 1, 0x1c,
- 0xfffd,
-
- 1, 0x40,
- 0x108,
- 0
-};
-
-static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n)
-{
- u16 l, r;
-
- l = pgm_read_word(n++);
- while (l) {
- r = pgm_read_word(n++);
- do {
- dib0090_write_reg(state, r, pgm_read_word(n++));
- r++;
- } while (--l);
- l = pgm_read_word(n++);
- }
-}
-
-#define CAP_VALUE_MIN (u8) 9
-#define CAP_VALUE_MAX (u8) 40
-#define HR_MIN (u8) 25
-#define HR_MAX (u8) 40
-#define POLY_MIN (u8) 0
-#define POLY_MAX (u8) 8
-
-static void dib0090_set_EFUSE(struct dib0090_state *state)
-{
- u8 c, h, n;
- u16 e2, e4;
- u16 cal;
-
- e2 = dib0090_read_reg(state, 0x26);
- e4 = dib0090_read_reg(state, 0x28);
-
- if ((state->identity.version == P1D_E_F) ||
- (state->identity.version == P1G) || (e2 == 0xffff)) {
-
- dib0090_write_reg(state, 0x22, 0x10);
- cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff;
-
- if ((cal < 670) || (cal == 1023))
- cal = 850;
- n = 165 - ((cal * 10)>>6) ;
- e2 = e4 = (3<<12) | (34<<6) | (n);
- }
-
- if (e2 != e4)
- e2 &= e4; /* Remove the redundancy */
-
- if (e2 != 0xffff) {
- c = e2 & 0x3f;
- n = (e2 >> 12) & 0xf;
- h = (e2 >> 6) & 0x3f;
-
- if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
- c = 32;
- if ((h >= HR_MAX) || (h <= HR_MIN))
- h = 34;
- if ((n >= POLY_MAX) || (n <= POLY_MIN))
- n = 3;
-
- dib0090_write_reg(state, 0x13, (h << 10)) ;
- e2 = (n<<11) | ((h>>2)<<6) | (c);
- dib0090_write_reg(state, 0x2, e2) ; /* Load the BB_2 */
- }
-}
-
-static int dib0090_reset(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
-
- dib0090_reset_digital(fe, state->config);
- if (dib0090_identify(fe) < 0)
- return -EIO;
-
-#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
- if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */
- return 0;
-#endif
-
- if (!state->identity.in_soc) {
- if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)
- dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));
- else
- dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));
- }
-
- dib0090_set_default_config(state, dib0090_defaults);
-
- if (state->identity.in_soc)
- dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */
-
- if (state->identity.p1g)
- dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);
-
- /* Update the efuse : Only available for KROSUS > P1C and SOC as well*/
- if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc))
- dib0090_set_EFUSE(state);
-
- /* Congigure in function of the crystal */
- if (state->config->force_crystal_mode != 0)
- dib0090_write_reg(state, 0x14,
- state->config->force_crystal_mode & 3);
- else if (state->config->io.clock_khz >= 24000)
- dib0090_write_reg(state, 0x14, 1);
- else
- dib0090_write_reg(state, 0x14, 2);
- dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
-
- state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibration when tuning next time */
-
- return 0;
-}
-
-#define steps(u) (((u) > 15) ? ((u)-16) : (u))
-#define INTERN_WAIT 10
-static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state)
-{
- int ret = INTERN_WAIT * 10;
-
- switch (*tune_state) {
- case CT_TUNER_STEP_2:
- /* Turns to positive */
- dib0090_write_reg(state, 0x1f, 0x7);
- *tune_state = CT_TUNER_STEP_3;
- break;
-
- case CT_TUNER_STEP_3:
- state->adc_diff = dib0090_read_reg(state, 0x1d);
-
- /* Turns to negative */
- dib0090_write_reg(state, 0x1f, 0x4);
- *tune_state = CT_TUNER_STEP_4;
- break;
-
- case CT_TUNER_STEP_4:
- state->adc_diff -= dib0090_read_reg(state, 0x1d);
- *tune_state = CT_TUNER_STEP_5;
- ret = 0;
- break;
-
- default:
- break;
- }
-
- return ret;
-}
-
-struct dc_calibration {
- u8 addr;
- u8 offset;
- u8 pga:1;
- u16 bb1;
- u8 i:1;
-};
-
-static const struct dc_calibration dc_table[] = {
- /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
- {0x06, 5, 1, (1 << 13) | (0 << 8) | (26 << 3), 1},
- {0x07, 11, 1, (1 << 13) | (0 << 8) | (26 << 3), 0},
- /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
- {0x06, 0, 0, (1 << 13) | (29 << 8) | (26 << 3), 1},
- {0x06, 10, 0, (1 << 13) | (29 << 8) | (26 << 3), 0},
- {0},
-};
-
-static const struct dc_calibration dc_p1g_table[] = {
- /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
- /* addr ; trim reg offset ; pga ; CTRL_BB1 value ; i or q */
- {0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},
- {0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},
- /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
- {0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},
- {0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},
- {0},
-};
-
-static void dib0090_set_trim(struct dib0090_state *state)
-{
- u16 *val;
-
- if (state->dc->addr == 0x07)
- val = &state->bb7;
- else
- val = &state->bb6;
-
- *val &= ~(0x1f << state->dc->offset);
- *val |= state->step << state->dc->offset;
-
- dib0090_write_reg(state, state->dc->addr, *val);
-}
-
-static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
-{
- int ret = 0;
- u16 reg;
-
- switch (*tune_state) {
- case CT_TUNER_START:
- dprintk("Start DC offset calibration");
-
- /* force vcm2 = 0.8V */
- state->bb6 = 0;
- state->bb7 = 0x040d;
-
- /* the LNA AND LO are off */
- reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */
- dib0090_write_reg(state, 0x24, reg);
-
- state->wbdmux = dib0090_read_reg(state, 0x10);
- dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);
- dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
-
- state->dc = dc_table;
-
- if (state->identity.p1g)
- state->dc = dc_p1g_table;
- *tune_state = CT_TUNER_STEP_0;
-
- /* fall through */
-
- case CT_TUNER_STEP_0:
- dprintk("Sart/continue DC calibration for %s path", (state->dc->i == 1) ? "I" : "Q");
- dib0090_write_reg(state, 0x01, state->dc->bb1);
- dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
-
- state->step = 0;
- state->min_adc_diff = 1023;
- *tune_state = CT_TUNER_STEP_1;
- ret = 50;
- break;
-
- case CT_TUNER_STEP_1:
- dib0090_set_trim(state);
- *tune_state = CT_TUNER_STEP_2;
- break;
-
- case CT_TUNER_STEP_2:
- case CT_TUNER_STEP_3:
- case CT_TUNER_STEP_4:
- ret = dib0090_get_offset(state, tune_state);
- break;
-
- case CT_TUNER_STEP_5: /* found an offset */
- dprintk("adc_diff = %d, current step= %d", (u32) state->adc_diff, state->step);
- if (state->step == 0 && state->adc_diff < 0) {
- state->min_adc_diff = -1023;
- dprintk("Change of sign of the minimum adc diff");
- }
-
- dprintk("adc_diff = %d, min_adc_diff = %d current_step = %d", state->adc_diff, state->min_adc_diff, state->step);
-
- /* first turn for this frequency */
- if (state->step == 0) {
- if (state->dc->pga && state->adc_diff < 0)
- state->step = 0x10;
- if (state->dc->pga == 0 && state->adc_diff > 0)
- state->step = 0x10;
- }
-
- /* Look for a change of Sign in the Adc_diff.min_adc_diff is used to STORE the setp N-1 */
- if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {
- /* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuance */
- state->step++;
- state->min_adc_diff = state->adc_diff;
- *tune_state = CT_TUNER_STEP_1;
- } else {
- /* the minimum was what we have seen in the step before */
- if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) {
- dprintk("Since adc_diff N = %d > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_diff);
- state->step--;
- }
-
- dib0090_set_trim(state);
- dprintk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->dc->addr, state->adc_diff, state->step);
-
- state->dc++;
- if (state->dc->addr == 0) /* done */
- *tune_state = CT_TUNER_STEP_6;
- else
- *tune_state = CT_TUNER_STEP_0;
-
- }
- break;
-
- case CT_TUNER_STEP_6:
- dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
- dib0090_write_reg(state, 0x1f, 0x7);
- *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
- state->calibrate &= ~DC_CAL;
- default:
- break;
- }
- return ret;
-}
-
-static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
-{
- u8 wbd_gain;
- const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
-
- switch (*tune_state) {
- case CT_TUNER_START:
- while (state->current_rf / 1000 > wbd->max_freq)
- wbd++;
- if (wbd->wbd_gain != 0)
- wbd_gain = wbd->wbd_gain;
- else {
- wbd_gain = 4;
-#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
- if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND))
- wbd_gain = 2;
-#endif
- }
-
- if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */
- *tune_state = CT_TUNER_START;
- state->calibrate &= ~WBD_CAL;
- return 0;
- }
-
- dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));
-
- dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));
- *tune_state = CT_TUNER_STEP_0;
- state->wbd_calibration_gain = wbd_gain;
- return 90; /* wait for the WBDMUX to switch and for the ADC to sample */
-
- case CT_TUNER_STEP_0:
- state->wbd_offset = dib0090_get_slow_adc_val(state);
- dprintk("WBD calibration offset = %d", state->wbd_offset);
- *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
- state->calibrate &= ~WBD_CAL;
- break;
-
- default:
- break;
- }
- return 0;
-}
-
-static void dib0090_set_bandwidth(struct dib0090_state *state)
-{
- u16 tmp;
-
- if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 5000)
- tmp = (3 << 14);
- else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 6000)
- tmp = (2 << 14);
- else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 7000)
- tmp = (1 << 14);
- else
- tmp = (0 << 14);
-
- state->bb_1_def &= 0x3fff;
- state->bb_1_def |= tmp;
-
- dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
-
- dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */
- dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */
- if (state->identity.in_soc) {
- dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */
- } else {
- dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */
- dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */
- }
-}
-
-static const struct dib0090_pll dib0090_pll_table[] = {
-#ifdef CONFIG_BAND_CBAND
- {56000, 0, 9, 48, 6},
- {70000, 1, 9, 48, 6},
- {87000, 0, 8, 32, 4},
- {105000, 1, 8, 32, 4},
- {115000, 0, 7, 24, 6},
- {140000, 1, 7, 24, 6},
- {170000, 0, 6, 16, 4},
-#endif
-#ifdef CONFIG_BAND_VHF
- {200000, 1, 6, 16, 4},
- {230000, 0, 5, 12, 6},
- {280000, 1, 5, 12, 6},
- {340000, 0, 4, 8, 4},
- {380000, 1, 4, 8, 4},
- {450000, 0, 3, 6, 6},
-#endif
-#ifdef CONFIG_BAND_UHF
- {580000, 1, 3, 6, 6},
- {700000, 0, 2, 4, 4},
- {860000, 1, 2, 4, 4},
-#endif
-#ifdef CONFIG_BAND_LBAND
- {1800000, 1, 0, 2, 4},
-#endif
-#ifdef CONFIG_BAND_SBAND
- {2900000, 0, 14, 1, 4},
-#endif
-};
-
-static const struct dib0090_tuning dib0090_tuning_table_fm_vhf_on_cband[] = {
-
-#ifdef CONFIG_BAND_CBAND
- {184000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
- {227000, 4, 3, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
- {380000, 4, 7, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
-#endif
-#ifdef CONFIG_BAND_UHF
- {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
-#endif
-#ifdef CONFIG_BAND_LBAND
- {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
- {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
- {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
-#endif
-#ifdef CONFIG_BAND_SBAND
- {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
- {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
-#endif
-};
-
-static const struct dib0090_tuning dib0090_tuning_table[] = {
-
-#ifdef CONFIG_BAND_CBAND
- {170000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
-#endif
-#ifdef CONFIG_BAND_VHF
- {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
- {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
- {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
-#endif
-#ifdef CONFIG_BAND_UHF
- {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
-#endif
-#ifdef CONFIG_BAND_LBAND
- {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
- {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
- {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
-#endif
-#ifdef CONFIG_BAND_SBAND
- {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
- {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
-#endif
-};
-
-static const struct dib0090_tuning dib0090_p1g_tuning_table[] = {
-#ifdef CONFIG_BAND_CBAND
- {170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},
-#endif
-#ifdef CONFIG_BAND_VHF
- {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
- {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
- {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
-#endif
-#ifdef CONFIG_BAND_UHF
- {510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
-#endif
-#ifdef CONFIG_BAND_LBAND
- {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
- {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
- {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
-#endif
-#ifdef CONFIG_BAND_SBAND
- {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
- {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
-#endif
-};
-
-static const struct dib0090_pll dib0090_p1g_pll_table[] = {
-#ifdef CONFIG_BAND_CBAND
- {57000, 0, 11, 48, 6},
- {70000, 1, 11, 48, 6},
- {86000, 0, 10, 32, 4},
- {105000, 1, 10, 32, 4},
- {115000, 0, 9, 24, 6},
- {140000, 1, 9, 24, 6},
- {170000, 0, 8, 16, 4},
-#endif
-#ifdef CONFIG_BAND_VHF
- {200000, 1, 8, 16, 4},
- {230000, 0, 7, 12, 6},
- {280000, 1, 7, 12, 6},
- {340000, 0, 6, 8, 4},
- {380000, 1, 6, 8, 4},
- {455000, 0, 5, 6, 6},
-#endif
-#ifdef CONFIG_BAND_UHF
- {580000, 1, 5, 6, 6},
- {680000, 0, 4, 4, 4},
- {860000, 1, 4, 4, 4},
-#endif
-#ifdef CONFIG_BAND_LBAND
- {1800000, 1, 2, 2, 4},
-#endif
-#ifdef CONFIG_BAND_SBAND
- {2900000, 0, 1, 1, 6},
-#endif
-};
-
-static const struct dib0090_tuning dib0090_p1g_tuning_table_fm_vhf_on_cband[] = {
-#ifdef CONFIG_BAND_CBAND
- {184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
- {227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
- {380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
-#endif
-#ifdef CONFIG_BAND_UHF
- {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
- {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
-#endif
-#ifdef CONFIG_BAND_LBAND
- {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
- {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
- {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
-#endif
-#ifdef CONFIG_BAND_SBAND
- {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
- {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
-#endif
-};
-
-static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
-#ifdef CONFIG_BAND_CBAND
- {300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
- {380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
- {570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
- {858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
-#endif
-};
-
-static const struct dib0090_tuning dib0090_tuning_table_cband_7090e_sensitivity[] = {
-#ifdef CONFIG_BAND_CBAND
- { 300000, 0 , 3, 0x8105, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
- { 380000, 0 , 10, 0x810F, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
- { 600000, 0 , 10, 0x815E, 0x280, 0x2d12, 0xb84e, EN_CAB },
- { 660000, 0 , 5, 0x85E3, 0x280, 0x2d12, 0xb84e, EN_CAB },
- { 720000, 0 , 5, 0x852E, 0x280, 0x2d12, 0xb84e, EN_CAB },
- { 860000, 0 , 4, 0x85E5, 0x280, 0x2d12, 0xb84e, EN_CAB },
-#endif
-};
-
-int dib0090_update_tuning_table_7090(struct dvb_frontend *fe,
- u8 cfg_sensitivity)
-{
- struct dib0090_state *state = fe->tuner_priv;
- const struct dib0090_tuning *tune =
- dib0090_tuning_table_cband_7090e_sensitivity;
- const struct dib0090_tuning dib0090_tuning_table_cband_7090e_aci[] = {
- { 300000, 0 , 3, 0x8165, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
- { 650000, 0 , 4, 0x815B, 0x280, 0x2d12, 0xb84e, EN_CAB },
- { 860000, 0 , 5, 0x84EF, 0x280, 0x2d12, 0xb84e, EN_CAB },
- };
-
- if ((!state->identity.p1g) || (!state->identity.in_soc)
- || ((state->identity.version != SOC_7090_P1G_21R1)
- && (state->identity.version != SOC_7090_P1G_11R1))) {
- dprintk("%s() function can only be used for dib7090", __func__);
- return -ENODEV;
- }
-
- if (cfg_sensitivity)
- tune = dib0090_tuning_table_cband_7090e_sensitivity;
- else
- tune = dib0090_tuning_table_cband_7090e_aci;
-
- while (state->rf_request > tune->max_freq)
- tune++;
-
- dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000)
- | (tune->lna_bias & 0x7fff));
- dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f)
- | ((tune->lna_tune << 6) & 0x07c0));
- return 0;
-}
-EXPORT_SYMBOL(dib0090_update_tuning_table_7090);
-
-static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)
-{
- int ret = 0;
- u16 lo4 = 0xe900;
-
- s16 adc_target;
- u16 adc;
- s8 step_sign;
- u8 force_soft_search = 0;
-
- if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
- force_soft_search = 1;
-
- if (*tune_state == CT_TUNER_START) {
- dprintk("Start Captrim search : %s", (force_soft_search == 1) ? "FORCE SOFT SEARCH" : "AUTO");
- dib0090_write_reg(state, 0x10, 0x2B1);
- dib0090_write_reg(state, 0x1e, 0x0032);
-
- if (!state->tuner_is_tuned) {
- /* prepare a complete captrim */
- if (!state->identity.p1g || force_soft_search)
- state->step = state->captrim = state->fcaptrim = 64;
-
- state->current_rf = state->rf_request;
- } else { /* we are already tuned to this frequency - the configuration is correct */
- if (!state->identity.p1g || force_soft_search) {
- /* do a minimal captrim even if the frequency has not changed */
- state->step = 4;
- state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
- }
- }
- state->adc_diff = 3000;
- *tune_state = CT_TUNER_STEP_0;
-
- } else if (*tune_state == CT_TUNER_STEP_0) {
- if (state->identity.p1g && !force_soft_search) {
- u8 ratio = 31;
-
- dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
- dib0090_read_reg(state, 0x40);
- ret = 50;
- } else {
- state->step /= 2;
- dib0090_write_reg(state, 0x18, lo4 | state->captrim);
-
- if (state->identity.in_soc)
- ret = 25;
- }
- *tune_state = CT_TUNER_STEP_1;
-
- } else if (*tune_state == CT_TUNER_STEP_1) {
- if (state->identity.p1g && !force_soft_search) {
- dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);
- dib0090_read_reg(state, 0x40);
-
- state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;
- dprintk("***Final Captrim= 0x%x", state->fcaptrim);
- *tune_state = CT_TUNER_STEP_3;
-
- } else {
- /* MERGE for all krosus before P1G */
- adc = dib0090_get_slow_adc_val(state);
- dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) 1800 / (u32) 1024);
-
- if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug : TO CHECK IN ACI for SOCS !!! if 400 for 8090p SOC => tune issue !!! */
- adc_target = 200;
- } else
- adc_target = 400;
-
- if (adc >= adc_target) {
- adc -= adc_target;
- step_sign = -1;
- } else {
- adc = adc_target - adc;
- step_sign = 1;
- }
-
- if (adc < state->adc_diff) {
- dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
- state->adc_diff = adc;
- state->fcaptrim = state->captrim;
- }
-
- state->captrim += step_sign * state->step;
- if (state->step >= 1)
- *tune_state = CT_TUNER_STEP_0;
- else
- *tune_state = CT_TUNER_STEP_2;
-
- ret = 25;
- }
- } else if (*tune_state == CT_TUNER_STEP_2) { /* this step is only used by krosus < P1G */
- /*write the final cptrim config */
- dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
-
- *tune_state = CT_TUNER_STEP_3;
-
- } else if (*tune_state == CT_TUNER_STEP_3) {
- state->calibrate &= ~CAPTRIM_CAL;
- *tune_state = CT_TUNER_STEP_0;
- }
-
- return ret;
-}
-
-static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_state)
-{
- int ret = 15;
- s16 val;
-
- switch (*tune_state) {
- case CT_TUNER_START:
- state->wbdmux = dib0090_read_reg(state, 0x10);
- dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));
-
- state->bias = dib0090_read_reg(state, 0x13);
- dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));
-
- *tune_state = CT_TUNER_STEP_0;
- /* wait for the WBDMUX to switch and for the ADC to sample */
- break;
-
- case CT_TUNER_STEP_0:
- state->adc_diff = dib0090_get_slow_adc_val(state);
- dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));
- *tune_state = CT_TUNER_STEP_1;
- break;
-
- case CT_TUNER_STEP_1:
- val = dib0090_get_slow_adc_val(state);
- state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55;
-
- dprintk("temperature: %d C", state->temperature - 30);
-
- *tune_state = CT_TUNER_STEP_2;
- break;
-
- case CT_TUNER_STEP_2:
- dib0090_write_reg(state, 0x13, state->bias);
- dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */
-
- *tune_state = CT_TUNER_START;
- state->calibrate &= ~TEMP_CAL;
- if (state->config->analog_output == 0)
- dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
-
- break;
-
- default:
- ret = 0;
- break;
- }
- return ret;
-}
-
-#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
-static int dib0090_tune(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- const struct dib0090_tuning *tune = state->current_tune_table_index;
- const struct dib0090_pll *pll = state->current_pll_table_index;
- enum frontend_tune_state *tune_state = &state->tune_state;
-
- u16 lo5, lo6, Den, tmp;
- u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
- int ret = 10; /* 1ms is the default delay most of the time */
- u8 c, i;
-
- /************************* VCO ***************************/
- /* Default values for FG */
- /* from these are needed : */
- /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */
-
- /* in any case we first need to do a calibration if needed */
- if (*tune_state == CT_TUNER_START) {
- /* deactivate DataTX before some calibrations */
- if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))
- dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
- else
- /* Activate DataTX in case a calibration has been done before */
- if (state->config->analog_output == 0)
- dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
- }
-
- if (state->calibrate & DC_CAL)
- return dib0090_dc_offset_calibration(state, tune_state);
- else if (state->calibrate & WBD_CAL) {
- if (state->current_rf == 0)
- state->current_rf = state->fe->dtv_property_cache.frequency / 1000;
- return dib0090_wbd_calibration(state, tune_state);
- } else if (state->calibrate & TEMP_CAL)
- return dib0090_get_temperature(state, tune_state);
- else if (state->calibrate & CAPTRIM_CAL)
- return dib0090_captrim_search(state, tune_state);
-
- if (*tune_state == CT_TUNER_START) {
- /* if soc and AGC pwm control, disengage mux to be able to R/W access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, otherwise, SOC SERPAR error when accessing to 0x01 */
- if (state->config->use_pwm_agc && state->identity.in_soc) {
- tmp = dib0090_read_reg(state, 0x39);
- if ((tmp >> 10) & 0x1)
- dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));
- }
-
- state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);
- state->rf_request =
- state->fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
- BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->
- freq_offset_khz_vhf);
-
- /* in ISDB-T 1seg we shift tuning frequency */
- if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1
- && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) {
- const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if;
- u8 found_offset = 0;
- u32 margin_khz = 100;
-
- if (LUT_offset != NULL) {
- while (LUT_offset->RF_freq != 0xffff) {
- if (((state->rf_request > (LUT_offset->RF_freq - margin_khz))
- && (state->rf_request < (LUT_offset->RF_freq + margin_khz)))
- && LUT_offset->std == state->fe->dtv_property_cache.delivery_system) {
- state->rf_request += LUT_offset->offset_khz;
- found_offset = 1;
- break;
- }
- LUT_offset++;
- }
- }
-
- if (found_offset == 0)
- state->rf_request += 400;
- }
- if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_cache.delivery_system)) {
- state->tuner_is_tuned = 0;
- state->current_rf = 0;
- state->current_standard = 0;
-
- tune = dib0090_tuning_table;
- if (state->identity.p1g)
- tune = dib0090_p1g_tuning_table;
-
- tmp = (state->identity.version >> 5) & 0x7;
-
- if (state->identity.in_soc) {
- if (state->config->force_cband_input) { /* Use the CBAND input for all band */
- if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF
- || state->current_band & BAND_UHF) {
- state->current_band = BAND_CBAND;
- if (state->config->is_dib7090e)
- tune = dib0090_tuning_table_cband_7090e_sensitivity;
- else
- tune = dib0090_tuning_table_cband_7090;
- }
- } else { /* Use the CBAND input for all band under UHF */
- if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) {
- state->current_band = BAND_CBAND;
- if (state->config->is_dib7090e)
- tune = dib0090_tuning_table_cband_7090e_sensitivity;
- else
- tune = dib0090_tuning_table_cband_7090;
- }
- }
- } else
- if (tmp == 0x4 || tmp == 0x7) {
- /* CBAND tuner version for VHF */
- if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == BAND_VHF) {
- state->current_band = BAND_CBAND; /* Force CBAND */
-
- tune = dib0090_tuning_table_fm_vhf_on_cband;
- if (state->identity.p1g)
- tune = dib0090_p1g_tuning_table_fm_vhf_on_cband;
- }
- }
-
- pll = dib0090_pll_table;
- if (state->identity.p1g)
- pll = dib0090_p1g_pll_table;
-
- /* Look for the interval */
- while (state->rf_request > tune->max_freq)
- tune++;
- while (state->rf_request > pll->max_freq)
- pll++;
-
- state->current_tune_table_index = tune;
- state->current_pll_table_index = pll;
-
- dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
-
- VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
-
- FREF = state->config->io.clock_khz;
- if (state->config->fref_clock_ratio != 0)
- FREF /= state->config->fref_clock_ratio;
-
- FBDiv = (VCOF_kHz / pll->topresc / FREF);
- Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
-
- if (Rest < LPF)
- Rest = 0;
- else if (Rest < 2 * LPF)
- Rest = 2 * LPF;
- else if (Rest > (FREF - LPF)) {
- Rest = 0;
- FBDiv += 1;
- } else if (Rest > (FREF - 2 * LPF))
- Rest = FREF - 2 * LPF;
- Rest = (Rest * 6528) / (FREF / 10);
- state->rest = Rest;
-
- /* external loop filter, otherwise:
- * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
- * lo6 = 0x0e34 */
-
- if (Rest == 0) {
- if (pll->vco_band)
- lo5 = 0x049f;
- else
- lo5 = 0x041f;
- } else {
- if (pll->vco_band)
- lo5 = 0x049e;
- else if (state->config->analog_output)
- lo5 = 0x041d;
- else
- lo5 = 0x041c;
- }
-
- if (state->identity.p1g) { /* Bias is done automatically in P1G */
- if (state->identity.in_soc) {
- if (state->identity.version == SOC_8090_P1G_11R1)
- lo5 = 0x46f;
- else
- lo5 = 0x42f;
- } else
- lo5 = 0x42c;
- }
-
- lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
-
- if (!state->config->io.pll_int_loop_filt) {
- if (state->identity.in_soc)
- lo6 = 0xff98;
- else if (state->identity.p1g || (Rest == 0))
- lo6 = 0xfff8;
- else
- lo6 = 0xff28;
- } else
- lo6 = (state->config->io.pll_int_loop_filt << 3);
-
- Den = 1;
-
- if (Rest > 0) {
- if (state->config->analog_output)
- lo6 |= (1 << 2) | 2;
- else {
- if (state->identity.in_soc)
- lo6 |= (1 << 2) | 2;
- else
- lo6 |= (1 << 2) | 2;
- }
- Den = 255;
- }
- dib0090_write_reg(state, 0x15, (u16) FBDiv);
- if (state->config->fref_clock_ratio != 0)
- dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
- else
- dib0090_write_reg(state, 0x16, (Den << 8) | 1);
- dib0090_write_reg(state, 0x17, (u16) Rest);
- dib0090_write_reg(state, 0x19, lo5);
- dib0090_write_reg(state, 0x1c, lo6);
-
- lo6 = tune->tuner_enable;
- if (state->config->analog_output)
- lo6 = (lo6 & 0xff9f) | 0x2;
-
- dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);
-
- }
-
- state->current_rf = state->rf_request;
- state->current_standard = state->fe->dtv_property_cache.delivery_system;
-
- ret = 20;
- state->calibrate = CAPTRIM_CAL; /* captrim serach now */
- }
-
- else if (*tune_state == CT_TUNER_STEP_0) { /* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */
- const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
-
- while (state->current_rf / 1000 > wbd->max_freq)
- wbd++;
-
- dib0090_write_reg(state, 0x1e, 0x07ff);
- dprintk("Final Captrim: %d", (u32) state->fcaptrim);
- dprintk("HFDIV code: %d", (u32) pll->hfdiv_code);
- dprintk("VCO = %d", (u32) pll->vco_band);
- dprintk("VCOF in kHz: %d ((%d*%d) << 1))", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request);
- dprintk("REFDIV: %d, FREF: %d", (u32) 1, (u32) state->config->io.clock_khz);
- dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
- dprintk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8),
- (u32) dib0090_read_reg(state, 0x1c) & 0x3);
-
-#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
- c = 4;
- i = 3;
-
- if (wbd->wbd_gain != 0)
- c = wbd->wbd_gain;
-
- state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));
- dib0090_write_reg(state, 0x10, state->wbdmux);
-
- if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) {
- dprintk("P1G : The cable band is selected and lna_tune = %d", tune->lna_tune);
- dib0090_write_reg(state, 0x09, tune->lna_bias);
- dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));
- } else
- dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);
-
- dib0090_write_reg(state, 0x0c, tune->v2i);
- dib0090_write_reg(state, 0x0d, tune->mix);
- dib0090_write_reg(state, 0x0e, tune->load);
- *tune_state = CT_TUNER_STEP_1;
-
- } else if (*tune_state == CT_TUNER_STEP_1) {
- /* initialize the lt gain register */
- state->rf_lt_def = 0x7c00;
-
- dib0090_set_bandwidth(state);
- state->tuner_is_tuned = 1;
-
- state->calibrate |= WBD_CAL;
- state->calibrate |= TEMP_CAL;
- *tune_state = CT_TUNER_STOP;
- } else
- ret = FE_CALLBACK_TIME_NEVER;
- return ret;
-}
-
-static int dib0090_release(struct dvb_frontend *fe)
-{
- kfree(fe->tuner_priv);
- fe->tuner_priv = NULL;
- return 0;
-}
-
-enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
-
- return state->tune_state;
-}
-
-EXPORT_SYMBOL(dib0090_get_tune_state);
-
-int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
-{
- struct dib0090_state *state = fe->tuner_priv;
-
- state->tune_state = tune_state;
- return 0;
-}
-
-EXPORT_SYMBOL(dib0090_set_tune_state);
-
-static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
-{
- struct dib0090_state *state = fe->tuner_priv;
-
- *frequency = 1000 * state->current_rf;
- return 0;
-}
-
-static int dib0090_set_params(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- u32 ret;
-
- state->tune_state = CT_TUNER_START;
-
- do {
- ret = dib0090_tune(fe);
- if (ret != FE_CALLBACK_TIME_NEVER)
- msleep(ret / 10);
- else
- break;
- } while (state->tune_state != CT_TUNER_STOP);
-
- return 0;
-}
-
-static const struct dvb_tuner_ops dib0090_ops = {
- .info = {
- .name = "DiBcom DiB0090",
- .frequency_min = 45000000,
- .frequency_max = 860000000,
- .frequency_step = 1000,
- },
- .release = dib0090_release,
-
- .init = dib0090_wakeup,
- .sleep = dib0090_sleep,
- .set_params = dib0090_set_params,
- .get_frequency = dib0090_get_frequency,
-};
-
-static const struct dvb_tuner_ops dib0090_fw_ops = {
- .info = {
- .name = "DiBcom DiB0090",
- .frequency_min = 45000000,
- .frequency_max = 860000000,
- .frequency_step = 1000,
- },
- .release = dib0090_release,
-
- .init = NULL,
- .sleep = NULL,
- .set_params = NULL,
- .get_frequency = NULL,
-};
-
-static const struct dib0090_wbd_slope dib0090_wbd_table_default[] = {
- {470, 0, 250, 0, 100, 4},
- {860, 51, 866, 21, 375, 4},
- {1700, 0, 800, 0, 850, 4},
- {2900, 0, 250, 0, 100, 6},
- {0xFFFF, 0, 0, 0, 0, 0},
-};
-
-struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
-{
- struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
- if (st == NULL)
- return NULL;
-
- st->config = config;
- st->i2c = i2c;
- st->fe = fe;
- mutex_init(&st->i2c_buffer_lock);
- fe->tuner_priv = st;
-
- if (config->wbd == NULL)
- st->current_wbd_table = dib0090_wbd_table_default;
- else
- st->current_wbd_table = config->wbd;
-
- if (dib0090_reset(fe) != 0)
- goto free_mem;
-
- printk(KERN_INFO "DiB0090: successfully identified\n");
- memcpy(&fe->ops.tuner_ops, &dib0090_ops, sizeof(struct dvb_tuner_ops));
-
- return fe;
- free_mem:
- kfree(st);
- fe->tuner_priv = NULL;
- return NULL;
-}
-
-EXPORT_SYMBOL(dib0090_register);
-
-struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
-{
- struct dib0090_fw_state *st = kzalloc(sizeof(struct dib0090_fw_state), GFP_KERNEL);
- if (st == NULL)
- return NULL;
-
- st->config = config;
- st->i2c = i2c;
- st->fe = fe;
- mutex_init(&st->i2c_buffer_lock);
- fe->tuner_priv = st;
-
- if (dib0090_fw_reset_digital(fe, st->config) != 0)
- goto free_mem;
-
- dprintk("DiB0090 FW: successfully identified");
- memcpy(&fe->ops.tuner_ops, &dib0090_fw_ops, sizeof(struct dvb_tuner_ops));
-
- return fe;
-free_mem:
- kfree(st);
- fe->tuner_priv = NULL;
- return NULL;
-}
-EXPORT_SYMBOL(dib0090_fw_register);
-
-MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
-MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>");
-MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib0090.h b/drivers/media/dvb/frontends/dib0090.h
deleted file mode 100644
index 781dc49de45..00000000000
--- a/drivers/media/dvb/frontends/dib0090.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Linux-DVB Driver for DiBcom's DiB0090 base-band RF Tuner.
- *
- * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- */
-#ifndef DIB0090_H
-#define DIB0090_H
-
-struct dvb_frontend;
-struct i2c_adapter;
-
-#define DEFAULT_DIB0090_I2C_ADDRESS 0x60
-
-struct dib0090_io_config {
- u32 clock_khz;
-
- u8 pll_bypass:1;
- u8 pll_range:1;
- u8 pll_prediv:6;
- u8 pll_loopdiv:6;
-
- u8 adc_clock_ratio; /* valid is 8, 7 ,6 */
- u16 pll_int_loop_filt;
-};
-
-struct dib0090_wbd_slope {
- u16 max_freq; /* for every frequency less than or equal to that field: this information is correct */
- u16 slope_cold;
- u16 offset_cold;
- u16 slope_hot;
- u16 offset_hot;
- u8 wbd_gain;
-};
-
-struct dib0090_low_if_offset_table {
- int std;
- u32 RF_freq;
- s32 offset_khz;
-};
-
-struct dib0090_config {
- struct dib0090_io_config io;
- int (*reset) (struct dvb_frontend *, int);
- int (*sleep) (struct dvb_frontend *, int);
-
- /* offset in kHz */
- int freq_offset_khz_uhf;
- int freq_offset_khz_vhf;
-
- int (*get_adc_power) (struct dvb_frontend *);
-
- u8 clkouttobamse:1; /* activate or deactivate clock output */
- u8 analog_output;
-
- u8 i2c_address;
- /* add drives and other things if necessary */
- u16 wbd_vhf_offset;
- u16 wbd_cband_offset;
- u8 use_pwm_agc;
- u8 clkoutdrive;
-
- u8 ls_cfg_pad_drv;
- u8 data_tx_drv;
-
- u8 in_soc;
- const struct dib0090_low_if_offset_table *low_if;
- u8 fref_clock_ratio;
- u16 force_cband_input;
- struct dib0090_wbd_slope *wbd;
- u8 is_dib7090e;
- u8 force_crystal_mode;
-};
-
-#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE))
-extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
-extern struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
-extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast);
-extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe);
-extern u16 dib0090_get_wbd_target(struct dvb_frontend *tuner);
-extern u16 dib0090_get_wbd_offset(struct dvb_frontend *fe);
-extern int dib0090_gain_control(struct dvb_frontend *fe);
-extern enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe);
-extern int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state);
-extern void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt);
-extern void dib0090_set_dc_servo(struct dvb_frontend *fe, u8 DC_servo_cutoff);
-extern int dib0090_set_switch(struct dvb_frontend *fe, u8 sw1, u8 sw2, u8 sw3);
-extern int dib0090_set_vga(struct dvb_frontend *fe, u8 onoff);
-extern int dib0090_update_rframp_7090(struct dvb_frontend *fe,
- u8 cfg_sensitivity);
-extern int dib0090_update_tuning_table_7090(struct dvb_frontend *fe,
- u8 cfg_sensitivity);
-#else
-static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0090_config *config)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-}
-
-static inline void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-}
-
-static inline u16 dib0090_get_wbd_target(struct dvb_frontend *tuner)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return 0;
-}
-
-static inline u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return 0;
-}
-
-static inline int dib0090_gain_control(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return CT_DONE;
-}
-
-static inline int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-}
-
-static inline void dib0090_set_dc_servo(struct dvb_frontend *fe, u8 DC_servo_cutoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-}
-
-static inline int dib0090_set_switch(struct dvb_frontend *fe,
- u8 sw1, u8 sw2, u8 sw3)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib0090_set_vga(struct dvb_frontend *fe, u8 onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib0090_update_rframp_7090(struct dvb_frontend *fe,
- u8 cfg_sensitivity)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib0090_update_tuning_table_7090(struct dvb_frontend *fe,
- u8 cfg_sensitivity)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-#endif
-
-#endif
diff --git a/drivers/media/dvb/frontends/dib3000.h b/drivers/media/dvb/frontends/dib3000.h
deleted file mode 100644
index 404f63a6f26..00000000000
--- a/drivers/media/dvb/frontends/dib3000.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * public header file of the frontend drivers for mobile DVB-T demodulators
- * DiBcom 3000M-B and DiBcom 3000P/M-C (http://www.dibcom.fr/)
- *
- * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
- *
- * based on GPL code from DibCom, which has
- *
- * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- *
- * Acknowledgements
- *
- * Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
- * sources, on which this driver (and the dvb-dibusb) are based.
- *
- * see Documentation/dvb/README.dvb-usb for more information
- *
- */
-
-#ifndef DIB3000_H
-#define DIB3000_H
-
-#include <linux/dvb/frontend.h>
-
-struct dib3000_config
-{
- /* the demodulator's i2c address */
- u8 demod_address;
-};
-
-struct dib_fe_xfer_ops
-{
- /* pid and transfer handling is done in the demodulator */
- int (*pid_parse)(struct dvb_frontend *fe, int onoff);
- int (*fifo_ctrl)(struct dvb_frontend *fe, int onoff);
- int (*pid_ctrl)(struct dvb_frontend *fe, int index, int pid, int onoff);
- int (*tuner_pass_ctrl)(struct dvb_frontend *fe, int onoff, u8 pll_ctrl);
-};
-
-#if defined(CONFIG_DVB_DIB3000MB) || (defined(CONFIG_DVB_DIB3000MB_MODULE) && defined(MODULE))
-extern struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
- struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops);
-#else
-static inline struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
- struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif // CONFIG_DVB_DIB3000MB
-
-#endif // DIB3000_H
diff --git a/drivers/media/dvb/frontends/dib3000mb.c b/drivers/media/dvb/frontends/dib3000mb.c
deleted file mode 100644
index af91e0c9233..00000000000
--- a/drivers/media/dvb/frontends/dib3000mb.c
+++ /dev/null
@@ -1,829 +0,0 @@
-/*
- * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
- * DiBcom (http://www.dibcom.fr/)
- *
- * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
- *
- * based on GPL code from DibCom, which has
- *
- * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- *
- * Acknowledgements
- *
- * Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
- * sources, on which this driver (and the dvb-dibusb) are based.
- *
- * see Documentation/dvb/README.dvb-usb for more information
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-
-#include "dvb_frontend.h"
-
-#include "dib3000.h"
-#include "dib3000mb_priv.h"
-
-/* Version information */
-#define DRIVER_VERSION "0.1"
-#define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
-#define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
-
-#define deb_info(args...) dprintk(0x01,args)
-#define deb_i2c(args...) dprintk(0x02,args)
-#define deb_srch(args...) dprintk(0x04,args)
-#define deb_info(args...) dprintk(0x01,args)
-#define deb_xfer(args...) dprintk(0x02,args)
-#define deb_setf(args...) dprintk(0x04,args)
-#define deb_getf(args...) dprintk(0x08,args)
-
-static int dib3000_read_reg(struct dib3000_state *state, u16 reg)
-{
- u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff };
- u8 rb[2];
- struct i2c_msg msg[] = {
- { .addr = state->config.demod_address, .flags = 0, .buf = wb, .len = 2 },
- { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 },
- };
-
- if (i2c_transfer(state->i2c, msg, 2) != 2)
- deb_i2c("i2c read error\n");
-
- deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,
- (rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]);
-
- return (rb[0] << 8) | rb[1];
-}
-
-static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val)
-{
- u8 b[] = {
- (reg >> 8) & 0xff, reg & 0xff,
- (val >> 8) & 0xff, val & 0xff,
- };
- struct i2c_msg msg[] = {
- { .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 }
- };
- deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val);
-
- return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0;
-}
-
-static int dib3000_search_status(u16 irq,u16 lock)
-{
- if (irq & 0x02) {
- if (lock & 0x01) {
- deb_srch("auto search succeeded\n");
- return 1; // auto search succeeded
- } else {
- deb_srch("auto search not successful\n");
- return 0; // auto search failed
- }
- } else if (irq & 0x01) {
- deb_srch("auto search failed\n");
- return 0; // auto search failed
- }
- return -1; // try again
-}
-
-/* for auto search */
-static u16 dib3000_seq[2][2][2] = /* fft,gua, inv */
- { /* fft */
- { /* gua */
- { 0, 1 }, /* 0 0 { 0,1 } */
- { 3, 9 }, /* 0 1 { 0,1 } */
- },
- {
- { 2, 5 }, /* 1 0 { 0,1 } */
- { 6, 11 }, /* 1 1 { 0,1 } */
- }
- };
-
-static int dib3000mb_get_frontend(struct dvb_frontend* fe);
-
-static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner)
-{
- struct dib3000_state* state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- fe_code_rate_t fe_cr = FEC_NONE;
- int search_state, seq;
-
- if (tuner && fe->ops.tuner_ops.set_params) {
- fe->ops.tuner_ops.set_params(fe);
- if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
-
- deb_setf("bandwidth: ");
- switch (c->bandwidth_hz) {
- case 8000000:
- deb_setf("8 MHz\n");
- wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
- wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
- break;
- case 7000000:
- deb_setf("7 MHz\n");
- wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
- wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
- break;
- case 6000000:
- deb_setf("6 MHz\n");
- wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
- wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
- break;
- case 0:
- return -EOPNOTSUPP;
- default:
- err("unknown bandwidth value.");
- return -EINVAL;
- }
- }
- wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
-
- deb_setf("transmission mode: ");
- switch (c->transmission_mode) {
- case TRANSMISSION_MODE_2K:
- deb_setf("2k\n");
- wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
- break;
- case TRANSMISSION_MODE_8K:
- deb_setf("8k\n");
- wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
- break;
- case TRANSMISSION_MODE_AUTO:
- deb_setf("auto\n");
- break;
- default:
- return -EINVAL;
- }
-
- deb_setf("guard: ");
- switch (c->guard_interval) {
- case GUARD_INTERVAL_1_32:
- deb_setf("1_32\n");
- wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
- break;
- case GUARD_INTERVAL_1_16:
- deb_setf("1_16\n");
- wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
- break;
- case GUARD_INTERVAL_1_8:
- deb_setf("1_8\n");
- wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
- break;
- case GUARD_INTERVAL_1_4:
- deb_setf("1_4\n");
- wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
- break;
- case GUARD_INTERVAL_AUTO:
- deb_setf("auto\n");
- break;
- default:
- return -EINVAL;
- }
-
- deb_setf("inversion: ");
- switch (c->inversion) {
- case INVERSION_OFF:
- deb_setf("off\n");
- wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
- break;
- case INVERSION_AUTO:
- deb_setf("auto ");
- break;
- case INVERSION_ON:
- deb_setf("on\n");
- wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
- break;
- default:
- return -EINVAL;
- }
-
- deb_setf("modulation: ");
- switch (c->modulation) {
- case QPSK:
- deb_setf("qpsk\n");
- wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
- break;
- case QAM_16:
- deb_setf("qam16\n");
- wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
- break;
- case QAM_64:
- deb_setf("qam64\n");
- wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
- break;
- case QAM_AUTO:
- break;
- default:
- return -EINVAL;
- }
- deb_setf("hierarchy: ");
- switch (c->hierarchy) {
- case HIERARCHY_NONE:
- deb_setf("none ");
- /* fall through */
- case HIERARCHY_1:
- deb_setf("alpha=1\n");
- wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
- break;
- case HIERARCHY_2:
- deb_setf("alpha=2\n");
- wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
- break;
- case HIERARCHY_4:
- deb_setf("alpha=4\n");
- wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
- break;
- case HIERARCHY_AUTO:
- deb_setf("alpha=auto\n");
- break;
- default:
- return -EINVAL;
- }
-
- deb_setf("hierarchy: ");
- if (c->hierarchy == HIERARCHY_NONE) {
- deb_setf("none\n");
- wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
- wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
- fe_cr = c->code_rate_HP;
- } else if (c->hierarchy != HIERARCHY_AUTO) {
- deb_setf("on\n");
- wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
- wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
- fe_cr = c->code_rate_LP;
- }
- deb_setf("fec: ");
- switch (fe_cr) {
- case FEC_1_2:
- deb_setf("1_2\n");
- wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
- break;
- case FEC_2_3:
- deb_setf("2_3\n");
- wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
- break;
- case FEC_3_4:
- deb_setf("3_4\n");
- wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
- break;
- case FEC_5_6:
- deb_setf("5_6\n");
- wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
- break;
- case FEC_7_8:
- deb_setf("7_8\n");
- wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
- break;
- case FEC_NONE:
- deb_setf("none ");
- break;
- case FEC_AUTO:
- deb_setf("auto\n");
- break;
- default:
- return -EINVAL;
- }
-
- seq = dib3000_seq
- [c->transmission_mode == TRANSMISSION_MODE_AUTO]
- [c->guard_interval == GUARD_INTERVAL_AUTO]
- [c->inversion == INVERSION_AUTO];
-
- deb_setf("seq? %d\n", seq);
-
- wr(DIB3000MB_REG_SEQ, seq);
-
- wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
-
- if (c->transmission_mode == TRANSMISSION_MODE_2K) {
- if (c->guard_interval == GUARD_INTERVAL_1_8) {
- wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
- } else {
- wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
- }
-
- wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
- } else {
- wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
- }
-
- wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
- wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
- wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
-
- wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
-
- wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
-
- wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
- wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
-
- /* wait for AGC lock */
- msleep(70);
-
- wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
-
- /* something has to be auto searched */
- if (c->modulation == QAM_AUTO ||
- c->hierarchy == HIERARCHY_AUTO ||
- fe_cr == FEC_AUTO ||
- c->inversion == INVERSION_AUTO) {
- int as_count=0;
-
- deb_setf("autosearch enabled.\n");
-
- wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
-
- wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
- wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
-
- while ((search_state =
- dib3000_search_status(
- rd(DIB3000MB_REG_AS_IRQ_PENDING),
- rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
- msleep(1);
-
- deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count);
-
- if (search_state == 1) {
- if (dib3000mb_get_frontend(fe) == 0) {
- deb_setf("reading tuning data from frontend succeeded.\n");
- return dib3000mb_set_frontend(fe, 0);
- }
- }
-
- } else {
- wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
- wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
- }
-
- return 0;
-}
-
-static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
-{
- struct dib3000_state* state = fe->demodulator_priv;
-
- deb_info("dib3000mb is getting up.\n");
- wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
-
- wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
-
- wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
- wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
-
- wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
-
- wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
-
- wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
- wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
-
- wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
-
- wr_foreach(dib3000mb_reg_impulse_noise,
- dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
-
- wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
-
- wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
-
- wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
-
- wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
-
- wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
-
- wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
- wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
- wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
- wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
-
- wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
-
- wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
- wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
- wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
- wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
- wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
- wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
- wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
- wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
- wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
- wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
- wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
- wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
- wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
- wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
- wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
-
- wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
-
- wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
- wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
- wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
-
- wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
-
- wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
- wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
- wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
- wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
- wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
- wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
-
- wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
-
- return 0;
-}
-
-static int dib3000mb_get_frontend(struct dvb_frontend* fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct dib3000_state* state = fe->demodulator_priv;
- fe_code_rate_t *cr;
- u16 tps_val;
- int inv_test1,inv_test2;
- u32 dds_val, threshold = 0x800000;
-
- if (!rd(DIB3000MB_REG_TPS_LOCK))
- return 0;
-
- dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
- deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
- if (dds_val < threshold)
- inv_test1 = 0;
- else if (dds_val == threshold)
- inv_test1 = 1;
- else
- inv_test1 = 2;
-
- dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
- deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
- if (dds_val < threshold)
- inv_test2 = 0;
- else if (dds_val == threshold)
- inv_test2 = 1;
- else
- inv_test2 = 2;
-
- c->inversion =
- ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
- ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
- INVERSION_ON : INVERSION_OFF;
-
- deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion);
-
- switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
- case DIB3000_CONSTELLATION_QPSK:
- deb_getf("QPSK ");
- c->modulation = QPSK;
- break;
- case DIB3000_CONSTELLATION_16QAM:
- deb_getf("QAM16 ");
- c->modulation = QAM_16;
- break;
- case DIB3000_CONSTELLATION_64QAM:
- deb_getf("QAM64 ");
- c->modulation = QAM_64;
- break;
- default:
- err("Unexpected constellation returned by TPS (%d)", tps_val);
- break;
- }
- deb_getf("TPS: %d\n", tps_val);
-
- if (rd(DIB3000MB_REG_TPS_HRCH)) {
- deb_getf("HRCH ON\n");
- cr = &c->code_rate_LP;
- c->code_rate_HP = FEC_NONE;
- switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
- case DIB3000_ALPHA_0:
- deb_getf("HIERARCHY_NONE ");
- c->hierarchy = HIERARCHY_NONE;
- break;
- case DIB3000_ALPHA_1:
- deb_getf("HIERARCHY_1 ");
- c->hierarchy = HIERARCHY_1;
- break;
- case DIB3000_ALPHA_2:
- deb_getf("HIERARCHY_2 ");
- c->hierarchy = HIERARCHY_2;
- break;
- case DIB3000_ALPHA_4:
- deb_getf("HIERARCHY_4 ");
- c->hierarchy = HIERARCHY_4;
- break;
- default:
- err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
- break;
- }
- deb_getf("TPS: %d\n", tps_val);
-
- tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
- } else {
- deb_getf("HRCH OFF\n");
- cr = &c->code_rate_HP;
- c->code_rate_LP = FEC_NONE;
- c->hierarchy = HIERARCHY_NONE;
-
- tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
- }
-
- switch (tps_val) {
- case DIB3000_FEC_1_2:
- deb_getf("FEC_1_2 ");
- *cr = FEC_1_2;
- break;
- case DIB3000_FEC_2_3:
- deb_getf("FEC_2_3 ");
- *cr = FEC_2_3;
- break;
- case DIB3000_FEC_3_4:
- deb_getf("FEC_3_4 ");
- *cr = FEC_3_4;
- break;
- case DIB3000_FEC_5_6:
- deb_getf("FEC_5_6 ");
- *cr = FEC_4_5;
- break;
- case DIB3000_FEC_7_8:
- deb_getf("FEC_7_8 ");
- *cr = FEC_7_8;
- break;
- default:
- err("Unexpected FEC returned by TPS (%d)", tps_val);
- break;
- }
- deb_getf("TPS: %d\n",tps_val);
-
- switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
- case DIB3000_GUARD_TIME_1_32:
- deb_getf("GUARD_INTERVAL_1_32 ");
- c->guard_interval = GUARD_INTERVAL_1_32;
- break;
- case DIB3000_GUARD_TIME_1_16:
- deb_getf("GUARD_INTERVAL_1_16 ");
- c->guard_interval = GUARD_INTERVAL_1_16;
- break;
- case DIB3000_GUARD_TIME_1_8:
- deb_getf("GUARD_INTERVAL_1_8 ");
- c->guard_interval = GUARD_INTERVAL_1_8;
- break;
- case DIB3000_GUARD_TIME_1_4:
- deb_getf("GUARD_INTERVAL_1_4 ");
- c->guard_interval = GUARD_INTERVAL_1_4;
- break;
- default:
- err("Unexpected Guard Time returned by TPS (%d)", tps_val);
- break;
- }
- deb_getf("TPS: %d\n", tps_val);
-
- switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
- case DIB3000_TRANSMISSION_MODE_2K:
- deb_getf("TRANSMISSION_MODE_2K ");
- c->transmission_mode = TRANSMISSION_MODE_2K;
- break;
- case DIB3000_TRANSMISSION_MODE_8K:
- deb_getf("TRANSMISSION_MODE_8K ");
- c->transmission_mode = TRANSMISSION_MODE_8K;
- break;
- default:
- err("unexpected transmission mode return by TPS (%d)", tps_val);
- break;
- }
- deb_getf("TPS: %d\n", tps_val);
-
- return 0;
-}
-
-static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
-{
- struct dib3000_state* state = fe->demodulator_priv;
-
- *stat = 0;
-
- if (rd(DIB3000MB_REG_AGC_LOCK))
- *stat |= FE_HAS_SIGNAL;
- if (rd(DIB3000MB_REG_CARRIER_LOCK))
- *stat |= FE_HAS_CARRIER;
- if (rd(DIB3000MB_REG_VIT_LCK))
- *stat |= FE_HAS_VITERBI;
- if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
- *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
-
- deb_getf("actual status is %2x\n",*stat);
-
- deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
- rd(DIB3000MB_REG_TPS_LOCK),
- rd(DIB3000MB_REG_TPS_QAM),
- rd(DIB3000MB_REG_TPS_HRCH),
- rd(DIB3000MB_REG_TPS_VIT_ALPHA),
- rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
- rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
- rd(DIB3000MB_REG_TPS_GUARD_TIME),
- rd(DIB3000MB_REG_TPS_FFT),
- rd(DIB3000MB_REG_TPS_CELL_ID));
-
- //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
- return 0;
-}
-
-static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
-{
- struct dib3000_state* state = fe->demodulator_priv;
-
- *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
- return 0;
-}
-
-/* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
-static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
-{
- struct dib3000_state* state = fe->demodulator_priv;
-
- *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
- return 0;
-}
-
-static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
-{
- struct dib3000_state* state = fe->demodulator_priv;
- short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
- int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
- rd(DIB3000MB_REG_NOISE_POWER_LSB);
- *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
- return 0;
-}
-
-static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
-{
- struct dib3000_state* state = fe->demodulator_priv;
-
- *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
- return 0;
-}
-
-static int dib3000mb_sleep(struct dvb_frontend* fe)
-{
- struct dib3000_state* state = fe->demodulator_priv;
- deb_info("dib3000mb is going to bed.\n");
- wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
- return 0;
-}
-
-static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
-{
- tune->min_delay_ms = 800;
- return 0;
-}
-
-static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
-{
- return dib3000mb_fe_init(fe, 0);
-}
-
-static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe)
-{
- return dib3000mb_set_frontend(fe, 1);
-}
-
-static void dib3000mb_release(struct dvb_frontend* fe)
-{
- struct dib3000_state *state = fe->demodulator_priv;
- kfree(state);
-}
-
-/* pid filter and transfer stuff */
-static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
-{
- struct dib3000_state *state = fe->demodulator_priv;
- pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
- wr(index+DIB3000MB_REG_FIRST_PID,pid);
- return 0;
-}
-
-static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
-{
- struct dib3000_state *state = fe->demodulator_priv;
-
- deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
- if (onoff) {
- wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
- } else {
- wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
- }
- return 0;
-}
-
-static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
-{
- struct dib3000_state *state = fe->demodulator_priv;
- deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
- wr(DIB3000MB_REG_PID_PARSE,onoff);
- return 0;
-}
-
-static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
-{
- struct dib3000_state *state = fe->demodulator_priv;
- if (onoff) {
- wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
- } else {
- wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
- }
- return 0;
-}
-
-static struct dvb_frontend_ops dib3000mb_ops;
-
-struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
- struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
-{
- struct dib3000_state* state = NULL;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL);
- if (state == NULL)
- goto error;
-
- /* setup the state */
- state->i2c = i2c;
- memcpy(&state->config,config,sizeof(struct dib3000_config));
-
- /* check for the correct demod */
- if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
- goto error;
-
- if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
- goto error;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
-
- /* set the xfer operations */
- xfer_ops->pid_parse = dib3000mb_pid_parse;
- xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
- xfer_ops->pid_ctrl = dib3000mb_pid_control;
- xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
-
- return &state->frontend;
-
-error:
- kfree(state);
- return NULL;
-}
-
-static struct dvb_frontend_ops dib3000mb_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "DiBcom 3000M-B DVB-T",
- .frequency_min = 44250000,
- .frequency_max = 867250000,
- .frequency_stepsize = 62500,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_RECOVER |
- FE_CAN_HIERARCHY_AUTO,
- },
-
- .release = dib3000mb_release,
-
- .init = dib3000mb_fe_init_nonmobile,
- .sleep = dib3000mb_sleep,
-
- .set_frontend = dib3000mb_set_frontend_and_tuner,
- .get_frontend = dib3000mb_get_frontend,
- .get_tune_settings = dib3000mb_fe_get_tune_settings,
-
- .read_status = dib3000mb_read_status,
- .read_ber = dib3000mb_read_ber,
- .read_signal_strength = dib3000mb_read_signal_strength,
- .read_snr = dib3000mb_read_snr,
- .read_ucblocks = dib3000mb_read_unc_blocks,
-};
-
-MODULE_AUTHOR(DRIVER_AUTHOR);
-MODULE_DESCRIPTION(DRIVER_DESC);
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(dib3000mb_attach);
diff --git a/drivers/media/dvb/frontends/dib3000mb_priv.h b/drivers/media/dvb/frontends/dib3000mb_priv.h
deleted file mode 100644
index 9dc235aa44b..00000000000
--- a/drivers/media/dvb/frontends/dib3000mb_priv.h
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
- * dib3000mb_priv.h
- *
- * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- *
- * for more information see dib3000mb.c .
- */
-
-#ifndef __DIB3000MB_PRIV_H_INCLUDED__
-#define __DIB3000MB_PRIV_H_INCLUDED__
-
-/* info and err, taken from usb.h, if there is anything available like by default. */
-#define err(format, arg...) printk(KERN_ERR "dib3000: " format "\n" , ## arg)
-#define info(format, arg...) printk(KERN_INFO "dib3000: " format "\n" , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "dib3000: " format "\n" , ## arg)
-
-/* handy shortcuts */
-#define rd(reg) dib3000_read_reg(state,reg)
-
-#define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \
- { err("while sending 0x%04x to 0x%04x.",val,reg); return -EREMOTEIO; }
-
-#define wr_foreach(a,v) { int i; \
- if (sizeof(a) != sizeof(v)) \
- err("sizeof: %zu %zu is different",sizeof(a),sizeof(v));\
- for (i=0; i < sizeof(a)/sizeof(u16); i++) \
- wr(a[i],v[i]); \
- }
-
-#define set_or(reg,val) wr(reg,rd(reg) | val)
-
-#define set_and(reg,val) wr(reg,rd(reg) & val)
-
-/* debug */
-
-#define dprintk(level,args...) \
- do { if ((debug & level)) { printk(args); } } while (0)
-
-/* mask for enabling a specific pid for the pid_filter */
-#define DIB3000_ACTIVATE_PID_FILTERING (0x2000)
-
-/* common values for tuning */
-#define DIB3000_ALPHA_0 ( 0)
-#define DIB3000_ALPHA_1 ( 1)
-#define DIB3000_ALPHA_2 ( 2)
-#define DIB3000_ALPHA_4 ( 4)
-
-#define DIB3000_CONSTELLATION_QPSK ( 0)
-#define DIB3000_CONSTELLATION_16QAM ( 1)
-#define DIB3000_CONSTELLATION_64QAM ( 2)
-
-#define DIB3000_GUARD_TIME_1_32 ( 0)
-#define DIB3000_GUARD_TIME_1_16 ( 1)
-#define DIB3000_GUARD_TIME_1_8 ( 2)
-#define DIB3000_GUARD_TIME_1_4 ( 3)
-
-#define DIB3000_TRANSMISSION_MODE_2K ( 0)
-#define DIB3000_TRANSMISSION_MODE_8K ( 1)
-
-#define DIB3000_SELECT_LP ( 0)
-#define DIB3000_SELECT_HP ( 1)
-
-#define DIB3000_FEC_1_2 ( 1)
-#define DIB3000_FEC_2_3 ( 2)
-#define DIB3000_FEC_3_4 ( 3)
-#define DIB3000_FEC_5_6 ( 5)
-#define DIB3000_FEC_7_8 ( 7)
-
-#define DIB3000_HRCH_OFF ( 0)
-#define DIB3000_HRCH_ON ( 1)
-
-#define DIB3000_DDS_INVERSION_OFF ( 0)
-#define DIB3000_DDS_INVERSION_ON ( 1)
-
-#define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8))
-#define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7)))
-
-#define DIB3000_REG_MANUFACTOR_ID ( 1025)
-#define DIB3000_I2C_ID_DIBCOM (0x01b3)
-
-#define DIB3000_REG_DEVICE_ID ( 1026)
-#define DIB3000MB_DEVICE_ID (0x3000)
-#define DIB3000MC_DEVICE_ID (0x3001)
-#define DIB3000P_DEVICE_ID (0x3002)
-
-/* frontend state */
-struct dib3000_state {
- struct i2c_adapter* i2c;
-
-/* configuration settings */
- struct dib3000_config config;
-
- struct dvb_frontend frontend;
- int timing_offset;
- int timing_offset_comp_done;
-
- u32 last_tuned_bw;
- u32 last_tuned_freq;
-};
-
-/* register addresses and some of their default values */
-
-/* restart subsystems */
-#define DIB3000MB_REG_RESTART ( 0)
-
-#define DIB3000MB_RESTART_OFF ( 0)
-#define DIB3000MB_RESTART_AUTO_SEARCH (1 << 1)
-#define DIB3000MB_RESTART_CTRL (1 << 2)
-#define DIB3000MB_RESTART_AGC (1 << 3)
-
-/* FFT size */
-#define DIB3000MB_REG_FFT ( 1)
-
-/* Guard time */
-#define DIB3000MB_REG_GUARD_TIME ( 2)
-
-/* QAM */
-#define DIB3000MB_REG_QAM ( 3)
-
-/* Alpha coefficient high priority Viterbi algorithm */
-#define DIB3000MB_REG_VIT_ALPHA ( 4)
-
-/* spectrum inversion */
-#define DIB3000MB_REG_DDS_INV ( 5)
-
-/* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */
-#define DIB3000MB_REG_DDS_FREQ_MSB ( 6)
-#define DIB3000MB_REG_DDS_FREQ_LSB ( 7)
-#define DIB3000MB_DDS_FREQ_MSB ( 178)
-#define DIB3000MB_DDS_FREQ_LSB ( 8990)
-
-/* timing frequency (carrier spacing) */
-static u16 dib3000mb_reg_timing_freq[] = { 8,9 };
-static u16 dib3000mb_timing_freq[][2] = {
- { 126 , 48873 }, /* 6 MHz */
- { 147 , 57019 }, /* 7 MHz */
- { 168 , 65164 }, /* 8 MHz */
-};
-
-/* impulse noise parameter */
-/* 36 ??? */
-
-static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 };
-
-enum dib3000mb_impulse_noise_type {
- DIB3000MB_IMPNOISE_OFF,
- DIB3000MB_IMPNOISE_MOBILE,
- DIB3000MB_IMPNOISE_FIXED,
- DIB3000MB_IMPNOISE_DEFAULT
-};
-
-static u16 dib3000mb_impulse_noise_values[][5] = {
- { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */
- { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */
- { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */
- { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */
-};
-
-/*
- * Dual Automatic-Gain-Control
- * - gains RF in tuner (AGC1)
- * - gains IF after filtering (AGC2)
- */
-
-/* also from 16 to 18 */
-static u16 dib3000mb_reg_agc_gain[] = {
- 19,20,21,22,23,24,25,26,27,28,29,30,31,32
-};
-
-static u16 dib3000mb_default_agc_gain[] =
- { 0x0001, 52429, 623, 128, 166, 195, 61, /* RF ??? */
- 0x0001, 53766, 38011, 0, 90, 33, 23 }; /* IF ??? */
-
-/* phase noise */
-/* 36 is set when setting the impulse noise */
-static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 };
-
-static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 };
-
-/* lock duration */
-static u16 dib3000mb_reg_lock_duration[] = { 39,40 };
-static u16 dib3000mb_default_lock_duration[] = { 135, 135 };
-
-/* AGC loop bandwidth */
-static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 };
-
-static u16 dib3000mb_agc_bandwidth_low[] =
- { 2088, 10, 2088, 10, 3448, 5, 3448, 5 };
-static u16 dib3000mb_agc_bandwidth_high[] =
- { 2349, 5, 2349, 5, 2586, 2, 2586, 2 };
-
-/*
- * lock0 definition (coff_lock)
- */
-#define DIB3000MB_REG_LOCK0_MASK ( 51)
-#define DIB3000MB_LOCK0_DEFAULT ( 4)
-
-/*
- * lock1 definition (cpil_lock)
- * for auto search
- * which values hide behind the lock masks
- */
-#define DIB3000MB_REG_LOCK1_MASK ( 52)
-#define DIB3000MB_LOCK1_SEARCH_4 (0x0004)
-#define DIB3000MB_LOCK1_SEARCH_2048 (0x0800)
-#define DIB3000MB_LOCK1_DEFAULT (0x0001)
-
-/*
- * lock2 definition (fec_lock) */
-#define DIB3000MB_REG_LOCK2_MASK ( 53)
-#define DIB3000MB_LOCK2_DEFAULT (0x0080)
-
-/*
- * SEQ ? what was that again ... :)
- * changes when, inversion, guard time and fft is
- * either automatically detected or not
- */
-#define DIB3000MB_REG_SEQ ( 54)
-
-/* bandwidth */
-static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 };
-static u16 dib3000mb_bandwidth_6mhz[] =
- { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 };
-
-static u16 dib3000mb_bandwidth_7mhz[] =
- { 0, 28, 64421, 96, 39973, 483, 3255, 0, 1000, 0, 1010, 1, 45264 };
-
-static u16 dib3000mb_bandwidth_8mhz[] =
- { 0, 25, 23600, 84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 };
-
-#define DIB3000MB_REG_UNK_68 ( 68)
-#define DIB3000MB_UNK_68 ( 0)
-
-#define DIB3000MB_REG_UNK_69 ( 69)
-#define DIB3000MB_UNK_69 ( 0)
-
-#define DIB3000MB_REG_UNK_71 ( 71)
-#define DIB3000MB_UNK_71 ( 0)
-
-#define DIB3000MB_REG_UNK_77 ( 77)
-#define DIB3000MB_UNK_77 ( 6)
-
-#define DIB3000MB_REG_UNK_78 ( 78)
-#define DIB3000MB_UNK_78 (0x0080)
-
-/* isi */
-#define DIB3000MB_REG_ISI ( 79)
-#define DIB3000MB_ISI_ACTIVATE ( 0)
-#define DIB3000MB_ISI_INHIBIT ( 1)
-
-/* sync impovement */
-#define DIB3000MB_REG_SYNC_IMPROVEMENT ( 84)
-#define DIB3000MB_SYNC_IMPROVE_2K_1_8 ( 3)
-#define DIB3000MB_SYNC_IMPROVE_DEFAULT ( 0)
-
-/* phase noise compensation inhibition */
-#define DIB3000MB_REG_PHASE_NOISE ( 87)
-#define DIB3000MB_PHASE_NOISE_DEFAULT ( 0)
-
-#define DIB3000MB_REG_UNK_92 ( 92)
-#define DIB3000MB_UNK_92 (0x0080)
-
-#define DIB3000MB_REG_UNK_96 ( 96)
-#define DIB3000MB_UNK_96 (0x0010)
-
-#define DIB3000MB_REG_UNK_97 ( 97)
-#define DIB3000MB_UNK_97 (0x0009)
-
-/* mobile mode ??? */
-#define DIB3000MB_REG_MOBILE_MODE ( 101)
-#define DIB3000MB_MOBILE_MODE_ON ( 1)
-#define DIB3000MB_MOBILE_MODE_OFF ( 0)
-
-#define DIB3000MB_REG_UNK_106 ( 106)
-#define DIB3000MB_UNK_106 (0x0080)
-
-#define DIB3000MB_REG_UNK_107 ( 107)
-#define DIB3000MB_UNK_107 (0x0080)
-
-#define DIB3000MB_REG_UNK_108 ( 108)
-#define DIB3000MB_UNK_108 (0x0080)
-
-/* fft */
-#define DIB3000MB_REG_UNK_121 ( 121)
-#define DIB3000MB_UNK_121_2K ( 7)
-#define DIB3000MB_UNK_121_DEFAULT ( 5)
-
-#define DIB3000MB_REG_UNK_122 ( 122)
-#define DIB3000MB_UNK_122 ( 2867)
-
-/* QAM for mobile mode */
-#define DIB3000MB_REG_MOBILE_MODE_QAM ( 126)
-#define DIB3000MB_MOBILE_MODE_QAM_64 ( 3)
-#define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 ( 1)
-#define DIB3000MB_MOBILE_MODE_QAM_OFF ( 0)
-
-/*
- * data diversity when having more than one chip on-board
- * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY
- */
-#define DIB3000MB_REG_DATA_IN_DIVERSITY ( 127)
-#define DIB3000MB_DATA_DIVERSITY_IN_OFF ( 0)
-#define DIB3000MB_DATA_DIVERSITY_IN_ON ( 2)
-
-/* vit hrch */
-#define DIB3000MB_REG_VIT_HRCH ( 128)
-
-/* vit code rate */
-#define DIB3000MB_REG_VIT_CODE_RATE ( 129)
-
-/* vit select hp */
-#define DIB3000MB_REG_VIT_HP ( 130)
-
-/* time frame for Bit-Error-Rate calculation */
-#define DIB3000MB_REG_BERLEN ( 135)
-#define DIB3000MB_BERLEN_LONG ( 0)
-#define DIB3000MB_BERLEN_DEFAULT ( 1)
-#define DIB3000MB_BERLEN_MEDIUM ( 2)
-#define DIB3000MB_BERLEN_SHORT ( 3)
-
-/* 142 - 152 FIFO parameters
- * which is what ?
- */
-
-#define DIB3000MB_REG_FIFO_142 ( 142)
-#define DIB3000MB_FIFO_142 ( 0)
-
-/* MPEG2 TS output mode */
-#define DIB3000MB_REG_MPEG2_OUT_MODE ( 143)
-#define DIB3000MB_MPEG2_OUT_MODE_204 ( 0)
-#define DIB3000MB_MPEG2_OUT_MODE_188 ( 1)
-
-#define DIB3000MB_REG_PID_PARSE ( 144)
-#define DIB3000MB_PID_PARSE_INHIBIT ( 0)
-#define DIB3000MB_PID_PARSE_ACTIVATE ( 1)
-
-#define DIB3000MB_REG_FIFO ( 145)
-#define DIB3000MB_FIFO_INHIBIT ( 1)
-#define DIB3000MB_FIFO_ACTIVATE ( 0)
-
-#define DIB3000MB_REG_FIFO_146 ( 146)
-#define DIB3000MB_FIFO_146 ( 3)
-
-#define DIB3000MB_REG_FIFO_147 ( 147)
-#define DIB3000MB_FIFO_147 (0x0100)
-
-/*
- * pidfilter
- * it is not a hardware pidfilter but a filter which drops all pids
- * except the ones set. Necessary because of the limited USB1.1 bandwidth.
- * regs 153-168
- */
-
-#define DIB3000MB_REG_FIRST_PID ( 153)
-#define DIB3000MB_NUM_PIDS ( 16)
-
-/*
- * output mode
- * USB devices have to use 'slave'-mode
- * see also DIB3000MB_REG_ELECT_OUT_MODE
- */
-#define DIB3000MB_REG_OUTPUT_MODE ( 169)
-#define DIB3000MB_OUTPUT_MODE_GATED_CLK ( 0)
-#define DIB3000MB_OUTPUT_MODE_CONT_CLK ( 1)
-#define DIB3000MB_OUTPUT_MODE_SERIAL ( 2)
-#define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY ( 5)
-#define DIB3000MB_OUTPUT_MODE_SLAVE ( 6)
-
-/* irq event mask */
-#define DIB3000MB_REG_IRQ_EVENT_MASK ( 170)
-#define DIB3000MB_IRQ_EVENT_MASK ( 0)
-
-/* filter coefficients */
-static u16 dib3000mb_reg_filter_coeffs[] = {
- 171, 172, 173, 174, 175, 176, 177, 178,
- 179, 180, 181, 182, 183, 184, 185, 186,
- 188, 189, 190, 191, 192, 194
-};
-
-static u16 dib3000mb_filter_coeffs[] = {
- 226, 160, 29,
- 979, 998, 19,
- 22, 1019, 1006,
- 1022, 12, 6,
- 1017, 1017, 3,
- 6, 1019,
- 1021, 2, 3,
- 1, 0,
-};
-
-/*
- * mobile algorithm (when you are moving with your device)
- * but not faster than 90 km/h
- */
-#define DIB3000MB_REG_MOBILE_ALGO ( 195)
-#define DIB3000MB_MOBILE_ALGO_ON ( 0)
-#define DIB3000MB_MOBILE_ALGO_OFF ( 1)
-
-/* multiple demodulators algorithm */
-#define DIB3000MB_REG_MULTI_DEMOD_MSB ( 206)
-#define DIB3000MB_REG_MULTI_DEMOD_LSB ( 207)
-
-/* terminator, no more demods */
-#define DIB3000MB_MULTI_DEMOD_MSB ( 32767)
-#define DIB3000MB_MULTI_DEMOD_LSB ( 4095)
-
-/* bring the device into a known */
-#define DIB3000MB_REG_RESET_DEVICE ( 1024)
-#define DIB3000MB_RESET_DEVICE (0x812c)
-#define DIB3000MB_RESET_DEVICE_RST ( 0)
-
-/* hardware clock configuration */
-#define DIB3000MB_REG_CLOCK ( 1027)
-#define DIB3000MB_CLOCK_DEFAULT (0x9000)
-#define DIB3000MB_CLOCK_DIVERSITY (0x92b0)
-
-/* power down config */
-#define DIB3000MB_REG_POWER_CONTROL ( 1028)
-#define DIB3000MB_POWER_DOWN ( 1)
-#define DIB3000MB_POWER_UP ( 0)
-
-/* electrical output mode */
-#define DIB3000MB_REG_ELECT_OUT_MODE ( 1029)
-#define DIB3000MB_ELECT_OUT_MODE_OFF ( 0)
-#define DIB3000MB_ELECT_OUT_MODE_ON ( 1)
-
-/* set the tuner i2c address */
-#define DIB3000MB_REG_TUNER ( 1089)
-
-/* monitoring registers (read only) */
-
-/* agc loop locked (size: 1) */
-#define DIB3000MB_REG_AGC_LOCK ( 324)
-
-/* agc power (size: 16) */
-#define DIB3000MB_REG_AGC_POWER ( 325)
-
-/* agc1 value (16) */
-#define DIB3000MB_REG_AGC1_VALUE ( 326)
-
-/* agc2 value (16) */
-#define DIB3000MB_REG_AGC2_VALUE ( 327)
-
-/* total RF power (16), can be used for signal strength */
-#define DIB3000MB_REG_RF_POWER ( 328)
-
-/* dds_frequency with offset (24) */
-#define DIB3000MB_REG_DDS_VALUE_MSB ( 339)
-#define DIB3000MB_REG_DDS_VALUE_LSB ( 340)
-
-/* timing offset signed (24) */
-#define DIB3000MB_REG_TIMING_OFFSET_MSB ( 341)
-#define DIB3000MB_REG_TIMING_OFFSET_LSB ( 342)
-
-/* fft start position (13) */
-#define DIB3000MB_REG_FFT_WINDOW_POS ( 353)
-
-/* carriers locked (1) */
-#define DIB3000MB_REG_CARRIER_LOCK ( 355)
-
-/* noise power (24) */
-#define DIB3000MB_REG_NOISE_POWER_MSB ( 372)
-#define DIB3000MB_REG_NOISE_POWER_LSB ( 373)
-
-#define DIB3000MB_REG_MOBILE_NOISE_MSB ( 374)
-#define DIB3000MB_REG_MOBILE_NOISE_LSB ( 375)
-
-/*
- * signal power (16), this and the above can be
- * used to calculate the signal/noise - ratio
- */
-#define DIB3000MB_REG_SIGNAL_POWER ( 380)
-
-/* mer (24) */
-#define DIB3000MB_REG_MER_MSB ( 381)
-#define DIB3000MB_REG_MER_LSB ( 382)
-
-/*
- * Transmission Parameter Signalling (TPS)
- * the following registers can be used to get TPS-information.
- * The values are according to the DVB-T standard.
- */
-
-/* TPS locked (1) */
-#define DIB3000MB_REG_TPS_LOCK ( 394)
-
-/* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */
-#define DIB3000MB_REG_TPS_QAM ( 398)
-
-/* hierarchy from TPS (1) */
-#define DIB3000MB_REG_TPS_HRCH ( 399)
-
-/* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */
-#define DIB3000MB_REG_TPS_VIT_ALPHA ( 400)
-
-/* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */
-#define DIB3000MB_REG_TPS_CODE_RATE_HP ( 401)
-
-/* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */
-#define DIB3000MB_REG_TPS_CODE_RATE_LP ( 402)
-
-/* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */
-#define DIB3000MB_REG_TPS_GUARD_TIME ( 403)
-
-/* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */
-#define DIB3000MB_REG_TPS_FFT ( 404)
-
-/* cell id from TPS (16) */
-#define DIB3000MB_REG_TPS_CELL_ID ( 406)
-
-/* TPS (68) */
-#define DIB3000MB_REG_TPS_1 ( 408)
-#define DIB3000MB_REG_TPS_2 ( 409)
-#define DIB3000MB_REG_TPS_3 ( 410)
-#define DIB3000MB_REG_TPS_4 ( 411)
-#define DIB3000MB_REG_TPS_5 ( 412)
-
-/* bit error rate (before RS correction) (21) */
-#define DIB3000MB_REG_BER_MSB ( 414)
-#define DIB3000MB_REG_BER_LSB ( 415)
-
-/* packet error rate (uncorrected TS packets) (16) */
-#define DIB3000MB_REG_PACKET_ERROR_RATE ( 417)
-
-/* uncorrected packet count (16) */
-#define DIB3000MB_REG_UNC ( 420)
-
-/* viterbi locked (1) */
-#define DIB3000MB_REG_VIT_LCK ( 421)
-
-/* viterbi inidcator (16) */
-#define DIB3000MB_REG_VIT_INDICATOR ( 422)
-
-/* transport stream sync lock (1) */
-#define DIB3000MB_REG_TS_SYNC_LOCK ( 423)
-
-/* transport stream RS lock (1) */
-#define DIB3000MB_REG_TS_RS_LOCK ( 424)
-
-/* lock mask 0 value (1) */
-#define DIB3000MB_REG_LOCK0_VALUE ( 425)
-
-/* lock mask 1 value (1) */
-#define DIB3000MB_REG_LOCK1_VALUE ( 426)
-
-/* lock mask 2 value (1) */
-#define DIB3000MB_REG_LOCK2_VALUE ( 427)
-
-/* interrupt pending for auto search */
-#define DIB3000MB_REG_AS_IRQ_PENDING ( 434)
-
-#endif
diff --git a/drivers/media/dvb/frontends/dib3000mc.c b/drivers/media/dvb/frontends/dib3000mc.c
deleted file mode 100644
index ffad181a969..00000000000
--- a/drivers/media/dvb/frontends/dib3000mc.c
+++ /dev/null
@@ -1,940 +0,0 @@
-/*
- * Driver for DiBcom DiB3000MC/P-demodulator.
- *
- * Copyright (C) 2004-7 DiBcom (http://www.dibcom.fr/)
- * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
- *
- * This code is partially based on the previous dib3000mc.c .
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/i2c.h>
-
-#include "dvb_frontend.h"
-
-#include "dib3000mc.h"
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
-
-static int buggy_sfn_workaround;
-module_param(buggy_sfn_workaround, int, 0644);
-MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
-
-#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB3000MC/P:"); printk(args); printk("\n"); } } while (0)
-
-struct dib3000mc_state {
- struct dvb_frontend demod;
- struct dib3000mc_config *cfg;
-
- u8 i2c_addr;
- struct i2c_adapter *i2c_adap;
-
- struct dibx000_i2c_master i2c_master;
-
- u32 timf;
-
- u32 current_bandwidth;
-
- u16 dev_id;
-
- u8 sfn_workaround_active :1;
-};
-
-static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg)
-{
- u8 wb[2] = { (reg >> 8) | 0x80, reg & 0xff };
- u8 rb[2];
- struct i2c_msg msg[2] = {
- { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 },
- { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 },
- };
-
- if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
- dprintk("i2c read error on %d\n",reg);
-
- return (rb[0] << 8) | rb[1];
-}
-
-static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val)
-{
- u8 b[4] = {
- (reg >> 8) & 0xff, reg & 0xff,
- (val >> 8) & 0xff, val & 0xff,
- };
- struct i2c_msg msg = {
- .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
- };
- return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
-}
-
-static int dib3000mc_identify(struct dib3000mc_state *state)
-{
- u16 value;
- if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) {
- dprintk("-E- DiB3000MC/P: wrong Vendor ID (read=0x%x)\n",value);
- return -EREMOTEIO;
- }
-
- value = dib3000mc_read_word(state, 1026);
- if (value != 0x3001 && value != 0x3002) {
- dprintk("-E- DiB3000MC/P: wrong Device ID (%x)\n",value);
- return -EREMOTEIO;
- }
- state->dev_id = value;
-
- dprintk("-I- found DiB3000MC/P: %x\n",state->dev_id);
-
- return 0;
-}
-
-static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset)
-{
- u32 timf;
-
- if (state->timf == 0) {
- timf = 1384402; // default value for 8MHz
- if (update_offset)
- msleep(200); // first time we do an update
- } else
- timf = state->timf;
-
- timf *= (bw / 1000);
-
- if (update_offset) {
- s16 tim_offs = dib3000mc_read_word(state, 416);
-
- if (tim_offs & 0x2000)
- tim_offs -= 0x4000;
-
- if (nfft == TRANSMISSION_MODE_2K)
- tim_offs *= 4;
-
- timf += tim_offs;
- state->timf = timf / (bw / 1000);
- }
-
- dprintk("timf: %d\n", timf);
-
- dib3000mc_write_word(state, 23, (u16) (timf >> 16));
- dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff);
-
- return 0;
-}
-
-static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state)
-{
- u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb;
- if (state->cfg->pwm3_inversion) {
- reg_51 = (2 << 14) | (0 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
- reg_52 |= (1 << 2);
- } else {
- reg_51 = (2 << 14) | (4 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
- reg_52 |= (1 << 8);
- }
- dib3000mc_write_word(state, 51, reg_51);
- dib3000mc_write_word(state, 52, reg_52);
-
- if (state->cfg->use_pwm3)
- dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0));
- else
- dib3000mc_write_word(state, 245, 0);
-
- dib3000mc_write_word(state, 1040, 0x3);
- return 0;
-}
-
-static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode)
-{
- int ret = 0;
- u16 fifo_threshold = 1792;
- u16 outreg = 0;
- u16 outmode = 0;
- u16 elecout = 1;
- u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */
-
- dprintk("-I- Setting output mode for demod %p to %d\n",
- &state->demod, mode);
-
- switch (mode) {
- case OUTMODE_HIGH_Z: // disable
- elecout = 0;
- break;
- case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
- outmode = 0;
- break;
- case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
- outmode = 1;
- break;
- case OUTMODE_MPEG2_SERIAL: // STBs with serial input
- outmode = 2;
- break;
- case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
- elecout = 3;
- /*ADDR @ 206 :
- P_smo_error_discard [1;6:6] = 0
- P_smo_rs_discard [1;5:5] = 0
- P_smo_pid_parse [1;4:4] = 0
- P_smo_fifo_flush [1;3:3] = 0
- P_smo_mode [2;2:1] = 11
- P_smo_ovf_prot [1;0:0] = 0
- */
- smo_reg |= 3 << 1;
- fifo_threshold = 512;
- outmode = 5;
- break;
- case OUTMODE_DIVERSITY:
- outmode = 4;
- elecout = 1;
- break;
- default:
- dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod);
- outmode = 0;
- break;
- }
-
- if ((state->cfg->output_mpeg2_in_188_bytes))
- smo_reg |= (1 << 5); // P_smo_rs_discard [1;5:5] = 1
-
- outreg = dib3000mc_read_word(state, 244) & 0x07FF;
- outreg |= (outmode << 11);
- ret |= dib3000mc_write_word(state, 244, outreg);
- ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/
- ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */
- ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */
- return ret;
-}
-
-static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw)
-{
- u16 bw_cfg[6] = { 0 };
- u16 imp_bw_cfg[3] = { 0 };
- u16 reg;
-
-/* settings here are for 27.7MHz */
- switch (bw) {
- case 8000:
- bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6; bw_cfg[5] = 0xab20;
- imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7;
- break;
-
- case 7000:
- bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3; bw_cfg[5] = 0x0cb7;
- imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0;
- break;
-
- case 6000:
- bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233; bw_cfg[5] = 0x8ed5;
- imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089;
- break;
-
- case 5000:
- bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4; bw_cfg[5] = 0x4500;
- imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072;
- break;
-
- default: return -EINVAL;
- }
-
- for (reg = 6; reg < 12; reg++)
- dib3000mc_write_word(state, reg, bw_cfg[reg - 6]);
- dib3000mc_write_word(state, 12, 0x0000);
- dib3000mc_write_word(state, 13, 0x03e8);
- dib3000mc_write_word(state, 14, 0x0000);
- dib3000mc_write_word(state, 15, 0x03f2);
- dib3000mc_write_word(state, 16, 0x0001);
- dib3000mc_write_word(state, 17, 0xb0d0);
- // P_sec_len
- dib3000mc_write_word(state, 18, 0x0393);
- dib3000mc_write_word(state, 19, 0x8700);
-
- for (reg = 55; reg < 58; reg++)
- dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]);
-
- // Timing configuration
- dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0);
-
- return 0;
-}
-
-static u16 impulse_noise_val[29] =
-
-{
- 0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c, 0x3ffe, 0x7f3,
- 0x2d94, 0x76, 0x53d, 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3, 0x3feb, 0x7d2,
- 0x365e, 0x76, 0x48c, 0x3ffe, 0x5b3, 0x3feb, 0x76, 0x0000, 0xd
-};
-
-static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft)
-{
- u16 i;
- for (i = 58; i < 87; i++)
- dib3000mc_write_word(state, i, impulse_noise_val[i-58]);
-
- if (nfft == TRANSMISSION_MODE_8K) {
- dib3000mc_write_word(state, 58, 0x3b);
- dib3000mc_write_word(state, 84, 0x00);
- dib3000mc_write_word(state, 85, 0x8200);
- }
-
- dib3000mc_write_word(state, 34, 0x1294);
- dib3000mc_write_word(state, 35, 0x1ff8);
- if (mode == 1)
- dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10));
-}
-
-static int dib3000mc_init(struct dvb_frontend *demod)
-{
- struct dib3000mc_state *state = demod->demodulator_priv;
- struct dibx000_agc_config *agc = state->cfg->agc;
-
- // Restart Configuration
- dib3000mc_write_word(state, 1027, 0x8000);
- dib3000mc_write_word(state, 1027, 0x0000);
-
- // power up the demod + mobility configuration
- dib3000mc_write_word(state, 140, 0x0000);
- dib3000mc_write_word(state, 1031, 0);
-
- if (state->cfg->mobile_mode) {
- dib3000mc_write_word(state, 139, 0x0000);
- dib3000mc_write_word(state, 141, 0x0000);
- dib3000mc_write_word(state, 175, 0x0002);
- dib3000mc_write_word(state, 1032, 0x0000);
- } else {
- dib3000mc_write_word(state, 139, 0x0001);
- dib3000mc_write_word(state, 141, 0x0000);
- dib3000mc_write_word(state, 175, 0x0000);
- dib3000mc_write_word(state, 1032, 0x012C);
- }
- dib3000mc_write_word(state, 1033, 0x0000);
-
- // P_clk_cfg
- dib3000mc_write_word(state, 1037, 0x3130);
-
- // other configurations
-
- // P_ctrl_sfreq
- dib3000mc_write_word(state, 33, (5 << 0));
- dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0));
-
- // Phase noise control
- // P_fft_phacor_inh, P_fft_phacor_cpe, P_fft_powrange
- dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0));
-
- if (state->cfg->phase_noise_mode == 0)
- dib3000mc_write_word(state, 111, 0x00);
- else
- dib3000mc_write_word(state, 111, 0x02);
-
- // P_agc_global
- dib3000mc_write_word(state, 50, 0x8000);
-
- // agc setup misc
- dib3000mc_setup_pwm_state(state);
-
- // P_agc_counter_lock
- dib3000mc_write_word(state, 53, 0x87);
- // P_agc_counter_unlock
- dib3000mc_write_word(state, 54, 0x87);
-
- /* agc */
- dib3000mc_write_word(state, 36, state->cfg->max_time);
- dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0));
- dib3000mc_write_word(state, 38, state->cfg->pwm3_value);
- dib3000mc_write_word(state, 39, state->cfg->ln_adc_level);
-
- // set_agc_loop_Bw
- dib3000mc_write_word(state, 40, 0x0179);
- dib3000mc_write_word(state, 41, 0x03f0);
-
- dib3000mc_write_word(state, 42, agc->agc1_max);
- dib3000mc_write_word(state, 43, agc->agc1_min);
- dib3000mc_write_word(state, 44, agc->agc2_max);
- dib3000mc_write_word(state, 45, agc->agc2_min);
- dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
- dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
- dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
- dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
-
-// Begin: TimeOut registers
- // P_pha3_thres
- dib3000mc_write_word(state, 110, 3277);
- // P_timf_alpha = 6, P_corm_alpha = 6, P_corm_thres = 0x80
- dib3000mc_write_word(state, 26, 0x6680);
- // lock_mask0
- dib3000mc_write_word(state, 1, 4);
- // lock_mask1
- dib3000mc_write_word(state, 2, 4);
- // lock_mask2
- dib3000mc_write_word(state, 3, 0x1000);
- // P_search_maxtrial=1
- dib3000mc_write_word(state, 5, 1);
-
- dib3000mc_set_bandwidth(state, 8000);
-
- // div_lock_mask
- dib3000mc_write_word(state, 4, 0x814);
-
- dib3000mc_write_word(state, 21, (1 << 9) | 0x164);
- dib3000mc_write_word(state, 22, 0x463d);
-
- // Spurious rm cfg
- // P_cspu_regul, P_cspu_win_cut
- dib3000mc_write_word(state, 120, 0x200f);
- // P_adp_selec_monit
- dib3000mc_write_word(state, 134, 0);
-
- // Fec cfg
- dib3000mc_write_word(state, 195, 0x10);
-
- // diversity register: P_dvsy_sync_wait..
- dib3000mc_write_word(state, 180, 0x2FF0);
-
- // Impulse noise configuration
- dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K);
-
- // output mode set-up
- dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
-
- /* close the i2c-gate */
- dib3000mc_write_word(state, 769, (1 << 7) );
-
- return 0;
-}
-
-static int dib3000mc_sleep(struct dvb_frontend *demod)
-{
- struct dib3000mc_state *state = demod->demodulator_priv;
-
- dib3000mc_write_word(state, 1031, 0xFFFF);
- dib3000mc_write_word(state, 1032, 0xFFFF);
- dib3000mc_write_word(state, 1033, 0xFFF0);
-
- return 0;
-}
-
-static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam)
-{
- u16 cfg[4] = { 0 },reg;
- switch (qam) {
- case QPSK:
- cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0;
- break;
- case QAM_16:
- cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0;
- break;
- case QAM_64:
- cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8;
- break;
- }
- for (reg = 129; reg < 133; reg++)
- dib3000mc_write_word(state, reg, cfg[reg - 129]);
-}
-
-static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state,
- struct dtv_frontend_properties *ch, u16 seq)
-{
- u16 value;
- u32 bw = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
-
- dib3000mc_set_bandwidth(state, bw);
- dib3000mc_set_timing(state, ch->transmission_mode, bw, 0);
-
-// if (boost)
-// dib3000mc_write_word(state, 100, (11 << 6) + 6);
-// else
- dib3000mc_write_word(state, 100, (16 << 6) + 9);
-
- dib3000mc_write_word(state, 1027, 0x0800);
- dib3000mc_write_word(state, 1027, 0x0000);
-
- //Default cfg isi offset adp
- dib3000mc_write_word(state, 26, 0x6680);
- dib3000mc_write_word(state, 29, 0x1273);
- dib3000mc_write_word(state, 33, 5);
- dib3000mc_set_adp_cfg(state, QAM_16);
- dib3000mc_write_word(state, 133, 15564);
-
- dib3000mc_write_word(state, 12 , 0x0);
- dib3000mc_write_word(state, 13 , 0x3e8);
- dib3000mc_write_word(state, 14 , 0x0);
- dib3000mc_write_word(state, 15 , 0x3f2);
-
- dib3000mc_write_word(state, 93,0);
- dib3000mc_write_word(state, 94,0);
- dib3000mc_write_word(state, 95,0);
- dib3000mc_write_word(state, 96,0);
- dib3000mc_write_word(state, 97,0);
- dib3000mc_write_word(state, 98,0);
-
- dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode);
-
- value = 0;
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
- default:
- case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
- }
- switch (ch->guard_interval) {
- case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
- case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
- case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
- default:
- case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
- }
- switch (ch->modulation) {
- case QPSK: value |= (0 << 3); break;
- case QAM_16: value |= (1 << 3); break;
- default:
- case QAM_64: value |= (2 << 3); break;
- }
- switch (HIERARCHY_1) {
- case HIERARCHY_2: value |= 2; break;
- case HIERARCHY_4: value |= 4; break;
- default:
- case HIERARCHY_1: value |= 1; break;
- }
- dib3000mc_write_word(state, 0, value);
- dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
-
- value = 0;
- if (ch->hierarchy == 1)
- value |= (1 << 4);
- if (1 == 1)
- value |= 1;
- switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
- case FEC_2_3: value |= (2 << 1); break;
- case FEC_3_4: value |= (3 << 1); break;
- case FEC_5_6: value |= (5 << 1); break;
- case FEC_7_8: value |= (7 << 1); break;
- default:
- case FEC_1_2: value |= (1 << 1); break;
- }
- dib3000mc_write_word(state, 181, value);
-
- // diversity synchro delay add 50% SFN margin
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_8K: value = 256; break;
- case TRANSMISSION_MODE_2K:
- default: value = 64; break;
- }
- switch (ch->guard_interval) {
- case GUARD_INTERVAL_1_16: value *= 2; break;
- case GUARD_INTERVAL_1_8: value *= 4; break;
- case GUARD_INTERVAL_1_4: value *= 8; break;
- default:
- case GUARD_INTERVAL_1_32: value *= 1; break;
- }
- value <<= 4;
- value |= dib3000mc_read_word(state, 180) & 0x000f;
- dib3000mc_write_word(state, 180, value);
-
- // restart demod
- value = dib3000mc_read_word(state, 0);
- dib3000mc_write_word(state, 0, value | (1 << 9));
- dib3000mc_write_word(state, 0, value);
-
- msleep(30);
-
- dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->transmission_mode);
-}
-
-static int dib3000mc_autosearch_start(struct dvb_frontend *demod)
-{
- struct dtv_frontend_properties *chan = &demod->dtv_property_cache;
- struct dib3000mc_state *state = demod->demodulator_priv;
- u16 reg;
-// u32 val;
- struct dtv_frontend_properties schan;
-
- schan = *chan;
-
- /* TODO what is that ? */
-
- /* a channel for autosearch */
- schan.transmission_mode = TRANSMISSION_MODE_8K;
- schan.guard_interval = GUARD_INTERVAL_1_32;
- schan.modulation = QAM_64;
- schan.code_rate_HP = FEC_2_3;
- schan.code_rate_LP = FEC_2_3;
- schan.hierarchy = 0;
-
- dib3000mc_set_channel_cfg(state, &schan, 11);
-
- reg = dib3000mc_read_word(state, 0);
- dib3000mc_write_word(state, 0, reg | (1 << 8));
- dib3000mc_read_word(state, 511);
- dib3000mc_write_word(state, 0, reg);
-
- return 0;
-}
-
-static int dib3000mc_autosearch_is_irq(struct dvb_frontend *demod)
-{
- struct dib3000mc_state *state = demod->demodulator_priv;
- u16 irq_pending = dib3000mc_read_word(state, 511);
-
- if (irq_pending & 0x1) // failed
- return 1;
-
- if (irq_pending & 0x2) // succeeded
- return 2;
-
- return 0; // still pending
-}
-
-static int dib3000mc_tune(struct dvb_frontend *demod)
-{
- struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
- struct dib3000mc_state *state = demod->demodulator_priv;
-
- // ** configure demod **
- dib3000mc_set_channel_cfg(state, ch, 0);
-
- // activates isi
- if (state->sfn_workaround_active) {
- dprintk("SFN workaround is active\n");
- dib3000mc_write_word(state, 29, 0x1273);
- dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift
- } else {
- dib3000mc_write_word(state, 29, 0x1073);
- dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift
- }
-
- dib3000mc_set_adp_cfg(state, (u8)ch->modulation);
- if (ch->transmission_mode == TRANSMISSION_MODE_8K) {
- dib3000mc_write_word(state, 26, 38528);
- dib3000mc_write_word(state, 33, 8);
- } else {
- dib3000mc_write_word(state, 26, 30336);
- dib3000mc_write_word(state, 33, 6);
- }
-
- if (dib3000mc_read_word(state, 509) & 0x80)
- dib3000mc_set_timing(state, ch->transmission_mode,
- BANDWIDTH_TO_KHZ(ch->bandwidth_hz), 1);
-
- return 0;
-}
-
-struct i2c_adapter * dib3000mc_get_tuner_i2c_master(struct dvb_frontend *demod, int gating)
-{
- struct dib3000mc_state *st = demod->demodulator_priv;
- return dibx000_get_i2c_adapter(&st->i2c_master, DIBX000_I2C_INTERFACE_TUNER, gating);
-}
-
-EXPORT_SYMBOL(dib3000mc_get_tuner_i2c_master);
-
-static int dib3000mc_get_frontend(struct dvb_frontend* fe)
-{
- struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
- struct dib3000mc_state *state = fe->demodulator_priv;
- u16 tps = dib3000mc_read_word(state,458);
-
- fep->inversion = INVERSION_AUTO;
-
- fep->bandwidth_hz = state->current_bandwidth;
-
- switch ((tps >> 8) & 0x1) {
- case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break;
- case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break;
- }
-
- switch (tps & 0x3) {
- case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break;
- case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break;
- case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break;
- case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break;
- }
-
- switch ((tps >> 13) & 0x3) {
- case 0: fep->modulation = QPSK; break;
- case 1: fep->modulation = QAM_16; break;
- case 2:
- default: fep->modulation = QAM_64; break;
- }
-
- /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
- /* (tps >> 12) & 0x1 == hrch is used, (tps >> 9) & 0x7 == alpha */
-
- fep->hierarchy = HIERARCHY_NONE;
- switch ((tps >> 5) & 0x7) {
- case 1: fep->code_rate_HP = FEC_1_2; break;
- case 2: fep->code_rate_HP = FEC_2_3; break;
- case 3: fep->code_rate_HP = FEC_3_4; break;
- case 5: fep->code_rate_HP = FEC_5_6; break;
- case 7:
- default: fep->code_rate_HP = FEC_7_8; break;
-
- }
-
- switch ((tps >> 2) & 0x7) {
- case 1: fep->code_rate_LP = FEC_1_2; break;
- case 2: fep->code_rate_LP = FEC_2_3; break;
- case 3: fep->code_rate_LP = FEC_3_4; break;
- case 5: fep->code_rate_LP = FEC_5_6; break;
- case 7:
- default: fep->code_rate_LP = FEC_7_8; break;
- }
-
- return 0;
-}
-
-static int dib3000mc_set_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
- struct dib3000mc_state *state = fe->demodulator_priv;
- int ret;
-
- dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
-
- state->current_bandwidth = fep->bandwidth_hz;
- dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
-
- /* maybe the parameter has been changed */
- state->sfn_workaround_active = buggy_sfn_workaround;
-
- if (fe->ops.tuner_ops.set_params) {
- fe->ops.tuner_ops.set_params(fe);
- msleep(100);
- }
-
- if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
- fep->guard_interval == GUARD_INTERVAL_AUTO ||
- fep->modulation == QAM_AUTO ||
- fep->code_rate_HP == FEC_AUTO) {
- int i = 1000, found;
-
- dib3000mc_autosearch_start(fe);
- do {
- msleep(1);
- found = dib3000mc_autosearch_is_irq(fe);
- } while (found == 0 && i--);
-
- dprintk("autosearch returns: %d\n",found);
- if (found == 0 || found == 1)
- return 0; // no channel found
-
- dib3000mc_get_frontend(fe);
- }
-
- ret = dib3000mc_tune(fe);
-
- /* make this a config parameter */
- dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO);
- return ret;
-}
-
-static int dib3000mc_read_status(struct dvb_frontend *fe, fe_status_t *stat)
-{
- struct dib3000mc_state *state = fe->demodulator_priv;
- u16 lock = dib3000mc_read_word(state, 509);
-
- *stat = 0;
-
- if (lock & 0x8000)
- *stat |= FE_HAS_SIGNAL;
- if (lock & 0x3000)
- *stat |= FE_HAS_CARRIER;
- if (lock & 0x0100)
- *stat |= FE_HAS_VITERBI;
- if (lock & 0x0010)
- *stat |= FE_HAS_SYNC;
- if (lock & 0x0008)
- *stat |= FE_HAS_LOCK;
-
- return 0;
-}
-
-static int dib3000mc_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct dib3000mc_state *state = fe->demodulator_priv;
- *ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501);
- return 0;
-}
-
-static int dib3000mc_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
-{
- struct dib3000mc_state *state = fe->demodulator_priv;
- *unc = dib3000mc_read_word(state, 508);
- return 0;
-}
-
-static int dib3000mc_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
-{
- struct dib3000mc_state *state = fe->demodulator_priv;
- u16 val = dib3000mc_read_word(state, 392);
- *strength = 65535 - val;
- return 0;
-}
-
-static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
-{
- *snr = 0x0000;
- return 0;
-}
-
-static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
-{
- tune->min_delay_ms = 1000;
- return 0;
-}
-
-static void dib3000mc_release(struct dvb_frontend *fe)
-{
- struct dib3000mc_state *state = fe->demodulator_priv;
- dibx000_exit_i2c_master(&state->i2c_master);
- kfree(state);
-}
-
-int dib3000mc_pid_control(struct dvb_frontend *fe, int index, int pid,int onoff)
-{
- struct dib3000mc_state *state = fe->demodulator_priv;
- dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0);
- return 0;
-}
-EXPORT_SYMBOL(dib3000mc_pid_control);
-
-int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
-{
- struct dib3000mc_state *state = fe->demodulator_priv;
- u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4);
- tmp |= (onoff << 4);
- return dib3000mc_write_word(state, 206, tmp);
-}
-EXPORT_SYMBOL(dib3000mc_pid_parse);
-
-void dib3000mc_set_config(struct dvb_frontend *fe, struct dib3000mc_config *cfg)
-{
- struct dib3000mc_state *state = fe->demodulator_priv;
- state->cfg = cfg;
-}
-EXPORT_SYMBOL(dib3000mc_set_config);
-
-int dib3000mc_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib3000mc_config cfg[])
-{
- struct dib3000mc_state *dmcst;
- int k;
- u8 new_addr;
-
- static u8 DIB3000MC_I2C_ADDRESS[] = {20,22,24,26};
-
- dmcst = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL);
- if (dmcst == NULL)
- return -ENOMEM;
-
- dmcst->i2c_adap = i2c;
-
- for (k = no_of_demods-1; k >= 0; k--) {
- dmcst->cfg = &cfg[k];
-
- /* designated i2c address */
- new_addr = DIB3000MC_I2C_ADDRESS[k];
- dmcst->i2c_addr = new_addr;
- if (dib3000mc_identify(dmcst) != 0) {
- dmcst->i2c_addr = default_addr;
- if (dib3000mc_identify(dmcst) != 0) {
- dprintk("-E- DiB3000P/MC #%d: not identified\n", k);
- kfree(dmcst);
- return -ENODEV;
- }
- }
-
- dib3000mc_set_output_mode(dmcst, OUTMODE_MPEG2_PAR_CONT_CLK);
-
- // set new i2c address and force divstr (Bit 1) to value 0 (Bit 0)
- dib3000mc_write_word(dmcst, 1024, (new_addr << 3) | 0x1);
- dmcst->i2c_addr = new_addr;
- }
-
- for (k = 0; k < no_of_demods; k++) {
- dmcst->cfg = &cfg[k];
- dmcst->i2c_addr = DIB3000MC_I2C_ADDRESS[k];
-
- dib3000mc_write_word(dmcst, 1024, dmcst->i2c_addr << 3);
-
- /* turn off data output */
- dib3000mc_set_output_mode(dmcst, OUTMODE_HIGH_Z);
- }
-
- kfree(dmcst);
- return 0;
-}
-EXPORT_SYMBOL(dib3000mc_i2c_enumeration);
-
-static struct dvb_frontend_ops dib3000mc_ops;
-
-struct dvb_frontend * dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib3000mc_config *cfg)
-{
- struct dvb_frontend *demod;
- struct dib3000mc_state *st;
- st = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL);
- if (st == NULL)
- return NULL;
-
- st->cfg = cfg;
- st->i2c_adap = i2c_adap;
- st->i2c_addr = i2c_addr;
-
- demod = &st->demod;
- demod->demodulator_priv = st;
- memcpy(&st->demod.ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
-
- if (dib3000mc_identify(st) != 0)
- goto error;
-
- dibx000_init_i2c_master(&st->i2c_master, DIB3000MC, st->i2c_adap, st->i2c_addr);
-
- dib3000mc_write_word(st, 1037, 0x3130);
-
- return demod;
-
-error:
- kfree(st);
- return NULL;
-}
-EXPORT_SYMBOL(dib3000mc_attach);
-
-static struct dvb_frontend_ops dib3000mc_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "DiBcom 3000MC/P",
- .frequency_min = 44250000,
- .frequency_max = 867250000,
- .frequency_stepsize = 62500,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_RECOVER |
- FE_CAN_HIERARCHY_AUTO,
- },
-
- .release = dib3000mc_release,
-
- .init = dib3000mc_init,
- .sleep = dib3000mc_sleep,
-
- .set_frontend = dib3000mc_set_frontend,
- .get_tune_settings = dib3000mc_fe_get_tune_settings,
- .get_frontend = dib3000mc_get_frontend,
-
- .read_status = dib3000mc_read_status,
- .read_ber = dib3000mc_read_ber,
- .read_signal_strength = dib3000mc_read_signal_strength,
- .read_snr = dib3000mc_read_snr,
- .read_ucblocks = dib3000mc_read_unc_blocks,
-};
-
-MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
-MODULE_DESCRIPTION("Driver for the DiBcom 3000MC/P COFDM demodulator");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib3000mc.h b/drivers/media/dvb/frontends/dib3000mc.h
deleted file mode 100644
index d75ffad2d75..00000000000
--- a/drivers/media/dvb/frontends/dib3000mc.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Driver for DiBcom DiB3000MC/P-demodulator.
- *
- * Copyright (C) 2004-6 DiBcom (http://www.dibcom.fr/)
- * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher\@desy.de)
- *
- * This code is partially based on the previous dib3000mc.c .
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- */
-#ifndef DIB3000MC_H
-#define DIB3000MC_H
-
-#include "dibx000_common.h"
-
-struct dib3000mc_config {
- struct dibx000_agc_config *agc;
-
- u8 phase_noise_mode;
- u8 impulse_noise_mode;
-
- u8 pwm3_inversion;
- u8 use_pwm3;
- u16 pwm3_value;
-
- u16 max_time;
- u16 ln_adc_level;
-
- u8 agc_command1 :1;
- u8 agc_command2 :1;
-
- u8 mobile_mode;
-
- u8 output_mpeg2_in_188_bytes;
-};
-
-#define DEFAULT_DIB3000MC_I2C_ADDRESS 16
-#define DEFAULT_DIB3000P_I2C_ADDRESS 24
-
-#if defined(CONFIG_DVB_DIB3000MC) || (defined(CONFIG_DVB_DIB3000MC_MODULE) && \
- defined(MODULE))
-extern struct dvb_frontend *dib3000mc_attach(struct i2c_adapter *i2c_adap,
- u8 i2c_addr,
- struct dib3000mc_config *cfg);
-extern int dib3000mc_i2c_enumeration(struct i2c_adapter *i2c,
- int no_of_demods, u8 default_addr,
- struct dib3000mc_config cfg[]);
-extern
-struct i2c_adapter *dib3000mc_get_tuner_i2c_master(struct dvb_frontend *demod,
- int gating);
-#else
-static inline
-struct dvb_frontend *dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
- struct dib3000mc_config *cfg)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline
-int dib3000mc_i2c_enumeration(struct i2c_adapter *i2c,
- int no_of_demods, u8 default_addr,
- struct dib3000mc_config cfg[])
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline
-struct i2c_adapter *dib3000mc_get_tuner_i2c_master(struct dvb_frontend *demod,
- int gating)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif // CONFIG_DVB_DIB3000MC
-
-extern int dib3000mc_pid_control(struct dvb_frontend *fe, int index, int pid,int onoff);
-extern int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff);
-
-extern void dib3000mc_set_config(struct dvb_frontend *, struct dib3000mc_config *);
-
-#endif
diff --git a/drivers/media/dvb/frontends/dib7000m.c b/drivers/media/dvb/frontends/dib7000m.c
deleted file mode 100644
index 148bf79236f..00000000000
--- a/drivers/media/dvb/frontends/dib7000m.c
+++ /dev/null
@@ -1,1473 +0,0 @@
-/*
- * Linux-DVB Driver for DiBcom's DiB7000M and
- * first generation DiB7000P-demodulator-family.
- *
- * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- */
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/i2c.h>
-#include <linux/mutex.h>
-
-#include "dvb_frontend.h"
-
-#include "dib7000m.h"
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
-
-#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000M: "); printk(args); printk("\n"); } } while (0)
-
-struct dib7000m_state {
- struct dvb_frontend demod;
- struct dib7000m_config cfg;
-
- u8 i2c_addr;
- struct i2c_adapter *i2c_adap;
-
- struct dibx000_i2c_master i2c_master;
-
-/* offset is 1 in case of the 7000MC */
- u8 reg_offs;
-
- u16 wbd_ref;
-
- u8 current_band;
- u32 current_bandwidth;
- struct dibx000_agc_config *current_agc;
- u32 timf;
- u32 timf_default;
- u32 internal_clk;
-
- u8 div_force_off : 1;
- u8 div_state : 1;
- u16 div_sync_wait;
-
- u16 revision;
-
- u8 agc_state;
-
- /* for the I2C transfer */
- struct i2c_msg msg[2];
- u8 i2c_write_buffer[4];
- u8 i2c_read_buffer[2];
- struct mutex i2c_buffer_lock;
-};
-
-enum dib7000m_power_mode {
- DIB7000M_POWER_ALL = 0,
-
- DIB7000M_POWER_NO,
- DIB7000M_POWER_INTERF_ANALOG_AGC,
- DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
- DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD,
- DIB7000M_POWER_INTERFACE_ONLY,
-};
-
-static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg)
-{
- u16 ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return 0;
- }
-
- state->i2c_write_buffer[0] = (reg >> 8) | 0x80;
- state->i2c_write_buffer[1] = reg & 0xff;
-
- memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
- state->msg[0].addr = state->i2c_addr >> 1;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 2;
- state->msg[1].addr = state->i2c_addr >> 1;
- state->msg[1].flags = I2C_M_RD;
- state->msg[1].buf = state->i2c_read_buffer;
- state->msg[1].len = 2;
-
- if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
- dprintk("i2c read error on %d",reg);
-
- ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
- mutex_unlock(&state->i2c_buffer_lock);
-
- return ret;
-}
-
-static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val)
-{
- int ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
-
- state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
- state->i2c_write_buffer[1] = reg & 0xff;
- state->i2c_write_buffer[2] = (val >> 8) & 0xff;
- state->i2c_write_buffer[3] = val & 0xff;
-
- memset(&state->msg[0], 0, sizeof(struct i2c_msg));
- state->msg[0].addr = state->i2c_addr >> 1;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 4;
-
- ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
- -EREMOTEIO : 0);
- mutex_unlock(&state->i2c_buffer_lock);
- return ret;
-}
-static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf)
-{
- u16 l = 0, r, *n;
- n = buf;
- l = *n++;
- while (l) {
- r = *n++;
-
- if (state->reg_offs && (r >= 112 && r <= 331)) // compensate for 7000MC
- r++;
-
- do {
- dib7000m_write_word(state, r, *n++);
- r++;
- } while (--l);
- l = *n++;
- }
-}
-
-static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode)
-{
- int ret = 0;
- u16 outreg, fifo_threshold, smo_mode,
- sram = 0x0005; /* by default SRAM output is disabled */
-
- outreg = 0;
- fifo_threshold = 1792;
- smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1);
-
- dprintk( "setting output mode for demod %p to %d", &state->demod, mode);
-
- switch (mode) {
- case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
- outreg = (1 << 10); /* 0x0400 */
- break;
- case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
- outreg = (1 << 10) | (1 << 6); /* 0x0440 */
- break;
- case OUTMODE_MPEG2_SERIAL: // STBs with serial input
- outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
- break;
- case OUTMODE_DIVERSITY:
- if (state->cfg.hostbus_diversity)
- outreg = (1 << 10) | (4 << 6); /* 0x0500 */
- else
- sram |= 0x0c00;
- break;
- case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
- smo_mode |= (3 << 1);
- fifo_threshold = 512;
- outreg = (1 << 10) | (5 << 6);
- break;
- case OUTMODE_HIGH_Z: // disable
- outreg = 0;
- break;
- default:
- dprintk( "Unhandled output_mode passed to be set for demod %p",&state->demod);
- break;
- }
-
- if (state->cfg.output_mpeg2_in_188_bytes)
- smo_mode |= (1 << 5) ;
-
- ret |= dib7000m_write_word(state, 294 + state->reg_offs, smo_mode);
- ret |= dib7000m_write_word(state, 295 + state->reg_offs, fifo_threshold); /* synchronous fread */
- ret |= dib7000m_write_word(state, 1795, outreg);
- ret |= dib7000m_write_word(state, 1805, sram);
-
- if (state->revision == 0x4003) {
- u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd;
- if (mode == OUTMODE_DIVERSITY)
- clk_cfg1 |= (1 << 1); // P_O_CLK_en
- dib7000m_write_word(state, 909, clk_cfg1);
- }
- return ret;
-}
-
-static void dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_power_mode mode)
-{
- /* by default everything is going to be powered off */
- u16 reg_903 = 0xffff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906 = 0x3fff;
- u8 offset = 0;
-
- /* now, depending on the requested mode, we power on */
- switch (mode) {
- /* power up everything in the demod */
- case DIB7000M_POWER_ALL:
- reg_903 = 0x0000; reg_904 = 0x0000; reg_905 = 0x0000; reg_906 = 0x0000;
- break;
-
- /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
- case DIB7000M_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */
- reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
- break;
-
- case DIB7000M_POWER_INTERF_ANALOG_AGC:
- reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
- reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
- reg_906 &= ~((1 << 0));
- break;
-
- case DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
- reg_903 = 0x0000; reg_904 = 0x801f; reg_905 = 0x0000; reg_906 = 0x0000;
- break;
-
- case DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD:
- reg_903 = 0x0000; reg_904 = 0x8000; reg_905 = 0x010b; reg_906 = 0x0000;
- break;
- case DIB7000M_POWER_NO:
- break;
- }
-
- /* always power down unused parts */
- if (!state->cfg.mobile_mode)
- reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
-
- /* P_sdio_select_clk = 0 on MC and after*/
- if (state->revision != 0x4000)
- reg_906 <<= 1;
-
- if (state->revision == 0x4003)
- offset = 1;
-
- dib7000m_write_word(state, 903 + offset, reg_903);
- dib7000m_write_word(state, 904 + offset, reg_904);
- dib7000m_write_word(state, 905 + offset, reg_905);
- dib7000m_write_word(state, 906 + offset, reg_906);
-}
-
-static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc_states no)
-{
- int ret = 0;
- u16 reg_913 = dib7000m_read_word(state, 913),
- reg_914 = dib7000m_read_word(state, 914);
-
- switch (no) {
- case DIBX000_SLOW_ADC_ON:
- reg_914 |= (1 << 1) | (1 << 0);
- ret |= dib7000m_write_word(state, 914, reg_914);
- reg_914 &= ~(1 << 1);
- break;
-
- case DIBX000_SLOW_ADC_OFF:
- reg_914 |= (1 << 1) | (1 << 0);
- break;
-
- case DIBX000_ADC_ON:
- if (state->revision == 0x4000) { // workaround for PA/MA
- // power-up ADC
- dib7000m_write_word(state, 913, 0);
- dib7000m_write_word(state, 914, reg_914 & 0x3);
- // power-down bandgag
- dib7000m_write_word(state, 913, (1 << 15));
- dib7000m_write_word(state, 914, reg_914 & 0x3);
- }
-
- reg_913 &= 0x0fff;
- reg_914 &= 0x0003;
- break;
-
- case DIBX000_ADC_OFF: // leave the VBG voltage on
- reg_913 |= (1 << 14) | (1 << 13) | (1 << 12);
- reg_914 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
- break;
-
- case DIBX000_VBG_ENABLE:
- reg_913 &= ~(1 << 15);
- break;
-
- case DIBX000_VBG_DISABLE:
- reg_913 |= (1 << 15);
- break;
-
- default:
- break;
- }
-
-// dprintk( "913: %x, 914: %x", reg_913, reg_914);
- ret |= dib7000m_write_word(state, 913, reg_913);
- ret |= dib7000m_write_word(state, 914, reg_914);
-
- return ret;
-}
-
-static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw)
-{
- u32 timf;
-
- if (!bw)
- bw = 8000;
-
- // store the current bandwidth for later use
- state->current_bandwidth = bw;
-
- if (state->timf == 0) {
- dprintk( "using default timf");
- timf = state->timf_default;
- } else {
- dprintk( "using updated timf");
- timf = state->timf;
- }
-
- timf = timf * (bw / 50) / 160;
-
- dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
- dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff));
-
- return 0;
-}
-
-static int dib7000m_set_diversity_in(struct dvb_frontend *demod, int onoff)
-{
- struct dib7000m_state *state = demod->demodulator_priv;
-
- if (state->div_force_off) {
- dprintk( "diversity combination deactivated - forced by COFDM parameters");
- onoff = 0;
- }
- state->div_state = (u8)onoff;
-
- if (onoff) {
- dib7000m_write_word(state, 263 + state->reg_offs, 6);
- dib7000m_write_word(state, 264 + state->reg_offs, 6);
- dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
- } else {
- dib7000m_write_word(state, 263 + state->reg_offs, 1);
- dib7000m_write_word(state, 264 + state->reg_offs, 0);
- dib7000m_write_word(state, 266 + state->reg_offs, 0);
- }
-
- return 0;
-}
-
-static int dib7000m_sad_calib(struct dib7000m_state *state)
-{
-
-/* internal */
-// dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writting in set_bandwidth
- dib7000m_write_word(state, 929, (0 << 1) | (0 << 0));
- dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096
-
- /* do the calibration */
- dib7000m_write_word(state, 929, (1 << 0));
- dib7000m_write_word(state, 929, (0 << 0));
-
- msleep(1);
-
- return 0;
-}
-
-static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw)
-{
- dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
- dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff));
- dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff));
- dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff));
-
- dib7000m_write_word(state, 928, bw->sad_cfg);
-}
-
-static void dib7000m_reset_pll(struct dib7000m_state *state)
-{
- const struct dibx000_bandwidth_config *bw = state->cfg.bw;
- u16 reg_907,reg_910;
-
- /* default */
- reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) |
- (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) |
- (bw->enable_refdiv << 1) | (0 << 0);
- reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset;
-
- // for this oscillator frequency should be 30 MHz for the Master (default values in the board_parameters give that value)
- // this is only working only for 30 MHz crystals
- if (!state->cfg.quartz_direct) {
- reg_910 |= (1 << 5); // forcing the predivider to 1
-
- // if the previous front-end is baseband, its output frequency is 15 MHz (prev freq divided by 2)
- if(state->cfg.input_clk_is_div_2)
- reg_907 |= (16 << 9);
- else // otherwise the previous front-end puts out its input (default 30MHz) - no extra division necessary
- reg_907 |= (8 << 9);
- } else {
- reg_907 |= (bw->pll_ratio & 0x3f) << 9;
- reg_910 |= (bw->pll_prediv << 5);
- }
-
- dib7000m_write_word(state, 910, reg_910); // pll cfg
- dib7000m_write_word(state, 907, reg_907); // clk cfg0
- dib7000m_write_word(state, 908, 0x0006); // clk_cfg1
-
- dib7000m_reset_pll_common(state, bw);
-}
-
-static void dib7000mc_reset_pll(struct dib7000m_state *state)
-{
- const struct dibx000_bandwidth_config *bw = state->cfg.bw;
- u16 clk_cfg1;
-
- // clk_cfg0
- dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
-
- // clk_cfg1
- //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) |
- clk_cfg1 = (0 << 14) | (3 << 12) |(0 << 11) |
- (bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) |
- (1 << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0);
- dib7000m_write_word(state, 908, clk_cfg1);
- clk_cfg1 = (clk_cfg1 & 0xfff7) | (bw->pll_bypass << 3);
- dib7000m_write_word(state, 908, clk_cfg1);
-
- // smpl_cfg
- dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7));
-
- dib7000m_reset_pll_common(state, bw);
-}
-
-static int dib7000m_reset_gpio(struct dib7000m_state *st)
-{
- /* reset the GPIOs */
- dib7000m_write_word(st, 773, st->cfg.gpio_dir);
- dib7000m_write_word(st, 774, st->cfg.gpio_val);
-
- /* TODO 782 is P_gpio_od */
-
- dib7000m_write_word(st, 775, st->cfg.gpio_pwm_pos);
-
- dib7000m_write_word(st, 780, st->cfg.pwm_freq_div);
- return 0;
-}
-
-static u16 dib7000m_defaults_common[] =
-
-{
- // auto search configuration
- 3, 2,
- 0x0004,
- 0x1000,
- 0x0814,
-
- 12, 6,
- 0x001b,
- 0x7740,
- 0x005b,
- 0x8d80,
- 0x01c9,
- 0xc380,
- 0x0000,
- 0x0080,
- 0x0000,
- 0x0090,
- 0x0001,
- 0xd4c0,
-
- 1, 26,
- 0x6680, // P_corm_thres Lock algorithms configuration
-
- 1, 170,
- 0x0410, // P_palf_alpha_regul, P_palf_filter_freeze, P_palf_filter_on
-
- 8, 173,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
-
- 1, 182,
- 8192, // P_fft_nb_to_cut
-
- 2, 195,
- 0x0ccd, // P_pha3_thres
- 0, // P_cti_use_cpe, P_cti_use_prog
-
- 1, 205,
- 0x200f, // P_cspu_regul, P_cspu_win_cut
-
- 5, 214,
- 0x023d, // P_adp_regul_cnt
- 0x00a4, // P_adp_noise_cnt
- 0x00a4, // P_adp_regul_ext
- 0x7ff0, // P_adp_noise_ext
- 0x3ccc, // P_adp_fil
-
- 1, 226,
- 0, // P_2d_byp_ti_num
-
- 1, 255,
- 0x800, // P_equal_thres_wgn
-
- 1, 263,
- 0x0001,
-
- 1, 281,
- 0x0010, // P_fec_*
-
- 1, 294,
- 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
-
- 0
-};
-
-static u16 dib7000m_defaults[] =
-
-{
- /* set ADC level to -16 */
- 11, 76,
- (1 << 13) - 825 - 117,
- (1 << 13) - 837 - 117,
- (1 << 13) - 811 - 117,
- (1 << 13) - 766 - 117,
- (1 << 13) - 737 - 117,
- (1 << 13) - 693 - 117,
- (1 << 13) - 648 - 117,
- (1 << 13) - 619 - 117,
- (1 << 13) - 575 - 117,
- (1 << 13) - 531 - 117,
- (1 << 13) - 501 - 117,
-
- // Tuner IO bank: max drive (14mA)
- 1, 912,
- 0x2c8a,
-
- 1, 1817,
- 1,
-
- 0,
-};
-
-static int dib7000m_demod_reset(struct dib7000m_state *state)
-{
- dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
-
- /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
- dib7000m_set_adc_state(state, DIBX000_VBG_ENABLE);
-
- /* restart all parts */
- dib7000m_write_word(state, 898, 0xffff);
- dib7000m_write_word(state, 899, 0xffff);
- dib7000m_write_word(state, 900, 0xff0f);
- dib7000m_write_word(state, 901, 0xfffc);
-
- dib7000m_write_word(state, 898, 0);
- dib7000m_write_word(state, 899, 0);
- dib7000m_write_word(state, 900, 0);
- dib7000m_write_word(state, 901, 0);
-
- if (state->revision == 0x4000)
- dib7000m_reset_pll(state);
- else
- dib7000mc_reset_pll(state);
-
- if (dib7000m_reset_gpio(state) != 0)
- dprintk( "GPIO reset was not successful.");
-
- if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
- dprintk( "OUTPUT_MODE could not be reset.");
-
- /* unforce divstr regardless whether i2c enumeration was done or not */
- dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) );
-
- dib7000m_set_bandwidth(state, 8000);
-
- dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON);
- dib7000m_sad_calib(state);
- dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
-
- if (state->cfg.dvbt_mode)
- dib7000m_write_word(state, 1796, 0x0); // select DVB-T output
-
- if (state->cfg.mobile_mode)
- dib7000m_write_word(state, 261 + state->reg_offs, 2);
- else
- dib7000m_write_word(state, 224 + state->reg_offs, 1);
-
- // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
- if(state->cfg.tuner_is_baseband)
- dib7000m_write_word(state, 36, 0x0755);
- else
- dib7000m_write_word(state, 36, 0x1f55);
-
- // P_divclksel=3 P_divbitsel=1
- if (state->revision == 0x4000)
- dib7000m_write_word(state, 909, (3 << 10) | (1 << 6));
- else
- dib7000m_write_word(state, 909, (3 << 4) | 1);
-
- dib7000m_write_tab(state, dib7000m_defaults_common);
- dib7000m_write_tab(state, dib7000m_defaults);
-
- dib7000m_set_power_mode(state, DIB7000M_POWER_INTERFACE_ONLY);
-
- state->internal_clk = state->cfg.bw->internal;
-
- return 0;
-}
-
-static void dib7000m_restart_agc(struct dib7000m_state *state)
-{
- // P_restart_iqc & P_restart_agc
- dib7000m_write_word(state, 898, 0x0c00);
- dib7000m_write_word(state, 898, 0x0000);
-}
-
-static int dib7000m_agc_soft_split(struct dib7000m_state *state)
-{
- u16 agc,split_offset;
-
- if(!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
- return 0;
-
- // n_agc_global
- agc = dib7000m_read_word(state, 390);
-
- if (agc > state->current_agc->split.min_thres)
- split_offset = state->current_agc->split.min;
- else if (agc < state->current_agc->split.max_thres)
- split_offset = state->current_agc->split.max;
- else
- split_offset = state->current_agc->split.max *
- (agc - state->current_agc->split.min_thres) /
- (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
-
- dprintk( "AGC split_offset: %d",split_offset);
-
- // P_agc_force_split and P_agc_split_offset
- return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset);
-}
-
-static int dib7000m_update_lna(struct dib7000m_state *state)
-{
- u16 dyn_gain;
-
- if (state->cfg.update_lna) {
- // read dyn_gain here (because it is demod-dependent and not fe)
- dyn_gain = dib7000m_read_word(state, 390);
-
- if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed
- dib7000m_restart_agc(state);
- return 1;
- }
- }
- return 0;
-}
-
-static int dib7000m_set_agc_config(struct dib7000m_state *state, u8 band)
-{
- struct dibx000_agc_config *agc = NULL;
- int i;
- if (state->current_band == band && state->current_agc != NULL)
- return 0;
- state->current_band = band;
-
- for (i = 0; i < state->cfg.agc_config_count; i++)
- if (state->cfg.agc[i].band_caps & band) {
- agc = &state->cfg.agc[i];
- break;
- }
-
- if (agc == NULL) {
- dprintk( "no valid AGC configuration found for band 0x%02x",band);
- return -EINVAL;
- }
-
- state->current_agc = agc;
-
- /* AGC */
- dib7000m_write_word(state, 72 , agc->setup);
- dib7000m_write_word(state, 73 , agc->inv_gain);
- dib7000m_write_word(state, 74 , agc->time_stabiliz);
- dib7000m_write_word(state, 97 , (agc->alpha_level << 12) | agc->thlock);
-
- // Demod AGC loop configuration
- dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp);
- dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp);
-
- dprintk( "WBD: ref: %d, sel: %d, active: %d, alpha: %d",
- state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
-
- /* AGC continued */
- if (state->wbd_ref != 0)
- dib7000m_write_word(state, 102, state->wbd_ref);
- else // use default
- dib7000m_write_word(state, 102, agc->wbd_ref);
-
- dib7000m_write_word(state, 103, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) );
- dib7000m_write_word(state, 104, agc->agc1_max);
- dib7000m_write_word(state, 105, agc->agc1_min);
- dib7000m_write_word(state, 106, agc->agc2_max);
- dib7000m_write_word(state, 107, agc->agc2_min);
- dib7000m_write_word(state, 108, (agc->agc1_pt1 << 8) | agc->agc1_pt2 );
- dib7000m_write_word(state, 109, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
- dib7000m_write_word(state, 110, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
- dib7000m_write_word(state, 111, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
-
- if (state->revision > 0x4000) { // settings for the MC
- dib7000m_write_word(state, 71, agc->agc1_pt3);
-// dprintk( "929: %x %d %d",
-// (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wbd_inv, agc->wbd_sel);
- dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
- } else {
- // wrong default values
- u16 b[9] = { 676, 696, 717, 737, 758, 778, 799, 819, 840 };
- for (i = 0; i < 9; i++)
- dib7000m_write_word(state, 88 + i, b[i]);
- }
- return 0;
-}
-
-static void dib7000m_update_timf(struct dib7000m_state *state)
-{
- u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437);
- state->timf = timf * 160 / (state->current_bandwidth / 50);
- dib7000m_write_word(state, 23, (u16) (timf >> 16));
- dib7000m_write_word(state, 24, (u16) (timf & 0xffff));
- dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->timf_default);
-}
-
-static int dib7000m_agc_startup(struct dvb_frontend *demod)
-{
- struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
- struct dib7000m_state *state = demod->demodulator_priv;
- u16 cfg_72 = dib7000m_read_word(state, 72);
- int ret = -1;
- u8 *agc_state = &state->agc_state;
- u8 agc_split;
-
- switch (state->agc_state) {
- case 0:
- // set power-up level: interf+analog+AGC
- dib7000m_set_power_mode(state, DIB7000M_POWER_INTERF_ANALOG_AGC);
- dib7000m_set_adc_state(state, DIBX000_ADC_ON);
-
- if (dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0)
- return -1;
-
- ret = 7; /* ADC power up */
- (*agc_state)++;
- break;
-
- case 1:
- /* AGC initialization */
- if (state->cfg.agc_control)
- state->cfg.agc_control(&state->demod, 1);
-
- dib7000m_write_word(state, 75, 32768);
- if (!state->current_agc->perform_agc_softsplit) {
- /* we are using the wbd - so slow AGC startup */
- dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */
- (*agc_state)++;
- ret = 5;
- } else {
- /* default AGC startup */
- (*agc_state) = 4;
- /* wait AGC rough lock time */
- ret = 7;
- }
-
- dib7000m_restart_agc(state);
- break;
-
- case 2: /* fast split search path after 5sec */
- dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */
- dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */
- (*agc_state)++;
- ret = 14;
- break;
-
- case 3: /* split search ended */
- agc_split = (u8)dib7000m_read_word(state, 392); /* store the split value for the next time */
- dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */
-
- dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */
- dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
-
- dib7000m_restart_agc(state);
-
- dprintk( "SPLIT %p: %hd", demod, agc_split);
-
- (*agc_state)++;
- ret = 5;
- break;
-
- case 4: /* LNA startup */
- /* wait AGC accurate lock time */
- ret = 7;
-
- if (dib7000m_update_lna(state))
- // wait only AGC rough lock time
- ret = 5;
- else
- (*agc_state)++;
- break;
-
- case 5:
- dib7000m_agc_soft_split(state);
-
- if (state->cfg.agc_control)
- state->cfg.agc_control(&state->demod, 0);
-
- (*agc_state)++;
- break;
-
- default:
- break;
- }
- return ret;
-}
-
-static void dib7000m_set_channel(struct dib7000m_state *state, struct dtv_frontend_properties *ch,
- u8 seq)
-{
- u16 value, est[4];
-
- dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
-
- /* nfft, guard, qam, alpha */
- value = 0;
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
- case TRANSMISSION_MODE_4K: value |= (2 << 7); break;
- default:
- case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
- }
- switch (ch->guard_interval) {
- case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
- case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
- case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
- default:
- case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
- }
- switch (ch->modulation) {
- case QPSK: value |= (0 << 3); break;
- case QAM_16: value |= (1 << 3); break;
- default:
- case QAM_64: value |= (2 << 3); break;
- }
- switch (HIERARCHY_1) {
- case HIERARCHY_2: value |= 2; break;
- case HIERARCHY_4: value |= 4; break;
- default:
- case HIERARCHY_1: value |= 1; break;
- }
- dib7000m_write_word(state, 0, value);
- dib7000m_write_word(state, 5, (seq << 4));
-
- /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
- value = 0;
- if (1 != 0)
- value |= (1 << 6);
- if (ch->hierarchy == 1)
- value |= (1 << 4);
- if (1 == 1)
- value |= 1;
- switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
- case FEC_2_3: value |= (2 << 1); break;
- case FEC_3_4: value |= (3 << 1); break;
- case FEC_5_6: value |= (5 << 1); break;
- case FEC_7_8: value |= (7 << 1); break;
- default:
- case FEC_1_2: value |= (1 << 1); break;
- }
- dib7000m_write_word(state, 267 + state->reg_offs, value);
-
- /* offset loop parameters */
-
- /* P_timf_alpha = 6, P_corm_alpha=6, P_corm_thres=0x80 */
- dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80);
-
- /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=1, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
- dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3));
-
- /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max=3 */
- dib7000m_write_word(state, 32, (0 << 4) | 0x3);
-
- /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step=5 */
- dib7000m_write_word(state, 33, (0 << 4) | 0x5);
-
- /* P_dvsy_sync_wait */
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_8K: value = 256; break;
- case TRANSMISSION_MODE_4K: value = 128; break;
- case TRANSMISSION_MODE_2K:
- default: value = 64; break;
- }
- switch (ch->guard_interval) {
- case GUARD_INTERVAL_1_16: value *= 2; break;
- case GUARD_INTERVAL_1_8: value *= 4; break;
- case GUARD_INTERVAL_1_4: value *= 8; break;
- default:
- case GUARD_INTERVAL_1_32: value *= 1; break;
- }
- state->div_sync_wait = (value * 3) / 2 + 32; // add 50% SFN margin + compensate for one DVSY-fifo TODO
-
- /* deactive the possibility of diversity reception if extended interleave - not for 7000MC */
- /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
- if (1 == 1 || state->revision > 0x4000)
- state->div_force_off = 0;
- else
- state->div_force_off = 1;
- dib7000m_set_diversity_in(&state->demod, state->div_state);
-
- /* channel estimation fine configuration */
- switch (ch->modulation) {
- case QAM_64:
- est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
- est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
- est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
- est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
- break;
- case QAM_16:
- est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
- est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
- est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
- est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
- break;
- default:
- est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
- est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
- est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
- est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
- break;
- }
- for (value = 0; value < 4; value++)
- dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]);
-
- // set power-up level: autosearch
- dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD);
-}
-
-static int dib7000m_autosearch_start(struct dvb_frontend *demod)
-{
- struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
- struct dib7000m_state *state = demod->demodulator_priv;
- struct dtv_frontend_properties schan;
- int ret = 0;
- u32 value, factor;
-
- schan = *ch;
-
- schan.modulation = QAM_64;
- schan.guard_interval = GUARD_INTERVAL_1_32;
- schan.transmission_mode = TRANSMISSION_MODE_8K;
- schan.code_rate_HP = FEC_2_3;
- schan.code_rate_LP = FEC_3_4;
- schan.hierarchy = 0;
-
- dib7000m_set_channel(state, &schan, 7);
-
- factor = BANDWIDTH_TO_KHZ(schan.bandwidth_hz);
- if (factor >= 5000)
- factor = 1;
- else
- factor = 6;
-
- // always use the setting for 8MHz here lock_time for 7,6 MHz are longer
- value = 30 * state->internal_clk * factor;
- ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
- ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time
- value = 100 * state->internal_clk * factor;
- ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
- ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time
- value = 500 * state->internal_clk * factor;
- ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
- ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
-
- // start search
- value = dib7000m_read_word(state, 0);
- ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9)));
-
- /* clear n_irq_pending */
- if (state->revision == 0x4000)
- dib7000m_write_word(state, 1793, 0);
- else
- dib7000m_read_word(state, 537);
-
- ret |= dib7000m_write_word(state, 0, (u16) value);
-
- return ret;
-}
-
-static int dib7000m_autosearch_irq(struct dib7000m_state *state, u16 reg)
-{
- u16 irq_pending = dib7000m_read_word(state, reg);
-
- if (irq_pending & 0x1) { // failed
- dprintk( "autosearch failed");
- return 1;
- }
-
- if (irq_pending & 0x2) { // succeeded
- dprintk( "autosearch succeeded");
- return 2;
- }
- return 0; // still pending
-}
-
-static int dib7000m_autosearch_is_irq(struct dvb_frontend *demod)
-{
- struct dib7000m_state *state = demod->demodulator_priv;
- if (state->revision == 0x4000)
- return dib7000m_autosearch_irq(state, 1793);
- else
- return dib7000m_autosearch_irq(state, 537);
-}
-
-static int dib7000m_tune(struct dvb_frontend *demod)
-{
- struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
- struct dib7000m_state *state = demod->demodulator_priv;
- int ret = 0;
- u16 value;
-
- // we are already tuned - just resuming from suspend
- if (ch != NULL)
- dib7000m_set_channel(state, ch, 0);
- else
- return -EINVAL;
-
- // restart demod
- ret |= dib7000m_write_word(state, 898, 0x4000);
- ret |= dib7000m_write_word(state, 898, 0x0000);
- msleep(45);
-
- dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD);
- /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
- ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3));
-
- // never achieved a lock before - wait for timfreq to update
- if (state->timf == 0)
- msleep(200);
-
- //dump_reg(state);
- /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
- value = (6 << 8) | 0x80;
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_2K: value |= (7 << 12); break;
- case TRANSMISSION_MODE_4K: value |= (8 << 12); break;
- default:
- case TRANSMISSION_MODE_8K: value |= (9 << 12); break;
- }
- ret |= dib7000m_write_word(state, 26, value);
-
- /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
- value = (0 << 4);
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_2K: value |= 0x6; break;
- case TRANSMISSION_MODE_4K: value |= 0x7; break;
- default:
- case TRANSMISSION_MODE_8K: value |= 0x8; break;
- }
- ret |= dib7000m_write_word(state, 32, value);
-
- /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
- value = (0 << 4);
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_2K: value |= 0x6; break;
- case TRANSMISSION_MODE_4K: value |= 0x7; break;
- default:
- case TRANSMISSION_MODE_8K: value |= 0x8; break;
- }
- ret |= dib7000m_write_word(state, 33, value);
-
- // we achieved a lock - it's time to update the timf freq
- if ((dib7000m_read_word(state, 535) >> 6) & 0x1)
- dib7000m_update_timf(state);
-
- dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
- return ret;
-}
-
-static int dib7000m_wakeup(struct dvb_frontend *demod)
-{
- struct dib7000m_state *state = demod->demodulator_priv;
-
- dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
-
- if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
- dprintk( "could not start Slow ADC");
-
- return 0;
-}
-
-static int dib7000m_sleep(struct dvb_frontend *demod)
-{
- struct dib7000m_state *st = demod->demodulator_priv;
- dib7000m_set_output_mode(st, OUTMODE_HIGH_Z);
- dib7000m_set_power_mode(st, DIB7000M_POWER_INTERFACE_ONLY);
- return dib7000m_set_adc_state(st, DIBX000_SLOW_ADC_OFF) |
- dib7000m_set_adc_state(st, DIBX000_ADC_OFF);
-}
-
-static int dib7000m_identify(struct dib7000m_state *state)
-{
- u16 value;
-
- if ((value = dib7000m_read_word(state, 896)) != 0x01b3) {
- dprintk( "wrong Vendor ID (0x%x)",value);
- return -EREMOTEIO;
- }
-
- state->revision = dib7000m_read_word(state, 897);
- if (state->revision != 0x4000 &&
- state->revision != 0x4001 &&
- state->revision != 0x4002 &&
- state->revision != 0x4003) {
- dprintk( "wrong Device ID (0x%x)",value);
- return -EREMOTEIO;
- }
-
- /* protect this driver to be used with 7000PC */
- if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) {
- dprintk( "this driver does not work with DiB7000PC");
- return -EREMOTEIO;
- }
-
- switch (state->revision) {
- case 0x4000: dprintk( "found DiB7000MA/PA/MB/PB"); break;
- case 0x4001: state->reg_offs = 1; dprintk( "found DiB7000HC"); break;
- case 0x4002: state->reg_offs = 1; dprintk( "found DiB7000MC"); break;
- case 0x4003: state->reg_offs = 1; dprintk( "found DiB9000"); break;
- }
-
- return 0;
-}
-
-
-static int dib7000m_get_frontend(struct dvb_frontend* fe)
-{
- struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
- struct dib7000m_state *state = fe->demodulator_priv;
- u16 tps = dib7000m_read_word(state,480);
-
- fep->inversion = INVERSION_AUTO;
-
- fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
-
- switch ((tps >> 8) & 0x3) {
- case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break;
- case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break;
- /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
- }
-
- switch (tps & 0x3) {
- case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break;
- case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break;
- case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break;
- case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break;
- }
-
- switch ((tps >> 14) & 0x3) {
- case 0: fep->modulation = QPSK; break;
- case 1: fep->modulation = QAM_16; break;
- case 2:
- default: fep->modulation = QAM_64; break;
- }
-
- /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
- /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
-
- fep->hierarchy = HIERARCHY_NONE;
- switch ((tps >> 5) & 0x7) {
- case 1: fep->code_rate_HP = FEC_1_2; break;
- case 2: fep->code_rate_HP = FEC_2_3; break;
- case 3: fep->code_rate_HP = FEC_3_4; break;
- case 5: fep->code_rate_HP = FEC_5_6; break;
- case 7:
- default: fep->code_rate_HP = FEC_7_8; break;
-
- }
-
- switch ((tps >> 2) & 0x7) {
- case 1: fep->code_rate_LP = FEC_1_2; break;
- case 2: fep->code_rate_LP = FEC_2_3; break;
- case 3: fep->code_rate_LP = FEC_3_4; break;
- case 5: fep->code_rate_LP = FEC_5_6; break;
- case 7:
- default: fep->code_rate_LP = FEC_7_8; break;
- }
-
- /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */
-
- return 0;
-}
-
-static int dib7000m_set_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
- struct dib7000m_state *state = fe->demodulator_priv;
- int time, ret;
-
- dib7000m_set_output_mode(state, OUTMODE_HIGH_Z);
-
- dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
-
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
-
- /* start up the AGC */
- state->agc_state = 0;
- do {
- time = dib7000m_agc_startup(fe);
- if (time != -1)
- msleep(time);
- } while (time != -1);
-
- if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
- fep->guard_interval == GUARD_INTERVAL_AUTO ||
- fep->modulation == QAM_AUTO ||
- fep->code_rate_HP == FEC_AUTO) {
- int i = 800, found;
-
- dib7000m_autosearch_start(fe);
- do {
- msleep(1);
- found = dib7000m_autosearch_is_irq(fe);
- } while (found == 0 && i--);
-
- dprintk("autosearch returns: %d",found);
- if (found == 0 || found == 1)
- return 0; // no channel found
-
- dib7000m_get_frontend(fe);
- }
-
- ret = dib7000m_tune(fe);
-
- /* make this a config parameter */
- dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO);
- return ret;
-}
-
-static int dib7000m_read_status(struct dvb_frontend *fe, fe_status_t *stat)
-{
- struct dib7000m_state *state = fe->demodulator_priv;
- u16 lock = dib7000m_read_word(state, 535);
-
- *stat = 0;
-
- if (lock & 0x8000)
- *stat |= FE_HAS_SIGNAL;
- if (lock & 0x3000)
- *stat |= FE_HAS_CARRIER;
- if (lock & 0x0100)
- *stat |= FE_HAS_VITERBI;
- if (lock & 0x0010)
- *stat |= FE_HAS_SYNC;
- if (lock & 0x0008)
- *stat |= FE_HAS_LOCK;
-
- return 0;
-}
-
-static int dib7000m_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct dib7000m_state *state = fe->demodulator_priv;
- *ber = (dib7000m_read_word(state, 526) << 16) | dib7000m_read_word(state, 527);
- return 0;
-}
-
-static int dib7000m_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
-{
- struct dib7000m_state *state = fe->demodulator_priv;
- *unc = dib7000m_read_word(state, 534);
- return 0;
-}
-
-static int dib7000m_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
-{
- struct dib7000m_state *state = fe->demodulator_priv;
- u16 val = dib7000m_read_word(state, 390);
- *strength = 65535 - val;
- return 0;
-}
-
-static int dib7000m_read_snr(struct dvb_frontend* fe, u16 *snr)
-{
- *snr = 0x0000;
- return 0;
-}
-
-static int dib7000m_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
-{
- tune->min_delay_ms = 1000;
- return 0;
-}
-
-static void dib7000m_release(struct dvb_frontend *demod)
-{
- struct dib7000m_state *st = demod->demodulator_priv;
- dibx000_exit_i2c_master(&st->i2c_master);
- kfree(st);
-}
-
-struct i2c_adapter * dib7000m_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
-{
- struct dib7000m_state *st = demod->demodulator_priv;
- return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
-}
-EXPORT_SYMBOL(dib7000m_get_i2c_master);
-
-int dib7000m_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
-{
- struct dib7000m_state *state = fe->demodulator_priv;
- u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef;
- val |= (onoff & 0x1) << 4;
- dprintk("PID filter enabled %d", onoff);
- return dib7000m_write_word(state, 294 + state->reg_offs, val);
-}
-EXPORT_SYMBOL(dib7000m_pid_filter_ctrl);
-
-int dib7000m_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
-{
- struct dib7000m_state *state = fe->demodulator_priv;
- dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
- return dib7000m_write_word(state, 300 + state->reg_offs + id,
- onoff ? (1 << 13) | pid : 0);
-}
-EXPORT_SYMBOL(dib7000m_pid_filter);
-
-#if 0
-/* used with some prototype boards */
-int dib7000m_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods,
- u8 default_addr, struct dib7000m_config cfg[])
-{
- struct dib7000m_state st = { .i2c_adap = i2c };
- int k = 0;
- u8 new_addr = 0;
-
- for (k = no_of_demods-1; k >= 0; k--) {
- st.cfg = cfg[k];
-
- /* designated i2c address */
- new_addr = (0x40 + k) << 1;
- st.i2c_addr = new_addr;
- if (dib7000m_identify(&st) != 0) {
- st.i2c_addr = default_addr;
- if (dib7000m_identify(&st) != 0) {
- dprintk("DiB7000M #%d: not identified", k);
- return -EIO;
- }
- }
-
- /* start diversity to pull_down div_str - just for i2c-enumeration */
- dib7000m_set_output_mode(&st, OUTMODE_DIVERSITY);
-
- dib7000m_write_word(&st, 1796, 0x0); // select DVB-T output
-
- /* set new i2c address and force divstart */
- dib7000m_write_word(&st, 1794, (new_addr << 2) | 0x2);
-
- dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
- }
-
- for (k = 0; k < no_of_demods; k++) {
- st.cfg = cfg[k];
- st.i2c_addr = (0x40 + k) << 1;
-
- // unforce divstr
- dib7000m_write_word(&st,1794, st.i2c_addr << 2);
-
- /* deactivate div - it was just for i2c-enumeration */
- dib7000m_set_output_mode(&st, OUTMODE_HIGH_Z);
- }
-
- return 0;
-}
-EXPORT_SYMBOL(dib7000m_i2c_enumeration);
-#endif
-
-static struct dvb_frontend_ops dib7000m_ops;
-struct dvb_frontend * dib7000m_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000m_config *cfg)
-{
- struct dvb_frontend *demod;
- struct dib7000m_state *st;
- st = kzalloc(sizeof(struct dib7000m_state), GFP_KERNEL);
- if (st == NULL)
- return NULL;
-
- memcpy(&st->cfg, cfg, sizeof(struct dib7000m_config));
- st->i2c_adap = i2c_adap;
- st->i2c_addr = i2c_addr;
-
- demod = &st->demod;
- demod->demodulator_priv = st;
- memcpy(&st->demod.ops, &dib7000m_ops, sizeof(struct dvb_frontend_ops));
- mutex_init(&st->i2c_buffer_lock);
-
- st->timf_default = cfg->bw->timf;
-
- if (dib7000m_identify(st) != 0)
- goto error;
-
- if (st->revision == 0x4000)
- dibx000_init_i2c_master(&st->i2c_master, DIB7000, st->i2c_adap, st->i2c_addr);
- else
- dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c_adap, st->i2c_addr);
-
- dib7000m_demod_reset(st);
-
- return demod;
-
-error:
- kfree(st);
- return NULL;
-}
-EXPORT_SYMBOL(dib7000m_attach);
-
-static struct dvb_frontend_ops dib7000m_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "DiBcom 7000MA/MB/PA/PB/MC",
- .frequency_min = 44250000,
- .frequency_max = 867250000,
- .frequency_stepsize = 62500,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_RECOVER |
- FE_CAN_HIERARCHY_AUTO,
- },
-
- .release = dib7000m_release,
-
- .init = dib7000m_wakeup,
- .sleep = dib7000m_sleep,
-
- .set_frontend = dib7000m_set_frontend,
- .get_tune_settings = dib7000m_fe_get_tune_settings,
- .get_frontend = dib7000m_get_frontend,
-
- .read_status = dib7000m_read_status,
- .read_ber = dib7000m_read_ber,
- .read_signal_strength = dib7000m_read_signal_strength,
- .read_snr = dib7000m_read_snr,
- .read_ucblocks = dib7000m_read_unc_blocks,
-};
-
-MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
-MODULE_DESCRIPTION("Driver for the DiBcom 7000MA/MB/PA/PB/MC COFDM demodulator");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib7000m.h b/drivers/media/dvb/frontends/dib7000m.h
deleted file mode 100644
index 81fcf2241c6..00000000000
--- a/drivers/media/dvb/frontends/dib7000m.h
+++ /dev/null
@@ -1,90 +0,0 @@
-#ifndef DIB7000M_H
-#define DIB7000M_H
-
-#include "dibx000_common.h"
-
-struct dib7000m_config {
- u8 dvbt_mode;
- u8 output_mpeg2_in_188_bytes;
- u8 hostbus_diversity;
- u8 tuner_is_baseband;
- u8 mobile_mode;
- int (*update_lna) (struct dvb_frontend *, u16 agc_global);
-
- u8 agc_config_count;
- struct dibx000_agc_config *agc;
-
- struct dibx000_bandwidth_config *bw;
-
-#define DIB7000M_GPIO_DEFAULT_DIRECTIONS 0xffff
- u16 gpio_dir;
-#define DIB7000M_GPIO_DEFAULT_VALUES 0x0000
- u16 gpio_val;
-#define DIB7000M_GPIO_PWM_POS0(v) ((v & 0xf) << 12)
-#define DIB7000M_GPIO_PWM_POS1(v) ((v & 0xf) << 8 )
-#define DIB7000M_GPIO_PWM_POS2(v) ((v & 0xf) << 4 )
-#define DIB7000M_GPIO_PWM_POS3(v) (v & 0xf)
-#define DIB7000M_GPIO_DEFAULT_PWM_POS 0xffff
- u16 gpio_pwm_pos;
-
- u16 pwm_freq_div;
-
- u8 quartz_direct;
-
- u8 input_clk_is_div_2;
-
- int (*agc_control) (struct dvb_frontend *, u8 before);
-};
-
-#define DEFAULT_DIB7000M_I2C_ADDRESS 18
-
-#if defined(CONFIG_DVB_DIB7000M) || (defined(CONFIG_DVB_DIB7000M_MODULE) && \
- defined(MODULE))
-extern struct dvb_frontend *dib7000m_attach(struct i2c_adapter *i2c_adap,
- u8 i2c_addr,
- struct dib7000m_config *cfg);
-extern struct i2c_adapter *dib7000m_get_i2c_master(struct dvb_frontend *,
- enum dibx000_i2c_interface,
- int);
-extern int dib7000m_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
-extern int dib7000m_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
-#else
-static inline
-struct dvb_frontend *dib7000m_attach(struct i2c_adapter *i2c_adap,
- u8 i2c_addr, struct dib7000m_config *cfg)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline
-struct i2c_adapter *dib7000m_get_i2c_master(struct dvb_frontend *demod,
- enum dibx000_i2c_interface intf,
- int gating)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-static inline int dib7000m_pid_filter(struct dvb_frontend *fe, u8 id,
- u16 pid, u8 onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib7000m_pid_filter_ctrl(struct dvb_frontend *fe,
- uint8_t onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-#endif
-
-/* TODO
-extern INT dib7000m_set_gpio(struct dibDemod *demod, UCHAR num, UCHAR dir, UCHAR val);
-extern INT dib7000m_enable_vbg_voltage(struct dibDemod *demod);
-extern void dib7000m_set_hostbus_diversity(struct dibDemod *demod, UCHAR onoff);
-extern USHORT dib7000m_get_current_agc_global(struct dibDemod *demod);
-*/
-
-#endif
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
deleted file mode 100644
index 3e1eefada0e..00000000000
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ /dev/null
@@ -1,2457 +0,0 @@
-/*
- * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
- *
- * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- */
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/i2c.h>
-#include <linux/mutex.h>
-
-#include "dvb_math.h"
-#include "dvb_frontend.h"
-
-#include "dib7000p.h"
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
-
-static int buggy_sfn_workaround;
-module_param(buggy_sfn_workaround, int, 0644);
-MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
-
-#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0)
-
-struct i2c_device {
- struct i2c_adapter *i2c_adap;
- u8 i2c_addr;
-};
-
-struct dib7000p_state {
- struct dvb_frontend demod;
- struct dib7000p_config cfg;
-
- u8 i2c_addr;
- struct i2c_adapter *i2c_adap;
-
- struct dibx000_i2c_master i2c_master;
-
- u16 wbd_ref;
-
- u8 current_band;
- u32 current_bandwidth;
- struct dibx000_agc_config *current_agc;
- u32 timf;
-
- u8 div_force_off:1;
- u8 div_state:1;
- u16 div_sync_wait;
-
- u8 agc_state;
-
- u16 gpio_dir;
- u16 gpio_val;
-
- u8 sfn_workaround_active:1;
-
-#define SOC7090 0x7090
- u16 version;
-
- u16 tuner_enable;
- struct i2c_adapter dib7090_tuner_adap;
-
- /* for the I2C transfer */
- struct i2c_msg msg[2];
- u8 i2c_write_buffer[4];
- u8 i2c_read_buffer[2];
- struct mutex i2c_buffer_lock;
-
- u8 input_mode_mpeg;
-};
-
-enum dib7000p_power_mode {
- DIB7000P_POWER_ALL = 0,
- DIB7000P_POWER_ANALOG_ADC,
- DIB7000P_POWER_INTERFACE_ONLY,
-};
-
-/* dib7090 specific fonctions */
-static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
-static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
-static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode);
-static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode);
-
-static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
-{
- u16 ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return 0;
- }
-
- state->i2c_write_buffer[0] = reg >> 8;
- state->i2c_write_buffer[1] = reg & 0xff;
-
- memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
- state->msg[0].addr = state->i2c_addr >> 1;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 2;
- state->msg[1].addr = state->i2c_addr >> 1;
- state->msg[1].flags = I2C_M_RD;
- state->msg[1].buf = state->i2c_read_buffer;
- state->msg[1].len = 2;
-
- if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
- dprintk("i2c read error on %d", reg);
-
- ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
- mutex_unlock(&state->i2c_buffer_lock);
- return ret;
-}
-
-static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
-{
- int ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
-
- state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
- state->i2c_write_buffer[1] = reg & 0xff;
- state->i2c_write_buffer[2] = (val >> 8) & 0xff;
- state->i2c_write_buffer[3] = val & 0xff;
-
- memset(&state->msg[0], 0, sizeof(struct i2c_msg));
- state->msg[0].addr = state->i2c_addr >> 1;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 4;
-
- ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
- -EREMOTEIO : 0);
- mutex_unlock(&state->i2c_buffer_lock);
- return ret;
-}
-
-static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
-{
- u16 l = 0, r, *n;
- n = buf;
- l = *n++;
- while (l) {
- r = *n++;
-
- do {
- dib7000p_write_word(state, r, *n++);
- r++;
- } while (--l);
- l = *n++;
- }
-}
-
-static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
-{
- int ret = 0;
- u16 outreg, fifo_threshold, smo_mode;
-
- outreg = 0;
- fifo_threshold = 1792;
- smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
-
- dprintk("setting output mode for demod %p to %d", &state->demod, mode);
-
- switch (mode) {
- case OUTMODE_MPEG2_PAR_GATED_CLK:
- outreg = (1 << 10); /* 0x0400 */
- break;
- case OUTMODE_MPEG2_PAR_CONT_CLK:
- outreg = (1 << 10) | (1 << 6); /* 0x0440 */
- break;
- case OUTMODE_MPEG2_SERIAL:
- outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
- break;
- case OUTMODE_DIVERSITY:
- if (state->cfg.hostbus_diversity)
- outreg = (1 << 10) | (4 << 6); /* 0x0500 */
- else
- outreg = (1 << 11);
- break;
- case OUTMODE_MPEG2_FIFO:
- smo_mode |= (3 << 1);
- fifo_threshold = 512;
- outreg = (1 << 10) | (5 << 6);
- break;
- case OUTMODE_ANALOG_ADC:
- outreg = (1 << 10) | (3 << 6);
- break;
- case OUTMODE_HIGH_Z:
- outreg = 0;
- break;
- default:
- dprintk("Unhandled output_mode passed to be set for demod %p", &state->demod);
- break;
- }
-
- if (state->cfg.output_mpeg2_in_188_bytes)
- smo_mode |= (1 << 5);
-
- ret |= dib7000p_write_word(state, 235, smo_mode);
- ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
- if (state->version != SOC7090)
- ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */
-
- return ret;
-}
-
-static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
-{
- struct dib7000p_state *state = demod->demodulator_priv;
-
- if (state->div_force_off) {
- dprintk("diversity combination deactivated - forced by COFDM parameters");
- onoff = 0;
- dib7000p_write_word(state, 207, 0);
- } else
- dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
-
- state->div_state = (u8) onoff;
-
- if (onoff) {
- dib7000p_write_word(state, 204, 6);
- dib7000p_write_word(state, 205, 16);
- /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
- } else {
- dib7000p_write_word(state, 204, 1);
- dib7000p_write_word(state, 205, 0);
- }
-
- return 0;
-}
-
-static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
-{
- /* by default everything is powered off */
- u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
-
- /* now, depending on the requested mode, we power on */
- switch (mode) {
- /* power up everything in the demod */
- case DIB7000P_POWER_ALL:
- reg_774 = 0x0000;
- reg_775 = 0x0000;
- reg_776 = 0x0;
- reg_899 = 0x0;
- if (state->version == SOC7090)
- reg_1280 &= 0x001f;
- else
- reg_1280 &= 0x01ff;
- break;
-
- case DIB7000P_POWER_ANALOG_ADC:
- /* dem, cfg, iqc, sad, agc */
- reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
- /* nud */
- reg_776 &= ~((1 << 0));
- /* Dout */
- if (state->version != SOC7090)
- reg_1280 &= ~((1 << 11));
- reg_1280 &= ~(1 << 6);
- /* fall through wanted to enable the interfaces */
-
- /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
- case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */
- if (state->version == SOC7090)
- reg_1280 &= ~((1 << 7) | (1 << 5));
- else
- reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
- break;
-
-/* TODO following stuff is just converted from the dib7000-driver - check when is used what */
- }
-
- dib7000p_write_word(state, 774, reg_774);
- dib7000p_write_word(state, 775, reg_775);
- dib7000p_write_word(state, 776, reg_776);
- dib7000p_write_word(state, 1280, reg_1280);
- if (state->version != SOC7090)
- dib7000p_write_word(state, 899, reg_899);
-
- return 0;
-}
-
-static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
-{
- u16 reg_908 = 0, reg_909 = 0;
- u16 reg;
-
- if (state->version != SOC7090) {
- reg_908 = dib7000p_read_word(state, 908);
- reg_909 = dib7000p_read_word(state, 909);
- }
-
- switch (no) {
- case DIBX000_SLOW_ADC_ON:
- if (state->version == SOC7090) {
- reg = dib7000p_read_word(state, 1925);
-
- dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */
-
- reg = dib7000p_read_word(state, 1925); /* read acces to make it works... strange ... */
- msleep(200);
- dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */
-
- reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
- dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
- } else {
- reg_909 |= (1 << 1) | (1 << 0);
- dib7000p_write_word(state, 909, reg_909);
- reg_909 &= ~(1 << 1);
- }
- break;
-
- case DIBX000_SLOW_ADC_OFF:
- if (state->version == SOC7090) {
- reg = dib7000p_read_word(state, 1925);
- dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
- } else
- reg_909 |= (1 << 1) | (1 << 0);
- break;
-
- case DIBX000_ADC_ON:
- reg_908 &= 0x0fff;
- reg_909 &= 0x0003;
- break;
-
- case DIBX000_ADC_OFF:
- reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
- reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
- break;
-
- case DIBX000_VBG_ENABLE:
- reg_908 &= ~(1 << 15);
- break;
-
- case DIBX000_VBG_DISABLE:
- reg_908 |= (1 << 15);
- break;
-
- default:
- break;
- }
-
-// dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
-
- reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
- reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
-
- if (state->version != SOC7090) {
- dib7000p_write_word(state, 908, reg_908);
- dib7000p_write_word(state, 909, reg_909);
- }
-}
-
-static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
-{
- u32 timf;
-
- // store the current bandwidth for later use
- state->current_bandwidth = bw;
-
- if (state->timf == 0) {
- dprintk("using default timf");
- timf = state->cfg.bw->timf;
- } else {
- dprintk("using updated timf");
- timf = state->timf;
- }
-
- timf = timf * (bw / 50) / 160;
-
- dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
- dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
-
- return 0;
-}
-
-static int dib7000p_sad_calib(struct dib7000p_state *state)
-{
-/* internal */
- dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
-
- if (state->version == SOC7090)
- dib7000p_write_word(state, 74, 2048);
- else
- dib7000p_write_word(state, 74, 776);
-
- /* do the calibration */
- dib7000p_write_word(state, 73, (1 << 0));
- dib7000p_write_word(state, 73, (0 << 0));
-
- msleep(1);
-
- return 0;
-}
-
-int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
-{
- struct dib7000p_state *state = demod->demodulator_priv;
- if (value > 4095)
- value = 4095;
- state->wbd_ref = value;
- return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
-}
-EXPORT_SYMBOL(dib7000p_set_wbd_ref);
-
-int dib7000p_get_agc_values(struct dvb_frontend *fe,
- u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
-
- if (agc_global != NULL)
- *agc_global = dib7000p_read_word(state, 394);
- if (agc1 != NULL)
- *agc1 = dib7000p_read_word(state, 392);
- if (agc2 != NULL)
- *agc2 = dib7000p_read_word(state, 393);
- if (wbd != NULL)
- *wbd = dib7000p_read_word(state, 397);
-
- return 0;
-}
-EXPORT_SYMBOL(dib7000p_get_agc_values);
-
-static void dib7000p_reset_pll(struct dib7000p_state *state)
-{
- struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
- u16 clk_cfg0;
-
- if (state->version == SOC7090) {
- dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
-
- while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
- ;
-
- dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
- } else {
- /* force PLL bypass */
- clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
- (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
-
- dib7000p_write_word(state, 900, clk_cfg0);
-
- /* P_pll_cfg */
- dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
- clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
- dib7000p_write_word(state, 900, clk_cfg0);
- }
-
- dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
- dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
- dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
- dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
-
- dib7000p_write_word(state, 72, bw->sad_cfg);
-}
-
-static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
-{
- u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
- internal |= (u32) dib7000p_read_word(state, 19);
- internal /= 1000;
-
- return internal;
-}
-
-int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
- u8 loopdiv, prediv;
- u32 internal, xtal;
-
- /* get back old values */
- prediv = reg_1856 & 0x3f;
- loopdiv = (reg_1856 >> 6) & 0x3f;
-
- if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
- dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
- reg_1856 &= 0xf000;
- reg_1857 = dib7000p_read_word(state, 1857);
- dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
-
- dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
-
- /* write new system clk into P_sec_len */
- internal = dib7000p_get_internal_freq(state);
- xtal = (internal / loopdiv) * prediv;
- internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
- dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
- dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
-
- dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
-
- while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
- dprintk("Waiting for PLL to lock");
-
- return 0;
- }
- return -EIO;
-}
-EXPORT_SYMBOL(dib7000p_update_pll);
-
-static int dib7000p_reset_gpio(struct dib7000p_state *st)
-{
- /* reset the GPIOs */
- dprintk("gpio dir: %x: val: %x, pwm_pos: %x", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
-
- dib7000p_write_word(st, 1029, st->gpio_dir);
- dib7000p_write_word(st, 1030, st->gpio_val);
-
- /* TODO 1031 is P_gpio_od */
-
- dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos);
-
- dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div);
- return 0;
-}
-
-static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
-{
- st->gpio_dir = dib7000p_read_word(st, 1029);
- st->gpio_dir &= ~(1 << num); /* reset the direction bit */
- st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
- dib7000p_write_word(st, 1029, st->gpio_dir);
-
- st->gpio_val = dib7000p_read_word(st, 1030);
- st->gpio_val &= ~(1 << num); /* reset the direction bit */
- st->gpio_val |= (val & 0x01) << num; /* set the new value */
- dib7000p_write_word(st, 1030, st->gpio_val);
-
- return 0;
-}
-
-int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
-{
- struct dib7000p_state *state = demod->demodulator_priv;
- return dib7000p_cfg_gpio(state, num, dir, val);
-}
-EXPORT_SYMBOL(dib7000p_set_gpio);
-
-static u16 dib7000p_defaults[] = {
- // auto search configuration
- 3, 2,
- 0x0004,
- (1<<3)|(1<<11)|(1<<12)|(1<<13),
- 0x0814, /* Equal Lock */
-
- 12, 6,
- 0x001b,
- 0x7740,
- 0x005b,
- 0x8d80,
- 0x01c9,
- 0xc380,
- 0x0000,
- 0x0080,
- 0x0000,
- 0x0090,
- 0x0001,
- 0xd4c0,
-
- 1, 26,
- 0x6680,
-
- /* set ADC level to -16 */
- 11, 79,
- (1 << 13) - 825 - 117,
- (1 << 13) - 837 - 117,
- (1 << 13) - 811 - 117,
- (1 << 13) - 766 - 117,
- (1 << 13) - 737 - 117,
- (1 << 13) - 693 - 117,
- (1 << 13) - 648 - 117,
- (1 << 13) - 619 - 117,
- (1 << 13) - 575 - 117,
- (1 << 13) - 531 - 117,
- (1 << 13) - 501 - 117,
-
- 1, 142,
- 0x0410,
-
- /* disable power smoothing */
- 8, 145,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
-
- 1, 154,
- 1 << 13,
-
- 1, 168,
- 0x0ccd,
-
- 1, 183,
- 0x200f,
-
- 1, 212,
- 0x169,
-
- 5, 187,
- 0x023d,
- 0x00a4,
- 0x00a4,
- 0x7ff0,
- 0x3ccc,
-
- 1, 198,
- 0x800,
-
- 1, 222,
- 0x0010,
-
- 1, 235,
- 0x0062,
-
- 0,
-};
-
-static int dib7000p_demod_reset(struct dib7000p_state *state)
-{
- dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
-
- if (state->version == SOC7090)
- dibx000_reset_i2c_master(&state->i2c_master);
-
- dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
-
- /* restart all parts */
- dib7000p_write_word(state, 770, 0xffff);
- dib7000p_write_word(state, 771, 0xffff);
- dib7000p_write_word(state, 772, 0x001f);
- dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
-
- dib7000p_write_word(state, 770, 0);
- dib7000p_write_word(state, 771, 0);
- dib7000p_write_word(state, 772, 0);
- dib7000p_write_word(state, 1280, 0);
-
- if (state->version != SOC7090) {
- dib7000p_write_word(state, 898, 0x0003);
- dib7000p_write_word(state, 898, 0);
- }
-
- /* default */
- dib7000p_reset_pll(state);
-
- if (dib7000p_reset_gpio(state) != 0)
- dprintk("GPIO reset was not successful.");
-
- if (state->version == SOC7090) {
- dib7000p_write_word(state, 899, 0);
-
- /* impulse noise */
- dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
- dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
- dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
- dib7000p_write_word(state, 273, (0<<6) | 30);
- }
- if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
- dprintk("OUTPUT_MODE could not be reset.");
-
- dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
- dib7000p_sad_calib(state);
- dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
-
- /* unforce divstr regardless whether i2c enumeration was done or not */
- dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
-
- dib7000p_set_bandwidth(state, 8000);
-
- if (state->version == SOC7090) {
- dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
- } else {
- if (state->cfg.tuner_is_baseband)
- dib7000p_write_word(state, 36, 0x0755);
- else
- dib7000p_write_word(state, 36, 0x1f55);
- }
-
- dib7000p_write_tab(state, dib7000p_defaults);
- if (state->version != SOC7090) {
- dib7000p_write_word(state, 901, 0x0006);
- dib7000p_write_word(state, 902, (3 << 10) | (1 << 6));
- dib7000p_write_word(state, 905, 0x2c8e);
- }
-
- dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
-
- return 0;
-}
-
-static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
-{
- u16 tmp = 0;
- tmp = dib7000p_read_word(state, 903);
- dib7000p_write_word(state, 903, (tmp | 0x1));
- tmp = dib7000p_read_word(state, 900);
- dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
-}
-
-static void dib7000p_restart_agc(struct dib7000p_state *state)
-{
- // P_restart_iqc & P_restart_agc
- dib7000p_write_word(state, 770, (1 << 11) | (1 << 9));
- dib7000p_write_word(state, 770, 0x0000);
-}
-
-static int dib7000p_update_lna(struct dib7000p_state *state)
-{
- u16 dyn_gain;
-
- if (state->cfg.update_lna) {
- dyn_gain = dib7000p_read_word(state, 394);
- if (state->cfg.update_lna(&state->demod, dyn_gain)) {
- dib7000p_restart_agc(state);
- return 1;
- }
- }
-
- return 0;
-}
-
-static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
-{
- struct dibx000_agc_config *agc = NULL;
- int i;
- if (state->current_band == band && state->current_agc != NULL)
- return 0;
- state->current_band = band;
-
- for (i = 0; i < state->cfg.agc_config_count; i++)
- if (state->cfg.agc[i].band_caps & band) {
- agc = &state->cfg.agc[i];
- break;
- }
-
- if (agc == NULL) {
- dprintk("no valid AGC configuration found for band 0x%02x", band);
- return -EINVAL;
- }
-
- state->current_agc = agc;
-
- /* AGC */
- dib7000p_write_word(state, 75, agc->setup);
- dib7000p_write_word(state, 76, agc->inv_gain);
- dib7000p_write_word(state, 77, agc->time_stabiliz);
- dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
-
- // Demod AGC loop configuration
- dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
- dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
-
- /* AGC continued */
- dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
- state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
-
- if (state->wbd_ref != 0)
- dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
- else
- dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
-
- dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
-
- dib7000p_write_word(state, 107, agc->agc1_max);
- dib7000p_write_word(state, 108, agc->agc1_min);
- dib7000p_write_word(state, 109, agc->agc2_max);
- dib7000p_write_word(state, 110, agc->agc2_min);
- dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
- dib7000p_write_word(state, 112, agc->agc1_pt3);
- dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
- dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
- dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
- return 0;
-}
-
-static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
-{
- u32 internal = dib7000p_get_internal_freq(state);
- s32 unit_khz_dds_val = 67108864 / (internal); /* 2**26 / Fsampling is the unit 1KHz offset */
- u32 abs_offset_khz = ABS(offset_khz);
- u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
- u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
-
- dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d", offset_khz, internal, invert);
-
- if (offset_khz < 0)
- unit_khz_dds_val *= -1;
-
- /* IF tuner */
- if (invert)
- dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
- else
- dds += (abs_offset_khz * unit_khz_dds_val);
-
- if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
- dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
- dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
- }
-}
-
-static int dib7000p_agc_startup(struct dvb_frontend *demod)
-{
- struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
- struct dib7000p_state *state = demod->demodulator_priv;
- int ret = -1;
- u8 *agc_state = &state->agc_state;
- u8 agc_split;
- u16 reg;
- u32 upd_demod_gain_period = 0x1000;
-
- switch (state->agc_state) {
- case 0:
- dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
- if (state->version == SOC7090) {
- reg = dib7000p_read_word(state, 0x79b) & 0xff00;
- dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */
- dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
-
- /* enable adc i & q */
- reg = dib7000p_read_word(state, 0x780);
- dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
- } else {
- dib7000p_set_adc_state(state, DIBX000_ADC_ON);
- dib7000p_pll_clk_cfg(state);
- }
-
- if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
- return -1;
-
- dib7000p_set_dds(state, 0);
- ret = 7;
- (*agc_state)++;
- break;
-
- case 1:
- if (state->cfg.agc_control)
- state->cfg.agc_control(&state->demod, 1);
-
- dib7000p_write_word(state, 78, 32768);
- if (!state->current_agc->perform_agc_softsplit) {
- /* we are using the wbd - so slow AGC startup */
- /* force 0 split on WBD and restart AGC */
- dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
- (*agc_state)++;
- ret = 5;
- } else {
- /* default AGC startup */
- (*agc_state) = 4;
- /* wait AGC rough lock time */
- ret = 7;
- }
-
- dib7000p_restart_agc(state);
- break;
-
- case 2: /* fast split search path after 5sec */
- dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
- dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
- (*agc_state)++;
- ret = 14;
- break;
-
- case 3: /* split search ended */
- agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */
- dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
-
- dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
- dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
-
- dib7000p_restart_agc(state);
-
- dprintk("SPLIT %p: %hd", demod, agc_split);
-
- (*agc_state)++;
- ret = 5;
- break;
-
- case 4: /* LNA startup */
- ret = 7;
-
- if (dib7000p_update_lna(state))
- ret = 5;
- else
- (*agc_state)++;
- break;
-
- case 5:
- if (state->cfg.agc_control)
- state->cfg.agc_control(&state->demod, 0);
- (*agc_state)++;
- break;
- default:
- break;
- }
- return ret;
-}
-
-static void dib7000p_update_timf(struct dib7000p_state *state)
-{
- u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428);
- state->timf = timf * 160 / (state->current_bandwidth / 50);
- dib7000p_write_word(state, 23, (u16) (timf >> 16));
- dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
- dprintk("updated timf_frequency: %d (default: %d)", state->timf, state->cfg.bw->timf);
-
-}
-
-u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- switch (op) {
- case DEMOD_TIMF_SET:
- state->timf = timf;
- break;
- case DEMOD_TIMF_UPDATE:
- dib7000p_update_timf(state);
- break;
- case DEMOD_TIMF_GET:
- break;
- }
- dib7000p_set_bandwidth(state, state->current_bandwidth);
- return state->timf;
-}
-EXPORT_SYMBOL(dib7000p_ctrl_timf);
-
-static void dib7000p_set_channel(struct dib7000p_state *state,
- struct dtv_frontend_properties *ch, u8 seq)
-{
- u16 value, est[4];
-
- dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
-
- /* nfft, guard, qam, alpha */
- value = 0;
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_2K:
- value |= (0 << 7);
- break;
- case TRANSMISSION_MODE_4K:
- value |= (2 << 7);
- break;
- default:
- case TRANSMISSION_MODE_8K:
- value |= (1 << 7);
- break;
- }
- switch (ch->guard_interval) {
- case GUARD_INTERVAL_1_32:
- value |= (0 << 5);
- break;
- case GUARD_INTERVAL_1_16:
- value |= (1 << 5);
- break;
- case GUARD_INTERVAL_1_4:
- value |= (3 << 5);
- break;
- default:
- case GUARD_INTERVAL_1_8:
- value |= (2 << 5);
- break;
- }
- switch (ch->modulation) {
- case QPSK:
- value |= (0 << 3);
- break;
- case QAM_16:
- value |= (1 << 3);
- break;
- default:
- case QAM_64:
- value |= (2 << 3);
- break;
- }
- switch (HIERARCHY_1) {
- case HIERARCHY_2:
- value |= 2;
- break;
- case HIERARCHY_4:
- value |= 4;
- break;
- default:
- case HIERARCHY_1:
- value |= 1;
- break;
- }
- dib7000p_write_word(state, 0, value);
- dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
-
- /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
- value = 0;
- if (1 != 0)
- value |= (1 << 6);
- if (ch->hierarchy == 1)
- value |= (1 << 4);
- if (1 == 1)
- value |= 1;
- switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
- case FEC_2_3:
- value |= (2 << 1);
- break;
- case FEC_3_4:
- value |= (3 << 1);
- break;
- case FEC_5_6:
- value |= (5 << 1);
- break;
- case FEC_7_8:
- value |= (7 << 1);
- break;
- default:
- case FEC_1_2:
- value |= (1 << 1);
- break;
- }
- dib7000p_write_word(state, 208, value);
-
- /* offset loop parameters */
- dib7000p_write_word(state, 26, 0x6680);
- dib7000p_write_word(state, 32, 0x0003);
- dib7000p_write_word(state, 29, 0x1273);
- dib7000p_write_word(state, 33, 0x0005);
-
- /* P_dvsy_sync_wait */
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_8K:
- value = 256;
- break;
- case TRANSMISSION_MODE_4K:
- value = 128;
- break;
- case TRANSMISSION_MODE_2K:
- default:
- value = 64;
- break;
- }
- switch (ch->guard_interval) {
- case GUARD_INTERVAL_1_16:
- value *= 2;
- break;
- case GUARD_INTERVAL_1_8:
- value *= 4;
- break;
- case GUARD_INTERVAL_1_4:
- value *= 8;
- break;
- default:
- case GUARD_INTERVAL_1_32:
- value *= 1;
- break;
- }
- if (state->cfg.diversity_delay == 0)
- state->div_sync_wait = (value * 3) / 2 + 48;
- else
- state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
-
- /* deactive the possibility of diversity reception if extended interleaver */
- state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K;
- dib7000p_set_diversity_in(&state->demod, state->div_state);
-
- /* channel estimation fine configuration */
- switch (ch->modulation) {
- case QAM_64:
- est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
- est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
- est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
- est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
- break;
- case QAM_16:
- est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
- est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
- est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
- est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
- break;
- default:
- est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
- est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
- est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
- est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
- break;
- }
- for (value = 0; value < 4; value++)
- dib7000p_write_word(state, 187 + value, est[value]);
-}
-
-static int dib7000p_autosearch_start(struct dvb_frontend *demod)
-{
- struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
- struct dib7000p_state *state = demod->demodulator_priv;
- struct dtv_frontend_properties schan;
- u32 value, factor;
- u32 internal = dib7000p_get_internal_freq(state);
-
- schan = *ch;
- schan.modulation = QAM_64;
- schan.guard_interval = GUARD_INTERVAL_1_32;
- schan.transmission_mode = TRANSMISSION_MODE_8K;
- schan.code_rate_HP = FEC_2_3;
- schan.code_rate_LP = FEC_3_4;
- schan.hierarchy = 0;
-
- dib7000p_set_channel(state, &schan, 7);
-
- factor = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
- if (factor >= 5000) {
- if (state->version == SOC7090)
- factor = 2;
- else
- factor = 1;
- } else
- factor = 6;
-
- value = 30 * internal * factor;
- dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
- dib7000p_write_word(state, 7, (u16) (value & 0xffff));
- value = 100 * internal * factor;
- dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
- dib7000p_write_word(state, 9, (u16) (value & 0xffff));
- value = 500 * internal * factor;
- dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
- dib7000p_write_word(state, 11, (u16) (value & 0xffff));
-
- value = dib7000p_read_word(state, 0);
- dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
- dib7000p_read_word(state, 1284);
- dib7000p_write_word(state, 0, (u16) value);
-
- return 0;
-}
-
-static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
-{
- struct dib7000p_state *state = demod->demodulator_priv;
- u16 irq_pending = dib7000p_read_word(state, 1284);
-
- if (irq_pending & 0x1)
- return 1;
-
- if (irq_pending & 0x2)
- return 2;
-
- return 0;
-}
-
-static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
-{
- static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
- static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
- 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
- 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
- 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
- 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
- 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
- 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
- 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
- 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
- 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
- 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
- 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
- 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
- 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
- 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
- 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
- 255, 255, 255, 255, 255, 255
- };
-
- u32 xtal = state->cfg.bw->xtal_hz / 1000;
- int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
- int k;
- int coef_re[8], coef_im[8];
- int bw_khz = bw;
- u32 pha;
-
- dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal);
-
- if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
- return;
-
- bw_khz /= 100;
-
- dib7000p_write_word(state, 142, 0x0610);
-
- for (k = 0; k < 8; k++) {
- pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
-
- if (pha == 0) {
- coef_re[k] = 256;
- coef_im[k] = 0;
- } else if (pha < 256) {
- coef_re[k] = sine[256 - (pha & 0xff)];
- coef_im[k] = sine[pha & 0xff];
- } else if (pha == 256) {
- coef_re[k] = 0;
- coef_im[k] = 256;
- } else if (pha < 512) {
- coef_re[k] = -sine[pha & 0xff];
- coef_im[k] = sine[256 - (pha & 0xff)];
- } else if (pha == 512) {
- coef_re[k] = -256;
- coef_im[k] = 0;
- } else if (pha < 768) {
- coef_re[k] = -sine[256 - (pha & 0xff)];
- coef_im[k] = -sine[pha & 0xff];
- } else if (pha == 768) {
- coef_re[k] = 0;
- coef_im[k] = -256;
- } else {
- coef_re[k] = sine[pha & 0xff];
- coef_im[k] = -sine[256 - (pha & 0xff)];
- }
-
- coef_re[k] *= notch[k];
- coef_re[k] += (1 << 14);
- if (coef_re[k] >= (1 << 24))
- coef_re[k] = (1 << 24) - 1;
- coef_re[k] /= (1 << 15);
-
- coef_im[k] *= notch[k];
- coef_im[k] += (1 << 14);
- if (coef_im[k] >= (1 << 24))
- coef_im[k] = (1 << 24) - 1;
- coef_im[k] /= (1 << 15);
-
- dprintk("PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]);
-
- dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
- dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
- dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
- }
- dib7000p_write_word(state, 143, 0);
-}
-
-static int dib7000p_tune(struct dvb_frontend *demod)
-{
- struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
- struct dib7000p_state *state = demod->demodulator_priv;
- u16 tmp = 0;
-
- if (ch != NULL)
- dib7000p_set_channel(state, ch, 0);
- else
- return -EINVAL;
-
- // restart demod
- dib7000p_write_word(state, 770, 0x4000);
- dib7000p_write_word(state, 770, 0x0000);
- msleep(45);
-
- /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
- tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
- if (state->sfn_workaround_active) {
- dprintk("SFN workaround is active");
- tmp |= (1 << 9);
- dib7000p_write_word(state, 166, 0x4000);
- } else {
- dib7000p_write_word(state, 166, 0x0000);
- }
- dib7000p_write_word(state, 29, tmp);
-
- // never achieved a lock with that bandwidth so far - wait for osc-freq to update
- if (state->timf == 0)
- msleep(200);
-
- /* offset loop parameters */
-
- /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
- tmp = (6 << 8) | 0x80;
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_2K:
- tmp |= (2 << 12);
- break;
- case TRANSMISSION_MODE_4K:
- tmp |= (3 << 12);
- break;
- default:
- case TRANSMISSION_MODE_8K:
- tmp |= (4 << 12);
- break;
- }
- dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
-
- /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
- tmp = (0 << 4);
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_2K:
- tmp |= 0x6;
- break;
- case TRANSMISSION_MODE_4K:
- tmp |= 0x7;
- break;
- default:
- case TRANSMISSION_MODE_8K:
- tmp |= 0x8;
- break;
- }
- dib7000p_write_word(state, 32, tmp);
-
- /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
- tmp = (0 << 4);
- switch (ch->transmission_mode) {
- case TRANSMISSION_MODE_2K:
- tmp |= 0x6;
- break;
- case TRANSMISSION_MODE_4K:
- tmp |= 0x7;
- break;
- default:
- case TRANSMISSION_MODE_8K:
- tmp |= 0x8;
- break;
- }
- dib7000p_write_word(state, 33, tmp);
-
- tmp = dib7000p_read_word(state, 509);
- if (!((tmp >> 6) & 0x1)) {
- /* restart the fec */
- tmp = dib7000p_read_word(state, 771);
- dib7000p_write_word(state, 771, tmp | (1 << 1));
- dib7000p_write_word(state, 771, tmp);
- msleep(40);
- tmp = dib7000p_read_word(state, 509);
- }
- // we achieved a lock - it's time to update the osc freq
- if ((tmp >> 6) & 0x1) {
- dib7000p_update_timf(state);
- /* P_timf_alpha += 2 */
- tmp = dib7000p_read_word(state, 26);
- dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
- }
-
- if (state->cfg.spur_protect)
- dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
-
- dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
- return 0;
-}
-
-static int dib7000p_wakeup(struct dvb_frontend *demod)
-{
- struct dib7000p_state *state = demod->demodulator_priv;
- dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
- dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
- if (state->version == SOC7090)
- dib7000p_sad_calib(state);
- return 0;
-}
-
-static int dib7000p_sleep(struct dvb_frontend *demod)
-{
- struct dib7000p_state *state = demod->demodulator_priv;
- if (state->version == SOC7090)
- return dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
- return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
-}
-
-static int dib7000p_identify(struct dib7000p_state *st)
-{
- u16 value;
- dprintk("checking demod on I2C address: %d (%x)", st->i2c_addr, st->i2c_addr);
-
- if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
- dprintk("wrong Vendor ID (read=0x%x)", value);
- return -EREMOTEIO;
- }
-
- if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
- dprintk("wrong Device ID (%x)", value);
- return -EREMOTEIO;
- }
-
- return 0;
-}
-
-static int dib7000p_get_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 tps = dib7000p_read_word(state, 463);
-
- fep->inversion = INVERSION_AUTO;
-
- fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
-
- switch ((tps >> 8) & 0x3) {
- case 0:
- fep->transmission_mode = TRANSMISSION_MODE_2K;
- break;
- case 1:
- fep->transmission_mode = TRANSMISSION_MODE_8K;
- break;
- /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
- }
-
- switch (tps & 0x3) {
- case 0:
- fep->guard_interval = GUARD_INTERVAL_1_32;
- break;
- case 1:
- fep->guard_interval = GUARD_INTERVAL_1_16;
- break;
- case 2:
- fep->guard_interval = GUARD_INTERVAL_1_8;
- break;
- case 3:
- fep->guard_interval = GUARD_INTERVAL_1_4;
- break;
- }
-
- switch ((tps >> 14) & 0x3) {
- case 0:
- fep->modulation = QPSK;
- break;
- case 1:
- fep->modulation = QAM_16;
- break;
- case 2:
- default:
- fep->modulation = QAM_64;
- break;
- }
-
- /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
- /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
-
- fep->hierarchy = HIERARCHY_NONE;
- switch ((tps >> 5) & 0x7) {
- case 1:
- fep->code_rate_HP = FEC_1_2;
- break;
- case 2:
- fep->code_rate_HP = FEC_2_3;
- break;
- case 3:
- fep->code_rate_HP = FEC_3_4;
- break;
- case 5:
- fep->code_rate_HP = FEC_5_6;
- break;
- case 7:
- default:
- fep->code_rate_HP = FEC_7_8;
- break;
-
- }
-
- switch ((tps >> 2) & 0x7) {
- case 1:
- fep->code_rate_LP = FEC_1_2;
- break;
- case 2:
- fep->code_rate_LP = FEC_2_3;
- break;
- case 3:
- fep->code_rate_LP = FEC_3_4;
- break;
- case 5:
- fep->code_rate_LP = FEC_5_6;
- break;
- case 7:
- default:
- fep->code_rate_LP = FEC_7_8;
- break;
- }
-
- /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */
-
- return 0;
-}
-
-static int dib7000p_set_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
- struct dib7000p_state *state = fe->demodulator_priv;
- int time, ret;
-
- if (state->version == SOC7090)
- dib7090_set_diversity_in(fe, 0);
- else
- dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
-
- /* maybe the parameter has been changed */
- state->sfn_workaround_active = buggy_sfn_workaround;
-
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
-
- /* start up the AGC */
- state->agc_state = 0;
- do {
- time = dib7000p_agc_startup(fe);
- if (time != -1)
- msleep(time);
- } while (time != -1);
-
- if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
- fep->guard_interval == GUARD_INTERVAL_AUTO || fep->modulation == QAM_AUTO || fep->code_rate_HP == FEC_AUTO) {
- int i = 800, found;
-
- dib7000p_autosearch_start(fe);
- do {
- msleep(1);
- found = dib7000p_autosearch_is_irq(fe);
- } while (found == 0 && i--);
-
- dprintk("autosearch returns: %d", found);
- if (found == 0 || found == 1)
- return 0;
-
- dib7000p_get_frontend(fe);
- }
-
- ret = dib7000p_tune(fe);
-
- /* make this a config parameter */
- if (state->version == SOC7090) {
- dib7090_set_output_mode(fe, state->cfg.output_mode);
- if (state->cfg.enMpegOutput == 0) {
- dib7090_setDibTxMux(state, MPEG_ON_DIBTX);
- dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
- }
- } else
- dib7000p_set_output_mode(state, state->cfg.output_mode);
-
- return ret;
-}
-
-static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t * stat)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 lock = dib7000p_read_word(state, 509);
-
- *stat = 0;
-
- if (lock & 0x8000)
- *stat |= FE_HAS_SIGNAL;
- if (lock & 0x3000)
- *stat |= FE_HAS_CARRIER;
- if (lock & 0x0100)
- *stat |= FE_HAS_VITERBI;
- if (lock & 0x0010)
- *stat |= FE_HAS_SYNC;
- if ((lock & 0x0038) == 0x38)
- *stat |= FE_HAS_LOCK;
-
- return 0;
-}
-
-static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
- return 0;
-}
-
-static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- *unc = dib7000p_read_word(state, 506);
- return 0;
-}
-
-static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 val = dib7000p_read_word(state, 394);
- *strength = 65535 - val;
- return 0;
-}
-
-static int dib7000p_read_snr(struct dvb_frontend *fe, u16 * snr)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 val;
- s32 signal_mant, signal_exp, noise_mant, noise_exp;
- u32 result = 0;
-
- val = dib7000p_read_word(state, 479);
- noise_mant = (val >> 4) & 0xff;
- noise_exp = ((val & 0xf) << 2);
- val = dib7000p_read_word(state, 480);
- noise_exp += ((val >> 14) & 0x3);
- if ((noise_exp & 0x20) != 0)
- noise_exp -= 0x40;
-
- signal_mant = (val >> 6) & 0xFF;
- signal_exp = (val & 0x3F);
- if ((signal_exp & 0x20) != 0)
- signal_exp -= 0x40;
-
- if (signal_mant != 0)
- result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
- else
- result = intlog10(2) * 10 * signal_exp - 100;
-
- if (noise_mant != 0)
- result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
- else
- result -= intlog10(2) * 10 * noise_exp - 100;
-
- *snr = result / ((1 << 24) / 10);
- return 0;
-}
-
-static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
-{
- tune->min_delay_ms = 1000;
- return 0;
-}
-
-static void dib7000p_release(struct dvb_frontend *demod)
-{
- struct dib7000p_state *st = demod->demodulator_priv;
- dibx000_exit_i2c_master(&st->i2c_master);
- i2c_del_adapter(&st->dib7090_tuner_adap);
- kfree(st);
-}
-
-int dib7000pc_detection(struct i2c_adapter *i2c_adap)
-{
- u8 *tx, *rx;
- struct i2c_msg msg[2] = {
- {.addr = 18 >> 1, .flags = 0, .len = 2},
- {.addr = 18 >> 1, .flags = I2C_M_RD, .len = 2},
- };
- int ret = 0;
-
- tx = kzalloc(2*sizeof(u8), GFP_KERNEL);
- if (!tx)
- return -ENOMEM;
- rx = kzalloc(2*sizeof(u8), GFP_KERNEL);
- if (!rx) {
- ret = -ENOMEM;
- goto rx_memory_error;
- }
-
- msg[0].buf = tx;
- msg[1].buf = rx;
-
- tx[0] = 0x03;
- tx[1] = 0x00;
-
- if (i2c_transfer(i2c_adap, msg, 2) == 2)
- if (rx[0] == 0x01 && rx[1] == 0xb3) {
- dprintk("-D- DiB7000PC detected");
- return 1;
- }
-
- msg[0].addr = msg[1].addr = 0x40;
-
- if (i2c_transfer(i2c_adap, msg, 2) == 2)
- if (rx[0] == 0x01 && rx[1] == 0xb3) {
- dprintk("-D- DiB7000PC detected");
- return 1;
- }
-
- dprintk("-D- DiB7000PC not detected");
-
- kfree(rx);
-rx_memory_error:
- kfree(tx);
- return ret;
-}
-EXPORT_SYMBOL(dib7000pc_detection);
-
-struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
-{
- struct dib7000p_state *st = demod->demodulator_priv;
- return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
-}
-EXPORT_SYMBOL(dib7000p_get_i2c_master);
-
-int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 val = dib7000p_read_word(state, 235) & 0xffef;
- val |= (onoff & 0x1) << 4;
- dprintk("PID filter enabled %d", onoff);
- return dib7000p_write_word(state, 235, val);
-}
-EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
-
-int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
- return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
-}
-EXPORT_SYMBOL(dib7000p_pid_filter);
-
-int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
-{
- struct dib7000p_state *dpst;
- int k = 0;
- u8 new_addr = 0;
-
- dpst = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
- if (!dpst)
- return -ENOMEM;
-
- dpst->i2c_adap = i2c;
- mutex_init(&dpst->i2c_buffer_lock);
-
- for (k = no_of_demods - 1; k >= 0; k--) {
- dpst->cfg = cfg[k];
-
- /* designated i2c address */
- if (cfg[k].default_i2c_addr != 0)
- new_addr = cfg[k].default_i2c_addr + (k << 1);
- else
- new_addr = (0x40 + k) << 1;
- dpst->i2c_addr = new_addr;
- dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
- if (dib7000p_identify(dpst) != 0) {
- dpst->i2c_addr = default_addr;
- dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
- if (dib7000p_identify(dpst) != 0) {
- dprintk("DiB7000P #%d: not identified\n", k);
- kfree(dpst);
- return -EIO;
- }
- }
-
- /* start diversity to pull_down div_str - just for i2c-enumeration */
- dib7000p_set_output_mode(dpst, OUTMODE_DIVERSITY);
-
- /* set new i2c address and force divstart */
- dib7000p_write_word(dpst, 1285, (new_addr << 2) | 0x2);
-
- dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
- }
-
- for (k = 0; k < no_of_demods; k++) {
- dpst->cfg = cfg[k];
- if (cfg[k].default_i2c_addr != 0)
- dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
- else
- dpst->i2c_addr = (0x40 + k) << 1;
-
- // unforce divstr
- dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
-
- /* deactivate div - it was just for i2c-enumeration */
- dib7000p_set_output_mode(dpst, OUTMODE_HIGH_Z);
- }
-
- kfree(dpst);
- return 0;
-}
-EXPORT_SYMBOL(dib7000p_i2c_enumeration);
-
-static const s32 lut_1000ln_mant[] = {
- 6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
-};
-
-static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- u32 tmp_val = 0, exp = 0, mant = 0;
- s32 pow_i;
- u16 buf[2];
- u8 ix = 0;
-
- buf[0] = dib7000p_read_word(state, 0x184);
- buf[1] = dib7000p_read_word(state, 0x185);
- pow_i = (buf[0] << 16) | buf[1];
- dprintk("raw pow_i = %d", pow_i);
-
- tmp_val = pow_i;
- while (tmp_val >>= 1)
- exp++;
-
- mant = (pow_i * 1000 / (1 << exp));
- dprintk(" mant = %d exp = %d", mant / 1000, exp);
-
- ix = (u8) ((mant - 1000) / 100); /* index of the LUT */
- dprintk(" ix = %d", ix);
-
- pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
- pow_i = (pow_i << 8) / 1000;
- dprintk(" pow_i = %d", pow_i);
-
- return pow_i;
-}
-
-static int map_addr_to_serpar_number(struct i2c_msg *msg)
-{
- if ((msg->buf[0] <= 15))
- msg->buf[0] -= 1;
- else if (msg->buf[0] == 17)
- msg->buf[0] = 15;
- else if (msg->buf[0] == 16)
- msg->buf[0] = 17;
- else if (msg->buf[0] == 19)
- msg->buf[0] = 16;
- else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
- msg->buf[0] -= 3;
- else if (msg->buf[0] == 28)
- msg->buf[0] = 23;
- else
- return -EINVAL;
- return 0;
-}
-
-static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
-{
- struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
- u8 n_overflow = 1;
- u16 i = 1000;
- u16 serpar_num = msg[0].buf[0];
-
- while (n_overflow == 1 && i) {
- n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
- i--;
- if (i == 0)
- dprintk("Tuner ITF: write busy (overflow)");
- }
- dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
- dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
-
- return num;
-}
-
-static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
-{
- struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
- u8 n_overflow = 1, n_empty = 1;
- u16 i = 1000;
- u16 serpar_num = msg[0].buf[0];
- u16 read_word;
-
- while (n_overflow == 1 && i) {
- n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
- i--;
- if (i == 0)
- dprintk("TunerITF: read busy (overflow)");
- }
- dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
-
- i = 1000;
- while (n_empty == 1 && i) {
- n_empty = dib7000p_read_word(state, 1984) & 0x1;
- i--;
- if (i == 0)
- dprintk("TunerITF: read busy (empty)");
- }
- read_word = dib7000p_read_word(state, 1987);
- msg[1].buf[0] = (read_word >> 8) & 0xff;
- msg[1].buf[1] = (read_word) & 0xff;
-
- return num;
-}
-
-static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
-{
- if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
- if (num == 1) { /* write */
- return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
- } else { /* read */
- return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
- }
- }
- return num;
-}
-
-static int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap,
- struct i2c_msg msg[], int num, u16 apb_address)
-{
- struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
- u16 word;
-
- if (num == 1) { /* write */
- dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
- } else {
- word = dib7000p_read_word(state, apb_address);
- msg[1].buf[0] = (word >> 8) & 0xff;
- msg[1].buf[1] = (word) & 0xff;
- }
-
- return num;
-}
-
-static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
-{
- struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
-
- u16 apb_address = 0, word;
- int i = 0;
- switch (msg[0].buf[0]) {
- case 0x12:
- apb_address = 1920;
- break;
- case 0x14:
- apb_address = 1921;
- break;
- case 0x24:
- apb_address = 1922;
- break;
- case 0x1a:
- apb_address = 1923;
- break;
- case 0x22:
- apb_address = 1924;
- break;
- case 0x33:
- apb_address = 1926;
- break;
- case 0x34:
- apb_address = 1927;
- break;
- case 0x35:
- apb_address = 1928;
- break;
- case 0x36:
- apb_address = 1929;
- break;
- case 0x37:
- apb_address = 1930;
- break;
- case 0x38:
- apb_address = 1931;
- break;
- case 0x39:
- apb_address = 1932;
- break;
- case 0x2a:
- apb_address = 1935;
- break;
- case 0x2b:
- apb_address = 1936;
- break;
- case 0x2c:
- apb_address = 1937;
- break;
- case 0x2d:
- apb_address = 1938;
- break;
- case 0x2e:
- apb_address = 1939;
- break;
- case 0x2f:
- apb_address = 1940;
- break;
- case 0x30:
- apb_address = 1941;
- break;
- case 0x31:
- apb_address = 1942;
- break;
- case 0x32:
- apb_address = 1943;
- break;
- case 0x3e:
- apb_address = 1944;
- break;
- case 0x3f:
- apb_address = 1945;
- break;
- case 0x40:
- apb_address = 1948;
- break;
- case 0x25:
- apb_address = 914;
- break;
- case 0x26:
- apb_address = 915;
- break;
- case 0x27:
- apb_address = 917;
- break;
- case 0x28:
- apb_address = 916;
- break;
- case 0x1d:
- i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
- word = dib7000p_read_word(state, 384 + i);
- msg[1].buf[0] = (word >> 8) & 0xff;
- msg[1].buf[1] = (word) & 0xff;
- return num;
- case 0x1f:
- if (num == 1) { /* write */
- word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
- word &= 0x3;
- word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
- dib7000p_write_word(state, 72, word); /* Set the proper input */
- return num;
- }
- }
-
- if (apb_address != 0) /* R/W acces via APB */
- return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
- else /* R/W access via SERPAR */
- return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
-
- return 0;
-}
-
-static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
-{
- return I2C_FUNC_I2C;
-}
-
-static struct i2c_algorithm dib7090_tuner_xfer_algo = {
- .master_xfer = dib7090_tuner_xfer,
- .functionality = dib7000p_i2c_func,
-};
-
-struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
-{
- struct dib7000p_state *st = fe->demodulator_priv;
- return &st->dib7090_tuner_adap;
-}
-EXPORT_SYMBOL(dib7090_get_i2c_tuner);
-
-static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
-{
- u16 reg;
-
- /* drive host bus 2, 3, 4 */
- reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
- reg |= (drive << 12) | (drive << 6) | drive;
- dib7000p_write_word(state, 1798, reg);
-
- /* drive host bus 5,6 */
- reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
- reg |= (drive << 8) | (drive << 2);
- dib7000p_write_word(state, 1799, reg);
-
- /* drive host bus 7, 8, 9 */
- reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
- reg |= (drive << 12) | (drive << 6) | drive;
- dib7000p_write_word(state, 1800, reg);
-
- /* drive host bus 10, 11 */
- reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
- reg |= (drive << 8) | (drive << 2);
- dib7000p_write_word(state, 1801, reg);
-
- /* drive host bus 12, 13, 14 */
- reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
- reg |= (drive << 12) | (drive << 6) | drive;
- dib7000p_write_word(state, 1802, reg);
-
- return 0;
-}
-
-static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
-{
- u32 quantif = 3;
- u32 nom = (insertExtSynchro * P_Kin + syncSize);
- u32 denom = P_Kout;
- u32 syncFreq = ((nom << quantif) / denom);
-
- if ((syncFreq & ((1 << quantif) - 1)) != 0)
- syncFreq = (syncFreq >> quantif) + 1;
- else
- syncFreq = (syncFreq >> quantif);
-
- if (syncFreq != 0)
- syncFreq = syncFreq - 1;
-
- return syncFreq;
-}
-
-static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
-{
- dprintk("Configure DibStream Tx");
-
- dib7000p_write_word(state, 1615, 1);
- dib7000p_write_word(state, 1603, P_Kin);
- dib7000p_write_word(state, 1605, P_Kout);
- dib7000p_write_word(state, 1606, insertExtSynchro);
- dib7000p_write_word(state, 1608, synchroMode);
- dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
- dib7000p_write_word(state, 1610, syncWord & 0xffff);
- dib7000p_write_word(state, 1612, syncSize);
- dib7000p_write_word(state, 1615, 0);
-
- return 0;
-}
-
-static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
- u32 dataOutRate)
-{
- u32 syncFreq;
-
- dprintk("Configure DibStream Rx");
- if ((P_Kin != 0) && (P_Kout != 0)) {
- syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
- dib7000p_write_word(state, 1542, syncFreq);
- }
- dib7000p_write_word(state, 1554, 1);
- dib7000p_write_word(state, 1536, P_Kin);
- dib7000p_write_word(state, 1537, P_Kout);
- dib7000p_write_word(state, 1539, synchroMode);
- dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
- dib7000p_write_word(state, 1541, syncWord & 0xffff);
- dib7000p_write_word(state, 1543, syncSize);
- dib7000p_write_word(state, 1544, dataOutRate);
- dib7000p_write_word(state, 1554, 0);
-
- return 0;
-}
-
-static void dib7090_enMpegMux(struct dib7000p_state *state, int onoff)
-{
- u16 reg_1287 = dib7000p_read_word(state, 1287);
-
- switch (onoff) {
- case 1:
- reg_1287 &= ~(1<<7);
- break;
- case 0:
- reg_1287 |= (1<<7);
- break;
- }
-
- dib7000p_write_word(state, 1287, reg_1287);
-}
-
-static void dib7090_configMpegMux(struct dib7000p_state *state,
- u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
-{
- dprintk("Enable Mpeg mux");
-
- dib7090_enMpegMux(state, 0);
-
- /* If the input mode is MPEG do not divide the serial clock */
- if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
- enSerialClkDiv2 = 0;
-
- dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2)
- | ((enSerialMode & 0x1) << 1)
- | (enSerialClkDiv2 & 0x1));
-
- dib7090_enMpegMux(state, 1);
-}
-
-static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode)
-{
- u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7);
-
- switch (mode) {
- case MPEG_ON_DIBTX:
- dprintk("SET MPEG ON DIBSTREAM TX");
- dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
- reg_1288 |= (1<<9);
- break;
- case DIV_ON_DIBTX:
- dprintk("SET DIV_OUT ON DIBSTREAM TX");
- dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
- reg_1288 |= (1<<8);
- break;
- case ADC_ON_DIBTX:
- dprintk("SET ADC_OUT ON DIBSTREAM TX");
- dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
- reg_1288 |= (1<<7);
- break;
- default:
- break;
- }
- dib7000p_write_word(state, 1288, reg_1288);
-}
-
-static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode)
-{
- u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4);
-
- switch (mode) {
- case DEMOUT_ON_HOSTBUS:
- dprintk("SET DEM OUT OLD INTERF ON HOST BUS");
- dib7090_enMpegMux(state, 0);
- reg_1288 |= (1<<6);
- break;
- case DIBTX_ON_HOSTBUS:
- dprintk("SET DIBSTREAM TX ON HOST BUS");
- dib7090_enMpegMux(state, 0);
- reg_1288 |= (1<<5);
- break;
- case MPEG_ON_HOSTBUS:
- dprintk("SET MPEG MUX ON HOST BUS");
- reg_1288 |= (1<<4);
- break;
- default:
- break;
- }
- dib7000p_write_word(state, 1288, reg_1288);
-}
-
-int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 reg_1287;
-
- switch (onoff) {
- case 0: /* only use the internal way - not the diversity input */
- dprintk("%s mode OFF : by default Enable Mpeg INPUT", __func__);
- dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
-
- /* Do not divide the serial clock of MPEG MUX */
- /* in SERIAL MODE in case input mode MPEG is used */
- reg_1287 = dib7000p_read_word(state, 1287);
- /* enSerialClkDiv2 == 1 ? */
- if ((reg_1287 & 0x1) == 1) {
- /* force enSerialClkDiv2 = 0 */
- reg_1287 &= ~0x1;
- dib7000p_write_word(state, 1287, reg_1287);
- }
- state->input_mode_mpeg = 1;
- break;
- case 1: /* both ways */
- case 2: /* only the diversity input */
- dprintk("%s ON : Enable diversity INPUT", __func__);
- dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
- state->input_mode_mpeg = 0;
- break;
- }
-
- dib7000p_set_diversity_in(&state->demod, onoff);
- return 0;
-}
-
-static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
-
- u16 outreg, smo_mode, fifo_threshold;
- u8 prefer_mpeg_mux_use = 1;
- int ret = 0;
-
- dib7090_host_bus_drive(state, 1);
-
- fifo_threshold = 1792;
- smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
- outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
-
- switch (mode) {
- case OUTMODE_HIGH_Z:
- outreg = 0;
- break;
-
- case OUTMODE_MPEG2_SERIAL:
- if (prefer_mpeg_mux_use) {
- dprintk("setting output mode TS_SERIAL using Mpeg Mux");
- dib7090_configMpegMux(state, 3, 1, 1);
- dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
- } else {/* Use Smooth block */
- dprintk("setting output mode TS_SERIAL using Smooth bloc");
- dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
- outreg |= (2<<6) | (0 << 1);
- }
- break;
-
- case OUTMODE_MPEG2_PAR_GATED_CLK:
- if (prefer_mpeg_mux_use) {
- dprintk("setting output mode TS_PARALLEL_GATED using Mpeg Mux");
- dib7090_configMpegMux(state, 2, 0, 0);
- dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
- } else { /* Use Smooth block */
- dprintk("setting output mode TS_PARALLEL_GATED using Smooth block");
- dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
- outreg |= (0<<6);
- }
- break;
-
- case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
- dprintk("setting output mode TS_PARALLEL_CONT using Smooth block");
- dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
- outreg |= (1<<6);
- break;
-
- case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
- dprintk("setting output mode TS_FIFO using Smooth block");
- dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
- outreg |= (5<<6);
- smo_mode |= (3 << 1);
- fifo_threshold = 512;
- break;
-
- case OUTMODE_DIVERSITY:
- dprintk("setting output mode MODE_DIVERSITY");
- dib7090_setDibTxMux(state, DIV_ON_DIBTX);
- dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
- break;
-
- case OUTMODE_ANALOG_ADC:
- dprintk("setting output mode MODE_ANALOG_ADC");
- dib7090_setDibTxMux(state, ADC_ON_DIBTX);
- dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
- break;
- }
- if (mode != OUTMODE_HIGH_Z)
- outreg |= (1 << 10);
-
- if (state->cfg.output_mpeg2_in_188_bytes)
- smo_mode |= (1 << 5);
-
- ret |= dib7000p_write_word(state, 235, smo_mode);
- ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
- ret |= dib7000p_write_word(state, 1286, outreg);
-
- return ret;
-}
-
-int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 en_cur_state;
-
- dprintk("sleep dib7090: %d", onoff);
-
- en_cur_state = dib7000p_read_word(state, 1922);
-
- if (en_cur_state > 0xff)
- state->tuner_enable = en_cur_state;
-
- if (onoff)
- en_cur_state &= 0x00ff;
- else {
- if (state->tuner_enable != 0)
- en_cur_state = state->tuner_enable;
- }
-
- dib7000p_write_word(state, 1922, en_cur_state);
-
- return 0;
-}
-EXPORT_SYMBOL(dib7090_tuner_sleep);
-
-int dib7090_get_adc_power(struct dvb_frontend *fe)
-{
- return dib7000p_get_adc_power(fe);
-}
-EXPORT_SYMBOL(dib7090_get_adc_power);
-
-int dib7090_slave_reset(struct dvb_frontend *fe)
-{
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 reg;
-
- reg = dib7000p_read_word(state, 1794);
- dib7000p_write_word(state, 1794, reg | (4 << 12));
-
- dib7000p_write_word(state, 1032, 0xffff);
- return 0;
-}
-EXPORT_SYMBOL(dib7090_slave_reset);
-
-static struct dvb_frontend_ops dib7000p_ops;
-struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
-{
- struct dvb_frontend *demod;
- struct dib7000p_state *st;
- st = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
- if (st == NULL)
- return NULL;
-
- memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config));
- st->i2c_adap = i2c_adap;
- st->i2c_addr = i2c_addr;
- st->gpio_val = cfg->gpio_val;
- st->gpio_dir = cfg->gpio_dir;
-
- /* Ensure the output mode remains at the previous default if it's
- * not specifically set by the caller.
- */
- if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
- st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
-
- demod = &st->demod;
- demod->demodulator_priv = st;
- memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
- mutex_init(&st->i2c_buffer_lock);
-
- dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
-
- if (dib7000p_identify(st) != 0)
- goto error;
-
- st->version = dib7000p_read_word(st, 897);
-
- /* FIXME: make sure the dev.parent field is initialized, or else
- request_firmware() will hit an OOPS (this should be moved somewhere
- more common) */
- st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
-
- dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
-
- /* init 7090 tuner adapter */
- strncpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface", sizeof(st->dib7090_tuner_adap.name));
- st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
- st->dib7090_tuner_adap.algo_data = NULL;
- st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
- i2c_set_adapdata(&st->dib7090_tuner_adap, st);
- i2c_add_adapter(&st->dib7090_tuner_adap);
-
- dib7000p_demod_reset(st);
-
- if (st->version == SOC7090) {
- dib7090_set_output_mode(demod, st->cfg.output_mode);
- dib7090_set_diversity_in(demod, 0);
- }
-
- return demod;
-
-error:
- kfree(st);
- return NULL;
-}
-EXPORT_SYMBOL(dib7000p_attach);
-
-static struct dvb_frontend_ops dib7000p_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "DiBcom 7000PC",
- .frequency_min = 44250000,
- .frequency_max = 867250000,
- .frequency_stepsize = 62500,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
- },
-
- .release = dib7000p_release,
-
- .init = dib7000p_wakeup,
- .sleep = dib7000p_sleep,
-
- .set_frontend = dib7000p_set_frontend,
- .get_tune_settings = dib7000p_fe_get_tune_settings,
- .get_frontend = dib7000p_get_frontend,
-
- .read_status = dib7000p_read_status,
- .read_ber = dib7000p_read_ber,
- .read_signal_strength = dib7000p_read_signal_strength,
- .read_snr = dib7000p_read_snr,
- .read_ucblocks = dib7000p_read_unc_blocks,
-};
-
-MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
-MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
-MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib7000p.h b/drivers/media/dvb/frontends/dib7000p.h
deleted file mode 100644
index b61b03a6e1e..00000000000
--- a/drivers/media/dvb/frontends/dib7000p.h
+++ /dev/null
@@ -1,158 +0,0 @@
-#ifndef DIB7000P_H
-#define DIB7000P_H
-
-#include "dibx000_common.h"
-
-struct dib7000p_config {
- u8 output_mpeg2_in_188_bytes;
- u8 hostbus_diversity;
- u8 tuner_is_baseband;
- int (*update_lna) (struct dvb_frontend *, u16 agc_global);
-
- u8 agc_config_count;
- struct dibx000_agc_config *agc;
- struct dibx000_bandwidth_config *bw;
-
-#define DIB7000P_GPIO_DEFAULT_DIRECTIONS 0xffff
- u16 gpio_dir;
-#define DIB7000P_GPIO_DEFAULT_VALUES 0x0000
- u16 gpio_val;
-#define DIB7000P_GPIO_PWM_POS0(v) ((v & 0xf) << 12)
-#define DIB7000P_GPIO_PWM_POS1(v) ((v & 0xf) << 8 )
-#define DIB7000P_GPIO_PWM_POS2(v) ((v & 0xf) << 4 )
-#define DIB7000P_GPIO_PWM_POS3(v) (v & 0xf)
-#define DIB7000P_GPIO_DEFAULT_PWM_POS 0xffff
- u16 gpio_pwm_pos;
-
- u16 pwm_freq_div;
-
- u8 quartz_direct;
-
- u8 spur_protect;
-
- int (*agc_control) (struct dvb_frontend *, u8 before);
-
- u8 output_mode;
- u8 disable_sample_and_hold:1;
-
- u8 enable_current_mirror:1;
- u16 diversity_delay;
-
- u8 default_i2c_addr;
- u8 enMpegOutput:1;
-};
-
-#define DEFAULT_DIB7000P_I2C_ADDRESS 18
-
-#if defined(CONFIG_DVB_DIB7000P) || (defined(CONFIG_DVB_DIB7000P_MODULE) && \
- defined(MODULE))
-extern struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg);
-extern struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *, enum dibx000_i2c_interface, int);
-extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[]);
-extern int dib7000p_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
-extern int dib7000p_set_wbd_ref(struct dvb_frontend *, u16 value);
-extern int dib7000pc_detection(struct i2c_adapter *i2c_adap);
-extern int dib7000p_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
-extern int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
-extern int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw);
-extern u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf);
-extern int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff);
-extern int dib7090_get_adc_power(struct dvb_frontend *fe);
-extern struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe);
-extern int dib7090_slave_reset(struct dvb_frontend *fe);
-extern int dib7000p_get_agc_values(struct dvb_frontend *fe,
- u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd);
-#else
-static inline struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface i, int x)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib7000p_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib7000p_set_wbd_ref(struct dvb_frontend *fe, u16 value)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib7000pc_detection(struct i2c_adapter *i2c_adap)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, uint8_t onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return 0;
-}
-
-static inline int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib7090_get_adc_power(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline int dib7090_slave_reset(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib7000p_get_agc_values(struct dvb_frontend *fe,
- u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-#endif
-
-#endif
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c
deleted file mode 100644
index 1f3bcb5a1de..00000000000
--- a/drivers/media/dvb/frontends/dib8000.c
+++ /dev/null
@@ -1,3560 +0,0 @@
-/*
- * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
- *
- * Copyright (C) 2009 DiBcom (http://www.dibcom.fr/)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- */
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/i2c.h>
-#include <linux/mutex.h>
-
-#include "dvb_math.h"
-
-#include "dvb_frontend.h"
-
-#include "dib8000.h"
-
-#define LAYER_ALL -1
-#define LAYER_A 1
-#define LAYER_B 2
-#define LAYER_C 3
-
-#define FE_CALLBACK_TIME_NEVER 0xffffffff
-#define MAX_NUMBER_OF_FRONTENDS 6
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
-
-#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB8000: "); printk(args); printk("\n"); } } while (0)
-
-#define FE_STATUS_TUNE_FAILED 0
-
-struct i2c_device {
- struct i2c_adapter *adap;
- u8 addr;
- u8 *i2c_write_buffer;
- u8 *i2c_read_buffer;
- struct mutex *i2c_buffer_lock;
-};
-
-struct dib8000_state {
- struct dib8000_config cfg;
-
- struct i2c_device i2c;
-
- struct dibx000_i2c_master i2c_master;
-
- u16 wbd_ref;
-
- u8 current_band;
- u32 current_bandwidth;
- struct dibx000_agc_config *current_agc;
- u32 timf;
- u32 timf_default;
-
- u8 div_force_off:1;
- u8 div_state:1;
- u16 div_sync_wait;
-
- u8 agc_state;
- u8 differential_constellation;
- u8 diversity_onoff;
-
- s16 ber_monitored_layer;
- u16 gpio_dir;
- u16 gpio_val;
-
- u16 revision;
- u8 isdbt_cfg_loaded;
- enum frontend_tune_state tune_state;
- u32 status;
-
- struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
-
- /* for the I2C transfer */
- struct i2c_msg msg[2];
- u8 i2c_write_buffer[4];
- u8 i2c_read_buffer[2];
- struct mutex i2c_buffer_lock;
- u8 input_mode_mpeg;
-
- u16 tuner_enable;
- struct i2c_adapter dib8096p_tuner_adap;
-};
-
-enum dib8000_power_mode {
- DIB8000_POWER_ALL = 0,
- DIB8000_POWER_INTERFACE_ONLY,
-};
-
-static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
-{
- u16 ret;
- struct i2c_msg msg[2] = {
- {.addr = i2c->addr >> 1, .flags = 0, .len = 2},
- {.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2},
- };
-
- if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return 0;
- }
-
- msg[0].buf = i2c->i2c_write_buffer;
- msg[0].buf[0] = reg >> 8;
- msg[0].buf[1] = reg & 0xff;
- msg[1].buf = i2c->i2c_read_buffer;
-
- if (i2c_transfer(i2c->adap, msg, 2) != 2)
- dprintk("i2c read error on %d", reg);
-
- ret = (msg[1].buf[0] << 8) | msg[1].buf[1];
- mutex_unlock(i2c->i2c_buffer_lock);
- return ret;
-}
-
-static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
-{
- u16 ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return 0;
- }
-
- state->i2c_write_buffer[0] = reg >> 8;
- state->i2c_write_buffer[1] = reg & 0xff;
-
- memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
- state->msg[0].addr = state->i2c.addr >> 1;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 2;
- state->msg[1].addr = state->i2c.addr >> 1;
- state->msg[1].flags = I2C_M_RD;
- state->msg[1].buf = state->i2c_read_buffer;
- state->msg[1].len = 2;
-
- if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
- dprintk("i2c read error on %d", reg);
-
- ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
- mutex_unlock(&state->i2c_buffer_lock);
-
- return ret;
-}
-
-static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
-{
- u16 rw[2];
-
- rw[0] = dib8000_read_word(state, reg + 0);
- rw[1] = dib8000_read_word(state, reg + 1);
-
- return ((rw[0] << 16) | (rw[1]));
-}
-
-static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
-{
- struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4};
- int ret = 0;
-
- if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
-
- msg.buf = i2c->i2c_write_buffer;
- msg.buf[0] = (reg >> 8) & 0xff;
- msg.buf[1] = reg & 0xff;
- msg.buf[2] = (val >> 8) & 0xff;
- msg.buf[3] = val & 0xff;
-
- ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
- mutex_unlock(i2c->i2c_buffer_lock);
-
- return ret;
-}
-
-static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
-{
- int ret;
-
- if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
-
- state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
- state->i2c_write_buffer[1] = reg & 0xff;
- state->i2c_write_buffer[2] = (val >> 8) & 0xff;
- state->i2c_write_buffer[3] = val & 0xff;
-
- memset(&state->msg[0], 0, sizeof(struct i2c_msg));
- state->msg[0].addr = state->i2c.addr >> 1;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 4;
-
- ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?
- -EREMOTEIO : 0);
- mutex_unlock(&state->i2c_buffer_lock);
-
- return ret;
-}
-
-static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
- (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
- (920 << 5) | 0x09
-};
-
-static const s16 coeff_2k_sb_1seg[8] = {
- (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
-};
-
-static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
- (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
- (-931 << 5) | 0x0f
-};
-
-static const s16 coeff_2k_sb_3seg_0dqpsk[8] = {
- (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
- (982 << 5) | 0x0c
-};
-
-static const s16 coeff_2k_sb_3seg_1dqpsk[8] = {
- (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
- (-720 << 5) | 0x0d
-};
-
-static const s16 coeff_2k_sb_3seg[8] = {
- (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
- (-610 << 5) | 0x0a
-};
-
-static const s16 coeff_4k_sb_1seg_dqpsk[8] = {
- (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
- (-922 << 5) | 0x0d
-};
-
-static const s16 coeff_4k_sb_1seg[8] = {
- (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
- (-655 << 5) | 0x0a
-};
-
-static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
- (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
- (-958 << 5) | 0x13
-};
-
-static const s16 coeff_4k_sb_3seg_0dqpsk[8] = {
- (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
- (-568 << 5) | 0x0f
-};
-
-static const s16 coeff_4k_sb_3seg_1dqpsk[8] = {
- (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
- (-848 << 5) | 0x13
-};
-
-static const s16 coeff_4k_sb_3seg[8] = {
- (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
- (-869 << 5) | 0x13
-};
-
-static const s16 coeff_8k_sb_1seg_dqpsk[8] = {
- (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
- (-598 << 5) | 0x10
-};
-
-static const s16 coeff_8k_sb_1seg[8] = {
- (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
- (585 << 5) | 0x0f
-};
-
-static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
- (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
- (0 << 5) | 0x14
-};
-
-static const s16 coeff_8k_sb_3seg_0dqpsk[8] = {
- (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
- (-877 << 5) | 0x15
-};
-
-static const s16 coeff_8k_sb_3seg_1dqpsk[8] = {
- (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
- (-921 << 5) | 0x14
-};
-
-static const s16 coeff_8k_sb_3seg[8] = {
- (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
- (690 << 5) | 0x14
-};
-
-static const s16 ana_fe_coeff_3seg[24] = {
- 81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
-};
-
-static const s16 ana_fe_coeff_1seg[24] = {
- 249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
-};
-
-static const s16 ana_fe_coeff_13seg[24] = {
- 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
-};
-
-static u16 fft_to_mode(struct dib8000_state *state)
-{
- u16 mode;
- switch (state->fe[0]->dtv_property_cache.transmission_mode) {
- case TRANSMISSION_MODE_2K:
- mode = 1;
- break;
- case TRANSMISSION_MODE_4K:
- mode = 2;
- break;
- default:
- case TRANSMISSION_MODE_AUTO:
- case TRANSMISSION_MODE_8K:
- mode = 3;
- break;
- }
- return mode;
-}
-
-static void dib8000_set_acquisition_mode(struct dib8000_state *state)
-{
- u16 nud = dib8000_read_word(state, 298);
- nud |= (1 << 3) | (1 << 0);
- dprintk("acquisition mode activated");
- dib8000_write_word(state, 298, nud);
-}
-static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode)
-{
- struct dib8000_state *state = fe->demodulator_priv;
-
- u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */
-
- outreg = 0;
- fifo_threshold = 1792;
- smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
-
- dprintk("-I- Setting output mode for demod %p to %d",
- &state->fe[0], mode);
-
- switch (mode) {
- case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
- outreg = (1 << 10); /* 0x0400 */
- break;
- case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
- outreg = (1 << 10) | (1 << 6); /* 0x0440 */
- break;
- case OUTMODE_MPEG2_SERIAL: // STBs with serial input
- outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
- break;
- case OUTMODE_DIVERSITY:
- if (state->cfg.hostbus_diversity) {
- outreg = (1 << 10) | (4 << 6); /* 0x0500 */
- sram &= 0xfdff;
- } else
- sram |= 0x0c00;
- break;
- case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
- smo_mode |= (3 << 1);
- fifo_threshold = 512;
- outreg = (1 << 10) | (5 << 6);
- break;
- case OUTMODE_HIGH_Z: // disable
- outreg = 0;
- break;
-
- case OUTMODE_ANALOG_ADC:
- outreg = (1 << 10) | (3 << 6);
- dib8000_set_acquisition_mode(state);
- break;
-
- default:
- dprintk("Unhandled output_mode passed to be set for demod %p",
- &state->fe[0]);
- return -EINVAL;
- }
-
- if (state->cfg.output_mpeg2_in_188_bytes)
- smo_mode |= (1 << 5);
-
- dib8000_write_word(state, 299, smo_mode);
- dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */
- dib8000_write_word(state, 1286, outreg);
- dib8000_write_word(state, 1291, sram);
-
- return 0;
-}
-
-static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u16 sync_wait = dib8000_read_word(state, 273) & 0xfff0;
-
- if (!state->differential_constellation) {
- dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1
- dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2
- } else {
- dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0
- dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0
- }
- state->diversity_onoff = onoff;
-
- switch (onoff) {
- case 0: /* only use the internal way - not the diversity input */
- dib8000_write_word(state, 270, 1);
- dib8000_write_word(state, 271, 0);
- break;
- case 1: /* both ways */
- dib8000_write_word(state, 270, 6);
- dib8000_write_word(state, 271, 6);
- break;
- case 2: /* only the diversity input */
- dib8000_write_word(state, 270, 0);
- dib8000_write_word(state, 271, 1);
- break;
- }
- return 0;
-}
-
-static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)
-{
- /* by default everything is going to be powered off */
- u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
- reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
- reg_1280;
-
- if (state->revision != 0x8090)
- reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
- else
- reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
-
- /* now, depending on the requested mode, we power on */
- switch (mode) {
- /* power up everything in the demod */
- case DIB8000_POWER_ALL:
- reg_774 = 0x0000;
- reg_775 = 0x0000;
- reg_776 = 0x0000;
- reg_900 &= 0xfffc;
- if (state->revision != 0x8090)
- reg_1280 &= 0x00ff;
- else
- reg_1280 &= 0x707f;
- break;
- case DIB8000_POWER_INTERFACE_ONLY:
- if (state->revision != 0x8090)
- reg_1280 &= 0x00ff;
- else
- reg_1280 &= 0xfa7b;
- break;
- }
-
- dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x", reg_774, reg_775, reg_776, reg_900, reg_1280);
- dib8000_write_word(state, 774, reg_774);
- dib8000_write_word(state, 775, reg_775);
- dib8000_write_word(state, 776, reg_776);
- dib8000_write_word(state, 900, reg_900);
- dib8000_write_word(state, 1280, reg_1280);
-}
-
-static int dib8000_init_sdram(struct dib8000_state *state)
-{
- u16 reg = 0;
- dprintk("Init sdram");
-
- reg = dib8000_read_word(state, 274)&0xfff0;
- /* P_dintlv_delay_ram = 7 because of MobileSdram */
- dib8000_write_word(state, 274, reg | 0x7);
-
- dib8000_write_word(state, 1803, (7<<2));
-
- reg = dib8000_read_word(state, 1280);
- /* force restart P_restart_sdram */
- dib8000_write_word(state, 1280, reg | (1<<2));
-
- /* release restart P_restart_sdram */
- dib8000_write_word(state, 1280, reg);
-
- return 0;
-}
-
-static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
-{
- int ret = 0;
- u16 reg, reg_907 = dib8000_read_word(state, 907);
- u16 reg_908 = dib8000_read_word(state, 908);
-
- switch (no) {
- case DIBX000_SLOW_ADC_ON:
- if (state->revision != 0x8090) {
- reg_908 |= (1 << 1) | (1 << 0);
- ret |= dib8000_write_word(state, 908, reg_908);
- reg_908 &= ~(1 << 1);
- } else {
- reg = dib8000_read_word(state, 1925);
- /* en_slowAdc = 1 & reset_sladc = 1 */
- dib8000_write_word(state, 1925, reg |
- (1<<4) | (1<<2));
-
- /* read acces to make it works... strange ... */
- reg = dib8000_read_word(state, 1925);
- msleep(20);
- /* en_slowAdc = 1 & reset_sladc = 0 */
- dib8000_write_word(state, 1925, reg & ~(1<<4));
-
- reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
- | (0x3 << 12));
- /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ;
- (Vin2 = Vcm) */
- dib8000_write_word(state, 921, reg | (1 << 14)
- | (3 << 12));
- }
- break;
-
- case DIBX000_SLOW_ADC_OFF:
- if (state->revision == 0x8090) {
- reg = dib8000_read_word(state, 1925);
- /* reset_sladc = 1 en_slowAdc = 0 */
- dib8000_write_word(state, 1925,
- (reg & ~(1<<2)) | (1<<4));
- }
- reg_908 |= (1 << 1) | (1 << 0);
- break;
-
- case DIBX000_ADC_ON:
- reg_907 &= 0x0fff;
- reg_908 &= 0x0003;
- break;
-
- case DIBX000_ADC_OFF: // leave the VBG voltage on
- reg_907 |= (1 << 14) | (1 << 13) | (1 << 12);
- reg_908 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
- break;
-
- case DIBX000_VBG_ENABLE:
- reg_907 &= ~(1 << 15);
- break;
-
- case DIBX000_VBG_DISABLE:
- reg_907 |= (1 << 15);
- break;
-
- default:
- break;
- }
-
- ret |= dib8000_write_word(state, 907, reg_907);
- ret |= dib8000_write_word(state, 908, reg_908);
-
- return ret;
-}
-
-static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u32 timf;
-
- if (bw == 0)
- bw = 6000;
-
- if (state->timf == 0) {
- dprintk("using default timf");
- timf = state->timf_default;
- } else {
- dprintk("using updated timf");
- timf = state->timf;
- }
-
- dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));
- dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));
-
- return 0;
-}
-
-static int dib8000_sad_calib(struct dib8000_state *state)
-{
- if (state->revision == 0x8090) {
- dprintk("%s: the sad calibration is not needed for the dib8096P",
- __func__);
- return 0;
- }
- /* internal */
- dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
- dib8000_write_word(state, 924, 776); // 0.625*3.3 / 4096
-
- /* do the calibration */
- dib8000_write_word(state, 923, (1 << 0));
- dib8000_write_word(state, 923, (0 << 0));
-
- msleep(1);
- return 0;
-}
-
-int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- if (value > 4095)
- value = 4095;
- state->wbd_ref = value;
- return dib8000_write_word(state, 106, value);
-}
-
-EXPORT_SYMBOL(dib8000_set_wbd_ref);
-static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
-{
- dprintk("ifreq: %d %x, inversion: %d", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
- if (state->revision != 0x8090) {
- dib8000_write_word(state, 23,
- (u16) (((bw->internal * 1000) >> 16) & 0xffff));
- dib8000_write_word(state, 24,
- (u16) ((bw->internal * 1000) & 0xffff));
- } else {
- dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
- dib8000_write_word(state, 24,
- (u16) ((bw->internal / 2 * 1000) & 0xffff));
- }
- dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
- dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
- dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
-
- if (state->revision != 0x8090)
- dib8000_write_word(state, 922, bw->sad_cfg);
-}
-
-static void dib8000_reset_pll(struct dib8000_state *state)
-{
- const struct dibx000_bandwidth_config *pll = state->cfg.pll;
- u16 clk_cfg1, reg;
-
- if (state->revision != 0x8090) {
- dib8000_write_word(state, 901,
- (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
-
- clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
- (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
- (1 << 3) | (pll->pll_range << 1) |
- (pll->pll_reset << 0);
-
- dib8000_write_word(state, 902, clk_cfg1);
- clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
- dib8000_write_word(state, 902, clk_cfg1);
-
- dprintk("clk_cfg1: 0x%04x", clk_cfg1);
-
- /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
- if (state->cfg.pll->ADClkSrc == 0)
- dib8000_write_word(state, 904,
- (0 << 15) | (0 << 12) | (0 << 10) |
- (pll->modulo << 8) |
- (pll->ADClkSrc << 7) | (0 << 1));
- else if (state->cfg.refclksel != 0)
- dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
- ((state->cfg.refclksel & 0x3) << 10) |
- (pll->modulo << 8) |
- (pll->ADClkSrc << 7) | (0 << 1));
- else
- dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
- (3 << 10) | (pll->modulo << 8) |
- (pll->ADClkSrc << 7) | (0 << 1));
- } else {
- dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
- (pll->pll_range<<12) | (pll->pll_ratio<<6) |
- (pll->pll_prediv));
-
- reg = dib8000_read_word(state, 1857);
- dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
-
- reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
- dib8000_write_word(state, 1858, reg | 1);
-
- dib8000_write_word(state, 904, (pll->modulo << 8));
- }
-
- dib8000_reset_pll_common(state, pll);
-}
-
-int dib8000_update_pll(struct dvb_frontend *fe,
- struct dibx000_bandwidth_config *pll)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
- u8 loopdiv, prediv;
- u32 internal, xtal;
-
- /* get back old values */
- prediv = reg_1856 & 0x3f;
- loopdiv = (reg_1856 >> 6) & 0x3f;
-
- if ((pll != NULL) && (pll->pll_prediv != prediv ||
- pll->pll_ratio != loopdiv)) {
- dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
- reg_1856 &= 0xf000;
- reg_1857 = dib8000_read_word(state, 1857);
- /* disable PLL */
- dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));
-
- dib8000_write_word(state, 1856, reg_1856 |
- ((pll->pll_ratio & 0x3f) << 6) |
- (pll->pll_prediv & 0x3f));
-
- /* write new system clk into P_sec_len */
- internal = dib8000_read32(state, 23) / 1000;
- dprintk("Old Internal = %d", internal);
- xtal = 2 * (internal / loopdiv) * prediv;
- internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
- dprintk("Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d", xtal, internal/1000, internal/2000, internal/8000);
- dprintk("New Internal = %d", internal);
-
- dib8000_write_word(state, 23,
- (u16) (((internal / 2) >> 16) & 0xffff));
- dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));
- /* enable PLL */
- dib8000_write_word(state, 1857, reg_1857 | (1 << 15));
-
- while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
- dprintk("Waiting for PLL to lock");
-
- /* verify */
- reg_1856 = dib8000_read_word(state, 1856);
- dprintk("PLL Updated with prediv = %d and loopdiv = %d",
- reg_1856&0x3f, (reg_1856>>6)&0x3f);
-
- return 0;
- }
- return -EINVAL;
-}
-EXPORT_SYMBOL(dib8000_update_pll);
-
-
-static int dib8000_reset_gpio(struct dib8000_state *st)
-{
- /* reset the GPIOs */
- dib8000_write_word(st, 1029, st->cfg.gpio_dir);
- dib8000_write_word(st, 1030, st->cfg.gpio_val);
-
- /* TODO 782 is P_gpio_od */
-
- dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos);
-
- dib8000_write_word(st, 1037, st->cfg.pwm_freq_div);
- return 0;
-}
-
-static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val)
-{
- st->cfg.gpio_dir = dib8000_read_word(st, 1029);
- st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */
- st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */
- dib8000_write_word(st, 1029, st->cfg.gpio_dir);
-
- st->cfg.gpio_val = dib8000_read_word(st, 1030);
- st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */
- st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */
- dib8000_write_word(st, 1030, st->cfg.gpio_val);
-
- dprintk("gpio dir: %x: gpio val: %x", st->cfg.gpio_dir, st->cfg.gpio_val);
-
- return 0;
-}
-
-int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- return dib8000_cfg_gpio(state, num, dir, val);
-}
-
-EXPORT_SYMBOL(dib8000_set_gpio);
-static const u16 dib8000_defaults[] = {
- /* auto search configuration - lock0 by default waiting
- * for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */
- 3, 7,
- 0x0004,
- 0x0400,
- 0x0814,
-
- 12, 11,
- 0x001b,
- 0x7740,
- 0x005b,
- 0x8d80,
- 0x01c9,
- 0xc380,
- 0x0000,
- 0x0080,
- 0x0000,
- 0x0090,
- 0x0001,
- 0xd4c0,
-
- /*1, 32,
- 0x6680 // P_corm_thres Lock algorithms configuration */
-
- 11, 80, /* set ADC level to -16 */
- (1 << 13) - 825 - 117,
- (1 << 13) - 837 - 117,
- (1 << 13) - 811 - 117,
- (1 << 13) - 766 - 117,
- (1 << 13) - 737 - 117,
- (1 << 13) - 693 - 117,
- (1 << 13) - 648 - 117,
- (1 << 13) - 619 - 117,
- (1 << 13) - 575 - 117,
- (1 << 13) - 531 - 117,
- (1 << 13) - 501 - 117,
-
- 4, 108,
- 0,
- 0,
- 0,
- 0,
-
- 1, 175,
- 0x0410,
- 1, 179,
- 8192, // P_fft_nb_to_cut
-
- 6, 181,
- 0x2800, // P_coff_corthres_ ( 2k 4k 8k ) 0x2800
- 0x2800,
- 0x2800,
- 0x2800, // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800
- 0x2800,
- 0x2800,
-
- 2, 193,
- 0x0666, // P_pha3_thres
- 0x0000, // P_cti_use_cpe, P_cti_use_prog
-
- 2, 205,
- 0x200f, // P_cspu_regul, P_cspu_win_cut
- 0x000f, // P_des_shift_work
-
- 5, 215,
- 0x023d, // P_adp_regul_cnt
- 0x00a4, // P_adp_noise_cnt
- 0x00a4, // P_adp_regul_ext
- 0x7ff0, // P_adp_noise_ext
- 0x3ccc, // P_adp_fil
-
- 1, 230,
- 0x0000, // P_2d_byp_ti_num
-
- 1, 263,
- 0x800, //P_equal_thres_wgn
-
- 1, 268,
- (2 << 9) | 39, // P_equal_ctrl_synchro, P_equal_speedmode
-
- 1, 270,
- 0x0001, // P_div_lock0_wait
- 1, 285,
- 0x0020, //p_fec_
- 1, 299,
- 0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
-
- 1, 338,
- (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1
- (1 << 10) |
- (0 << 9) | /* P_ctrl_pre_freq_inh=0 */
- (3 << 5) | /* P_ctrl_pre_freq_step=3 */
- (1 << 0), /* P_pre_freq_win_len=1 */
-
- 0,
-};
-
-static u16 dib8000_identify(struct i2c_device *client)
-{
- u16 value;
-
- //because of glitches sometimes
- value = dib8000_i2c_read16(client, 896);
-
- if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) {
- dprintk("wrong Vendor ID (read=0x%x)", value);
- return 0;
- }
-
- value = dib8000_i2c_read16(client, 897);
- if (value != 0x8000 && value != 0x8001 &&
- value != 0x8002 && value != 0x8090) {
- dprintk("wrong Device ID (%x)", value);
- return 0;
- }
-
- switch (value) {
- case 0x8000:
- dprintk("found DiB8000A");
- break;
- case 0x8001:
- dprintk("found DiB8000B");
- break;
- case 0x8002:
- dprintk("found DiB8000C");
- break;
- case 0x8090:
- dprintk("found DiB8096P");
- break;
- }
- return value;
-}
-
-static int dib8000_reset(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
-
- if ((state->revision = dib8000_identify(&state->i2c)) == 0)
- return -EINVAL;
-
- /* sram lead in, rdy */
- if (state->revision != 0x8090)
- dib8000_write_word(state, 1287, 0x0003);
-
- if (state->revision == 0x8000)
- dprintk("error : dib8000 MA not supported");
-
- dibx000_reset_i2c_master(&state->i2c_master);
-
- dib8000_set_power_mode(state, DIB8000_POWER_ALL);
-
- /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
- dib8000_set_adc_state(state, DIBX000_VBG_ENABLE);
-
- /* restart all parts */
- dib8000_write_word(state, 770, 0xffff);
- dib8000_write_word(state, 771, 0xffff);
- dib8000_write_word(state, 772, 0xfffc);
- if (state->revision == 0x8090)
- dib8000_write_word(state, 1280, 0x0045);
- else
- dib8000_write_word(state, 1280, 0x004d);
- dib8000_write_word(state, 1281, 0x000c);
-
- dib8000_write_word(state, 770, 0x0000);
- dib8000_write_word(state, 771, 0x0000);
- dib8000_write_word(state, 772, 0x0000);
- dib8000_write_word(state, 898, 0x0004); // sad
- dib8000_write_word(state, 1280, 0x0000);
- dib8000_write_word(state, 1281, 0x0000);
-
- /* drives */
- if (state->revision != 0x8090) {
- if (state->cfg.drives)
- dib8000_write_word(state, 906, state->cfg.drives);
- else {
- dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.");
- /* min drive SDRAM - not optimal - adjust */
- dib8000_write_word(state, 906, 0x2d98);
- }
- }
-
- dib8000_reset_pll(state);
- if (state->revision != 0x8090)
- dib8000_write_word(state, 898, 0x0004);
-
- if (dib8000_reset_gpio(state) != 0)
- dprintk("GPIO reset was not successful.");
-
- if ((state->revision != 0x8090) &&
- (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0))
- dprintk("OUTPUT_MODE could not be resetted.");
-
- state->current_agc = NULL;
-
- // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
- /* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */
- if (state->cfg.pll->ifreq == 0)
- dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */
- else
- dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */
-
- {
- u16 l = 0, r;
- const u16 *n;
- n = dib8000_defaults;
- l = *n++;
- while (l) {
- r = *n++;
- do {
- dib8000_write_word(state, r, *n++);
- r++;
- } while (--l);
- l = *n++;
- }
- }
- if (state->revision != 0x8090)
- dib8000_write_word(state, 903, (0 << 4) | 2);
- state->isdbt_cfg_loaded = 0;
-
- //div_cfg override for special configs
- if (state->cfg.div_cfg != 0)
- dib8000_write_word(state, 903, state->cfg.div_cfg);
-
- /* unforce divstr regardless whether i2c enumeration was done or not */
- dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
-
- dib8000_set_bandwidth(fe, 6000);
-
- dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
- if (state->revision != 0x8090) {
- dib8000_sad_calib(state);
- dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
- }
-
- dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
-
- return 0;
-}
-
-static void dib8000_restart_agc(struct dib8000_state *state)
-{
- // P_restart_iqc & P_restart_agc
- dib8000_write_word(state, 770, 0x0a00);
- dib8000_write_word(state, 770, 0x0000);
-}
-
-static int dib8000_update_lna(struct dib8000_state *state)
-{
- u16 dyn_gain;
-
- if (state->cfg.update_lna) {
- // read dyn_gain here (because it is demod-dependent and not tuner)
- dyn_gain = dib8000_read_word(state, 390);
-
- if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
- dib8000_restart_agc(state);
- return 1;
- }
- }
- return 0;
-}
-
-static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
-{
- struct dibx000_agc_config *agc = NULL;
- int i;
- u16 reg;
-
- if (state->current_band == band && state->current_agc != NULL)
- return 0;
- state->current_band = band;
-
- for (i = 0; i < state->cfg.agc_config_count; i++)
- if (state->cfg.agc[i].band_caps & band) {
- agc = &state->cfg.agc[i];
- break;
- }
-
- if (agc == NULL) {
- dprintk("no valid AGC configuration found for band 0x%02x", band);
- return -EINVAL;
- }
-
- state->current_agc = agc;
-
- /* AGC */
- dib8000_write_word(state, 76, agc->setup);
- dib8000_write_word(state, 77, agc->inv_gain);
- dib8000_write_word(state, 78, agc->time_stabiliz);
- dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
-
- // Demod AGC loop configuration
- dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
- dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
-
- dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
- state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
-
- /* AGC continued */
- if (state->wbd_ref != 0)
- dib8000_write_word(state, 106, state->wbd_ref);
- else // use default
- dib8000_write_word(state, 106, agc->wbd_ref);
-
- if (state->revision == 0x8090) {
- reg = dib8000_read_word(state, 922) & (0x3 << 2);
- dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
- }
-
- dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
- dib8000_write_word(state, 108, agc->agc1_max);
- dib8000_write_word(state, 109, agc->agc1_min);
- dib8000_write_word(state, 110, agc->agc2_max);
- dib8000_write_word(state, 111, agc->agc2_min);
- dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
- dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
- dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
- dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
-
- dib8000_write_word(state, 75, agc->agc1_pt3);
- if (state->revision != 0x8090)
- dib8000_write_word(state, 923,
- (dib8000_read_word(state, 923) & 0xffe3) |
- (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
-
- return 0;
-}
-
-void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- dib8000_set_adc_state(state, DIBX000_ADC_ON);
- dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
-}
-EXPORT_SYMBOL(dib8000_pwm_agc_reset);
-
-static int dib8000_agc_soft_split(struct dib8000_state *state)
-{
- u16 agc, split_offset;
-
- if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
- return FE_CALLBACK_TIME_NEVER;
-
- // n_agc_global
- agc = dib8000_read_word(state, 390);
-
- if (agc > state->current_agc->split.min_thres)
- split_offset = state->current_agc->split.min;
- else if (agc < state->current_agc->split.max_thres)
- split_offset = state->current_agc->split.max;
- else
- split_offset = state->current_agc->split.max *
- (agc - state->current_agc->split.min_thres) /
- (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
-
- dprintk("AGC split_offset: %d", split_offset);
-
- // P_agc_force_split and P_agc_split_offset
- dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
- return 5000;
-}
-
-static int dib8000_agc_startup(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- enum frontend_tune_state *tune_state = &state->tune_state;
- int ret = 0;
- u16 reg, upd_demod_gain_period = 0x8000;
-
- switch (*tune_state) {
- case CT_AGC_START:
- // set power-up level: interf+analog+AGC
-
- if (state->revision != 0x8090)
- dib8000_set_adc_state(state, DIBX000_ADC_ON);
- else {
- dib8000_set_power_mode(state, DIB8000_POWER_ALL);
-
- reg = dib8000_read_word(state, 1947)&0xff00;
- dib8000_write_word(state, 1946,
- upd_demod_gain_period & 0xFFFF);
- /* bit 14 = enDemodGain */
- dib8000_write_word(state, 1947, reg | (1<<14) |
- ((upd_demod_gain_period >> 16) & 0xFF));
-
- /* enable adc i & q */
- reg = dib8000_read_word(state, 1920);
- dib8000_write_word(state, 1920, (reg | 0x3) &
- (~(1 << 7)));
- }
-
- if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
- *tune_state = CT_AGC_STOP;
- state->status = FE_STATUS_TUNE_FAILED;
- break;
- }
-
- ret = 70;
- *tune_state = CT_AGC_STEP_0;
- break;
-
- case CT_AGC_STEP_0:
- //AGC initialization
- if (state->cfg.agc_control)
- state->cfg.agc_control(fe, 1);
-
- dib8000_restart_agc(state);
-
- // wait AGC rough lock time
- ret = 50;
- *tune_state = CT_AGC_STEP_1;
- break;
-
- case CT_AGC_STEP_1:
- // wait AGC accurate lock time
- ret = 70;
-
- if (dib8000_update_lna(state))
- // wait only AGC rough lock time
- ret = 50;
- else
- *tune_state = CT_AGC_STEP_2;
- break;
-
- case CT_AGC_STEP_2:
- dib8000_agc_soft_split(state);
-
- if (state->cfg.agc_control)
- state->cfg.agc_control(fe, 0);
-
- *tune_state = CT_AGC_STOP;
- break;
- default:
- ret = dib8000_agc_soft_split(state);
- break;
- }
- return ret;
-
-}
-
-static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)
-{
- u16 reg;
-
- drive &= 0x7;
-
- /* drive host bus 2, 3, 4 */
- reg = dib8000_read_word(state, 1798) &
- ~(0x7 | (0x7 << 6) | (0x7 << 12));
- reg |= (drive<<12) | (drive<<6) | drive;
- dib8000_write_word(state, 1798, reg);
-
- /* drive host bus 5,6 */
- reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
- reg |= (drive<<8) | (drive<<2);
- dib8000_write_word(state, 1799, reg);
-
- /* drive host bus 7, 8, 9 */
- reg = dib8000_read_word(state, 1800) &
- ~(0x7 | (0x7 << 6) | (0x7 << 12));
- reg |= (drive<<12) | (drive<<6) | drive;
- dib8000_write_word(state, 1800, reg);
-
- /* drive host bus 10, 11 */
- reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
- reg |= (drive<<8) | (drive<<2);
- dib8000_write_word(state, 1801, reg);
-
- /* drive host bus 12, 13, 14 */
- reg = dib8000_read_word(state, 1802) &
- ~(0x7 | (0x7 << 6) | (0x7 << 12));
- reg |= (drive<<12) | (drive<<6) | drive;
- dib8000_write_word(state, 1802, reg);
-}
-
-static u32 dib8096p_calcSyncFreq(u32 P_Kin, u32 P_Kout,
- u32 insertExtSynchro, u32 syncSize)
-{
- u32 quantif = 3;
- u32 nom = (insertExtSynchro * P_Kin+syncSize);
- u32 denom = P_Kout;
- u32 syncFreq = ((nom << quantif) / denom);
-
- if ((syncFreq & ((1 << quantif) - 1)) != 0)
- syncFreq = (syncFreq >> quantif) + 1;
- else
- syncFreq = (syncFreq >> quantif);
-
- if (syncFreq != 0)
- syncFreq = syncFreq - 1;
-
- return syncFreq;
-}
-
-static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,
- u32 P_Kout, u32 insertExtSynchro, u32 synchroMode,
- u32 syncWord, u32 syncSize)
-{
- dprintk("Configure DibStream Tx");
-
- dib8000_write_word(state, 1615, 1);
- dib8000_write_word(state, 1603, P_Kin);
- dib8000_write_word(state, 1605, P_Kout);
- dib8000_write_word(state, 1606, insertExtSynchro);
- dib8000_write_word(state, 1608, synchroMode);
- dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);
- dib8000_write_word(state, 1610, syncWord & 0xffff);
- dib8000_write_word(state, 1612, syncSize);
- dib8000_write_word(state, 1615, 0);
-}
-
-static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,
- u32 P_Kout, u32 synchroMode, u32 insertExtSynchro,
- u32 syncWord, u32 syncSize, u32 dataOutRate)
-{
- u32 syncFreq;
-
- dprintk("Configure DibStream Rx synchroMode = %d", synchroMode);
-
- if ((P_Kin != 0) && (P_Kout != 0)) {
- syncFreq = dib8096p_calcSyncFreq(P_Kin, P_Kout,
- insertExtSynchro, syncSize);
- dib8000_write_word(state, 1542, syncFreq);
- }
-
- dib8000_write_word(state, 1554, 1);
- dib8000_write_word(state, 1536, P_Kin);
- dib8000_write_word(state, 1537, P_Kout);
- dib8000_write_word(state, 1539, synchroMode);
- dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);
- dib8000_write_word(state, 1541, syncWord & 0xffff);
- dib8000_write_word(state, 1543, syncSize);
- dib8000_write_word(state, 1544, dataOutRate);
- dib8000_write_word(state, 1554, 0);
-}
-
-static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)
-{
- u16 reg_1287;
-
- reg_1287 = dib8000_read_word(state, 1287);
-
- switch (onoff) {
- case 1:
- reg_1287 &= ~(1 << 8);
- break;
- case 0:
- reg_1287 |= (1 << 8);
- break;
- }
-
- dib8000_write_word(state, 1287, reg_1287);
-}
-
-static void dib8096p_configMpegMux(struct dib8000_state *state,
- u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
-{
- u16 reg_1287;
-
- dprintk("Enable Mpeg mux");
-
- dib8096p_enMpegMux(state, 0);
-
- /* If the input mode is MPEG do not divide the serial clock */
- if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
- enSerialClkDiv2 = 0;
-
- reg_1287 = ((pulseWidth & 0x1f) << 3) |
- ((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1);
- dib8000_write_word(state, 1287, reg_1287);
-
- dib8096p_enMpegMux(state, 1);
-}
-
-static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)
-{
- u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
-
- switch (mode) {
- case MPEG_ON_DIBTX:
- dprintk("SET MPEG ON DIBSTREAM TX");
- dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
- reg_1288 |= (1 << 9); break;
- case DIV_ON_DIBTX:
- dprintk("SET DIV_OUT ON DIBSTREAM TX");
- dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
- reg_1288 |= (1 << 8); break;
- case ADC_ON_DIBTX:
- dprintk("SET ADC_OUT ON DIBSTREAM TX");
- dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
- reg_1288 |= (1 << 7); break;
- default:
- break;
- }
- dib8000_write_word(state, 1288, reg_1288);
-}
-
-static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)
-{
- u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
-
- switch (mode) {
- case DEMOUT_ON_HOSTBUS:
- dprintk("SET DEM OUT OLD INTERF ON HOST BUS");
- dib8096p_enMpegMux(state, 0);
- reg_1288 |= (1 << 6);
- break;
- case DIBTX_ON_HOSTBUS:
- dprintk("SET DIBSTREAM TX ON HOST BUS");
- dib8096p_enMpegMux(state, 0);
- reg_1288 |= (1 << 5);
- break;
- case MPEG_ON_HOSTBUS:
- dprintk("SET MPEG MUX ON HOST BUS");
- reg_1288 |= (1 << 4);
- break;
- default:
- break;
- }
- dib8000_write_word(state, 1288, reg_1288);
-}
-
-static int dib8096p_set_diversity_in(struct dvb_frontend *fe, int onoff)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u16 reg_1287;
-
- switch (onoff) {
- case 0: /* only use the internal way - not the diversity input */
- dprintk("%s mode OFF : by default Enable Mpeg INPUT",
- __func__);
- /* outputRate = 8 */
- dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
-
- /* Do not divide the serial clock of MPEG MUX in
- SERIAL MODE in case input mode MPEG is used */
- reg_1287 = dib8000_read_word(state, 1287);
- /* enSerialClkDiv2 == 1 ? */
- if ((reg_1287 & 0x1) == 1) {
- /* force enSerialClkDiv2 = 0 */
- reg_1287 &= ~0x1;
- dib8000_write_word(state, 1287, reg_1287);
- }
- state->input_mode_mpeg = 1;
- break;
- case 1: /* both ways */
- case 2: /* only the diversity input */
- dprintk("%s ON : Enable diversity INPUT", __func__);
- dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
- state->input_mode_mpeg = 0;
- break;
- }
-
- dib8000_set_diversity_in(state->fe[0], onoff);
- return 0;
-}
-
-static int dib8096p_set_output_mode(struct dvb_frontend *fe, int mode)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u16 outreg, smo_mode, fifo_threshold;
- u8 prefer_mpeg_mux_use = 1;
- int ret = 0;
-
- dib8096p_host_bus_drive(state, 1);
-
- fifo_threshold = 1792;
- smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
- outreg = dib8000_read_word(state, 1286) &
- ~((1 << 10) | (0x7 << 6) | (1 << 1));
-
- switch (mode) {
- case OUTMODE_HIGH_Z:
- outreg = 0;
- break;
-
- case OUTMODE_MPEG2_SERIAL:
- if (prefer_mpeg_mux_use) {
- dprintk("dib8096P setting output mode TS_SERIAL using Mpeg Mux");
- dib8096p_configMpegMux(state, 3, 1, 1);
- dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
- } else {/* Use Smooth block */
- dprintk("dib8096P setting output mode TS_SERIAL using Smooth bloc");
- dib8096p_setHostBusMux(state,
- DEMOUT_ON_HOSTBUS);
- outreg |= (2 << 6) | (0 << 1);
- }
- break;
-
- case OUTMODE_MPEG2_PAR_GATED_CLK:
- if (prefer_mpeg_mux_use) {
- dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
- dib8096p_configMpegMux(state, 2, 0, 0);
- dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
- } else { /* Use Smooth block */
- dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Smooth block");
- dib8096p_setHostBusMux(state,
- DEMOUT_ON_HOSTBUS);
- outreg |= (0 << 6);
- }
- break;
-
- case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
- dprintk("dib8096P setting output mode TS_PARALLEL_CONT using Smooth block");
- dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
- outreg |= (1 << 6);
- break;
-
- case OUTMODE_MPEG2_FIFO:
- /* Using Smooth block because not supported
- by new Mpeg Mux bloc */
- dprintk("dib8096P setting output mode TS_FIFO using Smooth block");
- dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
- outreg |= (5 << 6);
- smo_mode |= (3 << 1);
- fifo_threshold = 512;
- break;
-
- case OUTMODE_DIVERSITY:
- dprintk("dib8096P setting output mode MODE_DIVERSITY");
- dib8096p_setDibTxMux(state, DIV_ON_DIBTX);
- dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
- break;
-
- case OUTMODE_ANALOG_ADC:
- dprintk("dib8096P setting output mode MODE_ANALOG_ADC");
- dib8096p_setDibTxMux(state, ADC_ON_DIBTX);
- dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
- break;
- }
-
- if (mode != OUTMODE_HIGH_Z)
- outreg |= (1<<10);
-
- dprintk("output_mpeg2_in_188_bytes = %d",
- state->cfg.output_mpeg2_in_188_bytes);
- if (state->cfg.output_mpeg2_in_188_bytes)
- smo_mode |= (1 << 5);
-
- ret |= dib8000_write_word(state, 299, smo_mode);
- /* synchronous fread */
- ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);
- ret |= dib8000_write_word(state, 1286, outreg);
-
- return ret;
-}
-
-static int map_addr_to_serpar_number(struct i2c_msg *msg)
-{
- if (msg->buf[0] <= 15)
- msg->buf[0] -= 1;
- else if (msg->buf[0] == 17)
- msg->buf[0] = 15;
- else if (msg->buf[0] == 16)
- msg->buf[0] = 17;
- else if (msg->buf[0] == 19)
- msg->buf[0] = 16;
- else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
- msg->buf[0] -= 3;
- else if (msg->buf[0] == 28)
- msg->buf[0] = 23;
- else if (msg->buf[0] == 99)
- msg->buf[0] = 99;
- else
- return -EINVAL;
- return 0;
-}
-
-static int dib8096p_tuner_write_serpar(struct i2c_adapter *i2c_adap,
- struct i2c_msg msg[], int num)
-{
- struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
- u8 n_overflow = 1;
- u16 i = 1000;
- u16 serpar_num = msg[0].buf[0];
-
- while (n_overflow == 1 && i) {
- n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
- i--;
- if (i == 0)
- dprintk("Tuner ITF: write busy (overflow)");
- }
- dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
- dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
-
- return num;
-}
-
-static int dib8096p_tuner_read_serpar(struct i2c_adapter *i2c_adap,
- struct i2c_msg msg[], int num)
-{
- struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
- u8 n_overflow = 1, n_empty = 1;
- u16 i = 1000;
- u16 serpar_num = msg[0].buf[0];
- u16 read_word;
-
- while (n_overflow == 1 && i) {
- n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
- i--;
- if (i == 0)
- dprintk("TunerITF: read busy (overflow)");
- }
- dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));
-
- i = 1000;
- while (n_empty == 1 && i) {
- n_empty = dib8000_read_word(state, 1984)&0x1;
- i--;
- if (i == 0)
- dprintk("TunerITF: read busy (empty)");
- }
-
- read_word = dib8000_read_word(state, 1987);
- msg[1].buf[0] = (read_word >> 8) & 0xff;
- msg[1].buf[1] = (read_word) & 0xff;
-
- return num;
-}
-
-static int dib8096p_tuner_rw_serpar(struct i2c_adapter *i2c_adap,
- struct i2c_msg msg[], int num)
-{
- if (map_addr_to_serpar_number(&msg[0]) == 0) {
- if (num == 1) /* write */
- return dib8096p_tuner_write_serpar(i2c_adap, msg, 1);
- else /* read */
- return dib8096p_tuner_read_serpar(i2c_adap, msg, 2);
- }
- return num;
-}
-
-static int dib8096p_rw_on_apb(struct i2c_adapter *i2c_adap,
- struct i2c_msg msg[], int num, u16 apb_address)
-{
- struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
- u16 word;
-
- if (num == 1) { /* write */
- dib8000_write_word(state, apb_address,
- ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
- } else {
- word = dib8000_read_word(state, apb_address);
- msg[1].buf[0] = (word >> 8) & 0xff;
- msg[1].buf[1] = (word) & 0xff;
- }
- return num;
-}
-
-static int dib8096p_tuner_xfer(struct i2c_adapter *i2c_adap,
- struct i2c_msg msg[], int num)
-{
- struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
- u16 apb_address = 0, word;
- int i = 0;
-
- switch (msg[0].buf[0]) {
- case 0x12:
- apb_address = 1920;
- break;
- case 0x14:
- apb_address = 1921;
- break;
- case 0x24:
- apb_address = 1922;
- break;
- case 0x1a:
- apb_address = 1923;
- break;
- case 0x22:
- apb_address = 1924;
- break;
- case 0x33:
- apb_address = 1926;
- break;
- case 0x34:
- apb_address = 1927;
- break;
- case 0x35:
- apb_address = 1928;
- break;
- case 0x36:
- apb_address = 1929;
- break;
- case 0x37:
- apb_address = 1930;
- break;
- case 0x38:
- apb_address = 1931;
- break;
- case 0x39:
- apb_address = 1932;
- break;
- case 0x2a:
- apb_address = 1935;
- break;
- case 0x2b:
- apb_address = 1936;
- break;
- case 0x2c:
- apb_address = 1937;
- break;
- case 0x2d:
- apb_address = 1938;
- break;
- case 0x2e:
- apb_address = 1939;
- break;
- case 0x2f:
- apb_address = 1940;
- break;
- case 0x30:
- apb_address = 1941;
- break;
- case 0x31:
- apb_address = 1942;
- break;
- case 0x32:
- apb_address = 1943;
- break;
- case 0x3e:
- apb_address = 1944;
- break;
- case 0x3f:
- apb_address = 1945;
- break;
- case 0x40:
- apb_address = 1948;
- break;
- case 0x25:
- apb_address = 936;
- break;
- case 0x26:
- apb_address = 937;
- break;
- case 0x27:
- apb_address = 938;
- break;
- case 0x28:
- apb_address = 939;
- break;
- case 0x1d:
- /* get sad sel request */
- i = ((dib8000_read_word(state, 921) >> 12)&0x3);
- word = dib8000_read_word(state, 924+i);
- msg[1].buf[0] = (word >> 8) & 0xff;
- msg[1].buf[1] = (word) & 0xff;
- return num;
- case 0x1f:
- if (num == 1) { /* write */
- word = (u16) ((msg[0].buf[1] << 8) |
- msg[0].buf[2]);
- /* in the VGAMODE Sel are located on bit 0/1 */
- word &= 0x3;
- word = (dib8000_read_word(state, 921) &
- ~(3<<12)) | (word<<12);
- /* Set the proper input */
- dib8000_write_word(state, 921, word);
- return num;
- }
- }
-
- if (apb_address != 0) /* R/W acces via APB */
- return dib8096p_rw_on_apb(i2c_adap, msg, num, apb_address);
- else /* R/W access via SERPAR */
- return dib8096p_tuner_rw_serpar(i2c_adap, msg, num);
-
- return 0;
-}
-
-static u32 dib8096p_i2c_func(struct i2c_adapter *adapter)
-{
- return I2C_FUNC_I2C;
-}
-
-static struct i2c_algorithm dib8096p_tuner_xfer_algo = {
- .master_xfer = dib8096p_tuner_xfer,
- .functionality = dib8096p_i2c_func,
-};
-
-struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
-{
- struct dib8000_state *st = fe->demodulator_priv;
- return &st->dib8096p_tuner_adap;
-}
-EXPORT_SYMBOL(dib8096p_get_i2c_tuner);
-
-int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u16 en_cur_state;
-
- dprintk("sleep dib8096p: %d", onoff);
-
- en_cur_state = dib8000_read_word(state, 1922);
-
- /* LNAs and MIX are ON and therefore it is a valid configuration */
- if (en_cur_state > 0xff)
- state->tuner_enable = en_cur_state ;
-
- if (onoff)
- en_cur_state &= 0x00ff;
- else {
- if (state->tuner_enable != 0)
- en_cur_state = state->tuner_enable;
- }
-
- dib8000_write_word(state, 1922, en_cur_state);
-
- return 0;
-}
-EXPORT_SYMBOL(dib8096p_tuner_sleep);
-
-static const s32 lut_1000ln_mant[] =
-{
- 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
-};
-
-s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u32 ix = 0, tmp_val = 0, exp = 0, mant = 0;
- s32 val;
-
- val = dib8000_read32(state, 384);
- if (mode) {
- tmp_val = val;
- while (tmp_val >>= 1)
- exp++;
- mant = (val * 1000 / (1<<exp));
- ix = (u8)((mant-1000)/100); /* index of the LUT */
- val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
- val = (val*256)/1000;
- }
- return val;
-}
-EXPORT_SYMBOL(dib8000_get_adc_power);
-
-int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- int val = 0;
-
- switch (IQ) {
- case 1:
- val = dib8000_read_word(state, 403);
- break;
- case 0:
- val = dib8000_read_word(state, 404);
- break;
- }
- if (val & 0x200)
- val -= 1024;
-
- return val;
-}
-EXPORT_SYMBOL(dib8090p_get_dc_power);
-
-static void dib8000_update_timf(struct dib8000_state *state)
-{
- u32 timf = state->timf = dib8000_read32(state, 435);
-
- dib8000_write_word(state, 29, (u16) (timf >> 16));
- dib8000_write_word(state, 30, (u16) (timf & 0xffff));
- dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default);
-}
-
-u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)
-{
- struct dib8000_state *state = fe->demodulator_priv;
-
- switch (op) {
- case DEMOD_TIMF_SET:
- state->timf = timf;
- break;
- case DEMOD_TIMF_UPDATE:
- dib8000_update_timf(state);
- break;
- case DEMOD_TIMF_GET:
- break;
- }
- dib8000_set_bandwidth(state->fe[0], 6000);
-
- return state->timf;
-}
-EXPORT_SYMBOL(dib8000_ctrl_timf);
-
-static const u16 adc_target_16dB[11] = {
- (1 << 13) - 825 - 117,
- (1 << 13) - 837 - 117,
- (1 << 13) - 811 - 117,
- (1 << 13) - 766 - 117,
- (1 << 13) - 737 - 117,
- (1 << 13) - 693 - 117,
- (1 << 13) - 648 - 117,
- (1 << 13) - 619 - 117,
- (1 << 13) - 575 - 117,
- (1 << 13) - 531 - 117,
- (1 << 13) - 501 - 117
-};
-static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
-
-static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
-{
- u16 mode, max_constellation, seg_diff_mask = 0, nbseg_diff = 0;
- u8 guard, crate, constellation, timeI;
- u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled
- const s16 *ncoeff = NULL, *ana_fe;
- u16 tmcc_pow = 0;
- u16 coff_pow = 0x2800;
- u16 init_prbs = 0xfff;
- u16 ana_gain = 0;
-
- if (state->revision == 0x8090)
- dib8000_init_sdram(state);
-
- if (state->ber_monitored_layer != LAYER_ALL)
- dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer);
- else
- dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
-
- i = dib8000_read_word(state, 26) & 1; // P_dds_invspec
- dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion^i);
-
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
- //compute new dds_freq for the seg and adjust prbs
- int seg_offset =
- state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx -
- (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) -
- (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2);
- int clk = state->cfg.pll->internal;
- u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26)
- int dds_offset = seg_offset * segtodds;
- int new_dds, sub_channel;
- if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
- dds_offset -= (int)(segtodds / 2);
-
- if (state->cfg.pll->ifreq == 0) {
- if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0) {
- dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
- new_dds = dds_offset;
- } else
- new_dds = dds_offset;
-
- // We shift tuning frequency if the wanted segment is :
- // - the segment of center frequency with an odd total number of segments
- // - the segment to the left of center frequency with an even total number of segments
- // - the segment to the right of center frequency with an even total number of segments
- if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT)
- && (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
- && (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
- && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
- ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
- || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
- && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2)))
- || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
- && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
- ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
- )) {
- new_dds -= ((u32) (850 << 22) / clk) << 4; // new_dds = 850 (freq shift in KHz) / Fclk * pow(2,26)
- }
- } else {
- if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0)
- new_dds = state->cfg.pll->ifreq - dds_offset;
- else
- new_dds = state->cfg.pll->ifreq + dds_offset;
- }
- dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff));
- dib8000_write_word(state, 28, (u16) (new_dds & 0xffff));
- if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
- sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3;
- else
- sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3;
- sub_channel -= 6;
-
- if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K
- || state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) {
- dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); //adp_pass =1
- dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); //pha3_force_pha_shift = 1
- } else {
- dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); //adp_pass =0
- dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); //pha3_force_pha_shift = 0
- }
-
- switch (state->fe[0]->dtv_property_cache.transmission_mode) {
- case TRANSMISSION_MODE_2K:
- switch (sub_channel) {
- case -6:
- init_prbs = 0x0;
- break; // 41, 0, 1
- case -5:
- init_prbs = 0x423;
- break; // 02~04
- case -4:
- init_prbs = 0x9;
- break; // 05~07
- case -3:
- init_prbs = 0x5C7;
- break; // 08~10
- case -2:
- init_prbs = 0x7A6;
- break; // 11~13
- case -1:
- init_prbs = 0x3D8;
- break; // 14~16
- case 0:
- init_prbs = 0x527;
- break; // 17~19
- case 1:
- init_prbs = 0x7FF;
- break; // 20~22
- case 2:
- init_prbs = 0x79B;
- break; // 23~25
- case 3:
- init_prbs = 0x3D6;
- break; // 26~28
- case 4:
- init_prbs = 0x3A2;
- break; // 29~31
- case 5:
- init_prbs = 0x53B;
- break; // 32~34
- case 6:
- init_prbs = 0x2F4;
- break; // 35~37
- default:
- case 7:
- init_prbs = 0x213;
- break; // 38~40
- }
- break;
-
- case TRANSMISSION_MODE_4K:
- switch (sub_channel) {
- case -6:
- init_prbs = 0x0;
- break; // 41, 0, 1
- case -5:
- init_prbs = 0x208;
- break; // 02~04
- case -4:
- init_prbs = 0xC3;
- break; // 05~07
- case -3:
- init_prbs = 0x7B9;
- break; // 08~10
- case -2:
- init_prbs = 0x423;
- break; // 11~13
- case -1:
- init_prbs = 0x5C7;
- break; // 14~16
- case 0:
- init_prbs = 0x3D8;
- break; // 17~19
- case 1:
- init_prbs = 0x7FF;
- break; // 20~22
- case 2:
- init_prbs = 0x3D6;
- break; // 23~25
- case 3:
- init_prbs = 0x53B;
- break; // 26~28
- case 4:
- init_prbs = 0x213;
- break; // 29~31
- case 5:
- init_prbs = 0x29;
- break; // 32~34
- case 6:
- init_prbs = 0xD0;
- break; // 35~37
- default:
- case 7:
- init_prbs = 0x48E;
- break; // 38~40
- }
- break;
-
- default:
- case TRANSMISSION_MODE_8K:
- switch (sub_channel) {
- case -6:
- init_prbs = 0x0;
- break; // 41, 0, 1
- case -5:
- init_prbs = 0x740;
- break; // 02~04
- case -4:
- init_prbs = 0x069;
- break; // 05~07
- case -3:
- init_prbs = 0x7DD;
- break; // 08~10
- case -2:
- init_prbs = 0x208;
- break; // 11~13
- case -1:
- init_prbs = 0x7B9;
- break; // 14~16
- case 0:
- init_prbs = 0x5C7;
- break; // 17~19
- case 1:
- init_prbs = 0x7FF;
- break; // 20~22
- case 2:
- init_prbs = 0x53B;
- break; // 23~25
- case 3:
- init_prbs = 0x29;
- break; // 26~28
- case 4:
- init_prbs = 0x48E;
- break; // 29~31
- case 5:
- init_prbs = 0x4C4;
- break; // 32~34
- case 6:
- init_prbs = 0x367;
- break; // 33~37
- default:
- case 7:
- init_prbs = 0x684;
- break; // 38~40
- }
- break;
- }
- } else {
- dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff));
- dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff));
- dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003));
- }
- /*P_mode == ?? */
- dib8000_write_word(state, 10, (seq << 4));
- // dib8000_write_word(state, 287, (dib8000_read_word(state, 287) & 0xe000) | 0x1000);
-
- switch (state->fe[0]->dtv_property_cache.guard_interval) {
- case GUARD_INTERVAL_1_32:
- guard = 0;
- break;
- case GUARD_INTERVAL_1_16:
- guard = 1;
- break;
- case GUARD_INTERVAL_1_8:
- guard = 2;
- break;
- case GUARD_INTERVAL_1_4:
- default:
- guard = 3;
- break;
- }
-
- dib8000_write_word(state, 1, (init_prbs << 2) | (guard & 0x3)); // ADDR 1
-
- max_constellation = DQPSK;
- for (i = 0; i < 3; i++) {
- switch (state->fe[0]->dtv_property_cache.layer[i].modulation) {
- case DQPSK:
- constellation = 0;
- break;
- case QPSK:
- constellation = 1;
- break;
- case QAM_16:
- constellation = 2;
- break;
- case QAM_64:
- default:
- constellation = 3;
- break;
- }
-
- switch (state->fe[0]->dtv_property_cache.layer[i].fec) {
- case FEC_1_2:
- crate = 1;
- break;
- case FEC_2_3:
- crate = 2;
- break;
- case FEC_3_4:
- crate = 3;
- break;
- case FEC_5_6:
- crate = 5;
- break;
- case FEC_7_8:
- default:
- crate = 7;
- break;
- }
-
- if ((state->fe[0]->dtv_property_cache.layer[i].interleaving > 0) &&
- ((state->fe[0]->dtv_property_cache.layer[i].interleaving <= 3) ||
- (state->fe[0]->dtv_property_cache.layer[i].interleaving == 4 && state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1))
- )
- timeI = state->fe[0]->dtv_property_cache.layer[i].interleaving;
- else
- timeI = 0;
- dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe[0]->dtv_property_cache.layer[i].segment_count & 0xf) << 6) |
- (crate << 3) | timeI);
- if (state->fe[0]->dtv_property_cache.layer[i].segment_count > 0) {
- switch (max_constellation) {
- case DQPSK:
- case QPSK:
- if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_16 ||
- state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
- max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
- break;
- case QAM_16:
- if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
- max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
- break;
- }
- }
- }
-
- mode = fft_to_mode(state);
-
- //dib8000_write_word(state, 5, 13); /*p_last_seg = 13*/
-
- dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) |
- ((state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe[0]->dtv_property_cache.
- isdbt_sb_mode & 1) << 4));
-
- dprintk("mode = %d ; guard = %d", mode, state->fe[0]->dtv_property_cache.guard_interval);
-
- /* signal optimization parameter */
-
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception) {
- seg_diff_mask = (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0];
- for (i = 1; i < 3; i++)
- nbseg_diff +=
- (state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
- for (i = 0; i < nbseg_diff; i++)
- seg_diff_mask |= 1 << permu_seg[i + 1];
- } else {
- for (i = 0; i < 3; i++)
- nbseg_diff +=
- (state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
- for (i = 0; i < nbseg_diff; i++)
- seg_diff_mask |= 1 << permu_seg[i];
- }
- dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask);
-
- state->differential_constellation = (seg_diff_mask != 0);
- if (state->revision != 0x8090)
- dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
- else
- dib8096p_set_diversity_in(state->fe[0], state->diversity_onoff);
-
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
- seg_mask13 = 0x00E0;
- else // 1-segment
- seg_mask13 = 0x0040;
- } else
- seg_mask13 = 0x1fff;
-
- // WRITE: Mode & Diff mask
- dib8000_write_word(state, 0, (mode << 13) | seg_diff_mask);
-
- if ((seg_diff_mask) || (state->fe[0]->dtv_property_cache.isdbt_sb_mode))
- dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
- else
- dib8000_write_word(state, 268, (2 << 9) | 39); //init value
-
- // ---- SMALL ----
- // P_small_seg_diff
- dib8000_write_word(state, 352, seg_diff_mask); // ADDR 352
-
- dib8000_write_word(state, 353, seg_mask13); // ADDR 353
-
-/* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */
-
- // ---- SMALL ----
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
- switch (state->fe[0]->dtv_property_cache.transmission_mode) {
- case TRANSMISSION_MODE_2K:
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
- if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
- ncoeff = coeff_2k_sb_1seg_dqpsk;
- else // QPSK or QAM
- ncoeff = coeff_2k_sb_1seg;
- } else { // 3-segments
- if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
- if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
- ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
- else // QPSK or QAM on external segments
- ncoeff = coeff_2k_sb_3seg_0dqpsk;
- } else { // QPSK or QAM on central segment
- if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
- ncoeff = coeff_2k_sb_3seg_1dqpsk;
- else // QPSK or QAM on external segments
- ncoeff = coeff_2k_sb_3seg;
- }
- }
- break;
-
- case TRANSMISSION_MODE_4K:
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
- if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
- ncoeff = coeff_4k_sb_1seg_dqpsk;
- else // QPSK or QAM
- ncoeff = coeff_4k_sb_1seg;
- } else { // 3-segments
- if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
- if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
- ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
- } else { // QPSK or QAM on external segments
- ncoeff = coeff_4k_sb_3seg_0dqpsk;
- }
- } else { // QPSK or QAM on central segment
- if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
- ncoeff = coeff_4k_sb_3seg_1dqpsk;
- } else // QPSK or QAM on external segments
- ncoeff = coeff_4k_sb_3seg;
- }
- }
- break;
-
- case TRANSMISSION_MODE_AUTO:
- case TRANSMISSION_MODE_8K:
- default:
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
- if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
- ncoeff = coeff_8k_sb_1seg_dqpsk;
- else // QPSK or QAM
- ncoeff = coeff_8k_sb_1seg;
- } else { // 3-segments
- if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
- if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
- ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
- } else { // QPSK or QAM on external segments
- ncoeff = coeff_8k_sb_3seg_0dqpsk;
- }
- } else { // QPSK or QAM on central segment
- if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
- ncoeff = coeff_8k_sb_3seg_1dqpsk;
- } else // QPSK or QAM on external segments
- ncoeff = coeff_8k_sb_3seg;
- }
- }
- break;
- }
- for (i = 0; i < 8; i++)
- dib8000_write_word(state, 343 + i, ncoeff[i]);
- }
-
- // P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5
- dib8000_write_word(state, 351,
- (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 9) | (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5);
-
- // ---- COFF ----
- // Carloff, the most robust
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
-
- // P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64
- // P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1
- dib8000_write_word(state, 187,
- (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 2)
- | 0x3);
-
-/* // P_small_coef_ext_enable = 1 */
-/* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */
-
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
-
- // P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1)
- if (mode == 3)
- dib8000_write_word(state, 180, 0x1fcf | ((mode - 1) << 14));
- else
- dib8000_write_word(state, 180, 0x0fcf | ((mode - 1) << 14));
- // P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1,
- // P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4
- dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);
- // P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8
- dib8000_write_word(state, 340, (16 << 6) | (8 << 0));
- // P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1
- dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
-
- // P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k
- dib8000_write_word(state, 181, 300);
- dib8000_write_word(state, 182, 150);
- dib8000_write_word(state, 183, 80);
- dib8000_write_word(state, 184, 300);
- dib8000_write_word(state, 185, 150);
- dib8000_write_word(state, 186, 80);
- } else { // Sound Broadcasting mode 3 seg
- // P_coff_one_seg_sym= 1, P_coff_one_seg_width= 1, P_coff_winlen=63, P_coff_thres_lock=15
- /* if (mode == 3) */
- /* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */
- /* else */
- /* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */
- dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
-
- // P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1,
- // P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4
- dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);
- // P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8
- dib8000_write_word(state, 340, (16 << 6) | (8 << 0));
- //P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1
- dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
-
- // P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k
- dib8000_write_word(state, 181, 350);
- dib8000_write_word(state, 182, 300);
- dib8000_write_word(state, 183, 250);
- dib8000_write_word(state, 184, 350);
- dib8000_write_word(state, 185, 300);
- dib8000_write_word(state, 186, 250);
- }
-
- } else if (state->isdbt_cfg_loaded == 0) { // if not Sound Broadcasting mode : put default values for 13 segments
- dib8000_write_word(state, 180, (16 << 6) | 9);
- dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);
- coff_pow = 0x2800;
- for (i = 0; i < 6; i++)
- dib8000_write_word(state, 181 + i, coff_pow);
-
- // P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1,
- // P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1
- dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);
-
- // P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6
- dib8000_write_word(state, 340, (8 << 6) | (6 << 0));
- // P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1
- dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
- }
- // ---- FFT ----
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
- dib8000_write_word(state, 178, 64); // P_fft_powrange=64
- else
- dib8000_write_word(state, 178, 32); // P_fft_powrange=32
-
- /* make the cpil_coff_lock more robust but slower p_coff_winlen
- * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
- */
- /* if ( ( nbseg_diff>0)&&(nbseg_diff<13))
- dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */
-
- dib8000_write_word(state, 189, ~seg_mask13 | seg_diff_mask); /* P_lmod4_seg_inh */
- dib8000_write_word(state, 192, ~seg_mask13 | seg_diff_mask); /* P_pha3_seg_inh */
- dib8000_write_word(state, 225, ~seg_mask13 | seg_diff_mask); /* P_tac_seg_inh */
- if ((!state->fe[0]->dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0))
- dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
- else
- dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask); /* P_equal_noise_seg_inh */
- dib8000_write_word(state, 287, ~seg_mask13 | 0x1000); /* P_tmcc_seg_inh */
- //dib8000_write_word(state, 288, ~seg_mask13 | seg_diff_mask); /* P_tmcc_seg_eq_inh */
- if (!autosearching)
- dib8000_write_word(state, 288, (~seg_mask13 | seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
- else
- dib8000_write_word(state, 288, 0x1fff); //disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels.
- dprintk("287 = %X (%d)", ~seg_mask13 | 0x1000, ~seg_mask13 | 0x1000);
-
- dib8000_write_word(state, 211, seg_mask13 & (~seg_diff_mask)); /* P_des_seg_enabled */
-
- /* offset loop parameters */
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
- /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
- dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40);
-
- else // Sound Broadcasting mode 3 seg
- /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
- dib8000_write_word(state, 32, ((10 - mode) << 12) | (6 << 8) | 0x60);
- } else
- // TODO in 13 seg, timf_alpha can always be the same or not ?
- /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
- dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80);
-
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
- /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */
- dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode));
-
- else // Sound Broadcasting mode 3 seg
- /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */
- dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (9 - mode));
- } else
- /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */
- dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (8 - mode));
-
- /* P_dvsy_sync_wait - reuse mode */
- switch (state->fe[0]->dtv_property_cache.transmission_mode) {
- case TRANSMISSION_MODE_8K:
- mode = 256;
- break;
- case TRANSMISSION_MODE_4K:
- mode = 128;
- break;
- default:
- case TRANSMISSION_MODE_2K:
- mode = 64;
- break;
- }
- if (state->cfg.diversity_delay == 0)
- mode = (mode * (1 << (guard)) * 3) / 2 + 48; // add 50% SFN margin + compensate for one DVSY-fifo
- else
- mode = (mode * (1 << (guard)) * 3) / 2 + state->cfg.diversity_delay; // add 50% SFN margin + compensate for DVSY-fifo
- mode <<= 4;
- dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | mode);
-
- /* channel estimation fine configuration */
- switch (max_constellation) {
- case QAM_64:
- ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB
- coeff[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
- coeff[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
- coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
- coeff[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
- //if (!state->cfg.hostbus_diversity) //if diversity, we should prehaps use the configuration of the max_constallation -1
- break;
- case QAM_16:
- ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB
- coeff[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
- coeff[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
- coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
- coeff[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
- //if (!((state->cfg.hostbus_diversity) && (max_constellation == QAM_16)))
- break;
- default:
- ana_gain = 0; // 0 : goes along with ADC target at -22dB to keep good mobile performance and lock at sensitivity level
- coeff[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
- coeff[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
- coeff[2] = 0x0333; /* P_adp_regul_ext 0.1 */
- coeff[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
- break;
- }
- for (mode = 0; mode < 4; mode++)
- dib8000_write_word(state, 215 + mode, coeff[mode]);
-
- // update ana_gain depending on max constellation
- dib8000_write_word(state, 116, ana_gain);
- // update ADC target depending on ana_gain
- if (ana_gain) { // set -16dB ADC target for ana_gain=-1
- for (i = 0; i < 10; i++)
- dib8000_write_word(state, 80 + i, adc_target_16dB[i]);
- } else { // set -22dB ADC target for ana_gain=0
- for (i = 0; i < 10; i++)
- dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
- }
-
- // ---- ANA_FE ----
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
- ana_fe = ana_fe_coeff_3seg;
- else // 1-segment
- ana_fe = ana_fe_coeff_1seg;
- } else
- ana_fe = ana_fe_coeff_13seg;
-
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0)
- for (mode = 0; mode < 24; mode++)
- dib8000_write_word(state, 117 + mode, ana_fe[mode]);
-
- // ---- CHAN_BLK ----
- for (i = 0; i < 13; i++) {
- if ((((~seg_diff_mask) >> i) & 1) == 1) {
- P_cfr_left_edge += (1 << i) * ((i == 0) || ((((seg_mask13 & (~seg_diff_mask)) >> (i - 1)) & 1) == 0));
- P_cfr_right_edge += (1 << i) * ((i == 12) || ((((seg_mask13 & (~seg_diff_mask)) >> (i + 1)) & 1) == 0));
- }
- }
- dib8000_write_word(state, 222, P_cfr_left_edge); // P_cfr_left_edge
- dib8000_write_word(state, 223, P_cfr_right_edge); // P_cfr_right_edge
- // "P_cspu_left_edge" not used => do not care
- // "P_cspu_right_edge" not used => do not care
-
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
- dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1
- dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0
- && state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) {
- //dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0
- dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15
- }
- } else if (state->isdbt_cfg_loaded == 0) {
- dib8000_write_word(state, 228, 0); // default value
- dib8000_write_word(state, 265, 31); // default value
- dib8000_write_word(state, 205, 0x200f); // init value
- }
- // ---- TMCC ----
- for (i = 0; i < 3; i++)
- tmcc_pow +=
- (((state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe[0]->dtv_property_cache.layer[i].segment_count);
- // Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9);
- // Threshold is set at 1/4 of max power.
- tmcc_pow *= (1 << (9 - 2));
-
- dib8000_write_word(state, 290, tmcc_pow); // P_tmcc_dec_thres_2k
- dib8000_write_word(state, 291, tmcc_pow); // P_tmcc_dec_thres_4k
- dib8000_write_word(state, 292, tmcc_pow); // P_tmcc_dec_thres_8k
- //dib8000_write_word(state, 287, (1 << 13) | 0x1000 );
- // ---- PHA3 ----
-
- if (state->isdbt_cfg_loaded == 0)
- dib8000_write_word(state, 250, 3285); /*p_2d_hspeed_thr0 */
-
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
- state->isdbt_cfg_loaded = 0;
- else
- state->isdbt_cfg_loaded = 1;
-
-}
-
-static int dib8000_autosearch_start(struct dvb_frontend *fe)
-{
- u8 factor;
- u32 value;
- struct dib8000_state *state = fe->demodulator_priv;
-
- int slist = 0;
-
- state->fe[0]->dtv_property_cache.inversion = 0;
- if (!state->fe[0]->dtv_property_cache.isdbt_sb_mode)
- state->fe[0]->dtv_property_cache.layer[0].segment_count = 13;
- state->fe[0]->dtv_property_cache.layer[0].modulation = QAM_64;
- state->fe[0]->dtv_property_cache.layer[0].fec = FEC_2_3;
- state->fe[0]->dtv_property_cache.layer[0].interleaving = 0;
-
- //choose the right list, in sb, always do everything
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
- state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
- state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
- slist = 7;
- dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
- } else {
- if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) {
- if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
- slist = 7;
- dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 to have autosearch start ok with mode2
- } else
- slist = 3;
- } else {
- if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
- slist = 2;
- dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
- } else
- slist = 0;
- }
-
- if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO)
- state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
- if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO)
- state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
-
- dprintk("using list for autosearch : %d", slist);
- dib8000_set_channel(state, (unsigned char)slist, 1);
- //dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
-
- factor = 1;
-
- //set lock_mask values
- dib8000_write_word(state, 6, 0x4);
- dib8000_write_word(state, 7, 0x8);
- dib8000_write_word(state, 8, 0x1000);
-
- //set lock_mask wait time values
- value = 50 * state->cfg.pll->internal * factor;
- dib8000_write_word(state, 11, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
- dib8000_write_word(state, 12, (u16) (value & 0xffff)); // lock0 wait time
- value = 100 * state->cfg.pll->internal * factor;
- dib8000_write_word(state, 13, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
- dib8000_write_word(state, 14, (u16) (value & 0xffff)); // lock1 wait time
- value = 1000 * state->cfg.pll->internal * factor;
- dib8000_write_word(state, 15, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
- dib8000_write_word(state, 16, (u16) (value & 0xffff)); // lock2 wait time
-
- value = dib8000_read_word(state, 0);
- dib8000_write_word(state, 0, (u16) ((1 << 15) | value));
- dib8000_read_word(state, 1284); // reset the INT. n_irq_pending
- dib8000_write_word(state, 0, (u16) value);
-
- }
-
- return 0;
-}
-
-static int dib8000_autosearch_irq(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u16 irq_pending = dib8000_read_word(state, 1284);
-
- if (irq_pending & 0x1) { // failed
- dprintk("dib8000_autosearch_irq failed");
- return 1;
- }
-
- if (irq_pending & 0x2) { // succeeded
- dprintk("dib8000_autosearch_irq succeeded");
- return 2;
- }
-
- return 0; // still pending
-}
-
-static int dib8000_tune(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- int ret = 0;
- u16 lock, value, mode;
-
- // we are already tuned - just resuming from suspend
- if (state == NULL)
- return -EINVAL;
-
- mode = fft_to_mode(state);
-
- dib8000_set_bandwidth(fe, state->fe[0]->dtv_property_cache.bandwidth_hz / 1000);
- dib8000_set_channel(state, 0, 0);
-
- // restart demod
- ret |= dib8000_write_word(state, 770, 0x4000);
- ret |= dib8000_write_word(state, 770, 0x0000);
- msleep(45);
-
- /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3 */
- /* ret |= dib8000_write_word(state, 29, (0 << 9) | (4 << 5) | (0 << 4) | (3 << 0) ); workaround inh_isi stays at 1 */
-
- // never achieved a lock before - wait for timfreq to update
- if (state->timf == 0) {
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
- msleep(300);
- else // Sound Broadcasting mode 3 seg
- msleep(500);
- } else // 13 seg
- msleep(200);
- }
- if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
- if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
-
- /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */
- dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40);
- //dib8000_write_word(state, 32, (8 << 12) | (6 << 8) | 0x80);
-
- /* P_ctrl_sfreq_step= (12-P_mode) P_ctrl_sfreq_inh =0 P_ctrl_pha_off_max */
- ret |= dib8000_write_word(state, 37, (12 - mode) | ((5 + mode) << 5));
-
- } else { // Sound Broadcasting mode 3 seg
-
- /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 alpha to check on board */
- dib8000_write_word(state, 32, ((12 - mode) << 12) | (6 << 8) | 0x60);
-
- ret |= dib8000_write_word(state, 37, (11 - mode) | ((5 + mode) << 5));
- }
-
- } else { // 13 seg
- /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 alpha to check on board */
- dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x80);
-
- ret |= dib8000_write_word(state, 37, (10 - mode) | ((5 + mode) << 5));
-
- }
-
- // we achieved a coff_cpil_lock - it's time to update the timf
- if (state->revision != 0x8090)
- lock = dib8000_read_word(state, 568);
- else
- lock = dib8000_read_word(state, 570);
- if ((lock >> 11) & 0x1)
- dib8000_update_timf(state);
-
- //now that tune is finished, lock0 should lock on fec_mpeg to output this lock on MP_LOCK. It's changed in autosearch start
- dib8000_write_word(state, 6, 0x200);
-
- if (state->revision == 0x8002) {
- value = dib8000_read_word(state, 903);
- dib8000_write_word(state, 903, value & ~(1 << 3));
- msleep(1);
- dib8000_write_word(state, 903, value | (1 << 3));
- }
-
- return ret;
-}
-
-static int dib8000_wakeup(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u8 index_frontend;
- int ret;
-
- dib8000_set_power_mode(state, DIB8000_POWER_ALL);
- dib8000_set_adc_state(state, DIBX000_ADC_ON);
- if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
- dprintk("could not start Slow ADC");
-
- if (state->revision != 0x8090)
- dib8000_sad_calib(state);
-
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
- if (ret < 0)
- return ret;
- }
-
- return 0;
-}
-
-static int dib8000_sleep(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u8 index_frontend;
- int ret;
-
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
- if (ret < 0)
- return ret;
- }
-
- if (state->revision != 0x8090)
- dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
- dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
- return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
-}
-
-enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- return state->tune_state;
-}
-EXPORT_SYMBOL(dib8000_get_tune_state);
-
-int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- state->tune_state = tune_state;
- return 0;
-}
-EXPORT_SYMBOL(dib8000_set_tune_state);
-
-static int dib8000_get_frontend(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u16 i, val = 0;
- fe_status_t stat;
- u8 index_frontend, sub_index_frontend;
-
- fe->dtv_property_cache.bandwidth_hz = 6000000;
-
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
- if (stat&FE_HAS_SYNC) {
- dprintk("TMCC lock on the slave%i", index_frontend);
- /* synchronize the cache with the other frontends */
- state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]);
- for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
- if (sub_index_frontend != index_frontend) {
- state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
- state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
- state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
- state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
- state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
- for (i = 0; i < 3; i++) {
- state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
- state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
- state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
- state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
- }
- }
- }
- return 0;
- }
- }
-
- fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
-
- if (state->revision == 0x8090)
- val = dib8000_read_word(state, 572);
- else
- val = dib8000_read_word(state, 570);
- fe->dtv_property_cache.inversion = (val & 0x40) >> 6;
- switch ((val & 0x30) >> 4) {
- case 1:
- fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
- break;
- case 3:
- default:
- fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
- break;
- }
-
- switch (val & 0x3) {
- case 0:
- fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
- dprintk("dib8000_get_frontend GI = 1/32 ");
- break;
- case 1:
- fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
- dprintk("dib8000_get_frontend GI = 1/16 ");
- break;
- case 2:
- dprintk("dib8000_get_frontend GI = 1/8 ");
- fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
- break;
- case 3:
- dprintk("dib8000_get_frontend GI = 1/4 ");
- fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
- break;
- }
-
- val = dib8000_read_word(state, 505);
- fe->dtv_property_cache.isdbt_partial_reception = val & 1;
- dprintk("dib8000_get_frontend : partial_reception = %d ", fe->dtv_property_cache.isdbt_partial_reception);
-
- for (i = 0; i < 3; i++) {
- val = dib8000_read_word(state, 493 + i);
- fe->dtv_property_cache.layer[i].segment_count = val & 0x0F;
- dprintk("dib8000_get_frontend : Layer %d segments = %d ", i, fe->dtv_property_cache.layer[i].segment_count);
-
- val = dib8000_read_word(state, 499 + i);
- fe->dtv_property_cache.layer[i].interleaving = val & 0x3;
- dprintk("dib8000_get_frontend : Layer %d time_intlv = %d ", i, fe->dtv_property_cache.layer[i].interleaving);
-
- val = dib8000_read_word(state, 481 + i);
- switch (val & 0x7) {
- case 1:
- fe->dtv_property_cache.layer[i].fec = FEC_1_2;
- dprintk("dib8000_get_frontend : Layer %d Code Rate = 1/2 ", i);
- break;
- case 2:
- fe->dtv_property_cache.layer[i].fec = FEC_2_3;
- dprintk("dib8000_get_frontend : Layer %d Code Rate = 2/3 ", i);
- break;
- case 3:
- fe->dtv_property_cache.layer[i].fec = FEC_3_4;
- dprintk("dib8000_get_frontend : Layer %d Code Rate = 3/4 ", i);
- break;
- case 5:
- fe->dtv_property_cache.layer[i].fec = FEC_5_6;
- dprintk("dib8000_get_frontend : Layer %d Code Rate = 5/6 ", i);
- break;
- default:
- fe->dtv_property_cache.layer[i].fec = FEC_7_8;
- dprintk("dib8000_get_frontend : Layer %d Code Rate = 7/8 ", i);
- break;
- }
-
- val = dib8000_read_word(state, 487 + i);
- switch (val & 0x3) {
- case 0:
- dprintk("dib8000_get_frontend : Layer %d DQPSK ", i);
- fe->dtv_property_cache.layer[i].modulation = DQPSK;
- break;
- case 1:
- fe->dtv_property_cache.layer[i].modulation = QPSK;
- dprintk("dib8000_get_frontend : Layer %d QPSK ", i);
- break;
- case 2:
- fe->dtv_property_cache.layer[i].modulation = QAM_16;
- dprintk("dib8000_get_frontend : Layer %d QAM16 ", i);
- break;
- case 3:
- default:
- dprintk("dib8000_get_frontend : Layer %d QAM64 ", i);
- fe->dtv_property_cache.layer[i].modulation = QAM_64;
- break;
- }
- }
-
- /* synchronize the cache with the other frontends */
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode;
- state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
- state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
- state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
- state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isdbt_partial_reception;
- for (i = 0; i < 3; i++) {
- state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.layer[i].segment_count;
- state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer[i].interleaving;
- state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec;
- state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i].modulation;
- }
- }
- return 0;
-}
-
-static int dib8000_set_frontend(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u8 nbr_pending, exit_condition, index_frontend;
- s8 index_frontend_success = -1;
- int time, ret;
- int time_slave = FE_CALLBACK_TIME_NEVER;
-
- if (state->fe[0]->dtv_property_cache.frequency == 0) {
- dprintk("dib8000: must at least specify frequency ");
- return 0;
- }
-
- if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
- dprintk("dib8000: no bandwidth specified, set to default ");
- state->fe[0]->dtv_property_cache.bandwidth_hz = 6000000;
- }
-
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- /* synchronization of the cache */
- state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
- memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
-
- if (state->revision != 0x8090)
- dib8000_set_output_mode(state->fe[index_frontend],
- OUTMODE_HIGH_Z);
- else
- dib8096p_set_output_mode(state->fe[index_frontend],
- OUTMODE_HIGH_Z);
- if (state->fe[index_frontend]->ops.tuner_ops.set_params)
- state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
-
- dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
- }
-
- /* start up the AGC */
- do {
- time = dib8000_agc_startup(state->fe[0]);
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- time_slave = dib8000_agc_startup(state->fe[index_frontend]);
- if (time == FE_CALLBACK_TIME_NEVER)
- time = time_slave;
- else if ((time_slave != FE_CALLBACK_TIME_NEVER) && (time_slave > time))
- time = time_slave;
- }
- if (time != FE_CALLBACK_TIME_NEVER)
- msleep(time / 10);
- else
- break;
- exit_condition = 1;
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
- exit_condition = 0;
- break;
- }
- }
- } while (exit_condition == 0);
-
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
- dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
-
- if ((state->fe[0]->dtv_property_cache.delivery_system != SYS_ISDBT) ||
- (state->fe[0]->dtv_property_cache.inversion == INVERSION_AUTO) ||
- (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) ||
- (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) ||
- (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) &&
- (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0xff) &&
- (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0) &&
- ((state->fe[0]->dtv_property_cache.layer[0].modulation == QAM_AUTO) ||
- (state->fe[0]->dtv_property_cache.layer[0].fec == FEC_AUTO))) ||
- (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) &&
- (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0xff) &&
- (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0) &&
- ((state->fe[0]->dtv_property_cache.layer[1].modulation == QAM_AUTO) ||
- (state->fe[0]->dtv_property_cache.layer[1].fec == FEC_AUTO))) ||
- (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) &&
- (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0xff) &&
- (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0) &&
- ((state->fe[0]->dtv_property_cache.layer[2].modulation == QAM_AUTO) ||
- (state->fe[0]->dtv_property_cache.layer[2].fec == FEC_AUTO))) ||
- (((state->fe[0]->dtv_property_cache.layer[0].segment_count == 0) ||
- ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) &&
- ((state->fe[0]->dtv_property_cache.layer[1].segment_count == 0) ||
- ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) &&
- ((state->fe[0]->dtv_property_cache.layer[2].segment_count == 0) || ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) {
- int i = 100;
- u8 found = 0;
- u8 tune_failed = 0;
-
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- dib8000_set_bandwidth(state->fe[index_frontend], fe->dtv_property_cache.bandwidth_hz / 1000);
- dib8000_autosearch_start(state->fe[index_frontend]);
- }
-
- do {
- msleep(20);
- nbr_pending = 0;
- exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- if (((tune_failed >> index_frontend) & 0x1) == 0) {
- found = dib8000_autosearch_irq(state->fe[index_frontend]);
- switch (found) {
- case 0: /* tune pending */
- nbr_pending++;
- break;
- case 2:
- dprintk("autosearch succeed on the frontend%i", index_frontend);
- exit_condition = 2;
- index_frontend_success = index_frontend;
- break;
- default:
- dprintk("unhandled autosearch result");
- case 1:
- tune_failed |= (1 << index_frontend);
- dprintk("autosearch failed for the frontend%i", index_frontend);
- break;
- }
- }
- }
-
- /* if all tune are done and no success, exit: tune failed */
- if ((nbr_pending == 0) && (exit_condition == 0))
- exit_condition = 1;
- } while ((exit_condition == 0) && i--);
-
- if (exit_condition == 1) { /* tune failed */
- dprintk("tune failed");
- return 0;
- }
-
- dprintk("tune success on frontend%i", index_frontend_success);
-
- dib8000_get_frontend(fe);
- }
-
- for (index_frontend = 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
- ret = dib8000_tune(state->fe[index_frontend]);
-
- /* set output mode and diversity input */
- if (state->revision != 0x8090) {
- dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
- for (index_frontend = 1;
- (index_frontend < MAX_NUMBER_OF_FRONTENDS) &&
- (state->fe[index_frontend] != NULL);
- index_frontend++) {
- dib8000_set_output_mode(state->fe[index_frontend],
- OUTMODE_DIVERSITY);
- dib8000_set_diversity_in(state->fe[index_frontend-1], 1);
- }
-
- /* turn off the diversity of the last chip */
- dib8000_set_diversity_in(state->fe[index_frontend-1], 0);
- } else {
- dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
- if (state->cfg.enMpegOutput == 0) {
- dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);
- dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
- }
- for (index_frontend = 1;
- (index_frontend < MAX_NUMBER_OF_FRONTENDS) &&
- (state->fe[index_frontend] != NULL);
- index_frontend++) {
- dib8096p_set_output_mode(state->fe[index_frontend],
- OUTMODE_DIVERSITY);
- dib8096p_set_diversity_in(state->fe[index_frontend-1], 1);
- }
-
- /* turn off the diversity of the last chip */
- dib8096p_set_diversity_in(state->fe[index_frontend-1], 0);
- }
-
- return ret;
-}
-
-static u16 dib8000_read_lock(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
-
- if (state->revision == 0x8090)
- return dib8000_read_word(state, 570);
- return dib8000_read_word(state, 568);
-}
-
-static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u16 lock_slave = 0, lock;
- u8 index_frontend;
-
- if (state->revision == 0x8090)
- lock = dib8000_read_word(state, 570);
- else
- lock = dib8000_read_word(state, 568);
-
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
- lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
-
- *stat = 0;
-
- if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1))
- *stat |= FE_HAS_SIGNAL;
-
- if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */
- *stat |= FE_HAS_CARRIER;
-
- if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */
- *stat |= FE_HAS_SYNC;
-
- if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */
- *stat |= FE_HAS_LOCK;
-
- if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) {
- lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
- if (lock & 0x01)
- *stat |= FE_HAS_VITERBI;
-
- lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
- if (lock & 0x01)
- *stat |= FE_HAS_VITERBI;
-
- lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
- if (lock & 0x01)
- *stat |= FE_HAS_VITERBI;
- }
-
- return 0;
-}
-
-static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber)
-{
- struct dib8000_state *state = fe->demodulator_priv;
-
- /* 13 segments */
- if (state->revision == 0x8090)
- *ber = (dib8000_read_word(state, 562) << 16) |
- dib8000_read_word(state, 563);
- else
- *ber = (dib8000_read_word(state, 560) << 16) |
- dib8000_read_word(state, 561);
- return 0;
-}
-
-static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
-{
- struct dib8000_state *state = fe->demodulator_priv;
-
- /* packet error on 13 seg */
- if (state->revision == 0x8090)
- *unc = dib8000_read_word(state, 567);
- else
- *unc = dib8000_read_word(state, 565);
- return 0;
-}
-
-static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u8 index_frontend;
- u16 val;
-
- *strength = 0;
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
- if (val > 65535 - *strength)
- *strength = 65535;
- else
- *strength += val;
- }
-
- val = 65535 - dib8000_read_word(state, 390);
- if (val > 65535 - *strength)
- *strength = 65535;
- else
- *strength += val;
- return 0;
-}
-
-static u32 dib8000_get_snr(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u32 n, s, exp;
- u16 val;
-
- if (state->revision != 0x8090)
- val = dib8000_read_word(state, 542);
- else
- val = dib8000_read_word(state, 544);
- n = (val >> 6) & 0xff;
- exp = (val & 0x3f);
- if ((exp & 0x20) != 0)
- exp -= 0x40;
- n <<= exp+16;
-
- if (state->revision != 0x8090)
- val = dib8000_read_word(state, 543);
- else
- val = dib8000_read_word(state, 545);
- s = (val >> 6) & 0xff;
- exp = (val & 0x3f);
- if ((exp & 0x20) != 0)
- exp -= 0x40;
- s <<= exp+16;
-
- if (n > 0) {
- u32 t = (s/n) << 16;
- return t + ((s << 16) - n*t) / n;
- }
- return 0xffffffff;
-}
-
-static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u8 index_frontend;
- u32 snr_master;
-
- snr_master = dib8000_get_snr(fe);
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
- snr_master += dib8000_get_snr(state->fe[index_frontend]);
-
- if ((snr_master >> 16) != 0) {
- snr_master = 10*intlog10(snr_master>>16);
- *snr = snr_master / ((1 << 24) / 10);
- }
- else
- *snr = 0;
-
- return 0;
-}
-
-int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u8 index_frontend = 1;
-
- while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
- index_frontend++;
- if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
- dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
- state->fe[index_frontend] = fe_slave;
- return 0;
- }
-
- dprintk("too many slave frontend");
- return -ENOMEM;
-}
-EXPORT_SYMBOL(dib8000_set_slave_frontend);
-
-int dib8000_remove_slave_frontend(struct dvb_frontend *fe)
-{
- struct dib8000_state *state = fe->demodulator_priv;
- u8 index_frontend = 1;
-
- while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
- index_frontend++;
- if (index_frontend != 1) {
- dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1);
- state->fe[index_frontend] = NULL;
- return 0;
- }
-
- dprintk("no frontend to be removed");
- return -ENODEV;
-}
-EXPORT_SYMBOL(dib8000_remove_slave_frontend);
-
-struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
-{
- struct dib8000_state *state = fe->demodulator_priv;
-
- if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
- return NULL;
- return state->fe[slave_index];
-}
-EXPORT_SYMBOL(dib8000_get_slave_frontend);
-
-
-int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
- u8 default_addr, u8 first_addr, u8 is_dib8096p)
-{
- int k = 0, ret = 0;
- u8 new_addr = 0;
- struct i2c_device client = {.adap = host };
-
- client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
- if (!client.i2c_write_buffer) {
- dprintk("%s: not enough memory", __func__);
- return -ENOMEM;
- }
- client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
- if (!client.i2c_read_buffer) {
- dprintk("%s: not enough memory", __func__);
- ret = -ENOMEM;
- goto error_memory_read;
- }
- client.i2c_buffer_lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
- if (!client.i2c_buffer_lock) {
- dprintk("%s: not enough memory", __func__);
- ret = -ENOMEM;
- goto error_memory_lock;
- }
- mutex_init(client.i2c_buffer_lock);
-
- for (k = no_of_demods - 1; k >= 0; k--) {
- /* designated i2c address */
- new_addr = first_addr + (k << 1);
-
- client.addr = new_addr;
- if (!is_dib8096p)
- dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */
- if (dib8000_identify(&client) == 0) {
- /* sram lead in, rdy */
- if (!is_dib8096p)
- dib8000_i2c_write16(&client, 1287, 0x0003);
- client.addr = default_addr;
- if (dib8000_identify(&client) == 0) {
- dprintk("#%d: not identified", k);
- ret = -EINVAL;
- goto error;
- }
- }
-
- /* start diversity to pull_down div_str - just for i2c-enumeration */
- dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6));
-
- /* set new i2c address and force divstart */
- dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2);
- client.addr = new_addr;
- dib8000_identify(&client);
-
- dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
- }
-
- for (k = 0; k < no_of_demods; k++) {
- new_addr = first_addr | (k << 1);
- client.addr = new_addr;
-
- // unforce divstr
- dib8000_i2c_write16(&client, 1285, new_addr << 2);
-
- /* deactivate div - it was just for i2c-enumeration */
- dib8000_i2c_write16(&client, 1286, 0);
- }
-
-error:
- kfree(client.i2c_buffer_lock);
-error_memory_lock:
- kfree(client.i2c_read_buffer);
-error_memory_read:
- kfree(client.i2c_write_buffer);
-
- return ret;
-}
-
-EXPORT_SYMBOL(dib8000_i2c_enumeration);
-static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
-{
- tune->min_delay_ms = 1000;
- tune->step_size = 0;
- tune->max_drift = 0;
- return 0;
-}
-
-static void dib8000_release(struct dvb_frontend *fe)
-{
- struct dib8000_state *st = fe->demodulator_priv;
- u8 index_frontend;
-
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
- dvb_frontend_detach(st->fe[index_frontend]);
-
- dibx000_exit_i2c_master(&st->i2c_master);
- i2c_del_adapter(&st->dib8096p_tuner_adap);
- kfree(st->fe[0]);
- kfree(st);
-}
-
-struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
-{
- struct dib8000_state *st = fe->demodulator_priv;
- return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
-}
-
-EXPORT_SYMBOL(dib8000_get_i2c_master);
-
-int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
-{
- struct dib8000_state *st = fe->demodulator_priv;
- u16 val = dib8000_read_word(st, 299) & 0xffef;
- val |= (onoff & 0x1) << 4;
-
- dprintk("pid filter enabled %d", onoff);
- return dib8000_write_word(st, 299, val);
-}
-EXPORT_SYMBOL(dib8000_pid_filter_ctrl);
-
-int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
-{
- struct dib8000_state *st = fe->demodulator_priv;
- dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
- return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
-}
-EXPORT_SYMBOL(dib8000_pid_filter);
-
-static const struct dvb_frontend_ops dib8000_ops = {
- .delsys = { SYS_ISDBT },
- .info = {
- .name = "DiBcom 8000 ISDB-T",
- .frequency_min = 44250000,
- .frequency_max = 867250000,
- .frequency_stepsize = 62500,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
- },
-
- .release = dib8000_release,
-
- .init = dib8000_wakeup,
- .sleep = dib8000_sleep,
-
- .set_frontend = dib8000_set_frontend,
- .get_tune_settings = dib8000_fe_get_tune_settings,
- .get_frontend = dib8000_get_frontend,
-
- .read_status = dib8000_read_status,
- .read_ber = dib8000_read_ber,
- .read_signal_strength = dib8000_read_signal_strength,
- .read_snr = dib8000_read_snr,
- .read_ucblocks = dib8000_read_unc_blocks,
-};
-
-struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
-{
- struct dvb_frontend *fe;
- struct dib8000_state *state;
-
- dprintk("dib8000_attach");
-
- state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
- if (state == NULL)
- return NULL;
- fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
- if (fe == NULL)
- goto error;
-
- memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
- state->i2c.adap = i2c_adap;
- state->i2c.addr = i2c_addr;
- state->i2c.i2c_write_buffer = state->i2c_write_buffer;
- state->i2c.i2c_read_buffer = state->i2c_read_buffer;
- mutex_init(&state->i2c_buffer_lock);
- state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;
- state->gpio_val = cfg->gpio_val;
- state->gpio_dir = cfg->gpio_dir;
-
- /* Ensure the output mode remains at the previous default if it's
- * not specifically set by the caller.
- */
- if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
- state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
-
- state->fe[0] = fe;
- fe->demodulator_priv = state;
- memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
-
- state->timf_default = cfg->pll->timf;
-
- if (dib8000_identify(&state->i2c) == 0)
- goto error;
-
- dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
-
- /* init 8096p tuner adapter */
- strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
- sizeof(state->dib8096p_tuner_adap.name));
- state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
- state->dib8096p_tuner_adap.algo_data = NULL;
- state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
- i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
- i2c_add_adapter(&state->dib8096p_tuner_adap);
-
- dib8000_reset(fe);
-
- dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */
-
- return fe;
-
- error:
- kfree(state);
- return NULL;
-}
-
-EXPORT_SYMBOL(dib8000_attach);
-
-MODULE_AUTHOR("Olivier Grenie <Olivier.Grenie@dibcom.fr, " "Patrick Boettcher <pboettcher@dibcom.fr>");
-MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib8000.h b/drivers/media/dvb/frontends/dib8000.h
deleted file mode 100644
index 39591bb172c..00000000000
--- a/drivers/media/dvb/frontends/dib8000.h
+++ /dev/null
@@ -1,174 +0,0 @@
-#ifndef DIB8000_H
-#define DIB8000_H
-
-#include "dibx000_common.h"
-
-struct dib8000_config {
- u8 output_mpeg2_in_188_bytes;
- u8 hostbus_diversity;
- u8 tuner_is_baseband;
- int (*update_lna) (struct dvb_frontend *, u16 agc_global);
-
- u8 agc_config_count;
- struct dibx000_agc_config *agc;
- struct dibx000_bandwidth_config *pll;
-
-#define DIB8000_GPIO_DEFAULT_DIRECTIONS 0xffff
- u16 gpio_dir;
-#define DIB8000_GPIO_DEFAULT_VALUES 0x0000
- u16 gpio_val;
-#define DIB8000_GPIO_PWM_POS0(v) ((v & 0xf) << 12)
-#define DIB8000_GPIO_PWM_POS1(v) ((v & 0xf) << 8 )
-#define DIB8000_GPIO_PWM_POS2(v) ((v & 0xf) << 4 )
-#define DIB8000_GPIO_PWM_POS3(v) (v & 0xf)
-#define DIB8000_GPIO_DEFAULT_PWM_POS 0xffff
- u16 gpio_pwm_pos;
- u16 pwm_freq_div;
-
- void (*agc_control) (struct dvb_frontend *, u8 before);
-
- u16 drives;
- u16 diversity_delay;
- u8 div_cfg;
- u8 output_mode;
- u8 refclksel;
- u8 enMpegOutput:1;
-};
-
-#define DEFAULT_DIB8000_I2C_ADDRESS 18
-
-#if defined(CONFIG_DVB_DIB8000) || (defined(CONFIG_DVB_DIB8000_MODULE) && defined(MODULE))
-extern struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg);
-extern struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *, enum dibx000_i2c_interface, int);
-
-extern int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
- u8 default_addr, u8 first_addr, u8 is_dib8096p);
-
-extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
-extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value);
-extern int dib8000_pid_filter_ctrl(struct dvb_frontend *, u8 onoff);
-extern int dib8000_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
-extern int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state);
-extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe);
-extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe);
-extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode);
-extern struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe);
-extern int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff);
-extern int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ);
-extern u32 dib8000_ctrl_timf(struct dvb_frontend *fe,
- uint8_t op, uint32_t timf);
-extern int dib8000_update_pll(struct dvb_frontend *fe,
- struct dibx000_bandwidth_config *pll);
-extern int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
-extern int dib8000_remove_slave_frontend(struct dvb_frontend *fe);
-extern struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
-#else
-static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface i, int x)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline int dib8000_i2c_enumeration(struct i2c_adapter *host,
- int no_of_demods, u8 default_addr, u8 first_addr,
- u8 is_dib8096p)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-static inline int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-static inline enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return CT_SHUTDOWN;
-}
-static inline void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-}
-static inline struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-static inline int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return 0;
-}
-static inline s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return 0;
-}
-static inline int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return 0;
-}
-static inline u32 dib8000_ctrl_timf(struct dvb_frontend *fe,
- uint8_t op, uint32_t timf)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return 0;
-}
-static inline int dib8000_update_pll(struct dvb_frontend *fe,
- struct dibx000_bandwidth_config *pll)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-static inline int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-int dib8000_remove_slave_frontend(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif
diff --git a/drivers/media/dvb/frontends/dib9000.c b/drivers/media/dvb/frontends/dib9000.c
deleted file mode 100644
index 6201c59a78d..00000000000
--- a/drivers/media/dvb/frontends/dib9000.c
+++ /dev/null
@@ -1,2590 +0,0 @@
-/*
- * Linux-DVB Driver for DiBcom's DiB9000 and demodulator-family.
- *
- * Copyright (C) 2005-10 DiBcom (http://www.dibcom.fr/)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation, version 2.
- */
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/mutex.h>
-
-#include "dvb_math.h"
-#include "dvb_frontend.h"
-
-#include "dib9000.h"
-#include "dibx000_common.h"
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
-
-#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB9000: "); printk(args); printk("\n"); } } while (0)
-#define MAX_NUMBER_OF_FRONTENDS 6
-
-struct i2c_device {
- struct i2c_adapter *i2c_adap;
- u8 i2c_addr;
- u8 *i2c_read_buffer;
- u8 *i2c_write_buffer;
-};
-
-struct dib9000_pid_ctrl {
-#define DIB9000_PID_FILTER_CTRL 0
-#define DIB9000_PID_FILTER 1
- u8 cmd;
- u8 id;
- u16 pid;
- u8 onoff;
-};
-
-struct dib9000_state {
- struct i2c_device i2c;
-
- struct dibx000_i2c_master i2c_master;
- struct i2c_adapter tuner_adap;
- struct i2c_adapter component_bus;
-
- u16 revision;
- u8 reg_offs;
-
- enum frontend_tune_state tune_state;
- u32 status;
- struct dvb_frontend_parametersContext channel_status;
-
- u8 fe_id;
-
-#define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff
- u16 gpio_dir;
-#define DIB9000_GPIO_DEFAULT_VALUES 0x0000
- u16 gpio_val;
-#define DIB9000_GPIO_DEFAULT_PWM_POS 0xffff
- u16 gpio_pwm_pos;
-
- union { /* common for all chips */
- struct {
- u8 mobile_mode:1;
- } host;
-
- struct {
- struct dib9000_fe_memory_map {
- u16 addr;
- u16 size;
- } fe_mm[18];
- u8 memcmd;
-
- struct mutex mbx_if_lock; /* to protect read/write operations */
- struct mutex mbx_lock; /* to protect the whole mailbox handling */
-
- struct mutex mem_lock; /* to protect the memory accesses */
- struct mutex mem_mbx_lock; /* to protect the memory-based mailbox */
-
-#define MBX_MAX_WORDS (256 - 200 - 2)
-#define DIB9000_MSG_CACHE_SIZE 2
- u16 message_cache[DIB9000_MSG_CACHE_SIZE][MBX_MAX_WORDS];
- u8 fw_is_running;
- } risc;
- } platform;
-
- union { /* common for all platforms */
- struct {
- struct dib9000_config cfg;
- } d9;
- } chip;
-
- struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
- u16 component_bus_speed;
-
- /* for the I2C transfer */
- struct i2c_msg msg[2];
- u8 i2c_write_buffer[255];
- u8 i2c_read_buffer[255];
- struct mutex demod_lock;
- u8 get_frontend_internal;
- struct dib9000_pid_ctrl pid_ctrl[10];
- s8 pid_ctrl_index; /* -1: empty list; -2: do not use the list */
-};
-
-static const u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-enum dib9000_power_mode {
- DIB9000_POWER_ALL = 0,
-
- DIB9000_POWER_NO,
- DIB9000_POWER_INTERF_ANALOG_AGC,
- DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
- DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD,
- DIB9000_POWER_INTERFACE_ONLY,
-};
-
-enum dib9000_out_messages {
- OUT_MSG_HBM_ACK,
- OUT_MSG_HOST_BUF_FAIL,
- OUT_MSG_REQ_VERSION,
- OUT_MSG_BRIDGE_I2C_W,
- OUT_MSG_BRIDGE_I2C_R,
- OUT_MSG_BRIDGE_APB_W,
- OUT_MSG_BRIDGE_APB_R,
- OUT_MSG_SCAN_CHANNEL,
- OUT_MSG_MONIT_DEMOD,
- OUT_MSG_CONF_GPIO,
- OUT_MSG_DEBUG_HELP,
- OUT_MSG_SUBBAND_SEL,
- OUT_MSG_ENABLE_TIME_SLICE,
- OUT_MSG_FE_FW_DL,
- OUT_MSG_FE_CHANNEL_SEARCH,
- OUT_MSG_FE_CHANNEL_TUNE,
- OUT_MSG_FE_SLEEP,
- OUT_MSG_FE_SYNC,
- OUT_MSG_CTL_MONIT,
-
- OUT_MSG_CONF_SVC,
- OUT_MSG_SET_HBM,
- OUT_MSG_INIT_DEMOD,
- OUT_MSG_ENABLE_DIVERSITY,
- OUT_MSG_SET_OUTPUT_MODE,
- OUT_MSG_SET_PRIORITARY_CHANNEL,
- OUT_MSG_ACK_FRG,
- OUT_MSG_INIT_PMU,
-};
-
-enum dib9000_in_messages {
- IN_MSG_DATA,
- IN_MSG_FRAME_INFO,
- IN_MSG_CTL_MONIT,
- IN_MSG_ACK_FREE_ITEM,
- IN_MSG_DEBUG_BUF,
- IN_MSG_MPE_MONITOR,
- IN_MSG_RAWTS_MONITOR,
- IN_MSG_END_BRIDGE_I2C_RW,
- IN_MSG_END_BRIDGE_APB_RW,
- IN_MSG_VERSION,
- IN_MSG_END_OF_SCAN,
- IN_MSG_MONIT_DEMOD,
- IN_MSG_ERROR,
- IN_MSG_FE_FW_DL_DONE,
- IN_MSG_EVENT,
- IN_MSG_ACK_CHANGE_SVC,
- IN_MSG_HBM_PROF,
-};
-
-/* memory_access requests */
-#define FE_MM_W_CHANNEL 0
-#define FE_MM_W_FE_INFO 1
-#define FE_MM_RW_SYNC 2
-
-#define FE_SYNC_CHANNEL 1
-#define FE_SYNC_W_GENERIC_MONIT 2
-#define FE_SYNC_COMPONENT_ACCESS 3
-
-#define FE_MM_R_CHANNEL_SEARCH_STATE 3
-#define FE_MM_R_CHANNEL_UNION_CONTEXT 4
-#define FE_MM_R_FE_INFO 5
-#define FE_MM_R_FE_MONITOR 6
-
-#define FE_MM_W_CHANNEL_HEAD 7
-#define FE_MM_W_CHANNEL_UNION 8
-#define FE_MM_W_CHANNEL_CONTEXT 9
-#define FE_MM_R_CHANNEL_UNION 10
-#define FE_MM_R_CHANNEL_CONTEXT 11
-#define FE_MM_R_CHANNEL_TUNE_STATE 12
-
-#define FE_MM_R_GENERIC_MONITORING_SIZE 13
-#define FE_MM_W_GENERIC_MONITORING 14
-#define FE_MM_R_GENERIC_MONITORING 15
-
-#define FE_MM_W_COMPONENT_ACCESS 16
-#define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
-static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len);
-static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
-
-static u16 to_fw_output_mode(u16 mode)
-{
- switch (mode) {
- case OUTMODE_HIGH_Z:
- return 0;
- case OUTMODE_MPEG2_PAR_GATED_CLK:
- return 4;
- case OUTMODE_MPEG2_PAR_CONT_CLK:
- return 8;
- case OUTMODE_MPEG2_SERIAL:
- return 16;
- case OUTMODE_DIVERSITY:
- return 128;
- case OUTMODE_MPEG2_FIFO:
- return 2;
- case OUTMODE_ANALOG_ADC:
- return 1;
- default:
- return 0;
- }
-}
-
-static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 len, u16 attribute)
-{
- u32 chunk_size = 126;
- u32 l;
- int ret;
-
- if (state->platform.risc.fw_is_running && (reg < 1024))
- return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len);
-
- memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
- state->msg[0].addr = state->i2c.i2c_addr >> 1;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = 2;
- state->msg[1].addr = state->i2c.i2c_addr >> 1;
- state->msg[1].flags = I2C_M_RD;
- state->msg[1].buf = b;
- state->msg[1].len = len;
-
- state->i2c_write_buffer[0] = reg >> 8;
- state->i2c_write_buffer[1] = reg & 0xff;
-
- if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
- state->i2c_write_buffer[0] |= (1 << 5);
- if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
- state->i2c_write_buffer[0] |= (1 << 4);
-
- do {
- l = len < chunk_size ? len : chunk_size;
- state->msg[1].len = l;
- state->msg[1].buf = b;
- ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 2) != 2 ? -EREMOTEIO : 0;
- if (ret != 0) {
- dprintk("i2c read error on %d", reg);
- return -EREMOTEIO;
- }
-
- b += l;
- len -= l;
-
- if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
- reg += l / 2;
- } while ((ret == 0) && len);
-
- return 0;
-}
-
-static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg)
-{
- struct i2c_msg msg[2] = {
- {.addr = i2c->i2c_addr >> 1, .flags = 0,
- .buf = i2c->i2c_write_buffer, .len = 2},
- {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD,
- .buf = i2c->i2c_read_buffer, .len = 2},
- };
-
- i2c->i2c_write_buffer[0] = reg >> 8;
- i2c->i2c_write_buffer[1] = reg & 0xff;
-
- if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
- dprintk("read register %x error", reg);
- return 0;
- }
-
- return (i2c->i2c_read_buffer[0] << 8) | i2c->i2c_read_buffer[1];
-}
-
-static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg)
-{
- if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, 0) != 0)
- return 0;
- return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
-}
-
-static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute)
-{
- if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2,
- attribute) != 0)
- return 0;
- return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
-}
-
-#define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
-
-static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute)
-{
- u32 chunk_size = 126;
- u32 l;
- int ret;
-
- if (state->platform.risc.fw_is_running && (reg < 1024)) {
- if (dib9000_risc_apb_access_write
- (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
- return -EINVAL;
- return 0;
- }
-
- memset(&state->msg[0], 0, sizeof(struct i2c_msg));
- state->msg[0].addr = state->i2c.i2c_addr >> 1;
- state->msg[0].flags = 0;
- state->msg[0].buf = state->i2c_write_buffer;
- state->msg[0].len = len + 2;
-
- state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
- state->i2c_write_buffer[1] = (reg) & 0xff;
-
- if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
- state->i2c_write_buffer[0] |= (1 << 5);
- if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
- state->i2c_write_buffer[0] |= (1 << 4);
-
- do {
- l = len < chunk_size ? len : chunk_size;
- state->msg[0].len = l + 2;
- memcpy(&state->i2c_write_buffer[2], buf, l);
-
- ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0;
-
- buf += l;
- len -= l;
-
- if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
- reg += l / 2;
- } while ((ret == 0) && len);
-
- return ret;
-}
-
-static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
-{
- struct i2c_msg msg = {
- .addr = i2c->i2c_addr >> 1, .flags = 0,
- .buf = i2c->i2c_write_buffer, .len = 4
- };
-
- i2c->i2c_write_buffer[0] = (reg >> 8) & 0xff;
- i2c->i2c_write_buffer[1] = reg & 0xff;
- i2c->i2c_write_buffer[2] = (val >> 8) & 0xff;
- i2c->i2c_write_buffer[3] = val & 0xff;
-
- return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
-}
-
-static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val)
-{
- u8 b[2] = { val >> 8, val & 0xff };
- return dib9000_write16_attr(state, reg, b, 2, 0);
-}
-
-static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute)
-{
- u8 b[2] = { val >> 8, val & 0xff };
- return dib9000_write16_attr(state, reg, b, 2, attribute);
-}
-
-#define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
-#define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
-#define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
-
-#define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
-#define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
-
-#define MAC_IRQ (1 << 1)
-#define IRQ_POL_MSK (1 << 4)
-
-#define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
-#define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
-
-static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading)
-{
- u8 b[14] = { 0 };
-
-/* dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */
-/* b[0] = 0 << 7; */
- b[1] = 1;
-
-/* b[2] = 0; */
-/* b[3] = 0; */
- b[4] = (u8) (addr >> 8);
- b[5] = (u8) (addr & 0xff);
-
-/* b[10] = 0; */
-/* b[11] = 0; */
- b[12] = (u8) (addr >> 8);
- b[13] = (u8) (addr & 0xff);
-
- addr += len;
-/* b[6] = 0; */
-/* b[7] = 0; */
- b[8] = (u8) (addr >> 8);
- b[9] = (u8) (addr & 0xff);
-
- dib9000_write(state, 1056, b, 14);
- if (reading)
- dib9000_write_word(state, 1056, (1 << 15) | 1);
- state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-call to set it */
-}
-
-static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd)
-{
- struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f];
- /* decide whether we need to "refresh" the memory controller */
- if (state->platform.risc.memcmd == cmd && /* same command */
- !(cmd & 0x80 && m->size < 67)) /* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
- return;
- dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80);
- state->platform.risc.memcmd = cmd;
-}
-
-static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len)
-{
- if (!state->platform.risc.fw_is_running)
- return -EIO;
-
- if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- dib9000_risc_mem_setup(state, cmd | 0x80);
- dib9000_risc_mem_read_chunks(state, b, len);
- mutex_unlock(&state->platform.risc.mem_lock);
- return 0;
-}
-
-static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b)
-{
- struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd];
- if (!state->platform.risc.fw_is_running)
- return -EIO;
-
- if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- dib9000_risc_mem_setup(state, cmd);
- dib9000_risc_mem_write_chunks(state, b, m->size);
- mutex_unlock(&state->platform.risc.mem_lock);
- return 0;
-}
-
-static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len)
-{
- u16 offs;
-
- if (risc_id == 1)
- offs = 16;
- else
- offs = 0;
-
- /* config crtl reg */
- dib9000_write_word(state, 1024 + offs, 0x000f);
- dib9000_write_word(state, 1025 + offs, 0);
- dib9000_write_word(state, 1031 + offs, key);
-
- dprintk("going to download %dB of microcode", len);
- if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) {
- dprintk("error while downloading microcode for RISC %c", 'A' + risc_id);
- return -EIO;
- }
-
- dprintk("Microcode for RISC %c loaded", 'A' + risc_id);
-
- return 0;
-}
-
-static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id)
-{
- u16 mbox_offs;
- u16 reset_reg;
- u16 tries = 1000;
-
- if (risc_id == 1)
- mbox_offs = 16;
- else
- mbox_offs = 0;
-
- /* Reset mailbox */
- dib9000_write_word(state, 1027 + mbox_offs, 0x8000);
-
- /* Read reset status */
- do {
- reset_reg = dib9000_read_word(state, 1027 + mbox_offs);
- msleep(100);
- } while ((reset_reg & 0x8000) && --tries);
-
- if (reset_reg & 0x8000) {
- dprintk("MBX: init ERROR, no response from RISC %c", 'A' + risc_id);
- return -EIO;
- }
- dprintk("MBX: initialized");
- return 0;
-}
-
-#define MAX_MAILBOX_TRY 100
-static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr)
-{
- u8 *d, b[2];
- u16 tmp;
- u16 size;
- u32 i;
- int ret = 0;
-
- if (!state->platform.risc.fw_is_running)
- return -EINVAL;
-
- if (mutex_lock_interruptible(&state->platform.risc.mbx_if_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- tmp = MAX_MAILBOX_TRY;
- do {
- size = dib9000_read_word_attr(state, 1043, attr) & 0xff;
- if ((size + len + 1) > MBX_MAX_WORDS && --tmp) {
- dprintk("MBX: RISC mbx full, retrying");
- msleep(100);
- } else
- break;
- } while (1);
-
- /*dprintk( "MBX: size: %d", size); */
-
- if (tmp == 0) {
- ret = -EINVAL;
- goto out;
- }
-#ifdef DUMP_MSG
- dprintk("--> %02x %d ", id, len + 1);
- for (i = 0; i < len; i++)
- dprintk("%04x ", data[i]);
- dprintk("\n");
-#endif
-
- /* byte-order conversion - works on big (where it is not necessary) or little endian */
- d = (u8 *) data;
- for (i = 0; i < len; i++) {
- tmp = data[i];
- *d++ = tmp >> 8;
- *d++ = tmp & 0xff;
- }
-
- /* write msg */
- b[0] = id;
- b[1] = len + 1;
- if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) {
- ret = -EIO;
- goto out;
- }
-
- /* update register nb_mes_in_RX */
- ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr);
-
-out:
- mutex_unlock(&state->platform.risc.mbx_if_lock);
-
- return ret;
-}
-
-static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr)
-{
-#ifdef DUMP_MSG
- u16 *d = data;
-#endif
-
- u16 tmp, i;
- u8 size;
- u8 mc_base;
-
- if (!state->platform.risc.fw_is_running)
- return 0;
-
- if (mutex_lock_interruptible(&state->platform.risc.mbx_if_lock) < 0) {
- dprintk("could not get the lock");
- return 0;
- }
- if (risc_id == 1)
- mc_base = 16;
- else
- mc_base = 0;
-
- /* Length and type in the first word */
- *data = dib9000_read_word_attr(state, 1029 + mc_base, attr);
-
- size = *data & 0xff;
- if (size <= MBX_MAX_WORDS) {
- data++;
- size--; /* Initial word already read */
-
- dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr);
-
- /* to word conversion */
- for (i = 0; i < size; i++) {
- tmp = *data;
- *data = (tmp >> 8) | (tmp << 8);
- data++;
- }
-
-#ifdef DUMP_MSG
- dprintk("<-- ");
- for (i = 0; i < size + 1; i++)
- dprintk("%04x ", d[i]);
- dprintk("\n");
-#endif
- } else {
- dprintk("MBX: message is too big for message cache (%d), flushing message", size);
- size--; /* Initial word already read */
- while (size--)
- dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr);
- }
- /* Update register nb_mes_in_TX */
- dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr);
-
- mutex_unlock(&state->platform.risc.mbx_if_lock);
-
- return size + 1;
-}
-
-static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size)
-{
- u32 ts = data[1] << 16 | data[0];
- char *b = (char *)&data[2];
-
- b[2 * (size - 2) - 1] = '\0'; /* Bullet proof the buffer */
- if (*b == '~') {
- b++;
- dprintk(b);
- } else
- dprintk("RISC%d: %d.%04d %s", state->fe_id, ts / 10000, ts % 10000, *b ? b : "<emtpy>");
- return 1;
-}
-
-static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr)
-{
- int i;
- u8 size;
- u16 *block;
- /* find a free slot */
- for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
- block = state->platform.risc.message_cache[i];
- if (*block == 0) {
- size = dib9000_mbx_read(state, block, 1, attr);
-
-/* dprintk( "MBX: fetched %04x message to cache", *block); */
-
- switch (*block >> 8) {
- case IN_MSG_DEBUG_BUF:
- dib9000_risc_debug_buf(state, block + 1, size); /* debug-messages are going to be printed right away */
- *block = 0; /* free the block */
- break;
-#if 0
- case IN_MSG_DATA: /* FE-TRACE */
- dib9000_risc_data_process(state, block + 1, size);
- *block = 0;
- break;
-#endif
- default:
- break;
- }
-
- return 1;
- }
- }
- dprintk("MBX: no free cache-slot found for new message...");
- return -1;
-}
-
-static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr)
-{
- if (risc_id == 0)
- return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f; /* 5 bit field */
- else
- return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f; /* 7 bit field */
-}
-
-static int dib9000_mbx_process(struct dib9000_state *state, u16 attr)
-{
- int ret = 0;
-
- if (!state->platform.risc.fw_is_running)
- return -1;
-
- if (mutex_lock_interruptible(&state->platform.risc.mbx_lock) < 0) {
- dprintk("could not get the lock");
- return -1;
- }
-
- if (dib9000_mbx_count(state, 1, attr)) /* 1=RiscB */
- ret = dib9000_mbx_fetch_to_cache(state, attr);
-
- dib9000_read_word_attr(state, 1229, attr); /* Clear the IRQ */
-/* if (tmp) */
-/* dprintk( "cleared IRQ: %x", tmp); */
- mutex_unlock(&state->platform.risc.mbx_lock);
-
- return ret;
-}
-
-static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr)
-{
- u8 i;
- u16 *block;
- u16 timeout = 30;
-
- *msg = 0;
- do {
- /* dib9000_mbx_get_from_cache(); */
- for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
- block = state->platform.risc.message_cache[i];
- if ((*block >> 8) == id) {
- *size = (*block & 0xff) - 1;
- memcpy(msg, block + 1, (*size) * 2);
- *block = 0; /* free the block */
- i = 0; /* signal that we found a message */
- break;
- }
- }
-
- if (i == 0)
- break;
-
- if (dib9000_mbx_process(state, attr) == -1) /* try to fetch one message - if any */
- return -1;
-
- } while (--timeout);
-
- if (timeout == 0) {
- dprintk("waiting for message %d timed out", id);
- return -1;
- }
-
- return i == 0;
-}
-
-static int dib9000_risc_check_version(struct dib9000_state *state)
-{
- u8 r[4];
- u8 size;
- u16 fw_version = 0;
-
- if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0)
- return -EIO;
-
- if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0)
- return -EIO;
-
- fw_version = (r[0] << 8) | r[1];
- dprintk("RISC: ver: %d.%02d (IC: %d)", fw_version >> 10, fw_version & 0x3ff, (r[2] << 8) | r[3]);
-
- if ((fw_version >> 10) != 7)
- return -EINVAL;
-
- switch (fw_version & 0x3ff) {
- case 11:
- case 12:
- case 14:
- case 15:
- case 16:
- case 17:
- break;
- default:
- dprintk("RISC: invalid firmware version");
- return -EINVAL;
- }
-
- dprintk("RISC: valid firmware version");
- return 0;
-}
-
-static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)
-{
- /* Reconfig pool mac ram */
- dib9000_write_word(state, 1225, 0x02); /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */
- dib9000_write_word(state, 1226, 0x05);
-
- /* Toggles IP crypto to Host APB interface. */
- dib9000_write_word(state, 1542, 1);
-
- /* Set jump and no jump in the dma box */
- dib9000_write_word(state, 1074, 0);
- dib9000_write_word(state, 1075, 0);
-
- /* Set MAC as APB Master. */
- dib9000_write_word(state, 1237, 0);
-
- /* Reset the RISCs */
- if (codeA != NULL)
- dib9000_write_word(state, 1024, 2);
- else
- dib9000_write_word(state, 1024, 15);
- if (codeB != NULL)
- dib9000_write_word(state, 1040, 2);
-
- if (codeA != NULL)
- dib9000_firmware_download(state, 0, 0x1234, codeA, lenA);
- if (codeB != NULL)
- dib9000_firmware_download(state, 1, 0x1234, codeB, lenB);
-
- /* Run the RISCs */
- if (codeA != NULL)
- dib9000_write_word(state, 1024, 0);
- if (codeB != NULL)
- dib9000_write_word(state, 1040, 0);
-
- if (codeA != NULL)
- if (dib9000_mbx_host_init(state, 0) != 0)
- return -EIO;
- if (codeB != NULL)
- if (dib9000_mbx_host_init(state, 1) != 0)
- return -EIO;
-
- msleep(100);
- state->platform.risc.fw_is_running = 1;
-
- if (dib9000_risc_check_version(state) != 0)
- return -EINVAL;
-
- state->platform.risc.memcmd = 0xff;
- return 0;
-}
-
-static u16 dib9000_identify(struct i2c_device *client)
-{
- u16 value;
-
- value = dib9000_i2c_read16(client, 896);
- if (value != 0x01b3) {
- dprintk("wrong Vendor ID (0x%x)", value);
- return 0;
- }
-
- value = dib9000_i2c_read16(client, 897);
- if (value != 0x4000 && value != 0x4001 && value != 0x4002 && value != 0x4003 && value != 0x4004 && value != 0x4005) {
- dprintk("wrong Device ID (0x%x)", value);
- return 0;
- }
-
- /* protect this driver to be used with 7000PC */
- if (value == 0x4000 && dib9000_i2c_read16(client, 769) == 0x4000) {
- dprintk("this driver does not work with DiB7000PC");
- return 0;
- }
-
- switch (value) {
- case 0x4000:
- dprintk("found DiB7000MA/PA/MB/PB");
- break;
- case 0x4001:
- dprintk("found DiB7000HC");
- break;
- case 0x4002:
- dprintk("found DiB7000MC");
- break;
- case 0x4003:
- dprintk("found DiB9000A");
- break;
- case 0x4004:
- dprintk("found DiB9000H");
- break;
- case 0x4005:
- dprintk("found DiB9000M");
- break;
- }
-
- return value;
-}
-
-static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode)
-{
- /* by default everything is going to be powered off */
- u16 reg_903 = 0x3fff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906;
- u8 offset;
-
- if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005)
- offset = 1;
- else
- offset = 0;
-
- reg_906 = dib9000_read_word(state, 906 + offset) | 0x3; /* keep settings for RISC */
-
- /* now, depending on the requested mode, we power on */
- switch (mode) {
- /* power up everything in the demod */
- case DIB9000_POWER_ALL:
- reg_903 = 0x0000;
- reg_904 = 0x0000;
- reg_905 = 0x0000;
- reg_906 = 0x0000;
- break;
-
- /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
- case DIB9000_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */
- reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
- break;
-
- case DIB9000_POWER_INTERF_ANALOG_AGC:
- reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
- reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
- reg_906 &= ~((1 << 0));
- break;
-
- case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
- reg_903 = 0x0000;
- reg_904 = 0x801f;
- reg_905 = 0x0000;
- reg_906 &= ~((1 << 0));
- break;
-
- case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD:
- reg_903 = 0x0000;
- reg_904 = 0x8000;
- reg_905 = 0x010b;
- reg_906 &= ~((1 << 0));
- break;
- default:
- case DIB9000_POWER_NO:
- break;
- }
-
- /* always power down unused parts */
- if (!state->platform.host.mobile_mode)
- reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
-
- /* P_sdio_select_clk = 0 on MC and after */
- if (state->revision != 0x4000)
- reg_906 <<= 1;
-
- dib9000_write_word(state, 903 + offset, reg_903);
- dib9000_write_word(state, 904 + offset, reg_904);
- dib9000_write_word(state, 905 + offset, reg_905);
- dib9000_write_word(state, 906 + offset, reg_906);
-}
-
-static int dib9000_fw_reset(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
-
- dib9000_write_word(state, 1817, 0x0003);
-
- dib9000_write_word(state, 1227, 1);
- dib9000_write_word(state, 1227, 0);
-
- switch ((state->revision = dib9000_identify(&state->i2c))) {
- case 0x4003:
- case 0x4004:
- case 0x4005:
- state->reg_offs = 1;
- break;
- default:
- return -EINVAL;
- }
-
- /* reset the i2c-master to use the host interface */
- dibx000_reset_i2c_master(&state->i2c_master);
-
- dib9000_set_power_mode(state, DIB9000_POWER_ALL);
-
- /* unforce divstr regardless whether i2c enumeration was done or not */
- dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1));
- dib9000_write_word(state, 1796, 0);
- dib9000_write_word(state, 1805, 0x805);
-
- /* restart all parts */
- dib9000_write_word(state, 898, 0xffff);
- dib9000_write_word(state, 899, 0xffff);
- dib9000_write_word(state, 900, 0x0001);
- dib9000_write_word(state, 901, 0xff19);
- dib9000_write_word(state, 902, 0x003c);
-
- dib9000_write_word(state, 898, 0);
- dib9000_write_word(state, 899, 0);
- dib9000_write_word(state, 900, 0);
- dib9000_write_word(state, 901, 0);
- dib9000_write_word(state, 902, 0);
-
- dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives);
-
- dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY);
-
- return 0;
-}
-
-static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len)
-{
- u16 mb[10];
- u8 i, s;
-
- if (address >= 1024 || !state->platform.risc.fw_is_running)
- return -EINVAL;
-
- /* dprintk( "APB access thru rd fw %d %x", address, attribute); */
-
- mb[0] = (u16) address;
- mb[1] = len / 2;
- dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute);
- switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) {
- case 1:
- s--;
- for (i = 0; i < s; i++) {
- b[i * 2] = (mb[i + 1] >> 8) & 0xff;
- b[i * 2 + 1] = (mb[i + 1]) & 0xff;
- }
- return 0;
- default:
- return -EIO;
- }
- return -EIO;
-}
-
-static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len)
-{
- u16 mb[10];
- u8 s, i;
-
- if (address >= 1024 || !state->platform.risc.fw_is_running)
- return -EINVAL;
-
- /* dprintk( "APB access thru wr fw %d %x", address, attribute); */
-
- mb[0] = (unsigned short)address;
- for (i = 0; i < len && i < 20; i += 2)
- mb[1 + (i / 2)] = (b[i] << 8 | b[i + 1]);
-
- dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, 1 + len / 2, attribute);
- return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL;
-}
-
-static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i)
-{
- u8 index_loop = 10;
-
- if (!state->platform.risc.fw_is_running)
- return 0;
- dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i);
- do {
- dib9000_risc_mem_read(state, FE_MM_RW_SYNC, state->i2c_read_buffer, 1);
- } while (state->i2c_read_buffer[0] && index_loop--);
-
- if (index_loop > 0)
- return 0;
- return -EIO;
-}
-
-static int dib9000_fw_init(struct dib9000_state *state)
-{
- struct dibGPIOFunction *f;
- u16 b[40] = { 0 };
- u8 i;
- u8 size;
-
- if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
- return -EIO;
-
- /* initialize the firmware */
- for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) {
- f = &state->chip.d9.cfg.gpio_function[i];
- if (f->mask) {
- switch (f->function) {
- case BOARD_GPIO_FUNCTION_COMPONENT_ON:
- b[0] = (u16) f->mask;
- b[1] = (u16) f->direction;
- b[2] = (u16) f->value;
- break;
- case BOARD_GPIO_FUNCTION_COMPONENT_OFF:
- b[3] = (u16) f->mask;
- b[4] = (u16) f->direction;
- b[5] = (u16) f->value;
- break;
- }
- }
- }
- if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0)
- return -EIO;
-
- /* subband */
- b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */
- for (i = 0; i < state->chip.d9.cfg.subband.size; i++) {
- b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz;
- b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
- b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
- b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
- }
- b[1 + i * 4] = 0; /* fe_id */
- if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0)
- return -EIO;
-
- /* 0 - id, 1 - no_of_frontends */
- b[0] = (0 << 8) | 1;
- /* 0 = i2c-address demod, 0 = tuner */
- b[1] = (0 << 8) | (0);
- b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
- b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
- b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
- b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff);
- b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff);
- b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff);
- b[29] = state->chip.d9.cfg.if_drives;
- if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0)
- return -EIO;
-
- if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0)
- return -EIO;
-
- if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0)
- return -EIO;
-
- if (size > ARRAY_SIZE(b)) {
- dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size,
- (int)ARRAY_SIZE(b));
- return -EINVAL;
- }
-
- for (i = 0; i < size; i += 2) {
- state->platform.risc.fe_mm[i / 2].addr = b[i + 0];
- state->platform.risc.fe_mm[i / 2].size = b[i + 1];
- }
-
- return 0;
-}
-
-static void dib9000_fw_set_channel_head(struct dib9000_state *state)
-{
- u8 b[9];
- u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000;
- if (state->fe_id % 2)
- freq += 101;
-
- b[0] = (u8) ((freq >> 0) & 0xff);
- b[1] = (u8) ((freq >> 8) & 0xff);
- b[2] = (u8) ((freq >> 16) & 0xff);
- b[3] = (u8) ((freq >> 24) & 0xff);
- b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff);
- b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff);
- b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff);
- b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff);
- b[8] = 0x80; /* do not wait for CELL ID when doing autosearch */
- if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT)
- b[8] |= 1;
- dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b);
-}
-
-static int dib9000_fw_get_channel(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- struct dibDVBTChannel {
- s8 spectrum_inversion;
-
- s8 nfft;
- s8 guard;
- s8 constellation;
-
- s8 hrch;
- s8 alpha;
- s8 code_rate_hp;
- s8 code_rate_lp;
- s8 select_hp;
-
- s8 intlv_native;
- };
- struct dibDVBTChannel *ch;
- int ret = 0;
-
- if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
- ret = -EIO;
- goto error;
- }
-
- dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION,
- state->i2c_read_buffer, sizeof(struct dibDVBTChannel));
- ch = (struct dibDVBTChannel *)state->i2c_read_buffer;
-
-
- switch (ch->spectrum_inversion & 0x7) {
- case 1:
- state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
- break;
- case 0:
- state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF;
- break;
- default:
- case -1:
- state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO;
- break;
- }
- switch (ch->nfft) {
- case 0:
- state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
- break;
- case 2:
- state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K;
- break;
- case 1:
- state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
- break;
- default:
- case -1:
- state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
- break;
- }
- switch (ch->guard) {
- case 0:
- state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
- break;
- case 1:
- state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
- break;
- case 2:
- state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
- break;
- case 3:
- state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
- break;
- default:
- case -1:
- state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
- break;
- }
- switch (ch->constellation) {
- case 2:
- state->fe[0]->dtv_property_cache.modulation = QAM_64;
- break;
- case 1:
- state->fe[0]->dtv_property_cache.modulation = QAM_16;
- break;
- case 0:
- state->fe[0]->dtv_property_cache.modulation = QPSK;
- break;
- default:
- case -1:
- state->fe[0]->dtv_property_cache.modulation = QAM_AUTO;
- break;
- }
- switch (ch->hrch) {
- case 0:
- state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE;
- break;
- case 1:
- state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1;
- break;
- default:
- case -1:
- state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
- break;
- }
- switch (ch->code_rate_hp) {
- case 1:
- state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2;
- break;
- case 2:
- state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3;
- break;
- case 3:
- state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4;
- break;
- case 5:
- state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6;
- break;
- case 7:
- state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8;
- break;
- default:
- case -1:
- state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO;
- break;
- }
- switch (ch->code_rate_lp) {
- case 1:
- state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2;
- break;
- case 2:
- state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3;
- break;
- case 3:
- state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4;
- break;
- case 5:
- state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6;
- break;
- case 7:
- state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8;
- break;
- default:
- case -1:
- state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO;
- break;
- }
-
-error:
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
- return ret;
-}
-
-static int dib9000_fw_set_channel_union(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- struct dibDVBTChannel {
- s8 spectrum_inversion;
-
- s8 nfft;
- s8 guard;
- s8 constellation;
-
- s8 hrch;
- s8 alpha;
- s8 code_rate_hp;
- s8 code_rate_lp;
- s8 select_hp;
-
- s8 intlv_native;
- };
- struct dibDVBTChannel ch;
-
- switch (state->fe[0]->dtv_property_cache.inversion) {
- case INVERSION_ON:
- ch.spectrum_inversion = 1;
- break;
- case INVERSION_OFF:
- ch.spectrum_inversion = 0;
- break;
- default:
- case INVERSION_AUTO:
- ch.spectrum_inversion = -1;
- break;
- }
- switch (state->fe[0]->dtv_property_cache.transmission_mode) {
- case TRANSMISSION_MODE_2K:
- ch.nfft = 0;
- break;
- case TRANSMISSION_MODE_4K:
- ch.nfft = 2;
- break;
- case TRANSMISSION_MODE_8K:
- ch.nfft = 1;
- break;
- default:
- case TRANSMISSION_MODE_AUTO:
- ch.nfft = 1;
- break;
- }
- switch (state->fe[0]->dtv_property_cache.guard_interval) {
- case GUARD_INTERVAL_1_32:
- ch.guard = 0;
- break;
- case GUARD_INTERVAL_1_16:
- ch.guard = 1;
- break;
- case GUARD_INTERVAL_1_8:
- ch.guard = 2;
- break;
- case GUARD_INTERVAL_1_4:
- ch.guard = 3;
- break;
- default:
- case GUARD_INTERVAL_AUTO:
- ch.guard = -1;
- break;
- }
- switch (state->fe[0]->dtv_property_cache.modulation) {
- case QAM_64:
- ch.constellation = 2;
- break;
- case QAM_16:
- ch.constellation = 1;
- break;
- case QPSK:
- ch.constellation = 0;
- break;
- default:
- case QAM_AUTO:
- ch.constellation = -1;
- break;
- }
- switch (state->fe[0]->dtv_property_cache.hierarchy) {
- case HIERARCHY_NONE:
- ch.hrch = 0;
- break;
- case HIERARCHY_1:
- case HIERARCHY_2:
- case HIERARCHY_4:
- ch.hrch = 1;
- break;
- default:
- case HIERARCHY_AUTO:
- ch.hrch = -1;
- break;
- }
- ch.alpha = 1;
- switch (state->fe[0]->dtv_property_cache.code_rate_HP) {
- case FEC_1_2:
- ch.code_rate_hp = 1;
- break;
- case FEC_2_3:
- ch.code_rate_hp = 2;
- break;
- case FEC_3_4:
- ch.code_rate_hp = 3;
- break;
- case FEC_5_6:
- ch.code_rate_hp = 5;
- break;
- case FEC_7_8:
- ch.code_rate_hp = 7;
- break;
- default:
- case FEC_AUTO:
- ch.code_rate_hp = -1;
- break;
- }
- switch (state->fe[0]->dtv_property_cache.code_rate_LP) {
- case FEC_1_2:
- ch.code_rate_lp = 1;
- break;
- case FEC_2_3:
- ch.code_rate_lp = 2;
- break;
- case FEC_3_4:
- ch.code_rate_lp = 3;
- break;
- case FEC_5_6:
- ch.code_rate_lp = 5;
- break;
- case FEC_7_8:
- ch.code_rate_lp = 7;
- break;
- default:
- case FEC_AUTO:
- ch.code_rate_lp = -1;
- break;
- }
- ch.select_hp = 1;
- ch.intlv_native = 1;
-
- dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch);
-
- return 0;
-}
-
-static int dib9000_fw_tune(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN;
- s8 i;
-
- switch (state->tune_state) {
- case CT_DEMOD_START:
- dib9000_fw_set_channel_head(state);
-
- /* write the channel context - a channel is initialized to 0, so it is OK */
- dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info);
- dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info);
-
- if (search)
- dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0);
- else {
- dib9000_fw_set_channel_union(fe);
- dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0);
- }
- state->tune_state = CT_DEMOD_STEP_1;
- break;
- case CT_DEMOD_STEP_1:
- if (search)
- dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, state->i2c_read_buffer, 1);
- else
- dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, state->i2c_read_buffer, 1);
- i = (s8)state->i2c_read_buffer[0];
- switch (i) { /* something happened */
- case 0:
- break;
- case -2: /* tps locks are "slower" than MPEG locks -> even in autosearch data is OK here */
- if (search)
- state->status = FE_STATUS_DEMOD_SUCCESS;
- else {
- state->tune_state = CT_DEMOD_STOP;
- state->status = FE_STATUS_LOCKED;
- }
- break;
- default:
- state->status = FE_STATUS_TUNE_FAILED;
- state->tune_state = CT_DEMOD_STOP;
- break;
- }
- break;
- default:
- ret = FE_CALLBACK_TIME_NEVER;
- break;
- }
-
- return ret;
-}
-
-static int dib9000_fw_set_diversity_in(struct dvb_frontend *fe, int onoff)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u16 mode = (u16) onoff;
- return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1);
-}
-
-static int dib9000_fw_set_output_mode(struct dvb_frontend *fe, int mode)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u16 outreg, smo_mode;
-
- dprintk("setting output mode for demod %p to %d", fe, mode);
-
- switch (mode) {
- case OUTMODE_MPEG2_PAR_GATED_CLK:
- outreg = (1 << 10); /* 0x0400 */
- break;
- case OUTMODE_MPEG2_PAR_CONT_CLK:
- outreg = (1 << 10) | (1 << 6); /* 0x0440 */
- break;
- case OUTMODE_MPEG2_SERIAL:
- outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
- break;
- case OUTMODE_DIVERSITY:
- outreg = (1 << 10) | (4 << 6); /* 0x0500 */
- break;
- case OUTMODE_MPEG2_FIFO:
- outreg = (1 << 10) | (5 << 6);
- break;
- case OUTMODE_HIGH_Z:
- outreg = 0;
- break;
- default:
- dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]);
- return -EINVAL;
- }
-
- dib9000_write_word(state, 1795, outreg);
-
- switch (mode) {
- case OUTMODE_MPEG2_PAR_GATED_CLK:
- case OUTMODE_MPEG2_PAR_CONT_CLK:
- case OUTMODE_MPEG2_SERIAL:
- case OUTMODE_MPEG2_FIFO:
- smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1);
- if (state->chip.d9.cfg.output_mpeg2_in_188_bytes)
- smo_mode |= (1 << 5);
- dib9000_write_word(state, 295, smo_mode);
- break;
- }
-
- outreg = to_fw_output_mode(mode);
- return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1);
-}
-
-static int dib9000_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
-{
- struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
- u16 i, len, t, index_msg;
-
- for (index_msg = 0; index_msg < num; index_msg++) {
- if (msg[index_msg].flags & I2C_M_RD) { /* read */
- len = msg[index_msg].len;
- if (len > 16)
- len = 16;
-
- if (dib9000_read_word(state, 790) != 0)
- dprintk("TunerITF: read busy");
-
- dib9000_write_word(state, 784, (u16) (msg[index_msg].addr));
- dib9000_write_word(state, 787, (len / 2) - 1);
- dib9000_write_word(state, 786, 1); /* start read */
-
- i = 1000;
- while (dib9000_read_word(state, 790) != (len / 2) && i)
- i--;
-
- if (i == 0)
- dprintk("TunerITF: read failed");
-
- for (i = 0; i < len; i += 2) {
- t = dib9000_read_word(state, 785);
- msg[index_msg].buf[i] = (t >> 8) & 0xff;
- msg[index_msg].buf[i + 1] = (t) & 0xff;
- }
- if (dib9000_read_word(state, 790) != 0)
- dprintk("TunerITF: read more data than expected");
- } else {
- i = 1000;
- while (dib9000_read_word(state, 789) && i)
- i--;
- if (i == 0)
- dprintk("TunerITF: write busy");
-
- len = msg[index_msg].len;
- if (len > 16)
- len = 16;
-
- for (i = 0; i < len; i += 2)
- dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]);
- dib9000_write_word(state, 784, (u16) msg[index_msg].addr);
- dib9000_write_word(state, 787, (len / 2) - 1);
- dib9000_write_word(state, 786, 0); /* start write */
-
- i = 1000;
- while (dib9000_read_word(state, 791) > 0 && i)
- i--;
- if (i == 0)
- dprintk("TunerITF: write failed");
- }
- }
- return num;
-}
-
-int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
-{
- struct dib9000_state *state = fe->demodulator_priv;
-
- state->component_bus_speed = speed;
- return 0;
-}
-EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed);
-
-static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
-{
- struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
- u8 type = 0; /* I2C */
- u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4;
- u16 scl = state->component_bus_speed; /* SCL frequency */
- struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER];
- u8 p[13] = { 0 };
-
- p[0] = type;
- p[1] = port;
- p[2] = msg[0].addr << 1;
-
- p[3] = (u8) scl & 0xff; /* scl */
- p[4] = (u8) (scl >> 8);
-
- p[7] = 0;
- p[8] = 0;
-
- p[9] = (u8) (msg[0].len);
- p[10] = (u8) (msg[0].len >> 8);
- if ((num > 1) && (msg[1].flags & I2C_M_RD)) {
- p[11] = (u8) (msg[1].len);
- p[12] = (u8) (msg[1].len >> 8);
- } else {
- p[11] = 0;
- p[12] = 0;
- }
-
- if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
- dprintk("could not get the lock");
- return 0;
- }
-
- dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p);
-
- { /* write-part */
- dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0);
- dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len);
- }
-
- /* do the transaction */
- if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) {
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
- return 0;
- }
-
- /* read back any possible result */
- if ((num > 1) && (msg[1].flags & I2C_M_RD))
- dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len);
-
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
-
- return num;
-}
-
-static u32 dib9000_i2c_func(struct i2c_adapter *adapter)
-{
- return I2C_FUNC_I2C;
-}
-
-static struct i2c_algorithm dib9000_tuner_algo = {
- .master_xfer = dib9000_tuner_xfer,
- .functionality = dib9000_i2c_func,
-};
-
-static struct i2c_algorithm dib9000_component_bus_algo = {
- .master_xfer = dib9000_fw_component_bus_xfer,
- .functionality = dib9000_i2c_func,
-};
-
-struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
-{
- struct dib9000_state *st = fe->demodulator_priv;
- return &st->tuner_adap;
-}
-EXPORT_SYMBOL(dib9000_get_tuner_interface);
-
-struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
-{
- struct dib9000_state *st = fe->demodulator_priv;
- return &st->component_bus;
-}
-EXPORT_SYMBOL(dib9000_get_component_bus_interface);
-
-struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
-{
- struct dib9000_state *st = fe->demodulator_priv;
- return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
-}
-EXPORT_SYMBOL(dib9000_get_i2c_master);
-
-int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
-{
- struct dib9000_state *st = fe->demodulator_priv;
-
- st->i2c.i2c_adap = i2c;
- return 0;
-}
-EXPORT_SYMBOL(dib9000_set_i2c_adapter);
-
-static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val)
-{
- st->gpio_dir = dib9000_read_word(st, 773);
- st->gpio_dir &= ~(1 << num); /* reset the direction bit */
- st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
- dib9000_write_word(st, 773, st->gpio_dir);
-
- st->gpio_val = dib9000_read_word(st, 774);
- st->gpio_val &= ~(1 << num); /* reset the direction bit */
- st->gpio_val |= (val & 0x01) << num; /* set the new value */
- dib9000_write_word(st, 774, st->gpio_val);
-
- dprintk("gpio dir: %04x: gpio val: %04x", st->gpio_dir, st->gpio_val);
-
- return 0;
-}
-
-int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- return dib9000_cfg_gpio(state, num, dir, val);
-}
-EXPORT_SYMBOL(dib9000_set_gpio);
-
-int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u16 val;
- int ret;
-
- if ((state->pid_ctrl_index != -2) && (state->pid_ctrl_index < 9)) {
- /* postpone the pid filtering cmd */
- dprintk("pid filter cmd postpone");
- state->pid_ctrl_index++;
- state->pid_ctrl[state->pid_ctrl_index].cmd = DIB9000_PID_FILTER_CTRL;
- state->pid_ctrl[state->pid_ctrl_index].onoff = onoff;
- return 0;
- }
-
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
-
- val = dib9000_read_word(state, 294 + 1) & 0xffef;
- val |= (onoff & 0x1) << 4;
-
- dprintk("PID filter enabled %d", onoff);
- ret = dib9000_write_word(state, 294 + 1, val);
- mutex_unlock(&state->demod_lock);
- return ret;
-
-}
-EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl);
-
-int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- int ret;
-
- if (state->pid_ctrl_index != -2) {
- /* postpone the pid filtering cmd */
- dprintk("pid filter postpone");
- if (state->pid_ctrl_index < 9) {
- state->pid_ctrl_index++;
- state->pid_ctrl[state->pid_ctrl_index].cmd = DIB9000_PID_FILTER;
- state->pid_ctrl[state->pid_ctrl_index].id = id;
- state->pid_ctrl[state->pid_ctrl_index].pid = pid;
- state->pid_ctrl[state->pid_ctrl_index].onoff = onoff;
- } else
- dprintk("can not add any more pid ctrl cmd");
- return 0;
- }
-
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
- ret = dib9000_write_word(state, 300 + 1 + id,
- onoff ? (1 << 13) | pid : 0);
- mutex_unlock(&state->demod_lock);
- return ret;
-}
-EXPORT_SYMBOL(dib9000_fw_pid_filter);
-
-int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- return dib9000_fw_init(state);
-}
-EXPORT_SYMBOL(dib9000_firmware_post_pll_init);
-
-static void dib9000_release(struct dvb_frontend *demod)
-{
- struct dib9000_state *st = demod->demodulator_priv;
- u8 index_frontend;
-
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
- dvb_frontend_detach(st->fe[index_frontend]);
-
- dibx000_exit_i2c_master(&st->i2c_master);
-
- i2c_del_adapter(&st->tuner_adap);
- i2c_del_adapter(&st->component_bus);
- kfree(st->fe[0]);
- kfree(st);
-}
-
-static int dib9000_wakeup(struct dvb_frontend *fe)
-{
- return 0;
-}
-
-static int dib9000_sleep(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u8 index_frontend;
- int ret = 0;
-
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
- if (ret < 0)
- goto error;
- }
- ret = dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0);
-
-error:
- mutex_unlock(&state->demod_lock);
- return ret;
-}
-
-static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
-{
- tune->min_delay_ms = 1000;
- return 0;
-}
-
-static int dib9000_get_frontend(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u8 index_frontend, sub_index_frontend;
- fe_status_t stat;
- int ret = 0;
-
- if (state->get_frontend_internal == 0) {
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- }
-
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
- if (stat & FE_HAS_SYNC) {
- dprintk("TPS lock on the slave%i", index_frontend);
-
- /* synchronize the cache with the other frontends */
- state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]);
- for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL);
- sub_index_frontend++) {
- if (sub_index_frontend != index_frontend) {
- state->fe[sub_index_frontend]->dtv_property_cache.modulation =
- state->fe[index_frontend]->dtv_property_cache.modulation;
- state->fe[sub_index_frontend]->dtv_property_cache.inversion =
- state->fe[index_frontend]->dtv_property_cache.inversion;
- state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode =
- state->fe[index_frontend]->dtv_property_cache.transmission_mode;
- state->fe[sub_index_frontend]->dtv_property_cache.guard_interval =
- state->fe[index_frontend]->dtv_property_cache.guard_interval;
- state->fe[sub_index_frontend]->dtv_property_cache.hierarchy =
- state->fe[index_frontend]->dtv_property_cache.hierarchy;
- state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP =
- state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
- state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP =
- state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
- state->fe[sub_index_frontend]->dtv_property_cache.rolloff =
- state->fe[index_frontend]->dtv_property_cache.rolloff;
- }
- }
- ret = 0;
- goto return_value;
- }
- }
-
- /* get the channel from master chip */
- ret = dib9000_fw_get_channel(fe);
- if (ret != 0)
- goto return_value;
-
- /* synchronize the cache with the other frontends */
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
- state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
- state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
- state->fe[index_frontend]->dtv_property_cache.modulation = fe->dtv_property_cache.modulation;
- state->fe[index_frontend]->dtv_property_cache.hierarchy = fe->dtv_property_cache.hierarchy;
- state->fe[index_frontend]->dtv_property_cache.code_rate_HP = fe->dtv_property_cache.code_rate_HP;
- state->fe[index_frontend]->dtv_property_cache.code_rate_LP = fe->dtv_property_cache.code_rate_LP;
- state->fe[index_frontend]->dtv_property_cache.rolloff = fe->dtv_property_cache.rolloff;
- }
- ret = 0;
-
-return_value:
- if (state->get_frontend_internal == 0)
- mutex_unlock(&state->demod_lock);
- return ret;
-}
-
-static int dib9000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- state->tune_state = tune_state;
- if (tune_state == CT_DEMOD_START)
- state->status = FE_STATUS_TUNE_PENDING;
-
- return 0;
-}
-
-static u32 dib9000_get_status(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- return state->status;
-}
-
-static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_frontend_parametersContext *channel_status)
-{
- struct dib9000_state *state = fe->demodulator_priv;
-
- memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext));
- return 0;
-}
-
-static int dib9000_set_frontend(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- int sleep_time, sleep_time_slave;
- u32 frontend_status;
- u8 nbr_pending, exit_condition, index_frontend, index_frontend_success;
- struct dvb_frontend_parametersContext channel_status;
-
- /* check that the correct parameters are set */
- if (state->fe[0]->dtv_property_cache.frequency == 0) {
- dprintk("dib9000: must specify frequency ");
- return 0;
- }
-
- if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
- dprintk("dib9000: must specify bandwidth ");
- return 0;
- }
-
- state->pid_ctrl_index = -1; /* postpone the pid filtering cmd */
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return 0;
- }
-
- fe->dtv_property_cache.delivery_system = SYS_DVBT;
-
- /* set the master status */
- if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO ||
- state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO ||
- state->fe[0]->dtv_property_cache.modulation == QAM_AUTO ||
- state->fe[0]->dtv_property_cache.code_rate_HP == FEC_AUTO) {
- /* no channel specified, autosearch the channel */
- state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
- } else
- state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
-
- /* set mode and status for the different frontends */
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- dib9000_fw_set_diversity_in(state->fe[index_frontend], 1);
-
- /* synchronization of the cache */
- memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
-
- state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT;
- dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
-
- dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status);
- dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
- }
-
- /* actual tune */
- exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
- index_frontend_success = 0;
- do {
- sleep_time = dib9000_fw_tune(state->fe[0]);
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]);
- if (sleep_time == FE_CALLBACK_TIME_NEVER)
- sleep_time = sleep_time_slave;
- else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
- sleep_time = sleep_time_slave;
- }
- if (sleep_time != FE_CALLBACK_TIME_NEVER)
- msleep(sleep_time / 10);
- else
- break;
-
- nbr_pending = 0;
- exit_condition = 0;
- index_frontend_success = 0;
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- frontend_status = -dib9000_get_status(state->fe[index_frontend]);
- if (frontend_status > -FE_STATUS_TUNE_PENDING) {
- exit_condition = 2; /* tune success */
- index_frontend_success = index_frontend;
- break;
- }
- if (frontend_status == -FE_STATUS_TUNE_PENDING)
- nbr_pending++; /* some frontends are still tuning */
- }
- if ((exit_condition != 2) && (nbr_pending == 0))
- exit_condition = 1; /* if all tune are done and no success, exit: tune failed */
-
- } while (exit_condition == 0);
-
- /* check the tune result */
- if (exit_condition == 1) { /* tune failed */
- dprintk("tune failed");
- mutex_unlock(&state->demod_lock);
- /* tune failed; put all the pid filtering cmd to junk */
- state->pid_ctrl_index = -1;
- return 0;
- }
-
- dprintk("tune success on frontend%i", index_frontend_success);
-
- /* synchronize all the channel cache */
- state->get_frontend_internal = 1;
- dib9000_get_frontend(state->fe[0]);
- state->get_frontend_internal = 0;
-
- /* retune the other frontends with the found channel */
- channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- /* only retune the frontends which was not tuned success */
- if (index_frontend != index_frontend_success) {
- dib9000_set_channel_status(state->fe[index_frontend], &channel_status);
- dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
- }
- }
- do {
- sleep_time = FE_CALLBACK_TIME_NEVER;
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- if (index_frontend != index_frontend_success) {
- sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]);
- if (sleep_time == FE_CALLBACK_TIME_NEVER)
- sleep_time = sleep_time_slave;
- else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
- sleep_time = sleep_time_slave;
- }
- }
- if (sleep_time != FE_CALLBACK_TIME_NEVER)
- msleep(sleep_time / 10);
- else
- break;
-
- nbr_pending = 0;
- for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- if (index_frontend != index_frontend_success) {
- frontend_status = -dib9000_get_status(state->fe[index_frontend]);
- if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING))
- nbr_pending++; /* some frontends are still tuning */
- }
- }
- } while (nbr_pending != 0);
-
- /* set the output mode */
- dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
- dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
-
- /* turn off the diversity for the last frontend */
- dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0);
-
- mutex_unlock(&state->demod_lock);
- if (state->pid_ctrl_index >= 0) {
- u8 index_pid_filter_cmd;
- u8 pid_ctrl_index = state->pid_ctrl_index;
-
- state->pid_ctrl_index = -2;
- for (index_pid_filter_cmd = 0;
- index_pid_filter_cmd <= pid_ctrl_index;
- index_pid_filter_cmd++) {
- if (state->pid_ctrl[index_pid_filter_cmd].cmd == DIB9000_PID_FILTER_CTRL)
- dib9000_fw_pid_filter_ctrl(state->fe[0],
- state->pid_ctrl[index_pid_filter_cmd].onoff);
- else if (state->pid_ctrl[index_pid_filter_cmd].cmd == DIB9000_PID_FILTER)
- dib9000_fw_pid_filter(state->fe[0],
- state->pid_ctrl[index_pid_filter_cmd].id,
- state->pid_ctrl[index_pid_filter_cmd].pid,
- state->pid_ctrl[index_pid_filter_cmd].onoff);
- }
- }
- /* do not postpone any more the pid filtering */
- state->pid_ctrl_index = -2;
-
- return 0;
-}
-
-static u16 dib9000_read_lock(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
-
- return dib9000_read_word(state, 535);
-}
-
-static int dib9000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u8 index_frontend;
- u16 lock = 0, lock_slave = 0;
-
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
- lock_slave |= dib9000_read_lock(state->fe[index_frontend]);
-
- lock = dib9000_read_word(state, 535);
-
- *stat = 0;
-
- if ((lock & 0x8000) || (lock_slave & 0x8000))
- *stat |= FE_HAS_SIGNAL;
- if ((lock & 0x3000) || (lock_slave & 0x3000))
- *stat |= FE_HAS_CARRIER;
- if ((lock & 0x0100) || (lock_slave & 0x0100))
- *stat |= FE_HAS_VITERBI;
- if (((lock & 0x0038) == 0x38) || ((lock_slave & 0x0038) == 0x38))
- *stat |= FE_HAS_SYNC;
- if ((lock & 0x0008) || (lock_slave & 0x0008))
- *stat |= FE_HAS_LOCK;
-
- mutex_unlock(&state->demod_lock);
-
- return 0;
-}
-
-static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u16 *c;
- int ret = 0;
-
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
- dprintk("could not get the lock");
- ret = -EINTR;
- goto error;
- }
- if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
- ret = -EIO;
- goto error;
- }
- dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR,
- state->i2c_read_buffer, 16 * 2);
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
-
- c = (u16 *)state->i2c_read_buffer;
-
- *ber = c[10] << 16 | c[11];
-
-error:
- mutex_unlock(&state->demod_lock);
- return ret;
-}
-
-static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u8 index_frontend;
- u16 *c = (u16 *)state->i2c_read_buffer;
- u16 val;
- int ret = 0;
-
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- *strength = 0;
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
- state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
- if (val > 65535 - *strength)
- *strength = 65535;
- else
- *strength += val;
- }
-
- if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
- dprintk("could not get the lock");
- ret = -EINTR;
- goto error;
- }
- if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
- ret = -EIO;
- goto error;
- }
- dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
-
- val = 65535 - c[4];
- if (val > 65535 - *strength)
- *strength = 65535;
- else
- *strength += val;
-
-error:
- mutex_unlock(&state->demod_lock);
- return ret;
-}
-
-static u32 dib9000_get_snr(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u16 *c = (u16 *)state->i2c_read_buffer;
- u32 n, s, exp;
- u16 val;
-
- if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
- dprintk("could not get the lock");
- return 0;
- }
- if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
- return 0;
- }
- dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
-
- val = c[7];
- n = (val >> 4) & 0xff;
- exp = ((val & 0xf) << 2);
- val = c[8];
- exp += ((val >> 14) & 0x3);
- if ((exp & 0x20) != 0)
- exp -= 0x40;
- n <<= exp + 16;
-
- s = (val >> 6) & 0xFF;
- exp = (val & 0x3F);
- if ((exp & 0x20) != 0)
- exp -= 0x40;
- s <<= exp + 16;
-
- if (n > 0) {
- u32 t = (s / n) << 16;
- return t + ((s << 16) - n * t) / n;
- }
- return 0xffffffff;
-}
-
-static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u8 index_frontend;
- u32 snr_master;
-
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- snr_master = dib9000_get_snr(fe);
- for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
- snr_master += dib9000_get_snr(state->fe[index_frontend]);
-
- if ((snr_master >> 16) != 0) {
- snr_master = 10 * intlog10(snr_master >> 16);
- *snr = snr_master / ((1 << 24) / 10);
- } else
- *snr = 0;
-
- mutex_unlock(&state->demod_lock);
-
- return 0;
-}
-
-static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u16 *c = (u16 *)state->i2c_read_buffer;
- int ret = 0;
-
- if (mutex_lock_interruptible(&state->demod_lock) < 0) {
- dprintk("could not get the lock");
- return -EINTR;
- }
- if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
- dprintk("could not get the lock");
- ret = -EINTR;
- goto error;
- }
- if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
- ret = -EIO;
- goto error;
- }
- dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
- mutex_unlock(&state->platform.risc.mem_mbx_lock);
-
- *unc = c[12];
-
-error:
- mutex_unlock(&state->demod_lock);
- return ret;
-}
-
-int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr)
-{
- int k = 0, ret = 0;
- u8 new_addr = 0;
- struct i2c_device client = {.i2c_adap = i2c };
-
- client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
- if (!client.i2c_write_buffer) {
- dprintk("%s: not enough memory", __func__);
- return -ENOMEM;
- }
- client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
- if (!client.i2c_read_buffer) {
- dprintk("%s: not enough memory", __func__);
- ret = -ENOMEM;
- goto error_memory;
- }
-
- client.i2c_addr = default_addr + 16;
- dib9000_i2c_write16(&client, 1796, 0x0);
-
- for (k = no_of_demods - 1; k >= 0; k--) {
- /* designated i2c address */
- new_addr = first_addr + (k << 1);
- client.i2c_addr = default_addr;
-
- dib9000_i2c_write16(&client, 1817, 3);
- dib9000_i2c_write16(&client, 1796, 0);
- dib9000_i2c_write16(&client, 1227, 1);
- dib9000_i2c_write16(&client, 1227, 0);
-
- client.i2c_addr = new_addr;
- dib9000_i2c_write16(&client, 1817, 3);
- dib9000_i2c_write16(&client, 1796, 0);
- dib9000_i2c_write16(&client, 1227, 1);
- dib9000_i2c_write16(&client, 1227, 0);
-
- if (dib9000_identify(&client) == 0) {
- client.i2c_addr = default_addr;
- if (dib9000_identify(&client) == 0) {
- dprintk("DiB9000 #%d: not identified", k);
- ret = -EIO;
- goto error;
- }
- }
-
- dib9000_i2c_write16(&client, 1795, (1 << 10) | (4 << 6));
- dib9000_i2c_write16(&client, 1794, (new_addr << 2) | 2);
-
- dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
- }
-
- for (k = 0; k < no_of_demods; k++) {
- new_addr = first_addr | (k << 1);
- client.i2c_addr = new_addr;
-
- dib9000_i2c_write16(&client, 1794, (new_addr << 2));
- dib9000_i2c_write16(&client, 1795, 0);
- }
-
-error:
- kfree(client.i2c_read_buffer);
-error_memory:
- kfree(client.i2c_write_buffer);
-
- return ret;
-}
-EXPORT_SYMBOL(dib9000_i2c_enumeration);
-
-int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u8 index_frontend = 1;
-
- while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
- index_frontend++;
- if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
- dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
- state->fe[index_frontend] = fe_slave;
- return 0;
- }
-
- dprintk("too many slave frontend");
- return -ENOMEM;
-}
-EXPORT_SYMBOL(dib9000_set_slave_frontend);
-
-int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
-{
- struct dib9000_state *state = fe->demodulator_priv;
- u8 index_frontend = 1;
-
- while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
- index_frontend++;
- if (index_frontend != 1) {
- dprintk("remove slave fe %p (index %i)", state->fe[index_frontend - 1], index_frontend - 1);
- state->fe[index_frontend] = NULL;
- return 0;
- }
-
- dprintk("no frontend to be removed");
- return -ENODEV;
-}
-EXPORT_SYMBOL(dib9000_remove_slave_frontend);
-
-struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
-{
- struct dib9000_state *state = fe->demodulator_priv;
-
- if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
- return NULL;
- return state->fe[slave_index];
-}
-EXPORT_SYMBOL(dib9000_get_slave_frontend);
-
-static struct dvb_frontend_ops dib9000_ops;
-struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg)
-{
- struct dvb_frontend *fe;
- struct dib9000_state *st;
- st = kzalloc(sizeof(struct dib9000_state), GFP_KERNEL);
- if (st == NULL)
- return NULL;
- fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
- if (fe == NULL) {
- kfree(st);
- return NULL;
- }
-
- memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
- st->i2c.i2c_adap = i2c_adap;
- st->i2c.i2c_addr = i2c_addr;
- st->i2c.i2c_write_buffer = st->i2c_write_buffer;
- st->i2c.i2c_read_buffer = st->i2c_read_buffer;
-
- st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS;
- st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES;
- st->gpio_pwm_pos = DIB9000_GPIO_DEFAULT_PWM_POS;
-
- mutex_init(&st->platform.risc.mbx_if_lock);
- mutex_init(&st->platform.risc.mbx_lock);
- mutex_init(&st->platform.risc.mem_lock);
- mutex_init(&st->platform.risc.mem_mbx_lock);
- mutex_init(&st->demod_lock);
- st->get_frontend_internal = 0;
-
- st->pid_ctrl_index = -2;
-
- st->fe[0] = fe;
- fe->demodulator_priv = st;
- memcpy(&st->fe[0]->ops, &dib9000_ops, sizeof(struct dvb_frontend_ops));
-
- /* Ensure the output mode remains at the previous default if it's
- * not specifically set by the caller.
- */
- if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
- st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO;
-
- if (dib9000_identify(&st->i2c) == 0)
- goto error;
-
- dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c.i2c_adap, st->i2c.i2c_addr);
-
- st->tuner_adap.dev.parent = i2c_adap->dev.parent;
- strncpy(st->tuner_adap.name, "DIB9000_FW TUNER ACCESS", sizeof(st->tuner_adap.name));
- st->tuner_adap.algo = &dib9000_tuner_algo;
- st->tuner_adap.algo_data = NULL;
- i2c_set_adapdata(&st->tuner_adap, st);
- if (i2c_add_adapter(&st->tuner_adap) < 0)
- goto error;
-
- st->component_bus.dev.parent = i2c_adap->dev.parent;
- strncpy(st->component_bus.name, "DIB9000_FW COMPONENT BUS ACCESS", sizeof(st->component_bus.name));
- st->component_bus.algo = &dib9000_component_bus_algo;
- st->component_bus.algo_data = NULL;
- st->component_bus_speed = 340;
- i2c_set_adapdata(&st->component_bus, st);
- if (i2c_add_adapter(&st->component_bus) < 0)
- goto component_bus_add_error;
-
- dib9000_fw_reset(fe);
-
- return fe;
-
-component_bus_add_error:
- i2c_del_adapter(&st->tuner_adap);
-error:
- kfree(st);
- return NULL;
-}
-EXPORT_SYMBOL(dib9000_attach);
-
-static struct dvb_frontend_ops dib9000_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "DiBcom 9000",
- .frequency_min = 44250000,
- .frequency_max = 867250000,
- .frequency_stepsize = 62500,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
- },
-
- .release = dib9000_release,
-
- .init = dib9000_wakeup,
- .sleep = dib9000_sleep,
-
- .set_frontend = dib9000_set_frontend,
- .get_tune_settings = dib9000_fe_get_tune_settings,
- .get_frontend = dib9000_get_frontend,
-
- .read_status = dib9000_read_status,
- .read_ber = dib9000_read_ber,
- .read_signal_strength = dib9000_read_signal_strength,
- .read_snr = dib9000_read_snr,
- .read_ucblocks = dib9000_read_unc_blocks,
-};
-
-MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
-MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
-MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib9000.h b/drivers/media/dvb/frontends/dib9000.h
deleted file mode 100644
index b5781a48034..00000000000
--- a/drivers/media/dvb/frontends/dib9000.h
+++ /dev/null
@@ -1,131 +0,0 @@
-#ifndef DIB9000_H
-#define DIB9000_H
-
-#include "dibx000_common.h"
-
-struct dib9000_config {
- u8 dvbt_mode;
- u8 output_mpeg2_in_188_bytes;
- u8 hostbus_diversity;
- struct dibx000_bandwidth_config *bw;
-
- u16 if_drives;
-
- u32 timing_frequency;
- u32 xtal_clock_khz;
- u32 vcxo_timer;
- u32 demod_clock_khz;
-
- const u8 *microcode_B_fe_buffer;
- u32 microcode_B_fe_size;
-
- struct dibGPIOFunction gpio_function[2];
- struct dibSubbandSelection subband;
-
- u8 output_mode;
-};
-
-#define DEFAULT_DIB9000_I2C_ADDRESS 18
-
-#if defined(CONFIG_DVB_DIB9000) || (defined(CONFIG_DVB_DIB9000_MODULE) && defined(MODULE))
-extern struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg);
-extern int dib9000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr);
-extern struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe);
-extern struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating);
-extern int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val);
-extern int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
-extern int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff);
-extern int dib9000_firmware_post_pll_init(struct dvb_frontend *fe);
-extern int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
-extern int dib9000_remove_slave_frontend(struct dvb_frontend *fe);
-extern struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
-extern struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe);
-extern int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c);
-extern int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed);
-#else
-static inline struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib9000_config *cfg)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline int dib9000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-static inline int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-
-static inline int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
-}
-#endif
-
-#endif
diff --git a/drivers/media/dvb/frontends/dibx000_common.c b/drivers/media/dvb/frontends/dibx000_common.c
deleted file mode 100644
index 43be7238311..00000000000
--- a/drivers/media/dvb/frontends/dibx000_common.c
+++ /dev/null
@@ -1,515 +0,0 @@
-#include <linux/i2c.h>
-#include <linux/mutex.h>
-#include <linux/module.h>
-
-#include "dibx000_common.h"
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
-
-#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiBX000: "); printk(args); printk("\n"); } } while (0)
-
-static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val)
-{
- int ret;
-
- if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
-
- mst->i2c_write_buffer[0] = (reg >> 8) & 0xff;
- mst->i2c_write_buffer[1] = reg & 0xff;
- mst->i2c_write_buffer[2] = (val >> 8) & 0xff;
- mst->i2c_write_buffer[3] = val & 0xff;
-
- memset(mst->msg, 0, sizeof(struct i2c_msg));
- mst->msg[0].addr = mst->i2c_addr;
- mst->msg[0].flags = 0;
- mst->msg[0].buf = mst->i2c_write_buffer;
- mst->msg[0].len = 4;
-
- ret = i2c_transfer(mst->i2c_adap, mst->msg, 1) != 1 ? -EREMOTEIO : 0;
- mutex_unlock(&mst->i2c_buffer_lock);
-
- return ret;
-}
-
-static u16 dibx000_read_word(struct dibx000_i2c_master *mst, u16 reg)
-{
- u16 ret;
-
- if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return 0;
- }
-
- mst->i2c_write_buffer[0] = reg >> 8;
- mst->i2c_write_buffer[1] = reg & 0xff;
-
- memset(mst->msg, 0, 2 * sizeof(struct i2c_msg));
- mst->msg[0].addr = mst->i2c_addr;
- mst->msg[0].flags = 0;
- mst->msg[0].buf = mst->i2c_write_buffer;
- mst->msg[0].len = 2;
- mst->msg[1].addr = mst->i2c_addr;
- mst->msg[1].flags = I2C_M_RD;
- mst->msg[1].buf = mst->i2c_read_buffer;
- mst->msg[1].len = 2;
-
- if (i2c_transfer(mst->i2c_adap, mst->msg, 2) != 2)
- dprintk("i2c read error on %d", reg);
-
- ret = (mst->i2c_read_buffer[0] << 8) | mst->i2c_read_buffer[1];
- mutex_unlock(&mst->i2c_buffer_lock);
-
- return ret;
-}
-
-static int dibx000_is_i2c_done(struct dibx000_i2c_master *mst)
-{
- int i = 100;
- u16 status;
-
- while (((status = dibx000_read_word(mst, mst->base_reg + 2)) & 0x0100) == 0 && --i > 0)
- ;
-
- /* i2c timed out */
- if (i == 0)
- return -EREMOTEIO;
-
- /* no acknowledge */
- if ((status & 0x0080) == 0)
- return -EREMOTEIO;
-
- return 0;
-}
-
-static int dibx000_master_i2c_write(struct dibx000_i2c_master *mst, struct i2c_msg *msg, u8 stop)
-{
- u16 data;
- u16 da;
- u16 i;
- u16 txlen = msg->len, len;
- const u8 *b = msg->buf;
-
- while (txlen) {
- dibx000_read_word(mst, mst->base_reg + 2);
-
- len = txlen > 8 ? 8 : txlen;
- for (i = 0; i < len; i += 2) {
- data = *b++ << 8;
- if (i+1 < len)
- data |= *b++;
- dibx000_write_word(mst, mst->base_reg, data);
- }
- da = (((u8) (msg->addr)) << 9) |
- (1 << 8) |
- (1 << 7) |
- (0 << 6) |
- (0 << 5) |
- ((len & 0x7) << 2) |
- (0 << 1) |
- (0 << 0);
-
- if (txlen == msg->len)
- da |= 1 << 5; /* start */
-
- if (txlen-len == 0 && stop)
- da |= 1 << 6; /* stop */
-
- dibx000_write_word(mst, mst->base_reg+1, da);
-
- if (dibx000_is_i2c_done(mst) != 0)
- return -EREMOTEIO;
- txlen -= len;
- }
-
- return 0;
-}
-
-static int dibx000_master_i2c_read(struct dibx000_i2c_master *mst, struct i2c_msg *msg)
-{
- u16 da;
- u8 *b = msg->buf;
- u16 rxlen = msg->len, len;
-
- while (rxlen) {
- len = rxlen > 8 ? 8 : rxlen;
- da = (((u8) (msg->addr)) << 9) |
- (1 << 8) |
- (1 << 7) |
- (0 << 6) |
- (0 << 5) |
- ((len & 0x7) << 2) |
- (1 << 1) |
- (0 << 0);
-
- if (rxlen == msg->len)
- da |= 1 << 5; /* start */
-
- if (rxlen-len == 0)
- da |= 1 << 6; /* stop */
- dibx000_write_word(mst, mst->base_reg+1, da);
-
- if (dibx000_is_i2c_done(mst) != 0)
- return -EREMOTEIO;
-
- rxlen -= len;
-
- while (len) {
- da = dibx000_read_word(mst, mst->base_reg);
- *b++ = (da >> 8) & 0xff;
- len--;
- if (len >= 1) {
- *b++ = da & 0xff;
- len--;
- }
- }
- }
-
- return 0;
-}
-
-int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed)
-{
- struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
-
- if (mst->device_rev < DIB7000MC && speed < 235)
- speed = 235;
- return dibx000_write_word(mst, mst->base_reg + 3, (u16)(60000 / speed));
-
-}
-EXPORT_SYMBOL(dibx000_i2c_set_speed);
-
-static u32 dibx000_i2c_func(struct i2c_adapter *adapter)
-{
- return I2C_FUNC_I2C;
-}
-
-static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst,
- enum dibx000_i2c_interface intf)
-{
- if (mst->device_rev > DIB3000MC && mst->selected_interface != intf) {
- dprintk("selecting interface: %d", intf);
- mst->selected_interface = intf;
- return dibx000_write_word(mst, mst->base_reg + 4, intf);
- }
- return 0;
-}
-
-static int dibx000_i2c_master_xfer_gpio12(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
-{
- struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
- int msg_index;
- int ret = 0;
-
- dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_1_2);
- for (msg_index = 0; msg_index < num; msg_index++) {
- if (msg[msg_index].flags & I2C_M_RD) {
- ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
- if (ret != 0)
- return 0;
- } else {
- ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
- if (ret != 0)
- return 0;
- }
- }
-
- return num;
-}
-
-static int dibx000_i2c_master_xfer_gpio34(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
-{
- struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
- int msg_index;
- int ret = 0;
-
- dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_3_4);
- for (msg_index = 0; msg_index < num; msg_index++) {
- if (msg[msg_index].flags & I2C_M_RD) {
- ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
- if (ret != 0)
- return 0;
- } else {
- ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
- if (ret != 0)
- return 0;
- }
- }
-
- return num;
-}
-
-static struct i2c_algorithm dibx000_i2c_master_gpio12_xfer_algo = {
- .master_xfer = dibx000_i2c_master_xfer_gpio12,
- .functionality = dibx000_i2c_func,
-};
-
-static struct i2c_algorithm dibx000_i2c_master_gpio34_xfer_algo = {
- .master_xfer = dibx000_i2c_master_xfer_gpio34,
- .functionality = dibx000_i2c_func,
-};
-
-static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4],
- u8 addr, int onoff)
-{
- u16 val;
-
-
- if (onoff)
- val = addr << 8; // bit 7 = use master or not, if 0, the gate is open
- else
- val = 1 << 7;
-
- if (mst->device_rev > DIB7000)
- val <<= 1;
-
- tx[0] = (((mst->base_reg + 1) >> 8) & 0xff);
- tx[1] = ((mst->base_reg + 1) & 0xff);
- tx[2] = val >> 8;
- tx[3] = val & 0xff;
-
- return 0;
-}
-
-static int dibx000_i2c_gated_gpio67_xfer(struct i2c_adapter *i2c_adap,
- struct i2c_msg msg[], int num)
-{
- struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
- int ret;
-
- if (num > 32) {
- dprintk("%s: too much I2C message to be transmitted (%i).\
- Maximum is 32", __func__, num);
- return -ENOMEM;
- }
-
- dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_6_7);
-
- if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
-
- memset(mst->msg, 0, sizeof(struct i2c_msg) * (2 + num));
-
- /* open the gate */
- dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[0], msg[0].addr, 1);
- mst->msg[0].addr = mst->i2c_addr;
- mst->msg[0].buf = &mst->i2c_write_buffer[0];
- mst->msg[0].len = 4;
-
- memcpy(&mst->msg[1], msg, sizeof(struct i2c_msg) * num);
-
- /* close the gate */
- dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[4], 0, 0);
- mst->msg[num + 1].addr = mst->i2c_addr;
- mst->msg[num + 1].buf = &mst->i2c_write_buffer[4];
- mst->msg[num + 1].len = 4;
-
- ret = (i2c_transfer(mst->i2c_adap, mst->msg, 2 + num) == 2 + num ?
- num : -EIO);
-
- mutex_unlock(&mst->i2c_buffer_lock);
- return ret;
-}
-
-static struct i2c_algorithm dibx000_i2c_gated_gpio67_algo = {
- .master_xfer = dibx000_i2c_gated_gpio67_xfer,
- .functionality = dibx000_i2c_func,
-};
-
-static int dibx000_i2c_gated_tuner_xfer(struct i2c_adapter *i2c_adap,
- struct i2c_msg msg[], int num)
-{
- struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
- int ret;
-
- if (num > 32) {
- dprintk("%s: too much I2C message to be transmitted (%i).\
- Maximum is 32", __func__, num);
- return -ENOMEM;
- }
-
- dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_TUNER);
-
- if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
- memset(mst->msg, 0, sizeof(struct i2c_msg) * (2 + num));
-
- /* open the gate */
- dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[0], msg[0].addr, 1);
- mst->msg[0].addr = mst->i2c_addr;
- mst->msg[0].buf = &mst->i2c_write_buffer[0];
- mst->msg[0].len = 4;
-
- memcpy(&mst->msg[1], msg, sizeof(struct i2c_msg) * num);
-
- /* close the gate */
- dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[4], 0, 0);
- mst->msg[num + 1].addr = mst->i2c_addr;
- mst->msg[num + 1].buf = &mst->i2c_write_buffer[4];
- mst->msg[num + 1].len = 4;
-
- ret = (i2c_transfer(mst->i2c_adap, mst->msg, 2 + num) == 2 + num ?
- num : -EIO);
- mutex_unlock(&mst->i2c_buffer_lock);
- return ret;
-}
-
-static struct i2c_algorithm dibx000_i2c_gated_tuner_algo = {
- .master_xfer = dibx000_i2c_gated_tuner_xfer,
- .functionality = dibx000_i2c_func,
-};
-
-struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst,
- enum dibx000_i2c_interface intf,
- int gating)
-{
- struct i2c_adapter *i2c = NULL;
-
- switch (intf) {
- case DIBX000_I2C_INTERFACE_TUNER:
- if (gating)
- i2c = &mst->gated_tuner_i2c_adap;
- break;
- case DIBX000_I2C_INTERFACE_GPIO_1_2:
- if (!gating)
- i2c = &mst->master_i2c_adap_gpio12;
- break;
- case DIBX000_I2C_INTERFACE_GPIO_3_4:
- if (!gating)
- i2c = &mst->master_i2c_adap_gpio34;
- break;
- case DIBX000_I2C_INTERFACE_GPIO_6_7:
- if (gating)
- i2c = &mst->master_i2c_adap_gpio67;
- break;
- default:
- printk(KERN_ERR "DiBX000: incorrect I2C interface selected\n");
- break;
- }
-
- return i2c;
-}
-
-EXPORT_SYMBOL(dibx000_get_i2c_adapter);
-
-void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst)
-{
- /* initialize the i2c-master by closing the gate */
- u8 tx[4];
- struct i2c_msg m = {.addr = mst->i2c_addr,.buf = tx,.len = 4 };
-
- dibx000_i2c_gate_ctrl(mst, tx, 0, 0);
- i2c_transfer(mst->i2c_adap, &m, 1);
- mst->selected_interface = 0xff; // the first time force a select of the I2C
- dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_TUNER);
-}
-
-EXPORT_SYMBOL(dibx000_reset_i2c_master);
-
-static int i2c_adapter_init(struct i2c_adapter *i2c_adap,
- struct i2c_algorithm *algo, const char *name,
- struct dibx000_i2c_master *mst)
-{
- strncpy(i2c_adap->name, name, sizeof(i2c_adap->name));
- i2c_adap->algo = algo;
- i2c_adap->algo_data = NULL;
- i2c_set_adapdata(i2c_adap, mst);
- if (i2c_add_adapter(i2c_adap) < 0)
- return -ENODEV;
- return 0;
-}
-
-int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev,
- struct i2c_adapter *i2c_adap, u8 i2c_addr)
-{
- int ret;
-
- mutex_init(&mst->i2c_buffer_lock);
- if (mutex_lock_interruptible(&mst->i2c_buffer_lock) < 0) {
- dprintk("could not acquire lock");
- return -EINVAL;
- }
- memset(mst->msg, 0, sizeof(struct i2c_msg));
- mst->msg[0].addr = i2c_addr >> 1;
- mst->msg[0].flags = 0;
- mst->msg[0].buf = mst->i2c_write_buffer;
- mst->msg[0].len = 4;
-
- mst->device_rev = device_rev;
- mst->i2c_adap = i2c_adap;
- mst->i2c_addr = i2c_addr >> 1;
-
- if (device_rev == DIB7000P || device_rev == DIB8000)
- mst->base_reg = 1024;
- else
- mst->base_reg = 768;
-
- mst->gated_tuner_i2c_adap.dev.parent = mst->i2c_adap->dev.parent;
- if (i2c_adapter_init
- (&mst->gated_tuner_i2c_adap, &dibx000_i2c_gated_tuner_algo,
- "DiBX000 tuner I2C bus", mst) != 0)
- printk(KERN_ERR
- "DiBX000: could not initialize the tuner i2c_adapter\n");
-
- mst->master_i2c_adap_gpio12.dev.parent = mst->i2c_adap->dev.parent;
- if (i2c_adapter_init
- (&mst->master_i2c_adap_gpio12, &dibx000_i2c_master_gpio12_xfer_algo,
- "DiBX000 master GPIO12 I2C bus", mst) != 0)
- printk(KERN_ERR
- "DiBX000: could not initialize the master i2c_adapter\n");
-
- mst->master_i2c_adap_gpio34.dev.parent = mst->i2c_adap->dev.parent;
- if (i2c_adapter_init
- (&mst->master_i2c_adap_gpio34, &dibx000_i2c_master_gpio34_xfer_algo,
- "DiBX000 master GPIO34 I2C bus", mst) != 0)
- printk(KERN_ERR
- "DiBX000: could not initialize the master i2c_adapter\n");
-
- mst->master_i2c_adap_gpio67.dev.parent = mst->i2c_adap->dev.parent;
- if (i2c_adapter_init
- (&mst->master_i2c_adap_gpio67, &dibx000_i2c_gated_gpio67_algo,
- "DiBX000 master GPIO67 I2C bus", mst) != 0)
- printk(KERN_ERR
- "DiBX000: could not initialize the master i2c_adapter\n");
-
- /* initialize the i2c-master by closing the gate */
- dibx000_i2c_gate_ctrl(mst, mst->i2c_write_buffer, 0, 0);
-
- ret = (i2c_transfer(i2c_adap, mst->msg, 1) == 1);
- mutex_unlock(&mst->i2c_buffer_lock);
-
- return ret;
-}
-
-EXPORT_SYMBOL(dibx000_init_i2c_master);
-
-void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst)
-{
- i2c_del_adapter(&mst->gated_tuner_i2c_adap);
- i2c_del_adapter(&mst->master_i2c_adap_gpio12);
- i2c_del_adapter(&mst->master_i2c_adap_gpio34);
- i2c_del_adapter(&mst->master_i2c_adap_gpio67);
-}
-EXPORT_SYMBOL(dibx000_exit_i2c_master);
-
-
-u32 systime(void)
-{
- struct timespec t;
-
- t = current_kernel_time();
- return (t.tv_sec * 10000) + (t.tv_nsec / 100000);
-}
-EXPORT_SYMBOL(systime);
-
-MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
-MODULE_DESCRIPTION("Common function the DiBcom demodulator family");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h
deleted file mode 100644
index 5f484881d7b..00000000000
--- a/drivers/media/dvb/frontends/dibx000_common.h
+++ /dev/null
@@ -1,280 +0,0 @@
-#ifndef DIBX000_COMMON_H
-#define DIBX000_COMMON_H
-
-enum dibx000_i2c_interface {
- DIBX000_I2C_INTERFACE_TUNER = 0,
- DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
- DIBX000_I2C_INTERFACE_GPIO_3_4 = 2,
- DIBX000_I2C_INTERFACE_GPIO_6_7 = 3
-};
-
-struct dibx000_i2c_master {
-#define DIB3000MC 1
-#define DIB7000 2
-#define DIB7000P 11
-#define DIB7000MC 12
-#define DIB8000 13
- u16 device_rev;
-
- enum dibx000_i2c_interface selected_interface;
-
-/* struct i2c_adapter tuner_i2c_adap; */
- struct i2c_adapter gated_tuner_i2c_adap;
- struct i2c_adapter master_i2c_adap_gpio12;
- struct i2c_adapter master_i2c_adap_gpio34;
- struct i2c_adapter master_i2c_adap_gpio67;
-
- struct i2c_adapter *i2c_adap;
- u8 i2c_addr;
-
- u16 base_reg;
-
- /* for the I2C transfer */
- struct i2c_msg msg[34];
- u8 i2c_write_buffer[8];
- u8 i2c_read_buffer[2];
- struct mutex i2c_buffer_lock;
-};
-
-extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
- u16 device_rev, struct i2c_adapter *i2c_adap,
- u8 i2c_addr);
-extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
- *mst,
- enum dibx000_i2c_interface
- intf, int gating);
-extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
-extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
-extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed);
-
-extern u32 systime(void);
-
-#define BAND_LBAND 0x01
-#define BAND_UHF 0x02
-#define BAND_VHF 0x04
-#define BAND_SBAND 0x08
-#define BAND_FM 0x10
-#define BAND_CBAND 0x20
-
-#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
- (freq_kHz) <= 115000 ? BAND_FM : \
- (freq_kHz) <= 250000 ? BAND_VHF : \
- (freq_kHz) <= 863000 ? BAND_UHF : \
- (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
-
-struct dibx000_agc_config {
- /* defines the capabilities of this AGC-setting - using the BAND_-defines */
- u8 band_caps;
-
- u16 setup;
-
- u16 inv_gain;
- u16 time_stabiliz;
-
- u8 alpha_level;
- u16 thlock;
-
- u8 wbd_inv;
- u16 wbd_ref;
- u8 wbd_sel;
- u8 wbd_alpha;
-
- u16 agc1_max;
- u16 agc1_min;
- u16 agc2_max;
- u16 agc2_min;
-
- u8 agc1_pt1;
- u8 agc1_pt2;
- u8 agc1_pt3;
-
- u8 agc1_slope1;
- u8 agc1_slope2;
-
- u8 agc2_pt1;
- u8 agc2_pt2;
-
- u8 agc2_slope1;
- u8 agc2_slope2;
-
- u8 alpha_mant;
- u8 alpha_exp;
-
- u8 beta_mant;
- u8 beta_exp;
-
- u8 perform_agc_softsplit;
-
- struct {
- u16 min;
- u16 max;
- u16 min_thres;
- u16 max_thres;
- } split;
-};
-
-struct dibx000_bandwidth_config {
- u32 internal;
- u32 sampling;
-
- u8 pll_prediv;
- u8 pll_ratio;
- u8 pll_range;
- u8 pll_reset;
- u8 pll_bypass;
-
- u8 enable_refdiv;
- u8 bypclk_div;
- u8 IO_CLK_en_core;
- u8 ADClkSrc;
- u8 modulo;
-
- u16 sad_cfg;
-
- u32 ifreq;
- u32 timf;
-
- u32 xtal_hz;
-};
-
-enum dibx000_adc_states {
- DIBX000_SLOW_ADC_ON = 0,
- DIBX000_SLOW_ADC_OFF,
- DIBX000_ADC_ON,
- DIBX000_ADC_OFF,
- DIBX000_VBG_ENABLE,
- DIBX000_VBG_DISABLE,
-};
-
-#define BANDWIDTH_TO_KHZ(v) ((v) / 1000)
-#define BANDWIDTH_TO_HZ(v) ((v) * 1000)
-
-/* Chip output mode. */
-#define OUTMODE_HIGH_Z 0
-#define OUTMODE_MPEG2_PAR_GATED_CLK 1
-#define OUTMODE_MPEG2_PAR_CONT_CLK 2
-#define OUTMODE_MPEG2_SERIAL 7
-#define OUTMODE_DIVERSITY 4
-#define OUTMODE_MPEG2_FIFO 5
-#define OUTMODE_ANALOG_ADC 6
-
-#define INPUT_MODE_OFF 0x11
-#define INPUT_MODE_DIVERSITY 0x12
-#define INPUT_MODE_MPEG 0x13
-
-enum frontend_tune_state {
- CT_TUNER_START = 10,
- CT_TUNER_STEP_0,
- CT_TUNER_STEP_1,
- CT_TUNER_STEP_2,
- CT_TUNER_STEP_3,
- CT_TUNER_STEP_4,
- CT_TUNER_STEP_5,
- CT_TUNER_STEP_6,
- CT_TUNER_STEP_7,
- CT_TUNER_STOP,
-
- CT_AGC_START = 20,
- CT_AGC_STEP_0,
- CT_AGC_STEP_1,
- CT_AGC_STEP_2,
- CT_AGC_STEP_3,
- CT_AGC_STEP_4,
- CT_AGC_STOP,
-
- CT_DEMOD_START = 30,
- CT_DEMOD_STEP_1,
- CT_DEMOD_STEP_2,
- CT_DEMOD_STEP_3,
- CT_DEMOD_STEP_4,
- CT_DEMOD_STEP_5,
- CT_DEMOD_STEP_6,
- CT_DEMOD_STEP_7,
- CT_DEMOD_STEP_8,
- CT_DEMOD_STEP_9,
- CT_DEMOD_STEP_10,
- CT_DEMOD_SEARCH_NEXT = 41,
- CT_DEMOD_STEP_LOCKED,
- CT_DEMOD_STOP,
-
- CT_DONE = 100,
- CT_SHUTDOWN,
-
-};
-
-struct dvb_frontend_parametersContext {
-#define CHANNEL_STATUS_PARAMETERS_UNKNOWN 0x01
-#define CHANNEL_STATUS_PARAMETERS_SET 0x02
- u8 status;
- u32 tune_time_estimation[2];
- s32 tps_available;
- u16 tps[9];
-};
-
-#define FE_STATUS_TUNE_FAILED 0
-#define FE_STATUS_TUNE_TIMED_OUT -1
-#define FE_STATUS_TUNE_TIME_TOO_SHORT -2
-#define FE_STATUS_TUNE_PENDING -3
-#define FE_STATUS_STD_SUCCESS -4
-#define FE_STATUS_FFT_SUCCESS -5
-#define FE_STATUS_DEMOD_SUCCESS -6
-#define FE_STATUS_LOCKED -7
-#define FE_STATUS_DATA_LOCKED -8
-
-#define FE_CALLBACK_TIME_NEVER 0xffffffff
-
-#define ABS(x) ((x < 0) ? (-x) : (x))
-
-#define DATA_BUS_ACCESS_MODE_8BIT 0x01
-#define DATA_BUS_ACCESS_MODE_16BIT 0x02
-#define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10
-
-struct dibGPIOFunction {
-#define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1
-#define BOARD_GPIO_COMPONENT_DEMOD 2
- u8 component;
-
-#define BOARD_GPIO_FUNCTION_BOARD_ON 1
-#define BOARD_GPIO_FUNCTION_BOARD_OFF 2
-#define BOARD_GPIO_FUNCTION_COMPONENT_ON 3
-#define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4
-#define BOARD_GPIO_FUNCTION_SUBBAND_PWM 5
-#define BOARD_GPIO_FUNCTION_SUBBAND_GPIO 6
- u8 function;
-
-/* mask, direction and value are used specify which GPIO to change GPIO0
- * is LSB and possible GPIO31 is MSB. The same bit-position as in the
- * mask is used for the direction and the value. Direction == 1 is OUT,
- * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN
- * value has no meaning.
- *
- * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be
- * used to do the PWM. Direction gives the PWModulator to be used.
- * Value gives the PWM value in device-dependent scale.
- */
- u32 mask;
- u32 direction;
- u32 value;
-};
-
-#define MAX_NB_SUBBANDS 8
-struct dibSubbandSelection {
- u8 size; /* Actual number of subbands. */
- struct {
- u16 f_mhz;
- struct dibGPIOFunction gpio;
- } subband[MAX_NB_SUBBANDS];
-};
-
-#define DEMOD_TIMF_SET 0x00
-#define DEMOD_TIMF_GET 0x01
-#define DEMOD_TIMF_UPDATE 0x02
-
-#define MPEG_ON_DIBTX 1
-#define DIV_ON_DIBTX 2
-#define ADC_ON_DIBTX 3
-#define DEMOUT_ON_HOSTBUS 4
-#define DIBTX_ON_HOSTBUS 5
-#define MPEG_ON_HOSTBUS 6
-
-#endif
diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h
deleted file mode 100644
index 216c8c3702f..00000000000
--- a/drivers/media/dvb/frontends/drxd.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * drxd.h: DRXD DVB-T demodulator driver
- *
- * Copyright (C) 2005-2007 Micronas
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 only, as published by the Free Software Foundation.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef _DRXD_H_
-#define _DRXD_H_
-
-#include <linux/types.h>
-#include <linux/i2c.h>
-
-struct drxd_config {
- u8 index;
-
- u8 pll_address;
- u8 pll_type;
-#define DRXD_PLL_NONE 0
-#define DRXD_PLL_DTT7520X 1
-#define DRXD_PLL_MT3X0823 2
-
- u32 clock;
- u8 insert_rs_byte;
-
- u8 demod_address;
- u8 demoda_address;
- u8 demod_revision;
-
- /* If the tuner is not behind an i2c gate, be sure to flip this bit
- or else the i2c bus could get wedged */
- u8 disable_i2c_gate_ctrl;
-
- u32 IF;
- s16(*osc_deviation) (void *priv, s16 dev, int flag);
-};
-
-#if defined(CONFIG_DVB_DRXD) || \
- (defined(CONFIG_DVB_DRXD_MODULE) && defined(MODULE))
-extern
-struct dvb_frontend *drxd_attach(const struct drxd_config *config,
- void *priv, struct i2c_adapter *i2c,
- struct device *dev);
-#else
-static inline
-struct dvb_frontend *drxd_attach(const struct drxd_config *config,
- void *priv, struct i2c_adapter *i2c,
- struct device *dev)
-{
- printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n",
- __func__);
- return NULL;
-}
-#endif
-
-extern int drxd_config_i2c(struct dvb_frontend *, int);
-#endif
diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c
deleted file mode 100644
index 5418b0b1dad..00000000000
--- a/drivers/media/dvb/frontends/drxd_firm.c
+++ /dev/null
@@ -1,929 +0,0 @@
-/*
- * drxd_firm.c : DRXD firmware tables
- *
- * Copyright (C) 2006-2007 Micronas
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 only, as published by the Free Software Foundation.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- */
-
-/* TODO: generate this file with a script from a settings file */
-
-/* Contains A2 firmware version: 1.4.2
- * Contains B1 firmware version: 3.3.33
- * Contains settings from driver 1.4.23
-*/
-
-#include "drxd_firm.h"
-
-#define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
-#define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
-
-/* Is written via block write, must be little endian */
-#define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
-
-#define WRBLOCK(a, l) ADDRESS(a), LENGTH(l)
-#define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d)
-
-#define END_OF_TABLE 0xFF, 0xFF, 0xFF, 0xFF
-
-/* HI firmware patches */
-
-#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
-#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
-
-u8 DRXD_InitAtomicRead[] = {
- WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0x60, 0x04, /* r0rami.dt -> ring.xba; */
- 0x61, 0x04, /* r0rami.dt -> ring.xad; */
- 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
- 0x40, 0x00, /* (long immediate) */
- 0x64, 0x04, /* r0rami.dt -> ring.len; */
- 0x65, 0x04, /* r0rami.dt -> ring.ctl; */
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0x38, 0x00, /* 0 -> jumps.ad; */
- END_OF_TABLE
-};
-
-/* Pins D0 and D1 of the parallel MPEG output can be used
- to set the I2C address of a device. */
-
-#define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
-#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
-
-/* D0 Version */
-u8 DRXD_HiI2cPatch_1[] = {
- WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
- 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
- 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
- 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
- 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
- 0x23, 0x00, /* &data -> ring.iad; */
- 0x24, 0x00, /* 0 -> ring.len; */
- 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0x42, 0x00, /* &data+1 -> w0ram.ad; */
- 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
- 0x63, 0x00, /* &data+1 -> ring.iad; */
- 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
- 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
- 0x23, 0x00, /* &data -> ring.iad; */
- 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0x42, 0x00, /* &data+1 -> w0ram.ad; */
- 0x0F, 0x04, /* r0ram.dt -> and.op; */
- 0x1C, 0x06, /* reg0.dt -> and.tr; */
- 0xCF, 0x04, /* and.rs -> add.op; */
- 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
- 0xD0, 0x04, /* add.rs -> add.tr; */
- 0xC8, 0x04, /* add.rs -> reg0.dt; */
- 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
- 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
- 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
- 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
- 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
- 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
- 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
- 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
-
- WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
- (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
- WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
- (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
- WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
- (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
- WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
- (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
-
- /* Force quick and dirty reset */
- WR16(B_HI_CT_REG_COMM_STATE__A, 0),
- END_OF_TABLE
-};
-
-/* D0,D1 Version */
-u8 DRXD_HiI2cPatch_3[] = {
- WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
- 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
- 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
- 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
- 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
- 0x23, 0x00, /* &data -> ring.iad; */
- 0x24, 0x00, /* 0 -> ring.len; */
- 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0x42, 0x00, /* &data+1 -> w0ram.ad; */
- 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
- 0x63, 0x00, /* &data+1 -> ring.iad; */
- 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
- 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
- 0x23, 0x00, /* &data -> ring.iad; */
- 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
- 0x26, 0x00, /* 0 -> ring.rdy; */
- 0x42, 0x00, /* &data+1 -> w0ram.ad; */
- 0x0F, 0x04, /* r0ram.dt -> and.op; */
- 0x1C, 0x06, /* reg0.dt -> and.tr; */
- 0xCF, 0x04, /* and.rs -> add.op; */
- 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
- 0xD0, 0x04, /* add.rs -> add.tr; */
- 0xC8, 0x04, /* add.rs -> reg0.dt; */
- 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
- 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
- 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
- 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x01, 0x00, /* 0 -> w0rami.dt; */
- 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
- 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
- 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
- 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
- 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
-
- WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
- (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
- WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
- (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
- WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
- (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
- WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
- (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
-
- /* Force quick and dirty reset */
- WR16(B_HI_CT_REG_COMM_STATE__A, 0),
- END_OF_TABLE
-};
-
-u8 DRXD_ResetCEFR[] = {
- WRBLOCK(CE_REG_FR_TREAL00__A, 57),
- 0x52, 0x00, /* CE_REG_FR_TREAL00__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL01__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG01__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL02__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG02__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL03__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG03__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL04__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG04__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL05__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG05__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL06__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG06__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL07__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG07__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL08__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG08__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL09__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG09__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL10__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG10__A */
- 0x52, 0x00, /* CE_REG_FR_TREAL11__A */
- 0x00, 0x00, /* CE_REG_FR_TIMAG11__A */
-
- 0x52, 0x00, /* CE_REG_FR_MID_TAP__A */
-
- 0x0B, 0x00, /* CE_REG_FR_SQS_G00__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G01__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G02__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G03__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G04__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G05__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G06__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G07__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G08__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G09__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G10__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G11__A */
- 0x0B, 0x00, /* CE_REG_FR_SQS_G12__A */
-
- 0xFF, 0x01, /* CE_REG_FR_RIO_G00__A */
- 0x90, 0x01, /* CE_REG_FR_RIO_G01__A */
- 0x0B, 0x01, /* CE_REG_FR_RIO_G02__A */
- 0xC8, 0x00, /* CE_REG_FR_RIO_G03__A */
- 0xA0, 0x00, /* CE_REG_FR_RIO_G04__A */
- 0x85, 0x00, /* CE_REG_FR_RIO_G05__A */
- 0x72, 0x00, /* CE_REG_FR_RIO_G06__A */
- 0x64, 0x00, /* CE_REG_FR_RIO_G07__A */
- 0x59, 0x00, /* CE_REG_FR_RIO_G08__A */
- 0x50, 0x00, /* CE_REG_FR_RIO_G09__A */
- 0x49, 0x00, /* CE_REG_FR_RIO_G10__A */
-
- 0x10, 0x00, /* CE_REG_FR_MODE__A */
- 0x78, 0x00, /* CE_REG_FR_SQS_TRH__A */
- 0x00, 0x00, /* CE_REG_FR_RIO_GAIN__A */
- 0x00, 0x02, /* CE_REG_FR_BYPASS__A */
- 0x0D, 0x00, /* CE_REG_FR_PM_SET__A */
- 0x07, 0x00, /* CE_REG_FR_ERR_SH__A */
- 0x04, 0x00, /* CE_REG_FR_MAN_SH__A */
- 0x06, 0x00, /* CE_REG_FR_TAP_SH__A */
-
- END_OF_TABLE
-};
-
-u8 DRXD_InitFEA2_1[] = {
- WRBLOCK(FE_AD_REG_PD__A, 3),
- 0x00, 0x00, /* FE_AD_REG_PD__A */
- 0x01, 0x00, /* FE_AD_REG_INVEXT__A */
- 0x00, 0x00, /* FE_AD_REG_CLKNEG__A */
-
- WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2),
- 0x10, 0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
- 0x10, 0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
-
- WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2),
- 0x0E, 0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
- 0x00, 0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
-
- WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5),
- 0x04, 0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
- 0x1F, 0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
- 0x00, 0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
- 0x00, 0x00, /* FE_AG_REG_EGC_FLA_INC__A */
- 0x00, 0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
-
- WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2),
- 0xFF, 0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
- 0x00, 0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
-
- WRBLOCK(FE_AG_REG_IND_WIN__A, 29),
- 0x00, 0x00, /* FE_AG_REG_IND_WIN__A */
- 0x05, 0x00, /* FE_AG_REG_IND_THD_LOL__A */
- 0x0F, 0x00, /* FE_AG_REG_IND_THD_HIL__A */
- 0x00, 0x00, /* FE_AG_REG_IND_DEL__A don't care */
- 0x1E, 0x00, /* FE_AG_REG_IND_PD1_WRI__A */
- 0x0C, 0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
- 0x00, 0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
- 0x00, 0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
- 0x00, 0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
- 0x01, 0x00, /* FE_AG_REG_PDC_SET_LVL__A */
- 0x02, 0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
- 0x00, 0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
- 0xFF, 0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
- 0xFF, 0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
- 0x00, 0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
- 0x00, 0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
- 0x02, 0x00, /* FE_AG_REG_PDC_MAX__A */
- 0x0C, 0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
- 0x00, 0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
- 0x00, 0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
- 0x00, 0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
- 0x22, 0x00, /* FE_AG_REG_TGC_SET_LVL__A */
- 0x15, 0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
- 0x00, 0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
- 0x01, 0x00, /* FE_AG_REG_TGC_FLA_STP__A */
- 0x0A, 0x00, /* FE_AG_REG_TGC_SLO_STP__A */
- 0x00, 0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
- 0x10, 0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
- 0x10, 0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
-
- WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2),
- 0x00, 0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
- 0x00, 0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
-
- WRBLOCK(FE_FD_REG_SCL__A, 3),
- 0x05, 0x00, /* FE_FD_REG_SCL__A */
- 0x03, 0x00, /* FE_FD_REG_MAX_LEV__A */
- 0x05, 0x00, /* FE_FD_REG_NR__A */
-
- WRBLOCK(FE_CF_REG_SCL__A, 5),
- 0x16, 0x00, /* FE_CF_REG_SCL__A */
- 0x04, 0x00, /* FE_CF_REG_MAX_LEV__A */
- 0x06, 0x00, /* FE_CF_REG_NR__A */
- 0x00, 0x00, /* FE_CF_REG_IMP_VAL__A */
- 0x01, 0x00, /* FE_CF_REG_MEAS_VAL__A */
-
- WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2),
- 0x00, 0x08, /* FE_CU_REG_FRM_CNT_RST__A */
- 0x00, 0x00, /* FE_CU_REG_FRM_CNT_STR__A */
-
- END_OF_TABLE
-};
-
- /* with PGA */
-/* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */
- /* without PGA */
-/* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */
-/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
-/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
-
-u8 DRXD_InitFEA2_2[] = {
- WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
- WR16(FE_AG_REG_FGM_WRI__A, 48),
- /* Activate measurement, activate scale */
- WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
-
- WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
- WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
- WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
- WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
- WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
- WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
- WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
- WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
-
- END_OF_TABLE
-};
-
-u8 DRXD_InitFEB1_1[] = {
- WR16(B_FE_AD_REG_PD__A, 0x0000),
- WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
- WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
- WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
- WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
- WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35),
- WR16(B_FE_AG_REG_IND_WIN__A, 0),
- WR16(B_FE_AG_REG_IND_THD_LOL__A, 8),
- WR16(B_FE_AG_REG_IND_THD_HIL__A, 8),
- WR16(B_FE_CF_REG_IMP_VAL__A, 1),
- WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
- END_OF_TABLE
-};
-
- /* with PGA */
-/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
- /* without PGA */
-/* WR16(B_FE_AG_REG_AG_PGA_MODE__A ,
- B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
- /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
-/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
-
-u8 DRXD_InitFEB1_2[] = {
- WR16(B_FE_COMM_EXEC__A, 0x0001),
-
- /* RF-AGC setup */
- WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
- WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
- WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
- WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
- WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
- WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
- WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
- WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
- WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
- WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
- WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
-
- WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
- WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000),
- WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1),
- END_OF_TABLE
-};
-
-u8 DRXD_InitCPA2[] = {
- WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
- 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */
- 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */
-
- WRBLOCK(CP_REG_RT_ANG_INC0__A, 4),
- 0x00, 0x00, /* CP_REG_RT_ANG_INC0__A */
- 0x00, 0x00, /* CP_REG_RT_ANG_INC1__A */
- 0x03, 0x00, /* CP_REG_RT_DETECT_ENA__A */
- 0x03, 0x00, /* CP_REG_RT_DETECT_TRH__A */
-
- WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5),
- 0x32, 0x00, /* CP_REG_AC_NEXP_OFFS__A */
- 0x62, 0x00, /* CP_REG_AC_AVER_POW__A */
- 0x82, 0x00, /* CP_REG_AC_MAX_POW__A */
- 0x26, 0x00, /* CP_REG_AC_WEIGHT_MAN__A */
- 0x0F, 0x00, /* CP_REG_AC_WEIGHT_EXP__A */
-
- WRBLOCK(CP_REG_AC_AMP_MODE__A, 2),
- 0x02, 0x00, /* CP_REG_AC_AMP_MODE__A */
- 0x01, 0x00, /* CP_REG_AC_AMP_FIX__A */
-
- WR16(CP_REG_INTERVAL__A, 0x0005),
- WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
- WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
-
- WR16(CP_REG_COMM_EXEC__A, 0x0001),
- END_OF_TABLE
-};
-
-u8 DRXD_InitCPB1[] = {
- WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
- WR16(B_CP_COMM_EXEC__A, 0x0001),
- END_OF_TABLE
-};
-
-u8 DRXD_InitCEA2[] = {
- WRBLOCK(CE_REG_AVG_POW__A, 4),
- 0x62, 0x00, /* CE_REG_AVG_POW__A */
- 0x78, 0x00, /* CE_REG_MAX_POW__A */
- 0x62, 0x00, /* CE_REG_ATT__A */
- 0x17, 0x00, /* CE_REG_NRED__A */
-
- WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2),
- 0x07, 0x00, /* CE_REG_NE_ERR_SELECT__A */
- 0xEB, 0xFF, /* CE_REG_NE_TD_CAL__A */
-
- WRBLOCK(CE_REG_NE_MIXAVG__A, 2),
- 0x06, 0x00, /* CE_REG_NE_MIXAVG__A */
- 0x00, 0x00, /* CE_REG_NE_NUPD_OFS__A */
-
- WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2),
- 0x00, 0x00, /* CE_REG_PE_NEXP_OFFS__A */
- 0x00, 0x00, /* CE_REG_PE_TIMESHIFT__A */
-
- WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3),
- 0x00, 0x01, /* CE_REG_TP_A0_TAP_NEW__A */
- 0x01, 0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
- 0x0E, 0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */
-
- WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3),
- 0x00, 0x00, /* CE_REG_TP_A1_TAP_NEW__A */
- 0x01, 0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
- 0x0A, 0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */
-
- WRBLOCK(CE_REG_FI_SHT_INCR__A, 2),
- 0x12, 0x00, /* CE_REG_FI_SHT_INCR__A */
- 0x0C, 0x00, /* CE_REG_FI_EXP_NORM__A */
-
- WRBLOCK(CE_REG_IR_INPUTSEL__A, 3),
- 0x00, 0x00, /* CE_REG_IR_INPUTSEL__A */
- 0x00, 0x00, /* CE_REG_IR_STARTPOS__A */
- 0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */
-
- WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
-
- END_OF_TABLE
-};
-
-u8 DRXD_InitCEB1[] = {
- WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
- WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
-
- END_OF_TABLE
-};
-
-u8 DRXD_InitEQA2[] = {
- WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
- 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */
- 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */
- 0x06, 0x00, /* EQ_REG_OT_CSI_STEP__A */
- 0x02, 0x00, /* EQ_REG_OT_CSI_OFFSET__A */
-
- WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
- WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
- WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)),
- WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
- WR16(EQ_REG_COMM_EXEC__A, 0x0001),
- END_OF_TABLE
-};
-
-u8 DRXD_InitEQB1[] = {
- WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
- END_OF_TABLE
-};
-
-u8 DRXD_ResetECRAM[] = {
- /* Reset packet sync bytes in EC_VD ram */
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
-
- /* Reset packet sync bytes in EC_RS ram */
- WR16(EC_RS_EC_RAM__A, 0x0000),
- WR16(EC_RS_EC_RAM__A + 204, 0x0000),
- END_OF_TABLE
-};
-
-u8 DRXD_InitECA2[] = {
- WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
- 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */
- 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */
- 0x01, 0x00, /* EC_SB_REG_SMB_TGL__A */
- 0x7F, 0x00, /* EC_SB_REG_SNR_HI__A */
- 0x7F, 0x00, /* EC_SB_REG_SNR_MID__A */
- 0x7F, 0x00, /* EC_SB_REG_SNR_LO__A */
-
- WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2),
- 0x00, 0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
- DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */
-
- WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
- 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
- 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
- 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
- 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
- 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
-
- WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
- 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
- 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
-
- WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
- 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
- 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
- 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
- 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
- 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
- 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
- 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
-
- WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
- 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
- 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
-
- WR16(EC_SB_REG_CSI_OFS__A, 0x0001),
- WR16(EC_VD_REG_FORCE__A, 0x0002),
- WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001),
- WR16(EC_VD_REG_RLK_ENA__A, 0x0001),
- WR16(EC_OD_REG_SYNC__A, 0x0664),
- WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
- WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
- /* Output zero on monitorbus pads, power saving */
- WR16(EC_OC_REG_OCR_MON_UOS__A,
- (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
- EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
- EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
- WR16(EC_OC_REG_OCR_MON_WRI__A,
- EC_OC_REG_OCR_MON_WRI_INIT),
-
-/* CHK_ERROR(ResetECRAM(demod)); */
- /* Reset packet sync bytes in EC_VD ram */
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
-
- /* Reset packet sync bytes in EC_RS ram */
- WR16(EC_RS_EC_RAM__A, 0x0000),
- WR16(EC_RS_EC_RAM__A + 204, 0x0000),
-
- WR16(EC_SB_REG_COMM_EXEC__A, 0x0001),
- WR16(EC_VD_REG_COMM_EXEC__A, 0x0001),
- WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
- WR16(EC_RS_REG_COMM_EXEC__A, 0x0001),
- END_OF_TABLE
-};
-
-u8 DRXD_InitECB1[] = {
- WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
- WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
- WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
- WR16(B_EC_SB_REG_CSI_LO__A, 0x000c),
- WR16(B_EC_SB_REG_CSI_HI__A, 0x0018),
- WR16(B_EC_SB_REG_SNR_HI__A, 0x007f),
- WR16(B_EC_SB_REG_SNR_MID__A, 0x007f),
- WR16(B_EC_SB_REG_SNR_LO__A, 0x007f),
-
- WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002),
- WR16(B_EC_OC_REG_DTO_PER__A, 0x0006),
- WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001),
- WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000),
- WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D),
- WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000),
-
- /* Needed because shadow registers do not have correct default value */
- WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000),
- WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000),
- WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000),
- WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0),
- WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000),
- WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0),
- WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000),
- WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0),
-
- WR16(B_EC_OD_REG_SYNC__A, 0x0664),
- WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000),
-
-/* CHK_ERROR(ResetECRAM(demod)); */
- /* Reset packet sync bytes in EC_VD ram */
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
-
- /* Reset packet sync bytes in EC_RS ram */
- WR16(EC_RS_EC_RAM__A, 0x0000),
- WR16(EC_RS_EC_RAM__A + 204, 0x0000),
-
- WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001),
- WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001),
- WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001),
- WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001),
- END_OF_TABLE
-};
-
-u8 DRXD_ResetECA2[] = {
-
- WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
- WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
-
- WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
- 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
- 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
- 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
- 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
- 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
-
- WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
- 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
- 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
-
- WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
- 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
- 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
- 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
- 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
- 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
- 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
- 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
-
- WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
- 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
- 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
-
- WR16(EC_OD_REG_SYNC__A, 0x0664),
- WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
- WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
- /* Output zero on monitorbus pads, power saving */
- WR16(EC_OC_REG_OCR_MON_UOS__A,
- (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
- EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
- EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
- EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
- WR16(EC_OC_REG_OCR_MON_WRI__A,
- EC_OC_REG_OCR_MON_WRI_INIT),
-
-/* CHK_ERROR(ResetECRAM(demod)); */
- /* Reset packet sync bytes in EC_VD ram */
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
- WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
-
- /* Reset packet sync bytes in EC_RS ram */
- WR16(EC_RS_EC_RAM__A, 0x0000),
- WR16(EC_RS_EC_RAM__A + 204, 0x0000),
-
- WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
- END_OF_TABLE
-};
-
-u8 DRXD_InitSC[] = {
- WR16(SC_COMM_EXEC__A, 0),
- WR16(SC_COMM_STATE__A, 0),
-
-#ifdef COMPILE_FOR_QT
- WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
-#endif
-
- /* SC is not started, this is done in SetChannels() */
- END_OF_TABLE
-};
-
-/* Diversity settings */
-
-u8 DRXD_InitDiversityFront[] = {
- /* Start demod ********* RF in , diversity out **************************** */
- WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
- B_SC_RA_RAM_CONFIG_FREQSCAN__M),
-
- WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
- WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
- WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
- WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
- WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
- WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
- WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
- WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
-
- WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
- WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
- WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
- WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
- WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
- WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
-
- WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
- WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
- WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
- WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
- WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
-
- WR16(B_CC_REG_DIVERSITY__A, 0x0001),
- WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
- WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
- B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
-
- /* 0x2a ), *//* CE to PASS mux */
-
- END_OF_TABLE
-};
-
-u8 DRXD_InitDiversityEnd[] = {
- /* End demod *********** combining RF in and diversity in, MPEG TS out **** */
- /* disable near/far; switch on timing slave mode */
- WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
- B_SC_RA_RAM_CONFIG_FREQSCAN__M |
- B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
- B_SC_RA_RAM_CONFIG_SLAVE__M |
- B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
-/* MV from CtrlDiversity */
- ),
-#ifdef DRXDDIV_SRMM_SLAVING
- WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
- WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
-#else
- WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
- WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
-#endif
-
- WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
- WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
- WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
- WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
- WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
- WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
-
- WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
- WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
- WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
- WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
- WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
- WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
-
- WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
- WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
- WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
- WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
- WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
-
- WR16(B_CC_REG_DIVERSITY__A, 0x0001),
- END_OF_TABLE
-};
-
-u8 DRXD_DisableDiversity[] = {
- WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
- WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
- WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
- B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
- WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
- B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
- WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
- B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
- WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
- B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
- WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
- B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
- WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
- B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
-
- WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
- B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
- WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
- B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
- WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
- B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
- WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
- B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
- WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
- B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
- WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
- B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
-
- WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
- WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
- WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
- WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
- WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
-
- WR16(B_CC_REG_DIVERSITY__A, 0x0000),
- WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */
-
- END_OF_TABLE
-};
-
-u8 DRXD_StartDiversityFront[] = {
- /* Start demod, RF in and diversity out, no combining */
- WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
- WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
- WR16(B_FE_AD_REG_INVEXT__A, 0x0),
- WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */
- WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
- B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
-
- WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
-
- END_OF_TABLE
-};
-
-u8 DRXD_StartDiversityEnd[] = {
- /* End demod, combining RF in and diversity in, MPEG TS out */
- WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */
- WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */
- WR16(B_CP_REG_BR_STR_DEL__A, 10), /* apperently no mb delay matching is best */
-
- WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
- B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
- B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
-
- END_OF_TABLE
-};
-
-u8 DRXD_DiversityDelay8MHZ[] = {
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50),
- END_OF_TABLE
-};
-
-u8 DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */
-{
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50),
- WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50),
- END_OF_TABLE
-};
diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h
deleted file mode 100644
index 41597e89941..00000000000
--- a/drivers/media/dvb/frontends/drxd_firm.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * drxd_firm.h
- *
- * Copyright (C) 2006-2007 Micronas
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 only, as published by the Free Software Foundation.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef _DRXD_FIRM_H_
-#define _DRXD_FIRM_H_
-
-#include <linux/types.h>
-#include "drxd_map_firm.h"
-
-#define VERSION_MAJOR 1
-#define VERSION_MINOR 4
-#define VERSION_PATCH 23
-
-#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
-
-#define DRXD_MAX_RETRIES (1000)
-#define HI_I2C_DELAY 84
-#define HI_I2C_BRIDGE_DELAY 750
-
-#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */
-#define EQ_TD_TPS_PWR_QPSK 0x016a
-#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195
-#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195
-#define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E
-#define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE
-#define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F
-#define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F
-#define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8
-#define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D
-
-#define DRXD_DEF_AG_PWD_CONSUMER 0x000E
-#define DRXD_DEF_AG_PWD_PRO 0x0000
-#define DRXD_DEF_AG_AGC_SIO 0x0000
-
-#define DRXD_FE_CTRL_MAX 1023
-
-#define DRXD_OSCDEV_DO_SCAN (16)
-
-#define DRXD_OSCDEV_DONT_SCAN (0)
-
-#define DRXD_OSCDEV_STEP (275)
-
-#define DRXD_SCAN_TIMEOUT (650)
-
-#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
-#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
-#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
-
-#define IRLEN_COARSE_8K (10)
-#define IRLEN_FINE_8K (10)
-#define IRLEN_COARSE_2K (7)
-#define IRLEN_FINE_2K (9)
-#define DIFF_INVALID (511)
-#define DIFF_TARGET (4)
-#define DIFF_MARGIN (1)
-
-extern u8 DRXD_InitAtomicRead[];
-extern u8 DRXD_HiI2cPatch_1[];
-extern u8 DRXD_HiI2cPatch_3[];
-
-extern u8 DRXD_InitSC[];
-
-extern u8 DRXD_ResetCEFR[];
-extern u8 DRXD_InitFEA2_1[];
-extern u8 DRXD_InitFEA2_2[];
-extern u8 DRXD_InitCPA2[];
-extern u8 DRXD_InitCEA2[];
-extern u8 DRXD_InitEQA2[];
-extern u8 DRXD_InitECA2[];
-extern u8 DRXD_ResetECA2[];
-extern u8 DRXD_ResetECRAM[];
-
-extern u8 DRXD_A2_microcode[];
-extern u32 DRXD_A2_microcode_length;
-
-extern u8 DRXD_InitFEB1_1[];
-extern u8 DRXD_InitFEB1_2[];
-extern u8 DRXD_InitCPB1[];
-extern u8 DRXD_InitCEB1[];
-extern u8 DRXD_InitEQB1[];
-extern u8 DRXD_InitECB1[];
-
-extern u8 DRXD_InitDiversityFront[];
-extern u8 DRXD_InitDiversityEnd[];
-extern u8 DRXD_DisableDiversity[];
-extern u8 DRXD_StartDiversityFront[];
-extern u8 DRXD_StartDiversityEnd[];
-
-extern u8 DRXD_DiversityDelay8MHZ[];
-extern u8 DRXD_DiversityDelay6MHZ[];
-
-extern u8 DRXD_B1_microcode[];
-extern u32 DRXD_B1_microcode_length;
-
-#endif
diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c
deleted file mode 100644
index f380eb43e9d..00000000000
--- a/drivers/media/dvb/frontends/drxd_hard.c
+++ /dev/null
@@ -1,2992 +0,0 @@
-/*
- * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
- *
- * Copyright (C) 2003-2007 Micronas
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 only, as published by the Free Software Foundation.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/firmware.h>
-#include <linux/i2c.h>
-#include <asm/div64.h>
-
-#include "dvb_frontend.h"
-#include "drxd.h"
-#include "drxd_firm.h"
-
-#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
-#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
-
-#define CHUNK_SIZE 48
-
-#define DRX_I2C_RMW 0x10
-#define DRX_I2C_BROADCAST 0x20
-#define DRX_I2C_CLEARCRC 0x80
-#define DRX_I2C_SINGLE_MASTER 0xC0
-#define DRX_I2C_MODEFLAGS 0xC0
-#define DRX_I2C_FLAGS 0xF0
-
-#ifndef SIZEOF_ARRAY
-#define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
-#endif
-
-#define DEFAULT_LOCK_TIMEOUT 1100
-
-#define DRX_CHANNEL_AUTO 0
-#define DRX_CHANNEL_HIGH 1
-#define DRX_CHANNEL_LOW 2
-
-#define DRX_LOCK_MPEG 1
-#define DRX_LOCK_FEC 2
-#define DRX_LOCK_DEMOD 4
-
-/****************************************************************************/
-
-enum CSCDState {
- CSCD_INIT = 0,
- CSCD_SET,
- CSCD_SAVED
-};
-
-enum CDrxdState {
- DRXD_UNINITIALIZED = 0,
- DRXD_STOPPED,
- DRXD_STARTED
-};
-
-enum AGC_CTRL_MODE {
- AGC_CTRL_AUTO = 0,
- AGC_CTRL_USER,
- AGC_CTRL_OFF
-};
-
-enum OperationMode {
- OM_Default,
- OM_DVBT_Diversity_Front,
- OM_DVBT_Diversity_End
-};
-
-struct SCfgAgc {
- enum AGC_CTRL_MODE ctrlMode;
- u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
- u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
- u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
- u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
- u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
-
- u16 R1;
- u16 R2;
- u16 R3;
-};
-
-struct SNoiseCal {
- int cpOpt;
- short cpNexpOfs;
- short tdCal2k;
- short tdCal8k;
-};
-
-enum app_env {
- APPENV_STATIC = 0,
- APPENV_PORTABLE = 1,
- APPENV_MOBILE = 2
-};
-
-enum EIFFilter {
- IFFILTER_SAW = 0,
- IFFILTER_DISCRETE = 1
-};
-
-struct drxd_state {
- struct dvb_frontend frontend;
- struct dvb_frontend_ops ops;
- struct dtv_frontend_properties props;
-
- const struct firmware *fw;
- struct device *dev;
-
- struct i2c_adapter *i2c;
- void *priv;
- struct drxd_config config;
-
- int i2c_access;
- int init_done;
- struct mutex mutex;
-
- u8 chip_adr;
- u16 hi_cfg_timing_div;
- u16 hi_cfg_bridge_delay;
- u16 hi_cfg_wakeup_key;
- u16 hi_cfg_ctrl;
-
- u16 intermediate_freq;
- u16 osc_clock_freq;
-
- enum CSCDState cscd_state;
- enum CDrxdState drxd_state;
-
- u16 sys_clock_freq;
- s16 osc_clock_deviation;
- u16 expected_sys_clock_freq;
-
- u16 insert_rs_byte;
- u16 enable_parallel;
-
- int operation_mode;
-
- struct SCfgAgc if_agc_cfg;
- struct SCfgAgc rf_agc_cfg;
-
- struct SNoiseCal noise_cal;
-
- u32 fe_fs_add_incr;
- u32 org_fe_fs_add_incr;
- u16 current_fe_if_incr;
-
- u16 m_FeAgRegAgPwd;
- u16 m_FeAgRegAgAgcSio;
-
- u16 m_EcOcRegOcModeLop;
- u16 m_EcOcRegSncSncLvl;
- u8 *m_InitAtomicRead;
- u8 *m_HiI2cPatch;
-
- u8 *m_ResetCEFR;
- u8 *m_InitFE_1;
- u8 *m_InitFE_2;
- u8 *m_InitCP;
- u8 *m_InitCE;
- u8 *m_InitEQ;
- u8 *m_InitSC;
- u8 *m_InitEC;
- u8 *m_ResetECRAM;
- u8 *m_InitDiversityFront;
- u8 *m_InitDiversityEnd;
- u8 *m_DisableDiversity;
- u8 *m_StartDiversityFront;
- u8 *m_StartDiversityEnd;
-
- u8 *m_DiversityDelay8MHZ;
- u8 *m_DiversityDelay6MHZ;
-
- u8 *microcode;
- u32 microcode_length;
-
- int type_A;
- int PGA;
- int diversity;
- int tuner_mirrors;
-
- enum app_env app_env_default;
- enum app_env app_env_diversity;
-
-};
-
-/****************************************************************************/
-/* I2C **********************************************************************/
-/****************************************************************************/
-
-static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
-{
- struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
-
- if (i2c_transfer(adap, &msg, 1) != 1)
- return -1;
- return 0;
-}
-
-static int i2c_read(struct i2c_adapter *adap,
- u8 adr, u8 *msg, int len, u8 *answ, int alen)
-{
- struct i2c_msg msgs[2] = {
- {
- .addr = adr, .flags = 0,
- .buf = msg, .len = len
- }, {
- .addr = adr, .flags = I2C_M_RD,
- .buf = answ, .len = alen
- }
- };
- if (i2c_transfer(adap, msgs, 2) != 2)
- return -1;
- return 0;
-}
-
-static inline u32 MulDiv32(u32 a, u32 b, u32 c)
-{
- u64 tmp64;
-
- tmp64 = (u64)a * (u64)b;
- do_div(tmp64, c);
-
- return (u32) tmp64;
-}
-
-static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
-{
- u8 adr = state->config.demod_address;
- u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
- flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
- };
- u8 mm2[2];
- if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
- return -1;
- if (data)
- *data = mm2[0] | (mm2[1] << 8);
- return mm2[0] | (mm2[1] << 8);
-}
-
-static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
-{
- u8 adr = state->config.demod_address;
- u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
- flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
- };
- u8 mm2[4];
-
- if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
- return -1;
- if (data)
- *data =
- mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
- return 0;
-}
-
-static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
-{
- u8 adr = state->config.demod_address;
- u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
- flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
- data & 0xff, (data >> 8) & 0xff
- };
-
- if (i2c_write(state->i2c, adr, mm, 6) < 0)
- return -1;
- return 0;
-}
-
-static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
-{
- u8 adr = state->config.demod_address;
- u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
- flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
- data & 0xff, (data >> 8) & 0xff,
- (data >> 16) & 0xff, (data >> 24) & 0xff
- };
-
- if (i2c_write(state->i2c, adr, mm, 8) < 0)
- return -1;
- return 0;
-}
-
-static int write_chunk(struct drxd_state *state,
- u32 reg, u8 *data, u32 len, u8 flags)
-{
- u8 adr = state->config.demod_address;
- u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
- flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
- };
- int i;
-
- for (i = 0; i < len; i++)
- mm[4 + i] = data[i];
- if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
- printk(KERN_ERR "error in write_chunk\n");
- return -1;
- }
- return 0;
-}
-
-static int WriteBlock(struct drxd_state *state,
- u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
-{
- while (BlockSize > 0) {
- u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
-
- if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
- return -1;
- pBlock += Chunk;
- Address += (Chunk >> 1);
- BlockSize -= Chunk;
- }
- return 0;
-}
-
-static int WriteTable(struct drxd_state *state, u8 * pTable)
-{
- int status = 0;
-
- if (pTable == NULL)
- return 0;
-
- while (!status) {
- u16 Length;
- u32 Address = pTable[0] | (pTable[1] << 8) |
- (pTable[2] << 16) | (pTable[3] << 24);
-
- if (Address == 0xFFFFFFFF)
- break;
- pTable += sizeof(u32);
-
- Length = pTable[0] | (pTable[1] << 8);
- pTable += sizeof(u16);
- if (!Length)
- break;
- status = WriteBlock(state, Address, Length * 2, pTable, 0);
- pTable += (Length * 2);
- }
- return status;
-}
-
-/****************************************************************************/
-/****************************************************************************/
-/****************************************************************************/
-
-static int ResetCEFR(struct drxd_state *state)
-{
- return WriteTable(state, state->m_ResetCEFR);
-}
-
-static int InitCP(struct drxd_state *state)
-{
- return WriteTable(state, state->m_InitCP);
-}
-
-static int InitCE(struct drxd_state *state)
-{
- int status;
- enum app_env AppEnv = state->app_env_default;
-
- do {
- status = WriteTable(state, state->m_InitCE);
- if (status < 0)
- break;
-
- if (state->operation_mode == OM_DVBT_Diversity_Front ||
- state->operation_mode == OM_DVBT_Diversity_End) {
- AppEnv = state->app_env_diversity;
- }
- if (AppEnv == APPENV_STATIC) {
- status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
- if (status < 0)
- break;
- } else if (AppEnv == APPENV_PORTABLE) {
- status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
- if (status < 0)
- break;
- } else if (AppEnv == APPENV_MOBILE && state->type_A) {
- status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
- if (status < 0)
- break;
- } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
- status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
- if (status < 0)
- break;
- }
-
- /* start ce */
- status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
- if (status < 0)
- break;
- } while (0);
- return status;
-}
-
-static int StopOC(struct drxd_state *state)
-{
- int status = 0;
- u16 ocSyncLvl = 0;
- u16 ocModeLop = state->m_EcOcRegOcModeLop;
- u16 dtoIncLop = 0;
- u16 dtoIncHip = 0;
-
- do {
- /* Store output configuration */
- status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
- if (status < 0)
- break;
- /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
- state->m_EcOcRegSncSncLvl = ocSyncLvl;
- /* m_EcOcRegOcModeLop = ocModeLop; */
-
- /* Flush FIFO (byte-boundary) at fixed rate */
- status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
- if (status < 0)
- break;
- status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
- if (status < 0)
- break;
- status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
- if (status < 0)
- break;
- status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
- if (status < 0)
- break;
- ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
- ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
- status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
- if (status < 0)
- break;
- status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
- if (status < 0)
- break;
-
- msleep(1);
- /* Output pins to '0' */
- status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
- if (status < 0)
- break;
-
- /* Force the OC out of sync */
- ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
- status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
- if (status < 0)
- break;
- ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
- ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
- ocModeLop |= 0x2; /* Magically-out-of-sync */
- status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
- if (status < 0)
- break;
- status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
- if (status < 0)
- break;
- status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
- if (status < 0)
- break;
- } while (0);
-
- return status;
-}
-
-static int StartOC(struct drxd_state *state)
-{
- int status = 0;
-
- do {
- /* Stop OC */
- status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
- if (status < 0)
- break;
-
- /* Restore output configuration */
- status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
- if (status < 0)
- break;
- status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
- if (status < 0)
- break;
-
- /* Output pins active again */
- status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
- if (status < 0)
- break;
-
- /* Start OC */
- status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
- if (status < 0)
- break;
- } while (0);
- return status;
-}
-
-static int InitEQ(struct drxd_state *state)
-{
- return WriteTable(state, state->m_InitEQ);
-}
-
-static int InitEC(struct drxd_state *state)
-{
- return WriteTable(state, state->m_InitEC);
-}
-
-static int InitSC(struct drxd_state *state)
-{
- return WriteTable(state, state->m_InitSC);
-}
-
-static int InitAtomicRead(struct drxd_state *state)
-{
- return WriteTable(state, state->m_InitAtomicRead);
-}
-
-static int CorrectSysClockDeviation(struct drxd_state *state);
-
-static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
-{
- u16 ScRaRamLock = 0;
- const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
- SC_RA_RAM_LOCK_FEC__M |
- SC_RA_RAM_LOCK_DEMOD__M);
- const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
- SC_RA_RAM_LOCK_DEMOD__M);
- const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
-
- int status;
-
- *pLockStatus = 0;
-
- status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
- if (status < 0) {
- printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
- return status;
- }
-
- if (state->drxd_state != DRXD_STARTED)
- return 0;
-
- if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
- *pLockStatus |= DRX_LOCK_MPEG;
- CorrectSysClockDeviation(state);
- }
-
- if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
- *pLockStatus |= DRX_LOCK_FEC;
-
- if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
- *pLockStatus |= DRX_LOCK_DEMOD;
- return 0;
-}
-
-/****************************************************************************/
-
-static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
-{
- int status;
-
- if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
- return -1;
-
- if (cfg->ctrlMode == AGC_CTRL_USER) {
- do {
- u16 FeAgRegPm1AgcWri;
- u16 FeAgRegAgModeLop;
-
- status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
- if (status < 0)
- break;
- FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
- FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
- status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
- if (status < 0)
- break;
-
- FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
- FE_AG_REG_PM1_AGC_WRI__M);
- status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
- if (status < 0)
- break;
- } while (0);
- } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
- if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
- ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
- ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
- ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
- )
- return -1;
- do {
- u16 FeAgRegAgModeLop;
- u16 FeAgRegEgcSetLvl;
- u16 slope, offset;
-
- /* == Mode == */
-
- status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
- if (status < 0)
- break;
- FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
- FeAgRegAgModeLop |=
- FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
- status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
- if (status < 0)
- break;
-
- /* == Settle level == */
-
- FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
- FE_AG_REG_EGC_SET_LVL__M);
- status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
- if (status < 0)
- break;
-
- /* == Min/Max == */
-
- slope = (u16) ((cfg->maxOutputLevel -
- cfg->minOutputLevel) / 2);
- offset = (u16) ((cfg->maxOutputLevel +
- cfg->minOutputLevel) / 2 - 511);
-
- status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
- if (status < 0)
- break;
- status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
- if (status < 0)
- break;
-
- /* == Speed == */
- {
- const u16 maxRur = 8;
- const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
- const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
- 17, 18, 18, 19,
- 20, 21, 22, 23,
- 24, 26, 27, 28,
- 29, 31
- };
-
- u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
- (maxRur + 1);
- u16 fineSpeed = (u16) (cfg->speed -
- ((cfg->speed /
- fineSteps) *
- fineSteps));
- u16 invRurCount = (u16) (cfg->speed /
- fineSteps);
- u16 rurCount;
- if (invRurCount > maxRur) {
- rurCount = 0;
- fineSpeed += fineSteps;
- } else {
- rurCount = maxRur - invRurCount;
- }
-
- /*
- fastInc = default *
- (2^(fineSpeed/fineSteps))
- => range[default...2*default>
- slowInc = default *
- (2^(fineSpeed/fineSteps))
- */
- {
- u16 fastIncrDec =
- fastIncrDecLUT[fineSpeed /
- ((fineSteps /
- (14 + 1)) + 1)];
- u16 slowIncrDec =
- slowIncrDecLUT[fineSpeed /
- (fineSteps /
- (3 + 1))];
-
- status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
- if (status < 0)
- break;
- status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
- if (status < 0)
- break;
- status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
- if (status < 0)
- break;
- status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
- if (status < 0)
- break;
- status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
- if (status < 0)
- break;
- }
- }
- } while (0);
-
- } else {
- /* No OFF mode for IF control */
- return -1;
- }
- return status;
-}
-
-static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
-{
- int status = 0;
-
- if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
- return -1;
-
- if (cfg->ctrlMode == AGC_CTRL_USER) {
- do {
- u16 AgModeLop = 0;
- u16 level = (cfg->outputLevel);
-
- if (level == DRXD_FE_CTRL_MAX)
- level++;
-
- status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
- if (status < 0)
- break;
-
- /*==== Mode ====*/
-
- /* Powerdown PD2, WRI source */
- state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
- state->m_FeAgRegAgPwd |=
- FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
- status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
- if (status < 0)
- break;
-
- status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
- if (status < 0)
- break;
- AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
- FE_AG_REG_AG_MODE_LOP_MODE_E__M));
- AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
- FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
- status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
- if (status < 0)
- break;
-
- /* enable AGC2 pin */
- {
- u16 FeAgRegAgAgcSio = 0;
- status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
- if (status < 0)
- break;
- FeAgRegAgAgcSio &=
- ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
- FeAgRegAgAgcSio |=
- FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
- status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
- if (status < 0)
- break;
- }
-
- } while (0);
- } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
- u16 AgModeLop = 0;
-
- do {
- u16 level;
- /* Automatic control */
- /* Powerup PD2, AGC2 as output, TGC source */
- (state->m_FeAgRegAgPwd) &=
- ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
- (state->m_FeAgRegAgPwd) |=
- FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
- status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
- if (status < 0)
- break;
-
- status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
- if (status < 0)
- break;
- AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
- FE_AG_REG_AG_MODE_LOP_MODE_E__M));
- AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
- FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
- status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
- if (status < 0)
- break;
- /* Settle level */
- level = (((cfg->settleLevel) >> 4) &
- FE_AG_REG_TGC_SET_LVL__M);
- status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
- if (status < 0)
- break;
-
- /* Min/max: don't care */
-
- /* Speed: TODO */
-
- /* enable AGC2 pin */
- {
- u16 FeAgRegAgAgcSio = 0;
- status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
- if (status < 0)
- break;
- FeAgRegAgAgcSio &=
- ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
- FeAgRegAgAgcSio |=
- FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
- status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
- if (status < 0)
- break;
- }
-
- } while (0);
- } else {
- u16 AgModeLop = 0;
-
- do {
- /* No RF AGC control */
- /* Powerdown PD2, AGC2 as output, WRI source */
- (state->m_FeAgRegAgPwd) &=
- ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
- (state->m_FeAgRegAgPwd) |=
- FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
- status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
- if (status < 0)
- break;
-
- status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
- if (status < 0)
- break;
- AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
- FE_AG_REG_AG_MODE_LOP_MODE_E__M));
- AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
- FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
- status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
- if (status < 0)
- break;
-
- /* set FeAgRegAgAgcSio AGC2 (RF) as input */
- {
- u16 FeAgRegAgAgcSio = 0;
- status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
- if (status < 0)
- break;
- FeAgRegAgAgcSio &=
- ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
- FeAgRegAgAgcSio |=
- FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
- status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
- if (status < 0)
- break;
- }
- } while (0);
- }
- return status;
-}
-
-static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
-{
- int status = 0;
-
- *pValue = 0;
- if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
- u16 Value;
- status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
- Value &= FE_AG_REG_GC1_AGC_DAT__M;
- if (status >= 0) {
- /* 3.3V
- |
- R1
- |
- Vin - R3 - * -- Vout
- |
- R2
- |
- GND
- */
- u32 R1 = state->if_agc_cfg.R1;
- u32 R2 = state->if_agc_cfg.R2;
- u32 R3 = state->if_agc_cfg.R3;
-
- u32 Vmax, Rpar, Vmin, Vout;
-
- if (R2 == 0 && (R1 == 0 || R3 == 0))
- return 0;
-
- Vmax = (3300 * R2) / (R1 + R2);
- Rpar = (R2 * R3) / (R3 + R2);
- Vmin = (3300 * Rpar) / (R1 + Rpar);
- Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
-
- *pValue = Vout;
- }
- }
- return status;
-}
-
-static int load_firmware(struct drxd_state *state, const char *fw_name)
-{
- const struct firmware *fw;
-
- if (request_firmware(&fw, fw_name, state->dev) < 0) {
- printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
- return -EIO;
- }
-
- state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
- if (state->microcode == NULL) {
- release_firmware(fw);
- printk(KERN_ERR "drxd: firmware load failure: no memory\n");
- return -ENOMEM;
- }
-
- state->microcode_length = fw->size;
- release_firmware(fw);
- return 0;
-}
-
-static int DownloadMicrocode(struct drxd_state *state,
- const u8 *pMCImage, u32 Length)
-{
- u8 *pSrc;
- u32 Address;
- u16 nBlocks;
- u16 BlockSize;
- u32 offset = 0;
- int i, status = 0;
-
- pSrc = (u8 *) pMCImage;
- /* We're not using Flags */
- /* Flags = (pSrc[0] << 8) | pSrc[1]; */
- pSrc += sizeof(u16);
- offset += sizeof(u16);
- nBlocks = (pSrc[0] << 8) | pSrc[1];
- pSrc += sizeof(u16);
- offset += sizeof(u16);
-
- for (i = 0; i < nBlocks; i++) {
- Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
- (pSrc[2] << 8) | pSrc[3];
- pSrc += sizeof(u32);
- offset += sizeof(u32);
-
- BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
- pSrc += sizeof(u16);
- offset += sizeof(u16);
-
- /* We're not using Flags */
- /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
- pSrc += sizeof(u16);
- offset += sizeof(u16);
-
- /* We're not using BlockCRC */
- /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
- pSrc += sizeof(u16);
- offset += sizeof(u16);
-
- status = WriteBlock(state, Address, BlockSize,
- pSrc, DRX_I2C_CLEARCRC);
- if (status < 0)
- break;
- pSrc += BlockSize;
- offset += BlockSize;
- }
-
- return status;
-}
-
-static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
-{
- u32 nrRetries = 0;
- u16 waitCmd;
- int status;
-
- status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
- if (status < 0)
- return status;
-
- do {
- nrRetries += 1;
- if (nrRetries > DRXD_MAX_RETRIES) {
- status = -1;
- break;
- };
- status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
- } while (waitCmd != 0);
-
- if (status >= 0)
- status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
- return status;
-}
-
-static int HI_CfgCommand(struct drxd_state *state)
-{
- int status = 0;
-
- mutex_lock(&state->mutex);
- Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
- Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
- Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
- Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
- Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
-
- Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
-
- if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
- HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
- status = Write16(state, HI_RA_RAM_SRV_CMD__A,
- HI_RA_RAM_SRV_CMD_CONFIG, 0);
- else
- status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
- mutex_unlock(&state->mutex);
- return status;
-}
-
-static int InitHI(struct drxd_state *state)
-{
- state->hi_cfg_wakeup_key = (state->chip_adr);
- /* port/bridge/power down ctrl */
- state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
- return HI_CfgCommand(state);
-}
-
-static int HI_ResetCommand(struct drxd_state *state)
-{
- int status;
-
- mutex_lock(&state->mutex);
- status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
- HI_RA_RAM_SRV_RST_KEY_ACT, 0);
- if (status == 0)
- status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
- mutex_unlock(&state->mutex);
- msleep(1);
- return status;
-}
-
-static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
-{
- state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
- if (bEnableBridge)
- state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
- else
- state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
-
- return HI_CfgCommand(state);
-}
-
-#define HI_TR_WRITE 0x9
-#define HI_TR_READ 0xA
-#define HI_TR_READ_WRITE 0xB
-#define HI_TR_BROADCAST 0x4
-
-#if 0
-static int AtomicReadBlock(struct drxd_state *state,
- u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
-{
- int status;
- int i = 0;
-
- /* Parameter check */
- if ((!pData) || ((DataSize & 1) != 0))
- return -1;
-
- mutex_lock(&state->mutex);
-
- do {
- /* Instruct HI to read n bytes */
- /* TODO use proper names forthese egisters */
- status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
- if (status < 0)
- break;
- status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
- if (status < 0)
- break;
- status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
- if (status < 0)
- break;
- status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
- if (status < 0)
- break;
- status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
- if (status < 0)
- break;
-
- status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
- if (status < 0)
- break;
-
- } while (0);
-
- if (status >= 0) {
- for (i = 0; i < (DataSize / 2); i += 1) {
- u16 word;
-
- status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
- &word, 0);
- if (status < 0)
- break;
- pData[2 * i] = (u8) (word & 0xFF);
- pData[(2 * i) + 1] = (u8) (word >> 8);
- }
- }
- mutex_unlock(&state->mutex);
- return status;
-}
-
-static int AtomicReadReg32(struct drxd_state *state,
- u32 Addr, u32 *pData, u8 Flags)
-{
- u8 buf[sizeof(u32)];
- int status;
-
- if (!pData)
- return -1;
- status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
- *pData = (((u32) buf[0]) << 0) +
- (((u32) buf[1]) << 8) +
- (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
- return status;
-}
-#endif
-
-static int StopAllProcessors(struct drxd_state *state)
-{
- return Write16(state, HI_COMM_EXEC__A,
- SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
-}
-
-static int EnableAndResetMB(struct drxd_state *state)
-{
- if (state->type_A) {
- /* disable? monitor bus observe @ EC_OC */
- Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
- }
-
- /* do inverse broadcast, followed by explicit write to HI */
- Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
- Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
- return 0;
-}
-
-static int InitCC(struct drxd_state *state)
-{
- if (state->osc_clock_freq == 0 ||
- state->osc_clock_freq > 20000 ||
- (state->osc_clock_freq % 4000) != 0) {
- printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
- return -1;
- }
-
- Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
- Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
- CC_REG_PLL_MODE_PUMP_CUR_12, 0);
- Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
- Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
- Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
-
- return 0;
-}
-
-static int ResetECOD(struct drxd_state *state)
-{
- int status = 0;
-
- if (state->type_A)
- status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
- else
- status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
-
- if (!(status < 0))
- status = WriteTable(state, state->m_ResetECRAM);
- if (!(status < 0))
- status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
- return status;
-}
-
-/* Configure PGA switch */
-
-static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
-{
- int status;
- u16 AgModeLop = 0;
- u16 AgModeHip = 0;
- do {
- if (pgaSwitch) {
- /* PGA on */
- /* fine gain */
- status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
- if (status < 0)
- break;
- AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
- AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
- status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
- if (status < 0)
- break;
-
- /* coarse gain */
- status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
- if (status < 0)
- break;
- AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
- AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
- status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
- if (status < 0)
- break;
-
- /* enable fine and coarse gain, enable AAF,
- no ext resistor */
- status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
- if (status < 0)
- break;
- } else {
- /* PGA off, bypass */
-
- /* fine gain */
- status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
- if (status < 0)
- break;
- AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
- AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
- status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
- if (status < 0)
- break;
-
- /* coarse gain */
- status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
- if (status < 0)
- break;
- AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
- AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
- status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
- if (status < 0)
- break;
-
- /* disable fine and coarse gain, enable AAF,
- no ext resistor */
- status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
- if (status < 0)
- break;
- }
- } while (0);
- return status;
-}
-
-static int InitFE(struct drxd_state *state)
-{
- int status;
-
- do {
- status = WriteTable(state, state->m_InitFE_1);
- if (status < 0)
- break;
-
- if (state->type_A) {
- status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
- FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
- 0);
- } else {
- if (state->PGA)
- status = SetCfgPga(state, 0);
- else
- status =
- Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
- B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
- 0);
- }
-
- if (status < 0)
- break;
- status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
- if (status < 0)
- break;
-
- status = WriteTable(state, state->m_InitFE_2);
- if (status < 0)
- break;
-
- } while (0);
-
- return status;
-}
-
-static int InitFT(struct drxd_state *state)
-{
- /*
- norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
- SC stuff
- */
- return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
-}
-
-static int SC_WaitForReady(struct drxd_state *state)
-{
- u16 curCmd;
- int i;
-
- for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
- int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
- if (status == 0 || curCmd == 0)
- return status;
- }
- return -1;
-}
-
-static int SC_SendCommand(struct drxd_state *state, u16 cmd)
-{
- int status = 0;
- u16 errCode;
-
- Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
- SC_WaitForReady(state);
-
- Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
-
- if (errCode == 0xFFFF) {
- printk(KERN_ERR "Command Error\n");
- status = -1;
- }
-
- return status;
-}
-
-static int SC_ProcStartCommand(struct drxd_state *state,
- u16 subCmd, u16 param0, u16 param1)
-{
- int status = 0;
- u16 scExec;
-
- mutex_lock(&state->mutex);
- do {
- Read16(state, SC_COMM_EXEC__A, &scExec, 0);
- if (scExec != 1) {
- status = -1;
- break;
- }
- SC_WaitForReady(state);
- Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
- Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
- Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
-
- SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
- } while (0);
- mutex_unlock(&state->mutex);
- return status;
-}
-
-static int SC_SetPrefParamCommand(struct drxd_state *state,
- u16 subCmd, u16 param0, u16 param1)
-{
- int status;
-
- mutex_lock(&state->mutex);
- do {
- status = SC_WaitForReady(state);
- if (status < 0)
- break;
- status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
- if (status < 0)
- break;
- status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
- if (status < 0)
- break;
- status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
- if (status < 0)
- break;
-
- status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
- if (status < 0)
- break;
- } while (0);
- mutex_unlock(&state->mutex);
- return status;
-}
-
-#if 0
-static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
-{
- int status = 0;
-
- mutex_lock(&state->mutex);
- do {
- status = SC_WaitForReady(state);
- if (status < 0)
- break;
- status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
- if (status < 0)
- break;
- status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
- if (status < 0)
- break;
- } while (0);
- mutex_unlock(&state->mutex);
- return status;
-}
-#endif
-
-static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
-{
- int status;
-
- do {
- u16 EcOcRegIprInvMpg = 0;
- u16 EcOcRegOcModeLop = 0;
- u16 EcOcRegOcModeHip = 0;
- u16 EcOcRegOcMpgSio = 0;
-
- /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
-
- if (state->operation_mode == OM_DVBT_Diversity_Front) {
- if (bEnableOutput) {
- EcOcRegOcModeHip |=
- B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
- } else
- EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
- EcOcRegOcModeLop |=
- EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
- } else {
- EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
-
- if (bEnableOutput)
- EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
- else
- EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
-
- /* Don't Insert RS Byte */
- if (state->insert_rs_byte) {
- EcOcRegOcModeLop &=
- (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
- EcOcRegOcModeHip &=
- (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
- EcOcRegOcModeHip |=
- EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
- } else {
- EcOcRegOcModeLop |=
- EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
- EcOcRegOcModeHip &=
- (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
- EcOcRegOcModeHip |=
- EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
- }
-
- /* Mode = Parallel */
- if (state->enable_parallel)
- EcOcRegOcModeLop &=
- (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
- else
- EcOcRegOcModeLop |=
- EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
- }
- /* Invert Data */
- /* EcOcRegIprInvMpg |= 0x00FF; */
- EcOcRegIprInvMpg &= (~(0x00FF));
-
- /* Invert Error ( we don't use the pin ) */
- /* EcOcRegIprInvMpg |= 0x0100; */
- EcOcRegIprInvMpg &= (~(0x0100));
-
- /* Invert Start ( we don't use the pin ) */
- /* EcOcRegIprInvMpg |= 0x0200; */
- EcOcRegIprInvMpg &= (~(0x0200));
-
- /* Invert Valid ( we don't use the pin ) */
- /* EcOcRegIprInvMpg |= 0x0400; */
- EcOcRegIprInvMpg &= (~(0x0400));
-
- /* Invert Clock */
- /* EcOcRegIprInvMpg |= 0x0800; */
- EcOcRegIprInvMpg &= (~(0x0800));
-
- /* EcOcRegOcModeLop =0x05; */
- status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
- if (status < 0)
- break;
- status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
- if (status < 0)
- break;
- status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
- if (status < 0)
- break;
- } while (0);
- return status;
-}
-
-static int SetDeviceTypeId(struct drxd_state *state)
-{
- int status = 0;
- u16 deviceId = 0;
-
- do {
- status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
- if (status < 0)
- break;
- /* TODO: why twice? */
- status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
- if (status < 0)
- break;
- printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
-
- state->type_A = 0;
- state->PGA = 0;
- state->diversity = 0;
- if (deviceId == 0) { /* on A2 only 3975 available */
- state->type_A = 1;
- printk(KERN_INFO "DRX3975D-A2\n");
- } else {
- deviceId >>= 12;
- printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
- switch (deviceId) {
- case 4:
- state->diversity = 1;
- case 3:
- case 7:
- state->PGA = 1;
- break;
- case 6:
- state->diversity = 1;
- case 5:
- case 8:
- break;
- default:
- status = -1;
- break;
- }
- }
- } while (0);
-
- if (status < 0)
- return status;
-
- /* Init Table selection */
- state->m_InitAtomicRead = DRXD_InitAtomicRead;
- state->m_InitSC = DRXD_InitSC;
- state->m_ResetECRAM = DRXD_ResetECRAM;
- if (state->type_A) {
- state->m_ResetCEFR = DRXD_ResetCEFR;
- state->m_InitFE_1 = DRXD_InitFEA2_1;
- state->m_InitFE_2 = DRXD_InitFEA2_2;
- state->m_InitCP = DRXD_InitCPA2;
- state->m_InitCE = DRXD_InitCEA2;
- state->m_InitEQ = DRXD_InitEQA2;
- state->m_InitEC = DRXD_InitECA2;
- if (load_firmware(state, DRX_FW_FILENAME_A2))
- return -EIO;
- } else {
- state->m_ResetCEFR = NULL;
- state->m_InitFE_1 = DRXD_InitFEB1_1;
- state->m_InitFE_2 = DRXD_InitFEB1_2;
- state->m_InitCP = DRXD_InitCPB1;
- state->m_InitCE = DRXD_InitCEB1;
- state->m_InitEQ = DRXD_InitEQB1;
- state->m_InitEC = DRXD_InitECB1;
- if (load_firmware(state, DRX_FW_FILENAME_B1))
- return -EIO;
- }
- if (state->diversity) {
- state->m_InitDiversityFront = DRXD_InitDiversityFront;
- state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
- state->m_DisableDiversity = DRXD_DisableDiversity;
- state->m_StartDiversityFront = DRXD_StartDiversityFront;
- state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
- state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
- state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
- } else {
- state->m_InitDiversityFront = NULL;
- state->m_InitDiversityEnd = NULL;
- state->m_DisableDiversity = NULL;
- state->m_StartDiversityFront = NULL;
- state->m_StartDiversityEnd = NULL;
- state->m_DiversityDelay8MHZ = NULL;
- state->m_DiversityDelay6MHZ = NULL;
- }
-
- return status;
-}
-
-static int CorrectSysClockDeviation(struct drxd_state *state)
-{
- int status;
- s32 incr = 0;
- s32 nomincr = 0;
- u32 bandwidth = 0;
- u32 sysClockInHz = 0;
- u32 sysClockFreq = 0; /* in kHz */
- s16 oscClockDeviation;
- s16 Diff;
-
- do {
- /* Retrieve bandwidth and incr, sanity check */
-
- /* These accesses should be AtomicReadReg32, but that
- causes trouble (at least for diversity */
- status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
- if (status < 0)
- break;
- status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
- if (status < 0)
- break;
-
- if (state->type_A) {
- if ((nomincr - incr < -500) || (nomincr - incr > 500))
- break;
- } else {
- if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
- break;
- }
-
- switch (state->props.bandwidth_hz) {
- case 8000000:
- bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
- break;
- case 7000000:
- bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
- break;
- case 6000000:
- bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
- break;
- default:
- return -1;
- break;
- }
-
- /* Compute new sysclock value
- sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
- incr += (1 << 23);
- sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
- sysClockFreq = (u32) (sysClockInHz / 1000);
- /* rounding */
- if ((sysClockInHz % 1000) > 500)
- sysClockFreq++;
-
- /* Compute clock deviation in ppm */
- oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
- (s32)
- (state->expected_sys_clock_freq)) *
- 1000000L) /
- (s32)
- (state->expected_sys_clock_freq));
-
- Diff = oscClockDeviation - state->osc_clock_deviation;
- /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
- if (Diff >= -200 && Diff <= 200) {
- state->sys_clock_freq = (u16) sysClockFreq;
- if (oscClockDeviation != state->osc_clock_deviation) {
- if (state->config.osc_deviation) {
- state->config.osc_deviation(state->priv,
- oscClockDeviation,
- 1);
- state->osc_clock_deviation =
- oscClockDeviation;
- }
- }
- /* switch OFF SRMM scan in SC */
- status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
- if (status < 0)
- break;
- /* overrule FE_IF internal value for
- proper re-locking */
- status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
- if (status < 0)
- break;
- state->cscd_state = CSCD_SAVED;
- }
- } while (0);
-
- return status;
-}
-
-static int DRX_Stop(struct drxd_state *state)
-{
- int status;
-
- if (state->drxd_state != DRXD_STARTED)
- return 0;
-
- do {
- if (state->cscd_state != CSCD_SAVED) {
- u32 lock;
- status = DRX_GetLockStatus(state, &lock);
- if (status < 0)
- break;
- }
-
- status = StopOC(state);
- if (status < 0)
- break;
-
- state->drxd_state = DRXD_STOPPED;
-
- status = ConfigureMPEGOutput(state, 0);
- if (status < 0)
- break;
-
- if (state->type_A) {
- /* Stop relevant processors off the device */
- status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
- if (status < 0)
- break;
-
- status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
- status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
- } else {
- /* Stop all processors except HI & CC & FE */
- status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
- status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
- status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
- status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
- status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
- status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
- status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
- if (status < 0)
- break;
- }
-
- } while (0);
- return status;
-}
-
-int SetOperationMode(struct drxd_state *state, int oMode)
-{
- int status;
-
- do {
- if (state->drxd_state != DRXD_STOPPED) {
- status = -1;
- break;
- }
-
- if (oMode == state->operation_mode) {
- status = 0;
- break;
- }
-
- if (oMode != OM_Default && !state->diversity) {
- status = -1;
- break;
- }
-
- switch (oMode) {
- case OM_DVBT_Diversity_Front:
- status = WriteTable(state, state->m_InitDiversityFront);
- break;
- case OM_DVBT_Diversity_End:
- status = WriteTable(state, state->m_InitDiversityEnd);
- break;
- case OM_Default:
- /* We need to check how to
- get DRXD out of diversity */
- default:
- status = WriteTable(state, state->m_DisableDiversity);
- break;
- }
- } while (0);
-
- if (!status)
- state->operation_mode = oMode;
- return status;
-}
-
-static int StartDiversity(struct drxd_state *state)
-{
- int status = 0;
- u16 rcControl;
-
- do {
- if (state->operation_mode == OM_DVBT_Diversity_Front) {
- status = WriteTable(state, state->m_StartDiversityFront);
- if (status < 0)
- break;
- } else if (state->operation_mode == OM_DVBT_Diversity_End) {
- status = WriteTable(state, state->m_StartDiversityEnd);
- if (status < 0)
- break;
- if (state->props.bandwidth_hz == 8000000) {
- status = WriteTable(state, state->m_DiversityDelay8MHZ);
- if (status < 0)
- break;
- } else {
- status = WriteTable(state, state->m_DiversityDelay6MHZ);
- if (status < 0)
- break;
- }
-
- status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
- if (status < 0)
- break;
- rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
- rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
- /* combining enabled */
- B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
- B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
- B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
- status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
- if (status < 0)
- break;
- }
- } while (0);
- return status;
-}
-
-static int SetFrequencyShift(struct drxd_state *state,
- u32 offsetFreq, int channelMirrored)
-{
- int negativeShift = (state->tuner_mirrors == channelMirrored);
-
- /* Handle all mirroring
- *
- * Note: ADC mirroring (aliasing) is implictly handled by limiting
- * feFsRegAddInc to 28 bits below
- * (if the result before masking is more than 28 bits, this means
- * that the ADC is mirroring.
- * The masking is in fact the aliasing of the ADC)
- *
- */
-
- /* Compute register value, unsigned computation */
- state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
- offsetFreq,
- 1 << 28, state->sys_clock_freq);
- /* Remove integer part */
- state->fe_fs_add_incr &= 0x0FFFFFFFL;
- if (negativeShift)
- state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
-
- /* Save the frequency shift without tunerOffset compensation
- for CtrlGetChannel. */
- state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
- 1 << 28, state->sys_clock_freq);
- /* Remove integer part */
- state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
- if (negativeShift)
- state->org_fe_fs_add_incr = ((1L << 28) -
- state->org_fe_fs_add_incr);
-
- return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
- state->fe_fs_add_incr, 0);
-}
-
-static int SetCfgNoiseCalibration(struct drxd_state *state,
- struct SNoiseCal *noiseCal)
-{
- u16 beOptEna;
- int status = 0;
-
- do {
- status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
- if (status < 0)
- break;
- if (noiseCal->cpOpt) {
- beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
- } else {
- beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
- status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
- if (status < 0)
- break;
- }
- status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
- if (status < 0)
- break;
-
- if (!state->type_A) {
- status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
- if (status < 0)
- break;
- status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
- if (status < 0)
- break;
- }
- } while (0);
-
- return status;
-}
-
-static int DRX_Start(struct drxd_state *state, s32 off)
-{
- struct dtv_frontend_properties *p = &state->props;
- int status;
-
- u16 transmissionParams = 0;
- u16 operationMode = 0;
- u16 qpskTdTpsPwr = 0;
- u16 qam16TdTpsPwr = 0;
- u16 qam64TdTpsPwr = 0;
- u32 feIfIncr = 0;
- u32 bandwidth = 0;
- int mirrorFreqSpect;
-
- u16 qpskSnCeGain = 0;
- u16 qam16SnCeGain = 0;
- u16 qam64SnCeGain = 0;
- u16 qpskIsGainMan = 0;
- u16 qam16IsGainMan = 0;
- u16 qam64IsGainMan = 0;
- u16 qpskIsGainExp = 0;
- u16 qam16IsGainExp = 0;
- u16 qam64IsGainExp = 0;
- u16 bandwidthParam = 0;
-
- if (off < 0)
- off = (off - 500) / 1000;
- else
- off = (off + 500) / 1000;
-
- do {
- if (state->drxd_state != DRXD_STOPPED)
- return -1;
- status = ResetECOD(state);
- if (status < 0)
- break;
- if (state->type_A) {
- status = InitSC(state);
- if (status < 0)
- break;
- } else {
- status = InitFT(state);
- if (status < 0)
- break;
- status = InitCP(state);
- if (status < 0)
- break;
- status = InitCE(state);
- if (status < 0)
- break;
- status = InitEQ(state);
- if (status < 0)
- break;
- status = InitSC(state);
- if (status < 0)
- break;
- }
-
- /* Restore current IF & RF AGC settings */
-
- status = SetCfgIfAgc(state, &state->if_agc_cfg);
- if (status < 0)
- break;
- status = SetCfgRfAgc(state, &state->rf_agc_cfg);
- if (status < 0)
- break;
-
- mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
-
- switch (p->transmission_mode) {
- default: /* Not set, detect it automatically */
- operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
- /* fall through , try first guess DRX_FFTMODE_8K */
- case TRANSMISSION_MODE_8K:
- transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
- if (state->type_A) {
- status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
- if (status < 0)
- break;
- qpskSnCeGain = 99;
- qam16SnCeGain = 83;
- qam64SnCeGain = 67;
- }
- break;
- case TRANSMISSION_MODE_2K:
- transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
- if (state->type_A) {
- status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
- if (status < 0)
- break;
- qpskSnCeGain = 97;
- qam16SnCeGain = 71;
- qam64SnCeGain = 65;
- }
- break;
- }
-
- switch (p->guard_interval) {
- case GUARD_INTERVAL_1_4:
- transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
- break;
- case GUARD_INTERVAL_1_8:
- transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
- break;
- case GUARD_INTERVAL_1_16:
- transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
- break;
- case GUARD_INTERVAL_1_32:
- transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
- break;
- default: /* Not set, detect it automatically */
- operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
- /* try first guess 1/4 */
- transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
- break;
- }
-
- switch (p->hierarchy) {
- case HIERARCHY_1:
- transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
- if (state->type_A) {
- status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
- if (status < 0)
- break;
-
- qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
- qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
- qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
-
- qpskIsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
- qam16IsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
- qam64IsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
-
- qpskIsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
- qam16IsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
- qam64IsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
- }
- break;
-
- case HIERARCHY_2:
- transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
- if (state->type_A) {
- status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
- if (status < 0)
- break;
-
- qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
- qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
- qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
-
- qpskIsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
- qam16IsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
- qam64IsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
-
- qpskIsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
- qam16IsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
- qam64IsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
- }
- break;
- case HIERARCHY_4:
- transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
- if (state->type_A) {
- status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
- if (status < 0)
- break;
-
- qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
- qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
- qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
-
- qpskIsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
- qam16IsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
- qam64IsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
-
- qpskIsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
- qam16IsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
- qam64IsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
- }
- break;
- case HIERARCHY_AUTO:
- default:
- /* Not set, detect it automatically, start with none */
- operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
- transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
- if (state->type_A) {
- status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
- if (status < 0)
- break;
-
- qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
- qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
- qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
-
- qpskIsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
- qam16IsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
- qam64IsGainMan =
- SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
-
- qpskIsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
- qam16IsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
- qam64IsGainExp =
- SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
- }
- break;
- }
- status = status;
- if (status < 0)
- break;
-
- switch (p->modulation) {
- default:
- operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
- /* fall through , try first guess
- DRX_CONSTELLATION_QAM64 */
- case QAM_64:
- transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
- if (state->type_A) {
- status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
- if (status < 0)
- break;
-
- status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
- if (status < 0)
- break;
- }
- break;
- case QPSK:
- transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
- if (state->type_A) {
- status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
- if (status < 0)
- break;
-
- status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
- if (status < 0)
- break;
- }
- break;
-
- case QAM_16:
- transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
- if (state->type_A) {
- status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
- if (status < 0)
- break;
-
- status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
- if (status < 0)
- break;
- }
- break;
-
- }
- status = status;
- if (status < 0)
- break;
-
- switch (DRX_CHANNEL_HIGH) {
- default:
- case DRX_CHANNEL_AUTO:
- case DRX_CHANNEL_LOW:
- transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
- status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
- if (status < 0)
- break;
- break;
- case DRX_CHANNEL_HIGH:
- transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
- status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
- if (status < 0)
- break;
- break;
-
- }
-
- switch (p->code_rate_HP) {
- case FEC_1_2:
- transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
- if (state->type_A) {
- status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
- if (status < 0)
- break;
- }
- break;
- default:
- operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
- case FEC_2_3:
- transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
- if (state->type_A) {
- status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
- if (status < 0)
- break;
- }
- break;
- case FEC_3_4:
- transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
- if (state->type_A) {
- status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
- if (status < 0)
- break;
- }
- break;
- case FEC_5_6:
- transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
- if (state->type_A) {
- status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
- if (status < 0)
- break;
- }
- break;
- case FEC_7_8:
- transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
- if (state->type_A) {
- status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
- if (status < 0)
- break;
- }
- break;
- }
- status = status;
- if (status < 0)
- break;
-
- /* First determine real bandwidth (Hz) */
- /* Also set delay for impulse noise cruncher (only A2) */
- /* Also set parameters for EC_OC fix, note
- EC_OC_REG_TMD_HIL_MAR is changed
- by SC for fix for some 8K,1/8 guard but is restored by
- InitEC and ResetEC
- functions */
- switch (p->bandwidth_hz) {
- case 0:
- p->bandwidth_hz = 8000000;
- /* fall through */
- case 8000000:
- /* (64/7)*(8/8)*1000000 */
- bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
-
- bandwidthParam = 0;
- status = Write16(state,
- FE_AG_REG_IND_DEL__A, 50, 0x0000);
- break;
- case 7000000:
- /* (64/7)*(7/8)*1000000 */
- bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
- bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
- status = Write16(state,
- FE_AG_REG_IND_DEL__A, 59, 0x0000);
- break;
- case 6000000:
- /* (64/7)*(6/8)*1000000 */
- bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
- bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
- status = Write16(state,
- FE_AG_REG_IND_DEL__A, 71, 0x0000);
- break;
- default:
- status = -EINVAL;
- }
- if (status < 0)
- break;
-
- status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
- if (status < 0)
- break;
-
- {
- u16 sc_config;
- status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
- if (status < 0)
- break;
-
- /* enable SLAVE mode in 2k 1/32 to
- prevent timing change glitches */
- if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
- (p->guard_interval == GUARD_INTERVAL_1_32)) {
- /* enable slave */
- sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
- } else {
- /* disable slave */
- sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
- }
- status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
- if (status < 0)
- break;
- }
-
- status = SetCfgNoiseCalibration(state, &state->noise_cal);
- if (status < 0)
- break;
-
- if (state->cscd_state == CSCD_INIT) {
- /* switch on SRMM scan in SC */
- status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
- if (status < 0)
- break;
-/* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
- state->cscd_state = CSCD_SET;
- }
-
- /* Now compute FE_IF_REG_INCR */
- /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
- ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
- feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
- (1ULL << 21), bandwidth) - (1 << 23);
- status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
- if (status < 0)
- break;
- status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
- if (status < 0)
- break;
- /* Bandwidth setting done */
-
- /* Mirror & frequency offset */
- SetFrequencyShift(state, off, mirrorFreqSpect);
-
- /* Start SC, write channel settings to SC */
-
- /* Enable SC after setting all other parameters */
- status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
- if (status < 0)
- break;
- status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
- if (status < 0)
- break;
-
- /* Write SC parameter registers, operation mode */
-#if 1
- operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
- SC_RA_RAM_OP_AUTO_GUARD__M |
- SC_RA_RAM_OP_AUTO_CONST__M |
- SC_RA_RAM_OP_AUTO_HIER__M |
- SC_RA_RAM_OP_AUTO_RATE__M);
-#endif
- status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
- if (status < 0)
- break;
-
- /* Start correct processes to get in lock */
- status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
- if (status < 0)
- break;
-
- status = StartOC(state);
- if (status < 0)
- break;
-
- if (state->operation_mode != OM_Default) {
- status = StartDiversity(state);
- if (status < 0)
- break;
- }
-
- state->drxd_state = DRXD_STARTED;
- } while (0);
-
- return status;
-}
-
-static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
-{
- u32 ulRfAgcOutputLevel = 0xffffffff;
- u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
- u32 ulRfAgcMinLevel = 0; /* Currently unused */
- u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
- u32 ulRfAgcSpeed = 0; /* Currently unused */
- u32 ulRfAgcMode = 0; /*2; Off */
- u32 ulRfAgcR1 = 820;
- u32 ulRfAgcR2 = 2200;
- u32 ulRfAgcR3 = 150;
- u32 ulIfAgcMode = 0; /* Auto */
- u32 ulIfAgcOutputLevel = 0xffffffff;
- u32 ulIfAgcSettleLevel = 0xffffffff;
- u32 ulIfAgcMinLevel = 0xffffffff;
- u32 ulIfAgcMaxLevel = 0xffffffff;
- u32 ulIfAgcSpeed = 0xffffffff;
- u32 ulIfAgcR1 = 820;
- u32 ulIfAgcR2 = 2200;
- u32 ulIfAgcR3 = 150;
- u32 ulClock = state->config.clock;
- u32 ulSerialMode = 0;
- u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
- u32 ulHiI2cDelay = HI_I2C_DELAY;
- u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
- u32 ulHiI2cPatch = 0;
- u32 ulEnvironment = APPENV_PORTABLE;
- u32 ulEnvironmentDiversity = APPENV_MOBILE;
- u32 ulIFFilter = IFFILTER_SAW;
-
- state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
- state->if_agc_cfg.outputLevel = 0;
- state->if_agc_cfg.settleLevel = 140;
- state->if_agc_cfg.minOutputLevel = 0;
- state->if_agc_cfg.maxOutputLevel = 1023;
- state->if_agc_cfg.speed = 904;
-
- if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
- state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
- state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
- }
-
- if (ulIfAgcMode == 0 &&
- ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
- ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
- ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
- ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
- state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
- state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
- state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
- state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
- state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
- }
-
- state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
- state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
- state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
-
- state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
- state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
- state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
-
- state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
- /* rest of the RFAgcCfg structure currently unused */
- if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
- state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
- state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
- }
-
- if (ulRfAgcMode == 0 &&
- ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
- ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
- ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
- ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
- state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
- state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
- state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
- state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
- state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
- }
-
- if (ulRfAgcMode == 2)
- state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
-
- if (ulEnvironment <= 2)
- state->app_env_default = (enum app_env)
- (ulEnvironment);
- if (ulEnvironmentDiversity <= 2)
- state->app_env_diversity = (enum app_env)
- (ulEnvironmentDiversity);
-
- if (ulIFFilter == IFFILTER_DISCRETE) {
- /* discrete filter */
- state->noise_cal.cpOpt = 0;
- state->noise_cal.cpNexpOfs = 40;
- state->noise_cal.tdCal2k = -40;
- state->noise_cal.tdCal8k = -24;
- } else {
- /* SAW filter */
- state->noise_cal.cpOpt = 1;
- state->noise_cal.cpNexpOfs = 0;
- state->noise_cal.tdCal2k = -21;
- state->noise_cal.tdCal8k = -24;
- }
- state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
-
- state->chip_adr = (state->config.demod_address << 1) | 1;
- switch (ulHiI2cPatch) {
- case 1:
- state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
- break;
- case 3:
- state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
- break;
- default:
- state->m_HiI2cPatch = NULL;
- }
-
- /* modify tuner and clock attributes */
- state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
- /* expected system clock frequency in kHz */
- state->expected_sys_clock_freq = 48000;
- /* real system clock frequency in kHz */
- state->sys_clock_freq = 48000;
- state->osc_clock_freq = (u16) ulClock;
- state->osc_clock_deviation = 0;
- state->cscd_state = CSCD_INIT;
- state->drxd_state = DRXD_UNINITIALIZED;
-
- state->PGA = 0;
- state->type_A = 0;
- state->tuner_mirrors = 0;
-
- /* modify MPEG output attributes */
- state->insert_rs_byte = state->config.insert_rs_byte;
- state->enable_parallel = (ulSerialMode != 1);
-
- /* Timing div, 250ns/Psys */
- /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
-
- state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
- ulHiI2cDelay) / 1000;
- /* Bridge delay, uses oscilator clock */
- /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
- state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
- ulHiI2cBridgeDelay) / 1000;
-
- state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
- /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
- state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
- return 0;
-}
-
-int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
-{
- int status = 0;
- u32 driverVersion;
-
- if (state->init_done)
- return 0;
-
- CDRXD(state, state->config.IF ? state->config.IF : 36000000);
-
- do {
- state->operation_mode = OM_Default;
-
- status = SetDeviceTypeId(state);
- if (status < 0)
- break;
-
- /* Apply I2c address patch to B1 */
- if (!state->type_A && state->m_HiI2cPatch != NULL)
- status = WriteTable(state, state->m_HiI2cPatch);
- if (status < 0)
- break;
-
- if (state->type_A) {
- /* HI firmware patch for UIO readout,
- avoid clearing of result register */
- status = Write16(state, 0x43012D, 0x047f, 0);
- if (status < 0)
- break;
- }
-
- status = HI_ResetCommand(state);
- if (status < 0)
- break;
-
- status = StopAllProcessors(state);
- if (status < 0)
- break;
- status = InitCC(state);
- if (status < 0)
- break;
-
- state->osc_clock_deviation = 0;
-
- if (state->config.osc_deviation)
- state->osc_clock_deviation =
- state->config.osc_deviation(state->priv, 0, 0);
- {
- /* Handle clock deviation */
- s32 devB;
- s32 devA = (s32) (state->osc_clock_deviation) *
- (s32) (state->expected_sys_clock_freq);
- /* deviation in kHz */
- s32 deviation = (devA / (1000000L));
- /* rounding, signed */
- if (devA > 0)
- devB = (2);
- else
- devB = (-2);
- if ((devB * (devA % 1000000L) > 1000000L)) {
- /* add +1 or -1 */
- deviation += (devB / 2);
- }
-
- state->sys_clock_freq =
- (u16) ((state->expected_sys_clock_freq) +
- deviation);
- }
- status = InitHI(state);
- if (status < 0)
- break;
- status = InitAtomicRead(state);
- if (status < 0)
- break;
-
- status = EnableAndResetMB(state);
- if (status < 0)
- break;
- if (state->type_A)
- status = ResetCEFR(state);
- if (status < 0)
- break;
-
- if (fw) {
- status = DownloadMicrocode(state, fw, fw_size);
- if (status < 0)
- break;
- } else {
- status = DownloadMicrocode(state, state->microcode, state->microcode_length);
- if (status < 0)
- break;
- }
-
- if (state->PGA) {
- state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
- SetCfgPga(state, 0); /* PGA = 0 dB */
- } else {
- state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
- }
-
- state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
-
- status = InitFE(state);
- if (status < 0)
- break;
- status = InitFT(state);
- if (status < 0)
- break;
- status = InitCP(state);
- if (status < 0)
- break;
- status = InitCE(state);
- if (status < 0)
- break;
- status = InitEQ(state);
- if (status < 0)
- break;
- status = InitEC(state);
- if (status < 0)
- break;
- status = InitSC(state);
- if (status < 0)
- break;
-
- status = SetCfgIfAgc(state, &state->if_agc_cfg);
- if (status < 0)
- break;
- status = SetCfgRfAgc(state, &state->rf_agc_cfg);
- if (status < 0)
- break;
-
- state->cscd_state = CSCD_INIT;
- status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
- status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
- if (status < 0)
- break;
-
- driverVersion = (((VERSION_MAJOR / 10) << 4) +
- (VERSION_MAJOR % 10)) << 24;
- driverVersion += (((VERSION_MINOR / 10) << 4) +
- (VERSION_MINOR % 10)) << 16;
- driverVersion += ((VERSION_PATCH / 1000) << 12) +
- ((VERSION_PATCH / 100) << 8) +
- ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
-
- status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
- if (status < 0)
- break;
-
- status = StopOC(state);
- if (status < 0)
- break;
-
- state->drxd_state = DRXD_STOPPED;
- state->init_done = 1;
- status = 0;
- } while (0);
- return status;
-}
-
-int DRXD_status(struct drxd_state *state, u32 * pLockStatus)
-{
- DRX_GetLockStatus(state, pLockStatus);
-
- /*if (*pLockStatus&DRX_LOCK_MPEG) */
- if (*pLockStatus & DRX_LOCK_FEC) {
- ConfigureMPEGOutput(state, 1);
- /* Get status again, in case we have MPEG lock now */
- /*DRX_GetLockStatus(state, pLockStatus); */
- }
-
- return 0;
-}
-
-/****************************************************************************/
-/****************************************************************************/
-/****************************************************************************/
-
-static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
-{
- struct drxd_state *state = fe->demodulator_priv;
- u32 value;
- int res;
-
- res = ReadIFAgc(state, &value);
- if (res < 0)
- *strength = 0;
- else
- *strength = 0xffff - (value << 4);
- return 0;
-}
-
-static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
-{
- struct drxd_state *state = fe->demodulator_priv;
- u32 lock;
-
- DRXD_status(state, &lock);
- *status = 0;
- /* No MPEG lock in V255 firmware, bug ? */
-#if 1
- if (lock & DRX_LOCK_MPEG)
- *status |= FE_HAS_LOCK;
-#else
- if (lock & DRX_LOCK_FEC)
- *status |= FE_HAS_LOCK;
-#endif
- if (lock & DRX_LOCK_FEC)
- *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
- if (lock & DRX_LOCK_DEMOD)
- *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
-
- return 0;
-}
-
-static int drxd_init(struct dvb_frontend *fe)
-{
- struct drxd_state *state = fe->demodulator_priv;
- int err = 0;
-
-/* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
- return DRXD_init(state, 0, 0);
-
- err = DRXD_init(state, state->fw->data, state->fw->size);
- release_firmware(state->fw);
- return err;
-}
-
-int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
-{
- struct drxd_state *state = fe->demodulator_priv;
-
- if (state->config.disable_i2c_gate_ctrl == 1)
- return 0;
-
- return DRX_ConfigureI2CBridge(state, onoff);
-}
-EXPORT_SYMBOL(drxd_config_i2c);
-
-static int drxd_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *sets)
-{
- sets->min_delay_ms = 10000;
- sets->max_drift = 0;
- sets->step_size = 0;
- return 0;
-}
-
-static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
-{
- *ber = 0;
- return 0;
-}
-
-static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
-{
- *snr = 0;
- return 0;
-}
-
-static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
-{
- *ucblocks = 0;
- return 0;
-}
-
-static int drxd_sleep(struct dvb_frontend *fe)
-{
- struct drxd_state *state = fe->demodulator_priv;
-
- ConfigureMPEGOutput(state, 0);
- return 0;
-}
-
-static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- return drxd_config_i2c(fe, enable);
-}
-
-static int drxd_set_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- struct drxd_state *state = fe->demodulator_priv;
- s32 off = 0;
-
- state->props = *p;
- DRX_Stop(state);
-
- if (fe->ops.tuner_ops.set_params) {
- fe->ops.tuner_ops.set_params(fe);
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 0);
- }
-
- msleep(200);
-
- return DRX_Start(state, off);
-}
-
-static void drxd_release(struct dvb_frontend *fe)
-{
- struct drxd_state *state = fe->demodulator_priv;
-
- kfree(state);
-}
-
-static struct dvb_frontend_ops drxd_ops = {
- .delsys = { SYS_DVBT},
- .info = {
- .name = "Micronas DRXD DVB-T",
- .frequency_min = 47125000,
- .frequency_max = 855250000,
- .frequency_stepsize = 166667,
- .frequency_tolerance = 0,
- .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
- FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
- FE_CAN_FEC_AUTO |
- FE_CAN_QAM_16 | FE_CAN_QAM_64 |
- FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
-
- .release = drxd_release,
- .init = drxd_init,
- .sleep = drxd_sleep,
- .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
-
- .set_frontend = drxd_set_frontend,
- .get_tune_settings = drxd_get_tune_settings,
-
- .read_status = drxd_read_status,
- .read_ber = drxd_read_ber,
- .read_signal_strength = drxd_read_signal_strength,
- .read_snr = drxd_read_snr,
- .read_ucblocks = drxd_read_ucblocks,
-};
-
-struct dvb_frontend *drxd_attach(const struct drxd_config *config,
- void *priv, struct i2c_adapter *i2c,
- struct device *dev)
-{
- struct drxd_state *state = NULL;
-
- state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
- if (!state)
- return NULL;
- memset(state, 0, sizeof(*state));
-
- memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
- state->dev = dev;
- state->config = *config;
- state->i2c = i2c;
- state->priv = priv;
-
- mutex_init(&state->mutex);
-
- if (Read16(state, 0, 0, 0) < 0)
- goto error;
-
- memcpy(&state->frontend.ops, &drxd_ops,
- sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
- ConfigureMPEGOutput(state, 0);
- return &state->frontend;
-
-error:
- printk(KERN_ERR "drxd: not found\n");
- kfree(state);
- return NULL;
-}
-EXPORT_SYMBOL(drxd_attach);
-
-MODULE_DESCRIPTION("DRXD driver");
-MODULE_AUTHOR("Micronas");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/drxd_map_firm.h b/drivers/media/dvb/frontends/drxd_map_firm.h
deleted file mode 100644
index 6bc553abf21..00000000000
--- a/drivers/media/dvb/frontends/drxd_map_firm.h
+++ /dev/null
@@ -1,1013 +0,0 @@
-/*
- * drx3973d_map_firm.h
- *
- * Copyright (C) 2006-2007 Micronas
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 only, as published by the Free Software Foundation.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __DRX3973D_MAP__H__
-#define __DRX3973D_MAP__H__
-
-/*
- * Note: originally, this file contained 12000+ lines of data
- * Probably a few lines for every firwmare assembler instruction. However,
- * only a few defines were actually used. So, removed all uneeded lines.
- * If ever needed, the other lines can be easily obtained via git history.
- */
-
-#define HI_COMM_EXEC__A 0x400000
-#define HI_COMM_MB__A 0x400002
-#define HI_CT_REG_COMM_STATE__A 0x410001
-#define HI_RA_RAM_SRV_RES__A 0x420031
-#define HI_RA_RAM_SRV_CMD__A 0x420032
-#define HI_RA_RAM_SRV_CMD_RESET 0x2
-#define HI_RA_RAM_SRV_CMD_CONFIG 0x3
-#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
-#define HI_RA_RAM_SRV_RST_KEY__A 0x420033
-#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
-#define HI_RA_RAM_SRV_CFG_KEY__A 0x420033
-#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034
-#define HI_RA_RAM_SRV_CFG_BDL__A 0x420035
-#define HI_RA_RAM_SRV_CFG_WUP__A 0x420036
-#define HI_RA_RAM_SRV_CFG_ACT__A 0x420037
-#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1
-#define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4
-#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0
-#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4
-#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8
-#define HI_RA_RAM_USR_BEGIN__A 0x420040
-#define HI_IF_RAM_TRP_BPT0__AX 0x430000
-#define HI_IF_RAM_USR_BEGIN__A 0x430200
-#define SC_COMM_EXEC__A 0x800000
-#define SC_COMM_EXEC_CTL_STOP 0x0
-#define SC_COMM_STATE__A 0x800001
-#define SC_RA_RAM_PARAM0__A 0x820040
-#define SC_RA_RAM_PARAM1__A 0x820041
-#define SC_RA_RAM_CMD_ADDR__A 0x820042
-#define SC_RA_RAM_CMD__A 0x820043
-#define SC_RA_RAM_CMD_PROC_START 0x1
-#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
-#define SC_RA_RAM_CMD_GET_OP_PARAM 0x5
-#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
-#define SC_RA_RAM_LOCKTRACK_MIN 0x1
-#define SC_RA_RAM_OP_PARAM_MODE_2K 0x0
-#define SC_RA_RAM_OP_PARAM_MODE_8K 0x1
-#define SC_RA_RAM_OP_PARAM_GUARD_32 0x0
-#define SC_RA_RAM_OP_PARAM_GUARD_16 0x4
-#define SC_RA_RAM_OP_PARAM_GUARD_8 0x8
-#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC
-#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
-#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
-#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
-#define SC_RA_RAM_OP_PARAM_HIER_NO 0x0
-#define SC_RA_RAM_OP_PARAM_HIER_A1 0x40
-#define SC_RA_RAM_OP_PARAM_HIER_A2 0x80
-#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
-#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
-#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
-#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
-#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
-#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
-#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
-#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
-#define SC_RA_RAM_OP_AUTO_MODE__M 0x1
-#define SC_RA_RAM_OP_AUTO_GUARD__M 0x2
-#define SC_RA_RAM_OP_AUTO_CONST__M 0x4
-#define SC_RA_RAM_OP_AUTO_HIER__M 0x8
-#define SC_RA_RAM_OP_AUTO_RATE__M 0x10
-#define SC_RA_RAM_LOCK__A 0x82004B
-#define SC_RA_RAM_LOCK_DEMOD__M 0x1
-#define SC_RA_RAM_LOCK_FEC__M 0x2
-#define SC_RA_RAM_LOCK_MPEG__M 0x4
-#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C
-#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1
-#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D
-#define SC_RA_RAM_CONFIG__A 0x820050
-#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4
-#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10
-#define SC_RA_RAM_CONFIG_SLAVE__M 0x20
-#define SC_RA_RAM_IF_SAVE__AX 0x82008E
-#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
-#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9
-#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2
-#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4
-#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3
-#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100
-#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4
-#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8
-#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5
-#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8
-#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6
-#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200
-#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7
-#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9
-#define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8
-#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4
-#define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9
-#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100
-#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA
-#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB
-#define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB
-#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1
-#define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC
-#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40
-#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD
-#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8
-#define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9
-#define SC_RA_RAM_BAND__A 0x8200EC
-#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4
-#define SC_RA_RAM_LC_ABS_2K__PRE 0x1F
-#define SC_RA_RAM_LC_ABS_8K__A 0x8200F5
-#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F
-#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6
-#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4
-#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB
-#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5
-#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF
-#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5
-#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E
-#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5
-#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A
-#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6
-#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB
-#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5
-#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F
-#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5
-#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197
-#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5
-#define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE
-#define SC_RA_RAM_PROC_LOCKTRACK 0x0
-#define FE_COMM_EXEC__A 0xC00000
-#define FE_AD_REG_COMM_EXEC__A 0xC10000
-#define FE_AD_REG_FDB_IN__A 0xC10012
-#define FE_AD_REG_PD__A 0xC10013
-#define FE_AD_REG_INVEXT__A 0xC10014
-#define FE_AD_REG_CLKNEG__A 0xC10015
-#define FE_AG_REG_COMM_EXEC__A 0xC20000
-#define FE_AG_REG_AG_MODE_LOP__A 0xC20010
-#define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10
-#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0
-#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10
-#define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20
-#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0
-#define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000
-#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0
-#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000
-#define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000
-#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0
-#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000
-#define FE_AG_REG_AG_MODE_HIP__A 0xC20011
-#define FE_AG_REG_AG_PGA_MODE__A 0xC20012
-#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0
-#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1
-#define FE_AG_REG_AG_AGC_SIO__A 0xC20013
-#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2
-#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0
-#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2
-#define FE_AG_REG_AG_PWD__A 0xC20015
-#define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2
-#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0
-#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2
-#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016
-#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017
-#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A
-#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B
-#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020
-#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024
-#define FE_AG_REG_EGC_SET_LVL__A 0xC20025
-#define FE_AG_REG_EGC_SET_LVL__M 0x1FF
-#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026
-#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027
-#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028
-#define FE_AG_REG_EGC_FLA_INC__A 0xC20029
-#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A
-#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B
-#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C
-#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D
-#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E
-#define FE_AG_REG_PM1_AGC_WRI__A 0xC20030
-#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF
-#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031
-#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032
-#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033
-#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034
-#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035
-#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF
-#define FE_AG_REG_PM2_AGC_WRI__A 0xC20036
-#define FE_AG_REG_IND_WIN__A 0xC2003C
-#define FE_AG_REG_IND_THD_LOL__A 0xC2003D
-#define FE_AG_REG_IND_THD_HIL__A 0xC2003E
-#define FE_AG_REG_IND_DEL__A 0xC2003F
-#define FE_AG_REG_IND_PD1_WRI__A 0xC20040
-#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041
-#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042
-#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043
-#define FE_AG_REG_PDC_RUR_CNT__A 0xC20044
-#define FE_AG_REG_PDC_SET_LVL__A 0xC20045
-#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046
-#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047
-#define FE_AG_REG_PDC_FLA_STP__A 0xC20048
-#define FE_AG_REG_PDC_SLO_STP__A 0xC20049
-#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A
-#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B
-#define FE_AG_REG_PDC_MAX__A 0xC2004C
-#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D
-#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E
-#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F
-#define FE_AG_REG_TGC_RUR_CNT__A 0xC20050
-#define FE_AG_REG_TGC_SET_LVL__A 0xC20051
-#define FE_AG_REG_TGC_SET_LVL__M 0x3F
-#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052
-#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053
-#define FE_AG_REG_TGC_FLA_STP__A 0xC20054
-#define FE_AG_REG_TGC_SLO_STP__A 0xC20055
-#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056
-#define FE_AG_REG_FGA_AUR_CNT__A 0xC20057
-#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058
-#define FE_AG_REG_FGM_WRI__A 0xC20061
-#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068
-#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069
-#define FE_FS_REG_COMM_EXEC__A 0xC30000
-#define FE_FS_REG_ADD_INC_LOP__A 0xC30010
-#define FE_FD_REG_COMM_EXEC__A 0xC40000
-#define FE_FD_REG_SCL__A 0xC40010
-#define FE_FD_REG_MAX_LEV__A 0xC40011
-#define FE_FD_REG_NR__A 0xC40012
-#define FE_FD_REG_MEAS_VAL__A 0xC40014
-#define FE_IF_REG_COMM_EXEC__A 0xC50000
-#define FE_IF_REG_INCR0__A 0xC50010
-#define FE_IF_REG_INCR0__W 16
-#define FE_IF_REG_INCR0__M 0xFFFF
-#define FE_IF_REG_INCR1__A 0xC50011
-#define FE_IF_REG_INCR1__M 0xFF
-#define FE_CF_REG_COMM_EXEC__A 0xC60000
-#define FE_CF_REG_SCL__A 0xC60010
-#define FE_CF_REG_MAX_LEV__A 0xC60011
-#define FE_CF_REG_NR__A 0xC60012
-#define FE_CF_REG_IMP_VAL__A 0xC60013
-#define FE_CF_REG_MEAS_VAL__A 0xC60014
-#define FE_CU_REG_COMM_EXEC__A 0xC70000
-#define FE_CU_REG_FRM_CNT_RST__A 0xC70011
-#define FE_CU_REG_FRM_CNT_STR__A 0xC70012
-#define FT_COMM_EXEC__A 0x1000000
-#define FT_REG_COMM_EXEC__A 0x1010000
-#define CP_COMM_EXEC__A 0x1400000
-#define CP_REG_COMM_EXEC__A 0x1410000
-#define CP_REG_INTERVAL__A 0x1410011
-#define CP_REG_BR_SPL_OFFSET__A 0x1410023
-#define CP_REG_BR_STR_DEL__A 0x1410024
-#define CP_REG_RT_ANG_INC0__A 0x1410030
-#define CP_REG_RT_ANG_INC1__A 0x1410031
-#define CP_REG_RT_DETECT_ENA__A 0x1410032
-#define CP_REG_RT_DETECT_TRH__A 0x1410033
-#define CP_REG_RT_EXP_MARG__A 0x141003E
-#define CP_REG_AC_NEXP_OFFS__A 0x1410040
-#define CP_REG_AC_AVER_POW__A 0x1410041
-#define CP_REG_AC_MAX_POW__A 0x1410042
-#define CP_REG_AC_WEIGHT_MAN__A 0x1410043
-#define CP_REG_AC_WEIGHT_EXP__A 0x1410044
-#define CP_REG_AC_AMP_MODE__A 0x1410047
-#define CP_REG_AC_AMP_FIX__A 0x1410048
-#define CP_REG_AC_ANG_MODE__A 0x141004A
-#define CE_COMM_EXEC__A 0x1800000
-#define CE_REG_COMM_EXEC__A 0x1810000
-#define CE_REG_TAPSET__A 0x1810011
-#define CE_REG_AVG_POW__A 0x1810012
-#define CE_REG_MAX_POW__A 0x1810013
-#define CE_REG_ATT__A 0x1810014
-#define CE_REG_NRED__A 0x1810015
-#define CE_REG_NE_ERR_SELECT__A 0x1810043
-#define CE_REG_NE_TD_CAL__A 0x1810044
-#define CE_REG_NE_MIXAVG__A 0x1810046
-#define CE_REG_NE_NUPD_OFS__A 0x1810047
-#define CE_REG_PE_NEXP_OFFS__A 0x1810050
-#define CE_REG_PE_TIMESHIFT__A 0x1810051
-#define CE_REG_TP_A0_TAP_NEW__A 0x1810064
-#define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065
-#define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066
-#define CE_REG_TP_A1_TAP_NEW__A 0x1810068
-#define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069
-#define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A
-#define CE_REG_TI_NEXP_OFFS__A 0x1810070
-#define CE_REG_FI_SHT_INCR__A 0x1810090
-#define CE_REG_FI_EXP_NORM__A 0x1810091
-#define CE_REG_IR_INPUTSEL__A 0x18100A0
-#define CE_REG_IR_STARTPOS__A 0x18100A1
-#define CE_REG_IR_NEXP_THRES__A 0x18100A2
-#define CE_REG_FR_TREAL00__A 0x1820010
-#define CE_REG_FR_TIMAG00__A 0x1820011
-#define CE_REG_FR_TREAL01__A 0x1820012
-#define CE_REG_FR_TIMAG01__A 0x1820013
-#define CE_REG_FR_TREAL02__A 0x1820014
-#define CE_REG_FR_TIMAG02__A 0x1820015
-#define CE_REG_FR_TREAL03__A 0x1820016
-#define CE_REG_FR_TIMAG03__A 0x1820017
-#define CE_REG_FR_TREAL04__A 0x1820018
-#define CE_REG_FR_TIMAG04__A 0x1820019
-#define CE_REG_FR_TREAL05__A 0x182001A
-#define CE_REG_FR_TIMAG05__A 0x182001B
-#define CE_REG_FR_TREAL06__A 0x182001C
-#define CE_REG_FR_TIMAG06__A 0x182001D
-#define CE_REG_FR_TREAL07__A 0x182001E
-#define CE_REG_FR_TIMAG07__A 0x182001F
-#define CE_REG_FR_TREAL08__A 0x1820020
-#define CE_REG_FR_TIMAG08__A 0x1820021
-#define CE_REG_FR_TREAL09__A 0x1820022
-#define CE_REG_FR_TIMAG09__A 0x1820023
-#define CE_REG_FR_TREAL10__A 0x1820024
-#define CE_REG_FR_TIMAG10__A 0x1820025
-#define CE_REG_FR_TREAL11__A 0x1820026
-#define CE_REG_FR_TIMAG11__A 0x1820027
-#define CE_REG_FR_MID_TAP__A 0x1820028
-#define CE_REG_FR_SQS_G00__A 0x1820029
-#define CE_REG_FR_SQS_G01__A 0x182002A
-#define CE_REG_FR_SQS_G02__A 0x182002B
-#define CE_REG_FR_SQS_G03__A 0x182002C
-#define CE_REG_FR_SQS_G04__A 0x182002D
-#define CE_REG_FR_SQS_G05__A 0x182002E
-#define CE_REG_FR_SQS_G06__A 0x182002F
-#define CE_REG_FR_SQS_G07__A 0x1820030
-#define CE_REG_FR_SQS_G08__A 0x1820031
-#define CE_REG_FR_SQS_G09__A 0x1820032
-#define CE_REG_FR_SQS_G10__A 0x1820033
-#define CE_REG_FR_SQS_G11__A 0x1820034
-#define CE_REG_FR_SQS_G12__A 0x1820035
-#define CE_REG_FR_RIO_G00__A 0x1820036
-#define CE_REG_FR_RIO_G01__A 0x1820037
-#define CE_REG_FR_RIO_G02__A 0x1820038
-#define CE_REG_FR_RIO_G03__A 0x1820039
-#define CE_REG_FR_RIO_G04__A 0x182003A
-#define CE_REG_FR_RIO_G05__A 0x182003B
-#define CE_REG_FR_RIO_G06__A 0x182003C
-#define CE_REG_FR_RIO_G07__A 0x182003D
-#define CE_REG_FR_RIO_G08__A 0x182003E
-#define CE_REG_FR_RIO_G09__A 0x182003F
-#define CE_REG_FR_RIO_G10__A 0x1820040
-#define CE_REG_FR_MODE__A 0x1820041
-#define CE_REG_FR_SQS_TRH__A 0x1820042
-#define CE_REG_FR_RIO_GAIN__A 0x1820043
-#define CE_REG_FR_BYPASS__A 0x1820044
-#define CE_REG_FR_PM_SET__A 0x1820045
-#define CE_REG_FR_ERR_SH__A 0x1820046
-#define CE_REG_FR_MAN_SH__A 0x1820047
-#define CE_REG_FR_TAP_SH__A 0x1820048
-#define EQ_COMM_EXEC__A 0x1C00000
-#define EQ_REG_COMM_EXEC__A 0x1C10000
-#define EQ_REG_COMM_MB__A 0x1C10002
-#define EQ_REG_IS_GAIN_MAN__A 0x1C10015
-#define EQ_REG_IS_GAIN_EXP__A 0x1C10016
-#define EQ_REG_IS_CLIP_EXP__A 0x1C10017
-#define EQ_REG_SN_CEGAIN__A 0x1C1002A
-#define EQ_REG_SN_OFFSET__A 0x1C1002B
-#define EQ_REG_RC_SEL_CAR__A 0x1C10032
-#define EQ_REG_RC_SEL_CAR_INIT 0x0
-#define EQ_REG_RC_SEL_CAR_DIV_ON 0x1
-#define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0
-#define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2
-#define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0
-#define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8
-#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0
-#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20
-#define EQ_REG_OT_CONST__A 0x1C10046
-#define EQ_REG_OT_ALPHA__A 0x1C10047
-#define EQ_REG_OT_QNT_THRES0__A 0x1C10048
-#define EQ_REG_OT_QNT_THRES1__A 0x1C10049
-#define EQ_REG_OT_CSI_STEP__A 0x1C1004A
-#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B
-#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061
-#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062
-#define EC_SB_REG_COMM_EXEC__A 0x2010000
-#define EC_SB_REG_TR_MODE__A 0x2010010
-#define EC_SB_REG_TR_MODE_8K 0x0
-#define EC_SB_REG_TR_MODE_2K 0x1
-#define EC_SB_REG_CONST__A 0x2010011
-#define EC_SB_REG_CONST_QPSK 0x0
-#define EC_SB_REG_CONST_16QAM 0x1
-#define EC_SB_REG_CONST_64QAM 0x2
-#define EC_SB_REG_ALPHA__A 0x2010012
-#define EC_SB_REG_PRIOR__A 0x2010013
-#define EC_SB_REG_PRIOR_HI 0x0
-#define EC_SB_REG_PRIOR_LO 0x1
-#define EC_SB_REG_CSI_HI__A 0x2010014
-#define EC_SB_REG_CSI_LO__A 0x2010015
-#define EC_SB_REG_SMB_TGL__A 0x2010016
-#define EC_SB_REG_SNR_HI__A 0x2010017
-#define EC_SB_REG_SNR_MID__A 0x2010018
-#define EC_SB_REG_SNR_LO__A 0x2010019
-#define EC_SB_REG_SCALE_MSB__A 0x201001A
-#define EC_SB_REG_SCALE_BIT2__A 0x201001B
-#define EC_SB_REG_SCALE_LSB__A 0x201001C
-#define EC_SB_REG_CSI_OFS__A 0x201001D
-#define EC_VD_REG_COMM_EXEC__A 0x2090000
-#define EC_VD_REG_FORCE__A 0x2090010
-#define EC_VD_REG_SET_CODERATE__A 0x2090011
-#define EC_VD_REG_SET_CODERATE_C1_2 0x0
-#define EC_VD_REG_SET_CODERATE_C2_3 0x1
-#define EC_VD_REG_SET_CODERATE_C3_4 0x2
-#define EC_VD_REG_SET_CODERATE_C5_6 0x3
-#define EC_VD_REG_SET_CODERATE_C7_8 0x4
-#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012
-#define EC_VD_REG_RLK_ENA__A 0x2090014
-#define EC_OD_REG_COMM_EXEC__A 0x2110000
-#define EC_OD_REG_SYNC__A 0x2110010
-#define EC_OD_DEINT_RAM__A 0x2120000
-#define EC_RS_REG_COMM_EXEC__A 0x2130000
-#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010
-#define EC_RS_REG_VAL__A 0x2130011
-#define EC_RS_REG_VAL_PCK 0x1
-#define EC_RS_EC_RAM__A 0x2140000
-#define EC_OC_REG_COMM_EXEC__A 0x2150000
-#define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1
-#define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2
-#define EC_OC_REG_COMM_INT_STA__A 0x2150007
-#define EC_OC_REG_OC_MODE_LOP__A 0x2150010
-#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1
-#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0
-#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1
-#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4
-#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0
-#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80
-#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80
-#define EC_OC_REG_OC_MODE_HIP__A 0x2150011
-#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10
-#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200
-#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0
-#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200
-#define EC_OC_REG_OC_MPG_SIO__A 0x2150012
-#define EC_OC_REG_OC_MPG_SIO__M 0xFFF
-#define EC_OC_REG_OC_MON_SIO__A 0x2150013
-#define EC_OC_REG_DTO_INC_LOP__A 0x2150014
-#define EC_OC_REG_DTO_INC_HIP__A 0x2150015
-#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016
-#define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0
-#define EC_OC_REG_TMD_TOP_MODE__A 0x215001D
-#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E
-#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F
-#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020
-#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021
-#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023
-#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024
-#define EC_OC_REG_RCN_MODE__A 0x2150027
-#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028
-#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029
-#define EC_OC_REG_RCN_CST_LOP__A 0x215002A
-#define EC_OC_REG_RCN_CST_HIP__A 0x215002B
-#define EC_OC_REG_RCN_SET_LVL__A 0x215002C
-#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D
-#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032
-#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033
-#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034
-#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035
-#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036
-#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF
-#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0
-#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038
-#define EC_OC_REG_OCR_MON_UOS__A 0x2150039
-#define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1
-#define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2
-#define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4
-#define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8
-#define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10
-#define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20
-#define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40
-#define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80
-#define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100
-#define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200
-#define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400
-#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800
-#define EC_OC_REG_OCR_MON_WRI__A 0x215003A
-#define EC_OC_REG_OCR_MON_WRI_INIT 0x0
-#define EC_OC_REG_IPR_INV_MPG__A 0x2150045
-#define CC_REG_OSC_MODE__A 0x2410010
-#define CC_REG_OSC_MODE_M20 0x1
-#define CC_REG_PLL_MODE__A 0x2410011
-#define CC_REG_PLL_MODE_BYPASS_PLL 0x1
-#define CC_REG_PLL_MODE_PUMP_CUR_12 0x14
-#define CC_REG_REF_DIVIDE__A 0x2410012
-#define CC_REG_PWD_MODE__A 0x2410015
-#define CC_REG_PWD_MODE_DOWN_PLL 0x2
-#define CC_REG_UPDATE__A 0x2410017
-#define CC_REG_UPDATE_KEY 0x3973
-#define CC_REG_JTAGID_L__A 0x2410019
-#define LC_COMM_EXEC__A 0x2800000
-#define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C
-#define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A
-#define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8
-#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060
-#define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4
-#define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061
-#define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1
-#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068
-#define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4
-#define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069
-#define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1
-#define B_HI_COMM_EXEC__A 0x400000
-#define B_HI_COMM_MB__A 0x400002
-#define B_HI_CT_REG_COMM_STATE__A 0x410001
-#define B_HI_RA_RAM_SRV_RES__A 0x420031
-#define B_HI_RA_RAM_SRV_CMD__A 0x420032
-#define B_HI_RA_RAM_SRV_CMD_RESET 0x2
-#define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3
-#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6
-#define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033
-#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
-#define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033
-#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034
-#define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035
-#define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036
-#define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037
-#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1
-#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4
-#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0
-#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4
-#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8
-#define B_HI_RA_RAM_USR_BEGIN__A 0x420040
-#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000
-#define B_HI_IF_RAM_USR_BEGIN__A 0x430200
-#define B_SC_COMM_EXEC__A 0x800000
-#define B_SC_COMM_EXEC_CTL_STOP 0x0
-#define B_SC_COMM_STATE__A 0x800001
-#define B_SC_RA_RAM_PARAM0__A 0x820040
-#define B_SC_RA_RAM_PARAM1__A 0x820041
-#define B_SC_RA_RAM_CMD_ADDR__A 0x820042
-#define B_SC_RA_RAM_CMD__A 0x820043
-#define B_SC_RA_RAM_CMD_PROC_START 0x1
-#define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
-#define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5
-#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
-#define B_SC_RA_RAM_LOCKTRACK_MIN 0x1
-#define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
-#define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
-#define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0
-#define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4
-#define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8
-#define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC
-#define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
-#define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
-#define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
-#define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0
-#define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40
-#define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80
-#define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
-#define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
-#define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
-#define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
-#define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
-#define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
-#define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
-#define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
-#define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1
-#define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
-#define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4
-#define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8
-#define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10
-#define B_SC_RA_RAM_LOCK__A 0x82004B
-#define B_SC_RA_RAM_LOCK_DEMOD__M 0x1
-#define B_SC_RA_RAM_LOCK_FEC__M 0x2
-#define B_SC_RA_RAM_LOCK_MPEG__M 0x4
-#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C
-#define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1
-#define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D
-#define B_SC_RA_RAM_CONFIG__A 0x820050
-#define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4
-#define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10
-#define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20
-#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200
-#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400
-#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D
-#define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E
-#define B_SC_RA_RAM_IF_SAVE__AX 0x82008E
-#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098
-#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099
-#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A
-#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B
-#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C
-#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D
-#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E
-#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F
-#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
-#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9
-#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2
-#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4
-#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3
-#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100
-#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4
-#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8
-#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5
-#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8
-#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6
-#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200
-#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7
-#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9
-#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8
-#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4
-#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9
-#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100
-#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA
-#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB
-#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB
-#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1
-#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC
-#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40
-#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD
-#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8
-#define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9
-#define B_SC_RA_RAM_BAND__A 0x8200EC
-#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4
-#define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F
-#define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5
-#define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F
-#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100
-#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4
-#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2
-#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4
-#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D
-#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5
-#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D
-#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4
-#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133
-#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5
-#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114
-#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5
-#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A
-#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4
-#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB
-#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4
-#define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE
-#define B_SC_RA_RAM_PROC_LOCKTRACK 0x0
-#define B_FE_COMM_EXEC__A 0xC00000
-#define B_FE_AD_REG_COMM_EXEC__A 0xC10000
-#define B_FE_AD_REG_FDB_IN__A 0xC10012
-#define B_FE_AD_REG_PD__A 0xC10013
-#define B_FE_AD_REG_INVEXT__A 0xC10014
-#define B_FE_AD_REG_CLKNEG__A 0xC10015
-#define B_FE_AG_REG_COMM_EXEC__A 0xC20000
-#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0
-#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000
-#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011
-#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8
-#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0
-#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8
-#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012
-#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0
-#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1
-#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013
-#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2
-#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0
-#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2
-#define B_FE_AG_REG_AG_PWD__A 0xC20015
-#define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2
-#define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0
-#define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2
-#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016
-#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017
-#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A
-#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B
-#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020
-#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024
-#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025
-#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF
-#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026
-#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027
-#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028
-#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029
-#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A
-#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B
-#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C
-#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D
-#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E
-#define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030
-#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF
-#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031
-#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032
-#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033
-#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034
-#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035
-#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF
-#define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036
-#define B_FE_AG_REG_IND_WIN__A 0xC2003C
-#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D
-#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E
-#define B_FE_AG_REG_IND_DEL__A 0xC2003F
-#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040
-#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041
-#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042
-#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043
-#define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044
-#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045
-#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046
-#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047
-#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048
-#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049
-#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A
-#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B
-#define B_FE_AG_REG_PDC_MAX__A 0xC2004C
-#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D
-#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E
-#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F
-#define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050
-#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051
-#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F
-#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052
-#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053
-#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054
-#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055
-#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056
-#define B_FE_AG_REG_FGM_WRI__A 0xC20061
-#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068
-#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069
-#define B_FE_FS_REG_COMM_EXEC__A 0xC30000
-#define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010
-#define B_FE_FD_REG_COMM_EXEC__A 0xC40000
-#define B_FE_FD_REG_SCL__A 0xC40010
-#define B_FE_FD_REG_MAX_LEV__A 0xC40011
-#define B_FE_FD_REG_NR__A 0xC40012
-#define B_FE_FD_REG_MEAS_VAL__A 0xC40014
-#define B_FE_IF_REG_COMM_EXEC__A 0xC50000
-#define B_FE_IF_REG_INCR0__A 0xC50010
-#define B_FE_IF_REG_INCR0__W 16
-#define B_FE_IF_REG_INCR0__M 0xFFFF
-#define B_FE_IF_REG_INCR1__A 0xC50011
-#define B_FE_IF_REG_INCR1__M 0xFF
-#define B_FE_CF_REG_COMM_EXEC__A 0xC60000
-#define B_FE_CF_REG_SCL__A 0xC60010
-#define B_FE_CF_REG_MAX_LEV__A 0xC60011
-#define B_FE_CF_REG_NR__A 0xC60012
-#define B_FE_CF_REG_IMP_VAL__A 0xC60013
-#define B_FE_CF_REG_MEAS_VAL__A 0xC60014
-#define B_FE_CU_REG_COMM_EXEC__A 0xC70000
-#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011
-#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012
-#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020
-#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021
-#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027
-#define B_FT_COMM_EXEC__A 0x1000000
-#define B_FT_REG_COMM_EXEC__A 0x1010000
-#define B_CP_COMM_EXEC__A 0x1400000
-#define B_CP_REG_COMM_EXEC__A 0x1410000
-#define B_CP_REG_INTERVAL__A 0x1410011
-#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023
-#define B_CP_REG_BR_STR_DEL__A 0x1410024
-#define B_CP_REG_RT_ANG_INC0__A 0x1410030
-#define B_CP_REG_RT_ANG_INC1__A 0x1410031
-#define B_CP_REG_RT_DETECT_TRH__A 0x1410033
-#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040
-#define B_CP_REG_AC_AVER_POW__A 0x1410041
-#define B_CP_REG_AC_MAX_POW__A 0x1410042
-#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043
-#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044
-#define B_CP_REG_AC_AMP_MODE__A 0x1410047
-#define B_CP_REG_AC_AMP_FIX__A 0x1410048
-#define B_CP_REG_AC_ANG_MODE__A 0x141004A
-#define B_CE_COMM_EXEC__A 0x1800000
-#define B_CE_REG_COMM_EXEC__A 0x1810000
-#define B_CE_REG_TAPSET__A 0x1810011
-#define B_CE_REG_AVG_POW__A 0x1810012
-#define B_CE_REG_MAX_POW__A 0x1810013
-#define B_CE_REG_ATT__A 0x1810014
-#define B_CE_REG_NRED__A 0x1810015
-#define B_CE_REG_NE_ERR_SELECT__A 0x1810043
-#define B_CE_REG_NE_TD_CAL__A 0x1810044
-#define B_CE_REG_NE_MIXAVG__A 0x1810046
-#define B_CE_REG_NE_NUPD_OFS__A 0x1810047
-#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050
-#define B_CE_REG_PE_TIMESHIFT__A 0x1810051
-#define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064
-#define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065
-#define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066
-#define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068
-#define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069
-#define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A
-#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073
-#define B_CE_REG_FI_SHT_INCR__A 0x1810090
-#define B_CE_REG_FI_EXP_NORM__A 0x1810091
-#define B_CE_REG_IR_INPUTSEL__A 0x18100A0
-#define B_CE_REG_IR_STARTPOS__A 0x18100A1
-#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2
-#define B_CE_REG_FR_TREAL00__A 0x1820010
-#define B_CE_REG_FR_TIMAG00__A 0x1820011
-#define B_CE_REG_FR_TREAL01__A 0x1820012
-#define B_CE_REG_FR_TIMAG01__A 0x1820013
-#define B_CE_REG_FR_TREAL02__A 0x1820014
-#define B_CE_REG_FR_TIMAG02__A 0x1820015
-#define B_CE_REG_FR_TREAL03__A 0x1820016
-#define B_CE_REG_FR_TIMAG03__A 0x1820017
-#define B_CE_REG_FR_TREAL04__A 0x1820018
-#define B_CE_REG_FR_TIMAG04__A 0x1820019
-#define B_CE_REG_FR_TREAL05__A 0x182001A
-#define B_CE_REG_FR_TIMAG05__A 0x182001B
-#define B_CE_REG_FR_TREAL06__A 0x182001C
-#define B_CE_REG_FR_TIMAG06__A 0x182001D
-#define B_CE_REG_FR_TREAL07__A 0x182001E
-#define B_CE_REG_FR_TIMAG07__A 0x182001F
-#define B_CE_REG_FR_TREAL08__A 0x1820020
-#define B_CE_REG_FR_TIMAG08__A 0x1820021
-#define B_CE_REG_FR_TREAL09__A 0x1820022
-#define B_CE_REG_FR_TIMAG09__A 0x1820023
-#define B_CE_REG_FR_TREAL10__A 0x1820024
-#define B_CE_REG_FR_TIMAG10__A 0x1820025
-#define B_CE_REG_FR_TREAL11__A 0x1820026
-#define B_CE_REG_FR_TIMAG11__A 0x1820027
-#define B_CE_REG_FR_MID_TAP__A 0x1820028
-#define B_CE_REG_FR_SQS_G00__A 0x1820029
-#define B_CE_REG_FR_SQS_G01__A 0x182002A
-#define B_CE_REG_FR_SQS_G02__A 0x182002B
-#define B_CE_REG_FR_SQS_G03__A 0x182002C
-#define B_CE_REG_FR_SQS_G04__A 0x182002D
-#define B_CE_REG_FR_SQS_G05__A 0x182002E
-#define B_CE_REG_FR_SQS_G06__A 0x182002F
-#define B_CE_REG_FR_SQS_G07__A 0x1820030
-#define B_CE_REG_FR_SQS_G08__A 0x1820031
-#define B_CE_REG_FR_SQS_G09__A 0x1820032
-#define B_CE_REG_FR_SQS_G10__A 0x1820033
-#define B_CE_REG_FR_SQS_G11__A 0x1820034
-#define B_CE_REG_FR_SQS_G12__A 0x1820035
-#define B_CE_REG_FR_RIO_G00__A 0x1820036
-#define B_CE_REG_FR_RIO_G01__A 0x1820037
-#define B_CE_REG_FR_RIO_G02__A 0x1820038
-#define B_CE_REG_FR_RIO_G03__A 0x1820039
-#define B_CE_REG_FR_RIO_G04__A 0x182003A
-#define B_CE_REG_FR_RIO_G05__A 0x182003B
-#define B_CE_REG_FR_RIO_G06__A 0x182003C
-#define B_CE_REG_FR_RIO_G07__A 0x182003D
-#define B_CE_REG_FR_RIO_G08__A 0x182003E
-#define B_CE_REG_FR_RIO_G09__A 0x182003F
-#define B_CE_REG_FR_RIO_G10__A 0x1820040
-#define B_CE_REG_FR_MODE__A 0x1820041
-#define B_CE_REG_FR_SQS_TRH__A 0x1820042
-#define B_CE_REG_FR_RIO_GAIN__A 0x1820043
-#define B_CE_REG_FR_BYPASS__A 0x1820044
-#define B_CE_REG_FR_PM_SET__A 0x1820045
-#define B_CE_REG_FR_ERR_SH__A 0x1820046
-#define B_CE_REG_FR_MAN_SH__A 0x1820047
-#define B_CE_REG_FR_TAP_SH__A 0x1820048
-#define B_EQ_COMM_EXEC__A 0x1C00000
-#define B_EQ_REG_COMM_EXEC__A 0x1C10000
-#define B_EQ_REG_COMM_MB__A 0x1C10002
-#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015
-#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016
-#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017
-#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A
-#define B_EQ_REG_SN_OFFSET__A 0x1C1002B
-#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032
-#define B_EQ_REG_RC_SEL_CAR_INIT 0x2
-#define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1
-#define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0
-#define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2
-#define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0
-#define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8
-#define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0
-#define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20
-#define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80
-#define B_EQ_REG_OT_CONST__A 0x1C10046
-#define B_EQ_REG_OT_ALPHA__A 0x1C10047
-#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048
-#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049
-#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A
-#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B
-#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061
-#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062
-#define B_EC_SB_REG_COMM_EXEC__A 0x2010000
-#define B_EC_SB_REG_TR_MODE__A 0x2010010
-#define B_EC_SB_REG_TR_MODE_8K 0x0
-#define B_EC_SB_REG_TR_MODE_2K 0x1
-#define B_EC_SB_REG_CONST__A 0x2010011
-#define B_EC_SB_REG_CONST_QPSK 0x0
-#define B_EC_SB_REG_CONST_16QAM 0x1
-#define B_EC_SB_REG_CONST_64QAM 0x2
-#define B_EC_SB_REG_ALPHA__A 0x2010012
-#define B_EC_SB_REG_PRIOR__A 0x2010013
-#define B_EC_SB_REG_PRIOR_HI 0x0
-#define B_EC_SB_REG_PRIOR_LO 0x1
-#define B_EC_SB_REG_CSI_HI__A 0x2010014
-#define B_EC_SB_REG_CSI_LO__A 0x2010015
-#define B_EC_SB_REG_SMB_TGL__A 0x2010016
-#define B_EC_SB_REG_SNR_HI__A 0x2010017
-#define B_EC_SB_REG_SNR_MID__A 0x2010018
-#define B_EC_SB_REG_SNR_LO__A 0x2010019
-#define B_EC_SB_REG_SCALE_MSB__A 0x201001A
-#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B
-#define B_EC_SB_REG_SCALE_LSB__A 0x201001C
-#define B_EC_SB_REG_CSI_OFS0__A 0x201001D
-#define B_EC_SB_REG_CSI_OFS1__A 0x201001E
-#define B_EC_SB_REG_CSI_OFS2__A 0x201001F
-#define B_EC_VD_REG_COMM_EXEC__A 0x2090000
-#define B_EC_VD_REG_FORCE__A 0x2090010
-#define B_EC_VD_REG_SET_CODERATE__A 0x2090011
-#define B_EC_VD_REG_SET_CODERATE_C1_2 0x0
-#define B_EC_VD_REG_SET_CODERATE_C2_3 0x1
-#define B_EC_VD_REG_SET_CODERATE_C3_4 0x2
-#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3
-#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4
-#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012
-#define B_EC_VD_REG_RLK_ENA__A 0x2090014
-#define B_EC_OD_REG_COMM_EXEC__A 0x2110000
-#define B_EC_OD_REG_SYNC__A 0x2110664
-#define B_EC_OD_DEINT_RAM__A 0x2120000
-#define B_EC_RS_REG_COMM_EXEC__A 0x2130000
-#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010
-#define B_EC_RS_REG_VAL__A 0x2130011
-#define B_EC_RS_REG_VAL_PCK 0x1
-#define B_EC_RS_EC_RAM__A 0x2140000
-#define B_EC_OC_REG_COMM_EXEC__A 0x2150000
-#define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1
-#define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2
-#define B_EC_OC_REG_COMM_INT_STA__A 0x2150007
-#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010
-#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1
-#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0
-#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1
-#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4
-#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0
-#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80
-#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80
-#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011
-#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10
-#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200
-#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0
-#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200
-#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012
-#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF
-#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014
-#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015
-#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016
-#define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0
-#define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D
-#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E
-#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F
-#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020
-#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021
-#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023
-#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024
-#define B_EC_OC_REG_RCN_MODE__A 0x2150027
-#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028
-#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029
-#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A
-#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B
-#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C
-#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D
-#define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032
-#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033
-#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034
-#define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035
-#define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036
-#define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF
-#define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0
-#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038
-#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045
-#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047
-#define B_EC_OC_REG_DTO_PER__A 0x2150048
-#define B_EC_OC_REG_DTO_BUR__A 0x2150049
-#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A
-#define B_CC_REG_OSC_MODE__A 0x2410010
-#define B_CC_REG_OSC_MODE_M20 0x1
-#define B_CC_REG_PLL_MODE__A 0x2410011
-#define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1
-#define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14
-#define B_CC_REG_REF_DIVIDE__A 0x2410012
-#define B_CC_REG_PWD_MODE__A 0x2410015
-#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2
-#define B_CC_REG_UPDATE__A 0x2410017
-#define B_CC_REG_UPDATE_KEY 0x3973
-#define B_CC_REG_JTAGID_L__A 0x2410019
-#define B_CC_REG_DIVERSITY__A 0x241001B
-#define B_LC_COMM_EXEC__A 0x2800000
-#define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C
-#define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A
-#define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8
-#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060
-#define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4
-#define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061
-#define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1
-#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068
-#define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4
-#define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069
-#define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1
-
-#endif
diff --git a/drivers/media/dvb/frontends/drxk.h b/drivers/media/dvb/frontends/drxk.h
deleted file mode 100644
index d615d7d055a..00000000000
--- a/drivers/media/dvb/frontends/drxk.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef _DRXK_H_
-#define _DRXK_H_
-
-#include <linux/types.h>
-#include <linux/i2c.h>
-
-/**
- * struct drxk_config - Configure the initial parameters for DRX-K
- *
- * @adr: I2C Address of the DRX-K
- * @parallel_ts: True means that the device uses parallel TS,
- * Serial otherwise.
- * @dynamic_clk: True means that the clock will be dynamically
- * adjusted. Static clock otherwise.
- * @enable_merr_cfg: Enable SIO_PDR_PERR_CFG/SIO_PDR_MVAL_CFG.
- * @single_master: Device is on the single master mode
- * @no_i2c_bridge: Don't switch the I2C bridge to talk with tuner
- * @antenna_gpio: GPIO bit used to control the antenna
- * @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1
- * means that 1=DVBC, 0 = DVBT. Zero means the opposite.
- * @mpeg_out_clk_strength: DRXK Mpeg output clock drive strength.
- * @microcode_name: Name of the firmware file with the microcode
- * @qam_demod_parameter_count: The number of parameters used for the command
- * to set the demodulator parameters. All
- * firmwares are using the 2-parameter commmand.
- * An exception is the "drxk_a3.mc" firmware,
- * which uses the 4-parameter command.
- * A value of 0 (default) or lower indicates that
- * the correct number of parameters will be
- * automatically detected.
- *
- * On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is
- * UIO-3.
- */
-struct drxk_config {
- u8 adr;
- bool single_master;
- bool no_i2c_bridge;
- bool parallel_ts;
- bool dynamic_clk;
- bool enable_merr_cfg;
-
- bool antenna_dvbt;
- u16 antenna_gpio;
-
- u8 mpeg_out_clk_strength;
- int chunk_size;
-
- const char *microcode_name;
- int qam_demod_parameter_count;
-};
-
-#if defined(CONFIG_DVB_DRXK) || (defined(CONFIG_DVB_DRXK_MODULE) \
- && defined(MODULE))
-extern struct dvb_frontend *drxk_attach(const struct drxk_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline struct dvb_frontend *drxk_attach(const struct drxk_config *config,
- struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif
diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c
deleted file mode 100644
index 1ab8154542d..00000000000
--- a/drivers/media/dvb/frontends/drxk_hard.c
+++ /dev/null
@@ -1,6637 +0,0 @@
-/*
- * drxk_hard: DRX-K DVB-C/T demodulator driver
- *
- * Copyright (C) 2010-2011 Digital Devices GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 only, as published by the Free Software Foundation.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/firmware.h>
-#include <linux/i2c.h>
-#include <linux/hardirq.h>
-#include <asm/div64.h>
-
-#include "dvb_frontend.h"
-#include "drxk.h"
-#include "drxk_hard.h"
-
-static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
-static int PowerDownQAM(struct drxk_state *state);
-static int SetDVBTStandard(struct drxk_state *state,
- enum OperationMode oMode);
-static int SetQAMStandard(struct drxk_state *state,
- enum OperationMode oMode);
-static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
- s32 tunerFreqOffset);
-static int SetDVBTStandard(struct drxk_state *state,
- enum OperationMode oMode);
-static int DVBTStart(struct drxk_state *state);
-static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
- s32 tunerFreqOffset);
-static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
-static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
-static int SwitchAntennaToQAM(struct drxk_state *state);
-static int SwitchAntennaToDVBT(struct drxk_state *state);
-
-static bool IsDVBT(struct drxk_state *state)
-{
- return state->m_OperationMode == OM_DVBT;
-}
-
-static bool IsQAM(struct drxk_state *state)
-{
- return state->m_OperationMode == OM_QAM_ITU_A ||
- state->m_OperationMode == OM_QAM_ITU_B ||
- state->m_OperationMode == OM_QAM_ITU_C;
-}
-
-bool IsA1WithPatchCode(struct drxk_state *state)
-{
- return state->m_DRXK_A1_PATCH_CODE;
-}
-
-bool IsA1WithRomCode(struct drxk_state *state)
-{
- return state->m_DRXK_A1_ROM_CODE;
-}
-
-#define NOA1ROM 0
-
-#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
-#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
-
-#define DEFAULT_MER_83 165
-#define DEFAULT_MER_93 250
-
-#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
-#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
-#endif
-
-#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
-#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
-#endif
-
-#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
-#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
-
-#ifndef DRXK_KI_RAGC_ATV
-#define DRXK_KI_RAGC_ATV 4
-#endif
-#ifndef DRXK_KI_IAGC_ATV
-#define DRXK_KI_IAGC_ATV 6
-#endif
-#ifndef DRXK_KI_DAGC_ATV
-#define DRXK_KI_DAGC_ATV 7
-#endif
-
-#ifndef DRXK_KI_RAGC_QAM
-#define DRXK_KI_RAGC_QAM 3
-#endif
-#ifndef DRXK_KI_IAGC_QAM
-#define DRXK_KI_IAGC_QAM 4
-#endif
-#ifndef DRXK_KI_DAGC_QAM
-#define DRXK_KI_DAGC_QAM 7
-#endif
-#ifndef DRXK_KI_RAGC_DVBT
-#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
-#endif
-#ifndef DRXK_KI_IAGC_DVBT
-#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
-#endif
-#ifndef DRXK_KI_DAGC_DVBT
-#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
-#endif
-
-#ifndef DRXK_AGC_DAC_OFFSET
-#define DRXK_AGC_DAC_OFFSET (0x800)
-#endif
-
-#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
-#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
-#endif
-
-#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
-#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
-#endif
-
-#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
-#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
-#endif
-
-#ifndef DRXK_QAM_SYMBOLRATE_MAX
-#define DRXK_QAM_SYMBOLRATE_MAX (7233000)
-#endif
-
-#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
-#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
-#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
-#define DRXK_BL_ROM_OFFSET_TAPS_BG 24
-#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
-#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
-#define DRXK_BL_ROM_OFFSET_TAPS_FM 48
-#define DRXK_BL_ROM_OFFSET_UCODE 0
-
-#define DRXK_BLC_TIMEOUT 100
-
-#define DRXK_BLCC_NR_ELEMENTS_TAPS 2
-#define DRXK_BLCC_NR_ELEMENTS_UCODE 6
-
-#define DRXK_BLDC_NR_ELEMENTS_TAPS 28
-
-#ifndef DRXK_OFDM_NE_NOTCH_WIDTH
-#define DRXK_OFDM_NE_NOTCH_WIDTH (4)
-#endif
-
-#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
-#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
-#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
-#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
-#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
-
-static unsigned int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "enable debug messages");
-
-#define dprintk(level, fmt, arg...) do { \
-if (debug >= level) \
- printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
-} while (0)
-
-
-static inline u32 MulDiv32(u32 a, u32 b, u32 c)
-{
- u64 tmp64;
-
- tmp64 = (u64) a * (u64) b;
- do_div(tmp64, c);
-
- return (u32) tmp64;
-}
-
-inline u32 Frac28a(u32 a, u32 c)
-{
- int i = 0;
- u32 Q1 = 0;
- u32 R0 = 0;
-
- R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
- Q1 = a / c; /* integer part, only the 4 least significant bits
- will be visible in the result */
-
- /* division using radix 16, 7 nibbles in the result */
- for (i = 0; i < 7; i++) {
- Q1 = (Q1 << 4) | (R0 / c);
- R0 = (R0 % c) << 4;
- }
- /* rounding */
- if ((R0 >> 3) >= c)
- Q1++;
-
- return Q1;
-}
-
-static u32 Log10Times100(u32 x)
-{
- static const u8 scale = 15;
- static const u8 indexWidth = 5;
- u8 i = 0;
- u32 y = 0;
- u32 d = 0;
- u32 k = 0;
- u32 r = 0;
- /*
- log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
- 0 <= n < ((1<<INDEXWIDTH)+1)
- */
-
- static const u32 log2lut[] = {
- 0, /* 0.000000 */
- 290941, /* 290941.300628 */
- 573196, /* 573196.476418 */
- 847269, /* 847269.179851 */
- 1113620, /* 1113620.489452 */
- 1372674, /* 1372673.576986 */
- 1624818, /* 1624817.752104 */
- 1870412, /* 1870411.981536 */
- 2109788, /* 2109787.962654 */
- 2343253, /* 2343252.817465 */
- 2571091, /* 2571091.461923 */
- 2793569, /* 2793568.696416 */
- 3010931, /* 3010931.055901 */
- 3223408, /* 3223408.452106 */
- 3431216, /* 3431215.635215 */
- 3634553, /* 3634553.498355 */
- 3833610, /* 3833610.244726 */
- 4028562, /* 4028562.434393 */
- 4219576, /* 4219575.925308 */
- 4406807, /* 4406806.721144 */
- 4590402, /* 4590401.736809 */
- 4770499, /* 4770499.491025 */
- 4947231, /* 4947230.734179 */
- 5120719, /* 5120719.018555 */
- 5291081, /* 5291081.217197 */
- 5458428, /* 5458427.996830 */
- 5622864, /* 5622864.249668 */
- 5784489, /* 5784489.488298 */
- 5943398, /* 5943398.207380 */
- 6099680, /* 6099680.215452 */
- 6253421, /* 6253420.939751 */
- 6404702, /* 6404701.706649 */
- 6553600, /* 6553600.000000 */
- };
-
-
- if (x == 0)
- return 0;
-
- /* Scale x (normalize) */
- /* computing y in log(x/y) = log(x) - log(y) */
- if ((x & ((0xffffffff) << (scale + 1))) == 0) {
- for (k = scale; k > 0; k--) {
- if (x & (((u32) 1) << scale))
- break;
- x <<= 1;
- }
- } else {
- for (k = scale; k < 31; k++) {
- if ((x & (((u32) (-1)) << (scale + 1))) == 0)
- break;
- x >>= 1;
- }
- }
- /*
- Now x has binary point between bit[scale] and bit[scale-1]
- and 1.0 <= x < 2.0 */
-
- /* correction for divison: log(x) = log(x/y)+log(y) */
- y = k * ((((u32) 1) << scale) * 200);
-
- /* remove integer part */
- x &= ((((u32) 1) << scale) - 1);
- /* get index */
- i = (u8) (x >> (scale - indexWidth));
- /* compute delta (x - a) */
- d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
- /* compute log, multiplication (d* (..)) must be within range ! */
- y += log2lut[i] +
- ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
- /* Conver to log10() */
- y /= 108853; /* (log2(10) << scale) */
- r = (y >> 1);
- /* rounding */
- if (y & ((u32) 1))
- r++;
- return r;
-}
-
-/****************************************************************************/
-/* I2C **********************************************************************/
-/****************************************************************************/
-
-static int drxk_i2c_lock(struct drxk_state *state)
-{
- i2c_lock_adapter(state->i2c);
- state->drxk_i2c_exclusive_lock = true;
-
- return 0;
-}
-
-static void drxk_i2c_unlock(struct drxk_state *state)
-{
- if (!state->drxk_i2c_exclusive_lock)
- return;
-
- i2c_unlock_adapter(state->i2c);
- state->drxk_i2c_exclusive_lock = false;
-}
-
-static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
- unsigned len)
-{
- if (state->drxk_i2c_exclusive_lock)
- return __i2c_transfer(state->i2c, msgs, len);
- else
- return i2c_transfer(state->i2c, msgs, len);
-}
-
-static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
-{
- struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
- .buf = val, .len = 1}
- };
-
- return drxk_i2c_transfer(state, msgs, 1);
-}
-
-static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
-{
- int status;
- struct i2c_msg msg = {
- .addr = adr, .flags = 0, .buf = data, .len = len };
-
- dprintk(3, ":");
- if (debug > 2) {
- int i;
- for (i = 0; i < len; i++)
- printk(KERN_CONT " %02x", data[i]);
- printk(KERN_CONT "\n");
- }
- status = drxk_i2c_transfer(state, &msg, 1);
- if (status >= 0 && status != 1)
- status = -EIO;
-
- if (status < 0)
- printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
-
- return status;
-}
-
-static int i2c_read(struct drxk_state *state,
- u8 adr, u8 *msg, int len, u8 *answ, int alen)
-{
- int status;
- struct i2c_msg msgs[2] = {
- {.addr = adr, .flags = 0,
- .buf = msg, .len = len},
- {.addr = adr, .flags = I2C_M_RD,
- .buf = answ, .len = alen}
- };
-
- status = drxk_i2c_transfer(state, msgs, 2);
- if (status != 2) {
- if (debug > 2)
- printk(KERN_CONT ": ERROR!\n");
- if (status >= 0)
- status = -EIO;
-
- printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
- return status;
- }
- if (debug > 2) {
- int i;
- dprintk(2, ": read from");
- for (i = 0; i < len; i++)
- printk(KERN_CONT " %02x", msg[i]);
- printk(KERN_CONT ", value = ");
- for (i = 0; i < alen; i++)
- printk(KERN_CONT " %02x", answ[i]);
- printk(KERN_CONT "\n");
- }
- return 0;
-}
-
-static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
-{
- int status;
- u8 adr = state->demod_address, mm1[4], mm2[2], len;
-
- if (state->single_master)
- flags |= 0xC0;
-
- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
- mm1[0] = (((reg << 1) & 0xFF) | 0x01);
- mm1[1] = ((reg >> 16) & 0xFF);
- mm1[2] = ((reg >> 24) & 0xFF) | flags;
- mm1[3] = ((reg >> 7) & 0xFF);
- len = 4;
- } else {
- mm1[0] = ((reg << 1) & 0xFF);
- mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
- len = 2;
- }
- dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
- status = i2c_read(state, adr, mm1, len, mm2, 2);
- if (status < 0)
- return status;
- if (data)
- *data = mm2[0] | (mm2[1] << 8);
-
- return 0;
-}
-
-static int read16(struct drxk_state *state, u32 reg, u16 *data)
-{
- return read16_flags(state, reg, data, 0);
-}
-
-static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
-{
- int status;
- u8 adr = state->demod_address, mm1[4], mm2[4], len;
-
- if (state->single_master)
- flags |= 0xC0;
-
- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
- mm1[0] = (((reg << 1) & 0xFF) | 0x01);
- mm1[1] = ((reg >> 16) & 0xFF);
- mm1[2] = ((reg >> 24) & 0xFF) | flags;
- mm1[3] = ((reg >> 7) & 0xFF);
- len = 4;
- } else {
- mm1[0] = ((reg << 1) & 0xFF);
- mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
- len = 2;
- }
- dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
- status = i2c_read(state, adr, mm1, len, mm2, 4);
- if (status < 0)
- return status;
- if (data)
- *data = mm2[0] | (mm2[1] << 8) |
- (mm2[2] << 16) | (mm2[3] << 24);
-
- return 0;
-}
-
-static int read32(struct drxk_state *state, u32 reg, u32 *data)
-{
- return read32_flags(state, reg, data, 0);
-}
-
-static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
-{
- u8 adr = state->demod_address, mm[6], len;
-
- if (state->single_master)
- flags |= 0xC0;
- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
- mm[0] = (((reg << 1) & 0xFF) | 0x01);
- mm[1] = ((reg >> 16) & 0xFF);
- mm[2] = ((reg >> 24) & 0xFF) | flags;
- mm[3] = ((reg >> 7) & 0xFF);
- len = 4;
- } else {
- mm[0] = ((reg << 1) & 0xFF);
- mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
- len = 2;
- }
- mm[len] = data & 0xff;
- mm[len + 1] = (data >> 8) & 0xff;
-
- dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
- return i2c_write(state, adr, mm, len + 2);
-}
-
-static int write16(struct drxk_state *state, u32 reg, u16 data)
-{
- return write16_flags(state, reg, data, 0);
-}
-
-static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
-{
- u8 adr = state->demod_address, mm[8], len;
-
- if (state->single_master)
- flags |= 0xC0;
- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
- mm[0] = (((reg << 1) & 0xFF) | 0x01);
- mm[1] = ((reg >> 16) & 0xFF);
- mm[2] = ((reg >> 24) & 0xFF) | flags;
- mm[3] = ((reg >> 7) & 0xFF);
- len = 4;
- } else {
- mm[0] = ((reg << 1) & 0xFF);
- mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
- len = 2;
- }
- mm[len] = data & 0xff;
- mm[len + 1] = (data >> 8) & 0xff;
- mm[len + 2] = (data >> 16) & 0xff;
- mm[len + 3] = (data >> 24) & 0xff;
- dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
-
- return i2c_write(state, adr, mm, len + 4);
-}
-
-static int write32(struct drxk_state *state, u32 reg, u32 data)
-{
- return write32_flags(state, reg, data, 0);
-}
-
-static int write_block(struct drxk_state *state, u32 Address,
- const int BlockSize, const u8 pBlock[])
-{
- int status = 0, BlkSize = BlockSize;
- u8 Flags = 0;
-
- if (state->single_master)
- Flags |= 0xC0;
-
- while (BlkSize > 0) {
- int Chunk = BlkSize > state->m_ChunkSize ?
- state->m_ChunkSize : BlkSize;
- u8 *AdrBuf = &state->Chunk[0];
- u32 AdrLength = 0;
-
- if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
- AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
- AdrBuf[1] = ((Address >> 16) & 0xFF);
- AdrBuf[2] = ((Address >> 24) & 0xFF);
- AdrBuf[3] = ((Address >> 7) & 0xFF);
- AdrBuf[2] |= Flags;
- AdrLength = 4;
- if (Chunk == state->m_ChunkSize)
- Chunk -= 2;
- } else {
- AdrBuf[0] = ((Address << 1) & 0xFF);
- AdrBuf[1] = (((Address >> 16) & 0x0F) |
- ((Address >> 18) & 0xF0));
- AdrLength = 2;
- }
- memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
- dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
- if (debug > 1) {
- int i;
- if (pBlock)
- for (i = 0; i < Chunk; i++)
- printk(KERN_CONT " %02x", pBlock[i]);
- printk(KERN_CONT "\n");
- }
- status = i2c_write(state, state->demod_address,
- &state->Chunk[0], Chunk + AdrLength);
- if (status < 0) {
- printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
- __func__, Address);
- break;
- }
- pBlock += Chunk;
- Address += (Chunk >> 1);
- BlkSize -= Chunk;
- }
- return status;
-}
-
-#ifndef DRXK_MAX_RETRIES_POWERUP
-#define DRXK_MAX_RETRIES_POWERUP 20
-#endif
-
-int PowerUpDevice(struct drxk_state *state)
-{
- int status;
- u8 data = 0;
- u16 retryCount = 0;
-
- dprintk(1, "\n");
-
- status = i2c_read1(state, state->demod_address, &data);
- if (status < 0) {
- do {
- data = 0;
- status = i2c_write(state, state->demod_address,
- &data, 1);
- msleep(10);
- retryCount++;
- if (status < 0)
- continue;
- status = i2c_read1(state, state->demod_address,
- &data);
- } while (status < 0 &&
- (retryCount < DRXK_MAX_RETRIES_POWERUP));
- if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
- goto error;
- }
-
- /* Make sure all clk domains are active */
- status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
- if (status < 0)
- goto error;
- status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
- if (status < 0)
- goto error;
- /* Enable pll lock tests */
- status = write16(state, SIO_CC_PLL_LOCK__A, 1);
- if (status < 0)
- goto error;
-
- state->m_currentPowerMode = DRX_POWER_UP;
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-
-static int init_state(struct drxk_state *state)
-{
- /*
- * FIXME: most (all?) of the values bellow should be moved into
- * struct drxk_config, as they are probably board-specific
- */
- u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
- u32 ulVSBIfAgcOutputLevel = 0;
- u32 ulVSBIfAgcMinLevel = 0;
- u32 ulVSBIfAgcMaxLevel = 0x7FFF;
- u32 ulVSBIfAgcSpeed = 3;
-
- u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
- u32 ulVSBRfAgcOutputLevel = 0;
- u32 ulVSBRfAgcMinLevel = 0;
- u32 ulVSBRfAgcMaxLevel = 0x7FFF;
- u32 ulVSBRfAgcSpeed = 3;
- u32 ulVSBRfAgcTop = 9500;
- u32 ulVSBRfAgcCutOffCurrent = 4000;
-
- u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
- u32 ulATVIfAgcOutputLevel = 0;
- u32 ulATVIfAgcMinLevel = 0;
- u32 ulATVIfAgcMaxLevel = 0;
- u32 ulATVIfAgcSpeed = 3;
-
- u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
- u32 ulATVRfAgcOutputLevel = 0;
- u32 ulATVRfAgcMinLevel = 0;
- u32 ulATVRfAgcMaxLevel = 0;
- u32 ulATVRfAgcTop = 9500;
- u32 ulATVRfAgcCutOffCurrent = 4000;
- u32 ulATVRfAgcSpeed = 3;
-
- u32 ulQual83 = DEFAULT_MER_83;
- u32 ulQual93 = DEFAULT_MER_93;
-
- u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
- u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
-
- /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
- /* io_pad_cfg_mode output mode is drive always */
- /* io_pad_cfg_drive is set to power 2 (23 mA) */
- u32 ulGPIOCfg = 0x0113;
- u32 ulInvertTSClock = 0;
- u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
- u32 ulDVBTBitrate = 50000000;
- u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
-
- u32 ulInsertRSByte = 0;
-
- u32 ulRfMirror = 1;
- u32 ulPowerDown = 0;
-
- dprintk(1, "\n");
-
- state->m_hasLNA = false;
- state->m_hasDVBT = false;
- state->m_hasDVBC = false;
- state->m_hasATV = false;
- state->m_hasOOB = false;
- state->m_hasAudio = false;
-
- if (!state->m_ChunkSize)
- state->m_ChunkSize = 124;
-
- state->m_oscClockFreq = 0;
- state->m_smartAntInverted = false;
- state->m_bPDownOpenBridge = false;
-
- /* real system clock frequency in kHz */
- state->m_sysClockFreq = 151875;
- /* Timing div, 250ns/Psys */
- /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
- state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
- HI_I2C_DELAY) / 1000;
- /* Clipping */
- if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
- state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
- state->m_HICfgWakeUpKey = (state->demod_address << 1);
- /* port/bridge/power down ctrl */
- state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
-
- state->m_bPowerDown = (ulPowerDown != 0);
-
- state->m_DRXK_A1_PATCH_CODE = false;
- state->m_DRXK_A1_ROM_CODE = false;
- state->m_DRXK_A2_ROM_CODE = false;
- state->m_DRXK_A3_ROM_CODE = false;
- state->m_DRXK_A2_PATCH_CODE = false;
- state->m_DRXK_A3_PATCH_CODE = false;
-
- /* Init AGC and PGA parameters */
- /* VSB IF */
- state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
- state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
- state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
- state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
- state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
- state->m_vsbPgaCfg = 140;
-
- /* VSB RF */
- state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
- state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
- state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
- state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
- state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
- state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
- state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
- state->m_vsbPreSawCfg.reference = 0x07;
- state->m_vsbPreSawCfg.usePreSaw = true;
-
- state->m_Quality83percent = DEFAULT_MER_83;
- state->m_Quality93percent = DEFAULT_MER_93;
- if (ulQual93 <= 500 && ulQual83 < ulQual93) {
- state->m_Quality83percent = ulQual83;
- state->m_Quality93percent = ulQual93;
- }
-
- /* ATV IF */
- state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
- state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
- state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
- state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
- state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
-
- /* ATV RF */
- state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
- state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
- state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
- state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
- state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
- state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
- state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
- state->m_atvPreSawCfg.reference = 0x04;
- state->m_atvPreSawCfg.usePreSaw = true;
-
-
- /* DVBT RF */
- state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
- state->m_dvbtRfAgcCfg.outputLevel = 0;
- state->m_dvbtRfAgcCfg.minOutputLevel = 0;
- state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
- state->m_dvbtRfAgcCfg.top = 0x2100;
- state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
- state->m_dvbtRfAgcCfg.speed = 1;
-
-
- /* DVBT IF */
- state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
- state->m_dvbtIfAgcCfg.outputLevel = 0;
- state->m_dvbtIfAgcCfg.minOutputLevel = 0;
- state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
- state->m_dvbtIfAgcCfg.top = 13424;
- state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
- state->m_dvbtIfAgcCfg.speed = 3;
- state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
- state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
- /* state->m_dvbtPgaCfg = 140; */
-
- state->m_dvbtPreSawCfg.reference = 4;
- state->m_dvbtPreSawCfg.usePreSaw = false;
-
- /* QAM RF */
- state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
- state->m_qamRfAgcCfg.outputLevel = 0;
- state->m_qamRfAgcCfg.minOutputLevel = 6023;
- state->m_qamRfAgcCfg.maxOutputLevel = 27000;
- state->m_qamRfAgcCfg.top = 0x2380;
- state->m_qamRfAgcCfg.cutOffCurrent = 4000;
- state->m_qamRfAgcCfg.speed = 3;
-
- /* QAM IF */
- state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
- state->m_qamIfAgcCfg.outputLevel = 0;
- state->m_qamIfAgcCfg.minOutputLevel = 0;
- state->m_qamIfAgcCfg.maxOutputLevel = 9000;
- state->m_qamIfAgcCfg.top = 0x0511;
- state->m_qamIfAgcCfg.cutOffCurrent = 0;
- state->m_qamIfAgcCfg.speed = 3;
- state->m_qamIfAgcCfg.IngainTgtMax = 5119;
- state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
-
- state->m_qamPgaCfg = 140;
- state->m_qamPreSawCfg.reference = 4;
- state->m_qamPreSawCfg.usePreSaw = false;
-
- state->m_OperationMode = OM_NONE;
- state->m_DrxkState = DRXK_UNINITIALIZED;
-
- /* MPEG output configuration */
- state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
- state->m_insertRSByte = false; /* If TRUE; insert RS byte */
- state->m_invertDATA = false; /* If TRUE; invert DATA signals */
- state->m_invertERR = false; /* If TRUE; invert ERR signal */
- state->m_invertSTR = false; /* If TRUE; invert STR signals */
- state->m_invertVAL = false; /* If TRUE; invert VAL signals */
- state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
-
- /* If TRUE; static MPEG clockrate will be used;
- otherwise clockrate will adapt to the bitrate of the TS */
-
- state->m_DVBTBitrate = ulDVBTBitrate;
- state->m_DVBCBitrate = ulDVBCBitrate;
-
- state->m_TSDataStrength = (ulTSDataStrength & 0x07);
-
- /* Maximum bitrate in b/s in case static clockrate is selected */
- state->m_mpegTsStaticBitrate = 19392658;
- state->m_disableTEIhandling = false;
-
- if (ulInsertRSByte)
- state->m_insertRSByte = true;
-
- state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
- if (ulMpegLockTimeOut < 10000)
- state->m_MpegLockTimeOut = ulMpegLockTimeOut;
- state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
- if (ulDemodLockTimeOut < 10000)
- state->m_DemodLockTimeOut = ulDemodLockTimeOut;
-
- /* QAM defaults */
- state->m_Constellation = DRX_CONSTELLATION_AUTO;
- state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
- state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
- state->m_fecRsPrescale = 1;
-
- state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
- state->m_agcFastClipCtrlDelay = 0;
-
- state->m_GPIOCfg = (ulGPIOCfg);
-
- state->m_bPowerDown = false;
- state->m_currentPowerMode = DRX_POWER_DOWN;
-
- state->m_rfmirror = (ulRfMirror == 0);
- state->m_IfAgcPol = false;
- return 0;
-}
-
-static int DRXX_Open(struct drxk_state *state)
-{
- int status = 0;
- u32 jtag = 0;
- u16 bid = 0;
- u16 key = 0;
-
- dprintk(1, "\n");
- /* stop lock indicator process */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
- if (status < 0)
- goto error;
- /* Check device id */
- status = read16(state, SIO_TOP_COMM_KEY__A, &key);
- if (status < 0)
- goto error;
- status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
- if (status < 0)
- goto error;
- status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
- if (status < 0)
- goto error;
- status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
- if (status < 0)
- goto error;
- status = write16(state, SIO_TOP_COMM_KEY__A, key);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int GetDeviceCapabilities(struct drxk_state *state)
-{
- u16 sioPdrOhwCfg = 0;
- u32 sioTopJtagidLo = 0;
- int status;
- const char *spin = "";
-
- dprintk(1, "\n");
-
- /* driver 0.9.0 */
- /* stop lock indicator process */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
- if (status < 0)
- goto error;
- status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
- if (status < 0)
- goto error;
- status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
- if (status < 0)
- goto error;
- status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
- if (status < 0)
- goto error;
-
- switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
- case 0:
- /* ignore (bypass ?) */
- break;
- case 1:
- /* 27 MHz */
- state->m_oscClockFreq = 27000;
- break;
- case 2:
- /* 20.25 MHz */
- state->m_oscClockFreq = 20250;
- break;
- case 3:
- /* 4 MHz */
- state->m_oscClockFreq = 20250;
- break;
- default:
- printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
- return -EINVAL;
- }
- /*
- Determine device capabilities
- Based on pinning v14
- */
- status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
- if (status < 0)
- goto error;
-
- printk(KERN_INFO "drxk: status = 0x%08x\n", sioTopJtagidLo);
-
- /* driver 0.9.0 */
- switch ((sioTopJtagidLo >> 29) & 0xF) {
- case 0:
- state->m_deviceSpin = DRXK_SPIN_A1;
- spin = "A1";
- break;
- case 2:
- state->m_deviceSpin = DRXK_SPIN_A2;
- spin = "A2";
- break;
- case 3:
- state->m_deviceSpin = DRXK_SPIN_A3;
- spin = "A3";
- break;
- default:
- state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
- status = -EINVAL;
- printk(KERN_ERR "drxk: Spin %d unknown\n",
- (sioTopJtagidLo >> 29) & 0xF);
- goto error2;
- }
- switch ((sioTopJtagidLo >> 12) & 0xFF) {
- case 0x13:
- /* typeId = DRX3913K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = false;
- state->m_hasAudio = false;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
- state->m_hasSAWSW = true;
- state->m_hasGPIO2 = false;
- state->m_hasGPIO1 = false;
- state->m_hasIRQN = false;
- break;
- case 0x15:
- /* typeId = DRX3915K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
- state->m_hasAudio = false;
- state->m_hasDVBT = true;
- state->m_hasDVBC = false;
- state->m_hasSAWSW = true;
- state->m_hasGPIO2 = true;
- state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
- break;
- case 0x16:
- /* typeId = DRX3916K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
- state->m_hasAudio = false;
- state->m_hasDVBT = true;
- state->m_hasDVBC = false;
- state->m_hasSAWSW = true;
- state->m_hasGPIO2 = true;
- state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
- break;
- case 0x18:
- /* typeId = DRX3918K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
- state->m_hasAudio = true;
- state->m_hasDVBT = true;
- state->m_hasDVBC = false;
- state->m_hasSAWSW = true;
- state->m_hasGPIO2 = true;
- state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
- break;
- case 0x21:
- /* typeId = DRX3921K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
- state->m_hasAudio = true;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
- state->m_hasSAWSW = true;
- state->m_hasGPIO2 = true;
- state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
- break;
- case 0x23:
- /* typeId = DRX3923K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
- state->m_hasAudio = true;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
- state->m_hasSAWSW = true;
- state->m_hasGPIO2 = true;
- state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
- break;
- case 0x25:
- /* typeId = DRX3925K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
- state->m_hasAudio = true;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
- state->m_hasSAWSW = true;
- state->m_hasGPIO2 = true;
- state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
- break;
- case 0x26:
- /* typeId = DRX3926K_TYPE_ID */
- state->m_hasLNA = false;
- state->m_hasOOB = false;
- state->m_hasATV = true;
- state->m_hasAudio = false;
- state->m_hasDVBT = true;
- state->m_hasDVBC = true;
- state->m_hasSAWSW = true;
- state->m_hasGPIO2 = true;
- state->m_hasGPIO1 = true;
- state->m_hasIRQN = false;
- break;
- default:
- printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
- ((sioTopJtagidLo >> 12) & 0xFF));
- status = -EINVAL;
- goto error2;
- }
-
- printk(KERN_INFO
- "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
- ((sioTopJtagidLo >> 12) & 0xFF), spin,
- state->m_oscClockFreq / 1000,
- state->m_oscClockFreq % 1000);
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
-error2:
- return status;
-}
-
-static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
-{
- int status;
- bool powerdown_cmd;
-
- dprintk(1, "\n");
-
- /* Write command */
- status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
- if (status < 0)
- goto error;
- if (cmd == SIO_HI_RA_RAM_CMD_RESET)
- msleep(1);
-
- powerdown_cmd =
- (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
- ((state->m_HICfgCtrl) &
- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
- if (powerdown_cmd == false) {
- /* Wait until command rdy */
- u32 retryCount = 0;
- u16 waitCmd;
-
- do {
- msleep(1);
- retryCount += 1;
- status = read16(state, SIO_HI_RA_RAM_CMD__A,
- &waitCmd);
- } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
- && (waitCmd != 0));
- if (status < 0)
- goto error;
- status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
- }
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-static int HI_CfgCommand(struct drxk_state *state)
-{
- int status;
-
- dprintk(1, "\n");
-
- mutex_lock(&state->mutex);
-
- status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
- if (status < 0)
- goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
- if (status < 0)
- goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
- if (status < 0)
- goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
- if (status < 0)
- goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
- if (status < 0)
- goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
- if (status < 0)
- goto error;
- status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
- if (status < 0)
- goto error;
-
- state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
-error:
- mutex_unlock(&state->mutex);
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int InitHI(struct drxk_state *state)
-{
- dprintk(1, "\n");
-
- state->m_HICfgWakeUpKey = (state->demod_address << 1);
- state->m_HICfgTimeout = 0x96FF;
- /* port/bridge/power down ctrl */
- state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
-
- return HI_CfgCommand(state);
-}
-
-static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
-{
- int status = -1;
- u16 sioPdrMclkCfg = 0;
- u16 sioPdrMdxCfg = 0;
- u16 err_cfg = 0;
-
- dprintk(1, ": mpeg %s, %s mode\n",
- mpegEnable ? "enable" : "disable",
- state->m_enableParallel ? "parallel" : "serial");
-
- /* stop lock indicator process */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
- if (status < 0)
- goto error;
-
- /* MPEG TS pad configuration */
- status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
- if (status < 0)
- goto error;
-
- if (mpegEnable == false) {
- /* Set MPEG TS pads to inputmode */
- status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- } else {
- /* Enable MPEG output */
- sioPdrMdxCfg =
- ((state->m_TSDataStrength <<
- SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
- sioPdrMclkCfg = ((state->m_TSClockkStrength <<
- SIO_PDR_MCLK_CFG_DRIVE__B) |
- 0x0003);
-
- status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
- if (status < 0)
- goto error;
-
- if (state->enable_merr_cfg)
- err_cfg = sioPdrMdxCfg;
-
- status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
- if (status < 0)
- goto error;
-
- if (state->m_enableParallel == true) {
- /* paralel -> enable MD1 to MD7 */
- status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
- if (status < 0)
- goto error;
- } else {
- sioPdrMdxCfg = ((state->m_TSDataStrength <<
- SIO_PDR_MD0_CFG_DRIVE__B)
- | 0x0003);
- /* serial -> disable MD1 to MD7 */
- status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- }
- status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
- if (status < 0)
- goto error;
- status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
- if (status < 0)
- goto error;
- }
- /* Enable MB output over MPEG pads and ctl input */
- status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
- if (status < 0)
- goto error;
- /* Write nomagic word to enable pdr reg write */
- status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int MPEGTSDisable(struct drxk_state *state)
-{
- dprintk(1, "\n");
-
- return MPEGTSConfigurePins(state, false);
-}
-
-static int BLChainCmd(struct drxk_state *state,
- u16 romOffset, u16 nrOfElements, u32 timeOut)
-{
- u16 blStatus = 0;
- int status;
- unsigned long end;
-
- dprintk(1, "\n");
- mutex_lock(&state->mutex);
- status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
- if (status < 0)
- goto error;
- status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
- if (status < 0)
- goto error;
- status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
- if (status < 0)
- goto error;
- status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
- if (status < 0)
- goto error;
-
- end = jiffies + msecs_to_jiffies(timeOut);
- do {
- msleep(1);
- status = read16(state, SIO_BL_STATUS__A, &blStatus);
- if (status < 0)
- goto error;
- } while ((blStatus == 0x1) &&
- ((time_is_after_jiffies(end))));
-
- if (blStatus == 0x1) {
- printk(KERN_ERR "drxk: SIO not ready\n");
- status = -EINVAL;
- goto error2;
- }
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-error2:
- mutex_unlock(&state->mutex);
- return status;
-}
-
-
-static int DownloadMicrocode(struct drxk_state *state,
- const u8 pMCImage[], u32 Length)
-{
- const u8 *pSrc = pMCImage;
- u32 Address;
- u16 nBlocks;
- u16 BlockSize;
- u32 offset = 0;
- u32 i;
- int status = 0;
-
- dprintk(1, "\n");
-
- /* down the drain (we don't care about MAGIC_WORD) */
-#if 0
- /* For future reference */
- Drain = (pSrc[0] << 8) | pSrc[1];
-#endif
- pSrc += sizeof(u16);
- offset += sizeof(u16);
- nBlocks = (pSrc[0] << 8) | pSrc[1];
- pSrc += sizeof(u16);
- offset += sizeof(u16);
-
- for (i = 0; i < nBlocks; i += 1) {
- Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
- (pSrc[2] << 8) | pSrc[3];
- pSrc += sizeof(u32);
- offset += sizeof(u32);
-
- BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
- pSrc += sizeof(u16);
- offset += sizeof(u16);
-
-#if 0
- /* For future reference */
- Flags = (pSrc[0] << 8) | pSrc[1];
-#endif
- pSrc += sizeof(u16);
- offset += sizeof(u16);
-
-#if 0
- /* For future reference */
- BlockCRC = (pSrc[0] << 8) | pSrc[1];
-#endif
- pSrc += sizeof(u16);
- offset += sizeof(u16);
-
- if (offset + BlockSize > Length) {
- printk(KERN_ERR "drxk: Firmware is corrupted.\n");
- return -EINVAL;
- }
-
- status = write_block(state, Address, BlockSize, pSrc);
- if (status < 0) {
- printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
- break;
- }
- pSrc += BlockSize;
- offset += BlockSize;
- }
- return status;
-}
-
-static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
-{
- int status;
- u16 data = 0;
- u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
- u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
- unsigned long end;
-
- dprintk(1, "\n");
-
- if (enable == false) {
- desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
- desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
- }
-
- status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
- if (status >= 0 && data == desiredStatus) {
- /* tokenring already has correct status */
- return status;
- }
- /* Disable/enable dvbt tokenring bridge */
- status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
-
- end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
- do {
- status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
- if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
- break;
- msleep(1);
- } while (1);
- if (data != desiredStatus) {
- printk(KERN_ERR "drxk: SIO not ready\n");
- return -EINVAL;
- }
- return status;
-}
-
-static int MPEGTSStop(struct drxk_state *state)
-{
- int status = 0;
- u16 fecOcSncMode = 0;
- u16 fecOcIprMode = 0;
-
- dprintk(1, "\n");
-
- /* Gracefull shutdown (byte boundaries) */
- status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
- if (status < 0)
- goto error;
- fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
- status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
- if (status < 0)
- goto error;
-
- /* Suppress MCLK during absence of data */
- status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
- if (status < 0)
- goto error;
- fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
- status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-static int scu_command(struct drxk_state *state,
- u16 cmd, u8 parameterLen,
- u16 *parameter, u8 resultLen, u16 *result)
-{
-#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
-#error DRXK register mapping no longer compatible with this routine!
-#endif
- u16 curCmd = 0;
- int status = -EINVAL;
- unsigned long end;
- u8 buffer[34];
- int cnt = 0, ii;
- const char *p;
- char errname[30];
-
- dprintk(1, "\n");
-
- if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
- ((resultLen > 0) && (result == NULL))) {
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
- }
-
- mutex_lock(&state->mutex);
-
- /* assume that the command register is ready
- since it is checked afterwards */
- for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
- buffer[cnt++] = (parameter[ii] & 0xFF);
- buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
- }
- buffer[cnt++] = (cmd & 0xFF);
- buffer[cnt++] = ((cmd >> 8) & 0xFF);
-
- write_block(state, SCU_RAM_PARAM_0__A -
- (parameterLen - 1), cnt, buffer);
- /* Wait until SCU has processed command */
- end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
- do {
- msleep(1);
- status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
- if (status < 0)
- goto error;
- } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
- if (curCmd != DRX_SCU_READY) {
- printk(KERN_ERR "drxk: SCU not ready\n");
- status = -EIO;
- goto error2;
- }
- /* read results */
- if ((resultLen > 0) && (result != NULL)) {
- s16 err;
- int ii;
-
- for (ii = resultLen - 1; ii >= 0; ii -= 1) {
- status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
- if (status < 0)
- goto error;
- }
-
- /* Check if an error was reported by SCU */
- err = (s16)result[0];
- if (err >= 0)
- goto error;
-
- /* check for the known error codes */
- switch (err) {
- case SCU_RESULT_UNKCMD:
- p = "SCU_RESULT_UNKCMD";
- break;
- case SCU_RESULT_UNKSTD:
- p = "SCU_RESULT_UNKSTD";
- break;
- case SCU_RESULT_SIZE:
- p = "SCU_RESULT_SIZE";
- break;
- case SCU_RESULT_INVPAR:
- p = "SCU_RESULT_INVPAR";
- break;
- default: /* Other negative values are errors */
- sprintf(errname, "ERROR: %d\n", err);
- p = errname;
- }
- printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
- print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
- status = -EINVAL;
- goto error2;
- }
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-error2:
- mutex_unlock(&state->mutex);
- return status;
-}
-
-static int SetIqmAf(struct drxk_state *state, bool active)
-{
- u16 data = 0;
- int status;
-
- dprintk(1, "\n");
-
- /* Configure IQM */
- status = read16(state, IQM_AF_STDBY__A, &data);
- if (status < 0)
- goto error;
-
- if (!active) {
- data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
- | IQM_AF_STDBY_STDBY_AMP_STANDBY
- | IQM_AF_STDBY_STDBY_PD_STANDBY
- | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
- | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
- } else {
- data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
- & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
- & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
- & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
- & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
- );
- }
- status = write16(state, IQM_AF_STDBY__A, data);
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
-{
- int status = 0;
- u16 sioCcPwdMode = 0;
-
- dprintk(1, "\n");
-
- /* Check arguments */
- if (mode == NULL)
- return -EINVAL;
-
- switch (*mode) {
- case DRX_POWER_UP:
- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
- break;
- case DRXK_POWER_DOWN_OFDM:
- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
- break;
- case DRXK_POWER_DOWN_CORE:
- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
- break;
- case DRXK_POWER_DOWN_PLL:
- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
- break;
- case DRX_POWER_DOWN:
- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
- break;
- default:
- /* Unknow sleep mode */
- return -EINVAL;
- }
-
- /* If already in requested power mode, do nothing */
- if (state->m_currentPowerMode == *mode)
- return 0;
-
- /* For next steps make sure to start from DRX_POWER_UP mode */
- if (state->m_currentPowerMode != DRX_POWER_UP) {
- status = PowerUpDevice(state);
- if (status < 0)
- goto error;
- status = DVBTEnableOFDMTokenRing(state, true);
- if (status < 0)
- goto error;
- }
-
- if (*mode == DRX_POWER_UP) {
- /* Restore analog & pin configuartion */
- } else {
- /* Power down to requested mode */
- /* Backup some register settings */
- /* Set pins with possible pull-ups connected
- to them in input mode */
- /* Analog power down */
- /* ADC power down */
- /* Power down device */
- /* stop all comm_exec */
- /* Stop and power down previous standard */
- switch (state->m_OperationMode) {
- case OM_DVBT:
- status = MPEGTSStop(state);
- if (status < 0)
- goto error;
- status = PowerDownDVBT(state, false);
- if (status < 0)
- goto error;
- break;
- case OM_QAM_ITU_A:
- case OM_QAM_ITU_C:
- status = MPEGTSStop(state);
- if (status < 0)
- goto error;
- status = PowerDownQAM(state);
- if (status < 0)
- goto error;
- break;
- default:
- break;
- }
- status = DVBTEnableOFDMTokenRing(state, false);
- if (status < 0)
- goto error;
- status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
- if (status < 0)
- goto error;
- status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
- if (status < 0)
- goto error;
-
- if (*mode != DRXK_POWER_DOWN_OFDM) {
- state->m_HICfgCtrl |=
- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
- status = HI_CfgCommand(state);
- if (status < 0)
- goto error;
- }
- }
- state->m_currentPowerMode = *mode;
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
-{
- enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
- u16 cmdResult = 0;
- u16 data = 0;
- int status;
-
- dprintk(1, "\n");
-
- status = read16(state, SCU_COMM_EXEC__A, &data);
- if (status < 0)
- goto error;
- if (data == SCU_COMM_EXEC_ACTIVE) {
- /* Send OFDM stop command */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
- if (status < 0)
- goto error;
- /* Send OFDM reset command */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
- if (status < 0)
- goto error;
- }
-
- /* Reset datapath for OFDM, processors first */
- status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
- if (status < 0)
- goto error;
-
- /* powerdown AFE */
- status = SetIqmAf(state, false);
- if (status < 0)
- goto error;
-
- /* powerdown to OFDM mode */
- if (setPowerMode) {
- status = CtrlPowerMode(state, &powerMode);
- if (status < 0)
- goto error;
- }
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int SetOperationMode(struct drxk_state *state,
- enum OperationMode oMode)
-{
- int status = 0;
-
- dprintk(1, "\n");
- /*
- Stop and power down previous standard
- TODO investigate total power down instead of partial
- power down depending on "previous" standard.
- */
-
- /* disable HW lock indicator */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
- if (status < 0)
- goto error;
-
- /* Device is already at the required mode */
- if (state->m_OperationMode == oMode)
- return 0;
-
- switch (state->m_OperationMode) {
- /* OM_NONE was added for start up */
- case OM_NONE:
- break;
- case OM_DVBT:
- status = MPEGTSStop(state);
- if (status < 0)
- goto error;
- status = PowerDownDVBT(state, true);
- if (status < 0)
- goto error;
- state->m_OperationMode = OM_NONE;
- break;
- case OM_QAM_ITU_A: /* fallthrough */
- case OM_QAM_ITU_C:
- status = MPEGTSStop(state);
- if (status < 0)
- goto error;
- status = PowerDownQAM(state);
- if (status < 0)
- goto error;
- state->m_OperationMode = OM_NONE;
- break;
- case OM_QAM_ITU_B:
- default:
- status = -EINVAL;
- goto error;
- }
-
- /*
- Power up new standard
- */
- switch (oMode) {
- case OM_DVBT:
- dprintk(1, ": DVB-T\n");
- state->m_OperationMode = oMode;
- status = SetDVBTStandard(state, oMode);
- if (status < 0)
- goto error;
- break;
- case OM_QAM_ITU_A: /* fallthrough */
- case OM_QAM_ITU_C:
- dprintk(1, ": DVB-C Annex %c\n",
- (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
- state->m_OperationMode = oMode;
- status = SetQAMStandard(state, oMode);
- if (status < 0)
- goto error;
- break;
- case OM_QAM_ITU_B:
- default:
- status = -EINVAL;
- }
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int Start(struct drxk_state *state, s32 offsetFreq,
- s32 IntermediateFrequency)
-{
- int status = -EINVAL;
-
- u16 IFreqkHz;
- s32 OffsetkHz = offsetFreq / 1000;
-
- dprintk(1, "\n");
- if (state->m_DrxkState != DRXK_STOPPED &&
- state->m_DrxkState != DRXK_DTV_STARTED)
- goto error;
-
- state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
-
- if (IntermediateFrequency < 0) {
- state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
- IntermediateFrequency = -IntermediateFrequency;
- }
-
- switch (state->m_OperationMode) {
- case OM_QAM_ITU_A:
- case OM_QAM_ITU_C:
- IFreqkHz = (IntermediateFrequency / 1000);
- status = SetQAM(state, IFreqkHz, OffsetkHz);
- if (status < 0)
- goto error;
- state->m_DrxkState = DRXK_DTV_STARTED;
- break;
- case OM_DVBT:
- IFreqkHz = (IntermediateFrequency / 1000);
- status = MPEGTSStop(state);
- if (status < 0)
- goto error;
- status = SetDVBT(state, IFreqkHz, OffsetkHz);
- if (status < 0)
- goto error;
- status = DVBTStart(state);
- if (status < 0)
- goto error;
- state->m_DrxkState = DRXK_DTV_STARTED;
- break;
- default:
- break;
- }
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int ShutDown(struct drxk_state *state)
-{
- dprintk(1, "\n");
-
- MPEGTSStop(state);
- return 0;
-}
-
-static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
- u32 Time)
-{
- int status = -EINVAL;
-
- dprintk(1, "\n");
-
- if (pLockStatus == NULL)
- goto error;
-
- *pLockStatus = NOT_LOCKED;
-
- /* define the SCU command code */
- switch (state->m_OperationMode) {
- case OM_QAM_ITU_A:
- case OM_QAM_ITU_B:
- case OM_QAM_ITU_C:
- status = GetQAMLockStatus(state, pLockStatus);
- break;
- case OM_DVBT:
- status = GetDVBTLockStatus(state, pLockStatus);
- break;
- default:
- break;
- }
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int MPEGTSStart(struct drxk_state *state)
-{
- int status;
-
- u16 fecOcSncMode = 0;
-
- /* Allow OC to sync again */
- status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
- if (status < 0)
- goto error;
- fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
- status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int MPEGTSDtoInit(struct drxk_state *state)
-{
- int status;
-
- dprintk(1, "\n");
-
- /* Rate integration settings */
- status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
- if (status < 0)
- goto error;
-
- /* Additional configuration */
- status = write16(state, FEC_OC_OCR_INVERT__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_SNC_LWM__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_SNC_HWM__A, 12);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-static int MPEGTSDtoSetup(struct drxk_state *state,
- enum OperationMode oMode)
-{
- int status;
-
- u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
- u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
- u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
- u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
- u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
- u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
- u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
- u16 fecOcTmdMode = 0;
- u16 fecOcTmdIntUpdRate = 0;
- u32 maxBitRate = 0;
- bool staticCLK = false;
-
- dprintk(1, "\n");
-
- /* Check insertion of the Reed-Solomon parity bytes */
- status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
- if (status < 0)
- goto error;
- status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
- if (status < 0)
- goto error;
- fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
- fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
- if (state->m_insertRSByte == true) {
- /* enable parity symbol forward */
- fecOcRegMode |= FEC_OC_MODE_PARITY__M;
- /* MVAL disable during parity bytes */
- fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
- /* TS burst length to 204 */
- fecOcDtoBurstLen = 204;
- }
-
- /* Check serial or parrallel output */
- fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
- if (state->m_enableParallel == false) {
- /* MPEG data output is serial -> set ipr_mode[0] */
- fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
- }
-
- switch (oMode) {
- case OM_DVBT:
- maxBitRate = state->m_DVBTBitrate;
- fecOcTmdMode = 3;
- fecOcRcnCtlRate = 0xC00000;
- staticCLK = state->m_DVBTStaticCLK;
- break;
- case OM_QAM_ITU_A: /* fallthrough */
- case OM_QAM_ITU_C:
- fecOcTmdMode = 0x0004;
- fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
- maxBitRate = state->m_DVBCBitrate;
- staticCLK = state->m_DVBCStaticCLK;
- break;
- default:
- status = -EINVAL;
- } /* switch (standard) */
- if (status < 0)
- goto error;
-
- /* Configure DTO's */
- if (staticCLK) {
- u32 bitRate = 0;
-
- /* Rational DTO for MCLK source (static MCLK rate),
- Dynamic DTO for optimal grouping
- (avoid intra-packet gaps),
- DTO offset enable to sync TS burst with MSTRT */
- fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
- FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
- fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
- FEC_OC_FCT_MODE_VIRT_ENA__M);
-
- /* Check user defined bitrate */
- bitRate = maxBitRate;
- if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
- bitRate = 75900000UL;
- }
- /* Rational DTO period:
- dto_period = (Fsys / bitrate) - 2
-
- Result should be floored,
- to make sure >= requested bitrate
- */
- fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
- * 1000) / bitRate);
- if (fecOcDtoPeriod <= 2)
- fecOcDtoPeriod = 0;
- else
- fecOcDtoPeriod -= 2;
- fecOcTmdIntUpdRate = 8;
- } else {
- /* (commonAttr->staticCLK == false) => dynamic mode */
- fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
- fecOcFctMode = FEC_OC_FCT_MODE__PRE;
- fecOcTmdIntUpdRate = 5;
- }
-
- /* Write appropriate registers with requested configuration */
- status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
- if (status < 0)
- goto error;
-
- /* Rate integration settings */
- status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int MPEGTSConfigurePolarity(struct drxk_state *state)
-{
- u16 fecOcRegIprInvert = 0;
-
- /* Data mask for the output data byte */
- u16 InvertDataMask =
- FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
- FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
- FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
- FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
-
- dprintk(1, "\n");
-
- /* Control selective inversion of output bits */
- fecOcRegIprInvert &= (~(InvertDataMask));
- if (state->m_invertDATA == true)
- fecOcRegIprInvert |= InvertDataMask;
- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
- if (state->m_invertERR == true)
- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
- if (state->m_invertSTR == true)
- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
- if (state->m_invertVAL == true)
- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
- if (state->m_invertCLK == true)
- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
-
- return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
-}
-
-#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
-
-static int SetAgcRf(struct drxk_state *state,
- struct SCfgAgc *pAgcCfg, bool isDTV)
-{
- int status = -EINVAL;
- u16 data = 0;
- struct SCfgAgc *pIfAgcSettings;
-
- dprintk(1, "\n");
-
- if (pAgcCfg == NULL)
- goto error;
-
- switch (pAgcCfg->ctrlMode) {
- case DRXK_AGC_CTRL_AUTO:
- /* Enable RF AGC DAC */
- status = read16(state, IQM_AF_STDBY__A, &data);
- if (status < 0)
- goto error;
- data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
- status = write16(state, IQM_AF_STDBY__A, data);
- if (status < 0)
- goto error;
- status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
- if (status < 0)
- goto error;
-
- /* Enable SCU RF AGC loop */
- data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
-
- /* Polarity */
- if (state->m_RfAgcPol)
- data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
- else
- data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
- status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
- if (status < 0)
- goto error;
-
- /* Set speed (using complementary reduction value) */
- status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
- if (status < 0)
- goto error;
-
- data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
- data |= (~(pAgcCfg->speed <<
- SCU_RAM_AGC_KI_RED_RAGC_RED__B)
- & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
-
- status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
- if (status < 0)
- goto error;
-
- if (IsDVBT(state))
- pIfAgcSettings = &state->m_dvbtIfAgcCfg;
- else if (IsQAM(state))
- pIfAgcSettings = &state->m_qamIfAgcCfg;
- else
- pIfAgcSettings = &state->m_atvIfAgcCfg;
- if (pIfAgcSettings == NULL) {
- status = -EINVAL;
- goto error;
- }
-
- /* Set TOP, only if IF-AGC is in AUTO mode */
- if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
- if (status < 0)
- goto error;
-
- /* Cut-Off current */
- status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
- if (status < 0)
- goto error;
-
- /* Max. output level */
- status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
- if (status < 0)
- goto error;
-
- break;
-
- case DRXK_AGC_CTRL_USER:
- /* Enable RF AGC DAC */
- status = read16(state, IQM_AF_STDBY__A, &data);
- if (status < 0)
- goto error;
- data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
- status = write16(state, IQM_AF_STDBY__A, data);
- if (status < 0)
- goto error;
-
- /* Disable SCU RF AGC loop */
- status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
- if (status < 0)
- goto error;
- data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
- if (state->m_RfAgcPol)
- data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
- else
- data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
- status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
- if (status < 0)
- goto error;
-
- /* SCU c.o.c. to 0, enabling full control range */
- status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
- if (status < 0)
- goto error;
-
- /* Write value to output pin */
- status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
- if (status < 0)
- goto error;
- break;
-
- case DRXK_AGC_CTRL_OFF:
- /* Disable RF AGC DAC */
- status = read16(state, IQM_AF_STDBY__A, &data);
- if (status < 0)
- goto error;
- data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
- status = write16(state, IQM_AF_STDBY__A, data);
- if (status < 0)
- goto error;
-
- /* Disable SCU RF AGC loop */
- status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
- if (status < 0)
- goto error;
- data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
- status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
- if (status < 0)
- goto error;
- break;
-
- default:
- status = -EINVAL;
-
- }
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
-
-static int SetAgcIf(struct drxk_state *state,
- struct SCfgAgc *pAgcCfg, bool isDTV)
-{
- u16 data = 0;
- int status = 0;
- struct SCfgAgc *pRfAgcSettings;
-
- dprintk(1, "\n");
-
- switch (pAgcCfg->ctrlMode) {
- case DRXK_AGC_CTRL_AUTO:
-
- /* Enable IF AGC DAC */
- status = read16(state, IQM_AF_STDBY__A, &data);
- if (status < 0)
- goto error;
- data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
- status = write16(state, IQM_AF_STDBY__A, data);
- if (status < 0)
- goto error;
-
- status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
- if (status < 0)
- goto error;
-
- /* Enable SCU IF AGC loop */
- data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
-
- /* Polarity */
- if (state->m_IfAgcPol)
- data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
- else
- data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
- status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
- if (status < 0)
- goto error;
-
- /* Set speed (using complementary reduction value) */
- status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
- if (status < 0)
- goto error;
- data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
- data |= (~(pAgcCfg->speed <<
- SCU_RAM_AGC_KI_RED_IAGC_RED__B)
- & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
-
- status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
- if (status < 0)
- goto error;
-
- if (IsQAM(state))
- pRfAgcSettings = &state->m_qamRfAgcCfg;
- else
- pRfAgcSettings = &state->m_atvRfAgcCfg;
- if (pRfAgcSettings == NULL)
- return -1;
- /* Restore TOP */
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
- if (status < 0)
- goto error;
- break;
-
- case DRXK_AGC_CTRL_USER:
-
- /* Enable IF AGC DAC */
- status = read16(state, IQM_AF_STDBY__A, &data);
- if (status < 0)
- goto error;
- data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
- status = write16(state, IQM_AF_STDBY__A, data);
- if (status < 0)
- goto error;
-
- status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
- if (status < 0)
- goto error;
-
- /* Disable SCU IF AGC loop */
- data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
-
- /* Polarity */
- if (state->m_IfAgcPol)
- data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
- else
- data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
- status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
- if (status < 0)
- goto error;
-
- /* Write value to output pin */
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
- if (status < 0)
- goto error;
- break;
-
- case DRXK_AGC_CTRL_OFF:
-
- /* Disable If AGC DAC */
- status = read16(state, IQM_AF_STDBY__A, &data);
- if (status < 0)
- goto error;
- data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
- status = write16(state, IQM_AF_STDBY__A, data);
- if (status < 0)
- goto error;
-
- /* Disable SCU IF AGC loop */
- status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
- if (status < 0)
- goto error;
- data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
- status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
- if (status < 0)
- goto error;
- break;
- } /* switch (agcSettingsIf->ctrlMode) */
-
- /* always set the top to support
- configurations without if-loop */
- status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
-{
- u16 agcDacLvl;
- int status;
- u16 Level = 0;
-
- dprintk(1, "\n");
-
- status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
- if (status < 0) {
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
- }
-
- *pValue = 0;
-
- if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
- Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
- if (Level < 14000)
- *pValue = (14000 - Level) / 4;
- else
- *pValue = 0;
-
- return status;
-}
-
-static int GetQAMSignalToNoise(struct drxk_state *state,
- s32 *pSignalToNoise)
-{
- int status = 0;
- u16 qamSlErrPower = 0; /* accum. error between
- raw and sliced symbols */
- u32 qamSlSigPower = 0; /* used for MER, depends of
- QAM modulation */
- u32 qamSlMer = 0; /* QAM MER */
-
- dprintk(1, "\n");
-
- /* MER calculation */
-
- /* get the register value needed for MER */
- status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
- if (status < 0) {
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return -EINVAL;
- }
-
- switch (state->props.modulation) {
- case QAM_16:
- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
- break;
- case QAM_32:
- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
- break;
- case QAM_64:
- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
- break;
- case QAM_128:
- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
- break;
- default:
- case QAM_256:
- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
- break;
- }
-
- if (qamSlErrPower > 0) {
- qamSlMer = Log10Times100(qamSlSigPower) -
- Log10Times100((u32) qamSlErrPower);
- }
- *pSignalToNoise = qamSlMer;
-
- return status;
-}
-
-static int GetDVBTSignalToNoise(struct drxk_state *state,
- s32 *pSignalToNoise)
-{
- int status;
- u16 regData = 0;
- u32 EqRegTdSqrErrI = 0;
- u32 EqRegTdSqrErrQ = 0;
- u16 EqRegTdSqrErrExp = 0;
- u16 EqRegTdTpsPwrOfs = 0;
- u16 EqRegTdReqSmbCnt = 0;
- u32 tpsCnt = 0;
- u32 SqrErrIQ = 0;
- u32 a = 0;
- u32 b = 0;
- u32 c = 0;
- u32 iMER = 0;
- u16 transmissionParams = 0;
-
- dprintk(1, "\n");
-
- status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
- if (status < 0)
- goto error;
- status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
- if (status < 0)
- goto error;
- status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
- if (status < 0)
- goto error;
- status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
- if (status < 0)
- goto error;
- /* Extend SQR_ERR_I operational range */
- EqRegTdSqrErrI = (u32) regData;
- if ((EqRegTdSqrErrExp > 11) &&
- (EqRegTdSqrErrI < 0x00000FFFUL)) {
- EqRegTdSqrErrI += 0x00010000UL;
- }
- status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
- if (status < 0)
- goto error;
- /* Extend SQR_ERR_Q operational range */
- EqRegTdSqrErrQ = (u32) regData;
- if ((EqRegTdSqrErrExp > 11) &&
- (EqRegTdSqrErrQ < 0x00000FFFUL))
- EqRegTdSqrErrQ += 0x00010000UL;
-
- status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
- if (status < 0)
- goto error;
-
- /* Check input data for MER */
-
- /* MER calculation (in 0.1 dB) without math.h */
- if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
- iMER = 0;
- else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
- /* No error at all, this must be the HW reset value
- * Apparently no first measurement yet
- * Set MER to 0.0 */
- iMER = 0;
- } else {
- SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
- EqRegTdSqrErrExp;
- if ((transmissionParams &
- OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
- == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
- tpsCnt = 17;
- else
- tpsCnt = 68;
-
- /* IMER = 100 * log10 (x)
- where x = (EqRegTdTpsPwrOfs^2 *
- EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
-
- => IMER = a + b -c
- where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
- b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
- c = 100 * log10 (SqrErrIQ)
- */
-
- /* log(x) x = 9bits * 9bits->18 bits */
- a = Log10Times100(EqRegTdTpsPwrOfs *
- EqRegTdTpsPwrOfs);
- /* log(x) x = 16bits * 7bits->23 bits */
- b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
- /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
- c = Log10Times100(SqrErrIQ);
-
- iMER = a + b;
- /* No negative MER, clip to zero */
- if (iMER > c)
- iMER -= c;
- else
- iMER = 0;
- }
- *pSignalToNoise = iMER;
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
-{
- dprintk(1, "\n");
-
- *pSignalToNoise = 0;
- switch (state->m_OperationMode) {
- case OM_DVBT:
- return GetDVBTSignalToNoise(state, pSignalToNoise);
- case OM_QAM_ITU_A:
- case OM_QAM_ITU_C:
- return GetQAMSignalToNoise(state, pSignalToNoise);
- default:
- break;
- }
- return 0;
-}
-
-#if 0
-static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
-{
- /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
- int status = 0;
-
- dprintk(1, "\n");
-
- static s32 QE_SN[] = {
- 51, /* QPSK 1/2 */
- 69, /* QPSK 2/3 */
- 79, /* QPSK 3/4 */
- 89, /* QPSK 5/6 */
- 97, /* QPSK 7/8 */
- 108, /* 16-QAM 1/2 */
- 131, /* 16-QAM 2/3 */
- 146, /* 16-QAM 3/4 */
- 156, /* 16-QAM 5/6 */
- 160, /* 16-QAM 7/8 */
- 165, /* 64-QAM 1/2 */
- 187, /* 64-QAM 2/3 */
- 202, /* 64-QAM 3/4 */
- 216, /* 64-QAM 5/6 */
- 225, /* 64-QAM 7/8 */
- };
-
- *pQuality = 0;
-
- do {
- s32 SignalToNoise = 0;
- u16 Constellation = 0;
- u16 CodeRate = 0;
- u32 SignalToNoiseRel;
- u32 BERQuality;
-
- status = GetDVBTSignalToNoise(state, &SignalToNoise);
- if (status < 0)
- break;
- status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
- if (status < 0)
- break;
- Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
-
- status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
- if (status < 0)
- break;
- CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
-
- if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
- CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
- break;
- SignalToNoiseRel = SignalToNoise -
- QE_SN[Constellation * 5 + CodeRate];
- BERQuality = 100;
-
- if (SignalToNoiseRel < -70)
- *pQuality = 0;
- else if (SignalToNoiseRel < 30)
- *pQuality = ((SignalToNoiseRel + 70) *
- BERQuality) / 100;
- else
- *pQuality = BERQuality;
- } while (0);
- return 0;
-};
-
-static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
-{
- int status = 0;
- *pQuality = 0;
-
- dprintk(1, "\n");
-
- do {
- u32 SignalToNoise = 0;
- u32 BERQuality = 100;
- u32 SignalToNoiseRel = 0;
-
- status = GetQAMSignalToNoise(state, &SignalToNoise);
- if (status < 0)
- break;
-
- switch (state->props.modulation) {
- case QAM_16:
- SignalToNoiseRel = SignalToNoise - 200;
- break;
- case QAM_32:
- SignalToNoiseRel = SignalToNoise - 230;
- break; /* Not in NorDig */
- case QAM_64:
- SignalToNoiseRel = SignalToNoise - 260;
- break;
- case QAM_128:
- SignalToNoiseRel = SignalToNoise - 290;
- break;
- default:
- case QAM_256:
- SignalToNoiseRel = SignalToNoise - 320;
- break;
- }
-
- if (SignalToNoiseRel < -70)
- *pQuality = 0;
- else if (SignalToNoiseRel < 30)
- *pQuality = ((SignalToNoiseRel + 70) *
- BERQuality) / 100;
- else
- *pQuality = BERQuality;
- } while (0);
-
- return status;
-}
-
-static int GetQuality(struct drxk_state *state, s32 *pQuality)
-{
- dprintk(1, "\n");
-
- switch (state->m_OperationMode) {
- case OM_DVBT:
- return GetDVBTQuality(state, pQuality);
- case OM_QAM_ITU_A:
- return GetDVBCQuality(state, pQuality);
- default:
- break;
- }
-
- return 0;
-}
-#endif
-
-/* Free data ram in SIO HI */
-#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
-#define SIO_HI_RA_RAM_USR_END__A 0x420060
-
-#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
-#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
-#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
-#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
-
-#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
-#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
-#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
-
-static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
-{
- int status = -EINVAL;
-
- dprintk(1, "\n");
-
- if (state->m_DrxkState == DRXK_UNINITIALIZED)
- return 0;
- if (state->m_DrxkState == DRXK_POWERED_DOWN)
- goto error;
-
- if (state->no_i2c_bridge)
- return 0;
-
- status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
- if (status < 0)
- goto error;
- if (bEnableBridge) {
- status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
- if (status < 0)
- goto error;
- } else {
- status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
- if (status < 0)
- goto error;
- }
-
- status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int SetPreSaw(struct drxk_state *state,
- struct SCfgPreSaw *pPreSawCfg)
-{
- int status = -EINVAL;
-
- dprintk(1, "\n");
-
- if ((pPreSawCfg == NULL)
- || (pPreSawCfg->reference > IQM_AF_PDREF__M))
- goto error;
-
- status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
- u16 romOffset, u16 nrOfElements, u32 timeOut)
-{
- u16 blStatus = 0;
- u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
- u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
- int status;
- unsigned long end;
-
- dprintk(1, "\n");
-
- mutex_lock(&state->mutex);
- status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
- if (status < 0)
- goto error;
- status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
- if (status < 0)
- goto error;
- status = write16(state, SIO_BL_TGT_ADDR__A, offset);
- if (status < 0)
- goto error;
- status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
- if (status < 0)
- goto error;
- status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
- if (status < 0)
- goto error;
- status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
- if (status < 0)
- goto error;
-
- end = jiffies + msecs_to_jiffies(timeOut);
- do {
- status = read16(state, SIO_BL_STATUS__A, &blStatus);
- if (status < 0)
- goto error;
- } while ((blStatus == 0x1) && time_is_after_jiffies(end));
- if (blStatus == 0x1) {
- printk(KERN_ERR "drxk: SIO not ready\n");
- status = -EINVAL;
- goto error2;
- }
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-error2:
- mutex_unlock(&state->mutex);
- return status;
-
-}
-
-static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
-{
- u16 data = 0;
- int status;
-
- dprintk(1, "\n");
-
- /* Start measurement */
- status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
- if (status < 0)
- goto error;
- status = write16(state, IQM_AF_START_LOCK__A, 1);
- if (status < 0)
- goto error;
-
- *count = 0;
- status = read16(state, IQM_AF_PHASE0__A, &data);
- if (status < 0)
- goto error;
- if (data == 127)
- *count = *count + 1;
- status = read16(state, IQM_AF_PHASE1__A, &data);
- if (status < 0)
- goto error;
- if (data == 127)
- *count = *count + 1;
- status = read16(state, IQM_AF_PHASE2__A, &data);
- if (status < 0)
- goto error;
- if (data == 127)
- *count = *count + 1;
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int ADCSynchronization(struct drxk_state *state)
-{
- u16 count = 0;
- int status;
-
- dprintk(1, "\n");
-
- status = ADCSyncMeasurement(state, &count);
- if (status < 0)
- goto error;
-
- if (count == 1) {
- /* Try sampling on a diffrent edge */
- u16 clkNeg = 0;
-
- status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
- if (status < 0)
- goto error;
- if ((clkNeg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
- clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
- clkNeg |=
- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
- } else {
- clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
- clkNeg |=
- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
- }
- status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
- if (status < 0)
- goto error;
- status = ADCSyncMeasurement(state, &count);
- if (status < 0)
- goto error;
- }
-
- if (count < 2)
- status = -EINVAL;
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int SetFrequencyShifter(struct drxk_state *state,
- u16 intermediateFreqkHz,
- s32 tunerFreqOffset, bool isDTV)
-{
- bool selectPosImage = false;
- u32 rfFreqResidual = tunerFreqOffset;
- u32 fmFrequencyShift = 0;
- bool tunerMirror = !state->m_bMirrorFreqSpect;
- u32 adcFreq;
- bool adcFlip;
- int status;
- u32 ifFreqActual;
- u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
- u32 frequencyShift;
- bool imageToSelect;
-
- dprintk(1, "\n");
-
- /*
- Program frequency shifter
- No need to account for mirroring on RF
- */
- if (isDTV) {
- if ((state->m_OperationMode == OM_QAM_ITU_A) ||
- (state->m_OperationMode == OM_QAM_ITU_C) ||
- (state->m_OperationMode == OM_DVBT))
- selectPosImage = true;
- else
- selectPosImage = false;
- }
- if (tunerMirror)
- /* tuner doesn't mirror */
- ifFreqActual = intermediateFreqkHz +
- rfFreqResidual + fmFrequencyShift;
- else
- /* tuner mirrors */
- ifFreqActual = intermediateFreqkHz -
- rfFreqResidual - fmFrequencyShift;
- if (ifFreqActual > samplingFrequency / 2) {
- /* adc mirrors */
- adcFreq = samplingFrequency - ifFreqActual;
- adcFlip = true;
- } else {
- /* adc doesn't mirror */
- adcFreq = ifFreqActual;
- adcFlip = false;
- }
-
- frequencyShift = adcFreq;
- imageToSelect = state->m_rfmirror ^ tunerMirror ^
- adcFlip ^ selectPosImage;
- state->m_IqmFsRateOfs =
- Frac28a((frequencyShift), samplingFrequency);
-
- if (imageToSelect)
- state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
-
- /* Program frequency shifter with tuner offset compensation */
- /* frequencyShift += tunerFreqOffset; TODO */
- status = write32(state, IQM_FS_RATE_OFS_LO__A,
- state->m_IqmFsRateOfs);
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int InitAGC(struct drxk_state *state, bool isDTV)
-{
- u16 ingainTgt = 0;
- u16 ingainTgtMin = 0;
- u16 ingainTgtMax = 0;
- u16 clpCyclen = 0;
- u16 clpSumMin = 0;
- u16 clpDirTo = 0;
- u16 snsSumMin = 0;
- u16 snsSumMax = 0;
- u16 clpSumMax = 0;
- u16 snsDirTo = 0;
- u16 kiInnergainMin = 0;
- u16 ifIaccuHiTgt = 0;
- u16 ifIaccuHiTgtMin = 0;
- u16 ifIaccuHiTgtMax = 0;
- u16 data = 0;
- u16 fastClpCtrlDelay = 0;
- u16 clpCtrlMode = 0;
- int status = 0;
-
- dprintk(1, "\n");
-
- /* Common settings */
- snsSumMax = 1023;
- ifIaccuHiTgtMin = 2047;
- clpCyclen = 500;
- clpSumMax = 1023;
-
- /* AGCInit() not available for DVBT; init done in microcode */
- if (!IsQAM(state)) {
- printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
- return -EINVAL;
- }
-
- /* FIXME: Analog TV AGC require different settings */
-
- /* Standard specific settings */
- clpSumMin = 8;
- clpDirTo = (u16) -9;
- clpCtrlMode = 0;
- snsSumMin = 8;
- snsDirTo = (u16) -9;
- kiInnergainMin = (u16) -1030;
- ifIaccuHiTgtMax = 0x2380;
- ifIaccuHiTgt = 0x2380;
- ingainTgtMin = 0x0511;
- ingainTgt = 0x0511;
- ingainTgtMax = 5119;
- fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
-
- status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
- if (status < 0)
- goto error;
-
- /* Initialize inner-loop KI gain factors */
- status = read16(state, SCU_RAM_AGC_KI__A, &data);
- if (status < 0)
- goto error;
-
- data = 0x0657;
- data &= ~SCU_RAM_AGC_KI_RF__M;
- data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
- data &= ~SCU_RAM_AGC_KI_IF__M;
- data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
-
- status = write16(state, SCU_RAM_AGC_KI__A, data);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
-{
- int status;
-
- dprintk(1, "\n");
- if (packetErr == NULL)
- status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
- else
- status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int DVBTScCommand(struct drxk_state *state,
- u16 cmd, u16 subcmd,
- u16 param0, u16 param1, u16 param2,
- u16 param3, u16 param4)
-{
- u16 curCmd = 0;
- u16 errCode = 0;
- u16 retryCnt = 0;
- u16 scExec = 0;
- int status;
-
- dprintk(1, "\n");
- status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
- if (scExec != 1) {
- /* SC is not running */
- status = -EINVAL;
- }
- if (status < 0)
- goto error;
-
- /* Wait until sc is ready to receive command */
- retryCnt = 0;
- do {
- msleep(1);
- status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
- retryCnt++;
- } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
- if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
- goto error;
-
- /* Write sub-command */
- switch (cmd) {
- /* All commands using sub-cmd */
- case OFDM_SC_RA_RAM_CMD_PROC_START:
- case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
- case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
- status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
- if (status < 0)
- goto error;
- break;
- default:
- /* Do nothing */
- break;
- }
-
- /* Write needed parameters and the command */
- switch (cmd) {
- /* All commands using 5 parameters */
- /* All commands using 4 parameters */
- /* All commands using 3 parameters */
- /* All commands using 2 parameters */
- case OFDM_SC_RA_RAM_CMD_PROC_START:
- case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
- case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
- status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
- /* All commands using 1 parameters */
- case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
- case OFDM_SC_RA_RAM_CMD_USER_IO:
- status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
- /* All commands using 0 parameters */
- case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
- case OFDM_SC_RA_RAM_CMD_NULL:
- /* Write command */
- status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
- break;
- default:
- /* Unknown command */
- status = -EINVAL;
- }
- if (status < 0)
- goto error;
-
- /* Wait until sc is ready processing command */
- retryCnt = 0;
- do {
- msleep(1);
- status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
- retryCnt++;
- } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
- if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
- goto error;
-
- /* Check for illegal cmd */
- status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
- if (errCode == 0xFFFF) {
- /* illegal command */
- status = -EINVAL;
- }
- if (status < 0)
- goto error;
-
- /* Retreive results parameters from SC */
- switch (cmd) {
- /* All commands yielding 5 results */
- /* All commands yielding 4 results */
- /* All commands yielding 3 results */
- /* All commands yielding 2 results */
- /* All commands yielding 1 result */
- case OFDM_SC_RA_RAM_CMD_USER_IO:
- case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
- status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
- /* All commands yielding 0 results */
- case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
- case OFDM_SC_RA_RAM_CMD_SET_TIMER:
- case OFDM_SC_RA_RAM_CMD_PROC_START:
- case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
- case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
- case OFDM_SC_RA_RAM_CMD_NULL:
- break;
- default:
- /* Unknown command */
- status = -EINVAL;
- break;
- } /* switch (cmd->cmd) */
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int PowerUpDVBT(struct drxk_state *state)
-{
- enum DRXPowerMode powerMode = DRX_POWER_UP;
- int status;
-
- dprintk(1, "\n");
- status = CtrlPowerMode(state, &powerMode);
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
-{
- int status;
-
- dprintk(1, "\n");
- if (*enabled == true)
- status = write16(state, IQM_CF_BYPASSDET__A, 0);
- else
- status = write16(state, IQM_CF_BYPASSDET__A, 1);
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-#define DEFAULT_FR_THRES_8K 4000
-static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
-{
-
- int status;
-
- dprintk(1, "\n");
- if (*enabled == true) {
- /* write mask to 1 */
- status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
- DEFAULT_FR_THRES_8K);
- } else {
- /* write mask to 0 */
- status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
- }
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
- struct DRXKCfgDvbtEchoThres_t *echoThres)
-{
- u16 data = 0;
- int status;
-
- dprintk(1, "\n");
- status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
- if (status < 0)
- goto error;
-
- switch (echoThres->fftMode) {
- case DRX_FFTMODE_2K:
- data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
- data |= ((echoThres->threshold <<
- OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
- & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
- break;
- case DRX_FFTMODE_8K:
- data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
- data |= ((echoThres->threshold <<
- OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
- & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
- break;
- default:
- return -EINVAL;
- }
-
- status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
- enum DRXKCfgDvbtSqiSpeed *speed)
-{
- int status = -EINVAL;
-
- dprintk(1, "\n");
-
- switch (*speed) {
- case DRXK_DVBT_SQI_SPEED_FAST:
- case DRXK_DVBT_SQI_SPEED_MEDIUM:
- case DRXK_DVBT_SQI_SPEED_SLOW:
- break;
- default:
- goto error;
- }
- status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
- (u16) *speed);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-/*============================================================================*/
-
-/**
-* \brief Activate DVBT specific presets
-* \param demod instance of demodulator.
-* \return DRXStatus_t.
-*
-* Called in DVBTSetStandard
-*
-*/
-static int DVBTActivatePresets(struct drxk_state *state)
-{
- int status;
- bool setincenable = false;
- bool setfrenable = true;
-
- struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
- struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
-
- dprintk(1, "\n");
- status = DVBTCtrlSetIncEnable(state, &setincenable);
- if (status < 0)
- goto error;
- status = DVBTCtrlSetFrEnable(state, &setfrenable);
- if (status < 0)
- goto error;
- status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
- if (status < 0)
- goto error;
- status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-/*============================================================================*/
-
-/**
-* \brief Initialize channelswitch-independent settings for DVBT.
-* \param demod instance of demodulator.
-* \return DRXStatus_t.
-*
-* For ROM code channel filter taps are loaded from the bootloader. For microcode
-* the DVB-T taps from the drxk_filters.h are used.
-*/
-static int SetDVBTStandard(struct drxk_state *state,
- enum OperationMode oMode)
-{
- u16 cmdResult = 0;
- u16 data = 0;
- int status;
-
- dprintk(1, "\n");
-
- PowerUpDVBT(state);
- /* added antenna switch */
- SwitchAntennaToDVBT(state);
- /* send OFDM reset command */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
- if (status < 0)
- goto error;
-
- /* send OFDM setenv command */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
- if (status < 0)
- goto error;
-
- /* reset datapath for OFDM, processors first */
- status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
- if (status < 0)
- goto error;
-
- /* IQM setup */
- /* synchronize on ofdstate->m_festart */
- status = write16(state, IQM_AF_UPD_SEL__A, 1);
- if (status < 0)
- goto error;
- /* window size for clipping ADC detection */
- status = write16(state, IQM_AF_CLP_LEN__A, 0);
- if (status < 0)
- goto error;
- /* window size for for sense pre-SAW detection */
- status = write16(state, IQM_AF_SNS_LEN__A, 0);
- if (status < 0)
- goto error;
- /* sense threshold for sense pre-SAW detection */
- status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
- if (status < 0)
- goto error;
- status = SetIqmAf(state, true);
- if (status < 0)
- goto error;
-
- status = write16(state, IQM_AF_AGC_RF__A, 0);
- if (status < 0)
- goto error;
-
- /* Impulse noise cruncher setup */
- status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
- if (status < 0)
- goto error;
-
- status = write16(state, IQM_RC_STRETCH__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_SCALE__A, 1600);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_SCALE_SH__A, 0);
- if (status < 0)
- goto error;
-
- /* virtual clipping threshold for clipping ADC detection */
- status = write16(state, IQM_AF_CLP_TH__A, 448);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
- if (status < 0)
- goto error;
-
- status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
- if (status < 0)
- goto error;
-
- status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
- if (status < 0)
- goto error;
- /* enable power measurement interrupt */
- status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
- if (status < 0)
- goto error;
-
- /* IQM will not be reset from here, sync ADC and update/init AGC */
- status = ADCSynchronization(state);
- if (status < 0)
- goto error;
- status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
- if (status < 0)
- goto error;
-
- /* Halt SCU to enable safe non-atomic accesses */
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
- if (status < 0)
- goto error;
-
- status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
- if (status < 0)
- goto error;
- status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
- if (status < 0)
- goto error;
-
- /* Set Noise Estimation notch width and enable DC fix */
- status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
- if (status < 0)
- goto error;
- data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
- status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
- if (status < 0)
- goto error;
-
- /* Activate SCU to enable SCU commands */
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
- if (status < 0)
- goto error;
-
- if (!state->m_DRXK_A3_ROM_CODE) {
- /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
- status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
- if (status < 0)
- goto error;
- }
-
- /* OFDM_SC setup */
-#ifdef COMPILE_FOR_NONRT
- status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
- if (status < 0)
- goto error;
-#endif
-
- /* FEC setup */
- status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
- if (status < 0)
- goto error;
-
-
-#ifdef COMPILE_FOR_NONRT
- status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
- if (status < 0)
- goto error;
-#else
- status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
- if (status < 0)
- goto error;
-#endif
- status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
- if (status < 0)
- goto error;
-
- /* Setup MPEG bus */
- status = MPEGTSDtoSetup(state, OM_DVBT);
- if (status < 0)
- goto error;
- /* Set DVBT Presets */
- status = DVBTActivatePresets(state);
- if (status < 0)
- goto error;
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-/*============================================================================*/
-/**
-* \brief Start dvbt demodulating for channel.
-* \param demod instance of demodulator.
-* \return DRXStatus_t.
-*/
-static int DVBTStart(struct drxk_state *state)
-{
- u16 param1;
- int status;
- /* DRXKOfdmScCmd_t scCmd; */
-
- dprintk(1, "\n");
- /* Start correct processes to get in lock */
- /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
- param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
- status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
- if (status < 0)
- goto error;
- /* Start FEC OC */
- status = MPEGTSStart(state);
- if (status < 0)
- goto error;
- status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
- if (status < 0)
- goto error;
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-
-/*============================================================================*/
-
-/**
-* \brief Set up dvbt demodulator for channel.
-* \param demod instance of demodulator.
-* \return DRXStatus_t.
-* // original DVBTSetChannel()
-*/
-static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
- s32 tunerFreqOffset)
-{
- u16 cmdResult = 0;
- u16 transmissionParams = 0;
- u16 operationMode = 0;
- u32 iqmRcRateOfs = 0;
- u32 bandwidth = 0;
- u16 param1;
- int status;
-
- dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
-
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
- if (status < 0)
- goto error;
-
- /* Halt SCU to enable safe non-atomic accesses */
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
- if (status < 0)
- goto error;
-
- /* Stop processors */
- status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
-
- /* Mandatory fix, always stop CP, required to set spl offset back to
- hardware default (is set to 0 by ucode during pilot detection */
- status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
-
- /*== Write channel settings to device =====================================*/
-
- /* mode */
- switch (state->props.transmission_mode) {
- case TRANSMISSION_MODE_AUTO:
- default:
- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
- /* fall through , try first guess DRX_FFTMODE_8K */
- case TRANSMISSION_MODE_8K:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
- break;
- case TRANSMISSION_MODE_2K:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
- break;
- }
-
- /* guard */
- switch (state->props.guard_interval) {
- default:
- case GUARD_INTERVAL_AUTO:
- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
- /* fall through , try first guess DRX_GUARD_1DIV4 */
- case GUARD_INTERVAL_1_4:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
- break;
- case GUARD_INTERVAL_1_32:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
- break;
- case GUARD_INTERVAL_1_16:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
- break;
- case GUARD_INTERVAL_1_8:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
- break;
- }
-
- /* hierarchy */
- switch (state->props.hierarchy) {
- case HIERARCHY_AUTO:
- case HIERARCHY_NONE:
- default:
- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
- /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
- /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
- /* break; */
- case HIERARCHY_1:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
- break;
- case HIERARCHY_2:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
- break;
- case HIERARCHY_4:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
- break;
- }
-
-
- /* modulation */
- switch (state->props.modulation) {
- case QAM_AUTO:
- default:
- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
- /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
- case QAM_64:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
- break;
- case QPSK:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
- break;
- case QAM_16:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
- break;
- }
-#if 0
- /* No hierachical channels support in BDA */
- /* Priority (only for hierarchical channels) */
- switch (channel->priority) {
- case DRX_PRIORITY_LOW:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
- WR16(devAddr, OFDM_EC_SB_PRIOR__A,
- OFDM_EC_SB_PRIOR_LO);
- break;
- case DRX_PRIORITY_HIGH:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
- WR16(devAddr, OFDM_EC_SB_PRIOR__A,
- OFDM_EC_SB_PRIOR_HI));
- break;
- case DRX_PRIORITY_UNKNOWN: /* fall through */
- default:
- status = -EINVAL;
- goto error;
- }
-#else
- /* Set Priorty high */
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
- status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
- if (status < 0)
- goto error;
-#endif
-
- /* coderate */
- switch (state->props.code_rate_HP) {
- case FEC_AUTO:
- default:
- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
- /* fall through , try first guess DRX_CODERATE_2DIV3 */
- case FEC_2_3:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
- break;
- case FEC_1_2:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
- break;
- case FEC_3_4:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
- break;
- case FEC_5_6:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
- break;
- case FEC_7_8:
- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
- break;
- }
-
- /* SAW filter selection: normaly not necesarry, but if wanted
- the application can select a SAW filter via the driver by using UIOs */
- /* First determine real bandwidth (Hz) */
- /* Also set delay for impulse noise cruncher */
- /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
- by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
- functions */
- switch (state->props.bandwidth_hz) {
- case 0:
- state->props.bandwidth_hz = 8000000;
- /* fall though */
- case 8000000:
- bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
- status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
- if (status < 0)
- goto error;
- /* cochannel protection for PAL 8 MHz */
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
- if (status < 0)
- goto error;
- break;
- case 7000000:
- bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
- status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
- if (status < 0)
- goto error;
- /* cochannel protection for PAL 7 MHz */
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
- if (status < 0)
- goto error;
- break;
- case 6000000:
- bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
- status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
- if (status < 0)
- goto error;
- /* cochannel protection for NTSC 6 MHz */
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
- if (status < 0)
- goto error;
- break;
- default:
- status = -EINVAL;
- goto error;
- }
-
- if (iqmRcRateOfs == 0) {
- /* Now compute IQM_RC_RATE_OFS
- (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
- =>
- ((SysFreq / BandWidth) * (2^21)) - (2^23)
- */
- /* (SysFreq / BandWidth) * (2^28) */
- /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
- => assert(MAX(sysClk) < 16*MIN(bandwidth))
- => assert(109714272 > 48000000) = true so Frac 28 can be used */
- iqmRcRateOfs = Frac28a((u32)
- ((state->m_sysClockFreq *
- 1000) / 3), bandwidth);
- /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
- if ((iqmRcRateOfs & 0x7fL) >= 0x40)
- iqmRcRateOfs += 0x80L;
- iqmRcRateOfs = iqmRcRateOfs >> 7;
- /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
- iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
- }
-
- iqmRcRateOfs &=
- ((((u32) IQM_RC_RATE_OFS_HI__M) <<
- IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
- status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
- if (status < 0)
- goto error;
-
- /* Bandwidth setting done */
-
-#if 0
- status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
- if (status < 0)
- goto error;
-#endif
- status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
- if (status < 0)
- goto error;
-
- /*== Start SC, write channel settings to SC ===============================*/
-
- /* Activate SCU to enable SCU commands */
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
- if (status < 0)
- goto error;
-
- /* Enable SC after setting all other parameters */
- status = write16(state, OFDM_SC_COMM_STATE__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
- if (status < 0)
- goto error;
-
-
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
- if (status < 0)
- goto error;
-
- /* Write SC parameter registers, set all AUTO flags in operation mode */
- param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
- OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
- OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
- OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
- OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
- status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
- 0, transmissionParams, param1, 0, 0, 0);
- if (status < 0)
- goto error;
-
- if (!state->m_DRXK_A3_ROM_CODE)
- status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-
-/*============================================================================*/
-
-/**
-* \brief Retreive lock status .
-* \param demod Pointer to demodulator instance.
-* \param lockStat Pointer to lock status structure.
-* \return DRXStatus_t.
-*
-*/
-static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
-{
- int status;
- const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
- OFDM_SC_RA_RAM_LOCK_FEC__M);
- const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
- const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
-
- u16 ScRaRamLock = 0;
- u16 ScCommExec = 0;
-
- dprintk(1, "\n");
-
- *pLockStatus = NOT_LOCKED;
- /* driver 0.9.0 */
- /* Check if SC is running */
- status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
- if (status < 0)
- goto end;
- if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
- goto end;
-
- status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
- if (status < 0)
- goto end;
-
- if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
- *pLockStatus = MPEG_LOCK;
- else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
- *pLockStatus = FEC_LOCK;
- else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
- *pLockStatus = DEMOD_LOCK;
- else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
- *pLockStatus = NEVER_LOCK;
-end:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-static int PowerUpQAM(struct drxk_state *state)
-{
- enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
- int status;
-
- dprintk(1, "\n");
- status = CtrlPowerMode(state, &powerMode);
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-
-/** Power Down QAM */
-static int PowerDownQAM(struct drxk_state *state)
-{
- u16 data = 0;
- u16 cmdResult;
- int status = 0;
-
- dprintk(1, "\n");
- status = read16(state, SCU_COMM_EXEC__A, &data);
- if (status < 0)
- goto error;
- if (data == SCU_COMM_EXEC_ACTIVE) {
- /*
- STOP demodulator
- QAM and HW blocks
- */
- /* stop all comstate->m_exec */
- status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
- if (status < 0)
- goto error;
- }
- /* powerdown AFE */
- status = SetIqmAf(state, false);
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-/*============================================================================*/
-
-/**
-* \brief Setup of the QAM Measurement intervals for signal quality
-* \param demod instance of demod.
-* \param modulation current modulation.
-* \return DRXStatus_t.
-*
-* NOTE:
-* Take into account that for certain settings the errorcounters can overflow.
-* The implementation does not check this.
-*
-*/
-static int SetQAMMeasurement(struct drxk_state *state,
- enum EDrxkConstellation modulation,
- u32 symbolRate)
-{
- u32 fecBitsDesired = 0; /* BER accounting period */
- u32 fecRsPeriodTotal = 0; /* Total period */
- u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
- u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
- int status = 0;
-
- dprintk(1, "\n");
-
- fecRsPrescale = 1;
- /* fecBitsDesired = symbolRate [kHz] *
- FrameLenght [ms] *
- (modulation + 1) *
- SyncLoss (== 1) *
- ViterbiLoss (==1)
- */
- switch (modulation) {
- case DRX_CONSTELLATION_QAM16:
- fecBitsDesired = 4 * symbolRate;
- break;
- case DRX_CONSTELLATION_QAM32:
- fecBitsDesired = 5 * symbolRate;
- break;
- case DRX_CONSTELLATION_QAM64:
- fecBitsDesired = 6 * symbolRate;
- break;
- case DRX_CONSTELLATION_QAM128:
- fecBitsDesired = 7 * symbolRate;
- break;
- case DRX_CONSTELLATION_QAM256:
- fecBitsDesired = 8 * symbolRate;
- break;
- default:
- status = -EINVAL;
- }
- if (status < 0)
- goto error;
-
- fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
- fecBitsDesired *= 500; /* meas. period [ms] */
-
- /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
- /* fecRsPeriodTotal = fecBitsDesired / 1632 */
- fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
-
- /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
- fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
- if (fecRsPrescale == 0) {
- /* Divide by zero (though impossible) */
- status = -EINVAL;
- if (status < 0)
- goto error;
- }
- fecRsPeriod =
- ((u16) fecRsPeriodTotal +
- (fecRsPrescale >> 1)) / fecRsPrescale;
-
- /* write corresponding registers */
- status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
- if (status < 0)
- goto error;
- status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
- if (status < 0)
- goto error;
- status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int SetQAM16(struct drxk_state *state)
-{
- int status = 0;
-
- dprintk(1, "\n");
- /* QAM Equalizer Setup */
- /* Equalizer */
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
- if (status < 0)
- goto error;
- /* Decision Feedback Equalizer */
- status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
- if (status < 0)
- goto error;
-
- status = write16(state, QAM_SY_SYNC_HWM__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_AWM__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_LWM__A, 3);
- if (status < 0)
- goto error;
-
- /* QAM Slicer Settings */
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
- if (status < 0)
- goto error;
-
- /* QAM Loop Controller Coeficients */
- status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
- if (status < 0)
- goto error;
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
- if (status < 0)
- goto error;
-
-
- /* QAM FSM Tracking Parameters */
-
- status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
- if (status < 0)
- goto error;
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-/*============================================================================*/
-
-/**
-* \brief QAM32 specific setup
-* \param demod instance of demod.
-* \return DRXStatus_t.
-*/
-static int SetQAM32(struct drxk_state *state)
-{
- int status = 0;
-
- dprintk(1, "\n");
-
- /* QAM Equalizer Setup */
- /* Equalizer */
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
- if (status < 0)
- goto error;
-
- /* Decision Feedback Equalizer */
- status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
- if (status < 0)
- goto error;
-
- status = write16(state, QAM_SY_SYNC_HWM__A, 6);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_AWM__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_LWM__A, 3);
- if (status < 0)
- goto error;
-
- /* QAM Slicer Settings */
-
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
- if (status < 0)
- goto error;
-
-
- /* QAM Loop Controller Coeficients */
-
- status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
- if (status < 0)
- goto error;
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
- if (status < 0)
- goto error;
-
-
- /* QAM FSM Tracking Parameters */
-
- status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-/*============================================================================*/
-
-/**
-* \brief QAM64 specific setup
-* \param demod instance of demod.
-* \return DRXStatus_t.
-*/
-static int SetQAM64(struct drxk_state *state)
-{
- int status = 0;
-
- dprintk(1, "\n");
- /* QAM Equalizer Setup */
- /* Equalizer */
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
- if (status < 0)
- goto error;
-
- /* Decision Feedback Equalizer */
- status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
- if (status < 0)
- goto error;
-
- status = write16(state, QAM_SY_SYNC_HWM__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_AWM__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_LWM__A, 3);
- if (status < 0)
- goto error;
-
- /* QAM Slicer Settings */
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
- if (status < 0)
- goto error;
-
-
- /* QAM Loop Controller Coeficients */
-
- status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
- if (status < 0)
- goto error;
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
- if (status < 0)
- goto error;
-
-
- /* QAM FSM Tracking Parameters */
-
- status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-/*============================================================================*/
-
-/**
-* \brief QAM128 specific setup
-* \param demod: instance of demod.
-* \return DRXStatus_t.
-*/
-static int SetQAM128(struct drxk_state *state)
-{
- int status = 0;
-
- dprintk(1, "\n");
- /* QAM Equalizer Setup */
- /* Equalizer */
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
- if (status < 0)
- goto error;
-
- /* Decision Feedback Equalizer */
- status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
- if (status < 0)
- goto error;
-
- status = write16(state, QAM_SY_SYNC_HWM__A, 6);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_AWM__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_LWM__A, 3);
- if (status < 0)
- goto error;
-
-
- /* QAM Slicer Settings */
-
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
- if (status < 0)
- goto error;
-
-
- /* QAM Loop Controller Coeficients */
-
- status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
- if (status < 0)
- goto error;
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
- if (status < 0)
- goto error;
-
- /* QAM FSM Tracking Parameters */
-
- status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-/*============================================================================*/
-
-/**
-* \brief QAM256 specific setup
-* \param demod: instance of demod.
-* \return DRXStatus_t.
-*/
-static int SetQAM256(struct drxk_state *state)
-{
- int status = 0;
-
- dprintk(1, "\n");
- /* QAM Equalizer Setup */
- /* Equalizer */
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
- if (status < 0)
- goto error;
-
- /* Decision Feedback Equalizer */
- status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
- if (status < 0)
- goto error;
- status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
- if (status < 0)
- goto error;
-
- status = write16(state, QAM_SY_SYNC_HWM__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_AWM__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_SYNC_LWM__A, 3);
- if (status < 0)
- goto error;
-
- /* QAM Slicer Settings */
-
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
- if (status < 0)
- goto error;
-
-
- /* QAM Loop Controller Coeficients */
-
- status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
- if (status < 0)
- goto error;
-
-
- /* QAM State Machine (FSM) Thresholds */
-
- status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
- if (status < 0)
- goto error;
-
- status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
- if (status < 0)
- goto error;
-
-
- /* QAM FSM Tracking Parameters */
-
- status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
- if (status < 0)
- goto error;
- status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-
-/*============================================================================*/
-/**
-* \brief Reset QAM block.
-* \param demod: instance of demod.
-* \param channel: pointer to channel data.
-* \return DRXStatus_t.
-*/
-static int QAMResetQAM(struct drxk_state *state)
-{
- int status;
- u16 cmdResult;
-
- dprintk(1, "\n");
- /* Stop QAM comstate->m_exec */
- status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
-
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-/*============================================================================*/
-
-/**
-* \brief Set QAM symbolrate.
-* \param demod: instance of demod.
-* \param channel: pointer to channel data.
-* \return DRXStatus_t.
-*/
-static int QAMSetSymbolrate(struct drxk_state *state)
-{
- u32 adcFrequency = 0;
- u32 symbFreq = 0;
- u32 iqmRcRate = 0;
- u16 ratesel = 0;
- u32 lcSymbRate = 0;
- int status;
-
- dprintk(1, "\n");
- /* Select & calculate correct IQM rate */
- adcFrequency = (state->m_sysClockFreq * 1000) / 3;
- ratesel = 0;
- /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
- if (state->props.symbol_rate <= 1188750)
- ratesel = 3;
- else if (state->props.symbol_rate <= 2377500)
- ratesel = 2;
- else if (state->props.symbol_rate <= 4755000)
- ratesel = 1;
- status = write16(state, IQM_FD_RATESEL__A, ratesel);
- if (status < 0)
- goto error;
-
- /*
- IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
- */
- symbFreq = state->props.symbol_rate * (1 << ratesel);
- if (symbFreq == 0) {
- /* Divide by zero */
- status = -EINVAL;
- goto error;
- }
- iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
- (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
- (1 << 23);
- status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
- if (status < 0)
- goto error;
- state->m_iqmRcRate = iqmRcRate;
- /*
- LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
- */
- symbFreq = state->props.symbol_rate;
- if (adcFrequency == 0) {
- /* Divide by zero */
- status = -EINVAL;
- goto error;
- }
- lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
- (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
- 16);
- if (lcSymbRate > 511)
- lcSymbRate = 511;
- status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-/*============================================================================*/
-
-/**
-* \brief Get QAM lock status.
-* \param demod: instance of demod.
-* \param channel: pointer to channel data.
-* \return DRXStatus_t.
-*/
-
-static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
-{
- int status;
- u16 Result[2] = { 0, 0 };
-
- dprintk(1, "\n");
- *pLockStatus = NOT_LOCKED;
- status = scu_command(state,
- SCU_RAM_COMMAND_STANDARD_QAM |
- SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
- Result);
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
- /* 0x0000 NOT LOCKED */
- } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
- /* 0x4000 DEMOD LOCKED */
- *pLockStatus = DEMOD_LOCK;
- } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
- /* 0x8000 DEMOD + FEC LOCKED (system lock) */
- *pLockStatus = MPEG_LOCK;
- } else {
- /* 0xC000 NEVER LOCKED */
- /* (system will never be able to lock to the signal) */
- /* TODO: check this, intermediate & standard specific lock states are not
- taken into account here */
- *pLockStatus = NEVER_LOCK;
- }
- return status;
-}
-
-#define QAM_MIRROR__M 0x03
-#define QAM_MIRROR_NORMAL 0x00
-#define QAM_MIRRORED 0x01
-#define QAM_MIRROR_AUTO_ON 0x02
-#define QAM_LOCKRANGE__M 0x10
-#define QAM_LOCKRANGE_NORMAL 0x10
-
-static int QAMDemodulatorCommand(struct drxk_state *state,
- int numberOfParameters)
-{
- int status;
- u16 cmdResult;
- u16 setParamParameters[4] = { 0, 0, 0, 0 };
-
- setParamParameters[0] = state->m_Constellation; /* modulation */
- setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
-
- if (numberOfParameters == 2) {
- u16 setEnvParameters[1] = { 0 };
-
- if (state->m_OperationMode == OM_QAM_ITU_C)
- setEnvParameters[0] = QAM_TOP_ANNEX_C;
- else
- setEnvParameters[0] = QAM_TOP_ANNEX_A;
-
- status = scu_command(state,
- SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
- 1, setEnvParameters, 1, &cmdResult);
- if (status < 0)
- goto error;
-
- status = scu_command(state,
- SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
- numberOfParameters, setParamParameters,
- 1, &cmdResult);
- } else if (numberOfParameters == 4) {
- if (state->m_OperationMode == OM_QAM_ITU_C)
- setParamParameters[2] = QAM_TOP_ANNEX_C;
- else
- setParamParameters[2] = QAM_TOP_ANNEX_A;
-
- setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
- /* Env parameters */
- /* check for LOCKRANGE Extented */
- /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
-
- status = scu_command(state,
- SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
- numberOfParameters, setParamParameters,
- 1, &cmdResult);
- } else {
- printk(KERN_WARNING "drxk: Unknown QAM demodulator parameter "
- "count %d\n", numberOfParameters);
- }
-
-error:
- if (status < 0)
- printk(KERN_WARNING "drxk: Warning %d on %s\n",
- status, __func__);
- return status;
-}
-
-static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
- s32 tunerFreqOffset)
-{
- int status;
- u16 cmdResult;
- int qamDemodParamCount = state->qam_demod_parameter_count;
-
- dprintk(1, "\n");
- /*
- * STEP 1: reset demodulator
- * resets FEC DI and FEC RS
- * resets QAM block
- * resets SCU variables
- */
- status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- status = QAMResetQAM(state);
- if (status < 0)
- goto error;
-
- /*
- * STEP 2: configure demodulator
- * -set params; resets IQM,QAM,FEC HW; initializes some
- * SCU variables
- */
- status = QAMSetSymbolrate(state);
- if (status < 0)
- goto error;
-
- /* Set params */
- switch (state->props.modulation) {
- case QAM_256:
- state->m_Constellation = DRX_CONSTELLATION_QAM256;
- break;
- case QAM_AUTO:
- case QAM_64:
- state->m_Constellation = DRX_CONSTELLATION_QAM64;
- break;
- case QAM_16:
- state->m_Constellation = DRX_CONSTELLATION_QAM16;
- break;
- case QAM_32:
- state->m_Constellation = DRX_CONSTELLATION_QAM32;
- break;
- case QAM_128:
- state->m_Constellation = DRX_CONSTELLATION_QAM128;
- break;
- default:
- status = -EINVAL;
- break;
- }
- if (status < 0)
- goto error;
-
- /* Use the 4-parameter if it's requested or we're probing for
- * the correct command. */
- if (state->qam_demod_parameter_count == 4
- || !state->qam_demod_parameter_count) {
- qamDemodParamCount = 4;
- status = QAMDemodulatorCommand(state, qamDemodParamCount);
- }
-
- /* Use the 2-parameter command if it was requested or if we're
- * probing for the correct command and the 4-parameter command
- * failed. */
- if (state->qam_demod_parameter_count == 2
- || (!state->qam_demod_parameter_count && status < 0)) {
- qamDemodParamCount = 2;
- status = QAMDemodulatorCommand(state, qamDemodParamCount);
- }
-
- if (status < 0) {
- dprintk(1, "Could not set demodulator parameters. Make "
- "sure qam_demod_parameter_count (%d) is correct for "
- "your firmware (%s).\n",
- state->qam_demod_parameter_count,
- state->microcode_name);
- goto error;
- } else if (!state->qam_demod_parameter_count) {
- dprintk(1, "Auto-probing the correct QAM demodulator command "
- "parameters was successful - using %d parameters.\n",
- qamDemodParamCount);
-
- /*
- * One of our commands was successful. We don't need to
- * auto-probe anymore, now that we got the correct command.
- */
- state->qam_demod_parameter_count = qamDemodParamCount;
- }
-
- /*
- * STEP 3: enable the system in a mode where the ADC provides valid
- * signal setup modulation independent registers
- */
-#if 0
- status = SetFrequency(channel, tunerFreqOffset));
- if (status < 0)
- goto error;
-#endif
- status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
- if (status < 0)
- goto error;
-
- /* Setup BER measurement */
- status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
- if (status < 0)
- goto error;
-
- /* Reset default values */
- status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
- if (status < 0)
- goto error;
- status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
- if (status < 0)
- goto error;
-
- /* Reset default LC values */
- status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_MODE__A, 7);
- if (status < 0)
- goto error;
-
- status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
- if (status < 0)
- goto error;
- status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
- if (status < 0)
- goto error;
-
- /* Mirroring, QAM-block starting point not inverted */
- status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
- if (status < 0)
- goto error;
-
- /* Halt SCU to enable safe non-atomic accesses */
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
- if (status < 0)
- goto error;
-
- /* STEP 4: modulation specific setup */
- switch (state->props.modulation) {
- case QAM_16:
- status = SetQAM16(state);
- break;
- case QAM_32:
- status = SetQAM32(state);
- break;
- case QAM_AUTO:
- case QAM_64:
- status = SetQAM64(state);
- break;
- case QAM_128:
- status = SetQAM128(state);
- break;
- case QAM_256:
- status = SetQAM256(state);
- break;
- default:
- status = -EINVAL;
- break;
- }
- if (status < 0)
- goto error;
-
- /* Activate SCU to enable SCU commands */
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
- if (status < 0)
- goto error;
-
- /* Re-configure MPEG output, requires knowledge of channel bitrate */
- /* extAttr->currentChannel.modulation = channel->modulation; */
- /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
- status = MPEGTSDtoSetup(state, state->m_OperationMode);
- if (status < 0)
- goto error;
-
- /* Start processes */
- status = MPEGTSStart(state);
- if (status < 0)
- goto error;
- status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
- if (status < 0)
- goto error;
- status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
- if (status < 0)
- goto error;
- status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
- if (status < 0)
- goto error;
-
- /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
- if (status < 0)
- goto error;
-
- /* update global DRXK data container */
-/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
-
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int SetQAMStandard(struct drxk_state *state,
- enum OperationMode oMode)
-{
- int status;
-#ifdef DRXK_QAM_TAPS
-#define DRXK_QAMA_TAPS_SELECT
-#include "drxk_filters.h"
-#undef DRXK_QAMA_TAPS_SELECT
-#endif
-
- dprintk(1, "\n");
-
- /* added antenna switch */
- SwitchAntennaToQAM(state);
-
- /* Ensure correct power-up mode */
- status = PowerUpQAM(state);
- if (status < 0)
- goto error;
- /* Reset QAM block */
- status = QAMResetQAM(state);
- if (status < 0)
- goto error;
-
- /* Setup IQM */
-
- status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
- if (status < 0)
- goto error;
- status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
- if (status < 0)
- goto error;
-
- /* Upload IQM Channel Filter settings by
- boot loader from ROM table */
- switch (oMode) {
- case OM_QAM_ITU_A:
- status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
- break;
- case OM_QAM_ITU_C:
- status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
- if (status < 0)
- goto error;
- status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
- break;
- default:
- status = -EINVAL;
- }
- if (status < 0)
- goto error;
-
- status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_SYMMETRIC__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
- if (status < 0)
- goto error;
-
- status = write16(state, IQM_RC_STRETCH__A, 21);
- if (status < 0)
- goto error;
- status = write16(state, IQM_AF_CLP_LEN__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, IQM_AF_CLP_TH__A, 448);
- if (status < 0)
- goto error;
- status = write16(state, IQM_AF_SNS_LEN__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
- if (status < 0)
- goto error;
-
- status = write16(state, IQM_FS_ADJ_SEL__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, IQM_RC_ADJ_SEL__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_ADJ_SEL__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, IQM_AF_UPD_SEL__A, 0);
- if (status < 0)
- goto error;
-
- /* IQM Impulse Noise Processing Unit */
- status = write16(state, IQM_CF_CLP_VAL__A, 500);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_DATATH__A, 1000);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_BYPASSDET__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_DET_LCT__A, 0);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_WND_LEN__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, IQM_CF_PKDTH__A, 1);
- if (status < 0)
- goto error;
- status = write16(state, IQM_AF_INC_BYPASS__A, 1);
- if (status < 0)
- goto error;
-
- /* turn on IQMAF. Must be done before setAgc**() */
- status = SetIqmAf(state, true);
- if (status < 0)
- goto error;
- status = write16(state, IQM_AF_START_LOCK__A, 0x01);
- if (status < 0)
- goto error;
-
- /* IQM will not be reset from here, sync ADC and update/init AGC */
- status = ADCSynchronization(state);
- if (status < 0)
- goto error;
-
- /* Set the FSM step period */
- status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
- if (status < 0)
- goto error;
-
- /* Halt SCU to enable safe non-atomic accesses */
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
- if (status < 0)
- goto error;
-
- /* No more resets of the IQM, current standard correctly set =>
- now AGCs can be configured. */
-
- status = InitAGC(state, true);
- if (status < 0)
- goto error;
- status = SetPreSaw(state, &(state->m_qamPreSawCfg));
- if (status < 0)
- goto error;
-
- /* Configure AGC's */
- status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
- if (status < 0)
- goto error;
- status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
- if (status < 0)
- goto error;
-
- /* Activate SCU to enable SCU commands */
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int WriteGPIO(struct drxk_state *state)
-{
- int status;
- u16 value = 0;
-
- dprintk(1, "\n");
- /* stop lock indicator process */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
- if (status < 0)
- goto error;
-
- /* Write magic word to enable pdr reg write */
- status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
- if (status < 0)
- goto error;
-
- if (state->m_hasSAWSW) {
- if (state->UIO_mask & 0x0001) { /* UIO-1 */
- /* write to io pad configuration register - output mode */
- status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
- if (status < 0)
- goto error;
-
- /* use corresponding bit in io data output registar */
- status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
- if (status < 0)
- goto error;
- if ((state->m_GPIO & 0x0001) == 0)
- value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
- else
- value |= 0x8000; /* write one to 15th bit - 1st UIO */
- /* write back to io data output register */
- status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
- if (status < 0)
- goto error;
- }
- if (state->UIO_mask & 0x0002) { /* UIO-2 */
- /* write to io pad configuration register - output mode */
- status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg);
- if (status < 0)
- goto error;
-
- /* use corresponding bit in io data output registar */
- status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
- if (status < 0)
- goto error;
- if ((state->m_GPIO & 0x0002) == 0)
- value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
- else
- value |= 0x4000; /* write one to 14th bit - 2st UIO */
- /* write back to io data output register */
- status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
- if (status < 0)
- goto error;
- }
- if (state->UIO_mask & 0x0004) { /* UIO-3 */
- /* write to io pad configuration register - output mode */
- status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg);
- if (status < 0)
- goto error;
-
- /* use corresponding bit in io data output registar */
- status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
- if (status < 0)
- goto error;
- if ((state->m_GPIO & 0x0004) == 0)
- value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
- else
- value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
- /* write back to io data output register */
- status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
- if (status < 0)
- goto error;
- }
- }
- /* Write magic word to disable pdr reg write */
- status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int SwitchAntennaToQAM(struct drxk_state *state)
-{
- int status = 0;
- bool gpio_state;
-
- dprintk(1, "\n");
-
- if (!state->antenna_gpio)
- return 0;
-
- gpio_state = state->m_GPIO & state->antenna_gpio;
-
- if (state->antenna_dvbt ^ gpio_state) {
- /* Antenna is on DVB-T mode. Switch */
- if (state->antenna_dvbt)
- state->m_GPIO &= ~state->antenna_gpio;
- else
- state->m_GPIO |= state->antenna_gpio;
- status = WriteGPIO(state);
- }
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-static int SwitchAntennaToDVBT(struct drxk_state *state)
-{
- int status = 0;
- bool gpio_state;
-
- dprintk(1, "\n");
-
- if (!state->antenna_gpio)
- return 0;
-
- gpio_state = state->m_GPIO & state->antenna_gpio;
-
- if (!(state->antenna_dvbt ^ gpio_state)) {
- /* Antenna is on DVB-C mode. Switch */
- if (state->antenna_dvbt)
- state->m_GPIO |= state->antenna_gpio;
- else
- state->m_GPIO &= ~state->antenna_gpio;
- status = WriteGPIO(state);
- }
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- return status;
-}
-
-
-static int PowerDownDevice(struct drxk_state *state)
-{
- /* Power down to requested mode */
- /* Backup some register settings */
- /* Set pins with possible pull-ups connected to them in input mode */
- /* Analog power down */
- /* ADC power down */
- /* Power down device */
- int status;
-
- dprintk(1, "\n");
- if (state->m_bPDownOpenBridge) {
- /* Open I2C bridge before power down of DRXK */
- status = ConfigureI2CBridge(state, true);
- if (status < 0)
- goto error;
- }
- /* driver 0.9.0 */
- status = DVBTEnableOFDMTokenRing(state, false);
- if (status < 0)
- goto error;
-
- status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
- if (status < 0)
- goto error;
- status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
- if (status < 0)
- goto error;
- state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
- status = HI_CfgCommand(state);
-error:
- if (status < 0)
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
-
- return status;
-}
-
-static int init_drxk(struct drxk_state *state)
-{
- int status = 0, n = 0;
- enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
- u16 driverVersion;
-
- dprintk(1, "\n");
- if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
- drxk_i2c_lock(state);
- status = PowerUpDevice(state);
- if (status < 0)
- goto error;
- status = DRXX_Open(state);
- if (status < 0)
- goto error;
- /* Soft reset of OFDM-, sys- and osc-clockdomain */
- status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
- if (status < 0)
- goto error;
- status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
- if (status < 0)
- goto error;
- /* TODO is this needed, if yes how much delay in worst case scenario */
- msleep(1);
- state->m_DRXK_A3_PATCH_CODE = true;
- status = GetDeviceCapabilities(state);
- if (status < 0)
- goto error;
-
- /* Bridge delay, uses oscilator clock */
- /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
- /* SDA brdige delay */
- state->m_HICfgBridgeDelay =
- (u16) ((state->m_oscClockFreq / 1000) *
- HI_I2C_BRIDGE_DELAY) / 1000;
- /* Clipping */
- if (state->m_HICfgBridgeDelay >
- SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
- state->m_HICfgBridgeDelay =
- SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
- }
- /* SCL bridge delay, same as SDA for now */
- state->m_HICfgBridgeDelay +=
- state->m_HICfgBridgeDelay <<
- SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
-
- status = InitHI(state);
- if (status < 0)
- goto error;
- /* disable various processes */
-#if NOA1ROM
- if (!(state->m_DRXK_A1_ROM_CODE)
- && !(state->m_DRXK_A2_ROM_CODE))
-#endif
- {
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
- if (status < 0)
- goto error;
- }
-
- /* disable MPEG port */
- status = MPEGTSDisable(state);
- if (status < 0)
- goto error;
-
- /* Stop AUD and SCU */
- status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
-
- /* enable token-ring bus through OFDM block for possible ucode upload */
- status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
- if (status < 0)
- goto error;
-
- /* include boot loader section */
- status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
- if (status < 0)
- goto error;
- status = BLChainCmd(state, 0, 6, 100);
- if (status < 0)
- goto error;
-
- if (state->fw) {
- status = DownloadMicrocode(state, state->fw->data,
- state->fw->size);
- if (status < 0)
- goto error;
- }
-
- /* disable token-ring bus through OFDM block for possible ucode upload */
- status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
- if (status < 0)
- goto error;
-
- /* Run SCU for a little while to initialize microcode version numbers */
- status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
- if (status < 0)
- goto error;
- status = DRXX_Open(state);
- if (status < 0)
- goto error;
- /* added for test */
- msleep(30);
-
- powerMode = DRXK_POWER_DOWN_OFDM;
- status = CtrlPowerMode(state, &powerMode);
- if (status < 0)
- goto error;
-
- /* Stamp driver version number in SCU data RAM in BCD code
- Done to enable field application engineers to retreive drxdriver version
- via I2C from SCU RAM.
- Not using SCU command interface for SCU register access since no
- microcode may be present.
- */
- driverVersion =
- (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
- (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
- ((DRXK_VERSION_MAJOR % 10) << 4) +
- (DRXK_VERSION_MINOR % 10);
- status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
- if (status < 0)
- goto error;
- driverVersion =
- (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
- (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
- (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
- (DRXK_VERSION_PATCH % 10);
- status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
- if (status < 0)
- goto error;
-
- printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
- DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
- DRXK_VERSION_PATCH);
-
- /* Dirty fix of default values for ROM/PATCH microcode
- Dirty because this fix makes it impossible to setup suitable values
- before calling DRX_Open. This solution requires changes to RF AGC speed
- to be done via the CTRL function after calling DRX_Open */
-
- /* m_dvbtRfAgcCfg.speed = 3; */
-
- /* Reset driver debug flags to 0 */
- status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
- if (status < 0)
- goto error;
- /* driver 0.9.0 */
- /* Setup FEC OC:
- NOTE: No more full FEC resets allowed afterwards!! */
- status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
- if (status < 0)
- goto error;
- /* MPEGTS functions are still the same */
- status = MPEGTSDtoInit(state);
- if (status < 0)
- goto error;
- status = MPEGTSStop(state);
- if (status < 0)
- goto error;
- status = MPEGTSConfigurePolarity(state);
- if (status < 0)
- goto error;
- status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
- if (status < 0)
- goto error;
- /* added: configure GPIO */
- status = WriteGPIO(state);
- if (status < 0)
- goto error;
-
- state->m_DrxkState = DRXK_STOPPED;
-
- if (state->m_bPowerDown) {
- status = PowerDownDevice(state);
- if (status < 0)
- goto error;
- state->m_DrxkState = DRXK_POWERED_DOWN;
- } else
- state->m_DrxkState = DRXK_STOPPED;
-
- /* Initialize the supported delivery systems */
- n = 0;
- if (state->m_hasDVBC) {
- state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
- state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
- strlcat(state->frontend.ops.info.name, " DVB-C",
- sizeof(state->frontend.ops.info.name));
- }
- if (state->m_hasDVBT) {
- state->frontend.ops.delsys[n++] = SYS_DVBT;
- strlcat(state->frontend.ops.info.name, " DVB-T",
- sizeof(state->frontend.ops.info.name));
- }
- drxk_i2c_unlock(state);
- }
-error:
- if (status < 0) {
- state->m_DrxkState = DRXK_NO_DEV;
- drxk_i2c_unlock(state);
- printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
- }
-
- return status;
-}
-
-static void load_firmware_cb(const struct firmware *fw,
- void *context)
-{
- struct drxk_state *state = context;
-
- dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
- if (!fw) {
- printk(KERN_ERR
- "drxk: Could not load firmware file %s.\n",
- state->microcode_name);
- printk(KERN_INFO
- "drxk: Copy %s to your hotplug directory!\n",
- state->microcode_name);
- state->microcode_name = NULL;
-
- /*
- * As firmware is now load asynchronous, it is not possible
- * anymore to fail at frontend attach. We might silently
- * return here, and hope that the driver won't crash.
- * We might also change all DVB callbacks to return -ENODEV
- * if the device is not initialized.
- * As the DRX-K devices have their own internal firmware,
- * let's just hope that it will match a firmware revision
- * compatible with this driver and proceed.
- */
- }
- state->fw = fw;
-
- init_drxk(state);
-}
-
-static void drxk_release(struct dvb_frontend *fe)
-{
- struct drxk_state *state = fe->demodulator_priv;
-
- dprintk(1, "\n");
- if (state->fw)
- release_firmware(state->fw);
-
- kfree(state);
-}
-
-static int drxk_sleep(struct dvb_frontend *fe)
-{
- struct drxk_state *state = fe->demodulator_priv;
-
- dprintk(1, "\n");
-
- if (state->m_DrxkState == DRXK_NO_DEV)
- return -ENODEV;
- if (state->m_DrxkState == DRXK_UNINITIALIZED)
- return 0;
-
- ShutDown(state);
- return 0;
-}
-
-static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- struct drxk_state *state = fe->demodulator_priv;
-
- dprintk(1, ": %s\n", enable ? "enable" : "disable");
-
- if (state->m_DrxkState == DRXK_NO_DEV)
- return -ENODEV;
-
- return ConfigureI2CBridge(state, enable ? true : false);
-}
-
-static int drxk_set_parameters(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- u32 delsys = p->delivery_system, old_delsys;
- struct drxk_state *state = fe->demodulator_priv;
- u32 IF;
-
- dprintk(1, "\n");
-
- if (state->m_DrxkState == DRXK_NO_DEV)
- return -ENODEV;
-
- if (state->m_DrxkState == DRXK_UNINITIALIZED)
- return -EAGAIN;
-
- if (!fe->ops.tuner_ops.get_if_frequency) {
- printk(KERN_ERR
- "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
- return -EINVAL;
- }
-
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 0);
-
- old_delsys = state->props.delivery_system;
- state->props = *p;
-
- if (old_delsys != delsys) {
- ShutDown(state);
- switch (delsys) {
- case SYS_DVBC_ANNEX_A:
- case SYS_DVBC_ANNEX_C:
- if (!state->m_hasDVBC)
- return -EINVAL;
- state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
- if (state->m_itut_annex_c)
- SetOperationMode(state, OM_QAM_ITU_C);
- else
- SetOperationMode(state, OM_QAM_ITU_A);
- break;
- case SYS_DVBT:
- if (!state->m_hasDVBT)
- return -EINVAL;
- SetOperationMode(state, OM_DVBT);
- break;
- default:
- return -EINVAL;
- }
- }
-
- fe->ops.tuner_ops.get_if_frequency(fe, &IF);
- Start(state, 0, IF);
-
- /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
-
- return 0;
-}
-
-static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct drxk_state *state = fe->demodulator_priv;
- u32 stat;
-
- dprintk(1, "\n");
-
- if (state->m_DrxkState == DRXK_NO_DEV)
- return -ENODEV;
- if (state->m_DrxkState == DRXK_UNINITIALIZED)
- return -EAGAIN;
-
- *status = 0;
- GetLockStatus(state, &stat, 0);
- if (stat == MPEG_LOCK)
- *status |= 0x1f;
- if (stat == FEC_LOCK)
- *status |= 0x0f;
- if (stat == DEMOD_LOCK)
- *status |= 0x07;
- return 0;
-}
-
-static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct drxk_state *state = fe->demodulator_priv;
-
- dprintk(1, "\n");
-
- if (state->m_DrxkState == DRXK_NO_DEV)
- return -ENODEV;
- if (state->m_DrxkState == DRXK_UNINITIALIZED)
- return -EAGAIN;
-
- *ber = 0;
- return 0;
-}
-
-static int drxk_read_signal_strength(struct dvb_frontend *fe,
- u16 *strength)
-{
- struct drxk_state *state = fe->demodulator_priv;
- u32 val = 0;
-
- dprintk(1, "\n");
-
- if (state->m_DrxkState == DRXK_NO_DEV)
- return -ENODEV;
- if (state->m_DrxkState == DRXK_UNINITIALIZED)
- return -EAGAIN;
-
- ReadIFAgc(state, &val);
- *strength = val & 0xffff;
- return 0;
-}
-
-static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- struct drxk_state *state = fe->demodulator_priv;
- s32 snr2;
-
- dprintk(1, "\n");
-
- if (state->m_DrxkState == DRXK_NO_DEV)
- return -ENODEV;
- if (state->m_DrxkState == DRXK_UNINITIALIZED)
- return -EAGAIN;
-
- GetSignalToNoise(state, &snr2);
- *snr = snr2 & 0xffff;
- return 0;
-}
-
-static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- struct drxk_state *state = fe->demodulator_priv;
- u16 err;
-
- dprintk(1, "\n");
-
- if (state->m_DrxkState == DRXK_NO_DEV)
- return -ENODEV;
- if (state->m_DrxkState == DRXK_UNINITIALIZED)
- return -EAGAIN;
-
- DVBTQAMGetAccPktErr(state, &err);
- *ucblocks = (u32) err;
- return 0;
-}
-
-static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
- *sets)
-{
- struct drxk_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-
- dprintk(1, "\n");
-
- if (state->m_DrxkState == DRXK_NO_DEV)
- return -ENODEV;
- if (state->m_DrxkState == DRXK_UNINITIALIZED)
- return -EAGAIN;
-
- switch (p->delivery_system) {
- case SYS_DVBC_ANNEX_A:
- case SYS_DVBC_ANNEX_C:
- case SYS_DVBT:
- sets->min_delay_ms = 3000;
- sets->max_drift = 0;
- sets->step_size = 0;
- return 0;
- default:
- return -EINVAL;
- }
-}
-
-static struct dvb_frontend_ops drxk_ops = {
- /* .delsys will be filled dynamically */
- .info = {
- .name = "DRXK",
- .frequency_min = 47000000,
- .frequency_max = 865000000,
- /* For DVB-C */
- .symbol_rate_min = 870000,
- .symbol_rate_max = 11700000,
- /* For DVB-T */
- .frequency_stepsize = 166667,
-
- .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
- FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
- FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
- FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
- },
-
- .release = drxk_release,
- .sleep = drxk_sleep,
- .i2c_gate_ctrl = drxk_gate_ctrl,
-
- .set_frontend = drxk_set_parameters,
- .get_tune_settings = drxk_get_tune_settings,
-
- .read_status = drxk_read_status,
- .read_ber = drxk_read_ber,
- .read_signal_strength = drxk_read_signal_strength,
- .read_snr = drxk_read_snr,
- .read_ucblocks = drxk_read_ucblocks,
-};
-
-struct dvb_frontend *drxk_attach(const struct drxk_config *config,
- struct i2c_adapter *i2c)
-{
- struct drxk_state *state = NULL;
- u8 adr = config->adr;
- int status;
-
- dprintk(1, "\n");
- state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
- if (!state)
- return NULL;
-
- state->i2c = i2c;
- state->demod_address = adr;
- state->single_master = config->single_master;
- state->microcode_name = config->microcode_name;
- state->qam_demod_parameter_count = config->qam_demod_parameter_count;
- state->no_i2c_bridge = config->no_i2c_bridge;
- state->antenna_gpio = config->antenna_gpio;
- state->antenna_dvbt = config->antenna_dvbt;
- state->m_ChunkSize = config->chunk_size;
- state->enable_merr_cfg = config->enable_merr_cfg;
-
- if (config->dynamic_clk) {
- state->m_DVBTStaticCLK = 0;
- state->m_DVBCStaticCLK = 0;
- } else {
- state->m_DVBTStaticCLK = 1;
- state->m_DVBCStaticCLK = 1;
- }
-
-
- if (config->mpeg_out_clk_strength)
- state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07;
- else
- state->m_TSClockkStrength = 0x06;
-
- if (config->parallel_ts)
- state->m_enableParallel = true;
- else
- state->m_enableParallel = false;
-
- /* NOTE: as more UIO bits will be used, add them to the mask */
- state->UIO_mask = config->antenna_gpio;
-
- /* Default gpio to DVB-C */
- if (!state->antenna_dvbt && state->antenna_gpio)
- state->m_GPIO |= state->antenna_gpio;
- else
- state->m_GPIO &= ~state->antenna_gpio;
-
- mutex_init(&state->mutex);
-
- memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
- state->frontend.demodulator_priv = state;
-
- init_state(state);
-
- /* Load firmware and initialize DRX-K */
- if (state->microcode_name) {
- status = request_firmware_nowait(THIS_MODULE, 1,
- state->microcode_name,
- state->i2c->dev.parent,
- GFP_KERNEL,
- state, load_firmware_cb);
- if (status < 0) {
- printk(KERN_ERR
- "drxk: failed to request a firmware\n");
- return NULL;
- }
- } else if (init_drxk(state) < 0)
- goto error;
-
- printk(KERN_INFO "drxk: frontend initialized.\n");
- return &state->frontend;
-
-error:
- printk(KERN_ERR "drxk: not found\n");
- kfree(state);
- return NULL;
-}
-EXPORT_SYMBOL(drxk_attach);
-
-MODULE_DESCRIPTION("DRX-K driver");
-MODULE_AUTHOR("Ralph Metzler");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/drxk_hard.h b/drivers/media/dvb/frontends/drxk_hard.h
deleted file mode 100644
index 6bb9fc4a7b9..00000000000
--- a/drivers/media/dvb/frontends/drxk_hard.h
+++ /dev/null
@@ -1,364 +0,0 @@
-#include "drxk_map.h"
-
-#define DRXK_VERSION_MAJOR 0
-#define DRXK_VERSION_MINOR 9
-#define DRXK_VERSION_PATCH 4300
-
-#define HI_I2C_DELAY 42
-#define HI_I2C_BRIDGE_DELAY 350
-#define DRXK_MAX_RETRIES 100
-
-#define DRIVER_4400 1
-
-#define DRXX_JTAGID 0x039210D9
-#define DRXX_J_JTAGID 0x239310D9
-#define DRXX_K_JTAGID 0x039210D9
-
-#define DRX_UNKNOWN 254
-#define DRX_AUTO 255
-
-#define DRX_SCU_READY 0
-#define DRXK_MAX_WAITTIME (200)
-#define SCU_RESULT_OK 0
-#define SCU_RESULT_SIZE -4
-#define SCU_RESULT_INVPAR -3
-#define SCU_RESULT_UNKSTD -2
-#define SCU_RESULT_UNKCMD -1
-
-#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
-#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
-#endif
-
-#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/
-#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/
-#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/
-#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/
-#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/
-#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/
-#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/
-#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/
-
-#define IQM_CF_OUT_ENA_OFDM__M 0x4
-#define IQM_FS_ADJ_SEL_B_QAM 0x1
-#define IQM_FS_ADJ_SEL_B_OFF 0x0
-#define IQM_FS_ADJ_SEL_B_VSB 0x2
-#define IQM_RC_ADJ_SEL_B_OFF 0x0
-#define IQM_RC_ADJ_SEL_B_QAM 0x1
-#define IQM_RC_ADJ_SEL_B_VSB 0x2
-
-enum OperationMode {
- OM_NONE,
- OM_QAM_ITU_A,
- OM_QAM_ITU_B,
- OM_QAM_ITU_C,
- OM_DVBT
-};
-
-enum DRXPowerMode {
- DRX_POWER_UP = 0,
- DRX_POWER_MODE_1,
- DRX_POWER_MODE_2,
- DRX_POWER_MODE_3,
- DRX_POWER_MODE_4,
- DRX_POWER_MODE_5,
- DRX_POWER_MODE_6,
- DRX_POWER_MODE_7,
- DRX_POWER_MODE_8,
-
- DRX_POWER_MODE_9,
- DRX_POWER_MODE_10,
- DRX_POWER_MODE_11,
- DRX_POWER_MODE_12,
- DRX_POWER_MODE_13,
- DRX_POWER_MODE_14,
- DRX_POWER_MODE_15,
- DRX_POWER_MODE_16,
- DRX_POWER_DOWN = 255
-};
-
-
-/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
-#ifndef DRXK_POWER_DOWN_OFDM
-#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1
-#endif
-
-/** /brief Intermediate power mode for DRXK, power down core (sysclk) */
-#ifndef DRXK_POWER_DOWN_CORE
-#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9
-#endif
-
-/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */
-#ifndef DRXK_POWER_DOWN_PLL
-#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10
-#endif
-
-
-enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
-enum EDrxkState {
- DRXK_UNINITIALIZED = 0,
- DRXK_STOPPED,
- DRXK_DTV_STARTED,
- DRXK_ATV_STARTED,
- DRXK_POWERED_DOWN,
- DRXK_NO_DEV /* If drxk init failed */
-};
-
-enum EDrxkCoefArrayIndex {
- DRXK_COEF_IDX_MN = 0,
- DRXK_COEF_IDX_FM ,
- DRXK_COEF_IDX_L ,
- DRXK_COEF_IDX_LP ,
- DRXK_COEF_IDX_BG ,
- DRXK_COEF_IDX_DK ,
- DRXK_COEF_IDX_I ,
- DRXK_COEF_IDX_MAX
-};
-enum EDrxkSifAttenuation {
- DRXK_SIF_ATTENUATION_0DB,
- DRXK_SIF_ATTENUATION_3DB,
- DRXK_SIF_ATTENUATION_6DB,
- DRXK_SIF_ATTENUATION_9DB
-};
-enum EDrxkConstellation {
- DRX_CONSTELLATION_BPSK = 0,
- DRX_CONSTELLATION_QPSK,
- DRX_CONSTELLATION_PSK8,
- DRX_CONSTELLATION_QAM16,
- DRX_CONSTELLATION_QAM32,
- DRX_CONSTELLATION_QAM64,
- DRX_CONSTELLATION_QAM128,
- DRX_CONSTELLATION_QAM256,
- DRX_CONSTELLATION_QAM512,
- DRX_CONSTELLATION_QAM1024,
- DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
- DRX_CONSTELLATION_AUTO = DRX_AUTO
-};
-enum EDrxkInterleaveMode {
- DRXK_QAM_I12_J17 = 16,
- DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
-};
-enum {
- DRXK_SPIN_A1 = 0,
- DRXK_SPIN_A2,
- DRXK_SPIN_A3,
- DRXK_SPIN_UNKNOWN
-};
-
-enum DRXKCfgDvbtSqiSpeed {
- DRXK_DVBT_SQI_SPEED_FAST = 0,
- DRXK_DVBT_SQI_SPEED_MEDIUM,
- DRXK_DVBT_SQI_SPEED_SLOW,
- DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
-} ;
-
-enum DRXFftmode_t {
- DRX_FFTMODE_2K = 0,
- DRX_FFTMODE_4K,
- DRX_FFTMODE_8K,
- DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
- DRX_FFTMODE_AUTO = DRX_AUTO
-};
-
-enum DRXMPEGStrWidth_t {
- DRX_MPEG_STR_WIDTH_1,
- DRX_MPEG_STR_WIDTH_8
-};
-
-enum DRXQamLockRange_t {
- DRX_QAM_LOCKRANGE_NORMAL,
- DRX_QAM_LOCKRANGE_EXTENDED
-};
-
-struct DRXKCfgDvbtEchoThres_t {
- u16 threshold;
- enum DRXFftmode_t fftMode;
-} ;
-
-struct SCfgAgc {
- enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */
- u16 outputLevel; /* range dependent on AGC */
- u16 minOutputLevel; /* range dependent on AGC */
- u16 maxOutputLevel; /* range dependent on AGC */
- u16 speed; /* range dependent on AGC */
- u16 top; /* rf-agc take over point */
- u16 cutOffCurrent; /* rf-agc is accelerated if output current
- is below cut-off current */
- u16 IngainTgtMax;
- u16 FastClipCtrlDelay;
-};
-
-struct SCfgPreSaw {
- u16 reference; /* pre SAW reference value, range 0 .. 31 */
- bool usePreSaw; /* TRUE algorithms must use pre SAW sense */
-};
-
-struct DRXKOfdmScCmd_t {
- u16 cmd; /**< Command number */
- u16 subcmd; /**< Sub-command parameter*/
- u16 param0; /**< General purpous param */
- u16 param1; /**< General purpous param */
- u16 param2; /**< General purpous param */
- u16 param3; /**< General purpous param */
- u16 param4; /**< General purpous param */
-};
-
-struct drxk_state {
- struct dvb_frontend frontend;
- struct dtv_frontend_properties props;
- struct device *dev;
-
- struct i2c_adapter *i2c;
- u8 demod_address;
- void *priv;
-
- struct mutex mutex;
-
- u32 m_Instance; /**< Channel 1,2,3 or 4 */
-
- int m_ChunkSize;
- u8 Chunk[256];
-
- bool m_hasLNA;
- bool m_hasDVBT;
- bool m_hasDVBC;
- bool m_hasAudio;
- bool m_hasATV;
- bool m_hasOOB;
- bool m_hasSAWSW; /**< TRUE if mat_tx is available */
- bool m_hasGPIO1; /**< TRUE if mat_rx is available */
- bool m_hasGPIO2; /**< TRUE if GPIO is available */
- bool m_hasIRQN; /**< TRUE if IRQN is available */
- u16 m_oscClockFreq;
- u16 m_HICfgTimingDiv;
- u16 m_HICfgBridgeDelay;
- u16 m_HICfgWakeUpKey;
- u16 m_HICfgTimeout;
- u16 m_HICfgCtrl;
- s32 m_sysClockFreq; /**< system clock frequency in kHz */
-
- enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */
- enum OperationMode m_OperationMode; /**< digital standards */
- struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */
- struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */
- u16 m_vsbPgaCfg; /**< settings for VSB PGA */
- struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */
- s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */
- s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */
- bool m_smartAntInverted;
- bool m_bDebugEnableBridge;
- bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */
- bool m_bPowerDown; /**< Power down when not used */
-
- u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */
-
- bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
- bool m_insertRSByte; /**< If TRUE, insert RS byte */
- bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
- bool m_invertDATA; /**< If TRUE, invert DATA signals */
- bool m_invertERR; /**< If TRUE, invert ERR signal */
- bool m_invertSTR; /**< If TRUE, invert STR signals */
- bool m_invertVAL; /**< If TRUE, invert VAL signals */
- bool m_invertCLK; /**< If TRUE, invert CLK signals */
- bool m_DVBCStaticCLK;
- bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
- be used, otherwise clockrate will
- adapt to the bitrate of the TS */
- u32 m_DVBTBitrate;
- u32 m_DVBCBitrate;
-
- u8 m_TSDataStrength;
- u8 m_TSClockkStrength;
-
- bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
-
- enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */
- u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
- static clockrate is selected */
-
- /* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */
- s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
- s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
-
- bool m_disableTEIhandling;
-
- bool m_RfAgcPol;
- bool m_IfAgcPol;
-
- struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */
- struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */
- struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */
- bool m_phaseCorrectionBypass;
- s16 m_atvTopVidPeak;
- u16 m_atvTopNoiseTh;
- enum EDrxkSifAttenuation m_sifAttenuation;
- bool m_enableCVBSOutput;
- bool m_enableSIFOutput;
- bool m_bMirrorFreqSpect;
- enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */
- u32 m_CurrSymbolRate; /**< Current QAM symbol rate */
- struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */
- struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */
- u16 m_qamPgaCfg; /**< settings for QAM PGA */
- struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */
- enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */
- u16 m_fecRsPlen;
- u16 m_fecRsPrescale;
-
- enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
-
- u16 m_GPIO;
- u16 m_GPIOCfg;
-
- struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */
- struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */
- struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */
-
- u16 m_agcFastClipCtrlDelay;
- bool m_adcCompPassed;
- u16 m_adcCompCoef[64];
- u16 m_adcState;
-
- u8 *m_microcode;
- int m_microcode_length;
- bool m_DRXK_A1_PATCH_CODE;
- bool m_DRXK_A1_ROM_CODE;
- bool m_DRXK_A2_ROM_CODE;
- bool m_DRXK_A3_ROM_CODE;
- bool m_DRXK_A2_PATCH_CODE;
- bool m_DRXK_A3_PATCH_CODE;
-
- bool m_rfmirror;
- u8 m_deviceSpin;
- u32 m_iqmRcRate;
-
- enum DRXPowerMode m_currentPowerMode;
-
- /* when true, avoids other devices to use the I2C bus */
- bool drxk_i2c_exclusive_lock;
-
- /*
- * Configurable parameters at the driver. They stores the values found
- * at struct drxk_config.
- */
-
- u16 UIO_mask; /* Bits used by UIO */
-
- bool enable_merr_cfg;
- bool single_master;
- bool no_i2c_bridge;
- bool antenna_dvbt;
- u16 antenna_gpio;
-
- /* Firmware */
- const char *microcode_name;
- struct completion fw_wait_load;
- const struct firmware *fw;
- int qam_demod_parameter_count;
-};
-
-#define NEVER_LOCK 0
-#define NOT_LOCKED 1
-#define DEMOD_LOCK 2
-#define FEC_LOCK 3
-#define MPEG_LOCK 4
-
diff --git a/drivers/media/dvb/frontends/drxk_map.h b/drivers/media/dvb/frontends/drxk_map.h
deleted file mode 100644
index 23e16c12f23..00000000000
--- a/drivers/media/dvb/frontends/drxk_map.h
+++ /dev/null
@@ -1,451 +0,0 @@
-#define AUD_COMM_EXEC__A 0x1000000
-#define AUD_COMM_EXEC_STOP 0x0
-#define FEC_COMM_EXEC__A 0x1C00000
-#define FEC_COMM_EXEC_STOP 0x0
-#define FEC_COMM_EXEC_ACTIVE 0x1
-#define FEC_DI_COMM_EXEC__A 0x1C20000
-#define FEC_DI_COMM_EXEC_STOP 0x0
-#define FEC_DI_INPUT_CTL__A 0x1C20016
-#define FEC_RS_COMM_EXEC__A 0x1C30000
-#define FEC_RS_COMM_EXEC_STOP 0x0
-#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012
-#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013
-#define FEC_OC_MODE__A 0x1C40011
-#define FEC_OC_MODE_PARITY__M 0x1
-#define FEC_OC_DTO_MODE__A 0x1C40014
-#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1
-#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4
-#define FEC_OC_DTO_PERIOD__A 0x1C40015
-#define FEC_OC_DTO_BURST_LEN__A 0x1C40018
-#define FEC_OC_FCT_MODE__A 0x1C4001A
-#define FEC_OC_FCT_MODE__PRE 0x0
-#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1
-#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
-#define FEC_OC_TMD_MODE__A 0x1C4001E
-#define FEC_OC_TMD_COUNT__A 0x1C4001F
-#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020
-#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021
-#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023
-#define FEC_OC_AVR_PARM_A__A 0x1C40026
-#define FEC_OC_AVR_PARM_B__A 0x1C40027
-#define FEC_OC_RCN_GAIN__A 0x1C4002E
-#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030
-#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032
-#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033
-#define FEC_OC_SNC_MODE__A 0x1C40040
-#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10
-#define FEC_OC_SNC_LWM__A 0x1C40041
-#define FEC_OC_SNC_HWM__A 0x1C40042
-#define FEC_OC_SNC_UNLOCK__A 0x1C40043
-#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046
-#define FEC_OC_IPR_MODE__A 0x1C40048
-#define FEC_OC_IPR_MODE_SERIAL__M 0x1
-#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4
-#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10
-#define FEC_OC_IPR_INVERT__A 0x1C40049
-#define FEC_OC_IPR_INVERT_MD0__M 0x1
-#define FEC_OC_IPR_INVERT_MD1__M 0x2
-#define FEC_OC_IPR_INVERT_MD2__M 0x4
-#define FEC_OC_IPR_INVERT_MD3__M 0x8
-#define FEC_OC_IPR_INVERT_MD4__M 0x10
-#define FEC_OC_IPR_INVERT_MD5__M 0x20
-#define FEC_OC_IPR_INVERT_MD6__M 0x40
-#define FEC_OC_IPR_INVERT_MD7__M 0x80
-#define FEC_OC_IPR_INVERT_MERR__M 0x100
-#define FEC_OC_IPR_INVERT_MSTRT__M 0x200
-#define FEC_OC_IPR_INVERT_MVAL__M 0x400
-#define FEC_OC_IPR_INVERT_MCLK__M 0x800
-#define FEC_OC_OCR_INVERT__A 0x1C40052
-#define IQM_COMM_EXEC__A 0x1800000
-#define IQM_COMM_EXEC_B_STOP 0x0
-#define IQM_COMM_EXEC_B_ACTIVE 0x1
-#define IQM_FS_RATE_OFS_LO__A 0x1820010
-#define IQM_FS_ADJ_SEL__A 0x1820014
-#define IQM_FS_ADJ_SEL_B_OFF 0x0
-#define IQM_FS_ADJ_SEL_B_QAM 0x1
-#define IQM_FS_ADJ_SEL_B_VSB 0x2
-#define IQM_FD_RATESEL__A 0x1830010
-#define IQM_RC_RATE_OFS_LO__A 0x1840010
-#define IQM_RC_RATE_OFS_LO__W 16
-#define IQM_RC_RATE_OFS_LO__M 0xFFFF
-#define IQM_RC_RATE_OFS_HI__M 0xFF
-#define IQM_RC_ADJ_SEL__A 0x1840014
-#define IQM_RC_ADJ_SEL_B_OFF 0x0
-#define IQM_RC_ADJ_SEL_B_QAM 0x1
-#define IQM_RC_ADJ_SEL_B_VSB 0x2
-#define IQM_RC_STRETCH__A 0x1840016
-#define IQM_CF_COMM_INT_MSK__A 0x1860006
-#define IQM_CF_SYMMETRIC__A 0x1860010
-#define IQM_CF_MIDTAP__A 0x1860011
-#define IQM_CF_MIDTAP_RE__B 0
-#define IQM_CF_MIDTAP_IM__B 1
-#define IQM_CF_OUT_ENA__A 0x1860012
-#define IQM_CF_OUT_ENA_QAM__B 1
-#define IQM_CF_OUT_ENA_OFDM__M 0x4
-#define IQM_CF_ADJ_SEL__A 0x1860013
-#define IQM_CF_SCALE__A 0x1860014
-#define IQM_CF_SCALE_SH__A 0x1860015
-#define IQM_CF_SCALE_SH__PRE 0x0
-#define IQM_CF_POW_MEAS_LEN__A 0x1860017
-#define IQM_CF_DS_ENA__A 0x1860019
-#define IQM_CF_TAP_RE0__A 0x1860020
-#define IQM_CF_TAP_IM0__A 0x1860040
-#define IQM_CF_CLP_VAL__A 0x1860060
-#define IQM_CF_DATATH__A 0x1860061
-#define IQM_CF_PKDTH__A 0x1860062
-#define IQM_CF_WND_LEN__A 0x1860063
-#define IQM_CF_DET_LCT__A 0x1860064
-#define IQM_CF_BYPASSDET__A 0x1860067
-#define IQM_AF_COMM_EXEC__A 0x1870000
-#define IQM_AF_COMM_EXEC_ACTIVE 0x1
-#define IQM_AF_CLKNEG__A 0x1870012
-#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2
-#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0
-#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2
-#define IQM_AF_START_LOCK__A 0x187001B
-#define IQM_AF_PHASE0__A 0x187001C
-#define IQM_AF_PHASE1__A 0x187001D
-#define IQM_AF_PHASE2__A 0x187001E
-#define IQM_AF_CLP_LEN__A 0x1870023
-#define IQM_AF_CLP_TH__A 0x1870024
-#define IQM_AF_SNS_LEN__A 0x1870026
-#define IQM_AF_AGC_IF__A 0x1870028
-#define IQM_AF_AGC_RF__A 0x1870029
-#define IQM_AF_PDREF__A 0x187002B
-#define IQM_AF_PDREF__M 0x1F
-#define IQM_AF_STDBY__A 0x187002C
-#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2
-#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4
-#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8
-#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10
-#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20
-#define IQM_AF_AMUX__A 0x187002D
-#define IQM_AF_AMUX_SIGNAL2ADC 0x1
-#define IQM_AF_UPD_SEL__A 0x187002F
-#define IQM_AF_INC_LCT__A 0x1870034
-#define IQM_AF_INC_BYPASS__A 0x1870036
-#define OFDM_CP_COMM_EXEC__A 0x2800000
-#define OFDM_CP_COMM_EXEC_STOP 0x0
-#define OFDM_EC_SB_PRIOR__A 0x3410013
-#define OFDM_EC_SB_PRIOR_HI 0x0
-#define OFDM_EC_SB_PRIOR_LO 0x1
-#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054
-#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3
-#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2
-#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056
-#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7
-#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4
-#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E
-#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F
-#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060
-#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061
-#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062
-#define OFDM_LC_COMM_EXEC__A 0x3800000
-#define OFDM_LC_COMM_EXEC_STOP 0x0
-#define OFDM_SC_COMM_EXEC__A 0x3C00000
-#define OFDM_SC_COMM_EXEC_STOP 0x0
-#define OFDM_SC_COMM_STATE__A 0x3C00001
-#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040
-#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041
-#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042
-#define OFDM_SC_RA_RAM_CMD__A 0x3C20043
-#define OFDM_SC_RA_RAM_CMD_NULL 0x0
-#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1
-#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
-#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4
-#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5
-#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6
-#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7
-#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8
-#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
-#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1
-#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048
-#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3
-#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
-#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0
-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4
-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8
-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC
-#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
-#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
-#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
-#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0
-#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40
-#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80
-#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
-#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
-#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
-#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1
-#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
-#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4
-#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8
-#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10
-#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B
-#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1
-#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2
-#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4
-#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8
-#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D
-#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E
-#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F
-#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0
-#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF
-#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8
-#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00
-#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050
-#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800
-#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D
-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0
-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1
-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3
-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4
-#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8
-#define QAM_COMM_EXEC__A 0x1400000
-#define QAM_COMM_EXEC_STOP 0x0
-#define QAM_COMM_EXEC_ACTIVE 0x1
-#define QAM_TOP_ANNEX_A 0x0
-#define QAM_TOP_ANNEX_C 0x2
-#define QAM_SL_ERR_POWER__A 0x1430017
-#define QAM_DQ_QUAL_FUN0__A 0x1440018
-#define QAM_DQ_QUAL_FUN1__A 0x1440019
-#define QAM_DQ_QUAL_FUN2__A 0x144001A
-#define QAM_DQ_QUAL_FUN3__A 0x144001B
-#define QAM_DQ_QUAL_FUN4__A 0x144001C
-#define QAM_DQ_QUAL_FUN5__A 0x144001D
-#define QAM_LC_MODE__A 0x1450010
-#define QAM_LC_QUAL_TAB0__A 0x1450018
-#define QAM_LC_QUAL_TAB1__A 0x1450019
-#define QAM_LC_QUAL_TAB2__A 0x145001A
-#define QAM_LC_QUAL_TAB3__A 0x145001B
-#define QAM_LC_QUAL_TAB4__A 0x145001C
-#define QAM_LC_QUAL_TAB5__A 0x145001D
-#define QAM_LC_QUAL_TAB6__A 0x145001E
-#define QAM_LC_QUAL_TAB8__A 0x145001F
-#define QAM_LC_QUAL_TAB9__A 0x1450020
-#define QAM_LC_QUAL_TAB10__A 0x1450021
-#define QAM_LC_QUAL_TAB12__A 0x1450022
-#define QAM_LC_QUAL_TAB15__A 0x1450023
-#define QAM_LC_QUAL_TAB16__A 0x1450024
-#define QAM_LC_QUAL_TAB20__A 0x1450025
-#define QAM_LC_QUAL_TAB25__A 0x1450026
-#define QAM_LC_LPF_FACTORP__A 0x1450028
-#define QAM_LC_LPF_FACTORI__A 0x1450029
-#define QAM_LC_RATE_LIMIT__A 0x145002A
-#define QAM_LC_SYMBOL_FREQ__A 0x145002B
-#define QAM_SY_TIMEOUT__A 0x1470011
-#define QAM_SY_TIMEOUT__PRE 0x3A98
-#define QAM_SY_SYNC_LWM__A 0x1470012
-#define QAM_SY_SYNC_AWM__A 0x1470013
-#define QAM_SY_SYNC_HWM__A 0x1470014
-#define QAM_SY_SP_INV__A 0x1470017
-#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0
-#define SCU_COMM_EXEC__A 0x800000
-#define SCU_COMM_EXEC_STOP 0x0
-#define SCU_COMM_EXEC_ACTIVE 0x1
-#define SCU_COMM_EXEC_HOLD 0x2
-#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF
-#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4
-#define SCU_RAM_GPIO__A 0x831EC7
-#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
-#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8
-#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB
-#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05
-#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15
-#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17
-#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18
-#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19
-#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A
-#define SCU_RAM_AGC_RF_MAX__A 0x831F1B
-#define SCU_RAM_AGC_CONFIG__A 0x831F24
-#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1
-#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2
-#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100
-#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200
-#define SCU_RAM_AGC_KI__A 0x831F25
-#define SCU_RAM_AGC_KI_RF__B 4
-#define SCU_RAM_AGC_KI_RF__M 0xF0
-#define SCU_RAM_AGC_KI_IF__B 8
-#define SCU_RAM_AGC_KI_IF__M 0xF00
-#define SCU_RAM_AGC_KI_RED__A 0x831F26
-#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2
-#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC
-#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4
-#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30
-#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27
-#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28
-#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29
-#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A
-#define SCU_RAM_AGC_KI_MIN__A 0x831F2B
-#define SCU_RAM_AGC_KI_MAX__A 0x831F2C
-#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D
-#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E
-#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F
-#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30
-#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31
-#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32
-#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33
-#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34
-#define SCU_RAM_AGC_SNS_SUM__A 0x831F35
-#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36
-#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37
-#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38
-#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39
-#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A
-#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B
-#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D
-#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E
-#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F
-#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40
-#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41
-#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42
-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43
-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44
-#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45
-#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46
-#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47
-#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
-#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
-#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
-#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
-#define SCU_RAM_QAM_FSM_PTH__A 0x831F90
-#define SCU_RAM_QAM_FSM_MTH__A 0x831F91
-#define SCU_RAM_QAM_FSM_CTH__A 0x831F92
-#define SCU_RAM_QAM_FSM_QTH__A 0x831F93
-#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
-#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
-#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
-#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
-#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
-#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
-#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
-#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
-#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
-#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
-#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
-#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
-#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
-#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
-#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
-#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
-#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
-#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
-#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
-#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
-#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
-#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
-#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
-#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
-#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
-#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
-#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
-#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
-#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
-#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
-#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000
-#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000
-#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000
-#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA
-#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB
-#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC
-#define SCU_RAM_PARAM_15__A 0x831FED
-#define SCU_RAM_PARAM_0__A 0x831FFC
-#define SCU_RAM_COMMAND__A 0x831FFD
-#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1
-#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2
-#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3
-#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4
-#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5
-#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9
-#define SCU_RAM_COMMAND_STANDARD_QAM 0x200
-#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400
-#define SIO_TOP_COMM_KEY__A 0x41000F
-#define SIO_TOP_COMM_KEY_KEY 0xFABA
-#define SIO_TOP_JTAGID_LO__A 0x410012
-#define SIO_HI_RA_RAM_RES__A 0x420031
-#define SIO_HI_RA_RAM_CMD__A 0x420032
-#define SIO_HI_RA_RAM_CMD_RESET 0x2
-#define SIO_HI_RA_RAM_CMD_CONFIG 0x3
-#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7
-#define SIO_HI_RA_RAM_PAR_1__A 0x420033
-#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
-#define SIO_HI_RA_RAM_PAR_2__A 0x420034
-#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
-#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
-#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
-#define SIO_HI_RA_RAM_PAR_3__A 0x420035
-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
-#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
-#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
-#define SIO_HI_RA_RAM_PAR_4__A 0x420036
-#define SIO_HI_RA_RAM_PAR_5__A 0x420037
-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
-#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
-#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
-#define SIO_HI_RA_RAM_PAR_6__A 0x420038
-#define SIO_CC_PLL_LOCK__A 0x450012
-#define SIO_CC_PWD_MODE__A 0x450015
-#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0
-#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1
-#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2
-#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3
-#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4
-#define SIO_CC_SOFT_RST__A 0x450016
-#define SIO_CC_SOFT_RST_OFDM__M 0x1
-#define SIO_CC_SOFT_RST_SYS__M 0x2
-#define SIO_CC_SOFT_RST_OSC__M 0x4
-#define SIO_CC_UPDATE__A 0x450017
-#define SIO_CC_UPDATE_KEY 0xFABA
-#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010
-#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0
-#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1
-#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012
-#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0
-#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1
-#define SIO_BL_COMM_EXEC__A 0x480000
-#define SIO_BL_COMM_EXEC_ACTIVE 0x1
-#define SIO_BL_STATUS__A 0x480010
-#define SIO_BL_MODE__A 0x480011
-#define SIO_BL_MODE_DIRECT 0x0
-#define SIO_BL_MODE_CHAIN 0x1
-#define SIO_BL_ENABLE__A 0x480012
-#define SIO_BL_ENABLE_ON 0x1
-#define SIO_BL_TGT_HDR__A 0x480014
-#define SIO_BL_TGT_ADDR__A 0x480015
-#define SIO_BL_SRC_ADDR__A 0x480016
-#define SIO_BL_SRC_LEN__A 0x480017
-#define SIO_BL_CHAIN_ADDR__A 0x480018
-#define SIO_BL_CHAIN_LEN__A 0x480019
-#define SIO_PDR_MON_CFG__A 0x7F0010
-#define SIO_PDR_UIO_IN_HI__A 0x7F0015
-#define SIO_PDR_UIO_OUT_LO__A 0x7F0016
-#define SIO_PDR_OHW_CFG__A 0x7F001F
-#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3
-#define SIO_PDR_GPIO_CFG__A 0x7F0021
-#define SIO_PDR_MSTRT_CFG__A 0x7F0025
-#define SIO_PDR_MERR_CFG__A 0x7F0026
-#define SIO_PDR_MCLK_CFG__A 0x7F0028
-#define SIO_PDR_MCLK_CFG_DRIVE__B 3
-#define SIO_PDR_MVAL_CFG__A 0x7F0029
-#define SIO_PDR_MD0_CFG__A 0x7F002A
-#define SIO_PDR_MD0_CFG_DRIVE__B 3
-#define SIO_PDR_MD1_CFG__A 0x7F002B
-#define SIO_PDR_MD2_CFG__A 0x7F002C
-#define SIO_PDR_MD3_CFG__A 0x7F002D
-#define SIO_PDR_MD4_CFG__A 0x7F002F
-#define SIO_PDR_MD5_CFG__A 0x7F0030
-#define SIO_PDR_MD6_CFG__A 0x7F0031
-#define SIO_PDR_MD7_CFG__A 0x7F0032
-#define SIO_PDR_SMA_RX_CFG__A 0x7F0037
-#define SIO_PDR_SMA_TX_CFG__A 0x7F0038
diff --git a/drivers/media/dvb/frontends/ds3000.c b/drivers/media/dvb/frontends/ds3000.c
deleted file mode 100644
index 4c8ac2657c4..00000000000
--- a/drivers/media/dvb/frontends/ds3000.c
+++ /dev/null
@@ -1,1312 +0,0 @@
-/*
- Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver
- Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
-
- Copyright (C) 2009 TurboSight.com
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/firmware.h>
-
-#include "dvb_frontend.h"
-#include "ds3000.h"
-
-static int debug;
-
-#define dprintk(args...) \
- do { \
- if (debug) \
- printk(args); \
- } while (0)
-
-/* as of March 2009 current DS3000 firmware version is 1.78 */
-/* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
-#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
-
-#define DS3000_SAMPLE_RATE 96000 /* in kHz */
-#define DS3000_XTAL_FREQ 27000 /* in kHz */
-
-/* Register values to initialise the demod in DVB-S mode */
-static u8 ds3000_dvbs_init_tab[] = {
- 0x23, 0x05,
- 0x08, 0x03,
- 0x0c, 0x00,
- 0x21, 0x54,
- 0x25, 0x82,
- 0x27, 0x31,
- 0x30, 0x08,
- 0x31, 0x40,
- 0x32, 0x32,
- 0x33, 0x35,
- 0x35, 0xff,
- 0x3a, 0x00,
- 0x37, 0x10,
- 0x38, 0x10,
- 0x39, 0x02,
- 0x42, 0x60,
- 0x4a, 0x40,
- 0x4b, 0x04,
- 0x4d, 0x91,
- 0x5d, 0xc8,
- 0x50, 0x77,
- 0x51, 0x77,
- 0x52, 0x36,
- 0x53, 0x36,
- 0x56, 0x01,
- 0x63, 0x43,
- 0x64, 0x30,
- 0x65, 0x40,
- 0x68, 0x26,
- 0x69, 0x4c,
- 0x70, 0x20,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0x40,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0x60,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0x80,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0xa0,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0x1f,
- 0x76, 0x00,
- 0x77, 0xd1,
- 0x78, 0x0c,
- 0x79, 0x80,
- 0x7f, 0x04,
- 0x7c, 0x00,
- 0x80, 0x86,
- 0x81, 0xa6,
- 0x85, 0x04,
- 0xcd, 0xf4,
- 0x90, 0x33,
- 0xa0, 0x44,
- 0xc0, 0x18,
- 0xc3, 0x10,
- 0xc4, 0x08,
- 0xc5, 0x80,
- 0xc6, 0x80,
- 0xc7, 0x0a,
- 0xc8, 0x1a,
- 0xc9, 0x80,
- 0xfe, 0x92,
- 0xe0, 0xf8,
- 0xe6, 0x8b,
- 0xd0, 0x40,
- 0xf8, 0x20,
- 0xfa, 0x0f,
- 0xfd, 0x20,
- 0xad, 0x20,
- 0xae, 0x07,
- 0xb8, 0x00,
-};
-
-/* Register values to initialise the demod in DVB-S2 mode */
-static u8 ds3000_dvbs2_init_tab[] = {
- 0x23, 0x0f,
- 0x08, 0x07,
- 0x0c, 0x00,
- 0x21, 0x54,
- 0x25, 0x82,
- 0x27, 0x31,
- 0x30, 0x08,
- 0x31, 0x32,
- 0x32, 0x32,
- 0x33, 0x35,
- 0x35, 0xff,
- 0x3a, 0x00,
- 0x37, 0x10,
- 0x38, 0x10,
- 0x39, 0x02,
- 0x42, 0x60,
- 0x4a, 0x80,
- 0x4b, 0x04,
- 0x4d, 0x81,
- 0x5d, 0x88,
- 0x50, 0x36,
- 0x51, 0x36,
- 0x52, 0x36,
- 0x53, 0x36,
- 0x63, 0x60,
- 0x64, 0x10,
- 0x65, 0x10,
- 0x68, 0x04,
- 0x69, 0x29,
- 0x70, 0x20,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0x40,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0x60,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0x80,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0xa0,
- 0x71, 0x70,
- 0x72, 0x04,
- 0x73, 0x00,
- 0x70, 0x1f,
- 0xa0, 0x44,
- 0xc0, 0x08,
- 0xc1, 0x10,
- 0xc2, 0x08,
- 0xc3, 0x10,
- 0xc4, 0x08,
- 0xc5, 0xf0,
- 0xc6, 0xf0,
- 0xc7, 0x0a,
- 0xc8, 0x1a,
- 0xc9, 0x80,
- 0xca, 0x23,
- 0xcb, 0x24,
- 0xce, 0x74,
- 0x90, 0x03,
- 0x76, 0x80,
- 0x77, 0x42,
- 0x78, 0x0a,
- 0x79, 0x80,
- 0xad, 0x40,
- 0xae, 0x07,
- 0x7f, 0xd4,
- 0x7c, 0x00,
- 0x80, 0xa8,
- 0x81, 0xda,
- 0x7c, 0x01,
- 0x80, 0xda,
- 0x81, 0xec,
- 0x7c, 0x02,
- 0x80, 0xca,
- 0x81, 0xeb,
- 0x7c, 0x03,
- 0x80, 0xba,
- 0x81, 0xdb,
- 0x85, 0x08,
- 0x86, 0x00,
- 0x87, 0x02,
- 0x89, 0x80,
- 0x8b, 0x44,
- 0x8c, 0xaa,
- 0x8a, 0x10,
- 0xba, 0x00,
- 0xf5, 0x04,
- 0xfe, 0x44,
- 0xd2, 0x32,
- 0xb8, 0x00,
-};
-
-struct ds3000_state {
- struct i2c_adapter *i2c;
- const struct ds3000_config *config;
- struct dvb_frontend frontend;
- u8 skip_fw_load;
- /* previous uncorrected block counter for DVB-S2 */
- u16 prevUCBS2;
-};
-
-static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
-{
- u8 buf[] = { reg, data };
- struct i2c_msg msg = { .addr = state->config->demod_address,
- .flags = 0, .buf = buf, .len = 2 };
- int err;
-
- dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
-
- err = i2c_transfer(state->i2c, &msg, 1);
- if (err != 1) {
- printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
- " value == 0x%02x)\n", __func__, err, reg, data);
- return -EREMOTEIO;
- }
-
- return 0;
-}
-
-static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
-{
- u8 buf[] = { reg, data };
- struct i2c_msg msg = { .addr = 0x60,
- .flags = 0, .buf = buf, .len = 2 };
- int err;
-
- dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
-
- ds3000_writereg(state, 0x03, 0x11);
- err = i2c_transfer(state->i2c, &msg, 1);
- if (err != 1) {
- printk("%s: writereg error(err == %i, reg == 0x%02x,"
- " value == 0x%02x)\n", __func__, err, reg, data);
- return -EREMOTEIO;
- }
-
- return 0;
-}
-
-/* I2C write for 8k firmware load */
-static int ds3000_writeFW(struct ds3000_state *state, int reg,
- const u8 *data, u16 len)
-{
- int i, ret = -EREMOTEIO;
- struct i2c_msg msg;
- u8 *buf;
-
- buf = kmalloc(33, GFP_KERNEL);
- if (buf == NULL) {
- printk(KERN_ERR "Unable to kmalloc\n");
- ret = -ENOMEM;
- goto error;
- }
-
- *(buf) = reg;
-
- msg.addr = state->config->demod_address;
- msg.flags = 0;
- msg.buf = buf;
- msg.len = 33;
-
- for (i = 0; i < len; i += 32) {
- memcpy(buf + 1, data + i, 32);
-
- dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
-
- ret = i2c_transfer(state->i2c, &msg, 1);
- if (ret != 1) {
- printk(KERN_ERR "%s: write error(err == %i, "
- "reg == 0x%02x\n", __func__, ret, reg);
- ret = -EREMOTEIO;
- }
- }
-
-error:
- kfree(buf);
-
- return ret;
-}
-
-static int ds3000_readreg(struct ds3000_state *state, u8 reg)
-{
- int ret;
- u8 b0[] = { reg };
- u8 b1[] = { 0 };
- struct i2c_msg msg[] = {
- {
- .addr = state->config->demod_address,
- .flags = 0,
- .buf = b0,
- .len = 1
- }, {
- .addr = state->config->demod_address,
- .flags = I2C_M_RD,
- .buf = b1,
- .len = 1
- }
- };
-
- ret = i2c_transfer(state->i2c, msg, 2);
-
- if (ret != 2) {
- printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
- return ret;
- }
-
- dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
-
- return b1[0];
-}
-
-static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
-{
- int ret;
- u8 b0[] = { reg };
- u8 b1[] = { 0 };
- struct i2c_msg msg[] = {
- {
- .addr = 0x60,
- .flags = 0,
- .buf = b0,
- .len = 1
- }, {
- .addr = 0x60,
- .flags = I2C_M_RD,
- .buf = b1,
- .len = 1
- }
- };
-
- ds3000_writereg(state, 0x03, 0x12);
- ret = i2c_transfer(state->i2c, msg, 2);
-
- if (ret != 2) {
- printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
- return ret;
- }
-
- dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
-
- return b1[0];
-}
-
-static int ds3000_load_firmware(struct dvb_frontend *fe,
- const struct firmware *fw);
-
-static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- const struct firmware *fw;
- int ret = 0;
-
- dprintk("%s()\n", __func__);
-
- if (ds3000_readreg(state, 0xb2) <= 0)
- return ret;
-
- if (state->skip_fw_load)
- return 0;
- /* Load firmware */
- /* request the firmware, this will block until someone uploads it */
- printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
- DS3000_DEFAULT_FIRMWARE);
- ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
- state->i2c->dev.parent);
- printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
- if (ret) {
- printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
- "found?)\n", __func__);
- return ret;
- }
-
- /* Make sure we don't recurse back through here during loading */
- state->skip_fw_load = 1;
-
- ret = ds3000_load_firmware(fe, fw);
- if (ret)
- printk("%s: Writing firmware to device failed\n", __func__);
-
- release_firmware(fw);
-
- dprintk("%s: Firmware upload %s\n", __func__,
- ret == 0 ? "complete" : "failed");
-
- /* Ensure firmware is always loaded if required */
- state->skip_fw_load = 0;
-
- return ret;
-}
-
-static int ds3000_load_firmware(struct dvb_frontend *fe,
- const struct firmware *fw)
-{
- struct ds3000_state *state = fe->demodulator_priv;
-
- dprintk("%s\n", __func__);
- dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
- fw->size,
- fw->data[0],
- fw->data[1],
- fw->data[fw->size - 2],
- fw->data[fw->size - 1]);
-
- /* Begin the firmware load process */
- ds3000_writereg(state, 0xb2, 0x01);
- /* write the entire firmware */
- ds3000_writeFW(state, 0xb0, fw->data, fw->size);
- ds3000_writereg(state, 0xb2, 0x00);
-
- return 0;
-}
-
-static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- u8 data;
-
- dprintk("%s(%d)\n", __func__, voltage);
-
- data = ds3000_readreg(state, 0xa2);
- data |= 0x03; /* bit0 V/H, bit1 off/on */
-
- switch (voltage) {
- case SEC_VOLTAGE_18:
- data &= ~0x03;
- break;
- case SEC_VOLTAGE_13:
- data &= ~0x03;
- data |= 0x01;
- break;
- case SEC_VOLTAGE_OFF:
- break;
- }
-
- ds3000_writereg(state, 0xa2, data);
-
- return 0;
-}
-
-static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int lock;
-
- *status = 0;
-
- switch (c->delivery_system) {
- case SYS_DVBS:
- lock = ds3000_readreg(state, 0xd1);
- if ((lock & 0x07) == 0x07)
- *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC |
- FE_HAS_LOCK;
-
- break;
- case SYS_DVBS2:
- lock = ds3000_readreg(state, 0x0d);
- if ((lock & 0x8f) == 0x8f)
- *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC |
- FE_HAS_LOCK;
-
- break;
- default:
- return 1;
- }
-
- dprintk("%s: status = 0x%02x\n", __func__, lock);
-
- return 0;
-}
-
-/* read DS3000 BER value */
-static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- u8 data;
- u32 ber_reading, lpdc_frames;
-
- dprintk("%s()\n", __func__);
-
- switch (c->delivery_system) {
- case SYS_DVBS:
- /* set the number of bytes checked during
- BER estimation */
- ds3000_writereg(state, 0xf9, 0x04);
- /* read BER estimation status */
- data = ds3000_readreg(state, 0xf8);
- /* check if BER estimation is ready */
- if ((data & 0x10) == 0) {
- /* this is the number of error bits,
- to calculate the bit error rate
- divide to 8388608 */
- *ber = (ds3000_readreg(state, 0xf7) << 8) |
- ds3000_readreg(state, 0xf6);
- /* start counting error bits */
- /* need to be set twice
- otherwise it fails sometimes */
- data |= 0x10;
- ds3000_writereg(state, 0xf8, data);
- ds3000_writereg(state, 0xf8, data);
- } else
- /* used to indicate that BER estimation
- is not ready, i.e. BER is unknown */
- *ber = 0xffffffff;
- break;
- case SYS_DVBS2:
- /* read the number of LPDC decoded frames */
- lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
- (ds3000_readreg(state, 0xd6) << 8) |
- ds3000_readreg(state, 0xd5);
- /* read the number of packets with bad CRC */
- ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
- ds3000_readreg(state, 0xf7);
- if (lpdc_frames > 750) {
- /* clear LPDC frame counters */
- ds3000_writereg(state, 0xd1, 0x01);
- /* clear bad packets counter */
- ds3000_writereg(state, 0xf9, 0x01);
- /* enable bad packets counter */
- ds3000_writereg(state, 0xf9, 0x00);
- /* enable LPDC frame counters */
- ds3000_writereg(state, 0xd1, 0x00);
- *ber = ber_reading;
- } else
- /* used to indicate that BER estimation is not ready,
- i.e. BER is unknown */
- *ber = 0xffffffff;
- break;
- default:
- return 1;
- }
-
- return 0;
-}
-
-/* read TS2020 signal strength */
-static int ds3000_read_signal_strength(struct dvb_frontend *fe,
- u16 *signal_strength)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- u16 sig_reading, sig_strength;
- u8 rfgain, bbgain;
-
- dprintk("%s()\n", __func__);
-
- rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f;
- bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f;
-
- if (rfgain > 15)
- rfgain = 15;
- if (bbgain > 13)
- bbgain = 13;
-
- sig_reading = rfgain * 2 + bbgain * 3;
-
- sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
-
- /* cook the value to be suitable for szap-s2 human readable output */
- *signal_strength = sig_strength * 1000;
-
- dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
- sig_reading, *signal_strength);
-
- return 0;
-}
-
-/* calculate DS3000 snr value in dB */
-static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- u8 snr_reading, snr_value;
- u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
- static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
- 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
- 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
- 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
- };
- static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
- 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
- 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
- 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
- 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
- 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
- 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
- 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
- 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
- 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
- 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
- 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
- 0x49e9, 0x4a20, 0x4a57
- };
-
- dprintk("%s()\n", __func__);
-
- switch (c->delivery_system) {
- case SYS_DVBS:
- snr_reading = ds3000_readreg(state, 0xff);
- snr_reading /= 8;
- if (snr_reading == 0)
- *snr = 0x0000;
- else {
- if (snr_reading > 20)
- snr_reading = 20;
- snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
- /* cook the value to be suitable for szap-s2
- human readable output */
- *snr = snr_value * 8 * 655;
- }
- dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
- snr_reading, *snr);
- break;
- case SYS_DVBS2:
- dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
- (ds3000_readreg(state, 0x8d) << 4);
- dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
- tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
- if (tmp == 0) {
- *snr = 0x0000;
- return 0;
- }
- if (dvbs2_noise_reading == 0) {
- snr_value = 0x0013;
- /* cook the value to be suitable for szap-s2
- human readable output */
- *snr = 0xffff;
- return 0;
- }
- if (tmp > dvbs2_noise_reading) {
- snr_reading = tmp / dvbs2_noise_reading;
- if (snr_reading > 80)
- snr_reading = 80;
- snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
- /* cook the value to be suitable for szap-s2
- human readable output */
- *snr = snr_value * 5 * 655;
- } else {
- snr_reading = dvbs2_noise_reading / tmp;
- if (snr_reading > 80)
- snr_reading = 80;
- *snr = -(dvbs2_snr_tab[snr_reading] / 1000);
- }
- dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
- snr_reading, *snr);
- break;
- default:
- return 1;
- }
-
- return 0;
-}
-
-/* read DS3000 uncorrected blocks */
-static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- u8 data;
- u16 _ucblocks;
-
- dprintk("%s()\n", __func__);
-
- switch (c->delivery_system) {
- case SYS_DVBS:
- *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
- ds3000_readreg(state, 0xf4);
- data = ds3000_readreg(state, 0xf8);
- /* clear packet counters */
- data &= ~0x20;
- ds3000_writereg(state, 0xf8, data);
- /* enable packet counters */
- data |= 0x20;
- ds3000_writereg(state, 0xf8, data);
- break;
- case SYS_DVBS2:
- _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
- ds3000_readreg(state, 0xe1);
- if (_ucblocks > state->prevUCBS2)
- *ucblocks = _ucblocks - state->prevUCBS2;
- else
- *ucblocks = state->prevUCBS2 - _ucblocks;
- state->prevUCBS2 = _ucblocks;
- break;
- default:
- return 1;
- }
-
- return 0;
-}
-
-static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- u8 data;
-
- dprintk("%s(%d)\n", __func__, tone);
- if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
- printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
- return -EINVAL;
- }
-
- data = ds3000_readreg(state, 0xa2);
- data &= ~0xc0;
- ds3000_writereg(state, 0xa2, data);
-
- switch (tone) {
- case SEC_TONE_ON:
- dprintk("%s: setting tone on\n", __func__);
- data = ds3000_readreg(state, 0xa1);
- data &= ~0x43;
- data |= 0x04;
- ds3000_writereg(state, 0xa1, data);
- break;
- case SEC_TONE_OFF:
- dprintk("%s: setting tone off\n", __func__);
- data = ds3000_readreg(state, 0xa2);
- data |= 0x80;
- ds3000_writereg(state, 0xa2, data);
- break;
- }
-
- return 0;
-}
-
-static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
- struct dvb_diseqc_master_cmd *d)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- int i;
- u8 data;
-
- /* Dump DiSEqC message */
- dprintk("%s(", __func__);
- for (i = 0 ; i < d->msg_len;) {
- dprintk("0x%02x", d->msg[i]);
- if (++i < d->msg_len)
- dprintk(", ");
- }
-
- /* enable DiSEqC message send pin */
- data = ds3000_readreg(state, 0xa2);
- data &= ~0xc0;
- ds3000_writereg(state, 0xa2, data);
-
- /* DiSEqC message */
- for (i = 0; i < d->msg_len; i++)
- ds3000_writereg(state, 0xa3 + i, d->msg[i]);
-
- data = ds3000_readreg(state, 0xa1);
- /* clear DiSEqC message length and status,
- enable DiSEqC message send */
- data &= ~0xf8;
- /* set DiSEqC mode, modulation active during 33 pulses,
- set DiSEqC message length */
- data |= ((d->msg_len - 1) << 3) | 0x07;
- ds3000_writereg(state, 0xa1, data);
-
- /* wait up to 150ms for DiSEqC transmission to complete */
- for (i = 0; i < 15; i++) {
- data = ds3000_readreg(state, 0xa1);
- if ((data & 0x40) == 0)
- break;
- msleep(10);
- }
-
- /* DiSEqC timeout after 150ms */
- if (i == 15) {
- data = ds3000_readreg(state, 0xa1);
- data &= ~0x80;
- data |= 0x40;
- ds3000_writereg(state, 0xa1, data);
-
- data = ds3000_readreg(state, 0xa2);
- data &= ~0xc0;
- data |= 0x80;
- ds3000_writereg(state, 0xa2, data);
-
- return 1;
- }
-
- data = ds3000_readreg(state, 0xa2);
- data &= ~0xc0;
- data |= 0x80;
- ds3000_writereg(state, 0xa2, data);
-
- return 0;
-}
-
-/* Send DiSEqC burst */
-static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
- fe_sec_mini_cmd_t burst)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- int i;
- u8 data;
-
- dprintk("%s()\n", __func__);
-
- data = ds3000_readreg(state, 0xa2);
- data &= ~0xc0;
- ds3000_writereg(state, 0xa2, data);
-
- /* DiSEqC burst */
- if (burst == SEC_MINI_A)
- /* Unmodulated tone burst */
- ds3000_writereg(state, 0xa1, 0x02);
- else if (burst == SEC_MINI_B)
- /* Modulated tone burst */
- ds3000_writereg(state, 0xa1, 0x01);
- else
- return -EINVAL;
-
- msleep(13);
- for (i = 0; i < 5; i++) {
- data = ds3000_readreg(state, 0xa1);
- if ((data & 0x40) == 0)
- break;
- msleep(1);
- }
-
- if (i == 5) {
- data = ds3000_readreg(state, 0xa1);
- data &= ~0x80;
- data |= 0x40;
- ds3000_writereg(state, 0xa1, data);
-
- data = ds3000_readreg(state, 0xa2);
- data &= ~0xc0;
- data |= 0x80;
- ds3000_writereg(state, 0xa2, data);
-
- return 1;
- }
-
- data = ds3000_readreg(state, 0xa2);
- data &= ~0xc0;
- data |= 0x80;
- ds3000_writereg(state, 0xa2, data);
-
- return 0;
-}
-
-static void ds3000_release(struct dvb_frontend *fe)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- dprintk("%s\n", __func__);
- kfree(state);
-}
-
-static struct dvb_frontend_ops ds3000_ops;
-
-struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
- struct i2c_adapter *i2c)
-{
- struct ds3000_state *state = NULL;
- int ret;
-
- dprintk("%s\n", __func__);
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL);
- if (state == NULL) {
- printk(KERN_ERR "Unable to kmalloc\n");
- goto error2;
- }
-
- state->config = config;
- state->i2c = i2c;
- state->prevUCBS2 = 0;
-
- /* check if the demod is present */
- ret = ds3000_readreg(state, 0x00) & 0xfe;
- if (ret != 0xe0) {
- printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
- goto error3;
- }
-
- printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
- ds3000_readreg(state, 0x02),
- ds3000_readreg(state, 0x01));
-
- memcpy(&state->frontend.ops, &ds3000_ops,
- sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
- return &state->frontend;
-
-error3:
- kfree(state);
-error2:
- return NULL;
-}
-EXPORT_SYMBOL(ds3000_attach);
-
-static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
- s32 carrier_offset_khz)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- s32 tmp;
-
- tmp = carrier_offset_khz;
- tmp *= 65536;
- tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
-
- if (tmp < 0)
- tmp += 65536;
-
- ds3000_writereg(state, 0x5f, tmp >> 8);
- ds3000_writereg(state, 0x5e, tmp & 0xff);
-
- return 0;
-}
-
-static int ds3000_set_frontend(struct dvb_frontend *fe)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
-
- int i;
- fe_status_t status;
- u8 mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf, div4;
- s32 offset_khz;
- u16 value, ndiv;
- u32 f3db;
-
- dprintk("%s() ", __func__);
-
- if (state->config->set_ts_params)
- state->config->set_ts_params(fe, 0);
- /* Tune */
- /* unknown */
- ds3000_tuner_writereg(state, 0x07, 0x02);
- ds3000_tuner_writereg(state, 0x10, 0x00);
- ds3000_tuner_writereg(state, 0x60, 0x79);
- ds3000_tuner_writereg(state, 0x08, 0x01);
- ds3000_tuner_writereg(state, 0x00, 0x01);
- div4 = 0;
-
- /* calculate and set freq divider */
- if (c->frequency < 1146000) {
- ds3000_tuner_writereg(state, 0x10, 0x11);
- div4 = 1;
- ndiv = ((c->frequency * (6 + 8) * 4) +
- (DS3000_XTAL_FREQ / 2)) /
- DS3000_XTAL_FREQ - 1024;
- } else {
- ds3000_tuner_writereg(state, 0x10, 0x01);
- ndiv = ((c->frequency * (6 + 8) * 2) +
- (DS3000_XTAL_FREQ / 2)) /
- DS3000_XTAL_FREQ - 1024;
- }
-
- ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
- ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
-
- /* set pll */
- ds3000_tuner_writereg(state, 0x03, 0x06);
- ds3000_tuner_writereg(state, 0x51, 0x0f);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x10);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(5);
-
- /* unknown */
- ds3000_tuner_writereg(state, 0x51, 0x17);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x08);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(5);
-
- value = ds3000_tuner_readreg(state, 0x3d);
- value &= 0x0f;
- if ((value > 4) && (value < 15)) {
- value -= 3;
- if (value < 4)
- value = 4;
- value = ((value << 3) | 0x01) & 0x79;
- }
-
- ds3000_tuner_writereg(state, 0x60, value);
- ds3000_tuner_writereg(state, 0x51, 0x17);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x08);
- ds3000_tuner_writereg(state, 0x50, 0x00);
-
- /* set low-pass filter period */
- ds3000_tuner_writereg(state, 0x04, 0x2e);
- ds3000_tuner_writereg(state, 0x51, 0x1b);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x04);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(5);
-
- f3db = ((c->symbol_rate / 1000) << 2) / 5 + 2000;
- if ((c->symbol_rate / 1000) < 5000)
- f3db += 3000;
- if (f3db < 7000)
- f3db = 7000;
- if (f3db > 40000)
- f3db = 40000;
-
- /* set low-pass filter baseband */
- value = ds3000_tuner_readreg(state, 0x26);
- mlpf = 0x2e * 207 / ((value << 1) + 151);
- mlpf_max = mlpf * 135 / 100;
- mlpf_min = mlpf * 78 / 100;
- if (mlpf_max > 63)
- mlpf_max = 63;
-
- /* rounded to the closest integer */
- nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
- / (2766 * DS3000_XTAL_FREQ);
- if (nlpf > 23)
- nlpf = 23;
- if (nlpf < 1)
- nlpf = 1;
-
- /* rounded to the closest integer */
- mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
- (1000 * f3db / 2)) / (1000 * f3db);
-
- if (mlpf_new < mlpf_min) {
- nlpf++;
- mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
- (1000 * f3db / 2)) / (1000 * f3db);
- }
-
- if (mlpf_new > mlpf_max)
- mlpf_new = mlpf_max;
-
- ds3000_tuner_writereg(state, 0x04, mlpf_new);
- ds3000_tuner_writereg(state, 0x06, nlpf);
- ds3000_tuner_writereg(state, 0x51, 0x1b);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x04);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(5);
-
- /* unknown */
- ds3000_tuner_writereg(state, 0x51, 0x1e);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x01);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(60);
-
- offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ
- / (6 + 8) / (div4 + 1) / 2 - c->frequency;
-
- /* ds3000 global reset */
- ds3000_writereg(state, 0x07, 0x80);
- ds3000_writereg(state, 0x07, 0x00);
- /* ds3000 build-in uC reset */
- ds3000_writereg(state, 0xb2, 0x01);
- /* ds3000 software reset */
- ds3000_writereg(state, 0x00, 0x01);
-
- switch (c->delivery_system) {
- case SYS_DVBS:
- /* initialise the demod in DVB-S mode */
- for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
- ds3000_writereg(state,
- ds3000_dvbs_init_tab[i],
- ds3000_dvbs_init_tab[i + 1]);
- value = ds3000_readreg(state, 0xfe);
- value &= 0xc0;
- value |= 0x1b;
- ds3000_writereg(state, 0xfe, value);
- break;
- case SYS_DVBS2:
- /* initialise the demod in DVB-S2 mode */
- for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
- ds3000_writereg(state,
- ds3000_dvbs2_init_tab[i],
- ds3000_dvbs2_init_tab[i + 1]);
- if (c->symbol_rate >= 30000000)
- ds3000_writereg(state, 0xfe, 0x54);
- else
- ds3000_writereg(state, 0xfe, 0x98);
- break;
- default:
- return 1;
- }
-
- /* enable 27MHz clock output */
- ds3000_writereg(state, 0x29, 0x80);
- /* enable ac coupling */
- ds3000_writereg(state, 0x25, 0x8a);
-
- /* enhance symbol rate performance */
- if ((c->symbol_rate / 1000) <= 5000) {
- value = 29777 / (c->symbol_rate / 1000) + 1;
- if (value % 2 != 0)
- value++;
- ds3000_writereg(state, 0xc3, 0x0d);
- ds3000_writereg(state, 0xc8, value);
- ds3000_writereg(state, 0xc4, 0x10);
- ds3000_writereg(state, 0xc7, 0x0e);
- } else if ((c->symbol_rate / 1000) <= 10000) {
- value = 92166 / (c->symbol_rate / 1000) + 1;
- if (value % 2 != 0)
- value++;
- ds3000_writereg(state, 0xc3, 0x07);
- ds3000_writereg(state, 0xc8, value);
- ds3000_writereg(state, 0xc4, 0x09);
- ds3000_writereg(state, 0xc7, 0x12);
- } else if ((c->symbol_rate / 1000) <= 20000) {
- value = 64516 / (c->symbol_rate / 1000) + 1;
- ds3000_writereg(state, 0xc3, value);
- ds3000_writereg(state, 0xc8, 0x0e);
- ds3000_writereg(state, 0xc4, 0x07);
- ds3000_writereg(state, 0xc7, 0x18);
- } else {
- value = 129032 / (c->symbol_rate / 1000) + 1;
- ds3000_writereg(state, 0xc3, value);
- ds3000_writereg(state, 0xc8, 0x0a);
- ds3000_writereg(state, 0xc4, 0x05);
- ds3000_writereg(state, 0xc7, 0x24);
- }
-
- /* normalized symbol rate rounded to the closest integer */
- value = (((c->symbol_rate / 1000) << 16) +
- (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
- ds3000_writereg(state, 0x61, value & 0x00ff);
- ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
-
- /* co-channel interference cancellation disabled */
- ds3000_writereg(state, 0x56, 0x00);
-
- /* equalizer disabled */
- ds3000_writereg(state, 0x76, 0x00);
-
- /*ds3000_writereg(state, 0x08, 0x03);
- ds3000_writereg(state, 0xfd, 0x22);
- ds3000_writereg(state, 0x08, 0x07);
- ds3000_writereg(state, 0xfd, 0x42);
- ds3000_writereg(state, 0x08, 0x07);*/
-
- if (state->config->ci_mode) {
- switch (c->delivery_system) {
- case SYS_DVBS:
- default:
- ds3000_writereg(state, 0xfd, 0x80);
- break;
- case SYS_DVBS2:
- ds3000_writereg(state, 0xfd, 0x01);
- break;
- }
- }
-
- /* ds3000 out of software reset */
- ds3000_writereg(state, 0x00, 0x00);
- /* start ds3000 build-in uC */
- ds3000_writereg(state, 0xb2, 0x00);
-
- ds3000_set_carrier_offset(fe, offset_khz);
-
- for (i = 0; i < 30 ; i++) {
- ds3000_read_status(fe, &status);
- if (status & FE_HAS_LOCK)
- break;
-
- msleep(10);
- }
-
- return 0;
-}
-
-static int ds3000_tune(struct dvb_frontend *fe,
- bool re_tune,
- unsigned int mode_flags,
- unsigned int *delay,
- fe_status_t *status)
-{
- if (re_tune) {
- int ret = ds3000_set_frontend(fe);
- if (ret)
- return ret;
- }
-
- *delay = HZ / 5;
-
- return ds3000_read_status(fe, status);
-}
-
-static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
-{
- dprintk("%s()\n", __func__);
- return DVBFE_ALGO_HW;
-}
-
-/*
- * Initialise or wake up device
- *
- * Power config will reset and load initial firmware if required
- */
-static int ds3000_initfe(struct dvb_frontend *fe)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- int ret;
-
- dprintk("%s()\n", __func__);
- /* hard reset */
- ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
- msleep(1);
-
- /* TS2020 init */
- ds3000_tuner_writereg(state, 0x42, 0x73);
- ds3000_tuner_writereg(state, 0x05, 0x01);
- ds3000_tuner_writereg(state, 0x62, 0xf5);
- /* Load the firmware if required */
- ret = ds3000_firmware_ondemand(fe);
- if (ret != 0) {
- printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
- return ret;
- }
-
- return 0;
-}
-
-/* Put device to sleep */
-static int ds3000_sleep(struct dvb_frontend *fe)
-{
- dprintk("%s()\n", __func__);
- return 0;
-}
-
-static struct dvb_frontend_ops ds3000_ops = {
- .delsys = { SYS_DVBS, SYS_DVBS2},
- .info = {
- .name = "Montage Technology DS3000/TS2020",
- .frequency_min = 950000,
- .frequency_max = 2150000,
- .frequency_stepsize = 1011, /* kHz for QPSK frontends */
- .frequency_tolerance = 5000,
- .symbol_rate_min = 1000000,
- .symbol_rate_max = 45000000,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
- FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_2G_MODULATION |
- FE_CAN_QPSK | FE_CAN_RECOVER
- },
-
- .release = ds3000_release,
-
- .init = ds3000_initfe,
- .sleep = ds3000_sleep,
- .read_status = ds3000_read_status,
- .read_ber = ds3000_read_ber,
- .read_signal_strength = ds3000_read_signal_strength,
- .read_snr = ds3000_read_snr,
- .read_ucblocks = ds3000_read_ucblocks,
- .set_voltage = ds3000_set_voltage,
- .set_tone = ds3000_set_tone,
- .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
- .diseqc_send_burst = ds3000_diseqc_send_burst,
- .get_frontend_algo = ds3000_get_algo,
-
- .set_frontend = ds3000_set_frontend,
- .tune = ds3000_tune,
-};
-
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
-
-MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
- "DS3000/TS2020 hardware");
-MODULE_AUTHOR("Konstantin Dimitrov");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/ds3000.h b/drivers/media/dvb/frontends/ds3000.h
deleted file mode 100644
index 1b736888ea3..00000000000
--- a/drivers/media/dvb/frontends/ds3000.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- Montage Technology DS3000/TS2020 - DVBS/S2 Satellite demod/tuner driver
- Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
-
- Copyright (C) 2009 TurboSight.com
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-#ifndef DS3000_H
-#define DS3000_H
-
-#include <linux/dvb/frontend.h>
-
-struct ds3000_config {
- /* the demodulator's i2c address */
- u8 demod_address;
- u8 ci_mode;
- /* Set device param to start dma */
- int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
-};
-
-#if defined(CONFIG_DVB_DS3000) || \
- (defined(CONFIG_DVB_DS3000_MODULE) && defined(MODULE))
-extern struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline
-struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
- struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif /* CONFIG_DVB_DS3000 */
-#endif /* DS3000_H */
diff --git a/drivers/media/dvb/frontends/dvb-pll.c b/drivers/media/dvb/frontends/dvb-pll.c
deleted file mode 100644
index 6d8fe884323..00000000000
--- a/drivers/media/dvb/frontends/dvb-pll.c
+++ /dev/null
@@ -1,820 +0,0 @@
-/*
- * descriptions + helper functions for simple dvb plls.
- *
- * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/dvb/frontend.h>
-#include <asm/types.h>
-
-#include "dvb-pll.h"
-
-struct dvb_pll_priv {
- /* pll number */
- int nr;
-
- /* i2c details */
- int pll_i2c_address;
- struct i2c_adapter *i2c;
-
- /* the PLL descriptor */
- struct dvb_pll_desc *pll_desc;
-
- /* cached frequency/bandwidth */
- u32 frequency;
- u32 bandwidth;
-};
-
-#define DVB_PLL_MAX 64
-
-static unsigned int dvb_pll_devcount;
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "enable verbose debug messages");
-
-static unsigned int id[DVB_PLL_MAX] =
- { [ 0 ... (DVB_PLL_MAX-1) ] = DVB_PLL_UNDEFINED };
-module_param_array(id, int, NULL, 0644);
-MODULE_PARM_DESC(id, "force pll id to use (DEBUG ONLY)");
-
-/* ----------------------------------------------------------- */
-
-struct dvb_pll_desc {
- char *name;
- u32 min;
- u32 max;
- u32 iffreq;
- void (*set)(struct dvb_frontend *fe, u8 *buf);
- u8 *initdata;
- u8 *initdata2;
- u8 *sleepdata;
- int count;
- struct {
- u32 limit;
- u32 stepsize;
- u8 config;
- u8 cb;
- } entries[12];
-};
-
-/* ----------------------------------------------------------- */
-/* descriptions */
-
-static struct dvb_pll_desc dvb_pll_thomson_dtt7579 = {
- .name = "Thomson dtt7579",
- .min = 177000000,
- .max = 858000000,
- .iffreq= 36166667,
- .sleepdata = (u8[]){ 2, 0xb4, 0x03 },
- .count = 4,
- .entries = {
- { 443250000, 166667, 0xb4, 0x02 },
- { 542000000, 166667, 0xb4, 0x08 },
- { 771000000, 166667, 0xbc, 0x08 },
- { 999999999, 166667, 0xf4, 0x08 },
- },
-};
-
-static void thomson_dtt759x_bw(struct dvb_frontend *fe, u8 *buf)
-{
- u32 bw = fe->dtv_property_cache.bandwidth_hz;
- if (bw == 7000000)
- buf[3] |= 0x10;
-}
-
-static struct dvb_pll_desc dvb_pll_thomson_dtt759x = {
- .name = "Thomson dtt759x",
- .min = 177000000,
- .max = 896000000,
- .set = thomson_dtt759x_bw,
- .iffreq= 36166667,
- .sleepdata = (u8[]){ 2, 0x84, 0x03 },
- .count = 5,
- .entries = {
- { 264000000, 166667, 0xb4, 0x02 },
- { 470000000, 166667, 0xbc, 0x02 },
- { 735000000, 166667, 0xbc, 0x08 },
- { 835000000, 166667, 0xf4, 0x08 },
- { 999999999, 166667, 0xfc, 0x08 },
- },
-};
-
-static void thomson_dtt7520x_bw(struct dvb_frontend *fe, u8 *buf)
-{
- u32 bw = fe->dtv_property_cache.bandwidth_hz;
- if (bw == 8000000)
- buf[3] ^= 0x10;
-}
-
-static struct dvb_pll_desc dvb_pll_thomson_dtt7520x = {
- .name = "Thomson dtt7520x",
- .min = 185000000,
- .max = 900000000,
- .set = thomson_dtt7520x_bw,
- .iffreq = 36166667,
- .count = 7,
- .entries = {
- { 305000000, 166667, 0xb4, 0x12 },
- { 405000000, 166667, 0xbc, 0x12 },
- { 445000000, 166667, 0xbc, 0x12 },
- { 465000000, 166667, 0xf4, 0x18 },
- { 735000000, 166667, 0xfc, 0x18 },
- { 835000000, 166667, 0xbc, 0x18 },
- { 999999999, 166667, 0xfc, 0x18 },
- },
-};
-
-static struct dvb_pll_desc dvb_pll_lg_z201 = {
- .name = "LG z201",
- .min = 174000000,
- .max = 862000000,
- .iffreq= 36166667,
- .sleepdata = (u8[]){ 2, 0xbc, 0x03 },
- .count = 5,
- .entries = {
- { 157500000, 166667, 0xbc, 0x01 },
- { 443250000, 166667, 0xbc, 0x02 },
- { 542000000, 166667, 0xbc, 0x04 },
- { 830000000, 166667, 0xf4, 0x04 },
- { 999999999, 166667, 0xfc, 0x04 },
- },
-};
-
-static struct dvb_pll_desc dvb_pll_unknown_1 = {
- .name = "unknown 1", /* used by dntv live dvb-t */
- .min = 174000000,
- .max = 862000000,
- .iffreq= 36166667,
- .count = 9,
- .entries = {
- { 150000000, 166667, 0xb4, 0x01 },
- { 173000000, 166667, 0xbc, 0x01 },
- { 250000000, 166667, 0xb4, 0x02 },
- { 400000000, 166667, 0xbc, 0x02 },
- { 420000000, 166667, 0xf4, 0x02 },
- { 470000000, 166667, 0xfc, 0x02 },
- { 600000000, 166667, 0xbc, 0x08 },
- { 730000000, 166667, 0xf4, 0x08 },
- { 999999999, 166667, 0xfc, 0x08 },
- },
-};
-
-/* Infineon TUA6010XS
- * used in Thomson Cable Tuner
- */
-static struct dvb_pll_desc dvb_pll_tua6010xs = {
- .name = "Infineon TUA6010XS",
- .min = 44250000,
- .max = 858000000,
- .iffreq= 36125000,
- .count = 3,
- .entries = {
- { 115750000, 62500, 0x8e, 0x03 },
- { 403250000, 62500, 0x8e, 0x06 },
- { 999999999, 62500, 0x8e, 0x85 },
- },
-};
-
-/* Panasonic env57h1xd5 (some Philips PLL ?) */
-static struct dvb_pll_desc dvb_pll_env57h1xd5 = {
- .name = "Panasonic ENV57H1XD5",
- .min = 44250000,
- .max = 858000000,
- .iffreq= 36125000,
- .count = 4,
- .entries = {
- { 153000000, 166667, 0xc2, 0x41 },
- { 470000000, 166667, 0xc2, 0x42 },
- { 526000000, 166667, 0xc2, 0x84 },
- { 999999999, 166667, 0xc2, 0xa4 },
- },
-};
-
-/* Philips TDA6650/TDA6651
- * used in Panasonic ENV77H11D5
- */
-static void tda665x_bw(struct dvb_frontend *fe, u8 *buf)
-{
- u32 bw = fe->dtv_property_cache.bandwidth_hz;
- if (bw == 8000000)
- buf[3] |= 0x08;
-}
-
-static struct dvb_pll_desc dvb_pll_tda665x = {
- .name = "Philips TDA6650/TDA6651",
- .min = 44250000,
- .max = 858000000,
- .set = tda665x_bw,
- .iffreq= 36166667,
- .initdata = (u8[]){ 4, 0x0b, 0xf5, 0x85, 0xab },
- .count = 12,
- .entries = {
- { 93834000, 166667, 0xca, 0x61 /* 011 0 0 0 01 */ },
- { 123834000, 166667, 0xca, 0xa1 /* 101 0 0 0 01 */ },
- { 161000000, 166667, 0xca, 0xa1 /* 101 0 0 0 01 */ },
- { 163834000, 166667, 0xca, 0xc2 /* 110 0 0 0 10 */ },
- { 253834000, 166667, 0xca, 0x62 /* 011 0 0 0 10 */ },
- { 383834000, 166667, 0xca, 0xa2 /* 101 0 0 0 10 */ },
- { 443834000, 166667, 0xca, 0xc2 /* 110 0 0 0 10 */ },
- { 444000000, 166667, 0xca, 0xc4 /* 110 0 0 1 00 */ },
- { 583834000, 166667, 0xca, 0x64 /* 011 0 0 1 00 */ },
- { 793834000, 166667, 0xca, 0xa4 /* 101 0 0 1 00 */ },
- { 444834000, 166667, 0xca, 0xc4 /* 110 0 0 1 00 */ },
- { 861000000, 166667, 0xca, 0xe4 /* 111 0 0 1 00 */ },
- }
-};
-
-/* Infineon TUA6034
- * used in LG TDTP E102P
- */
-static void tua6034_bw(struct dvb_frontend *fe, u8 *buf)
-{
- u32 bw = fe->dtv_property_cache.bandwidth_hz;
- if (bw == 7000000)
- buf[3] |= 0x08;
-}
-
-static struct dvb_pll_desc dvb_pll_tua6034 = {
- .name = "Infineon TUA6034",
- .min = 44250000,
- .max = 858000000,
- .iffreq= 36166667,
- .count = 3,
- .set = tua6034_bw,
- .entries = {
- { 174500000, 62500, 0xce, 0x01 },
- { 230000000, 62500, 0xce, 0x02 },
- { 999999999, 62500, 0xce, 0x04 },
- },
-};
-
-/* ALPS TDED4
- * used in Nebula-Cards and USB boxes
- */
-static void tded4_bw(struct dvb_frontend *fe, u8 *buf)
-{
- u32 bw = fe->dtv_property_cache.bandwidth_hz;
- if (bw == 8000000)
- buf[3] |= 0x04;
-}
-
-static struct dvb_pll_desc dvb_pll_tded4 = {
- .name = "ALPS TDED4",
- .min = 47000000,
- .max = 863000000,
- .iffreq= 36166667,
- .set = tded4_bw,
- .count = 4,
- .entries = {
- { 153000000, 166667, 0x85, 0x01 },
- { 470000000, 166667, 0x85, 0x02 },
- { 823000000, 166667, 0x85, 0x08 },
- { 999999999, 166667, 0x85, 0x88 },
- }
-};
-
-/* ALPS TDHU2
- * used in AverTVHD MCE A180
- */
-static struct dvb_pll_desc dvb_pll_tdhu2 = {
- .name = "ALPS TDHU2",
- .min = 54000000,
- .max = 864000000,
- .iffreq= 44000000,
- .count = 4,
- .entries = {
- { 162000000, 62500, 0x85, 0x01 },
- { 426000000, 62500, 0x85, 0x02 },
- { 782000000, 62500, 0x85, 0x08 },
- { 999999999, 62500, 0x85, 0x88 },
- }
-};
-
-/* Samsung TBMV30111IN / TBMV30712IN1
- * used in Air2PC ATSC - 2nd generation (nxt2002)
- */
-static struct dvb_pll_desc dvb_pll_samsung_tbmv = {
- .name = "Samsung TBMV30111IN / TBMV30712IN1",
- .min = 54000000,
- .max = 860000000,
- .iffreq= 44000000,
- .count = 6,
- .entries = {
- { 172000000, 166667, 0xb4, 0x01 },
- { 214000000, 166667, 0xb4, 0x02 },
- { 467000000, 166667, 0xbc, 0x02 },
- { 721000000, 166667, 0xbc, 0x08 },
- { 841000000, 166667, 0xf4, 0x08 },
- { 999999999, 166667, 0xfc, 0x02 },
- }
-};
-
-/*
- * Philips SD1878 Tuner.
- */
-static struct dvb_pll_desc dvb_pll_philips_sd1878_tda8261 = {
- .name = "Philips SD1878",
- .min = 950000,
- .max = 2150000,
- .iffreq= 249, /* zero-IF, offset 249 is to round up */
- .count = 4,
- .entries = {
- { 1250000, 500, 0xc4, 0x00},
- { 1450000, 500, 0xc4, 0x40},
- { 2050000, 500, 0xc4, 0x80},
- { 2150000, 500, 0xc4, 0xc0},
- },
-};
-
-static void opera1_bw(struct dvb_frontend *fe, u8 *buf)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct dvb_pll_priv *priv = fe->tuner_priv;
- u32 b_w = (c->symbol_rate * 27) / 32000;
- struct i2c_msg msg = {
- .addr = priv->pll_i2c_address,
- .flags = 0,
- .buf = buf,
- .len = 4
- };
- int result;
- u8 lpf;
-
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
-
- result = i2c_transfer(priv->i2c, &msg, 1);
- if (result != 1)
- printk(KERN_ERR "%s: i2c_transfer failed:%d",
- __func__, result);
-
- if (b_w <= 10000)
- lpf = 0xc;
- else if (b_w <= 12000)
- lpf = 0x2;
- else if (b_w <= 14000)
- lpf = 0xa;
- else if (b_w <= 16000)
- lpf = 0x6;
- else if (b_w <= 18000)
- lpf = 0xe;
- else if (b_w <= 20000)
- lpf = 0x1;
- else if (b_w <= 22000)
- lpf = 0x9;
- else if (b_w <= 24000)
- lpf = 0x5;
- else if (b_w <= 26000)
- lpf = 0xd;
- else if (b_w <= 28000)
- lpf = 0x3;
- else
- lpf = 0xb;
- buf[2] ^= 0x1c; /* Flip bits 3-5 */
- /* Set lpf */
- buf[2] |= ((lpf >> 2) & 0x3) << 3;
- buf[3] |= (lpf & 0x3) << 2;
-
- return;
-}
-
-static struct dvb_pll_desc dvb_pll_opera1 = {
- .name = "Opera Tuner",
- .min = 900000,
- .max = 2250000,
- .initdata = (u8[]){ 4, 0x08, 0xe5, 0xe1, 0x00 },
- .initdata2 = (u8[]){ 4, 0x08, 0xe5, 0xe5, 0x00 },
- .iffreq= 0,
- .set = opera1_bw,
- .count = 8,
- .entries = {
- { 1064000, 500, 0xf9, 0xc2 },
- { 1169000, 500, 0xf9, 0xe2 },
- { 1299000, 500, 0xf9, 0x20 },
- { 1444000, 500, 0xf9, 0x40 },
- { 1606000, 500, 0xf9, 0x60 },
- { 1777000, 500, 0xf9, 0x80 },
- { 1941000, 500, 0xf9, 0xa0 },
- { 2250000, 500, 0xf9, 0xc0 },
- }
-};
-
-static void samsung_dtos403ih102a_set(struct dvb_frontend *fe, u8 *buf)
-{
- struct dvb_pll_priv *priv = fe->tuner_priv;
- struct i2c_msg msg = {
- .addr = priv->pll_i2c_address,
- .flags = 0,
- .buf = buf,
- .len = 4
- };
- int result;
-
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
-
- result = i2c_transfer(priv->i2c, &msg, 1);
- if (result != 1)
- printk(KERN_ERR "%s: i2c_transfer failed:%d",
- __func__, result);
-
- buf[2] = 0x9e;
- buf[3] = 0x90;
-
- return;
-}
-
-/* unknown pll used in Samsung DTOS403IH102A DVB-C tuner */
-static struct dvb_pll_desc dvb_pll_samsung_dtos403ih102a = {
- .name = "Samsung DTOS403IH102A",
- .min = 44250000,
- .max = 858000000,
- .iffreq = 36125000,
- .count = 8,
- .set = samsung_dtos403ih102a_set,
- .entries = {
- { 135000000, 62500, 0xbe, 0x01 },
- { 177000000, 62500, 0xf6, 0x01 },
- { 370000000, 62500, 0xbe, 0x02 },
- { 450000000, 62500, 0xf6, 0x02 },
- { 466000000, 62500, 0xfe, 0x02 },
- { 538000000, 62500, 0xbe, 0x08 },
- { 826000000, 62500, 0xf6, 0x08 },
- { 999999999, 62500, 0xfe, 0x08 },
- }
-};
-
-/* Samsung TDTC9251DH0 DVB-T NIM, as used on AirStar 2 */
-static struct dvb_pll_desc dvb_pll_samsung_tdtc9251dh0 = {
- .name = "Samsung TDTC9251DH0",
- .min = 48000000,
- .max = 863000000,
- .iffreq = 36166667,
- .count = 3,
- .entries = {
- { 157500000, 166667, 0xcc, 0x09 },
- { 443000000, 166667, 0xcc, 0x0a },
- { 863000000, 166667, 0xcc, 0x08 },
- }
-};
-
-/* Samsung TBDU18132 DVB-S NIM with TSA5059 PLL, used in SkyStar2 DVB-S 2.3 */
-static struct dvb_pll_desc dvb_pll_samsung_tbdu18132 = {
- .name = "Samsung TBDU18132",
- .min = 950000,
- .max = 2150000, /* guesses */
- .iffreq = 0,
- .count = 2,
- .entries = {
- { 1550000, 125, 0x84, 0x82 },
- { 4095937, 125, 0x84, 0x80 },
- }
- /* TSA5059 PLL has a 17 bit divisor rather than the 15 bits supported
- * by this driver. The two extra bits are 0x60 in the third byte. 15
- * bits is enough for over 4 GHz, which is enough to cover the range
- * of this tuner. We could use the additional divisor bits by adding
- * more entries, e.g.
- { 0x0ffff * 125 + 125/2, 125, 0x84 | 0x20, },
- { 0x17fff * 125 + 125/2, 125, 0x84 | 0x40, },
- { 0x1ffff * 125 + 125/2, 125, 0x84 | 0x60, }, */
-};
-
-/* Samsung TBMU24112 DVB-S NIM with SL1935 zero-IF tuner */
-static struct dvb_pll_desc dvb_pll_samsung_tbmu24112 = {
- .name = "Samsung TBMU24112",
- .min = 950000,
- .max = 2150000, /* guesses */
- .iffreq = 0,
- .count = 2,
- .entries = {
- { 1500000, 125, 0x84, 0x18 },
- { 9999999, 125, 0x84, 0x08 },
- }
-};
-
-/* Alps TDEE4 DVB-C NIM, used on Cablestar 2 */
-/* byte 4 : 1 * * AGD R3 R2 R1 R0
- * byte 5 : C1 * RE RTS BS4 BS3 BS2 BS1
- * AGD = 1, R3 R2 R1 R0 = 0 1 0 1 => byte 4 = 1**10101 = 0x95
- * Range(MHz) C1 * RE RTS BS4 BS3 BS2 BS1 Byte 5
- * 47 - 153 0 * 0 0 0 0 0 1 0x01
- * 153 - 430 0 * 0 0 0 0 1 0 0x02
- * 430 - 822 0 * 0 0 1 0 0 0 0x08
- * 822 - 862 1 * 0 0 1 0 0 0 0x88 */
-static struct dvb_pll_desc dvb_pll_alps_tdee4 = {
- .name = "ALPS TDEE4",
- .min = 47000000,
- .max = 862000000,
- .iffreq = 36125000,
- .count = 4,
- .entries = {
- { 153000000, 62500, 0x95, 0x01 },
- { 430000000, 62500, 0x95, 0x02 },
- { 822000000, 62500, 0x95, 0x08 },
- { 999999999, 62500, 0x95, 0x88 },
- }
-};
-
-/* ----------------------------------------------------------- */
-
-static struct dvb_pll_desc *pll_list[] = {
- [DVB_PLL_UNDEFINED] = NULL,
- [DVB_PLL_THOMSON_DTT7579] = &dvb_pll_thomson_dtt7579,
- [DVB_PLL_THOMSON_DTT759X] = &dvb_pll_thomson_dtt759x,
- [DVB_PLL_THOMSON_DTT7520X] = &dvb_pll_thomson_dtt7520x,
- [DVB_PLL_LG_Z201] = &dvb_pll_lg_z201,
- [DVB_PLL_UNKNOWN_1] = &dvb_pll_unknown_1,
- [DVB_PLL_TUA6010XS] = &dvb_pll_tua6010xs,
- [DVB_PLL_ENV57H1XD5] = &dvb_pll_env57h1xd5,
- [DVB_PLL_TUA6034] = &dvb_pll_tua6034,
- [DVB_PLL_TDA665X] = &dvb_pll_tda665x,
- [DVB_PLL_TDED4] = &dvb_pll_tded4,
- [DVB_PLL_TDEE4] = &dvb_pll_alps_tdee4,
- [DVB_PLL_TDHU2] = &dvb_pll_tdhu2,
- [DVB_PLL_SAMSUNG_TBMV] = &dvb_pll_samsung_tbmv,
- [DVB_PLL_PHILIPS_SD1878_TDA8261] = &dvb_pll_philips_sd1878_tda8261,
- [DVB_PLL_OPERA1] = &dvb_pll_opera1,
- [DVB_PLL_SAMSUNG_DTOS403IH102A] = &dvb_pll_samsung_dtos403ih102a,
- [DVB_PLL_SAMSUNG_TDTC9251DH0] = &dvb_pll_samsung_tdtc9251dh0,
- [DVB_PLL_SAMSUNG_TBDU18132] = &dvb_pll_samsung_tbdu18132,
- [DVB_PLL_SAMSUNG_TBMU24112] = &dvb_pll_samsung_tbmu24112,
-};
-
-/* ----------------------------------------------------------- */
-/* code */
-
-static int dvb_pll_configure(struct dvb_frontend *fe, u8 *buf,
- const u32 frequency)
-{
- struct dvb_pll_priv *priv = fe->tuner_priv;
- struct dvb_pll_desc *desc = priv->pll_desc;
- u32 div;
- int i;
-
- if (frequency && (frequency < desc->min || frequency > desc->max))
- return -EINVAL;
-
- for (i = 0; i < desc->count; i++) {
- if (frequency > desc->entries[i].limit)
- continue;
- break;
- }
-
- if (debug)
- printk("pll: %s: freq=%d | i=%d/%d\n", desc->name,
- frequency, i, desc->count);
- if (i == desc->count)
- return -EINVAL;
-
- div = (frequency + desc->iffreq +
- desc->entries[i].stepsize/2) / desc->entries[i].stepsize;
- buf[0] = div >> 8;
- buf[1] = div & 0xff;
- buf[2] = desc->entries[i].config;
- buf[3] = desc->entries[i].cb;
-
- if (desc->set)
- desc->set(fe, buf);
-
- if (debug)
- printk("pll: %s: div=%d | buf=0x%02x,0x%02x,0x%02x,0x%02x\n",
- desc->name, div, buf[0], buf[1], buf[2], buf[3]);
-
- // calculate the frequency we set it to
- return (div * desc->entries[i].stepsize) - desc->iffreq;
-}
-
-static int dvb_pll_release(struct dvb_frontend *fe)
-{
- kfree(fe->tuner_priv);
- fe->tuner_priv = NULL;
- return 0;
-}
-
-static int dvb_pll_sleep(struct dvb_frontend *fe)
-{
- struct dvb_pll_priv *priv = fe->tuner_priv;
-
- if (priv->i2c == NULL)
- return -EINVAL;
-
- if (priv->pll_desc->sleepdata) {
- struct i2c_msg msg = { .flags = 0,
- .addr = priv->pll_i2c_address,
- .buf = priv->pll_desc->sleepdata + 1,
- .len = priv->pll_desc->sleepdata[0] };
-
- int result;
-
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
- if ((result = i2c_transfer(priv->i2c, &msg, 1)) != 1) {
- return result;
- }
- return 0;
- }
- /* Shouldn't be called when initdata is NULL, maybe BUG()? */
- return -EINVAL;
-}
-
-static int dvb_pll_set_params(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct dvb_pll_priv *priv = fe->tuner_priv;
- u8 buf[4];
- struct i2c_msg msg =
- { .addr = priv->pll_i2c_address, .flags = 0,
- .buf = buf, .len = sizeof(buf) };
- int result;
- u32 frequency = 0;
-
- if (priv->i2c == NULL)
- return -EINVAL;
-
- result = dvb_pll_configure(fe, buf, c->frequency);
- if (result < 0)
- return result;
- else
- frequency = result;
-
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
- if ((result = i2c_transfer(priv->i2c, &msg, 1)) != 1) {
- return result;
- }
-
- priv->frequency = frequency;
- priv->bandwidth = c->bandwidth_hz;
-
- return 0;
-}
-
-static int dvb_pll_calc_regs(struct dvb_frontend *fe,
- u8 *buf, int buf_len)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct dvb_pll_priv *priv = fe->tuner_priv;
- int result;
- u32 frequency = 0;
-
- if (buf_len < 5)
- return -EINVAL;
-
- result = dvb_pll_configure(fe, buf + 1, c->frequency);
- if (result < 0)
- return result;
- else
- frequency = result;
-
- buf[0] = priv->pll_i2c_address;
-
- priv->frequency = frequency;
- priv->bandwidth = c->bandwidth_hz;
-
- return 5;
-}
-
-static int dvb_pll_get_frequency(struct dvb_frontend *fe, u32 *frequency)
-{
- struct dvb_pll_priv *priv = fe->tuner_priv;
- *frequency = priv->frequency;
- return 0;
-}
-
-static int dvb_pll_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
-{
- struct dvb_pll_priv *priv = fe->tuner_priv;
- *bandwidth = priv->bandwidth;
- return 0;
-}
-
-static int dvb_pll_init(struct dvb_frontend *fe)
-{
- struct dvb_pll_priv *priv = fe->tuner_priv;
-
- if (priv->i2c == NULL)
- return -EINVAL;
-
- if (priv->pll_desc->initdata) {
- struct i2c_msg msg = { .flags = 0,
- .addr = priv->pll_i2c_address,
- .buf = priv->pll_desc->initdata + 1,
- .len = priv->pll_desc->initdata[0] };
-
- int result;
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
- result = i2c_transfer(priv->i2c, &msg, 1);
- if (result != 1)
- return result;
- if (priv->pll_desc->initdata2) {
- msg.buf = priv->pll_desc->initdata2 + 1;
- msg.len = priv->pll_desc->initdata2[0];
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
- result = i2c_transfer(priv->i2c, &msg, 1);
- if (result != 1)
- return result;
- }
- return 0;
- }
- /* Shouldn't be called when initdata is NULL, maybe BUG()? */
- return -EINVAL;
-}
-
-static struct dvb_tuner_ops dvb_pll_tuner_ops = {
- .release = dvb_pll_release,
- .sleep = dvb_pll_sleep,
- .init = dvb_pll_init,
- .set_params = dvb_pll_set_params,
- .calc_regs = dvb_pll_calc_regs,
- .get_frequency = dvb_pll_get_frequency,
- .get_bandwidth = dvb_pll_get_bandwidth,
-};
-
-struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe, int pll_addr,
- struct i2c_adapter *i2c,
- unsigned int pll_desc_id)
-{
- u8 b1 [] = { 0 };
- struct i2c_msg msg = { .addr = pll_addr, .flags = I2C_M_RD,
- .buf = b1, .len = 1 };
- struct dvb_pll_priv *priv = NULL;
- int ret;
- struct dvb_pll_desc *desc;
-
- if ((id[dvb_pll_devcount] > DVB_PLL_UNDEFINED) &&
- (id[dvb_pll_devcount] < ARRAY_SIZE(pll_list)))
- pll_desc_id = id[dvb_pll_devcount];
-
- BUG_ON(pll_desc_id < 1 || pll_desc_id >= ARRAY_SIZE(pll_list));
-
- desc = pll_list[pll_desc_id];
-
- if (i2c != NULL) {
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 1);
-
- ret = i2c_transfer (i2c, &msg, 1);
- if (ret != 1)
- return NULL;
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 0);
- }
-
- priv = kzalloc(sizeof(struct dvb_pll_priv), GFP_KERNEL);
- if (priv == NULL)
- return NULL;
-
- priv->pll_i2c_address = pll_addr;
- priv->i2c = i2c;
- priv->pll_desc = desc;
- priv->nr = dvb_pll_devcount++;
-
- memcpy(&fe->ops.tuner_ops, &dvb_pll_tuner_ops,
- sizeof(struct dvb_tuner_ops));
-
- strncpy(fe->ops.tuner_ops.info.name, desc->name,
- sizeof(fe->ops.tuner_ops.info.name));
- fe->ops.tuner_ops.info.frequency_min = desc->min;
- fe->ops.tuner_ops.info.frequency_max = desc->max;
- if (!desc->initdata)
- fe->ops.tuner_ops.init = NULL;
- if (!desc->sleepdata)
- fe->ops.tuner_ops.sleep = NULL;
-
- fe->tuner_priv = priv;
-
- if ((debug) || (id[priv->nr] == pll_desc_id)) {
- printk("dvb-pll[%d]", priv->nr);
- if (i2c != NULL)
- printk(" %d-%04x", i2c_adapter_id(i2c), pll_addr);
- printk(": id# %d (%s) attached, %s\n", pll_desc_id, desc->name,
- id[priv->nr] == pll_desc_id ?
- "insmod option" : "autodetected");
- }
-
- return fe;
-}
-EXPORT_SYMBOL(dvb_pll_attach);
-
-MODULE_DESCRIPTION("dvb pll library");
-MODULE_AUTHOR("Gerd Knorr");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dvb-pll.h b/drivers/media/dvb/frontends/dvb-pll.h
deleted file mode 100644
index 4de754f76ce..00000000000
--- a/drivers/media/dvb/frontends/dvb-pll.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * descriptions + helper functions for simple dvb plls.
- */
-
-#ifndef __DVB_PLL_H__
-#define __DVB_PLL_H__
-
-#include <linux/i2c.h>
-#include "dvb_frontend.h"
-
-#define DVB_PLL_UNDEFINED 0
-#define DVB_PLL_THOMSON_DTT7579 1
-#define DVB_PLL_THOMSON_DTT759X 2
-#define DVB_PLL_LG_Z201 3
-#define DVB_PLL_UNKNOWN_1 4
-#define DVB_PLL_TUA6010XS 5
-#define DVB_PLL_ENV57H1XD5 6
-#define DVB_PLL_TUA6034 7
-#define DVB_PLL_TDA665X 8
-#define DVB_PLL_TDED4 9
-#define DVB_PLL_TDHU2 10
-#define DVB_PLL_SAMSUNG_TBMV 11
-#define DVB_PLL_PHILIPS_SD1878_TDA8261 12
-#define DVB_PLL_OPERA1 13
-#define DVB_PLL_SAMSUNG_DTOS403IH102A 14
-#define DVB_PLL_SAMSUNG_TDTC9251DH0 15
-#define DVB_PLL_SAMSUNG_TBDU18132 16
-#define DVB_PLL_SAMSUNG_TBMU24112 17
-#define DVB_PLL_TDEE4 18
-#define DVB_PLL_THOMSON_DTT7520X 19
-
-/**
- * Attach a dvb-pll to the supplied frontend structure.
- *
- * @param fe Frontend to attach to.
- * @param pll_addr i2c address of the PLL (if used).
- * @param i2c i2c adapter to use (set to NULL if not used).
- * @param pll_desc_id dvb_pll_desc to use.
- * @return Frontend pointer on success, NULL on failure
- */
-#if defined(CONFIG_DVB_PLL) || (defined(CONFIG_DVB_PLL_MODULE) && defined(MODULE))
-extern struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe,
- int pll_addr,
- struct i2c_adapter *i2c,
- unsigned int pll_desc_id);
-#else
-static inline struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe,
- int pll_addr,
- struct i2c_adapter *i2c,
- unsigned int pll_desc_id)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif
diff --git a/drivers/media/dvb/frontends/dvb_dummy_fe.c b/drivers/media/dvb/frontends/dvb_dummy_fe.c
deleted file mode 100644
index dcfc902c867..00000000000
--- a/drivers/media/dvb/frontends/dvb_dummy_fe.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * Driver for Dummy Frontend
- *
- * Written by Emard <emard@softhome.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-
-#include "dvb_frontend.h"
-#include "dvb_dummy_fe.h"
-
-
-struct dvb_dummy_fe_state {
- struct dvb_frontend frontend;
-};
-
-
-static int dvb_dummy_fe_read_status(struct dvb_frontend* fe, fe_status_t* status)
-{
- *status = FE_HAS_SIGNAL
- | FE_HAS_CARRIER
- | FE_HAS_VITERBI
- | FE_HAS_SYNC
- | FE_HAS_LOCK;
-
- return 0;
-}
-
-static int dvb_dummy_fe_read_ber(struct dvb_frontend* fe, u32* ber)
-{
- *ber = 0;
- return 0;
-}
-
-static int dvb_dummy_fe_read_signal_strength(struct dvb_frontend* fe, u16* strength)
-{
- *strength = 0;
- return 0;
-}
-
-static int dvb_dummy_fe_read_snr(struct dvb_frontend* fe, u16* snr)
-{
- *snr = 0;
- return 0;
-}
-
-static int dvb_dummy_fe_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
-{
- *ucblocks = 0;
- return 0;
-}
-
-/*
- * Only needed if it actually reads something from the hardware
- */
-static int dvb_dummy_fe_get_frontend(struct dvb_frontend *fe)
-{
- return 0;
-}
-
-static int dvb_dummy_fe_set_frontend(struct dvb_frontend *fe)
-{
- if (fe->ops.tuner_ops.set_params) {
- fe->ops.tuner_ops.set_params(fe);
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 0);
- }
-
- return 0;
-}
-
-static int dvb_dummy_fe_sleep(struct dvb_frontend* fe)
-{
- return 0;
-}
-
-static int dvb_dummy_fe_init(struct dvb_frontend* fe)
-{
- return 0;
-}
-
-static int dvb_dummy_fe_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
-{
- return 0;
-}
-
-static int dvb_dummy_fe_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
-{
- return 0;
-}
-
-static void dvb_dummy_fe_release(struct dvb_frontend* fe)
-{
- struct dvb_dummy_fe_state* state = fe->demodulator_priv;
- kfree(state);
-}
-
-static struct dvb_frontend_ops dvb_dummy_fe_ofdm_ops;
-
-struct dvb_frontend* dvb_dummy_fe_ofdm_attach(void)
-{
- struct dvb_dummy_fe_state* state = NULL;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
- if (state == NULL) goto error;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &dvb_dummy_fe_ofdm_ops, sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
- return &state->frontend;
-
-error:
- kfree(state);
- return NULL;
-}
-
-static struct dvb_frontend_ops dvb_dummy_fe_qpsk_ops;
-
-struct dvb_frontend *dvb_dummy_fe_qpsk_attach(void)
-{
- struct dvb_dummy_fe_state* state = NULL;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
- if (state == NULL) goto error;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &dvb_dummy_fe_qpsk_ops, sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
- return &state->frontend;
-
-error:
- kfree(state);
- return NULL;
-}
-
-static struct dvb_frontend_ops dvb_dummy_fe_qam_ops;
-
-struct dvb_frontend *dvb_dummy_fe_qam_attach(void)
-{
- struct dvb_dummy_fe_state* state = NULL;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
- if (state == NULL) goto error;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &dvb_dummy_fe_qam_ops, sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
- return &state->frontend;
-
-error:
- kfree(state);
- return NULL;
-}
-
-static struct dvb_frontend_ops dvb_dummy_fe_ofdm_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "Dummy DVB-T",
- .frequency_min = 0,
- .frequency_max = 863250000,
- .frequency_stepsize = 62500,
- .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
- FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
- FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_HIERARCHY_AUTO,
- },
-
- .release = dvb_dummy_fe_release,
-
- .init = dvb_dummy_fe_init,
- .sleep = dvb_dummy_fe_sleep,
-
- .set_frontend = dvb_dummy_fe_set_frontend,
- .get_frontend = dvb_dummy_fe_get_frontend,
-
- .read_status = dvb_dummy_fe_read_status,
- .read_ber = dvb_dummy_fe_read_ber,
- .read_signal_strength = dvb_dummy_fe_read_signal_strength,
- .read_snr = dvb_dummy_fe_read_snr,
- .read_ucblocks = dvb_dummy_fe_read_ucblocks,
-};
-
-static struct dvb_frontend_ops dvb_dummy_fe_qam_ops = {
- .delsys = { SYS_DVBC_ANNEX_A },
- .info = {
- .name = "Dummy DVB-C",
- .frequency_stepsize = 62500,
- .frequency_min = 51000000,
- .frequency_max = 858000000,
- .symbol_rate_min = (57840000/2)/64, /* SACLK/64 == (XIN/2)/64 */
- .symbol_rate_max = (57840000/2)/4, /* SACLK/4 */
- .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
- FE_CAN_QAM_128 | FE_CAN_QAM_256 |
- FE_CAN_FEC_AUTO | FE_CAN_INVERSION_AUTO
- },
-
- .release = dvb_dummy_fe_release,
-
- .init = dvb_dummy_fe_init,
- .sleep = dvb_dummy_fe_sleep,
-
- .set_frontend = dvb_dummy_fe_set_frontend,
- .get_frontend = dvb_dummy_fe_get_frontend,
-
- .read_status = dvb_dummy_fe_read_status,
- .read_ber = dvb_dummy_fe_read_ber,
- .read_signal_strength = dvb_dummy_fe_read_signal_strength,
- .read_snr = dvb_dummy_fe_read_snr,
- .read_ucblocks = dvb_dummy_fe_read_ucblocks,
-};
-
-static struct dvb_frontend_ops dvb_dummy_fe_qpsk_ops = {
- .delsys = { SYS_DVBS },
- .info = {
- .name = "Dummy DVB-S",
- .frequency_min = 950000,
- .frequency_max = 2150000,
- .frequency_stepsize = 250, /* kHz for QPSK frontends */
- .frequency_tolerance = 29500,
- .symbol_rate_min = 1000000,
- .symbol_rate_max = 45000000,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK
- },
-
- .release = dvb_dummy_fe_release,
-
- .init = dvb_dummy_fe_init,
- .sleep = dvb_dummy_fe_sleep,
-
- .set_frontend = dvb_dummy_fe_set_frontend,
- .get_frontend = dvb_dummy_fe_get_frontend,
-
- .read_status = dvb_dummy_fe_read_status,
- .read_ber = dvb_dummy_fe_read_ber,
- .read_signal_strength = dvb_dummy_fe_read_signal_strength,
- .read_snr = dvb_dummy_fe_read_snr,
- .read_ucblocks = dvb_dummy_fe_read_ucblocks,
-
- .set_voltage = dvb_dummy_fe_set_voltage,
- .set_tone = dvb_dummy_fe_set_tone,
-};
-
-MODULE_DESCRIPTION("DVB DUMMY Frontend");
-MODULE_AUTHOR("Emard");
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(dvb_dummy_fe_ofdm_attach);
-EXPORT_SYMBOL(dvb_dummy_fe_qam_attach);
-EXPORT_SYMBOL(dvb_dummy_fe_qpsk_attach);
diff --git a/drivers/media/dvb/frontends/dvb_dummy_fe.h b/drivers/media/dvb/frontends/dvb_dummy_fe.h
deleted file mode 100644
index 1fcb987d638..00000000000
--- a/drivers/media/dvb/frontends/dvb_dummy_fe.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Driver for Dummy Frontend
- *
- * Written by Emard <emard@softhome.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
- */
-
-#ifndef DVB_DUMMY_FE_H
-#define DVB_DUMMY_FE_H
-
-#include <linux/dvb/frontend.h>
-#include "dvb_frontend.h"
-
-#if defined(CONFIG_DVB_DUMMY_FE) || (defined(CONFIG_DVB_DUMMY_FE_MODULE) && \
-defined(MODULE))
-extern struct dvb_frontend* dvb_dummy_fe_ofdm_attach(void);
-extern struct dvb_frontend* dvb_dummy_fe_qpsk_attach(void);
-extern struct dvb_frontend* dvb_dummy_fe_qam_attach(void);
-#else
-static inline struct dvb_frontend *dvb_dummy_fe_ofdm_attach(void)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-static inline struct dvb_frontend *dvb_dummy_fe_qpsk_attach(void)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-static inline struct dvb_frontend *dvb_dummy_fe_qam_attach(void)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif /* CONFIG_DVB_DUMMY_FE */
-
-#endif // DVB_DUMMY_FE_H
diff --git a/drivers/media/dvb/frontends/ec100.c b/drivers/media/dvb/frontends/ec100.c
deleted file mode 100644
index c56fddbf53b..00000000000
--- a/drivers/media/dvb/frontends/ec100.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * E3C EC100 demodulator driver
- *
- * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include "dvb_frontend.h"
-#include "ec100_priv.h"
-#include "ec100.h"
-
-int ec100_debug;
-module_param_named(debug, ec100_debug, int, 0644);
-MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-
-struct ec100_state {
- struct i2c_adapter *i2c;
- struct dvb_frontend frontend;
- struct ec100_config config;
-
- u16 ber;
-};
-
-/* write single register */
-static int ec100_write_reg(struct ec100_state *state, u8 reg, u8 val)
-{
- u8 buf[2] = {reg, val};
- struct i2c_msg msg = {
- .addr = state->config.demod_address,
- .flags = 0,
- .len = 2,
- .buf = buf};
-
- if (i2c_transfer(state->i2c, &msg, 1) != 1) {
- warn("I2C write failed reg:%02x", reg);
- return -EREMOTEIO;
- }
- return 0;
-}
-
-/* read single register */
-static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val)
-{
- struct i2c_msg msg[2] = {
- {
- .addr = state->config.demod_address,
- .flags = 0,
- .len = 1,
- .buf = &reg
- }, {
- .addr = state->config.demod_address,
- .flags = I2C_M_RD,
- .len = 1,
- .buf = val
- }
- };
-
- if (i2c_transfer(state->i2c, msg, 2) != 2) {
- warn("I2C read failed reg:%02x", reg);
- return -EREMOTEIO;
- }
- return 0;
-}
-
-static int ec100_set_frontend(struct dvb_frontend *fe)
-{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- struct ec100_state *state = fe->demodulator_priv;
- int ret;
- u8 tmp, tmp2;
-
- deb_info("%s: freq:%d bw:%d\n", __func__, c->frequency,
- c->bandwidth_hz);
-
- /* program tuner */
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
-
- ret = ec100_write_reg(state, 0x04, 0x06);
- if (ret)
- goto error;
- ret = ec100_write_reg(state, 0x67, 0x58);
- if (ret)
- goto error;
- ret = ec100_write_reg(state, 0x05, 0x18);
- if (ret)
- goto error;
-
- /* reg/bw | 6 | 7 | 8
- -------+------+------+------
- A 0x1b | 0xa1 | 0xe7 | 0x2c
- A 0x1c | 0x55 | 0x63 | 0x72
- -------+------+------+------
- B 0x1b | 0xb7 | 0x00 | 0x49
- B 0x1c | 0x55 | 0x64 | 0x72 */
-
- switch (c->bandwidth_hz) {
- case 6000000:
- tmp = 0xb7;
- tmp2 = 0x55;
- break;
- case 7000000:
- tmp = 0x00;
- tmp2 = 0x64;
- break;
- case 8000000:
- default:
- tmp = 0x49;
- tmp2 = 0x72;
- }
-
- ret = ec100_write_reg(state, 0x1b, tmp);
- if (ret)
- goto error;
- ret = ec100_write_reg(state, 0x1c, tmp2);
- if (ret)
- goto error;
-
- ret = ec100_write_reg(state, 0x0c, 0xbb); /* if freq */
- if (ret)
- goto error;
- ret = ec100_write_reg(state, 0x0d, 0x31); /* if freq */
- if (ret)
- goto error;
-
- ret = ec100_write_reg(state, 0x08, 0x24);
- if (ret)
- goto error;
-
- ret = ec100_write_reg(state, 0x00, 0x00); /* go */
- if (ret)
- goto error;
- ret = ec100_write_reg(state, 0x00, 0x20); /* go */
- if (ret)
- goto error;
-
- return ret;
-error:
- deb_info("%s: failed:%d\n", __func__, ret);
- return ret;
-}
-
-static int ec100_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *fesettings)
-{
- fesettings->min_delay_ms = 300;
- fesettings->step_size = 0;
- fesettings->max_drift = 0;
-
- return 0;
-}
-
-static int ec100_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct ec100_state *state = fe->demodulator_priv;
- int ret;
- u8 tmp;
- *status = 0;
-
- ret = ec100_read_reg(state, 0x42, &tmp);
- if (ret)
- goto error;
-
- if (tmp & 0x80) {
- /* bit7 set - have lock */
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
- FE_HAS_SYNC | FE_HAS_LOCK;
- } else {
- ret = ec100_read_reg(state, 0x01, &tmp);
- if (ret)
- goto error;
-
- if (tmp & 0x10) {
- /* bit4 set - have signal */
- *status |= FE_HAS_SIGNAL;
- if (!(tmp & 0x01)) {
- /* bit0 clear - have ~valid signal */
- *status |= FE_HAS_CARRIER | FE_HAS_VITERBI;
- }
- }
- }
-
- return ret;
-error:
- deb_info("%s: failed:%d\n", __func__, ret);
- return ret;
-}
-
-static int ec100_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- struct ec100_state *state = fe->demodulator_priv;
- int ret;
- u8 tmp, tmp2;
- u16 ber2;
-
- *ber = 0;
-
- ret = ec100_read_reg(state, 0x65, &tmp);
- if (ret)
- goto error;
- ret = ec100_read_reg(state, 0x66, &tmp2);
- if (ret)
- goto error;
-
- ber2 = (tmp2 << 8) | tmp;
-
- /* if counter overflow or clear */
- if (ber2 < state->ber)
- *ber = ber2;
- else
- *ber = ber2 - state->ber;
-
- state->ber = ber2;
-
- return ret;
-error:
- deb_info("%s: failed:%d\n", __func__, ret);
- return ret;
-}
-
-static int ec100_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
-{
- struct ec100_state *state = fe->demodulator_priv;
- int ret;
- u8 tmp;
-
- ret = ec100_read_reg(state, 0x24, &tmp);
- if (ret) {
- *strength = 0;
- goto error;
- }
-
- *strength = ((tmp << 8) | tmp);
-
- return ret;
-error:
- deb_info("%s: failed:%d\n", __func__, ret);
- return ret;
-}
-
-static int ec100_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- *snr = 0;
- return 0;
-}
-
-static int ec100_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- *ucblocks = 0;
- return 0;
-}
-
-static void ec100_release(struct dvb_frontend *fe)
-{
- struct ec100_state *state = fe->demodulator_priv;
- kfree(state);
-}
-
-static struct dvb_frontend_ops ec100_ops;
-
-struct dvb_frontend *ec100_attach(const struct ec100_config *config,
- struct i2c_adapter *i2c)
-{
- int ret;
- struct ec100_state *state = NULL;
- u8 tmp;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct ec100_state), GFP_KERNEL);
- if (state == NULL)
- goto error;
-
- /* setup the state */
- state->i2c = i2c;
- memcpy(&state->config, config, sizeof(struct ec100_config));
-
- /* check if the demod is there */
- ret = ec100_read_reg(state, 0x33, &tmp);
- if (ret || tmp != 0x0b)
- goto error;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &ec100_ops,
- sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
-
- return &state->frontend;
-error:
- kfree(state);
- return NULL;
-}
-EXPORT_SYMBOL(ec100_attach);
-
-static struct dvb_frontend_ops ec100_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "E3C EC100 DVB-T",
- .caps =
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 |
- FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_HIERARCHY_AUTO |
- FE_CAN_MUTE_TS
- },
-
- .release = ec100_release,
- .set_frontend = ec100_set_frontend,
- .get_tune_settings = ec100_get_tune_settings,
- .read_status = ec100_read_status,
- .read_ber = ec100_read_ber,
- .read_signal_strength = ec100_read_signal_strength,
- .read_snr = ec100_read_snr,
- .read_ucblocks = ec100_read_ucblocks,
-};
-
-MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
-MODULE_DESCRIPTION("E3C EC100 DVB-T demodulator driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/ec100.h b/drivers/media/dvb/frontends/ec100.h
deleted file mode 100644
index ee8e5241795..00000000000
--- a/drivers/media/dvb/frontends/ec100.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * E3C EC100 demodulator driver
- *
- * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef EC100_H
-#define EC100_H
-
-#include <linux/dvb/frontend.h>
-
-struct ec100_config {
- /* demodulator's I2C address */
- u8 demod_address;
-};
-
-
-#if defined(CONFIG_DVB_EC100) || \
- (defined(CONFIG_DVB_EC100_MODULE) && defined(MODULE))
-extern struct dvb_frontend *ec100_attach(const struct ec100_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline struct dvb_frontend *ec100_attach(
- const struct ec100_config *config, struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif /* EC100_H */
diff --git a/drivers/media/dvb/frontends/ec100_priv.h b/drivers/media/dvb/frontends/ec100_priv.h
deleted file mode 100644
index 5c990144bc4..00000000000
--- a/drivers/media/dvb/frontends/ec100_priv.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * E3C EC100 demodulator driver
- *
- * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef EC100_PRIV
-#define EC100_PRIV
-
-#define LOG_PREFIX "ec100"
-
-#define dprintk(var, level, args...) \
- do { if ((var & level)) printk(args); } while (0)
-
-#define deb_info(args...) dprintk(ec100_debug, 0x01, args)
-
-#undef err
-#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
-#undef info
-#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
-#undef warn
-#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
-
-#endif /* EC100_PRIV */
diff --git a/drivers/media/dvb/frontends/eds1547.h b/drivers/media/dvb/frontends/eds1547.h
deleted file mode 100644
index c983f2f8580..00000000000
--- a/drivers/media/dvb/frontends/eds1547.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* eds1547.h Earda EDS-1547 tuner support
-*
-* Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by)
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation, version 2.
-*
-* see Documentation/dvb/README.dvb-usb for more information
-*/
-
-#ifndef EDS1547
-#define EDS1547
-
-static u8 stv0288_earda_inittab[] = {
- 0x01, 0x57,
- 0x02, 0x20,
- 0x03, 0x8e,
- 0x04, 0x8e,
- 0x05, 0x12,
- 0x06, 0x00,
- 0x07, 0x00,
- 0x09, 0x00,
- 0x0a, 0x04,
- 0x0b, 0x00,
- 0x0c, 0x00,
- 0x0d, 0x00,
- 0x0e, 0xd4,
- 0x0f, 0x30,
- 0x11, 0x44,
- 0x12, 0x03,
- 0x13, 0x48,
- 0x14, 0x84,
- 0x15, 0x45,
- 0x16, 0xb7,
- 0x17, 0x9c,
- 0x18, 0x00,
- 0x19, 0xa6,
- 0x1a, 0x88,
- 0x1b, 0x8f,
- 0x1c, 0xf0,
- 0x20, 0x0b,
- 0x21, 0x54,
- 0x22, 0x00,
- 0x23, 0x00,
- 0x2b, 0xff,
- 0x2c, 0xf7,
- 0x30, 0x00,
- 0x31, 0x1e,
- 0x32, 0x14,
- 0x33, 0x0f,
- 0x34, 0x09,
- 0x35, 0x0c,
- 0x36, 0x05,
- 0x37, 0x2f,
- 0x38, 0x16,
- 0x39, 0xbd,
- 0x3a, 0x00,
- 0x3b, 0x13,
- 0x3c, 0x11,
- 0x3d, 0x30,
- 0x40, 0x63,
- 0x41, 0x04,
- 0x42, 0x20,
- 0x43, 0x00,
- 0x44, 0x00,
- 0x45, 0x00,
- 0x46, 0x00,
- 0x47, 0x00,
- 0x4a, 0x00,
- 0x50, 0x10,
- 0x51, 0x36,
- 0x52, 0x09,
- 0x53, 0x94,
- 0x54, 0x62,
- 0x55, 0x29,
- 0x56, 0x64,
- 0x57, 0x2b,
- 0x58, 0x54,
- 0x59, 0x86,
- 0x5a, 0x00,
- 0x5b, 0x9b,
- 0x5c, 0x08,
- 0x5d, 0x7f,
- 0x5e, 0x00,
- 0x5f, 0xff,
- 0x70, 0x00,
- 0x71, 0x00,
- 0x72, 0x00,
- 0x74, 0x00,
- 0x75, 0x00,
- 0x76, 0x00,
- 0x81, 0x00,
- 0x82, 0x3f,
- 0x83, 0x3f,
- 0x84, 0x00,
- 0x85, 0x00,
- 0x88, 0x00,
- 0x89, 0x00,
- 0x8a, 0x00,
- 0x8b, 0x00,
- 0x8c, 0x00,
- 0x90, 0x00,
- 0x91, 0x00,
- 0x92, 0x00,
- 0x93, 0x00,
- 0x94, 0x1c,
- 0x97, 0x00,
- 0xa0, 0x48,
- 0xa1, 0x00,
- 0xb0, 0xb8,
- 0xb1, 0x3a,
- 0xb2, 0x10,
- 0xb3, 0x82,
- 0xb4, 0x80,
- 0xb5, 0x82,
- 0xb6, 0x82,
- 0xb7, 0x82,
- 0xb8, 0x20,
- 0xb9, 0x00,
- 0xf0, 0x00,
- 0xf1, 0x00,
- 0xf2, 0xc0,
- 0xff,0xff,
-};
-
-static struct stv0288_config earda_config = {
- .demod_address = 0x68,
- .min_delay_ms = 100,
- .inittab = stv0288_earda_inittab,
-};
-
-#endif
diff --git a/drivers/media/dvb/frontends/hd29l2.c b/drivers/media/dvb/frontends/hd29l2.c
deleted file mode 100644
index a0031819083..00000000000
--- a/drivers/media/dvb/frontends/hd29l2.c
+++ /dev/null
@@ -1,861 +0,0 @@
-/*
- * HDIC HD29L2 DMB-TH demodulator driver
- *
- * Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
- *
- * Author: Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include "hd29l2_priv.h"
-
-int hd29l2_debug;
-module_param_named(debug, hd29l2_debug, int, 0644);
-MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-
-/* write multiple registers */
-static int hd29l2_wr_regs(struct hd29l2_priv *priv, u8 reg, u8 *val, int len)
-{
- int ret;
- u8 buf[2 + len];
- struct i2c_msg msg[1] = {
- {
- .addr = priv->cfg.i2c_addr,
- .flags = 0,
- .len = sizeof(buf),
- .buf = buf,
- }
- };
-
- buf[0] = 0x00;
- buf[1] = reg;
- memcpy(&buf[2], val, len);
-
- ret = i2c_transfer(priv->i2c, msg, 1);
- if (ret == 1) {
- ret = 0;
- } else {
- warn("i2c wr failed=%d reg=%02x len=%d", ret, reg, len);
- ret = -EREMOTEIO;
- }
-
- return ret;
-}
-
-/* read multiple registers */
-static int hd29l2_rd_regs(struct hd29l2_priv *priv, u8 reg, u8 *val, int len)
-{
- int ret;
- u8 buf[2] = { 0x00, reg };
- struct i2c_msg msg[2] = {
- {
- .addr = priv->cfg.i2c_addr,
- .flags = 0,
- .len = 2,
- .buf = buf,
- }, {
- .addr = priv->cfg.i2c_addr,
- .flags = I2C_M_RD,
- .len = len,
- .buf = val,
- }
- };
-
- ret = i2c_transfer(priv->i2c, msg, 2);
- if (ret == 2) {
- ret = 0;
- } else {
- warn("i2c rd failed=%d reg=%02x len=%d", ret, reg, len);
- ret = -EREMOTEIO;
- }
-
- return ret;
-}
-
-/* write single register */
-static int hd29l2_wr_reg(struct hd29l2_priv *priv, u8 reg, u8 val)
-{
- return hd29l2_wr_regs(priv, reg, &val, 1);
-}
-
-/* read single register */
-static int hd29l2_rd_reg(struct hd29l2_priv *priv, u8 reg, u8 *val)
-{
- return hd29l2_rd_regs(priv, reg, val, 1);
-}
-
-/* write single register with mask */
-static int hd29l2_wr_reg_mask(struct hd29l2_priv *priv, u8 reg, u8 val, u8 mask)
-{
- int ret;
- u8 tmp;
-
- /* no need for read if whole reg is written */
- if (mask != 0xff) {
- ret = hd29l2_rd_regs(priv, reg, &tmp, 1);
- if (ret)
- return ret;
-
- val &= mask;
- tmp &= ~mask;
- val |= tmp;
- }
-
- return hd29l2_wr_regs(priv, reg, &val, 1);
-}
-
-/* read single register with mask */
-int hd29l2_rd_reg_mask(struct hd29l2_priv *priv, u8 reg, u8 *val, u8 mask)
-{
- int ret, i;
- u8 tmp;
-
- ret = hd29l2_rd_regs(priv, reg, &tmp, 1);
- if (ret)
- return ret;
-
- tmp &= mask;
-
- /* find position of the first bit */
- for (i = 0; i < 8; i++) {
- if ((mask >> i) & 0x01)
- break;
- }
- *val = tmp >> i;
-
- return 0;
-}
-
-static int hd29l2_soft_reset(struct hd29l2_priv *priv)
-{
- int ret;
- u8 tmp;
-
- ret = hd29l2_rd_reg(priv, 0x26, &tmp);
- if (ret)
- goto err;
-
- ret = hd29l2_wr_reg(priv, 0x26, 0x0d);
- if (ret)
- goto err;
-
- usleep_range(10000, 20000);
-
- ret = hd29l2_wr_reg(priv, 0x26, tmp);
- if (ret)
- goto err;
-
- return 0;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int hd29l2_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
-{
- int ret, i;
- struct hd29l2_priv *priv = fe->demodulator_priv;
- u8 tmp;
-
- dbg("%s: enable=%d", __func__, enable);
-
- /* set tuner address for demod */
- if (!priv->tuner_i2c_addr_programmed && enable) {
- /* no need to set tuner address every time, once is enough */
- ret = hd29l2_wr_reg(priv, 0x9d, priv->cfg.tuner_i2c_addr << 1);
- if (ret)
- goto err;
-
- priv->tuner_i2c_addr_programmed = true;
- }
-
- /* open / close gate */
- ret = hd29l2_wr_reg(priv, 0x9f, enable);
- if (ret)
- goto err;
-
- /* wait demod ready */
- for (i = 10; i; i--) {
- ret = hd29l2_rd_reg(priv, 0x9e, &tmp);
- if (ret)
- goto err;
-
- if (tmp == enable)
- break;
-
- usleep_range(5000, 10000);
- }
-
- dbg("%s: loop=%d", __func__, i);
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int hd29l2_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- int ret;
- struct hd29l2_priv *priv = fe->demodulator_priv;
- u8 buf[2];
-
- *status = 0;
-
- ret = hd29l2_rd_reg(priv, 0x05, &buf[0]);
- if (ret)
- goto err;
-
- if (buf[0] & 0x01) {
- /* full lock */
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
- FE_HAS_SYNC | FE_HAS_LOCK;
- } else {
- ret = hd29l2_rd_reg(priv, 0x0d, &buf[1]);
- if (ret)
- goto err;
-
- if ((buf[1] & 0xfe) == 0x78)
- /* partial lock */
- *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
- FE_HAS_VITERBI | FE_HAS_SYNC;
- }
-
- priv->fe_status = *status;
-
- return 0;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int hd29l2_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- int ret;
- struct hd29l2_priv *priv = fe->demodulator_priv;
- u8 buf[2];
- u16 tmp;
-
- if (!(priv->fe_status & FE_HAS_LOCK)) {
- *snr = 0;
- ret = 0;
- goto err;
- }
-
- ret = hd29l2_rd_regs(priv, 0x0b, buf, 2);
- if (ret)
- goto err;
-
- tmp = (buf[0] << 8) | buf[1];
-
- /* report SNR in dB * 10 */
- #define LOG10_20736_24 72422627 /* log10(20736) << 24 */
- if (tmp)
- *snr = (LOG10_20736_24 - intlog10(tmp)) / ((1 << 24) / 100);
- else
- *snr = 0;
-
- return 0;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int hd29l2_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
-{
- int ret;
- struct hd29l2_priv *priv = fe->demodulator_priv;
- u8 buf[2];
- u16 tmp;
-
- *strength = 0;
-
- ret = hd29l2_rd_regs(priv, 0xd5, buf, 2);
- if (ret)
- goto err;
-
- tmp = buf[0] << 8 | buf[1];
- tmp = ~tmp & 0x0fff;
-
- /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
- *strength = tmp * 0xffff / 0x0fff;
-
- return 0;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int hd29l2_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- int ret;
- struct hd29l2_priv *priv = fe->demodulator_priv;
- u8 buf[2];
-
- if (!(priv->fe_status & FE_HAS_SYNC)) {
- *ber = 0;
- ret = 0;
- goto err;
- }
-
- ret = hd29l2_rd_regs(priv, 0xd9, buf, 2);
- if (ret) {
- *ber = 0;
- goto err;
- }
-
- /* LDPC BER */
- *ber = ((buf[0] & 0x0f) << 8) | buf[1];
-
- return 0;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int hd29l2_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- /* no way to read? */
- *ucblocks = 0;
- return 0;
-}
-
-static enum dvbfe_search hd29l2_search(struct dvb_frontend *fe)
-{
- int ret, i;
- struct hd29l2_priv *priv = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- u8 tmp, buf[3];
- u8 modulation, carrier, guard_interval, interleave, code_rate;
- u64 num64;
- u32 if_freq, if_ctl;
- bool auto_mode;
-
- dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d " \
- "modulation=%d inversion=%d fec_inner=%d guard_interval=%d",
- __func__,
- c->delivery_system, c->frequency, c->bandwidth_hz,
- c->modulation, c->inversion, c->fec_inner, c->guard_interval);
-
- /* as for now we detect always params automatically */
- auto_mode = true;
-
- /* program tuner */
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe);
-
- /* get and program IF */
- if (fe->ops.tuner_ops.get_if_frequency)
- fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
- else
- if_freq = 0;
-
- if (if_freq) {
- /* normal IF */
-
- /* calc IF control value */
- num64 = if_freq;
- num64 *= 0x800000;
- num64 = div_u64(num64, HD29L2_XTAL);
- num64 -= 0x800000;
- if_ctl = num64;
-
- tmp = 0xfc; /* tuner type normal */
- } else {
- /* zero IF */
- if_ctl = 0;
- tmp = 0xfe; /* tuner type Zero-IF */
- }
-
- buf[0] = ((if_ctl >> 0) & 0xff);
- buf[1] = ((if_ctl >> 8) & 0xff);
- buf[2] = ((if_ctl >> 16) & 0xff);
-
- /* program IF control */
- ret = hd29l2_wr_regs(priv, 0x14, buf, 3);
- if (ret)
- goto err;
-
- /* program tuner type */
- ret = hd29l2_wr_reg(priv, 0xab, tmp);
- if (ret)
- goto err;
-
- dbg("%s: if_freq=%d if_ctl=%x", __func__, if_freq, if_ctl);
-
- if (auto_mode) {
- /*
- * use auto mode
- */
-
- /* disable quick mode */
- ret = hd29l2_wr_reg_mask(priv, 0xac, 0 << 7, 0x80);
- if (ret)
- goto err;
-
- ret = hd29l2_wr_reg_mask(priv, 0x82, 1 << 1, 0x02);
- if (ret)
- goto err;
-
- /* enable auto mode */
- ret = hd29l2_wr_reg_mask(priv, 0x7d, 1 << 6, 0x40);
- if (ret)
- goto err;
-
- ret = hd29l2_wr_reg_mask(priv, 0x81, 1 << 3, 0x08);
- if (ret)
- goto err;
-
- /* soft reset */
- ret = hd29l2_soft_reset(priv);
- if (ret)
- goto err;
-
- /* detect modulation */
- for (i = 30; i; i--) {
- msleep(100);
-
- ret = hd29l2_rd_reg(priv, 0x0d, &tmp);
- if (ret)
- goto err;
-
- if ((((tmp & 0xf0) >= 0x10) &&
- ((tmp & 0x0f) == 0x08)) || (tmp >= 0x2c))
- break;
- }
-
- dbg("%s: loop=%d", __func__, i);
-
- if (i == 0)
- /* detection failed */
- return DVBFE_ALGO_SEARCH_FAILED;
-
- /* read modulation */
- ret = hd29l2_rd_reg_mask(priv, 0x7d, &modulation, 0x07);
- if (ret)
- goto err;
- } else {
- /*
- * use manual mode
- */
-
- modulation = HD29L2_QAM64;
- carrier = HD29L2_CARRIER_MULTI;
- guard_interval = HD29L2_PN945;
- interleave = HD29L2_INTERLEAVER_420;
- code_rate = HD29L2_CODE_RATE_08;
-
- tmp = (code_rate << 3) | modulation;
- ret = hd29l2_wr_reg_mask(priv, 0x7d, tmp, 0x5f);
- if (ret)
- goto err;
-
- tmp = (carrier << 2) | guard_interval;
- ret = hd29l2_wr_reg_mask(priv, 0x81, tmp, 0x0f);
- if (ret)
- goto err;
-
- tmp = interleave;
- ret = hd29l2_wr_reg_mask(priv, 0x82, tmp, 0x03);
- if (ret)
- goto err;
- }
-
- /* ensure modulation validy */
- /* 0=QAM4_NR, 1=QAM4, 2=QAM16, 3=QAM32, 4=QAM64 */
- if (modulation > (ARRAY_SIZE(reg_mod_vals_tab[0].val) - 1)) {
- dbg("%s: modulation=%d not valid", __func__, modulation);
- goto err;
- }
-
- /* program registers according to modulation */
- for (i = 0; i < ARRAY_SIZE(reg_mod_vals_tab); i++) {
- ret = hd29l2_wr_reg(priv, reg_mod_vals_tab[i].reg,
- reg_mod_vals_tab[i].val[modulation]);
- if (ret)
- goto err;
- }
-
- /* read guard interval */
- ret = hd29l2_rd_reg_mask(priv, 0x81, &guard_interval, 0x03);
- if (ret)
- goto err;
-
- /* read carrier mode */
- ret = hd29l2_rd_reg_mask(priv, 0x81, &carrier, 0x04);
- if (ret)
- goto err;
-
- dbg("%s: modulation=%d guard_interval=%d carrier=%d",
- __func__, modulation, guard_interval, carrier);
-
- if ((carrier == HD29L2_CARRIER_MULTI) && (modulation == HD29L2_QAM64) &&
- (guard_interval == HD29L2_PN945)) {
- dbg("%s: C=3780 && QAM64 && PN945", __func__);
-
- ret = hd29l2_wr_reg(priv, 0x42, 0x33);
- if (ret)
- goto err;
-
- ret = hd29l2_wr_reg(priv, 0xdd, 0x01);
- if (ret)
- goto err;
- }
-
- usleep_range(10000, 20000);
-
- /* soft reset */
- ret = hd29l2_soft_reset(priv);
- if (ret)
- goto err;
-
- /* wait demod lock */
- for (i = 30; i; i--) {
- msleep(100);
-
- /* read lock bit */
- ret = hd29l2_rd_reg_mask(priv, 0x05, &tmp, 0x01);
- if (ret)
- goto err;
-
- if (tmp)
- break;
- }
-
- dbg("%s: loop=%d", __func__, i);
-
- if (i == 0)
- return DVBFE_ALGO_SEARCH_AGAIN;
-
- return DVBFE_ALGO_SEARCH_SUCCESS;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return DVBFE_ALGO_SEARCH_ERROR;
-}
-
-static int hd29l2_get_frontend_algo(struct dvb_frontend *fe)
-{
- return DVBFE_ALGO_CUSTOM;
-}
-
-static int hd29l2_get_frontend(struct dvb_frontend *fe)
-{
- int ret;
- struct hd29l2_priv *priv = fe->demodulator_priv;
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- u8 buf[3];
- u32 if_ctl;
- char *str_constellation, *str_code_rate, *str_constellation_code_rate,
- *str_guard_interval, *str_carrier, *str_guard_interval_carrier,
- *str_interleave, *str_interleave_;
-
- ret = hd29l2_rd_reg(priv, 0x7d, &buf[0]);
- if (ret)
- goto err;
-
- ret = hd29l2_rd_regs(priv, 0x81, &buf[1], 2);
- if (ret)
- goto err;
-
- /* constellation, 0x7d[2:0] */
- switch ((buf[0] >> 0) & 0x07) {
- case 0: /* QAM4NR */
- str_constellation = "QAM4NR";
- c->modulation = QAM_AUTO; /* FIXME */
- break;
- case 1: /* QAM4 */
- str_constellation = "QAM4";
- c->modulation = QPSK; /* FIXME */
- break;
- case 2:
- str_constellation = "QAM16";
- c->modulation = QAM_16;
- break;
- case 3:
- str_constellation = "QAM32";
- c->modulation = QAM_32;
- break;
- case 4:
- str_constellation = "QAM64";
- c->modulation = QAM_64;
- break;
- default:
- str_constellation = "?";
- }
-
- /* LDPC code rate, 0x7d[4:3] */
- switch ((buf[0] >> 3) & 0x03) {
- case 0: /* 0.4 */
- str_code_rate = "0.4";
- c->fec_inner = FEC_AUTO; /* FIXME */
- break;
- case 1: /* 0.6 */
- str_code_rate = "0.6";
- c->fec_inner = FEC_3_5;
- break;
- case 2: /* 0.8 */
- str_code_rate = "0.8";
- c->fec_inner = FEC_4_5;
- break;
- default:
- str_code_rate = "?";
- }
-
- /* constellation & code rate set, 0x7d[6] */
- switch ((buf[0] >> 6) & 0x01) {
- case 0:
- str_constellation_code_rate = "manual";
- break;
- case 1:
- str_constellation_code_rate = "auto";
- break;
- default:
- str_constellation_code_rate = "?";
- }
-
- /* frame header, 0x81[1:0] */
- switch ((buf[1] >> 0) & 0x03) {
- case 0: /* PN945 */
- str_guard_interval = "PN945";
- c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
- break;
- case 1: /* PN595 */
- str_guard_interval = "PN595";
- c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
- break;
- case 2: /* PN420 */
- str_guard_interval = "PN420";
- c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
- break;
- default:
- str_guard_interval = "?";
- }
-
- /* carrier, 0x81[2] */
- switch ((buf[1] >> 2) & 0x01) {
- case 0:
- str_carrier = "C=1";
- break;
- case 1:
- str_carrier = "C=3780";
- break;
- default:
- str_carrier = "?";
- }
-
- /* frame header & carrier set, 0x81[3] */
- switch ((buf[1] >> 3) & 0x01) {
- case 0:
- str_guard_interval_carrier = "manual";
- break;
- case 1:
- str_guard_interval_carrier = "auto";
- break;
- default:
- str_guard_interval_carrier = "?";
- }
-
- /* interleave, 0x82[0] */
- switch ((buf[2] >> 0) & 0x01) {
- case 0:
- str_interleave = "M=720";
- break;
- case 1:
- str_interleave = "M=240";
- break;
- default:
- str_interleave = "?";
- }
-
- /* interleave set, 0x82[1] */
- switch ((buf[2] >> 1) & 0x01) {
- case 0:
- str_interleave_ = "manual";
- break;
- case 1:
- str_interleave_ = "auto";
- break;
- default:
- str_interleave_ = "?";
- }
-
- /*
- * We can read out current detected NCO and use that value next
- * time instead of calculating new value from targed IF.
- * I think it will not effect receiver sensitivity but gaining lock
- * after tune could be easier...
- */
- ret = hd29l2_rd_regs(priv, 0xb1, &buf[0], 3);
- if (ret)
- goto err;
-
- if_ctl = (buf[0] << 16) | ((buf[1] - 7) << 8) | buf[2];
-
- dbg("%s: %s %s %s | %s %s %s | %s %s | NCO=%06x", __func__,
- str_constellation, str_code_rate, str_constellation_code_rate,
- str_guard_interval, str_carrier, str_guard_interval_carrier,
- str_interleave, str_interleave_, if_ctl);
-
- return 0;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static int hd29l2_init(struct dvb_frontend *fe)
-{
- int ret, i;
- struct hd29l2_priv *priv = fe->demodulator_priv;
- u8 tmp;
- static const struct reg_val tab[] = {
- { 0x3a, 0x06 },
- { 0x3b, 0x03 },
- { 0x3c, 0x04 },
- { 0xaf, 0x06 },
- { 0xb0, 0x1b },
- { 0x80, 0x64 },
- { 0x10, 0x38 },
- };
-
- dbg("%s:", __func__);
-
- /* reset demod */
- /* it is recommended to HW reset chip using RST_N pin */
- if (fe->callback) {
- ret = fe->callback(fe, DVB_FRONTEND_COMPONENT_DEMOD, 0, 0);
- if (ret)
- goto err;
-
- /* reprogramming needed because HW reset clears registers */
- priv->tuner_i2c_addr_programmed = false;
- }
-
- /* init */
- for (i = 0; i < ARRAY_SIZE(tab); i++) {
- ret = hd29l2_wr_reg(priv, tab[i].reg, tab[i].val);
- if (ret)
- goto err;
- }
-
- /* TS params */
- ret = hd29l2_rd_reg(priv, 0x36, &tmp);
- if (ret)
- goto err;
-
- tmp &= 0x1b;
- tmp |= priv->cfg.ts_mode;
- ret = hd29l2_wr_reg(priv, 0x36, tmp);
- if (ret)
- goto err;
-
- ret = hd29l2_rd_reg(priv, 0x31, &tmp);
- tmp &= 0xef;
-
- if (!(priv->cfg.ts_mode >> 7))
- /* set b4 for serial TS */
- tmp |= 0x10;
-
- ret = hd29l2_wr_reg(priv, 0x31, tmp);
- if (ret)
- goto err;
-
- return ret;
-err:
- dbg("%s: failed=%d", __func__, ret);
- return ret;
-}
-
-static void hd29l2_release(struct dvb_frontend *fe)
-{
- struct hd29l2_priv *priv = fe->demodulator_priv;
- kfree(priv);
-}
-
-static struct dvb_frontend_ops hd29l2_ops;
-
-struct dvb_frontend *hd29l2_attach(const struct hd29l2_config *config,
- struct i2c_adapter *i2c)
-{
- int ret;
- struct hd29l2_priv *priv = NULL;
- u8 tmp;
-
- /* allocate memory for the internal state */
- priv = kzalloc(sizeof(struct hd29l2_priv), GFP_KERNEL);
- if (priv == NULL)
- goto err;
-
- /* setup the state */
- priv->i2c = i2c;
- memcpy(&priv->cfg, config, sizeof(struct hd29l2_config));
-
-
- /* check if the demod is there */
- ret = hd29l2_rd_reg(priv, 0x00, &tmp);
- if (ret)
- goto err;
-
- /* create dvb_frontend */
- memcpy(&priv->fe.ops, &hd29l2_ops, sizeof(struct dvb_frontend_ops));
- priv->fe.demodulator_priv = priv;
-
- return &priv->fe;
-err:
- kfree(priv);
- return NULL;
-}
-EXPORT_SYMBOL(hd29l2_attach);
-
-static struct dvb_frontend_ops hd29l2_ops = {
- .delsys = { SYS_DVBT },
- .info = {
- .name = "HDIC HD29L2 DMB-TH",
- .frequency_min = 474000000,
- .frequency_max = 858000000,
- .frequency_stepsize = 10000,
- .caps = FE_CAN_FEC_AUTO |
- FE_CAN_QPSK |
- FE_CAN_QAM_16 |
- FE_CAN_QAM_32 |
- FE_CAN_QAM_64 |
- FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_BANDWIDTH_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_HIERARCHY_AUTO |
- FE_CAN_RECOVER
- },
-
- .release = hd29l2_release,
-
- .init = hd29l2_init,
-
- .get_frontend_algo = hd29l2_get_frontend_algo,
- .search = hd29l2_search,
- .get_frontend = hd29l2_get_frontend,
-
- .read_status = hd29l2_read_status,
- .read_snr = hd29l2_read_snr,
- .read_signal_strength = hd29l2_read_signal_strength,
- .read_ber = hd29l2_read_ber,
- .read_ucblocks = hd29l2_read_ucblocks,
-
- .i2c_gate_ctrl = hd29l2_i2c_gate_ctrl,
-};
-
-MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
-MODULE_DESCRIPTION("HDIC HD29L2 DMB-TH demodulator driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/hd29l2.h b/drivers/media/dvb/frontends/hd29l2.h
deleted file mode 100644
index a7a64431364..00000000000
--- a/drivers/media/dvb/frontends/hd29l2.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * HDIC HD29L2 DMB-TH demodulator driver
- *
- * Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
- *
- * Author: Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef HD29L2_H
-#define HD29L2_H
-
-#include <linux/dvb/frontend.h>
-
-struct hd29l2_config {
- /*
- * demodulator I2C address
- */
- u8 i2c_addr;
-
- /*
- * tuner I2C address
- * only needed when tuner is behind demod I2C-gate
- */
- u8 tuner_i2c_addr;
-
- /*
- * TS settings
- */
-#define HD29L2_TS_SERIAL 0x00
-#define HD29L2_TS_PARALLEL 0x80
-#define HD29L2_TS_CLK_NORMAL 0x40
-#define HD29L2_TS_CLK_INVERTED 0x00
-#define HD29L2_TS_CLK_GATED 0x20
-#define HD29L2_TS_CLK_FREE 0x00
- u8 ts_mode;
-};
-
-
-#if defined(CONFIG_DVB_HD29L2) || \
- (defined(CONFIG_DVB_HD29L2_MODULE) && defined(MODULE))
-extern struct dvb_frontend *hd29l2_attach(const struct hd29l2_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline struct dvb_frontend *hd29l2_attach(
-const struct hd29l2_config *config, struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif
-
-#endif /* HD29L2_H */
diff --git a/drivers/media/dvb/frontends/hd29l2_priv.h b/drivers/media/dvb/frontends/hd29l2_priv.h
deleted file mode 100644
index ba16dc3ec2b..00000000000
--- a/drivers/media/dvb/frontends/hd29l2_priv.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * HDIC HD29L2 DMB-TH demodulator driver
- *
- * Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
- *
- * Author: Antti Palosaari <crope@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef HD29L2_PRIV
-#define HD29L2_PRIV
-
-#include <linux/dvb/version.h>
-#include "dvb_frontend.h"
-#include "dvb_math.h"
-#include "hd29l2.h"
-
-#define LOG_PREFIX "hd29l2"
-
-#undef dbg
-#define dbg(f, arg...) \
- if (hd29l2_debug) \
- printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
-#undef err
-#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
-#undef info
-#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
-#undef warn
-#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
-
-#define HD29L2_XTAL 30400000 /* Hz */
-
-
-#define HD29L2_QAM4NR 0x00
-#define HD29L2_QAM4 0x01
-#define HD29L2_QAM16 0x02
-#define HD29L2_QAM32 0x03
-#define HD29L2_QAM64 0x04
-
-#define HD29L2_CODE_RATE_04 0x00
-#define HD29L2_CODE_RATE_06 0x08
-#define HD29L2_CODE_RATE_08 0x10
-
-#define HD29L2_PN945 0x00
-#define HD29L2_PN595 0x01
-#define HD29L2_PN420 0x02
-
-#define HD29L2_CARRIER_SINGLE 0x00
-#define HD29L2_CARRIER_MULTI 0x01
-
-#define HD29L2_INTERLEAVER_720 0x00
-#define HD29L2_INTERLEAVER_420 0x01
-
-struct reg_val {
- u8 reg;
- u8 val;
-};
-
-struct reg_mod_vals {
- u8 reg;
- u8 val[5];
-};
-
-struct hd29l2_priv {
- struct i2c_adapter *i2c;
- struct dvb_frontend fe;
- struct hd29l2_config cfg;
- u8 tuner_i2c_addr_programmed:1;
-
- fe_status_t fe_status;
-};
-
-static const struct reg_mod_vals reg_mod_vals_tab[] = {
- /* REG, QAM4NR, QAM4,QAM16,QAM32,QAM64 */
- { 0x01, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
- { 0x02, { 0x07, 0x07, 0x07, 0x07, 0x07 } },
- { 0x03, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
- { 0x04, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x05, { 0x61, 0x60, 0x60, 0x61, 0x60 } },
- { 0x06, { 0xff, 0xff, 0xff, 0xff, 0xff } },
- { 0x07, { 0xff, 0xff, 0xff, 0xff, 0xff } },
- { 0x08, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x09, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x0a, { 0x15, 0x15, 0x03, 0x03, 0x03 } },
- { 0x0d, { 0x78, 0x78, 0x88, 0x78, 0x78 } },
- { 0x0e, { 0xa0, 0x90, 0xa0, 0xa0, 0xa0 } },
- { 0x0f, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x10, { 0xa0, 0xa0, 0x58, 0x38, 0x38 } },
- { 0x11, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x12, { 0x5a, 0x5a, 0x5a, 0x5a, 0x5a } },
- { 0x13, { 0xa2, 0xa2, 0xa2, 0xa2, 0xa2 } },
- { 0x17, { 0x40, 0x40, 0x40, 0x40, 0x40 } },
- { 0x18, { 0x21, 0x21, 0x42, 0x52, 0x42 } },
- { 0x19, { 0x21, 0x21, 0x62, 0x72, 0x62 } },
- { 0x1a, { 0x32, 0x43, 0xa9, 0xb9, 0xa9 } },
- { 0x1b, { 0x32, 0x43, 0xb9, 0xd8, 0xb9 } },
- { 0x1c, { 0x02, 0x02, 0x03, 0x02, 0x03 } },
- { 0x1d, { 0x0c, 0x0c, 0x01, 0x02, 0x02 } },
- { 0x1e, { 0x02, 0x02, 0x02, 0x01, 0x02 } },
- { 0x1f, { 0x02, 0x02, 0x01, 0x02, 0x04 } },
- { 0x20, { 0x01, 0x02, 0x01, 0x01, 0x01 } },
- { 0x21, { 0x08, 0x08, 0x0a, 0x0a, 0x0a } },
- { 0x22, { 0x06, 0x06, 0x04, 0x05, 0x05 } },
- { 0x23, { 0x06, 0x06, 0x05, 0x03, 0x05 } },
- { 0x24, { 0x08, 0x08, 0x05, 0x07, 0x07 } },
- { 0x25, { 0x16, 0x10, 0x10, 0x0a, 0x10 } },
- { 0x26, { 0x14, 0x14, 0x04, 0x04, 0x04 } },
- { 0x27, { 0x58, 0x58, 0x58, 0x5c, 0x58 } },
- { 0x28, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
- { 0x29, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
- { 0x2a, { 0x08, 0x0a, 0x08, 0x08, 0x08 } },
- { 0x2b, { 0x08, 0x08, 0x08, 0x08, 0x08 } },
- { 0x2c, { 0x06, 0x06, 0x06, 0x06, 0x06 } },
- { 0x2d, { 0x05, 0x06, 0x06, 0x06, 0x06 } },
- { 0x2e, { 0x21, 0x21, 0x21, 0x21, 0x21 } },
- { 0x2f, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x30, { 0x14, 0x14, 0x14, 0x14, 0x14 } },
- { 0x33, { 0xb7, 0xb7, 0xb7, 0xb7, 0xb7 } },
- { 0x34, { 0x81, 0x81, 0x81, 0x81, 0x81 } },
- { 0x35, { 0x80, 0x80, 0x80, 0x80, 0x80 } },
- { 0x37, { 0x70, 0x70, 0x70, 0x70, 0x70 } },
- { 0x38, { 0x04, 0x04, 0x02, 0x02, 0x02 } },
- { 0x39, { 0x07, 0x07, 0x05, 0x05, 0x05 } },
- { 0x3a, { 0x06, 0x06, 0x06, 0x06, 0x06 } },
- { 0x3b, { 0x03, 0x03, 0x03, 0x03, 0x03 } },
- { 0x3c, { 0x07, 0x06, 0x04, 0x04, 0x04 } },
- { 0x3d, { 0xf0, 0xf0, 0xf0, 0xf0, 0x80 } },
- { 0x3e, { 0x60, 0x60, 0x60, 0x60, 0xff } },
- { 0x3f, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x40, { 0x5b, 0x5b, 0x5b, 0x57, 0x50 } },
- { 0x41, { 0x30, 0x30, 0x30, 0x30, 0x18 } },
- { 0x42, { 0x20, 0x20, 0x20, 0x00, 0x30 } },
- { 0x43, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x44, { 0x3f, 0x3f, 0x3f, 0x3f, 0x3f } },
- { 0x45, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x46, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
- { 0x47, { 0x00, 0x00, 0x95, 0x00, 0x95 } },
- { 0x48, { 0xc0, 0xc0, 0xc0, 0xc0, 0xc0 } },
- { 0x49, { 0xc0, 0xc0, 0xc0, 0xc0, 0xc0 } },
- { 0x4a, { 0x40, 0x40, 0x33, 0x11, 0x11 } },
- { 0x4b, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
- { 0x4c, { 0x40, 0x40, 0x99, 0x11, 0x11 } },
- { 0x4d, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
- { 0x4e, { 0x40, 0x40, 0x66, 0x77, 0x77 } },
- { 0x4f, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
- { 0x50, { 0x40, 0x40, 0x88, 0x33, 0x11 } },
- { 0x51, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
- { 0x52, { 0x40, 0x40, 0x88, 0x02, 0x02 } },
- { 0x53, { 0x40, 0x40, 0x00, 0x02, 0x02 } },
- { 0x54, { 0x00, 0x00, 0x88, 0x33, 0x33 } },
- { 0x55, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
- { 0x56, { 0x00, 0x00, 0x00, 0x0b, 0x00 } },
- { 0x57, { 0x40, 0x40, 0x0a, 0x0b, 0x0a } },
- { 0x58, { 0xaa, 0x00, 0x00, 0x00, 0x00 } },
- { 0x59, { 0x7a, 0x40, 0x02, 0x02, 0x02 } },
- { 0x5a, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
- { 0x5b, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
- { 0x5c, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
- { 0x5d, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
- { 0x5e, { 0xc0, 0xc0, 0xc0, 0xff, 0xc0 } },
- { 0x5f, { 0xc0, 0xc0, 0xc0, 0xff, 0xc0 } },
- { 0x60, { 0x40, 0x40, 0x00, 0x30, 0x30 } },
- { 0x61, { 0x40, 0x40, 0x10, 0x30, 0x30 } },
- { 0x62, { 0x40, 0x40, 0x00, 0x30, 0x30 } },
- { 0x63, { 0x40, 0x40, 0x05, 0x30, 0x30 } },
- { 0x64, { 0x40, 0x40, 0x06, 0x00, 0x30 } },
- { 0x65, { 0x40, 0x40, 0x06, 0x08, 0x30 } },
- { 0x66, { 0x40, 0x40, 0x00, 0x00, 0x20 } },
- { 0x67, { 0x40, 0x40, 0x01, 0x04, 0x20 } },
- { 0x68, { 0x00, 0x00, 0x30, 0x00, 0x20 } },
- { 0x69, { 0xa0, 0xa0, 0x00, 0x08, 0x20 } },
- { 0x6a, { 0x00, 0x00, 0x30, 0x00, 0x25 } },
- { 0x6b, { 0xa0, 0xa0, 0x00, 0x06, 0x25 } },
- { 0x6c, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x6d, { 0xa0, 0x60, 0x0c, 0x03, 0x0c } },
- { 0x6e, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x6f, { 0xa0, 0x60, 0x04, 0x01, 0x04 } },
- { 0x70, { 0x58, 0x58, 0xaa, 0xaa, 0xaa } },
- { 0x71, { 0x58, 0x58, 0xaa, 0xaa, 0xaa } },
- { 0x72, { 0x58, 0x58, 0xff, 0xff, 0xff } },
- { 0x73, { 0x58, 0x58, 0xff, 0xff, 0xff } },
- { 0x74, { 0x06, 0x06, 0x09, 0x05, 0x05 } },
- { 0x75, { 0x06, 0x06, 0x0a, 0x10, 0x10 } },
- { 0x76, { 0x10, 0x10, 0x06, 0x0a, 0x0a } },
- { 0x77, { 0x12, 0x18, 0x28, 0x10, 0x28 } },
- { 0x78, { 0xf8, 0xf8, 0xf8, 0xf8, 0xf8 } },
- { 0x79, { 0x15, 0x15, 0x03, 0x03, 0x03 } },
- { 0x7a, { 0x02, 0x02, 0x01, 0x04, 0x03 } },
- { 0x7b, { 0x01, 0x02, 0x03, 0x03, 0x03 } },
- { 0x7c, { 0x28, 0x28, 0x28, 0x28, 0x28 } },
- { 0x7f, { 0x25, 0x92, 0x5f, 0x17, 0x2d } },
- { 0x80, { 0x64, 0x64, 0x64, 0x74, 0x64 } },
- { 0x83, { 0x06, 0x03, 0x04, 0x04, 0x04 } },
- { 0x84, { 0xff, 0xff, 0xff, 0xff, 0xff } },
- { 0x85, { 0x05, 0x05, 0x05, 0x05, 0x05 } },
- { 0x86, { 0x00, 0x00, 0x11, 0x11, 0x11 } },
- { 0x87, { 0x03, 0x03, 0x03, 0x03, 0x03 } },
- { 0x88, { 0x09, 0x09, 0x09, 0x09, 0x09 } },
- { 0x89, { 0x20, 0x20, 0x30, 0x20, 0x20 } },
- { 0x8a, { 0x03, 0x03, 0x02, 0x03, 0x02 } },
- { 0x8b, { 0x00, 0x07, 0x09, 0x00, 0x09 } },
- { 0x8c, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x8d, { 0x4f, 0x4f, 0x4f, 0x3f, 0x4f } },
- { 0x8e, { 0xf0, 0xf0, 0x60, 0xf0, 0xa0 } },
- { 0x8f, { 0xe8, 0xe8, 0xe8, 0xe8, 0xe8 } },
- { 0x90, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
- { 0x91, { 0x40, 0x40, 0x70, 0x70, 0x10 } },
- { 0x92, { 0x00, 0x00, 0x00, 0x00, 0x04 } },
- { 0x93, { 0x60, 0x60, 0x60, 0x60, 0x60 } },
- { 0x94, { 0x00, 0x00, 0x00, 0x00, 0x03 } },
- { 0x95, { 0x09, 0x09, 0x47, 0x47, 0x47 } },
- { 0x96, { 0x80, 0xa0, 0xa0, 0x40, 0xa0 } },
- { 0x97, { 0x60, 0x60, 0x60, 0x60, 0x60 } },
- { 0x98, { 0x50, 0x50, 0x50, 0x30, 0x50 } },
- { 0x99, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
- { 0x9a, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0x9b, { 0x40, 0x40, 0x40, 0x30, 0x40 } },
- { 0x9c, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xa0, { 0xf0, 0xf0, 0xf0, 0xf0, 0xf0 } },
- { 0xa1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xa2, { 0x30, 0x30, 0x00, 0x30, 0x00 } },
- { 0xa3, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xa4, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xa5, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xa6, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xa7, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xa8, { 0x77, 0x77, 0x77, 0x77, 0x77 } },
- { 0xa9, { 0x02, 0x02, 0x02, 0x02, 0x02 } },
- { 0xaa, { 0x40, 0x40, 0x40, 0x40, 0x40 } },
- { 0xac, { 0x1f, 0x1f, 0x1f, 0x1f, 0x1f } },
- { 0xad, { 0x14, 0x14, 0x14, 0x14, 0x14 } },
- { 0xae, { 0x78, 0x78, 0x78, 0x78, 0x78 } },
- { 0xaf, { 0x06, 0x06, 0x06, 0x06, 0x07 } },
- { 0xb0, { 0x1b, 0x1b, 0x1b, 0x19, 0x1b } },
- { 0xb1, { 0x18, 0x17, 0x17, 0x18, 0x17 } },
- { 0xb2, { 0x35, 0x82, 0x82, 0x38, 0x82 } },
- { 0xb3, { 0xb6, 0xce, 0xc7, 0x5c, 0xb0 } },
- { 0xb4, { 0x3f, 0x3e, 0x3e, 0x3f, 0x3e } },
- { 0xb5, { 0x70, 0x58, 0x50, 0x68, 0x50 } },
- { 0xb6, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xb7, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xb8, { 0x03, 0x03, 0x01, 0x01, 0x01 } },
- { 0xb9, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xba, { 0x06, 0x06, 0x0a, 0x05, 0x0a } },
- { 0xbb, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xbc, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xbd, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xbe, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xbf, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xc0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xc1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xc2, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xc3, { 0x00, 0x00, 0x88, 0x66, 0x88 } },
- { 0xc4, { 0x10, 0x10, 0x00, 0x00, 0x00 } },
- { 0xc5, { 0x00, 0x00, 0x44, 0x60, 0x44 } },
- { 0xc6, { 0x10, 0x0a, 0x00, 0x00, 0x00 } },
- { 0xc7, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xc8, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xc9, { 0x90, 0x04, 0x00, 0x00, 0x00 } },
- { 0xca, { 0x90, 0x08, 0x01, 0x01, 0x01 } },
- { 0xcb, { 0xa0, 0x04, 0x00, 0x44, 0x00 } },
- { 0xcc, { 0xa0, 0x10, 0x03, 0x00, 0x03 } },
- { 0xcd, { 0x06, 0x06, 0x06, 0x05, 0x06 } },
- { 0xce, { 0x05, 0x05, 0x01, 0x01, 0x01 } },
- { 0xcf, { 0x40, 0x20, 0x18, 0x18, 0x18 } },
- { 0xd0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xd1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xd2, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xd3, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xd4, { 0x05, 0x05, 0x05, 0x05, 0x05 } },
- { 0xd5, { 0x05, 0x05, 0x05, 0x03, 0x05 } },
- { 0xd6, { 0xac, 0x22, 0xca, 0x8f, 0xca } },
- { 0xd7, { 0x20, 0x20, 0x20, 0x20, 0x20 } },
- { 0xd8, { 0x01, 0x01, 0x01, 0x01, 0x01 } },
- { 0xd9, { 0x00, 0x00, 0x0f, 0x00, 0x0f } },
- { 0xda, { 0x00, 0xff, 0xff, 0x0e, 0xff } },
- { 0xdb, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
- { 0xdc, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
- { 0xdd, { 0x05, 0x05, 0x05, 0x05, 0x05 } },
- { 0xde, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
- { 0xdf, { 0x42, 0x42, 0x44, 0x44, 0x04 } },
- { 0xe0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xe1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xe2, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xe3, { 0x00, 0x00, 0x26, 0x06, 0x26 } },
- { 0xe4, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xe5, { 0x01, 0x0a, 0x01, 0x01, 0x01 } },
- { 0xe6, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xe7, { 0x08, 0x08, 0x08, 0x08, 0x08 } },
- { 0xe8, { 0x63, 0x63, 0x63, 0x63, 0x63 } },
- { 0xe9, { 0x59, 0x59, 0x59, 0x59, 0x59 } },
- { 0xea, { 0x80, 0x80, 0x20, 0x80, 0x80 } },
- { 0xeb, { 0x37, 0x37, 0x78, 0x37, 0x77 } },
- { 0xec, { 0x1f, 0x1f, 0x25, 0x25, 0x25 } },
- { 0xed, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
- { 0xee, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
- { 0xef, { 0x70, 0x70, 0x58, 0x38, 0x58 } },
- { 0xf0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
-};
-
-#endif /* HD29L2_PRIV */
diff --git a/drivers/media/dvb/frontends/isl6405.c b/drivers/media/dvb/frontends/isl6405.c
deleted file mode 100644
index 33d33f4d886..00000000000
--- a/drivers/media/dvb/frontends/isl6405.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * isl6405.c - driver for dual lnb supply and control ic ISL6405
- *
- * Copyright (C) 2008 Hartmut Hackmann
- * Copyright (C) 2006 Oliver Endriss
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- *
- *
- * the project's page is at http://www.linuxtv.org
- */
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-
-#include "dvb_frontend.h"
-#include "isl6405.h"
-
-struct isl6405 {
- u8 config;
- u8 override_or;
- u8 override_and;
- struct i2c_adapter *i2c;
- u8 i2c_addr;
-};
-
-static int isl6405_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
-{
- struct isl6405 *isl6405 = (struct isl6405 *) fe->sec_priv;
- struct i2c_msg msg = { .addr = isl6405->i2c_addr, .flags = 0,
- .buf = &isl6405->config,
- .len = sizeof(isl6405->config) };
-
- if (isl6405->override_or & 0x80) {
- isl6405->config &= ~(ISL6405_VSEL2 | ISL6405_EN2);
- switch (voltage) {
- case SEC_VOLTAGE_OFF:
- break;
- case SEC_VOLTAGE_13:
- isl6405->config |= ISL6405_EN2;
- break;
- case SEC_VOLTAGE_18:
- isl6405->config |= (ISL6405_EN2 | ISL6405_VSEL2);
- break;
- default:
- return -EINVAL;
- }
- } else {
- isl6405->config &= ~(ISL6405_VSEL1 | ISL6405_EN1);
- switch (voltage) {
- case SEC_VOLTAGE_OFF:
- break;
- case SEC_VOLTAGE_13:
- isl6405->config |= ISL6405_EN1;
- break;
- case SEC_VOLTAGE_18:
- isl6405->config |= (ISL6405_EN1 | ISL6405_VSEL1);
- break;
- default:
- return -EINVAL;
- };
- }
- isl6405->config |= isl6405->override_or;
- isl6405->config &= isl6405->override_and;
-
- return (i2c_transfer(isl6405->i2c, &msg, 1) == 1) ? 0 : -EIO;
-}
-
-static int isl6405_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
-{
- struct isl6405 *isl6405 = (struct isl6405 *) fe->sec_priv;
- struct i2c_msg msg = { .addr = isl6405->i2c_addr, .flags = 0,
- .buf = &isl6405->config,
- .len = sizeof(isl6405->config) };
-
- if (isl6405->override_or & 0x80) {
- if (arg)
- isl6405->config |= ISL6405_LLC2;
- else
- isl6405->config &= ~ISL6405_LLC2;
- } else {
- if (arg)
- isl6405->config |= ISL6405_LLC1;
- else
- isl6405->config &= ~ISL6405_LLC1;
- }
- isl6405->config |= isl6405->override_or;
- isl6405->config &= isl6405->override_and;
-
- return (i2c_transfer(isl6405->i2c, &msg, 1) == 1) ? 0 : -EIO;
-}
-
-static void isl6405_release(struct dvb_frontend *fe)
-{
- /* power off */
- isl6405_set_voltage(fe, SEC_VOLTAGE_OFF);
-
- /* free */
- kfree(fe->sec_priv);
- fe->sec_priv = NULL;
-}
-
-struct dvb_frontend *isl6405_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c,
- u8 i2c_addr, u8 override_set, u8 override_clear)
-{
- struct isl6405 *isl6405 = kmalloc(sizeof(struct isl6405), GFP_KERNEL);
- if (!isl6405)
- return NULL;
-
- /* default configuration */
- if (override_set & 0x80)
- isl6405->config = ISL6405_ISEL2;
- else
- isl6405->config = ISL6405_ISEL1;
- isl6405->i2c = i2c;
- isl6405->i2c_addr = i2c_addr;
- fe->sec_priv = isl6405;
-
- /* bits which should be forced to '1' */
- isl6405->override_or = override_set;
-
- /* bits which should be forced to '0' */
- isl6405->override_and = ~override_clear;
-
- /* detect if it is present or not */
- if (isl6405_set_voltage(fe, SEC_VOLTAGE_OFF)) {
- kfree(isl6405);
- fe->sec_priv = NULL;
- return NULL;
- }
-
- /* install release callback */
- fe->ops.release_sec = isl6405_release;
-
- /* override frontend ops */
- fe->ops.set_voltage = isl6405_set_voltage;
- fe->ops.enable_high_lnb_voltage = isl6405_enable_high_lnb_voltage;
-
- return fe;
-}
-EXPORT_SYMBOL(isl6405_attach);
-
-MODULE_DESCRIPTION("Driver for lnb supply and control ic isl6405");
-MODULE_AUTHOR("Hartmut Hackmann & Oliver Endriss");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/isl6405.h b/drivers/media/dvb/frontends/isl6405.h
deleted file mode 100644
index 1c793d37576..00000000000
--- a/drivers/media/dvb/frontends/isl6405.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * isl6405.h - driver for dual lnb supply and control ic ISL6405
- *
- * Copyright (C) 2008 Hartmut Hackmann
- * Copyright (C) 2006 Oliver Endriss
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- *
- *
- * the project's page is at http://www.linuxtv.org
- */
-
-#ifndef _ISL6405_H
-#define _ISL6405_H
-
-#include <linux/dvb/frontend.h>
-
-/* system register bits */
-
-/* this bit selects register (control) 1 or 2
- note that the bit maps are different */
-
-#define ISL6405_SR 0x80
-
-/* SR = 0 */
-#define ISL6405_OLF1 0x01
-#define ISL6405_EN1 0x02
-#define ISL6405_VSEL1 0x04
-#define ISL6405_LLC1 0x08
-#define ISL6405_ENT1 0x10
-#define ISL6405_ISEL1 0x20
-#define ISL6405_DCL 0x40
-
-/* SR = 1 */
-#define ISL6405_OLF2 0x01
-#define ISL6405_OTF 0x02
-#define ISL6405_EN2 0x04
-#define ISL6405_VSEL2 0x08
-#define ISL6405_LLC2 0x10
-#define ISL6405_ENT2 0x20
-#define ISL6405_ISEL2 0x40
-
-#if defined(CONFIG_DVB_ISL6405) || (defined(CONFIG_DVB_ISL6405_MODULE) && defined(MODULE))
-/* override_set and override_clear control which system register bits (above)
- * to always set & clear
- */
-extern struct dvb_frontend *isl6405_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c,
- u8 i2c_addr, u8 override_set, u8 override_clear);
-#else
-static inline struct dvb_frontend *isl6405_attach(struct dvb_frontend *fe,
- struct i2c_adapter *i2c, u8 i2c_addr,
- u8 override_set, u8 override_clear)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif /* CONFIG_DVB_ISL6405 */
-
-#endif
diff --git a/drivers/media/dvb/frontends/isl6421.c b/drivers/media/dvb/frontends/isl6421.c
deleted file mode 100644
index 684c8ec166c..00000000000
--- a/drivers/media/dvb/frontends/isl6421.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * isl6421.h - driver for lnb supply and control ic ISL6421
- *
- * Copyright (C) 2006 Andrew de Quincey
- * Copyright (C) 2006 Oliver Endriss
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- *
- *
- * the project's page is at http://www.linuxtv.org
- */
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-
-#include "dvb_frontend.h"
-#include "isl6421.h"
-
-struct isl6421 {
- u8 config;
- u8 override_or;
- u8 override_and;
- struct i2c_adapter *i2c;
- u8 i2c_addr;
-};
-
-static int isl6421_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
-{
- struct isl6421 *isl6421 = (struct isl6421 *) fe->sec_priv;
- struct i2c_msg msg = { .addr = isl6421->i2c_addr, .flags = 0,
- .buf = &isl6421->config,
- .len = sizeof(isl6421->config) };
-
- isl6421->config &= ~(ISL6421_VSEL1 | ISL6421_EN1);
-
- switch(voltage) {
- case SEC_VOLTAGE_OFF:
- break;
- case SEC_VOLTAGE_13:
- isl6421->config |= ISL6421_EN1;
- break;
- case SEC_VOLTAGE_18:
- isl6421->config |= (ISL6421_EN1 | ISL6421_VSEL1);
- break;
- default:
- return -EINVAL;
- };
-
- isl6421->config |= isl6421->override_or;
- isl6421->config &= isl6421->override_and;
-
- return (i2c_transfer(isl6421->i2c, &msg, 1) == 1) ? 0 : -EIO;
-}
-
-static int isl6421_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
-{
- struct isl6421 *isl6421 = (struct isl6421 *) fe->sec_priv;
- struct i2c_msg msg = { .addr = isl6421->i2c_addr, .flags = 0,
- .buf = &isl6421->config,
- .len = sizeof(isl6421->config) };
-
- if (arg)
- isl6421->config |= ISL6421_LLC1;
- else
- isl6421->config &= ~ISL6421_LLC1;
-
- isl6421->config |= isl6421->override_or;
- isl6421->config &= isl6421->override_and;
-
- return (i2c_transfer(isl6421->i2c, &msg, 1) == 1) ? 0 : -EIO;
-}
-
-static void isl6421_release(struct dvb_frontend *fe)
-{
- /* power off */
- isl6421_set_voltage(fe, SEC_VOLTAGE_OFF);
-
- /* free */
- kfree(fe->sec_priv);
- fe->sec_priv = NULL;
-}
-
-struct dvb_frontend *isl6421_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, u8 i2c_addr,
- u8 override_set, u8 override_clear)
-{
- struct isl6421 *isl6421 = kmalloc(sizeof(struct isl6421), GFP_KERNEL);
- if (!isl6421)
- return NULL;
-
- /* default configuration */
- isl6421->config = ISL6421_ISEL1;
- isl6421->i2c = i2c;
- isl6421->i2c_addr = i2c_addr;
- fe->sec_priv = isl6421;
-
- /* bits which should be forced to '1' */
- isl6421->override_or = override_set;
-
- /* bits which should be forced to '0' */
- isl6421->override_and = ~override_clear;
-
- /* detect if it is present or not */
- if (isl6421_set_voltage(fe, SEC_VOLTAGE_OFF)) {
- kfree(isl6421);
- fe->sec_priv = NULL;
- return NULL;
- }
-
- /* install release callback */
- fe->ops.release_sec = isl6421_release;
-
- /* override frontend ops */
- fe->ops.set_voltage = isl6421_set_voltage;
- fe->ops.enable_high_lnb_voltage = isl6421_enable_high_lnb_voltage;
-
- return fe;
-}
-EXPORT_SYMBOL(isl6421_attach);
-
-MODULE_DESCRIPTION("Driver for lnb supply and control ic isl6421");
-MODULE_AUTHOR("Andrew de Quincey & Oliver Endriss");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/isl6421.h b/drivers/media/dvb/frontends/isl6421.h
deleted file mode 100644
index 47e4518a042..00000000000
--- a/drivers/media/dvb/frontends/isl6421.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * isl6421.h - driver for lnb supply and control ic ISL6421
- *
- * Copyright (C) 2006 Andrew de Quincey
- * Copyright (C) 2006 Oliver Endriss
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
- *
- *
- * the project's page is at http://www.linuxtv.org
- */
-
-#ifndef _ISL6421_H
-#define _ISL6421_H
-
-#include <linux/dvb/frontend.h>
-
-/* system register bits */
-#define ISL6421_OLF1 0x01
-#define ISL6421_EN1 0x02
-#define ISL6421_VSEL1 0x04
-#define ISL6421_LLC1 0x08
-#define ISL6421_ENT1 0x10
-#define ISL6421_ISEL1 0x20
-#define ISL6421_DCL 0x40
-
-#if defined(CONFIG_DVB_ISL6421) || (defined(CONFIG_DVB_ISL6421_MODULE) && defined(MODULE))
-/* override_set and override_clear control which system register bits (above) to always set & clear */
-extern struct dvb_frontend *isl6421_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, u8 i2c_addr,
- u8 override_set, u8 override_clear);
-#else
-static inline struct dvb_frontend *isl6421_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, u8 i2c_addr,
- u8 override_set, u8 override_clear)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif // CONFIG_DVB_ISL6421
-
-#endif
diff --git a/drivers/media/dvb/frontends/isl6423.c b/drivers/media/dvb/frontends/isl6423.c
deleted file mode 100644
index dca5bebfeeb..00000000000
--- a/drivers/media/dvb/frontends/isl6423.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- Intersil ISL6423 SEC and LNB Power supply controller
-
- Copyright (C) Manu Abraham <abraham.manu@gmail.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-
-#include "dvb_frontend.h"
-#include "isl6423.h"
-
-static unsigned int verbose;
-module_param(verbose, int, 0644);
-MODULE_PARM_DESC(verbose, "Set Verbosity level");
-
-#define FE_ERROR 0
-#define FE_NOTICE 1
-#define FE_INFO 2
-#define FE_DEBUG 3
-#define FE_DEBUGREG 4
-
-#define dprintk(__y, __z, format, arg...) do { \
- if (__z) { \
- if ((verbose > FE_ERROR) && (verbose > __y)) \
- printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
- else if ((verbose > FE_NOTICE) && (verbose > __y)) \
- printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
- else if ((verbose > FE_INFO) && (verbose > __y)) \
- printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
- else if ((verbose > FE_DEBUG) && (verbose > __y)) \
- printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
- } else { \
- if (verbose > __y) \
- printk(format, ##arg); \
- } \
-} while (0)
-
-struct isl6423_dev {
- const struct isl6423_config *config;
- struct i2c_adapter *i2c;
-
- u8 reg_3;
- u8 reg_4;
-
- unsigned int verbose;
-};
-
-static int isl6423_write(struct isl6423_dev *isl6423, u8 reg)
-{
- struct i2c_adapter *i2c = isl6423->i2c;
- u8 addr = isl6423->config->addr;
- int err = 0;
-
- struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = &reg, .len = 1 };
-
- dprintk(FE_DEBUG, 1, "write reg %02X", reg);
- err = i2c_transfer(i2c, &msg, 1);
- if (err < 0)
- goto exit;
- return 0;
-
-exit:
- dprintk(FE_ERROR, 1, "I/O error <%d>", err);
- return err;
-}
-
-static int isl6423_set_modulation(struct dvb_frontend *fe)
-{
- struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
- const struct isl6423_config *config = isl6423->config;
- int err = 0;
- u8 reg_2 = 0;
-
- reg_2 = 0x01 << 5;
-
- if (config->mod_extern)
- reg_2 |= (1 << 3);
- else
- reg_2 |= (1 << 4);
-
- err = isl6423_write(isl6423, reg_2);
- if (err < 0)
- goto exit;
- return 0;
-
-exit:
- dprintk(FE_ERROR, 1, "I/O error <%d>", err);
- return err;
-}
-
-static int isl6423_voltage_boost(struct dvb_frontend *fe, long arg)
-{
- struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
- u8 reg_3 = isl6423->reg_3;
- u8 reg_4 = isl6423->reg_4;
- int err = 0;
-
- if (arg) {
- /* EN = 1, VSPEN = 1, VBOT = 1 */
- reg_4 |= (1 << 4);
- reg_4 |= 0x1;
- reg_3 |= (1 << 3);
- } else {
- /* EN = 1, VSPEN = 1, VBOT = 0 */
- reg_4 |= (1 << 4);
- reg_4 &= ~0x1;
- reg_3 |= (1 << 3);
- }
- err = isl6423_write(isl6423, reg_3);
- if (err < 0)
- goto exit;
-
- err = isl6423_write(isl6423, reg_4);
- if (err < 0)
- goto exit;
-
- isl6423->reg_3 = reg_3;
- isl6423->reg_4 = reg_4;
-
- return 0;
-exit:
- dprintk(FE_ERROR, 1, "I/O error <%d>", err);
- return err;
-}
-
-
-static int isl6423_set_voltage(struct dvb_frontend *fe,
- enum fe_sec_voltage voltage)
-{
- struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
- u8 reg_3 = isl6423->reg_3;
- u8 reg_4 = isl6423->reg_4;
- int err = 0;
-
- switch (voltage) {
- case SEC_VOLTAGE_OFF:
- /* EN = 0 */
- reg_4 &= ~(1 << 4);
- break;
-
- case SEC_VOLTAGE_13:
- /* EN = 1, VSPEN = 1, VTOP = 0, VBOT = 0 */
- reg_4 |= (1 << 4);
- reg_4 &= ~0x3;
- reg_3 |= (1 << 3);
- break;
-
- case SEC_VOLTAGE_18:
- /* EN = 1, VSPEN = 1, VTOP = 1, VBOT = 0 */
- reg_4 |= (1 << 4);
- reg_4 |= 0x2;
- reg_4 &= ~0x1;
- reg_3 |= (1 << 3);
- break;
-
- default:
- break;
- }
- err = isl6423_write(isl6423, reg_3);
- if (err < 0)
- goto exit;
-
- err = isl6423_write(isl6423, reg_4);
- if (err < 0)
- goto exit;
-
- isl6423->reg_3 = reg_3;
- isl6423->reg_4 = reg_4;
-
- return 0;
-exit:
- dprintk(FE_ERROR, 1, "I/O error <%d>", err);
- return err;
-}
-
-static int isl6423_set_current(struct dvb_frontend *fe)
-{
- struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
- u8 reg_3 = isl6423->reg_3;
- const struct isl6423_config *config = isl6423->config;
- int err = 0;
-
- switch (config->current_max) {
- case SEC_CURRENT_275m:
- /* 275mA */
- /* ISELH = 0, ISELL = 0 */
- reg_3 &= ~0x3;
- break;
-
- case SEC_CURRENT_515m:
- /* 515mA */
- /* ISELH = 0, ISELL = 1 */
- reg_3 &= ~0x2;
- reg_3 |= 0x1;
- break;
-
- case SEC_CURRENT_635m:
- /* 635mA */
- /* ISELH = 1, ISELL = 0 */
- reg_3 &= ~0x1;
- reg_3 |= 0x2;
- break;
-
- case SEC_CURRENT_800m:
- /* 800mA */
- /* ISELH = 1, ISELL = 1 */
- reg_3 |= 0x3;
- break;
- }
-
- err = isl6423_write(isl6423, reg_3);
- if (err < 0)
- goto exit;
-
- switch (config->curlim) {
- case SEC_CURRENT_LIM_ON:
- /* DCL = 0 */
- reg_3 &= ~0x10;
- break;
-
- case SEC_CURRENT_LIM_OFF:
- /* DCL = 1 */
- reg_3 |= 0x10;
- break;
- }
-
- err = isl6423_write(isl6423, reg_3);
- if (err < 0)
- goto exit;
-
- isl6423->reg_3 = reg_3;
-
- return 0;
-exit:
- dprintk(FE_ERROR, 1, "I/O error <%d>", err);
- return err;
-}
-
-static void isl6423_release(struct dvb_frontend *fe)
-{
- isl6423_set_voltage(fe, SEC_VOLTAGE_OFF);
-
- kfree(fe->sec_priv);
- fe->sec_priv = NULL;
-}
-
-struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
- struct i2c_adapter *i2c,
- const struct isl6423_config *config)
-{
- struct isl6423_dev *isl6423;
-
- isl6423 = kzalloc(sizeof(struct isl6423_dev), GFP_KERNEL);
- if (!isl6423)
- return NULL;
-
- isl6423->config = config;
- isl6423->i2c = i2c;
- fe->sec_priv = isl6423;
-
- /* SR3H = 0, SR3M = 1, SR3L = 0 */
- isl6423->reg_3 = 0x02 << 5;
- /* SR4H = 0, SR4M = 1, SR4L = 1 */
- isl6423->reg_4 = 0x03 << 5;
-
- if (isl6423_set_current(fe))
- goto exit;
-
- if (isl6423_set_modulation(fe))
- goto exit;
-
- fe->ops.release_sec = isl6423_release;
- fe->ops.set_voltage = isl6423_set_voltage;
- fe->ops.enable_high_lnb_voltage = isl6423_voltage_boost;
- isl6423->verbose = verbose;
-
- return fe;
-
-exit:
- kfree(isl6423);
- fe->sec_priv = NULL;
- return NULL;
-}
-EXPORT_SYMBOL(isl6423_attach);
-
-MODULE_DESCRIPTION("ISL6423 SEC");
-MODULE_AUTHOR("Manu Abraham");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/isl6423.h b/drivers/media/dvb/frontends/isl6423.h
deleted file mode 100644
index e1a37fba01c..00000000000
--- a/drivers/media/dvb/frontends/isl6423.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- Intersil ISL6423 SEC and LNB Power supply controller
-
- Copyright (C) Manu Abraham <abraham.manu@gmail.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-#ifndef __ISL_6423_H
-#define __ISL_6423_H
-
-#include <linux/dvb/frontend.h>
-
-enum isl6423_current {
- SEC_CURRENT_275m = 0,
- SEC_CURRENT_515m,
- SEC_CURRENT_635m,
- SEC_CURRENT_800m,
-};
-
-enum isl6423_curlim {
- SEC_CURRENT_LIM_ON = 1,
- SEC_CURRENT_LIM_OFF
-};
-
-struct isl6423_config {
- enum isl6423_current current_max;
- enum isl6423_curlim curlim;
- u8 addr;
- u8 mod_extern;
-};
-
-#if defined(CONFIG_DVB_ISL6423) || (defined(CONFIG_DVB_ISL6423_MODULE) && defined(MODULE))
-
-
-extern struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
- struct i2c_adapter *i2c,
- const struct isl6423_config *config);
-
-#else
-static inline struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
- struct i2c_adapter *i2c,
- const struct isl6423_config *config)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-
-#endif /* CONFIG_DVB_ISL6423 */
-
-#endif /* __ISL_6423_H */
diff --git a/drivers/media/dvb/frontends/it913x-fe-priv.h b/drivers/media/dvb/frontends/it913x-fe-priv.h
deleted file mode 100644