path: root/drivers/staging/vt6656/rf.c

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 *
 *
 * File: rf.c
 *
 * Purpose: rf function code
 *
 * Author: Jerry Chen
 *
 * Date: Feb. 19, 2004
 *
 * Functions:
 *      IFRFbWriteEmbedded      - Embedded write RF register via MAC
 *
 * Revision History:
 *	RF_VT3226: RobertYu:20051111, VT3226C0 and before
 *	RF_VT3226D0: RobertYu:20051228
 *	RF_VT3342A0: RobertYu:20060609
 *
 */

#include "mac.h"
#include "rf.h"
#include "baseband.h"
#include "control.h"
#include "rndis.h"
#include "datarate.h"

static int          msglevel                =MSG_LEVEL_INFO;
//static int          msglevel                =MSG_LEVEL_DEBUG;
#define BY_AL2230_REG_LEN     23 //24bit
#define CB_AL2230_INIT_SEQ    15
#define AL2230_PWR_IDX_LEN    64

#define BY_AL7230_REG_LEN     23 //24bit
#define CB_AL7230_INIT_SEQ    16
#define AL7230_PWR_IDX_LEN    64

//{{RobertYu:20051111
#define BY_VT3226_REG_LEN     23
#define CB_VT3226_INIT_SEQ    11
#define VT3226_PWR_IDX_LEN    64
//}}

//{{RobertYu:20060609
#define BY_VT3342_REG_LEN     23
#define CB_VT3342_INIT_SEQ    13
#define VT3342_PWR_IDX_LEN    64
//}}

static u8 al2230_init_table[CB_AL2230_INIT_SEQ][3] = {
    {0x03, 0xF7, 0x90},
    {0x03, 0x33, 0x31},
    {0x01, 0xB8, 0x02},
    {0x00, 0xFF, 0xF3},
    {0x00, 0x05, 0xA4},
    {0x0F, 0x4D, 0xC5},   //RobertYu:20060814
    {0x08, 0x05, 0xB6},
    {0x01, 0x47, 0xC7},
    {0x00, 0x06, 0x88},
    {0x04, 0x03, 0xB9},
    {0x00, 0xDB, 0xBA},
    {0x00, 0x09, 0x9B},
    {0x0B, 0xDF, 0xFC},
    {0x00, 0x00, 0x0D},
    {0x00, 0x58, 0x0F}
    };

static u8 al2230_channel_table0[CB_MAX_CHANNEL_24G][3] = {
    {0x03, 0xF7, 0x90}, // channel = 1, Tf = 2412MHz
    {0x03, 0xF7, 0x90}, // channel = 2, Tf = 2417MHz
    {0x03, 0xE7, 0x90}, // channel = 3, Tf = 2422MHz
    {0x03, 0xE7, 0x90}, // channel = 4, Tf = 2427MHz
    {0x03, 0xF7, 0xA0}, // channel = 5, Tf = 2432MHz
    {0x03, 0xF7, 0xA0}, // channel = 6, Tf = 2437MHz
    {0x03, 0xE7, 0xA0}, // channel = 7, Tf = 2442MHz
    {0x03, 0xE7, 0xA0}, // channel = 8, Tf = 2447MHz
    {0x03, 0xF7, 0xB0}, // channel = 9, Tf = 2452MHz
    {0x03, 0xF7, 0xB0}, // channel = 10, Tf = 2457MHz
    {0x03, 0xE7, 0xB0}, // channel = 11, Tf = 2462MHz
    {0x03, 0xE7, 0xB0}, // channel = 12, Tf = 2467MHz
    {0x03, 0xF7, 0xC0}, // channel = 13, Tf = 2472MHz
    {0x03, 0xE7, 0xC0}  // channel = 14, Tf = 2412M
    };

static u8 al2230_channel_table1[CB_MAX_CHANNEL_24G][3] = {
    {0x03, 0x33, 0x31}, // channel = 1, Tf = 2412MHz
    {0x0B, 0x33, 0x31}, // channel = 2, Tf = 2417MHz
    {0x03, 0x33, 0x31}, // channel = 3, Tf = 2422MHz
    {0x0B, 0x33, 0x31}, // channel = 4, Tf = 2427MHz
    {0x03, 0x33, 0x31}, // channel = 5, Tf = 2432MHz
    {0x0B, 0x33, 0x31}, // channel = 6, Tf = 2437MHz
    {0x03, 0x33, 0x31}, // channel = 7, Tf = 2442MHz
    {0x0B, 0x33, 0x31}, // channel = 8, Tf = 2447MHz
    {0x03, 0x33, 0x31}, // channel = 9, Tf = 2452MHz
    {0x0B, 0x33, 0x31}, // channel = 10, Tf = 2457MHz
    {0x03, 0x33, 0x31}, // channel = 11, Tf = 2462MHz
    {0x0B, 0x33, 0x31}, // channel = 12, Tf = 2467MHz
    {0x03, 0x33, 0x31}, // channel = 13, Tf = 2472MHz
    {0x06, 0x66, 0x61}  // channel = 14, Tf = 2412M
    };

// 40MHz reference frequency
// Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
static u8 al7230_init_table[CB_AL7230_INIT_SEQ][3] = {
    {0x20, 0x37, 0x90}, // Channel1 // Need modify for 11a
    {0x13, 0x33, 0x31}, // Channel1 // Need modify for 11a
    {0x84, 0x1F, 0xF