path: root/drivers/staging/vt6655/rf.c

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 *
 *
 * File: rf.c
 *
 * Purpose: rf function code
 *
 * Author: Jerry Chen
 *
 * Date: Feb. 19, 2004
 *
 * Functions:
 *      IFRFbWriteEmbeded      - Embeded write RF register via MAC
 *
 * Revision History:
 *
 */

#include "mac.h"
#include "srom.h"
#include "rf.h"
#include "baseband.h"

/*---------------------  Static Definitions -------------------------*/

//static int          msglevel                =MSG_LEVEL_INFO;

#define BY_RF2959_REG_LEN     23 //24bits
#define CB_RF2959_INIT_SEQ    15
#define SWITCH_CHANNEL_DELAY_RF2959 200 //us
#define RF2959_PWR_IDX_LEN    32

#define BY_MA2825_REG_LEN     23 //24bit
#define CB_MA2825_INIT_SEQ    13
#define SWITCH_CHANNEL_DELAY_MA2825 200 //us
#define MA2825_PWR_IDX_LEN    31

#define BY_AL2230_REG_LEN     23 //24bit
#define CB_AL2230_INIT_SEQ    15
#define SWITCH_CHANNEL_DELAY_AL2230 200 //us
#define AL2230_PWR_IDX_LEN    64


#define BY_UW2451_REG_LEN     23
#define CB_UW2451_INIT_SEQ    6
#define SWITCH_CHANNEL_DELAY_UW2451 200 //us
#define UW2451_PWR_IDX_LEN    25

//{{ RobertYu: 20041118
#define BY_MA2829_REG_LEN     23 //24bit
#define CB_MA2829_INIT_SEQ    13
#define SWITCH_CHANNEL_DELAY_MA2829 200 //us
#define MA2829_PWR_IDX_LEN    64
//}} RobertYu

//{{ RobertYu:20050103
#define BY_AL7230_REG_LEN     23 //24bit
#define CB_AL7230_INIT_SEQ    16
#define SWITCH_CHANNEL_DELAY_AL7230 200 //us
#define AL7230_PWR_IDX_LEN    64
//}} RobertYu

//{{ RobertYu: 20041210
#define BY_UW2452_REG_LEN     23
#define CB_UW2452_INIT_SEQ    5 //RoberYu:20050113, Rev0.2 Programming Guide(remove R3, so 6-->5)
#define SWITCH_CHANNEL_DELAY_UW2452 100 //us
#define UW2452_PWR_IDX_LEN    64
//}} RobertYu

#define BY_VT3226_REG_LEN     23
#define CB_VT3226_INIT_SEQ    12
#define SWITCH_CHANNEL_DELAY_VT3226 200 //us
#define VT3226_PWR_IDX_LEN    16

/*---------------------  Static Classes  ----------------------------*/

/*---------------------  Static Variables  --------------------------*/



const DWORD dwAL2230InitTable[CB_AL2230_INIT_SEQ] = {
    0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
    0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
    };

const DWORD dwAL2230ChannelTable0[CB_MAX_CHANNEL] = {
    0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
    0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
    0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
    0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
    0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz