path: root/drivers/staging/octeon/cvmx-pip-defs.h

/***********************license start***************
 * Author: Cavium Networks
 *
 * Contact: support@caviumnetworks.com
 * This file is part of the OCTEON SDK
 *
 * Copyright (c) 2003-2008 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 *
 * This file is distributed in the hope that it will be useful, but
 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 * NONINFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this file; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 * or visit http://www.gnu.org/licenses/.
 *
 * This file may also be available under a different license from Cavium.
 * Contact Cavium Networks for more information
 ***********************license end**************************************/

#ifndef __CVMX_PIP_DEFS_H__
#define __CVMX_PIP_DEFS_H__

/*
 * Enumeration representing the amount of packet processing
 * and validation performed by the input hardware.
 */
enum cvmx_pip_port_parse_mode {
	/*
	 * Packet input doesn't perform any processing of the input
	 * packet.
	 */
	CVMX_PIP_PORT_CFG_MODE_NONE = 0ull,
	/*
	 * Full packet processing is performed with pointer starting
	 * at the L2 (ethernet MAC) header.
	 */
	CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,
	/*
	 * Input packets are assumed to be IP.  Results from non IP
	 * packets is undefined. Pointers reference the beginning of
	 * the IP header.
	 */
	CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull
};

#define CVMX_PIP_BCK_PRS \
	 CVMX_ADD_IO_SEG(0x00011800A0000038ull)
#define CVMX_PIP_BIST_STATUS \
	 CVMX_ADD_IO_SEG(0x00011800A0000000ull)
#define CVMX_PIP_CRC_CTLX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8))
#define CVMX_PIP_CRC_IVX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8))
#define CVMX_PIP_DEC_IPSECX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8))
#define CVMX_PIP_DSA_SRC_GRP \
	 CVMX_ADD_IO_SEG(0x00011800A0000190ull)
#define CVMX_PIP_DSA_VID_GRP \
	 CVMX_ADD_IO_SEG(0x00011800A0000198ull)
#define CVMX_PIP_FRM_LEN_CHKX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8))
#define CVMX_PIP_GBL_CFG \
	 CVMX_ADD_IO_SEG(0x00011800A0000028ull)
#define CVMX_PIP_GBL_CTL \
	 CVMX_ADD_IO_SEG(0x00011800A0000020ull)
#define CVMX_PIP_HG_PRI_QOS \
	 CVMX_ADD_IO_SEG(0x00011800A00001A0ull)
#define CVMX_PIP_INT_EN \
	 CVMX_ADD_IO_SEG(0x00011800A0000010ull)
#define CVMX_PIP_INT_REG \
	 CVMX_ADD_IO_SEG(0x00011800A0000008ull)
#define CVMX_PIP_IP_OFFSET \
	 CVMX_ADD_IO_SEG(0x00011800A0000060ull)
#define CVMX_PIP_PRT_CFGX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8))
#define CVMX_PIP_PRT_TAGX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8))
#define CVMX_PIP_QOS_DIFFX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8))
#define CVMX_PIP_QOS_VLANX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8))
#define CVMX_PIP_QOS_WATCHX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8))
#define CVMX_PIP_RAW_WORD \
	 CVMX_ADD_IO_SEG(0x00011800A00000B0ull)
#define CVMX_PIP_SFT_RST \
	 CVMX_ADD_IO_SEG(0x00011800A0000030ull)
#define CVMX_PIP_STAT0_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT1_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT2_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT3_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT4_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT5_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT6_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT7_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT8_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT9_PRTX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80))
#define CVMX_PIP_STAT_CTL \
	 CVMX_ADD_IO_SEG(0x00011800A0000018ull)
#define CVMX_PIP_STAT_INB_ERRSX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32))
#define CVMX_PIP_STAT_INB_OCTSX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32))
#define CVMX_PIP_STAT_INB_PKTSX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32))
#define CVMX_PIP_TAG_INCX(offset) \
	 CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8))
#define CVMX_PIP_TAG_MASK \
	 CVMX_ADD_IO_SEG(0x00011800A0000070ull)
#define CVMX_PIP_TAG_SECRET \
	 CVMX_ADD_IO_SEG(0x00011800A0000068ull)
#define CVMX_PIP_TODO_ENTRY \
	 CVMX_ADD_IO_SEG(0x00011800A0000078ull)

union cvmx_pip_bck_prs {
	uint64_t u64;
	struct cvmx_pip_bck_prs_s {
		uint64_t bckprs:1;
		uint64_t reserved_13_62:50;
		uint64_t hiwater:5;
		uint64_t reserved_5_7:3;
		uint64_t lowater:5;
	} s;
	struct cvmx_pip_bck_prs_s cn38xx;
	struct cvmx_pip_bck_prs_s cn38xxp2;
	struct cvmx_pip_bck_prs_s cn56xx;
	struct cvmx_pip_bck_prs_s cn56xxp1;
	struct cvmx_pip_bck_prs_s cn58xx;
	struct cvmx_pip_bck_prs_s cn58xxp1;
};

union cvmx_pip_bist_status {
	uint64_t u64;
	struct cvmx_pip_bist_status_s {
		uint64_t reserved_18_63:46;
		uint64_t bist:18;
	} s;
	struct cvmx_pip_bist_status_s cn30xx;
	struct cvmx_pip_bist_status_s cn31xx;
	struct cvmx_pip_bist_status_s cn38xx;