path: root/drivers/staging/dgap/dgap.h

/*
 * Copyright 2003 Digi International (www.digi.com)
 *      Scott H Kilau <Scott_Kilau at digi dot com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
 * PURPOSE.  See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *	NOTE: THIS IS A SHARED HEADER. DO NOT CHANGE CODING STYLE!!!
 *
 *************************************************************************
 *
 * Driver includes
 *
 *************************************************************************/

#ifndef __DGAP_DRIVER_H
#define __DGAP_DRIVER_H

#include <linux/types.h>        /* To pick up the varions Linux types */
#include <linux/tty.h>          /* To pick up the various tty structs/defines */
#include <linux/interrupt.h>    /* For irqreturn_t type */

#ifndef TRUE
# define TRUE 1
#endif

#ifndef FALSE
# define FALSE 0
#endif

/* Required for our shared headers! */
typedef unsigned char		uchar;

#if !defined(TTY_FLIPBUF_SIZE)
# define TTY_FLIPBUF_SIZE 512
#endif

/*************************************************************************
 *
 * Driver defines
 *
 *************************************************************************/

/*
 * Driver identification
 */
#define	DG_NAME		"dgap-1.3-16"
#define	DG_PART		"40002347_C"
#define	DRVSTR		"dgap"

/*
 * defines from dgap_pci.h
 */
#define PCIMAX 32			/* maximum number of PCI boards */

#define DIGI_VID		0x114F

#define PCI_DEV_EPC_DID		0x0002
#define PCI_DEV_XEM_DID		0x0004
#define PCI_DEV_XR_DID		0x0005
#define PCI_DEV_CX_DID		0x0006
#define PCI_DEV_XRJ_DID		0x0009	/* PLX-based Xr adapter */
#define PCI_DEV_XR_IBM_DID	0x0011	/* IBM 8-port Async Adapter */
#define PCI_DEV_XR_BULL_DID	0x0013	/* BULL 8-port Async Adapter */
#define PCI_DEV_XR_SAIP_DID	0x001c	/* SAIP card - Xr adapter */
#define PCI_DEV_XR_422_DID	0x0012	/* Xr-422 */
#define PCI_DEV_920_2_DID	0x0034	/* XR-Plus 920 K, 2 port */
#define PCI_DEV_920_4_DID	0x0026	/* XR-Plus 920 K, 4 port */
#define PCI_DEV_920_8_DID	0x0027	/* XR-Plus 920 K, 8 port */
#define PCI_DEV_EPCJ_DID	0x000a	/* PLX 9060 chip for PCI  */
#define PCI_DEV_CX_IBM_DID	0x001b	/* IBM 128-port Async Adapter */
#define PCI_DEV_920_8_HP_DID	0x0058	/* HP XR-Plus 920 K, 8 port */
#define PCI_DEV_XEM_HP_DID	0x0059  /* HP Xem PCI */

#define PCI_DEV_XEM_NAME	"AccelePort XEM"
#define PCI_DEV_CX_NAME		"AccelePort CX"
#define PCI_DEV_XR_NAME		"AccelePort Xr"
#define PCI_DEV_XRJ_NAME	"AccelePort Xr (PLX)"
#define PCI_DEV_XR_SAIP_NAME	"AccelePort Xr (SAIP)"
#define PCI_DEV_920_2_NAME	"AccelePort Xr920 2 port"
#define PCI_DEV_920_4_NAME	"AccelePort Xr920 4 port"
#define PCI_DEV_920_8_NAME	"AccelePort Xr920 8 port"
#define PCI_DEV_XR_422_NAME	"AccelePort Xr 422"
#define PCI_DEV_EPCJ_NAME	"AccelePort EPC (PLX)"
#define PCI_DEV_XR_BULL_NAME	"AccelePort Xr (BULL)"
#define PCI_DEV_XR_IBM_NAME	"AccelePort Xr (IBM)"
#define PCI_DEV_CX_IBM_NAME	"AccelePort CX (IBM)"
#define PCI_DEV_920_8_HP_NAME	"AccelePort Xr920 8 port (HP)"
#define PCI_DEV_XEM_HP_NAME	"AccelePort XEM (HP)"

/*
 * On the PCI boards, there is no IO space allocated
 * The I/O registers will be in the first 3 bytes of the
 * upper 2MB of the 4MB memory space.  The board memory
 * will be mapped into the low 2MB of the 4MB memory space
 */

/* Potential location of PCI Bios from E0000 to FFFFF*/
#define PCI_BIOS_SIZE		0x00020000

/* Size of Memory and I/O for PCI (4MB) */
#define PCI_RAM_SIZE		0x00400000

/* Size of Memory (2MB) */
#define PCI_MEM_SIZE		0x00200000

/* Max PCI Window Size (2MB) */
#define PCI_WIN_SIZE		0x00200000

#define PCI_WIN_SHIFT		21 /* 21 bits max */

/* Offset of I/0 in Memory (2MB) */
#define PCI_IO_OFFSET		0x00200000

/* Size of IO (2MB) */
#define PCI_IO_SIZE		0x00200000

/* Number of boards we support at once. */
#define	MAXBOARDS	32
#define	MAXPORTS	224
#define MAXTTYNAMELEN	200

/* Our 3 magic numbers for our board, channel and unit structs */
#define DGAP_BOARD_MAGIC	0x5c6df104
#define DGAP_CHANNEL_MAGIC	0x6c6df104
#define DGAP_UNIT_MAGIC		0x7c6df104

/* Serial port types */
#define DGAP_SERIAL		0
#define DGAP_PRINT		1

#define	SERIAL_TYPE_NORMAL	1

/* 4 extra for alignment play space */
#define WRITEBUFLEN		((4096) + 4)
#define MYFLIPLEN		N_TTY_BUF_SIZE

#define SBREAK_TIME 0x25
#define U2BSIZE 0x400

#define dgap_jiffies_from_ms(a) (((a) * HZ) / 1000)

/*
 * Our major for the mgmt devices.
 *
 * We can use 22, because Digi was allocated 22 and 23 for the epca driver.
 * 22 has now become obsolete now that the "cu" devices have
 * been removed from 2.6.
 * Also, this *IS* the epca driver, just PCI only now.
 */
#ifndef DIGI_DGAP_MAJOR
# define DIGI_DGAP_MAJOR         22
#endif

/*
 * The parameters we use to define the periods of the moving averages.
 */
#define		MA_PERIOD	(HZ / 10)
#define		SMA_DUR		(1 * HZ)
#define		EMA_DUR		(1 * HZ)
#define		SMA_NPERIODS	(SMA_DUR / MA_PERIOD)
#define		EMA_NPERIODS	(EMA_DUR / MA_PERIOD)

/*
 * Define a local default termios struct. All ports will be created
 * with this termios initially.  This is the same structure that is defined
 * as the default in tty_io.c with the same settings overriden as in serial.c
 *
 * In short, this should match the internal serial ports' defaults.
 */
#define	DEFAULT_IFLAGS	(ICRNL | IXON)
#define	DEFAULT_OFLAGS	(OPOST | ONLCR)
#define	DEFAULT_CFLAGS	(B9600 | CS8 | CREAD | HUPCL | CLOCAL)
#define	DEFAULT_LFLAGS	(ISIG | ICANON | ECHO | ECHOE | ECHOK | \
			ECHOCTL | ECHOKE | IEXTEN)

#ifndef _POSIX_VDISABLE
#define   _POSIX_VDISABLE '\0'
#endif

#define SNIFF_MAX	65536		/* Sniff buffer size (2^n) */
#define SNIFF_MASK	(SNIFF_MAX - 1)	/* Sniff wrap mask */

#define VPDSIZE (512)

/************************************************************************
 *      FEP memory offsets
 ************************************************************************/
#define START           0x00