#include "headers.h"
#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
#define MIPS_CLOCK_REG 0x0f000820
/* DDR INIT-133Mhz */
#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 /* index for 0x0F007000 */
static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = { /* DPLL Clock Setting */
{0x0F000800, 0x00007212},
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00000F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
/* Changed source for X-bar and MIPS clock to APLL */
{0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a04C, 0x0000000C},
/* Memcontroller Default values */
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001},
{0x0F007020, 0x04030107},
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020202},
{0x0F00702c, 0x0206060a},
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
{0x0F007038, 0x110a0200},
{0x0F00703C, 0x02101010},
{0x0F007040, 0x45751200},
{0x0F007044, 0x110a0d00},
{0x0F007048, 0x081b0306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x0010246c},
{0x0F007064, 0x00000010},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00007000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
/* Enable BW improvement within memory controller */
{0x0F007094, 0x00000104},
/* Enable 2 ports within X-bar */
{0x0F00A000, 0x00000016},
/* Enable start bit within memory controller */
{0x0F007018, 0x01010000}
};
/* 80Mhz */
#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 /* index for 0x0F007000 */
static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = { /* DPLL Clock Setting */
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07f1ffff},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a000, 0x00000016},
{0x0F00a04C, 0x0000000C},
/* Memcontroller Default values */
{0x0F007000, 0x00010001},
{0x0F007004, 0x01000000},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000},
{0x0F007020, 0x04020107},
{0x0F007024, 0x00000007},