path: root/drivers/pinctrl/pinctrl-adi2.c

/*
 * Pinctrl Driver for ADI GPIO2 controller
 *
 * Copyright 2007-2013 Analog Devices Inc.
 *
 * Licensed under the GPLv2 or later
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#include <linux/platform_data/pinctrl-adi2.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/syscore_ops.h>
#include <linux/gpio.h>
#include <asm/portmux.h>
#include "pinctrl-adi2.h"
#include "core.h"

/*
According to the BF54x HRM, pint means "pin interrupt".
http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf

ADSP-BF54x processor Blackfin processors have four SIC interrupt chan-
nels dedicated to pin interrupt purposes. These channels are managed by
four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
pins of port A and port B, PINT2 and PINT3 manage all the pins from port
C to port J as shown in Figure 9-2.

n BF54x HRM:
The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and
upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi-
plexers shown in Figure 9-3. Lower half units of eight pins can be
forwarded to either byte 0 or byte 2 of either associated PINTx block.
Upper half units can be forwarded to either byte 1 or byte 3 of the pin
interrupt blocks, without further restrictions.

All MMR registers in the pin interrupt module are 32 bits wide. To simply the
mapping logic, this driver only maps a 16-bit gpio port to the upper or lower
16 bits of a PINTx block. You can find the Figure 9-3 on page 583.

Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map
to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
interrupt handler.

The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
domain pointer in domain[0]. The IRQ domain pointer of the other bank is set
to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
the current domain pointer according to whether the interrupt request mask
is in lower 16 bits (domain[0]) or upper 16bits (domain[1]).

A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
port devices can be mapped to the same PINT device.

*/

static LIST_HEAD(adi_pint_list);
static LIST_HEAD(adi_gpio_port_list);

#define DRIVER_NAME "pinctrl-adi2"

#define PINT_HI_OFFSET		16

/**
 * struct gpio_port_saved - GPIO port registers that should be saved between
 * power suspend and resume operations.
 *
 * @fer: PORTx_FER register
 * @data: PORTx_DATA register
 * @dir: PORTx_DIR register
 * @inen: PORTx_INEN register
 * @mux: PORTx_MUX register
 */
struct gpio_port_saved {
	u16 fer;
	u16 data;
	u16 dir;
	u16 inen;
	u32 mux;
};

/*
 * struct gpio_pint_saved - PINT registers saved in PM operations
 *
 * @assign: ASSIGN register
 * @edge_set: EDGE_SET register
 * @invert_set: INVERT_SET register
 */
struct gpio_pint_saved {
	u32 assign;
	u32 edge_set;
	u32 invert_set;
};

/**
 * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
 * banks can be mapped into one Pin interrupt controller.
 *
 * @node: All gpio_pint instances are added to a global list.
 * @base: PINT device register base address
 * @irq: IRQ of the PINT device, it is the parent IRQ of all
 *       GPIO IRQs mapping to this device.
 * @domain: [0] irq domain of the gpio port, whose hardware interrupts are
 *		mapping to the low 16-bit of the pint registers.
 *          [1] irq domain of the gpio port, whose hardware interrupts are
 *		mapping to the high 16-bit of the pint registers.
 * @regs: address pointer to the PINT device
 * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
 * @lock: This lock make sure the irq_chip operations to one PINT device
 *        for different GPIO interrrupts are atomic.
 * @pint_map_port: Set up the mapping between one PINT device and
 *                 multiple GPIO banks.
 */
struct gpio_pint {
	struct list_head node;
	void __iomem *base;
	int irq;
	struct irq_domain *domain[2];
	struct gpio_pint_regs *regs;
	struct gpio_pint_saved saved_data;
	int map_count;
	spinlock_t lock;

	int (*pint_map_port)(struct gpio_pint *pint, bool assign,
				u8 map, struct irq_domain *domain);
};

/**
 * ADI pin controller
 *
 * @dev: a pointer back to containing device
 * @pctl: the pinctrl device
 * @soc: SoC data for this specific chip
 */
struct adi_pinctrl {
	struct device *dev;
	struct pinctrl_dev *pctl;
	const struct adi_pinctrl_soc_data *soc;
};

/**
 * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
 * into one pin interrupt controller.
 *
 * @node: All gpio_port instances are added to a list.
 * @base: GPIO bank device register base address
 * @irq_base: base IRQ of the GPIO bank device
 * @width: PIN number of the GPIO bank device
 * @regs: address pointer to the GPIO bank device
 * @saved_data: registers that should be saved between PM operations.
 * @dev: device structure of this GPIO bank
 * @pint: GPIO PINT device that this GPIO bank mapped to
 * @pint_map: GIOP bank mapping code in PINT device
 * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
 *               GPIO bank can be mapped into either low 16 bits[0] or high 16
 *               bits[1] of each PINT register.
 * @lock: This lock make sure the irq_chip operations to one PINT device
 *        for different GPIO interrrupts are atomic.
 * @chip: abstract a GPIO controller
 * @domain: The irq domain owned by the GPIO port.
 * @rsvmap: Reservation map array for each pin in the GPIO bank
 */
struct gpio_port {
	struct list_head node;
	void __iomem *base;
	int irq_base;
	unsigned int width;
	struct gpio_port_t *regs;
	struct gpio_port_saved saved_data;
	struct device *dev;

	struct gpio_pint *pint;
	u8 pint_map;
	bool pint_assign;

	spinlock_t lock;
	struct gpio_chip chip;
	struct irq_domain *domain;