path: root/drivers/net/wireless/rtlwifi/rtl8192de/reg.h

/******************************************************************************
 *
 * Copyright(c) 2009-2012  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#ifndef __RTL92D_REG_H__
#define __RTL92D_REG_H__

/* ----------------------------------------------------- */
/* 0x0000h ~ 0x00FFh System Configuration */
/* ----------------------------------------------------- */
#define REG_SYS_ISO_CTRL		0x0000
#define REG_SYS_FUNC_EN			0x0002
#define REG_APS_FSMCO			0x0004
#define REG_SYS_CLKR			0x0008
#define REG_9346CR			0x000A
#define REG_EE_VPD			0x000C
#define REG_AFE_MISC			0x0010
#define REG_SPS0_CTRL			0x0011
#define REG_POWER_OFF_IN_PROCESS	0x0017
#define REG_SPS_OCP_CFG			0x0018
#define REG_RSV_CTRL			0x001C
#define REG_RF_CTRL			0x001F
#define REG_LDOA15_CTRL			0x0020
#define REG_LDOV12D_CTRL		0x0021
#define REG_LDOHCI12_CTRL		0x0022
#define REG_LPLDO_CTRL			0x0023
#define REG_AFE_XTAL_CTRL		0x0024
#define REG_AFE_PLL_CTRL		0x0028
/* for 92d, DMDP,SMSP,DMSP contrl */
#define REG_MAC_PHY_CTRL		0x002c
#define REG_EFUSE_CTRL			0x0030
#define REG_EFUSE_TEST			0x0034
#define REG_PWR_DATA			0x0038
#define REG_CAL_TIMER			0x003C
#define REG_ACLK_MON			0x003E
#define REG_GPIO_MUXCFG			0x0040
#define REG_GPIO_IO_SEL			0x0042
#define REG_MAC_PINMUX_CFG		0x0043
#define REG_GPIO_PIN_CTRL		0x0044
#define REG_GPIO_INTM			0x0048
#define REG_LEDCFG0			0x004C
#define REG_LEDCFG1			0x004D
#define REG_LEDCFG2			0x004E
#define REG_LEDCFG3			0x004F
#define REG_FSIMR			0x0050
#define REG_FSISR			0x0054

#define REG_MCUFWDL			0x0080

#define REG_HMEBOX_EXT_0		0x0088
#define REG_HMEBOX_EXT_1		0x008A
#define REG_HMEBOX_EXT_2		0x008C
#define REG_HMEBOX_EXT_3		0x008E

#define REG_BIST_SCAN			0x00D0
#define REG_BIST_RPT			0x00D4
#define REG_BIST_ROM_RPT		0x00D8
#define REG_USB_SIE_INTF		0x00E0
#define REG_PCIE_MIO_INTF		0x00E4
#define REG_PCIE_MIO_INTD		0x00E8
#define REG_HPON_FSM			0x00EC
#define REG_SYS_CFG			0x00F0
#define REG_MAC_PHY_CTRL_NORMAL		0x00f8

#define  REG_MAC0			0x0081
#define  REG_MAC1			0x0053
#define  FW_MAC0_READY			0x18
#define  FW_MAC1_READY			0x1A
#define  MAC0_ON			BIT(7)
#define  MAC1_ON			BIT(0)
#define  MAC0_READY			BIT(0)
#define  MAC1_READY			BIT(0)

/* ----------------------------------------------------- */
/* 0x0100h ~ 0x01FFh	MACTOP General Configuration */
/* ----------------------------------------------------- */
#define REG_CR				0x0100
#define REG_PBP				0x0104
#define REG_TRXDMA_CTRL			0x010C
#define REG_TRXFF_BNDY			0x0114
#define REG_TRXFF_STATUS		0x0118
#define REG_RXFF_PTR			0x011C
#define REG_HIMR			0x0120
#define REG_HISR			0x0124
#define REG_HIMRE			0x0128
#define REG_HISRE			0x012C
#define REG_CPWM			0x012F
#define REG_FWIMR			0x0130
#define REG_FWISR			0x0134
#define REG_PKTBUF_DBG_CTRL		0x0140
#define REG_PKTBUF_DBG_DATA_L		0x0144
#define REG_PKTBUF_DBG_DATA_H		0x0148

#define REG_TC0_CTRL			0x0150
#define REG_TC1_CTRL			0x0154
#define REG_TC2_CTRL			0x0158
#define REG_TC3_CTRL			0x015C
#define REG_TC4_CTRL			0x0160
#define REG_TCUNIT_BASE			0x0164
#define REG_MBIST_START			0x0174
#define REG_MBIST_DONE			0x0178
#define REG_MBIST_FAIL			0x017C
#define REG_C2HEVT_MSG_NORMAL		0x01A0
#define REG_C2HEVT_MSG_TEST		0x01B8
#define REG_C2HEVT_CLEAR		0x01BF
#define REG_MCUTST_1			0x01c0
#define REG_FMETHR			0x01C8
#define REG_HMETFR			0x01CC
#define REG_HMEBOX_0			0x01D0
#define REG_HMEBOX_1			0x01D4
#define REG_HMEBOX_2			0x01D8
#define REG_HMEBOX_3			0x01DC

#define REG_LLT_INIT			0x01E0
#define REG_BB_ACCEESS_CTRL		0x01E8
#define REG_BB_ACCESS_DATA		0x01EC


/* ----------------------------------------------------- */
/*	0x0200h ~ 0x027Fh	TXDMA Configuration */
/* ----------------------------------------------------- */
#define REG_RQPN			0x0200
#define REG_FIFOPAGE			0x0204
#define REG_TDECTRL			0x0208
#define REG_TXDMA_OFFSET_CHK		0x020C
#define REG_TXDMA_STATUS		0x0210
#define REG_RQPN_NPQ			0x0214

/* ----------------------------------------------------- */
/*	0x0280h ~ 0x02FFh	RXDMA Configuration */
/* ----------------------------------------------------- */
#define REG_RXDMA_AGG_PG_TH		0x0280
#define REG_RXPKT_NUM			0x0284
#define REG_RXDMA_STATUS		0x0288

/* ----------------------------------------------------- */
/*	0x0300h ~ 0x03FFh	PCIe  */
/* ----------------------------------------------------- */
#define	REG_PCIE_CTRL_REG		0x0300
#define	REG_INT_MIG			0x0304
#define	REG_BCNQ_DESA			0x0308
#define	REG_HQ_DESA			0x0310
#define	REG_MGQ_DESA			0x0318
#define	REG_VOQ_DESA			0x0320
#define	REG_VIQ_DESA			0x0328
#define	REG_BEQ_DESA			0x0330
#define	REG_BKQ_DESA			0x0338
#define	REG_RX_DESA			0x0340
#define	REG_DBI				0x0348
#define	REG_DBI_WDATA			0x0348
#define REG_DBI_RDATA			0x034C
#define REG_DBI_CTRL			0x0350
#define REG_DBI_FLAG			0x0352
#define	REG_MDIO			0x0354
#define	REG_DBG_SEL			0x0360
#define	REG_PCIE_HRPWM			0x0361
#define	REG_PCIE_HCPWM			0x0363
#define	REG_UART_CTRL			0x0364
#define	REG_UART_TX_DESA		0x0370
#define	REG_UART_RX_DESA		0x0378

/* ----------------------------------------------------- */
/*	0x0400h ~ 0x047Fh	Protocol Configuration  */
/* ----------------------------------------------------- */
#define REG_VOQ_INFORMATION		0x0400
#define REG_VIQ_INFORMATION		0x0404
#define REG_BEQ_INFORMATION		0x0408
#define REG_BKQ_INFORMATION		0x040C
#define REG_MGQ_INFORMATION		0x0410
#define REG_HGQ_INFORMATION		0x0414
#define REG_BCNQ_INFORMATION		0x0418


#define REG_CPU_MGQ_INFORMATION		0x041C
#define REG_FWHW_TXQ_CTRL		0x0420
#define REG_HWSEQ_CTRL			0x0423
#define REG_TXPKTBUF_BCNQ_BDNY		0x0424
#define REG_TXPKTBUF_MGQ_BDNY		0x0425
#define REG_MULTI_BCNQ_EN		0x0426
#define REG_MULTI_BCNQ_OFFSET		0x0427
#define REG_SPEC_SIFS			0x0428
#define REG_RL				0x042A