path: root/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h

/*
 * Copyright (c) 2010-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef INITVALS_9580_1P0_H
#define INITVALS_9580_1P0_H

/* AR9580 1.0 */

#define ar9580_1p0_soc_preamble ar9300_2p2_soc_preamble

#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble

#define ar9580_1p0_radio_core ar9300_2p2_radio_core

#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble

#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2

#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2

#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2

#define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2

#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484

static const u32 ar9580_1p0_radio_postamble[][5] = {
	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
	{0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
	{0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
	{0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
	{0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
	{0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
	{0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
	{0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
	{0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
	{0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
};

static const u32 ar9580_1p0_baseband_core[][2] = {
	/* Addr      allmodes  */
	{0x00009800, 0xafe68e30},
	{0x00009804, 0xfd14e000},
	{0x00009808, 0x9c0a9f6b},
	{0x0000980c, 0x04900000},
	{0x0000981c, 0x00020028},
	{0x00009834, 0x6400a190},
	{0x00009838, 0x0108ecff},
	{0x0000983c, 0x14000600},
	{0x00009880, 0x201fff00},
	{0x00009884, 0x00001042},
	{0x000098a4, 0x00200400},
	{0x000098b0, 0x32840bbe},
	{0x000098d0, 0x004b6a8e},
	{0x000098d4, 0x00000820},
	{0x000098dc, 0x00000000},
	{0x000098f0, 0x00000000},
	{0x000098f4, 0x00000000},
	{0x00009c04, 0xff55ff55},
	{0x00009c08, 0x0320ff55},
	{0x00009c0c, 0x00000000},
	{0x00009c10, 0x00000000},
	{0x00009c14, 0x00046384},
	{0x00009c18, 0x05b6b440},
	{0x00009c1c, 0x00b6b440},
	{0x00009d00, 0xc080a333},
	{0x00009d04, 0x40206c10},
	{0x00009d08, 0x009c4060},
	{0x00009d0c, 0x9883800a},
	{0x00009d10, 0x01884061},
	{0x00009d14, 0x00c0040b},
	{0x00009d18, 0x00000000},
	{0x00009e08, 0x0038230c},
	{0x00009e24, 0x990bb515},
	{0x00009e28, 0x0c6f0000},
	{0x00009e30, 0x06336f77},
	{0x00009e34, 0x6af6532f},
	{0x00009e38, 0x0cc80c00},
	{0x00009e40, 0x0d261800},
	{0x00009e4c, 0x00001004},
	{0x00009e50, 0x00ff03f1},
	{0x00009e54, 0x00000000},
	{0x00009fc0, 0x803e4788},
	{0x00009fc4, 0x0001efb5},
	{0x00009fcc,