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/*
*
* ipg.h
*
* Include file for Gigabit Ethernet device driver for Network
* Interface Cards (NICs) utilizing the Tamarack Microelectronics
* Inc. IPG Gigabit or Triple Speed Ethernet Media Access
* Controller.
*
* Craig Rich
* Sundance Technology, Inc.
* 1485 Saratoga Avenue
* Suite 200
* San Jose, CA 95129
* 408 873 4117
* www.sundanceti.com
* craig_rich@sundanceti.com
*/
#ifndef __LINUX_IPG_H
#define __LINUX_IPG_H
#include <linux/version.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/skbuff.h>
#include <linux/version.h>
#include <asm/bitops.h>
/*#include <asm/spinlock.h>*/
#define DrvVer "2.09d"
#define IPG_DEV_KFREE_SKB(skb) dev_kfree_skb_irq(skb)
/*
* Constants
*/
/* GMII based PHY IDs */
#define NS 0x2000
#define MARVELL 0x0141
#define ICPLUS_PHY 0x243
/* NIC Physical Layer Device MII register fields. */
#define MII_PHY_SELECTOR_IEEE8023 0x0001
#define MII_PHY_TECHABILITYFIELD 0x1FE0
/* GMII_PHY_1000 need to set to prefer master */
#define GMII_PHY_1000BASETCONTROL_PreferMaster 0x0400
/* NIC Physical Layer Device GMII constants. */
#define GMII_PREAMBLE 0xFFFFFFFF
#define GMII_ST 0x1
#define GMII_READ 0x2
#define GMII_WRITE 0x1
#define GMII_TA_READ_MASK 0x1
#define GMII_TA_WRITE 0x2
/* I/O register offsets. */
enum ipg_regs {
DMA_CTRL = 0x00,
RX_DMA_STATUS = 0x08, // Unused + reserved
TFD_LIST_PTR_0 = 0x10,
TFD_LIST_PTR_1 = 0x14,
TX_DMA_BURST_THRESH = 0x18,
TX_DMA_URGENT_THRESH = 0x19,
TX_DMA_POLL_PERIOD = 0x1a,
RFD_LIST_PTR_0 = 0x1c,
RFD_LIST_PTR_1 = 0x20,
RX_DMA_BURST_THRESH = 0x24,
RX_DMA_URGENT_THRESH = 0x25,
RX_DMA_POLL_PERIOD = 0x26,
DEBUG_CTRL = 0x2c,
ASIC_CTRL = 0x30,
FIFO_CTRL = 0x38, // Unused
FLOW_OFF_THRESH = 0x3c,
FLOW_ON_THRESH = 0x3e,
EEPROM_DATA = 0x48,
EEPROM_CTRL = 0x4a,
EXPROM_ADDR = 0x4c, // Unused
EXPROM_DATA = 0x50, // Unused
WAKE_EVENT = 0x51, // Unused
COUNTDOWN = 0x54, // Unused
INT_STATUS_ACK = 0x5a,
INT_ENABLE = 0x5c,
INT_STATUS = 0x5e, // Unused
TX_STATUS = 0x60,
MAC_CTRL = 0x6c,
VLAN_TAG = 0x70, // Unused
PHY_SET = 0x75, // JES20040127EEPROM
PHY_CTRL = 0x76,
STATION_ADDRESS_0 = 0x78,
STATION_ADDRESS_1 = 0x7a,
STATION_ADDRESS_2 = 0x7c,
MAX_FRAME_SIZE = 0x86,
RECEIVE_MODE = 0x88,
HASHTABLE_0 = 0x8c,
HASHTABLE_1 = 0x90,
RMON_STATISTICS_MASK = 0x98,
STATISTICS_MASK = 0x9c,
RX_JUMBO_FRAMES = 0xbc, // Unused
TCP_CHECKSUM_ERRORS = 0xc0, // Unused
IP_CHECKSUM_ERRORS = 0xc2, // Unused
UDP_CHECKSUM_ERRORS = 0xc4, // Unused
TX_JUMBO_FRAMES = 0xf4 // Unused
};
/* Ethernet MIB statistic register offsets. */
#define IPG_OCTETRCVOK 0xA8
#define IPG_MCSTOCTETRCVDOK 0xAC
#define IPG_BCSTOCTETRCVOK 0xB0
#define IPG_FRAMESRCVDOK 0xB4
#define IPG_MCSTFRAMESRCVDOK 0xB8
#define IPG_BCSTFRAMESRCVDOK 0xBE
#define IPG_MACCONTROLFRAMESRCVD 0xC6
#define IPG_FRAMETOOLONGERRRORS 0xC8
#define IPG_INRANGELENGTHERRORS 0xCA
#define IPG_FRAMECHECKSEQERRORS 0xCC
#define IPG_FRAMESLOSTRXERRORS 0xCE
#define IPG_OCTETXMTOK 0xD0
#define IPG_MCSTOCTETXMTOK 0xD4
#define IPG_BCSTOCTETXMTOK 0xD8
#define IPG_FRAMESXMTDOK 0xDC
#define IPG_MCSTFRAMESXMTDOK 0xE0
#define IPG_FRAMESWDEFERREDXMT 0xE4
#define IPG_LATECOLLISIONS 0xE8
#define IPG_MULTICOLFRAMES 0xEC
#define IPG_SINGLECOLFRAMES 0xF0
#define IPG_BCSTFRAMESXMTDOK 0xF6
#define IPG_CARRIERSENSEERRORS 0xF8
#define IPG_MACCONTROLFRAMESXMTDOK 0xFA
#define IPG_FRAMESABORTXSCOLLS 0xFC
#define IPG_FRAMESWEXDEFERRAL 0xFE
/* RMON statistic register offsets. */
#define IPG_ETHERSTATSCOLLISIONS 0x100
#define IPG_ETHERSTATSOCTETSTRANSMIT 0x104
#define IPG_ETHERSTATSPKTSTRANSMIT 0x108
#define IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT 0x10C
#define IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT 0x110
#define IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT 0x114
#define IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT 0x118
#define IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT 0x11C
#define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT 0x120
#define IPG_ETHERSTATSCRCALIGNERRORS 0x124
#define IPG_ETHERSTATSUNDERSIZEPKTS 0x128
#define IPG_ETHERSTATSFRAGMENTS 0x12C
#define IPG_ETHERSTATSJABBERS 0x130
#define IPG_ETHERSTATSOCTETS 0x134
#define IPG_ETHERSTATSPKTS 0x138
#define IPG_ETHERSTATSPKTS64OCTESTS 0x13C
#define IPG_ETHERSTATSPKTS65TO127OCTESTS 0x140
#define IPG_ETHERSTATSPKTS128TO255OCTESTS 0x144
#define IPG_ETHERSTATSPKTS256TO511OCTESTS 0x148
#define IPG_ETHERSTATSPKTS512TO1023OCTESTS 0x14C
#define IPG_ETHERSTATSPKTS1024TO1518OCTESTS 0x150
/* RMON statistic register equivalents. */
#define IPG_ETHERSTATSMULTICASTPKTSTRANSMIT 0xE0
#define IPG_ETHERSTATSBROADCASTPKTSTRANSMIT 0xF6
#define IPG_ETHERSTATSMULTICASTPKTS 0xB8
#define IPG_ETHERSTATSBROADCASTPKTS 0xBE
#define IPG_ETHERSTATSOVERSIZEPKTS 0xC8
#define IPG_ETHERSTATSDROPEVENTS 0xCE
/* Serial EEPROM offsets */
#define IPG_EEPROM_CONFIGPARAM 0x00
#define IPG_EEPROM_ASICCTRL 0x01
#define IPG_EEPROM_SUBSYSTEMVENDORID 0x02
#define IPG_EEPROM_SUBSYSTEMID 0x03
#define IPG_EEPROM_STATIONADDRESS0 0x10
#define IPG_EEPROM_STATIONADDRESS1 0x11
#define IPG_EEPROM_STATIONADDRESS2 0x12
/* Register & data structure bit masks */
/* PCI register masks. */
/* IOBaseAddress */
#define IPG_PIB_RSVD_MASK 0xFFFFFE01
#define IPG_PIB_IOBASEADDRESS 0xFFFFFF00
#define IPG_PIB_IOBASEADDRIND 0x00000001
/* MemBaseAddress */
#define IPG_PMB_RSVD_MASK 0xFFFFFE07
#define IPG_PMB_MEMBASEADDRIND 0x00000001
#define IPG_PMB_MEMMAPTYPE 0x00000006
#define IPG_PMB_MEMMAPTYPE0 0x00000002
#define IPG_PMB_MEMMAPTYPE1 0x00000004
#define IPG_PMB_MEMBASEADDRESS 0xFFFFFE00
/* ConfigStatus */
#define IPG_CS_RSVD_MASK 0xFFB0
#define IPG_CS_CAPABILITIES 0x0010
#define IPG_CS_66MHZCAPABLE 0x0020
#define IPG_CS_FASTBACK2BACK 0x0080
#define IPG_CS_DATAPARITYREPORTED 0x0100
#define IPG_CS_DEVSELTIMING 0x0600
#define IPG_CS_SIGNALEDTARGETABORT 0x0800
#define IPG_CS_RECEIVEDTARGETABORT 0x1000
#define IPG_CS_RECEIVEDMASTERABORT 0x2000
#define IPG_CS_SIGNALEDSYSTEMERROR 0x4000
#define IPG_CS_DETECTEDPARITYERROR 0x8000
/* TFD data structure masks. */
/* TFDList, TFC */
#define IPG_TFC_RSVD_MASK 0x0000FFFF9FFFFFFF
#define IPG_TFC_FRAMEID 0x000000000000FFFF
#define IPG_TFC_WORDALIGN 0x0000000000030000
#define IPG_TFC_WORDALIGNTODWORD 0x0000000000000000
#define IPG_TFC_WORDALIGNTOWORD 0x0000000000020000
#define IPG_TFC_WORDALIGNDISABLED 0x0000000000030000
#define IPG_TFC_TCPCHECKSUMENABLE 0x0000000000040000
#define IPG_TFC_UDPCHECKSUMENABLE 0x0000000000080000
#define IPG_TFC_IPCHECKSUMENABLE 0x0000000000100000
#define IPG_TFC_FCSAPPENDDISABLE 0x0000000000200000
#define IPG_TFC_TXINDICATE 0x0000000000400000
#define IPG_TFC_TXDMAINDICATE 0x0000000000800000
#define IPG_TFC_FRAGCOUNT 0x000000000F000000
#define IPG_TFC_VLANTAGINSERT 0x0000000010000000
#define IPG_TFC_TFDDONE 0x0000000080000000
#define IPG_TFC_VID 0x00000FFF00000000
#define IPG_TFC_CFI 0x0000100000000000
#define IPG_TFC_USERPRIORITY 0x0000E00000000000
/* TFDList, FragInfo */
#define IPG_TFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
#define IPG_TFI_FRAGADDR 0x000000FFFFFFFFFF
#define IPG_TFI_FRAGLEN 0xFFFF000000000000LL
/* RFD data structure masks. */
/* RFDList, RFS */
#define IPG_RFS_RSVD_MASK 0x0000FFFFFFFFFFFF
#define IPG_RFS_RXFRAMELEN 0x000000000000FFFF
#define IPG_RFS_RXFIFOOVERRUN 0x0000000000010000
#define IPG_RFS_RXRUNTFRAME 0x0000000000020000
#define IPG_RFS_RXALIGNMENTERROR 0x0000000000040000
#define IPG_RFS_RXFCSERROR 0x0000000000080000
#define IPG_RFS_RXOVERSIZEDFRAME 0x0000000000100000
#define IPG_RFS_RXLENGTHERROR 0x0000000000200000
#define IPG_RFS_VLANDETECTED 0x0000000000400000
#define IPG_RFS_TCPDETECTED 0x0000000000800000
#define IPG_RFS_TCPERROR 0x0000000001000000
#define IPG_RFS_UDPDETECTED 0x0000000002000000
#define IPG_RFS_UDPERROR 0x0000000004000000
#define IPG_RFS_IPDETECTED 0x0000000008000000
#define IPG_RFS_IPERROR 0x0000000010000000
#define IPG_RFS_FRAMESTART 0x0000000020000000
#define IPG_RFS_FRAMEEND 0x0000000040000000
#define IPG_RFS_RFDDONE 0x0000000080000000
#define IPG_RFS_TCI 0x0000FFFF00000000
/* RFDList, FragInfo */
#define IPG_RFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
#define IPG_RFI_FRAGADDR 0x000000FFFFFFFFFF
#define IPG_RFI_FRAGLEN 0xFFFF000000000000LL
/* I/O Register masks. */
/* RMON Statistics Mask */
#define IPG_RZ_ALL 0x0FFFFFFF
/* Statistics Mask */
#define IPG_SM_ALL 0x0FFFFFFF
#define IPG_SM_OCTETRCVOK_FRAMESRCVDOK 0x00000001
#define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002
#define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004
#define IPG_SM_RXJUMBOFRAMES 0x00000008
#define IPG_SM_TCPCHECKSUMERRORS 0x00000010
#define IPG_SM_IPCHECKSUMERRORS 0x00000020
#define IPG_SM_UDPCHECKSUMERRORS 0x00000040
#define IPG_SM_MACCONTROLFRAMESRCVD 0x00000080
#define IPG_SM_FRAMESTOOLONGERRORS 0x00000100
#define IPG_SM_INRANGELENGTHERRORS 0x00000200
#define IPG_SM_FRAMECHECKSEQERRORS 0x00000400
#define IPG_SM_FRAMESLOSTRXERRORS 0x00000800
#define IPG_SM_OCTETXMTOK_FRAMESXMTOK 0x00001000
#define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK 0x00002000
#define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK 0x00004000
#define IPG_SM_FRAMESWDEFERREDXMT 0x00008000
#define IPG_SM_LATECOLLISIONS 0x00010000
#define IPG_SM_MULTICOLFRAMES 0x00020000
#define IPG_SM_SINGLECOLFRAMES 0x00040000
#define IPG_SM_TXJUMBOFRAMES 0x00080000
#define IPG_SM_CARRIERSENSEERRORS 0x00100000
#define IPG_SM_MACCONTROLFRAMESXMTD 0x00200000
#define IPG_SM_FRAMESABORTXSCOLLS 0x00400000
#define IPG_SM_FRAMESWEXDEFERAL 0x00800000
/* Countdown */
#define IPG_CD_RSVD_MASK 0x0700FFFF
#define IPG_CD_COUNT 0x0000FFFF
#define IPG_CD_COUNTDOWNSPEED 0x01000000
#define IPG_CD_COUNTDOWNMODE 0x02000000
#define IPG_CD_COUNTINTENABLED 0x04000000
/* TxDMABurstThresh */
#define IPG_TB_RSVD_MASK 0xFF
/* TxDMAUrgentThresh */
#define IPG_TU_RSVD_MASK 0xFF
/* TxDMAPollPeriod */
#define IPG_TP_RSVD_MASK 0xFF
/* RxDMAUrgentThresh */
#define IPG_RU_RSVD_MASK 0xFF
/* RxDMAPollPeriod */
#define IPG_RP_RSVD_MASK 0xFF
/* ReceiveMode */
#define IPG_RM_RSVD_MASK 0x3F
#define IPG_RM_RECEIVEUNICAST 0x01
#define IPG_RM_RECEIVEMULTICAST 0x02
#define IPG_RM_RECEIVEBROADCAST 0x04
#define IPG_RM_RECEIVEALLFRAMES 0x08
#define IPG_RM_RECEIVEMULTICASTHASH 0x10
#define IPG_RM_RECEIVEIPMULTICAST 0x20
/* PhySet JES20040127EEPROM*/
#define IPG_PS_MEM_LENB9B 0x01
#define IPG_PS_MEM_LEN9 0x02
#define IPG_PS_NON_COMPDET 0x04
/* PhyCtrl */
#define IPG_PC_RSVD_MASK 0xFF
#define IPG_PC_MGMTCLK_LO 0x00
#define IPG_PC_MGMTCLK_HI 0x01
#define IPG_PC_MGMTCLK 0x01
#define IPG_PC_MGMTDATA 0x02
#define IPG_PC_MGMTDIR 0x04
#define IPG_PC_DUPLEX_POLARITY 0x08
#define IPG_PC_DUPLEX_STATUS 0x10
#define IPG_PC_LINK_POLARITY 0x20
#define IPG_PC_LINK_SPEED 0xC0
#define IPG_PC_LINK_SPEED_10MBPS 0x40
#define IPG_PC_LINK_SPEED_100MBPS 0x80
#define IPG_PC_LINK_SPEED_1000MBPS 0xC0
/* DMACtrl */
#define IPG_DC_RSVD_MASK 0xC07D9818
#define IPG_DC_RX_DMA_COMPLETE 0x00000008
#define IPG_DC_RX_DMA_POLL_NOW 0x00000010
#define IPG_DC_TX_DMA_COMPLETE 0x00000800
#define IPG_DC_TX_DMA_POLL_NOW 0x00001000
#define IPG_DC_TX_DMA_IN_PROG 0x00008000
#define IPG_DC_RX_EARLY_DISABLE 0x00010000
#define IPG_DC_MWI_DISABLE 0x00040000
#define IPG_DC_TX_WRITE_BACK_DISABLE 0x00080000
#define IPG_DC_TX_BURST_LIMIT 0x00700000
#define IPG_DC_TARGET_ABORT 0x40000000
#define IPG_DC_MASTER_ABORT 0x80000000
/* ASICCtrl */
#define IPG_AC_RSVD_MASK 0x07FFEFF2
#define IPG_AC_EXP_ROM_SIZE 0x00000002
#define IPG_AC_PHY_SPEED10 0x00000010
#define IPG_AC_PHY_SPEED100 0x00000020
#define IPG_AC_PHY_SPEED1000 0x00000040
#define IPG_AC_PHY_MEDIA 0x00000080
#define IPG_AC_FORCED_CFG 0x00000700
#define IPG_AC_D3RESETDISABLE 0x00000800
#define IPG_AC_SPEED_UP_MODE 0x00002000
#define IPG_AC_LED_MODE 0x00004000
#define IPG_AC_RST_OUT_POLARITY 0x00008000
#define IPG_AC_GLOBAL_RESET 0x00010000
#define IPG_AC_RX_RESET 0x00020000
#define IPG_AC_TX_RESET 0x00040000
#define IPG_AC_DMA 0x00080000
#define IPG_AC_FIFO 0x00100000
#define IPG_AC_NETWORK 0x00200000
#define IPG_AC_HOST 0x00400000
#define IPG_AC_AUTO_INIT
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