1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
|
#ifndef MDP4_XML
#define MDP4_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
Copyright (C) 2013 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
enum mdp4_bpc {
BPC1 = 0,
BPC5 = 1,
BPC6 = 2,
BPC8 = 3,
};
enum mdp4_bpc_alpha {
BPC1A = 0,
BPC4A = 1,
BPC6A = 2,
BPC8A = 3,
};
enum mdp4_alpha_type {
FG_CONST = 0,
BG_CONST = 1,
FG_PIXEL = 2,
BG_PIXEL = 3,
};
enum mdp4_pipe {
VG1 = 0,
VG2 = 1,
RGB1 = 2,
RGB2 = 3,
RGB3 = 4,
VG3 = 5,
VG4 = 6,
};
enum mdp4_mixer {
MIXER0 = 0,
MIXER1 = 1,
MIXER2 = 2,
};
enum mdp4_mixer_stage_id {
STAGE_UNUSED = 0,
STAGE_BASE = 1,
STAGE0 = 2,
STAGE1 = 3,
STAGE2 = 4,
STAGE3 = 5,
};
enum mdp4_intf {
INTF_LCDC_DTV = 0,
INTF_DSI_VIDEO = 1,
INTF_DSI_CMD = 2,
INTF_EBI2_TV = 3,
};
enum mdp4_cursor_format {
CURSOR_ARGB = 1,
CURSOR_XRGB = 2,
};
enum mdp4_dma {
DMA_P = 0,
DMA_S = 1,
DMA_E = 2,
};
#define MDP4_IRQ_OVERLAY0_DONE 0x00000001
#define MDP4_IRQ_OVERLAY1_DONE 0x00000002
#define MDP4_IRQ_DMA_S_DONE 0x00000004
#define MDP4_IRQ_DMA_E_DONE 0x00000008
#define MDP4_IRQ_DMA_P_DONE 0x00000010
#define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
#define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
#define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
#define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
#define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
#define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
#define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
#define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
#define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
#define MDP4_IRQ_OVERLAY2_DONE 0x40000000
#define REG_MDP4_VERSION 0x00000000
#define MDP4_VERSION_MINOR__MASK 0x00ff0000
#define MDP4_VERSION_MINOR__SHIFT 16
static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
{
return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
}
#define MDP4_VERSION_MAJOR__MASK 0xff000000
#define MDP4_VERSION_MAJOR__SHIFT 24
static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
{
return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
}
#define REG_MDP4_OVLP0_KICK 0x00000004
#define REG_MDP4_OVLP1_KICK 0x00000008
#define REG_MDP4_OVLP2_KICK 0x000000d0
#define REG_MDP4_DMA_P_KICK 0x0000000c
#define REG_MDP4_DMA_S_KICK 0x00000010
#define REG_MDP4_DMA_E_KICK 0x00000014
#define REG_MDP4_DISP_STATUS 0x00000018
#define REG_MDP4_DISP_INTF_SEL 0x00000038
#define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
#define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
{
return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
}
#define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
#define MDP4_DISP_INTF_SEL_SEC__SHIFT 2
static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
{
return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
}
#define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
#define MDP4_DISP_INTF_SEL_EXT__SHIFT 4
static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
{
return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;
}
#define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
#define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
#define REG_MDP4_RESET_STATUS 0x0000003c
#define REG_MDP4_READ_CNFG 0x0000004c
#define REG_MDP4_INTR_ENABLE 0x00000050
#define REG_MDP4_INTR_STATUS 0x00000054
#define REG_MDP4_INTR_CLEAR 0x00000058
#define REG_MDP4_EBI2_LCD0 0x00000060
#define REG_MDP4_EBI2_LCD1 0x00000064
#define REG_MDP4_PORTMAP_MODE 0x00000070
#define REG_MDP4_CS_CONTROLLER0 0x000000c0
#define REG_MDP4_CS_CONTROLLER1 0x000000c4
#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
#define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
#define REG_MDP4_VG2_SRC_FORMAT 0x00030050
#define REG_MDP4_VG2_CONST_COLOR 0x00031008
#define REG_MDP4_OVERLAY_FLUSH 0x00018000
#define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
#define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
#define MDP4_OVERLAY_FLUSH_VG1 0x00000004
#define MDP4_OVERLAY_FLUSH_VG2 0x00000008
#define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
#define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
static inline uint32_t __offset_OVLP(uint32_t idx)
{
switch (idx) {
case 0: return 0x00010000;
case 1: return 0x00018000;
case 2: return 0x00088000;
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
#define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;
}
#define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
static inline uint32_t __offset_STAGE(uint32_t idx)
{
switch (idx) {
case 0: return 0x00000104;
case 1: return 0x00000124;
case 2: return 0x00000144;
case 3: return 0x00000160;
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val)
{
return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
}
#define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp4_alpha_type val)
{
return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
}
#define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
#define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
#define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
#define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t __offset_STAGE_CO3(uint32_t idx)
{
switch (idx) {
case 0: return 0x00001004;
case 1: return 0x00001404;
case 2: return 0x00001804;
case 3: return 0x00001b84;
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
#define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
#define REG_MDP4_DMA_P_OP_MODE 0x00090070
static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
#define REG_MDP4_DMA_S_OP_MODE 0x000a0028
static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
static inline uint32_t __offset_DMA(enum mdp4_dma idx)
{
switch (idx) {
case DMA_P: return 0x00090000;
case DMA_S: return 0x000a0000;
case DMA_E: return 0x000b0000;
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp4_bpc val)
{
return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
}
#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp4_bpc val)
{
return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
}
#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp4_bpc val)
{
return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
}
#define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
#define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
#define MDP4_DMA_CONFIG_PACK__SHIFT 8
static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
{
return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;
}
#define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
#define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
#define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;
}
#define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
#define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;
}
#define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
#define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
#define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;
}
#define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
#define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;
}
static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
#define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
#define MDP4_DMA_CURSOR_POS_X__SHIFT 0
static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
{
return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;
}
#define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
#define MDP4_DMA_CURSOR_POS_Y__SHIFT 16
static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
{
return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;
}
static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
#define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1
static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
{
return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK;
}
#define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
#define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;
}
#define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
#define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
#define MDP4_PIPE_SRC_XY_Y__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;
}
#define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
#define MDP4_PIPE_SRC_XY_X__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
}
static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
#define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;
}
#define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
#define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
#define MDP4_PIPE_DST_XY_Y__SHIFT 16
static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
{
return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;
}
#define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
#define MDP4_PIPE_DST_XY_X__SHIFT 0
static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
{
return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
#define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
#define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;
}
#define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
#define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
#define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
#define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;
}
#define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
#define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
}
static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
#define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK;
}
#define MDP4_PIPE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp4_bpc val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp4_bpc val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp4_bpc val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp4_bpc_alpha val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
#define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
#define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9
static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13
static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
#define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
#define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
#define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
#define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;
}
#define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
#define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;
}
#define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
#define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;
}
#define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
#define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
}
static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
#define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
#define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
#define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
#define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
#define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
#define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
#define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
#define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
#define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
#define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
#define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
#define REG_MDP4_LCDC 0x000c0000
#define REG_MDP4_LCDC_ENABLE 0x000c0000
#define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
#define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
#define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
{
return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;
}
#define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
#define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16
static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
{
return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;
}
#define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
#define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
#define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
#define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
#define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
{
return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;
}
#define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
#define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16
static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
{
return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;
}
#define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
#define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
#define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
#define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
#define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
{
return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;
}
#define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
#define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16
static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
{
return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;
}
#define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
#define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
#define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
#define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
#define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
{
return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;
}
#define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
#define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
#define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
#define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
#define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
#define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
#define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
#define REG_MDP4_DTV 0x000d0000
#define REG_MDP4_DTV_ENABLE 0x000d0000
#define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
#define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
#define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
{
return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;
}
#define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
#define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16
static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
{
return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;
}
#define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
#define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
#define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
#define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
#define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
{
return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;
}
#define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
#define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16
static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
{
return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;
}
#define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
#define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
#define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
#define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
#define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
{
return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;
}
#define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
#define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16
static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
{
return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;
}
#define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
#define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
#define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
#define REG_MDP4_DTV_BORDER_CLR 0x000d0040
#define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
#define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
#define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
{
return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;
}
#define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
#define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
#define REG_MDP4_DTV_TEST_CNTL 0x000d004c
#define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
#define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
#define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
#define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
#define REG_MDP4_DSI 0x000e0000
#define REG_MDP4_DSI_ENABLE 0x000e0000
#define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
#define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
#define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
{
return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;
}
#define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
#define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16
static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
{
return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;
}
#define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
#define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
#define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
#define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
#define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
{
return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;
}
#define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
#define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16
static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
{
return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;
}
#define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
#define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
#define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
#define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
#define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
{
return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;
}
#define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
#define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16
static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
{
return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;
}
#define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
#define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
#define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
#define REG_MDP4_DSI_BORDER_CLR 0x000e0028
#define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
#define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
#define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
{
return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;
}
#define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
#define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
#define REG_MDP4_DSI_TEST_CNTL 0x000e0034
#define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
#define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
#define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
#define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004
#endif /* MDP4_XML */
|
