path: root/arch/mips/kvm/kvm_locore.S

/*
* This file is subject to the terms and conditions of the GNU General Public
* License.  See the file "COPYING" in the main directory of this archive
* for more details.
*
* Main entry point for the guest, exception handling.
*
* Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
* Authors: Sanjay Lal <sanjayl@kymasys.com>
*/

#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/asm-offsets.h>


#define _C_LABEL(x)     x
#define MIPSX(name)     mips32_ ## name
#define CALLFRAME_SIZ   32

/*
 * VECTOR
 *  exception vector entrypoint
 */
#define VECTOR(x, regmask)      \
    .ent    _C_LABEL(x),0;      \
    EXPORT(x);

#define VECTOR_END(x)      \
    EXPORT(x);

/* Overload, Danger Will Robinson!! */
#define PT_HOST_ASID        PT_BVADDR
#define PT_HOST_USERLOCAL   PT_EPC

#define CP0_DDATA_LO        $28,3
#define CP0_EBASE           $15,1

#define CP0_INTCTL          $12,1
#define CP0_SRSCTL          $12,2
#define CP0_SRSMAP          $12,3
#define CP0_HWRENA          $7,0

/* Resume Flags */
#define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */

#define RESUME_GUEST            0
#define RESUME_HOST             RESUME_FLAG_HOST

/*
 * __kvm_mips_vcpu_run: entry point to the guest
 * a0: run
 * a1: vcpu
 */

FEXPORT(__kvm_mips_vcpu_run)
    .set    push
    .set    noreorder
    .set    noat

    /* k0/k1 not being used in host kernel context */
	addiu  		k1,sp, -PT_SIZE
    LONG_S	    $0, PT_R0(k1)
    LONG_S     	$1, PT_R1(k1)
    LONG_S     	$2, PT_R2(k1)
    LONG_S     	$3, PT_R3(k1)

    LONG_S     	$4, PT_R4(k1)
    LONG_S     	$5, PT_R5(k1)
    LONG_S     	$6, PT_R6(k1)
    LONG_S     	$7, PT_R7(k1)

    LONG_S     	$8,  PT_R8(k1)
    LONG_S     	$9,  PT_R9(k1)
    LONG_S     	$10, PT_R10(k1)
    LONG_S     	$11, PT_R11(k1)
    LONG_S     	$12, PT_R12(k1)
    LONG_S     	$13, PT_R13(k1)
    LONG_S     	$14, PT_R14(k1)
    LONG_S     	$15, PT_R15(k1)
    LONG_S     	$16, PT_R16(k1)
    LONG_S     	$17, PT_R17(k1)

    LONG_S     	$18, PT_R18(k1)
    LONG_S     	$19, PT_R19(k1)
    LONG_S     	$20, PT_R20(k1)
    LONG_S     	$21, PT_R21(k1)
    LONG_S     	$22, PT_R22(k1)
    LONG_S     	$23, PT_R23(k1)
    LONG_S     	$24, PT_R24(k1)
    LONG_S     	$25, PT_R25(k1)

	/* XXXKYMA k0/k1 not saved, not being used if we got here through an ioctl() */

    LONG_S     	$28, PT_R28(k1)
    LONG_S     	$29, PT_R29(k1)
    LONG_S     	$30, PT_R30(k1)
    LONG_S     	$31, PT_R31(k1)

    /* Save hi/lo */
	mflo		v0
	LONG_S		v0, PT_LO(k1)
	mfhi   		v1
	LONG_S		v1, PT_HI(k1)

	/* Save host status */
	mfc0		v0, CP0_STATUS
	LONG_S		v0, PT_STATUS(k1)

	/* Save host ASID, shove it into the BVADDR location */
	mfc0 		v1,CP0_ENTRYHI
	andi		v1, 0xff
	LONG_S		v1, PT_HOST_ASID(k1)

    /* Save DDATA_LO, will be used to store pointer to vcpu */
    mfc0        v1, CP0_DDATA_LO
    LONG_S      v1, PT_HOST_USERLOCAL(k1)

    /* DDATA_LO has pointer to vcpu */
    mtc0        a1,CP0_DDATA_LO

    /* Offset into vcpu->arch */
	addiu		k1, a1, VCPU_HOST_ARCH

    /* Save the host stack to VCPU, used for exception processing when we exit from the Guest */
    LONG_S      sp, VCPU_HOST_STACK(k1)

    /* Save the kernel gp as well */
    LONG_S      gp, VCPU_HOST_GP(k1)

	/* Setup status register for running the guest in UM, interrupts are disabled */
	li			k0,(ST0_EXL | KSU_USER| ST0_BEV)
	mtc0		k0,CP0_STATUS
    ehb

    /* load up the new EBASE */
    LONG_L      k0, VCPU_GUEST_EBASE(k1)
    mtc0        k0,CP0_EBASE

    /* Now that the new EBASE has been loaded, unset BEV, set interrupt mask as it was
     * but make sure that timer interrupts are enabled
     */
    li          k0,(ST0_EXL | KSU_USER | ST0_IE)
    andi        v0, v0, ST0_IM
    or          k0, k0, v0
    mtc0        k0,CP0_STATUS
    ehb


	/* Set Guest EPC */
	LONG_L		t0, VCPU_PC(k1)
	mtc0		t0, CP0_EPC

FEXPORT(__kvm_mips_load_asid)
    /* Set the ASID for the Guest Kernel */
    sll         t0, t0, 1                       /* with kseg0 @ 0x40000000, kernel */
                                                /* addresses shift to 0x80000000 */
    bltz        t0, 1f                          /* If kernel */
	addiu       t1, k1, VCPU_GUEST_KERNEL_ASID  /* (BD)  */
    addiu       t1, k1, VCPU_GUEST_USER_ASID    /* else user */
1:
    /* t1: contains the base of the ASID array, need to get the cpu id  */
    LONG_L      t2, TI_CPU($28)             /* smp_processor_id */
    sll         t2, t2, 2                   /* x4 */
    addu        t3, t1, t2
    LONG_L      k0, (t3)
    andi        k0, k0, 0xff
	mtc0		k0,CP0_ENTRYHI
    ehb

    /* Disable RDHWR access */
    mtc0    zero,  CP0_HWRENA

    /* Now load up the Guest Context from VCPU */
    LONG_L     	$1, VCPU_R1(k1)
    LONG_L     	$2, VCPU_R2(k1)
    LONG_L     	$3, VCPU_R3(k1)

    LONG_L     	$4, VCPU_R4(k1)
    LONG_L     	$5, VCPU_R5(k1)
    LONG_L     	$6, VCPU_R6(k1)
    LONG_L     	$7, VCPU_R7(k1)

    LONG_L     	$8,  VCPU_R8(k1)
    LONG_L     	$9,  VCPU_R9(k1)
    LONG_L     	$10, VCPU_R10(k1)
    LONG_L     	$11, VCPU_R11(k1)
    LONG_L     	$12, VCPU_R12(k1)
    LONG_L     	$13, VCPU_R13(k1)
    LONG_L     	$14, VCPU_R14(k1)
    LONG_L     	$15, VCPU_R15(k1)
    LONG_L     	$16, VCPU_R16(k1)
    LONG_L     	$17, VCPU_R17(k1)
    LONG_L     	$18, VCPU_R18(k1)
    LONG_L     	$19, VCPU_R19(k1)
    LONG_L     	$20, VCPU_R20(k1)
    LONG_L     	$21, VCPU_R21(k1)
    LONG_L     	$22, VCPU_R22(k1)
    LONG_L     	$23, VCPU_R23(k1)
    LONG_L     	$24, VCPU_R24(k1)
    LONG_L     	$25, VCPU_R25(k1)

    /* k0/k1 loaded up later */

    LONG_L     	$28, VCPU_R28(k1)
    LONG_L     	$29, VCPU_R29(k1)
    LONG_L     	$30, VCPU_R30(k1)
    LONG_L     	$31, VCPU_R31(k1)

    /* Restore hi/lo */
	LONG_L		k0, VCPU_LO(k1)
	mtlo		k0

	LONG_L		k0, VCPU_HI(k1)
	mthi   		k0

FEXPORT(__kvm_mips_load_k0k1)
	/* Restore the guest's k0/k1 registers */
    LONG_L     	k0, VCPU_R26(k1)
    LONG_L     	k1, VCPU_R27(k1)

    /* Jump to guest */
	eret
	.set	pop

VECTOR(MIPSX(exception), unknown)
/*
 * Find out what mode we came from and jump to the proper handler.
 */
    .set    push
	.set	noat
    .set    noreorder
    mtc0    k0, CP0_ERROREPC    #01: Save guest k0
    ehb                         #02:

    mfc0    k0, CP0_EBASE       #02: Get EBASE
    srl     k0, k0, 10          #03: Get rid of CPUNum
    sll     k0, k0, 10          #04
    LONG_S  k1, 0x3000(k0)      #05: Save k1 @ offset 0x3000
    addiu