path: root/arch/metag/tbx/tbipcx.S

/*
 * tbipcx.S
 *
 * Copyright (C) 2001, 2002, 2007, 2009, 2012 Imagination Technologies.
 *
 * This program is free software; you can redistribute it and/or modify it under
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 *
 * Asyncronous trigger handling including exceptions
 */

	.file	"tbipcx.S"
#include <asm/metag_regs.h>
#include <asm/tbx.h>

/* BEGIN HACK */
/* define these for now while doing inital conversion to GAS 
   will fix properly later */

/* Signal identifiers always have the TBID_SIGNAL_BIT set and contain the
   following related bit-fields */
#define TBID_SIGNUM_S       2

/* END HACK */

#ifdef METAC_1_0
/* Ax.4 is saved in TBICTX */
#define A0_4  ,A0.4
#else
/* Ax.4 is NOT saved in TBICTX */
#define A0_4
#endif

/* Size of the TBICTX structure */
#define TBICTX_BYTES ((TBICTX_AX_REGS*8)+TBICTX_AX)

#ifdef METAC_1_1
#ifndef BOOTROM
#ifndef SPECIAL_BUILD
/* Jump straight into the boot ROM version of this code */
#define CODE_USES_BOOTROM
#endif
#endif
#endif

/* Define space needed for CATCH buffer state in traditional units */
#define CATCH_ENTRIES      5
#define CATCH_ENTRY_BYTES 16

#ifndef CODE_USES_BOOTROM
#define A0GblIStP	A0.15  /* PTBICTX for current thread in PRIV system */
#define A1GblIGbP 	A1.15  /* Interrupt A1GbP value in PRIV system */
#endif

/*
 * TBIRES __TBIASyncTrigger( TBIRES State )
 */
	.text
	.balign	4
	.global	___TBIASyncTrigger
	.type	___TBIASyncTrigger,function
___TBIASyncTrigger:
#ifdef CODE_USES_BOOTROM
	MOVT	D0Re0,#HI(LINCORE_BASE)
	JUMP	D0Re0,#0xA0
#else
	MOV	D0FrT,A0FrP			/* Boing entry sequence */
	ADD	A0FrP,A0StP,#0
	SETL	[A0StP++],D0FrT,D1RtP
	MOV	D0Re0,PCX			/* Check for repeat call */
	MOVT	D0FrT,#HI(___TBIBoingRTI+4)
	ADD	D0FrT,D0FrT,#LO(___TBIBoingRTI+4)
	CMP	D0Re0,D0FrT
	BEQ	___TBIBoingExit			/* Already set up - come out */
	ADD	D1Ar1,D1Ar1,#7			/* PRIV system stack here */
	MOV	A0.2,A0StP			/*  else push context here */
	MOVS	D0Re0,D0Ar2			/* Return in user mode? */
	ANDMB	D1Ar1,D1Ar1,#0xfff8		/*  align priv stack to 64-bit */
	MOV	D1Re0,D1Ar1			/*   and set result to arg */
	MOVMI	A0.2,D1Ar1			/*  use priv stack if PRIV set			 */
/*
 * Generate an initial TBICTX to return to our own current call context
 */
	MOVT	D1Ar5,#HI(___TBIBoingExit)	/* Go here to return */
	ADD	D1Ar5,D1Ar5,#LO(___TBIBoingExit)
	ADD	A0.3,A0.2,#TBICTX_DX		/* DX Save area */
	ANDT	D0Ar2,D0Ar2,#TBICTX_PRIV_BIT	/* Extract PRIV bit */
	MOVT	D0Ar6,#TBICTX_SOFT_BIT		/* Only soft thread state */
	ADD	D0Ar6,D0Ar6,D0Ar2		/* Add in PRIV bit if requested */
	SETL	[A0.2],D0Ar6,D1Ar5		/* Push header fields */
	ADD	D0FrT,A0.2,#TBICTX_AX		/* Address AX save area */
	MSETL	[A0.3],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
	MOV	D0Ar6,#0
	MOV	D1Ar5,#0
	SETL	[A0.3++],D0Ar6,D1Ar5		/* Zero CT register states */
	SETL	[A0.3++],D0Ar6,D1Ar5
	MSETL	[D0FrT],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX regs */
	MOV	A0FrP,A0.2			/* Restore me! */
	B	___TBIResume
	.size	___TBIASyncTrigger,.-___TBIASyncTrigger

/*
 * Optimised return to handler for META Core
 */
___TBIBoingRTH:
	RTH					/* Go to background level */
	MOVT	A0.2,     #HI($Lpcx_target)
	ADD	A0.2,A0.2,#LO($Lpcx_target)
	MOV	PCX,A0.2                        /* Setup PCX for interrupts */
	MOV	PC,D1Re0			/* Jump to handler */
/*
 * This is where the code below needs to jump to wait for outermost interrupt
 * event in a non-privilege mode system (single shared interrupt stack).
 */
___TBIBoingPCX:
	MGETL	A0StP,A0FrP,A0.2,A0.3 A0_4,[D1Re0] /* Restore AX regs */
	MOV	TXSTATUS,D0Re0			/* Restore flags */
	GETL	D0Re0,D1Re0,[D1Re0+#TBICTX_DX-TBICTX_BYTES]
___TBIBoingRTI:
	RTI					/* Wait for interrupt */
$Lpcx_target:
/*
 * Save initial interrupt state on current stack
 */
	SETL	[A0StP+#TBICTX_DX],D0Re0,D1Re0	/* Save key registers */
	ADD	D1Re0,A0StP,#TBICTX_AX		/* Address AX save area */
	MOV	D0Re0,TXSTATUS			/* Read TXSTATUS into D0Re0 */
	MOV	TXSTATUS,#0			/* Clear TXSTATUS */
	MSETL	[D1Re0],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX critical regs */
/*
 * Register state at this point is-
 *
 *	D0Re0 - Old TXSTATUS with PRIV and CBUF bits set if appropriate
 *	A0StP - Is call stack frame and base of TBICTX being generated
 *	A1GbP - Is valid static access link
 */
___TBIBoing:
	LOCK0					/* Make sure we have no locks! */
	ADD	A1.2,A0StP,#TBICTX_DX+(8*1)	/* Address DX.1 save area */
	MOV	A0FrP,A0StP			/* Setup frame pointer */
	MSETL	[A1.2],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
	MOV	D0Ar4,TXRPT			/* Save critical CT regs */
	MOV	D1Ar3,TXBPOBITS
	MOV	D1Ar1,TXDIVTIME			/* Calc catch buffer pSrc */
	MOV	D0Ar2,TXMODE
	MOV	TXMODE,#0			/* Clear TXMODE */
#ifdef TXDIVTIME_RPDIRTY_BIT
	TSTT	D1Ar1,#HI(TXDIVTIME_RPDIRTY_BIT)/* NZ = RPDIRTY */
	MOVT	D0Ar6,#TBICTX_CBRP_BIT
	ORNZ	D0Re0,D0Re0,D0Ar6		/* Set CBRP if RPDIRTY set */
#endif
	MSETL	[A1.2],D0Ar4,D0Ar2		/* Save CT regs state */
	MOV	D0Ar2,D0Re0			/* Copy TXSTATUS */
	ANDMT	D0Ar2,D0Ar2,#TBICTX_CBUF_BIT+TBICTX_CBRP_BIT
#ifdef TBI_1_4
	MOVT	D1Ar1,#TBICTX_FPAC_BIT		/* Copy FPActive into FPAC */
	TSTT	D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
	ORNZ	D0Ar2,D0Ar2,D1Ar1
#endif
	MOV	D1Ar1,PCX			/* Read CurrPC */
	ORT	D0Ar2,D0Ar2,#TBICTX_CRIT_BIT	/* SaveMask + CRIT bit */
	SETL	[A0FrP+#TBICTX_Flags],D0Ar2,D1Ar1 /* Set pCtx header fields */
/*
 * Completed context save, now we need to make a call to an interrupt handler
 *
 *	D0Re0 - holds PRIV, WAIT, CBUF flags, HALT reason if appropriate
 *	A0FrP - interrupt stack frame and base of TBICTX being generated
 *	A0StP - same as A0FrP
 */
___TBIBoingWait:
				/* Reserve space for TBICTX and CBUF */
	ADD	A0StP,A0StP,#TBICTX_BYTES+(CATCH_ENTRY_BYTES*CATCH_ENTRIES)
	MOV	D0Ar4,TXSTATI			/* Read the Triggers data */
	MOV	D1Ar3,TXDIVTIME			/* Read IRQEnc bits */
	MOV	D0Ar2,D0Re0			/* Copy PRIV and WAIT flags */
	ANDT	D0Ar2,