path: root/arch/metag/include/asm/metag_regs.h

/*
 * asm/metag_regs.h
 *
 * Copyright (C) 2000-2007, 2012 Imagination Technologies.
 *
 * This program is free software; you can redistribute it and/or modify it under
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 *
 * Various defines for Meta core (non memory-mapped) registers.
 */

#ifndef _ASM_METAG_REGS_H_
#define _ASM_METAG_REGS_H_

/*
 * CHIP Unit Identifiers and Valid/Global register number masks
 * ------------------------------------------------------------
 */
#define TXUCT_ID    0x0     /* Control unit regs */
#ifdef METAC_1_2
#define     TXUCT_MASK  0xFF0FFFFF  /* Valid regs 0..31  */
#else
#define     TXUCT_MASK  0xFF1FFFFF  /* Valid regs 0..31  */
#endif
#define     TGUCT_MASK  0x00000000  /* No global regs    */
#define TXUD0_ID    0x1     /* Data unit regs */
#define TXUD1_ID    0x2
#define     TXUDX_MASK  0xFFFFFFFF  /* Valid regs 0..31 */
#define     TGUDX_MASK  0xFFFF0000  /* Global regs for base inst */
#define     TXUDXDSP_MASK   0x0F0FFFFF  /* Valid DSP regs */
#define     TGUDXDSP_MASK   0x0E0E0000  /* Global DSP ACC regs */
#define TXUA0_ID    0x3     /* Address unit regs */
#define TXUA1_ID    0x4
#define     TXUAX_MASK  0x0000FFFF  /* Valid regs   0-15 */
#define     TGUAX_MASK  0x0000FF00  /* Global regs  8-15 */
#define TXUPC_ID    0x5     /* PC registers */
#define     TXUPC_MASK  0x00000003  /* Valid regs   0- 1 */
#define     TGUPC_MASK  0x00000000  /* No global regs    */
#define TXUPORT_ID  0x6     /* Ports are not registers */
#define TXUTR_ID    0x7
#define     TXUTR_MASK  0x0000005F  /* Valid regs   0-3,4,6 */
#define     TGUTR_MASK  0x00000000  /* No global regs    */
#ifdef METAC_2_1
#define TXUTT_ID    0x8
#define     TXUTT_MASK  0x0000000F  /* Valid regs   0-3 */
#define     TGUTT_MASK  0x00000010  /* Global reg   4   */
#define TXUFP_ID    0x9     /* FPU regs */
#define     TXUFP_MASK  0x0000FFFF  /* Valid regs   0-15 */
#define     TGUFP_MASK  0x00000000  /* No global regs    */
#endif /* METAC_2_1 */

#ifdef METAC_1_2
#define TXUXX_MASKS { TXUCT_MASK, TXUDX_MASK, TXUDX_MASK, TXUAX_MASK, \
		      TXUAX_MASK, TXUPC_MASK,          0, TXUTR_MASK, \
		      0, 0, 0, 0, 0, 0, 0, 0                          }
#define TGUXX_MASKS { TGUCT_MASK, TGUDX_MASK, TGUDX_MASK, TGUAX_MASK, \
		      TGUAX_MASK, TGUPC_MASK,          0, TGUTR_MASK, \
		      0, 0, 0, 0, 0, 0, 0, 0                          }
#else /* METAC_1_2 */
#define TXUXX_MASKS { TXUCT_MASK, TXUDX_MASK, TXUDX_MASK, TXUAX_MASK, \
		      TXUAX_MASK, TXUPC_MASK,          0, TXUTR_MASK, \
		      TXUTT_MASK, TXUFP_MASK,          0,          0, \
			       0,          0,          0,          0  }
#define TGUXX_MASKS { TGUCT_MASK, TGUDX_MASK, TGUDX_MASK, TGUAX_MASK, \
		      TGUAX_MASK, TGUPC_MASK,          0, TGUTR_MASK, \
		      TGUTT_MASK, TGUFP_MASK,          0,          0, \
			       0,          0,          0,          0  }
#endif /* !METAC_1_2 */

#define TXUXXDSP_MASKS { 0, TXUDXDSP_MASK, TXUDXDSP_MASK, 0, 0, 0, 0, 0, \
			 0, 0, 0, 0, 0, 0, 0, 0                          }
#define TGUXXDSP_MASKS { 0, TGUDXDSP_MASK, TGUDXDSP_MASK, 0, 0, 0, 0, 0, \
			 0, 0, 0, 0, 0, 0, 0, 0                          }

/* -------------------------------------------------------------------------
;                          DATA AND ADDRESS UNIT REGISTERS
;  -----------------------------------------------------------------------*/
/*
  Thread local D0 registers
 */
/*   D0.0    ; Holds 32-bit result, can be used as scratch */
#define D0Re0 D0.0
/*   D0.1    ; Used to pass Arg6_32 */
#define D0Ar6 D0.1
/*   D0.2    ; Used to pass Arg4_32 */
#define D0Ar4 D0.2
/*   D0.3    ; Used to pass Arg2_32 to a called routine (see D1.3 below) */
#define D0Ar2 D0.3
/*   D0.4    ; Can be used as scratch; used to save A0FrP in entry sequences */
#define D0FrT D0.4
/*   D0.5    ; C compiler assumes preservation, save with D1.5 if used */
/*   D0.6    ; C compiler assumes preservation, save with D1.6 if used */
/*   D0.7    ; C compiler assumes preservation, save with D1.7 if used */
/*   D0.8    ; Use of D0.8 and above is not encouraged */
/*   D0.9  */
/*   D0.10 */
/*   D0.11 */
/*   D0.12 */
/*   D0.13 */
/*   D0.14 */
/*   D0.15 */
/*
   Thread local D1 registers
 */
/*   D1.0    ; Holds top 32-bits of 64-bit result, can be used as scratch */
#define D1Re0 D1.0
/*   D1.1    ; Used to pass Arg5_32 */
#define D1Ar5 D1.1
/*   D1.2    ; Used to pass Arg3_32 */
#define D1Ar3 D1.2
/*   D1.3    ; Used to pass Arg1_32 (first 32-bit argument) to a called routine */
#define D1Ar1 D1.3
/*   D1.4    ; Used for Return Pointer, save during entry with A0FrP (via D0.4) */
#define D1RtP D1.4
/*   D1.5    ; C compiler assumes preservation, save if used */
/*   D1.6    ; C compiler assumes preservation, save if used */
/*   D1.7    ; C compiler assumes preservation, save if used */
/*   D1.8    ; Use of D1.8 and above is not encouraged */
/*   D1.9  */
/*   D1.10 */
/*   D1.11 */
/*   D1.12 */
/*   D1.13 */
/*   D1.14 */
/*   D1.15 */
/*
   Thread local A0 registers
 */
/*   A0.0    ; Primary stack pointer */
#define A0StP A0.0
/*   A0.1    ; Used as local frame pointer in C, save if used (via D0.4) */
#define A0FrP A0.1
/*   A0.2  */
/*   A0.3  */
/*   A0.4    ; Use of A0.4 and above is not encouraged */
/*   A0.5  */
/*   A0.6  */
/*   A0.7  */
/*
   Thread local A1 registers
 */
/*   A1.0    ; Global static chain pointer - do not modify */
#define A1GbP A1.0
/*   A1.1    ; Local static chain pointer in C, can be used as scratch */
#define A1LbP A1.1
/*   A1.2  */
/*   A1.3  */
/*   A1.4    ; Use of A1.4 and above is not encouraged */
/*   A1.5  */
/*   A1.6  */
/*   A1.7  */
#ifdef METAC_2_1
/* Renameable registers for use with Fast Interrupts */
/* The interrupt stack pointer (usually a global register) */
#define A0IStP A0IReg
/* The interrupt global pointer (usually a global register) */
#define A1IGbP A1IReg
#endif
/*
   Further registers may be globally allocated via linkage/loading tools,
   normally they are not used.
 */
/*-------------------------------------------------------------------------
;                    STACK STRUCTURE and CALLING CONVENTION
; -----------------------------------------------------------------------*/
/*
; Calling convention indicates that the following is the state of the
; stack frame at the start of a routine-
;
;       Arg9_32 [A0StP+#-12]
;       Arg8_32 [A0StP+#- 8]
;       Arg7_32 [A0StP+#- 4]
;   A0StP->
;
; Registers D1.3, D0.3, ..., to D0.1 are used to pass Arg1_32 to Arg6_32
;   respectively. If a routine needs to store them on the stack in order
;   to make sub-calls or because of the general complexity of the routine it
;   is best to dump these registers immediately at the start of a routine
;   using a MSETL or SETL instruction-
;
;   MSETL   [A0StP],D0Ar6,D0Ar4,D0Ar2; Only dump argments expected
;or SETL    [A0StP+#8++],D0Ar2       ; Up to two 32-bit args expected
;
; For non-leaf routines it is always necessary to save and restore at least
; the return address value D1RtP on the stack. Also by convention if the
; frame is saved then a new A0FrP value must be set-up. So for non-leaf
; routines at this point both these registers must be saved onto the stack
; using a SETL instruction and the new A0FrP value is then set-up-
;
;   MOV     D0FrT,A0FrP
;   ADD     A0FrP,A0StP,#0
;   SETL    [A0StP+#8++],D0FrT,D1RtP
;
; Registers D0.5, D1.5, to D1.7 are assumed to be preserved across calls so
;   a SETL or MSETL instruction can be used to save the current state
;   of these registers if they are modified by the current routine-
;
;   MSETL   [A0StP],D0.5,D0.6,D0.7   ; Only save registers modified
;or SETL    [A0StP+#8++],D0.5        ; Only D0.5 and/or D1.5 modified
;
; All of the above sequences can be combined into one maximal case-
;
;   MOV     D0FrT,A0FrP              ; Save and calculate new frame pointer
;   ADD     A0FrP,A0StP,#(ARS)
;   MSETL   [A0StP],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
;
; Having completed the above sequence the only remaining task on routine
; entry is to reserve any local and outgoing argment storage space on the
; stack. This instruction may be omitted if the size of this region is zero-
;
;   ADD     A0StP,A0StP,#(LCS)
;
; LCS is the first example use of one of a number of standard local defined
; values that can be created to make assembler code more readable and
; potentially more robust-
;
; #define ARS   0x18                 ; Register arg bytes saved on stack
; #define FRS   0x20                 ; Frame save area size in bytes
; #define LCS   0x00                 ; Locals and Outgoing arg size
; #define ARO   (LCS+FRS)            ; Stack offset to access args
;
; All of the above defines should be undefined (#undef) at the end of each
; routine to avoid accidental use in the next routine.
;
; Given all of the above the following stack structure is expected during
; the body of a routine if all args passed in registers are saved during
; entry-
;
;                                    ; 'Incoming args area'
;         Arg10_32 [A0StP+#-((10*4)+ARO)]       Arg9_32  [A0StP+#-(( 9*4)+ARO)]
;         Arg8_32  [A0StP+#-(( 8*4)+ARO)]       Arg7_32  [A0StP+#-(( 7*4)+ARO)]
;--- Call point
; D0Ar6=  Arg6_32  [A0StP+#-(( 6*4)+ARO)] D1Ar5=Arg5_32  [A0StP+#-(( 5*4)+ARO)]
; D0Ar4=  Arg4_32  [A0StP+#-(( 4*4)+ARO)] D1Ar3=Arg3_32  [A0StP+#-(( 3*4)+ARO)]
; D0Ar2=  Arg2_32  [A0StP+#-(( 2*4)+ARO)] D1Ar2=Arg1_32  [A0StP+#-(( 1*4)+ARO)]
;                                    ; 'Frame area'
; A0FrP-> D0FrT, D1RtP,
;         D0.5, D1.5,
;         D0.6, D1.6,
;         D0.7, D1.7,
;                                    ; 'Locals area'
;         Loc0_32  [A0StP+# (( 0*4)-LCS)],      Loc1_32 [A0StP+# (( 1*4)-LCS)]
;               .... other locals
;         Locn_32  [A0StP+# (( n*4)-LCS)]
;                                    ; 'Outgoing args area'
;         Outm_32  [A0StP+#- ( m*4)]            .... other outgoing args
;         Out8_32  [A0StP+#- ( 1*4)]            Out7_32  [A0StP+#- ( 1*4)]
; A0StP-> (Out1_32-Out6_32 in regs D1Ar1-D0Ar6)
;
; The exit sequence for a non-leaf routine can use the frame pointer created
; in the entry sequence to optimise the recovery of the full state-
;
;   MGETL   D0FrT,D0.5,D0.6,D0.7,[A0FrP]
;   SUB     A0StP,A0FrP,#(ARS+FRS)