path: root/arch/metag/include/asm/metag_mem.h

/*
 * asm/metag_mem.h
 *
 * Copyright (C) 2000-2007, 2012 Imagination Technologies.
 *
 * This program is free software; you can redistribute it and/or modify it under
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 *
 * Various defines for Meta (memory-mapped) registers.
 */

#ifndef _ASM_METAG_MEM_H_
#define _ASM_METAG_MEM_H_

/*****************************************************************************
 *                   META MEMORY MAP LINEAR ADDRESS VALUES
 ****************************************************************************/
/*
 * COMMON MEMORY MAP
 * -----------------
 */

#define LINSYSTEM_BASE  0x00200000
#define LINSYSTEM_LIMIT 0x07FFFFFF

/* Linear cache flush now implemented via DCACHE instruction. These defines
   related to a special region that used to exist for achieving cache flushes.
 */
#define         LINSYSLFLUSH_S 0

#define     LINSYSRES0_BASE     0x00200000
#define     LINSYSRES0_LIMIT    0x01FFFFFF

#define     LINSYSCUSTOM_BASE 0x02000000
#define     LINSYSCUSTOM_LIMIT   0x02FFFFFF

#define     LINSYSEXPAND_BASE 0x03000000
#define     LINSYSEXPAND_LIMIT   0x03FFFFFF

#define     LINSYSEVENT_BASE  0x04000000
#define         LINSYSEVENT_WR_ATOMIC_UNLOCK    0x04000000
#define         LINSYSEVENT_WR_ATOMIC_LOCK      0x04000040
#define         LINSYSEVENT_WR_CACHE_DISABLE    0x04000080
#define         LINSYSEVENT_WR_CACHE_ENABLE     0x040000C0
#define         LINSYSEVENT_WR_COMBINE_FLUSH    0x04000100
#define         LINSYSEVENT_WR_FENCE            0x04000140
#define     LINSYSEVENT_LIMIT   0x04000FFF

#define     LINSYSCFLUSH_BASE   0x04400000
#define         LINSYSCFLUSH_DCACHE_LINE    0x04400000
#define         LINSYSCFLUSH_ICACHE_LINE    0x04500000
#define         LINSYSCFLUSH_MMCU           0x04700000
#ifndef METAC_1_2
#define         LINSYSCFLUSH_TxMMCU_BASE    0x04700020
#define         LINSYSCFLUSH_TxMMCU_STRIDE  0x00000008
#endif
#define         LINSYSCFLUSH_ADDR_BITS      0x000FFFFF
#define         LINSYSCFLUSH_ADDR_S         0
#define     LINSYSCFLUSH_LIMIT  0x047FFFFF

#define     LINSYSCTRL_BASE     0x04800000
#define     LINSYSCTRL_LIMIT    0x04FFFFFF

#define     LINSYSMTABLE_BASE   0x05000000
#define     LINSYSMTABLE_LIMIT  0x05FFFFFF

#define     LINSYSDIRECT_BASE   0x06000000
#define     LINSYSDIRECT_LIMIT  0x07FFFFFF

#define LINLOCAL_BASE   0x08000000
#define LINLOCAL_LIMIT  0x7FFFFFFF

#define LINCORE_BASE    0x80000000
#define LINCORE_LIMIT   0x87FFFFFF

#define LINCORE_CODE_BASE  0x80000000
#define LINCORE_CODE_LIMIT 0x81FFFFFF

#define LINCORE_DATA_BASE  0x82000000
#define LINCORE_DATA_LIMIT 0x83FFFFFF


/* The core can support locked icache lines in this region */
#define LINCORE_ICACHE_BASE  0x84000000
#define LINCORE_ICACHE_LIMIT 0x85FFFFFF

/* The core can support locked dcache lines in this region */
#define LINCORE_DCACHE_BASE  0x86000000
#define LINCORE_DCACHE_LIMIT 0x87FFFFFF

#define LINGLOBAL_BASE  0x88000000
#define LINGLOBAL_LIMIT 0xFFFDFFFF

/*
 * CHIP Core Register Map
 * ----------------------
 */
#define CORE_HWBASE     0x04800000
#define PRIV_HWBASE     0x04810000
#define TRIG_HWBASE     0x04820000
#define SYSC_HWBASE     0x04830000

/*****************************************************************************
 *         INTER-THREAD KICK REGISTERS FOR SOFTWARE EVENT GENERATION
 ****************************************************************************/
/*
 * These values define memory mapped registers that can be used to supply
 * kicks to threads that service arbitrary software events.
 */

#define T0KICK     0x04800800   /* Background kick 0     */
#define     TXXKICK_MAX 0xFFFF  /* Maximum kicks */
#define     TnXKICK_STRIDE      0x00001000  /* Thread scale value    */
#define     TnXKICK_STRIDE_S    12
#define T0KICKI    0x04800808   /* Interrupt kick 0      */
#define     TXIKICK_OFFSET  0x00000008  /* Int level offset value */
#define T1KICK     0x04801800   /* Background kick 1     */
#define T1KICKI    0x04801808   /* Interrupt kick 1      */
#define T2KICK     0x04802800   /* Background kick 2     */
#define T2KICKI    0x04802808   /* Interrupt kick 2      */
#define T3KICK     0x04803800   /* Background kick 3     */
#define T3KICKI    0x04803808   /* Interrupt kick 3      */

/*****************************************************************************
 *                GLOBAL REGISTER ACCESS RESOURCES
 ****************************************************************************/
/*
 * These values define memory mapped registers that allow access to the
 * internal state of all threads in order to allow global set-up of thread
 * state and external handling of thread events, errors, or debugging.
 *
 * The actual unit and register index values needed to access individul
 * registers are chip specific see - METAC_TXUXX_VALUES in metac_x_y.h.
 * However two C array initialisers TXUXX_MASKS and TGUXX_MASKS will always be
 * defined to allow arbitrary loading, display, and saving of all valid
 * register states without detailed knowledge of their purpose - TXUXX sets
 * bits for all valid registers and TGUXX sets bits for the sub-set which are
 * global.
 */

#define T0UCTREG0   0x04800000  /* Access to all CT regs */
#define TnUCTRX_STRIDE      0x00001000  /* Thread scale value    */
#define TXUCTREGn_STRIDE    0x00000008  /* Register scale value  */

#define TXUXXRXDT  0x0480FFF0   /* Data to/from any threads reg */
#define TXUXXRXRQ  0x0480FFF8
#define     TXUXXRXRQ_DREADY_BIT 0x80000000  /* Poll for done */
#define     TXUXXRXRQ_DSPEXT_BIT 0x00020000  /* Addr DSP Regs */
#define     TXUXXRXRQ_RDnWR_BIT  0x00010000  /* Set for read  */
#define     TXUXXRXRQ_TX_BITS    0x00003000  /* Thread number */
#define     TXUXXRXRQ_TX_S       12
#define     TXUXXRXRQ_RX_BITS    0x000001F0  /* Register num  */
#define     TXUXXRXRQ_RX_S       4
#define         TXUXXRXRQ_DSPRARD0    0      /* DSP RAM A Read Pointer 0 */
#define         TXUXXRXRQ_DSPRARD1    1      /* DSP RAM A Read Pointer 1 */
#define         TXUXXRXRQ_DSPRAWR0    2      /* DSP RAM A Write Pointer 0 */
#define         TXUXXRXRQ_DSPRAWR2    3      /* DSP RAM A Write Pointer 1 */
#define         TXUXXRXRQ_DSPRBRD0    4      /* DSP RAM B Read Pointer 0 */
#define         TXUXXRXRQ_DSPRBRD1    5      /* DSP RAM B Read Pointer 1 */
#define         TXUXXRXRQ_DSPRBWR0    6      /* DSP RAM B Write Pointer 0 */
#define         TXUXXRXRQ_DSPRBWR1    7      /* DSP RAM B Write Pointer 1 */
#define         TXUXXRXRQ_DSPRARINC0  8      /* DSP RAM A Read Increment 0 */
#define         TXUXXRXRQ_DSPRARINC1  9      /* DSP RAM A Read Increment 1 */
#define         TXUXXRXRQ_DSPRAWINC0 10      /* DSP RAM A Write Increment 0 */
#define         TXUXXRXRQ_DSPRAWINC1 11      /* DSP RAM A Write Increment 1 */
#define         TXUXXRXRQ_DSPRBRINC0 12      /* DSP RAM B Read Increment 0 */
#define         TXUXXRXRQ_DSPRBRINC1 13      /* DSP RAM B Read Increment 1 */
#define         TXUXXRXRQ_DSPRBWINC0 14      /* DSP RAM B Write Increment 0 */
#define         TXUXXRXRQ_DSPRBWINC1 15      /* DSP RAM B Write Increment 1 */

#define         TXUXXRXRQ_ACC0L0     16      /* Accumulator 0 bottom 32-bits */
#define         TXUXXRXRQ_ACC1L0     17      /* Accumulator 1 bottom 32-bits */
#define         TXUXXRXRQ_ACC2L0     18      /* Accumulator 2 bottom 32-bits */
#define         TXUXXRXRQ_ACC3L0     19      /* Accumulator 3 bottom 32-bits */
#define         TXUXXRXRQ_ACC0HI     20      /* Accumulator 0 top 8-bits */
#define         TXUXXRXRQ_ACC1HI     21      /* Accumulator 1 top 8-bits */
#define         TXUXXRXRQ_ACC2HI     22      /* Accumulator 2 top 8-bits */
#define         TXUXXRXRQ_ACC3HI     23      /* Accumulator 3 top 8-bits */
#define     TXUXXRXRQ_UXX_BITS   0x0000000F  /* Unit number   */
#define     TXUXXRXRQ_UXX_S      0

/*****************************************************************************
 *          PRIVILEGE CONTROL VALUES FOR MEMORY MAPPED RESOURCES
 ****************************************************************************/
/*
 * These values define memory mapped registers that give control over and
 * the privilege required to access other memory mapped resources. These
 * registers themselves always require privilege to update them.
 */

#define TXPRIVREG_STRIDE    0x8 /* Delta between per-thread regs */
#define TXPRIVREG_STRIDE_S  3

/*
 * Each bit 0 to 15 defines privilege required to access internal register
 * regions 0x04800000 to 0x048FFFFF in 64k chunks
 */
#define T0PIOREG    0x04810100
#define T1PIOREG    0x04810108
#define T2PIOREG    0x04810110
#define T3PIOREG    0x04810118

/*
 * Each bit 0 to 31 defines privilege required to use the pair of
 * system events implemented as writee in the regions 0x04000000 to
 * 0x04000FFF in 2*64 byte chunks.
 */
#define T0PSYREG    0x04810180
#define T1PSYREG    0x04810188
#define T2PSYREG    0x04810190
#define T3PSYREG    0x04810198

/*
 * CHIP PRIV CONTROLS
 * ------------------
 */

/* The TXPIOREG register holds a bit mask directly mappable to
   corresponding addresses in the range 0x04800000 to 049FFFFF */
#define     TXPIOREG_ADDR_BITS  0x1F0000 /* Up to 32x64K bytes */
#define     TXPIOREG_ADDR_S     16

/* Hence based on the _HWBASE values ... */
#define     TXPIOREG_CORE_BIT       (1<<((0x04800000>>16)&0x1F))
#define     TXPIOREG_PRIV_BIT       (1<<((0x04810000>>16)&0x1F))
#define     TXPIOREG_TRIG_BIT       (1<<((0x04820000>>16)&0x1F))
#define     TXPIOREG_SYSC_BIT       (1<<((0x04830000>>16)&0x1F))

#define     TXPIOREG_WRC_BIT          0x00080000  /* Wr combiner reg priv */
#define     TXPIOREG_LOCALBUS_RW_BIT  0x00040000  /* Local bus rd/wr priv */
#define     TXPIOREG_SYSREGBUS_RD_BIT 0x00020000  /* Sys reg bus write priv */
#define     TXPIOREG_SYSREGBUS_WR_BIT 0x00010000  /* Sys reg bus read priv */

/* CORE region privilege controls */
#define T0PRIVCORE 0x04800828
#define         TXPRIVCORE_TXBKICK_BIT   0x001  /* Background kick priv */
#define         TXPRIVCORE_TXIKICK_BIT   0x002  /* Interrupt kick priv  */
#define         TXPRIVCORE_TXAMAREGX_BIT 0x004  /* TXAMAREG4|5|6 priv   */
#define TnPRIVCORE_STRIDE 0x00001000

#define T0PRIVSYSR 0x04810000
#define     TnPRIVSYSR_STRIDE   0x00000008
#define     TnPRIVSYSR_STRIDE_S 3
#define     TXPRIVSYSR_CFLUSH_BIT     0x01
#define     TXPRIVSYSR_MTABLE_BIT     0x02
#define     TXPRIVSYSR_DIRECT_BIT     0x04
#ifdef METAC_1_2
#define     TXPRIVSYSR_ALL_BITS       0x07
#else
#define     TXPRIVSYSR_CORE_BIT       0x08
#define     TXPRIVSYSR_CORECODE_BIT   0x10
#define     TXPRIVSYSR_ALL_BITS       0x1F
#endif
#define T1PRIVSYSR 0x04810008
#define T2PRIVSYSR 0x04810010
#define T3PRIVSYSR 0x04810018

/*****************************************************************************
 *          H/W TRIGGER STATE/LEVEL REGISTERS AND H/W TRIGGER VECTORS
 ****************************************************************************/
/*
 * These values define memory mapped registers that give control over and
 * the state of hardware trigger sources both external to the META processor
 * and internal to it.
 */

#define HWSTATMETA  0x04820000  /* Hardware status/clear META trig */
#define         HWSTATMETA_T0HALT_BITS 0xF
#define         HWSTATMETA_T0HALT_S    0
#define     HWSTATMETA_T0BHALT_BIT 0x1  /* Background HALT */
#define     HWSTATMETA_T0IHALT_BIT 0x2  /* Interrupt HALT  */
#define     HWSTATMETA_T0PHALT_BIT 0x4  /* PF/RO Memory HALT */
#define     HWSTATMETA_T0AMATR_BIT 0x8  /* AMA trigger */
#define     HWSTATMETA_TnINT_S     4    /* Shift by (thread*4) */
#define HWSTATEXT   0x04820010  /* H/W status/clear external trigs  0-31 */
#define HWSTATEXT2  0x04820018  /* H/W status/clear external trigs 32-63 */
#define HWSTATEXT4  0x04820020  /* H/W status/clear external trigs 64-95 */
#define HWSTATEXT6  0x04820028  /* H/W status/clear external trigs 96-128 */
#define HWLEVELEXT  0x04820030  /* Edge/Level type of external trigs  0-31 */
#define HWLEVELEXT2 0x04820038  /* Edge/Level type of external trigs 32-63 */
#define HWLEVELEXT4 0x04820040  /* Edge/Level type of external trigs 64-95 */
#define HWLEVELEXT6 0x04820048  /* Edge/Level type of external trigs 96-128 */