path: root/arch/c6x/platforms/dscr.c

/*
 *  Device State Control Registers driver
 *
 *  Copyright (C) 2011 Texas Instruments Incorporated
 *  Author: Mark Salter <msalter@redhat.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

/*
 * The Device State Control Registers (DSCR) provide SoC level control over
 * a number of peripherals. Details vary considerably among the various SoC
 * parts. In general, the DSCR block will provide one or more configuration
 * registers often protected by a lock register. One or more key values must
 * be written to a lock register in order to unlock the configuration register.
 * The configuration register may be used to enable (and disable in some
 * cases) SoC pin drivers, peripheral clock sources (internal or pin), etc.
 * In some cases, a configuration register is write once or the individual
 * bits are write once. That is, you may be able to enable a device, but
 * will not be able to disable it.
 *
 * In addition to device configuration, the DSCR block may provide registers
 * which are used to reset SoC peripherals, provide device ID information,
 * provide MAC addresses, and other miscellaneous functions.
 */

#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <asm/soc.h>
#include <asm/dscr.h>

#define MAX_DEVSTATE_IDS   32
#define MAX_DEVCTL_REGS     8
#define MAX_DEVSTAT_REGS    8
#define MAX_LOCKED_REGS     4
#define MAX_SOC_EMACS       2

struct rmii_reset_reg {
	u32 reg;
	u32 mask;
};

/*
 * Some registerd may be locked. In order to write to these
 * registers, the key value must first be written to the lockreg.
 */
struct locked_reg {
	u32 reg;	/* offset from base */
	u32 lockreg;	/* offset from base */
	u32 key;	/* unlock key */
};

/*
 * This describes a contiguous area of like control bits used to enable/disable
 * SoC devices. Each controllable device is given an ID which is used by the
 * individual device drivers to control the device state. These IDs start at
 * zero and are assigned sequentially to the control bitfield ranges described
 * by this structure.
 */
struct devstate_ctl_reg {
	u32 reg;		/* register holding the control bits */
	u8  start_id;		/* start id of this range */
	u8  num_ids;		/* number of devices in this range */
	u8  enable_only;	/* bits are write-once to enable only */
	u8  enable;		/* value used to enable device */
	u8  disable;		/* value used to disable device */
	u8  shift;		/* starting (rightmost) bit in range */
	u8  nbits;		/* number of bits per device */
};


/*
 * This describes a region of status bits indicating the state of
 * various devices. This is used internally to wait for status
 * change completion when enabling/disabling a device. Status is
 * optional and not all device controls will have a corresponding
 * status.
 */
struct devstate_stat_reg {
	u32 reg;		/* register holding the status bits */
	u8  start_id;		/* start id of this range */
	u8  num_ids;		/* number of devices in this range */
	u8  enable;		/* value indicating enabled state */
	u8  disable;		/* value indicating disabled state */
	u8  shift;		/* starting (rightmost) bit in range */
	u8  nbits;		/* number of bits per device */
};

struct devstate_info {
	struct devstate_ctl_reg *ctl;
	struct devstate_stat_reg *stat;
};

/* These are callbacks to SOC-specific code. */
struct dscr_ops {
	void (*init)(struct device_node *node);
};

struct dscr_regs {
	spinlock_t		lock;
	void __iomem		*base;
	u32			kick_reg[2];
	u32			kick_key[2];
	struct locked_reg	locked[MAX_LOCKED_REGS];
	struct devstate_info	devstate_info[MAX_DEVSTATE_IDS];
	struct rmii_reset_reg   rmii_resets[MAX_SOC_EMACS];
	struct devstate_ctl_reg devctl[MAX_DEVCTL_REGS];
	struct devstate_stat_reg devstat[MAX_DEVSTAT_REGS];
};

static struct dscr_regs	dscr;

static struct locked_reg *find_locked_reg(u32 reg)
{
	int i;

	for (i = 0; i < MAX_LOCKED_REGS; i++)
		if (dscr.locked[i].key && reg == dscr.locked[i].reg)
			return &dscr.locked[i];
	return NULL;
}

/*
 * Write to a register with one lock
 */
static void dscr_write_locked1(u32 reg, u32 val,
			       u32 lock, u32 key)
{
	void __iomem *reg_addr = dscr.base + reg;
	void __iomem *lock_addr = dscr.base + lock;

	/*
	 * For some registers, the lock is relocked after a short number
	 * of cycles. We have to put the lock write and register write in
	 * the same fetch packet to meet this timing. The .align ensures
	 * the two stw instructions are in the same fetch packet.
	 */
	asm volatile ("b	.s2	0f\n"
		      "nop	5\n"
		      "    .align 5\n"
		      "0:\n"
		      "stw	.D1T2	%3,*%2\n"
		      "stw	.D1T2	%1,*%0\n"
		      :
		      : "a"(reg_addr), "b"(val), "a"(lock_addr), "b"(key)
		);

	/* in case the hw doesn't reset the lock */
	soc_writel(0, lock_addr);
}

/*
 * Write to a register protected by two lock registers
 */
static void dscr_write_locked2(u32 reg, u32 val,
			       u32 lock0, u32 key0,
			       u32 lock1, u32 key1)
{
	soc_writel(key0, dscr.base + lock0);
	soc_writel(key1, dscr.base + lock1);
	soc_writel(val, dscr.base + reg);
	soc_writel(0, dscr.base + lock0);
	soc_writel(0, dscr.base + lock1);
}

static void dscr_write(u32 reg, u32 val)
{
	struct locked_reg *lock;

	lock = find_locked_reg(reg);
	if (lock)
		dscr_write_locked1(reg, val, lock->lockreg, lock->key);
	else if (dscr.kick_key[0])
		dscr_write_locked2(reg, val, dscr.kick_reg[0], dscr.kick_key[0],
				   dscr.kick_reg[1], dscr.kick_key[1]);
	else
		soc_writel(val, dscr.base + reg);
}


/*
 * Drivers can use this interface to enable/disable SoC IP blocks.
 */
void dscr_set_devstate(int id, enum dscr_devstate_t state)
{
	struct devstate_ctl_reg *ctl;
	struct devstate_stat_reg *stat;
	struct devstate_info *info;
	u32 ctl_val, val;
	int ctl_shift, ctl_mask;
	unsigned long flags;

	if (!dscr.base)
		return;

	if (id < 0 || id >= MAX_DEVSTATE_IDS)
		return;

	info = &dscr.devstate_info[id];
	ctl = info->ctl;
	stat = info->stat;

	if (ctl == NULL)
		return;

	ctl_shift = ctl->shift + ctl->nbits * (id - ctl->start_id);
	ctl_mask = ((1 << ctl->nbits) - 1) << ctl_shift;

	switch (state) {
	case DSCR_DEVSTATE_ENABLED:
		ctl_val = ctl->enable << ctl_shift;
		break;
	case DSCR_DEVSTATE_DISABLED:
		if (ctl->enable_only)
			return;
		ctl_val = ctl->disable << ctl_shift;
		break;
	default:
		return;
	}

	spin_lock_irqsave(&dscr.lock, flags);

	val = soc_readl(dscr.base + ctl->reg);
	val &= ~ctl_mask;
	val |= ctl_val;

	dscr_write(ctl->reg, val);

	spin_unlock_irqrestore(&dscr.lock, flags);

	if (!stat)
		return;

	ctl_shift = stat->shift + stat->nbits * (id - stat->start_id);

	if (state == DSCR_DEVSTATE_ENABLED)
		ctl_val = stat->enable;
	else
		ctl_val = stat->disable;

	do {
		val = soc_readl(dscr.base + stat->reg);
		val >>= ctl_shift;
		val &= ((1 << stat->nbits) - 1);
	} while (val != ctl_val);
}
EXPORT_SYMBOL(dscr_set_devstate);

/*
 * Drivers can use this to reset RMII module.
 */
void dscr_rmii_reset(int id, int assert)
{
	struct rmii_reset_reg *r;
	unsigned