path: root/arch/arm/mach-omap2/voltage.c

/*
 * OMAP3/OMAP4 Voltage Management Routines
 *
 * Author: Thara Gopinath	<thara@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 * Lesly A M <x0080970@ti.com>
 *
 * Copyright (C) 2008, 2011 Nokia Corporation
 * Kalle Jokiniemi
 * Paul Walmsley
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Thara Gopinath <thara@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/debugfs.h>
#include <linux/slab.h>

#include <plat/common.h>

#include "prm-regbits-34xx.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"
#include "prcm44xx.h"
#include "prminst44xx.h"
#include "control.h"

#include "voltage.h"

#include "vc.h"
#include "vp.h"

#define VOLTAGE_DIR_SIZE	16


static struct omap_vdd_info **vdd_info;

/*
 * Number of scalable voltage domains.
 */
static int nr_scalable_vdd;

/* XXX document */
static s16 prm_mod_offs;
static s16 prm_irqst_ocp_mod_offs;

static struct dentry *voltage_dir;

/* Init function pointers */
static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
					unsigned long target_volt);

static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
{
	return omap2_prm_read_mod_reg(mod, offset);
}

static void omap3_voltage_write_reg(u32 val, u16 mod, u8 offset)
{
	omap2_prm_write_mod_reg(val, mod, offset);
}

static u32 omap4_voltage_read_reg(u16 mod, u8 offset)
{
	return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
					mod, offset);
}

static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
{
	omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
}

static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
{
	char *sys_ck_name;
	struct clk *sys_ck;
	u32 sys_clk_speed, timeout_val, waittime;

	/*
	 * XXX Clockfw should handle this, or this should be in a
	 * struct record
	 */
	if (cpu_is_omap24xx() || cpu_is_omap34xx())
		sys_ck_name = "sys_ck";
	else if (cpu_is_omap44xx())
		sys_ck_name = "sys_clkin_ck";
	else
		return -EINVAL;

	/*
	 * Sys clk rate is require to calculate vp timeout value and
	 * smpswaittimemin and smpswaittimemax.
	 */
	sys_ck = clk_get(NULL, sys_ck_name);
	if (IS_ERR(sys_ck)) {
		pr_warning("%s: Could not get the sys clk to calculate"
			"various vdd_%s params\n", __func__, vdd->voltdm.name);
		return -EINVAL;
	}
	sys_clk_speed = clk_get_rate(sys_ck);
	clk_put(sys_ck);
	/* Divide to avoid overflow */
	sys_clk_speed /= 1000;

	/* Generic voltage parameters */
	vdd->curr_volt = 1200000;
	vdd->volt_scale = vp_forceupdate_scale_voltage;
	vdd->vp_enabled = false;

	vdd->vp_rt_data.vpconfig_erroroffset =
		(vdd->pmic_info->vp_erroroffset <<
		 vdd->vp_data->vp_common->vpconfig_erroroffset_shift);

	timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
	vdd->vp_rt_data.vlimitto_timeout = timeout_val;
	vdd->vp_rt_data.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
	vdd->vp_rt_data.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;

	waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
				sys_clk_speed) / 1000;
	vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
	vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
	vdd->vp_rt_data.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
	vdd->vp_rt_data.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;

	return 0;
}

/* Voltage debugfs support */
static int vp_volt_debug_get(void *data, u64 *val)
{
	struct omap_vdd_info *vdd = (struct omap_vdd_info *)