path: root/arch/arm/mach-bcmring/csp/chipc/chipcHw.c

/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/

/****************************************************************************/
/**
*  @file    chipcHw.c
*
*  @brief   Low level Various CHIP clock controlling routines
*
*  @note
*
*   These routines provide basic clock controlling functionality only.
*/
/****************************************************************************/

/* ---- Include Files ---------------------------------------------------- */

#include <csp/errno.h>
#include <csp/stdint.h>
#include <csp/module.h>

#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>

#include <csp/reg.h>
#include <csp/delay.h>

/* ---- Private Constants and Types --------------------------------------- */

/* VPM alignment algorithm uses this */
#define MAX_PHASE_ADJUST_COUNT         0xFFFF	/* Max number of times allowed to adjust the phase */
#define MAX_PHASE_ALIGN_ATTEMPTS       10	/* Max number of attempt to align the phase */

/* Local definition of clock type */
#define PLL_CLOCK                      1	/* PLL Clock */
#define NON_PLL_CLOCK                  2	/* Divider clock */

static int chipcHw_divide(int num, int denom)
    __attribute__ ((section(".aramtext")));

/****************************************************************************/
/**
*  @brief   Set clock fequency for miscellaneous configurable clocks
*
*  This function sets clock frequency
*
*  @return  Configured clock frequency in hertz
*
*/
/****************************************************************************/
chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configurable clock */
    ) {
	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
	volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
	uint32_t vcoFreqPll1Hz = 0;	/* Effective VCO frequency for PLL1 in Hz */
	uint32_t vcoFreqPll2Hz = 0;	/* Effective VCO frequency for PLL2 in Hz */
	uint32_t dependentClockType = 0;
	uint32_t vcoHz = 0;

	/* Get VCO frequencies */
	if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
		uint64_t adjustFreq = 0;

		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);

		/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
		adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
			(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
			chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
		vcoFreqPll1Hz += (uint32_t) adjustFreq;
	} else {
		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
	}
	vcoFreqPll2Hz =
	    chipcHw_XTAL_FREQ_Hz *
		 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
	    ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
	     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);

	switch (clock) {
	case chipcHw_CLOCK_DDR:
		pPLLReg = &pChipcHw->DDRClock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_ARM:
		pPLLReg = &pChipcHw->ARMClock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_ESW:
		pPLLReg = &pChipcHw->ESWClock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_VPM:
		pPLLReg = &pChipcHw->VPMClock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_ESW125:
		pPLLReg = &pChipcHw->ESW125Clock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_UART:
		pPLLReg = &pChipcHw->UARTClock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_SDIO0:
		pPLLReg = &pChipcHw->SDIO0Clock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_SDIO1:
		pPLLReg = &pChipcHw->SDIO1Clock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_SPI:
		pPLLReg = &pChipcHw->SPIClock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_ETM:
		pPLLReg = &pChipcHw->ETMClock;
		vcoHz = vcoFreqPll1Hz;
		break;
	case chipcHw_CLOCK_USB:
		pPLLReg = &pChipcHw->USBClock;
		vcoHz = vcoFreqPll2Hz;
		break;
	case chipcHw_CLOCK_LCD:
		pPLLReg = &pChipcHw->LCDClock;
		vcoHz = vcoFreqPll2Hz;
		break;
	case chipcHw_CLOCK_APM:
		pPLLReg = &pChipcHw->APMClock;
		vcoHz = vcoFreqPll2Hz;
		break;
	case chipcHw_CLOCK_BUS:
		pClockCtrl = &pChipcHw->ACLKClock;
		pDependentClock = &pChipcHw->ARMClock;
		vcoHz = vcoFreqPll1Hz;
		dependentClockType = PLL_CLOCK;
		break;
	case chipcHw_CLOCK_OTP:
		pClockCtrl = &pChipcHw->OTPClock;
		break;
	case chipcHw_CLOCK_I2C:
		pClockCtrl = &pChipcHw->I2CClock;
		break;
	case chipcHw_CLOCK_I2S0:
		pClockCtrl = &pChipcHw->I2S0Clock;
		break;
	case chipcHw_CLOCK_RTBUS:
		pClockCtrl = &pChipcHw->RTBUSClock;
		pDependentClock = &pChipcHw->ACLKClock;
		dependentClockType = NON_PLL_CLOCK;
		break;
	case chipcHw_CLOCK_APM100:
		pClockCtrl = &pChipcHw->APM100Clock;
		pDependentClock = &pChipcHw->APMClock;
		vcoHz = vcoFreqPll2Hz;
		dependentClockType = PLL_CLOCK;
		break;
	case chipcHw_CLOCK_TSC:
		pClockCtrl = &pChipcHw->TSCClock;
		break;
	case chipcHw_CLOCK_LED:
		pClockCtrl = &pChipcHw->LEDClock;
		break;
	case chipcHw_CLOCK_I2S1:
		pClockCtrl = &pChipcHw->I2S1Clock;
		break;
	}

	if (pPLLReg) {
		/* Obtain PLL clock frequency */
		if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
			/* Return crystal clock frequency when bypassed */
			return chipcHw_XTAL_FREQ_Hz;
		} else if (clock == chipcHw_CLOCK_DDR) {
			/* DDR frequency is configured in PLLDivider register */
			return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
		} else {
			/* From chip revision number B0, LCD clock