path: root/arch/arm/boot/dts/r8a7791.dtsi

/*
 * Device Tree Source for the r8a7791 SoC
 *
 * Copyright (C) 2013 Renesas Electronics Corporation
 * Copyright (C) 2013-2014 Renesas Solutions Corp.
 * Copyright (C) 2014 Cogent Embedded Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r8a7791-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7791";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		spi0 = &qspi;
		spi1 = &msiof0;
		spi2 = &msiof1;
		spi3 = &msiof2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1500000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			clock-frequency = <1500000000>;
		};
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0xf1001000 0 0x1000>,
			<0 0xf1002000 0 0x1000>,
			<0 0xf1004000 0 0x2000>,
			<0 0xf1006000 0 0x2000>;
		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	gpio0: gpio@e6050000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6050000 0 0x50>;
		interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
	};

	gpio1: gpio@e6051000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6051000 0 0x50>;
		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
	};

	gpio2: gpio@e6052000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6052000 0 0x50>;
		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
	};

	gpio3: gpio@e6053000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6053000 0 0x50>;
		interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
	};

	gpio4: gpio@e6054000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6054000 0 0x50>;
		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
	};

	gpio5: gpio@e6055000 {
		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
		reg = <0 0xe6055000 0 0x50>;
		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;