path: root/arch/arm/boot/dts/prima2.dtsi

/*
 * DTS file for CSR SiRFprimaII SoC
 *
 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

/include/ "skeleton.dtsi"
/ {
	compatible = "sirf,prima2";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			/* from bootloader */
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
			clocks = <&clks 12>;
			operating-points = <
				/* kHz    uV */
				200000  1025000
				400000  1025000
				664000  1050000
				800000  1100000
			>;
			clock-latency = <150000>;
		};
	};

	axi {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x40000000 0x40000000 0x80000000>;

		l2-cache-controller@80040000 {
			compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
			reg = <0x80040000 0x1000>;
			interrupts = <59>;
			arm,tag-latency = <1 1 1>;
			arm,data-latency = <1 1 1>;
			arm,filter-ranges = <0 0x40000000>;
		};

		intc: interrupt-controller@80020000 {
			#interrupt-cells = <1>;
			interrupt-controller;
			compatible = "sirf,prima2-intc";
			reg = <0x80020000 0x1000>;
		};

		sys-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x88000000 0x88000000 0x40000>;

			clks: clock-controller@88000000 {
				compatible = "sirf,prima2-clkc";
				reg = <0x88000000 0x1000>;
				interrupts = <3>;
				#clock-cells = <1>;
			};

			rstc: reset-controller@88010000 {
				compatible = "sirf,prima2-rstc";
				reg = <0x88010000 0x1000>;
				#reset-cells = <1>;
			};

			rsc-controller@88020000 {
				compatible = "sirf,prima2-rsc";
				reg = <0x88020000 0x1000>;
			};

			cphifbg@88030000 {
				compatible = "sirf,prima2-cphifbg";
				reg = <0x88030000 0x1000>;
				clocks = <&clks 42>;
			};
		};

		mem-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x90000000 0x90000000 0x10000>;

			memory-controller@90000000 {
				compatible = "sirf,prima2-memc";
				reg = <0x90000000 0x2000>;
				interrupts = <27>;
				clocks = <&clks 5>;
			};

			memc-monitor {
				compatible = "sirf,prima2-memcmon";
				reg = <0x90002000 0x200>;
				interrupts = <4>;
				clocks = <&clks 32>;
			};
		};

		disp-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x90010000 0x90010000 0x30000>;

			display@90010000 {
				compatible = "sirf,prima2-lcd";
				reg = <0x90010000 0x20000>;
				interrupts = <30>;
			};

			vpp@90020000 {
				compatible = "sirf,prima2-vpp";
				reg = <0x90020000 0x10000>;
				interrupts = <31>;
				clocks = <&clks 35>;
			};
		};

		graphics-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x98000000 0x98000000 0x8000000>;

			graphics@98000000 {
				compatible = "powervr,sgx531";
				reg = <0x98000000 0x8000000>;
				interrupts = <6>;
				clocks = <&clks 32>;
			};
		};

		multimedia-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0xa0000000 0xa0000000 0x8000000>;

			multimedia@a0000000 {
				compatible = "sirf,prima2-video-codec";
				reg = <0xa0000000 0x8000000>;
				interrupts = <5>;
				clocks = <&clks 33>;
			};
		};

		dsp-iobg {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0xa8000000 0xa8000000 0x2000000>;

			dspif@a8000000 {
				compatible = "sirf,prima2-dspif";
				reg = <0xa8000000 0x10000>;
				interrupts = <9>;
			};<