/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx51-pinfunc.h"

/ {
	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &cspi;
	};

	tzic: tz-interrupt-controller@e0000000 {
		compatible = "fsl,imx51-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0xe0000000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <0>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks 24>;
			clock-names = "cpu";
			operating-points = <
				/* kHz  uV (No regulator support) */
				160000  0
				800000  0
			>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		ipu: ipu@40000000 {
			#crtc-cells = <1>;
			compatible = "fsl,imx51-ipu";
			reg = <0x40000000 0x20000000>;
			interrupts = <11 10>;
			clocks = <&clks 59>, <&clks 110>, <&clks 61>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 2>;
		};

		aips@70000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x70000000 0x10000000>;
			ranges;

			spba@70000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x70000000 0x40000>;
				ranges;

				esdhc1: esdhc@70004000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks 44>, <&clks 0>, <&clks 71>;
					clock-names = "ipg", "ahb", "per";
					status = "disabled";
				};

				esdhc2: esdhc@70008000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks 45>, <&clks 0>, <&clks 72>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@7000c000 {
					compatible = "fsl,imx51-uart", "fsl,imx21-uart";
					reg = <0x7000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks 32>, <&clks 33>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@70010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx51-ecspi";
					reg = <0x70010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks 51>, <&clks 52>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@70014000 {
					compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
					reg = <0x70014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks 49>;
					dmas = <&sdma 24 1 0>,
					       <&sdma 25 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>