path: root/arch/arm/boot/dts/exynos5420.dtsi

/*
 * SAMSUNG EXYNOS5420 SoC device tree source
 *
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
 * EXYNOS5420 based board files can include this file and provide
 * values for board specfic bindings.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/clock/exynos5420.h>
#include "exynos5.dtsi"
#include "exynos5420-pinctrl.dtsi"

#include <dt-bindings/clock/exynos-audss-clk.h>

/ {
	compatible = "samsung,exynos5420", "samsung,exynos5";

	aliases {
		mshc0 = &mmc_0;
		mshc1 = &mmc_1;
		mshc2 = &mmc_2;
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		pinctrl3 = &pinctrl_3;
		pinctrl4 = &pinctrl_4;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &hsi2c_4;
		i2c5 = &hsi2c_5;
		i2c6 = &hsi2c_6;
		i2c7 = &hsi2c_7;
		i2c8 = &hsi2c_8;
		i2c9 = &hsi2c_9;
		i2c10 = &hsi2c_10;
		gsc0 = &gsc_0;
		gsc1 = &gsc_1;
		spi0 = &spi_0;
		spi1 = &spi_1;
		spi2 = &spi_2;
		usbdrdphy0 = &usbdrd_phy0;
		usbdrdphy1 = &usbdrd_phy1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;
			clock-frequency = <1800000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;
			clock-frequency = <1800000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x2>;
			clock-frequency = <1800000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x3>;
			clock-frequency = <1800000000>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			clock-frequency = <1000000000>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			clock-frequency = <1000000000>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			clock-frequency = <1000000000>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x103>;
			clock-frequency = <1000000000>;
		};
	};

	sysram@02020000 {
		compatible = "mmio-sram";
		reg = <0x02020000 0x54000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x02020000 0x54000>;

		smp-sysram@0 {
			compatible = "samsung,exynos4210-sysram";
			reg = <0x0 0x1000>;
		};

		smp-sysram@53000 {
			compatible = "samsung,exynos4210-sysram-ns";
			reg = <0x53000 0x1000>;
		};
	};

	clock: clock-controller@10010000 {
		compatible = "samsung,exynos5420-clock";
		reg = <0x10010000 0x30000>;
		#clock-cells = <1>;
	};

	clock_audss: audss-clock-controller@3810000 {
		compatible = "samsung,exynos5420-audss-clock";
		reg = <0x03810000 0x0C>;
		#clock-cells = <1>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
			 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
		clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
	};

	mfc: codec@11000000 {
		compatible = "samsung,mfc-v7";
		reg = <0x11000000 0x10000>;
		interrupts = <0 96 0>;
		clocks = <&clock CLK_MFC>;
		clock-names = "mfc";
		samsung,power-domain = <&mfc_pd>;
	};

	mmc_0: mmc@12200000 {
		compatible = "samsung,exynos5420-dw-mshc-smu";
		interrupts = <0 75 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x12200000 0x2000>;
		clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x40>;
		status = "disabled";
	};

	mmc_1: mmc@12210000 {
		compatible = "samsung,exynos5420-dw-mshc-smu";
		interrupts = <