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path: root/drivers/gpu/drm/nouveau/core/include/engine
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2014-06-11drm/nouveau/disp: add internal representaion of output paths and connectorsBen Skeggs
This will, at some point, be used to replace various bits and pieces of code doing direct bios parsing. For now, it'll just be used for some DP improvements. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-06-11drm/nouveau/disp: nothing to see hereBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-06-10drm/nouveau/graph: add GK20A supportAlexandre Courbot
Add a GR device for GK20A based on NVE4, with the correct classes definitions (GK20A's 3D class is 0xa297). Most of the NVE4 code can be used on GK20A, so make relevant bits of NVE4 available to other chips as well. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-06-10drm/nouveau/fifo: add GK20A supportAlexandre Courbot
GK20A's FIFO is compatible with NVE0, but only features 128 channels and 1 runlist. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-03-26drm/gm107/gr: initial supportBen Skeggs
Our ucode only partially works at this point, so requiring binary fw image for now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-03-26drm/gf104/gr: rename gf104 (nvc4), it came before gf106 (nvc3)Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-03-26support for platform devicesAlexandre Courbot
Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead of PCI to which Nouveau is tightly dependent. This patch allows Nouveau to handle platform devices by: - abstracting PCI-dependent functions that were typically used for resource querying and page mapping, - introducing a nv_device_is_pci() function that allows to make PCI-dependent code conditional, - providing a nouveau_drm_platform_probe() function that takes a GPU platform device to be probed. Core code as well as engine/subdev drivers are updated wherever possible to make use of these functions. Some older drivers are too dependent on PCI to be properly updated, but all newer code on which future chips may depend should at least be runnable with platform devices. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-03-26drm/gm100/device: recognise GM107Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-03-26drm/gm107/disp: initial implementationBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-03-26drm/nv50/disp: preparation for storing static class dataBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-23drm/nv108/gr: initial support (need external fuc)Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-23drm/nv108/fifo: initial supportBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nouveau/perfmon: initial infrastructure to expose performance countersBen Skeggs
Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nouveau/fifo: make external class definitions into pointersBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nv31/mpeg: split the nv31 and nv40 dma setting implementationsIlia Mirkin
NV31 has different config bits than NV40+ do. Also fix the DMA_IMAGE VRAM-only setting to check the right bits. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nv40/mpeg: use the nv31-provided classesIlia Mirkin
Since nv40 only covers pre-nv44 now, it can use the nv31-provided functions. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nv44/mpeg: create a copy of the nv31/nv40 implsIlia Mirkin
The nv31/nv40 impls are actually fairly nv44-specific, since they assume the presence of the instance register/context switching. Create a copy before nv31/nv40 get fixed. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nouveau/sw: prepare for the sharing of constructors between implementationsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nv50-/sw: make vblank tracking data private to the implementationsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-10drm/nouveau: add falcon interrupt handlerMaarten Lankhorst
This prevents 100% cpu usage on fermi cards when the exit interrupt from the secret scrubber is not acked. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvd7/gr: initial supportMaarten Lankhorst
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: make register lists from initvals functionsBen Skeggs
Generated context verified to be the same for all supported chipsets. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: xtensa engine base class implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vdec: fork vp3 implementations from vp2Ilia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: move falcon class to engine/Ben Skeggs
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nv50/vm: remove explicit vm knowledge from enginesBen Skeggs
This reverses the lock ordering between VM and gr/nv84:nvc0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/ce: create engine object for ce2Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-05-02drm/nvf0/disp: expose display class 2.2Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-04-26drm/nouveau/fifo: implement channel creation event generationBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-04-26drm/nouveau/device: have engine object initialised before creationBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-04-26drm/nouveau/device: convert to engine, rather than subdevBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-04-26drm/nvc0-: support NOUVEAU_GETPARAM_GRAPH_UNITSChristoph Bumiller
Signed-off-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-20drm/nouveau/fifo/nvc0-: use interrupt 31 as an event triggerBen Skeggs
Generated if you try and use fifo method 0x20 on any subchannel, appears that it can be safely masked off without stalling the whole GPU. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-20drm/nouveau/disp: port vblank handling to event interfaceBen Skeggs
This removes the nastiness with the interactions between display and software engines when handling vblank semaphore release interrupts. Now, all the semantics are handled in one place (sw) \o/. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-20drm/nouveau: prepare for reporting channel ownerMarcin Slusarz
- record channel owner process name - add some helpers for accessing this information - let nouveau_enum hold additional value (will be needed in the next patch) Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nouveau/core: fix the assumption that NVDEV_XXXX is always under 32Martin Peres
It fixes a bug that would have been introduced when adding more sudevs/engines. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nouveau/ppp: remove nouveau_ppp base classBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29nvc0/ppp: initial implementation of engineMaarten Lankhorst
Will allow use of the engine if firmware (nvXX_fuc086) provided. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29nvc0/vp: initial implementation of engineMaarten Lankhorst
Will allow use of the engine if firmware (nvXX_fuc085) provided. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29nvc0/bsp: initial implementation of engineMaarten Lankhorst
Will allow use of the engine if firmware (nvXX_fuc084) provided. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nouveau/vdec: remove nouveau_{bsp,vp} base classes, use nouveau_engine ↵Ben Skeggs
directly Later chipsets use falcon anyway, and I can't currently see a good need for a shared base class. PPP will get the same treatment once Maarten's patches are merged. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nve0/vp: implement initial support for engineBen Skeggs
Will allow use of the engine if firmware (nvXX_fuc085) provided. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nve0/bsp: implement initial support for engineBen Skeggs
Will allow use of the engine if firmware (nvXX_fuc084) provided. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nvc0/copy: share interrupt handler with nva3Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nouveau/copy: remove nouveau_copy base classBen Skeggs
nva3/nvc0 are using falcon, nve0 is now using engine directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nv98/crypt: use nouveau_falcon base classBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nvd0-nve0/disp: initial implementation of evo channel classesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nv50/disp: create skeleton display/channel object classesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nv50/dmaobj: extend class to allow gpu-specific attributes to be definedBen Skeggs
disp is going to need to be able to create more specific dma objects than was previously possible. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nvd0/dmaobj: duplicate fermi class, will diverge real soon nowBen Skeggs
The hardware dmaobj format completely changed in GF119, so these will need a separate implementation. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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