| Age | Commit message (Expand) | Author |
|---|
| 2012-07-18 | Clk: SPEAr1340: Update sys clock parent array | Vipul Kumar Samar |
| 2012-07-18 | clk: SPEAr1340: Fix clk enable register for uart1 and i2c1. | Vipul Kumar Samar |
| 2012-07-18 | Clk:spear6xx:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar |
| 2012-07-18 | Clk:spear3xx:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar |
| 2012-07-18 | clk:spear1310:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar |
| 2012-07-18 | clk:spear1340:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar |
| 2012-06-25 | clk: SPEAr600: Fix ethernet clock name for DT based probing | Stefan Roese |
| 2012-06-20 | Viresh has moved | Viresh Kumar |
| 2012-05-14 | SPEAr13xx: Add common clock framework support | Viresh Kumar |
| 2012-05-12 | SPEAr: Switch to common clock framework | Viresh Kumar |
| 2012-05-12 | SPEAr: clk: Add General Purpose Timer Synthesizer clock | Viresh Kumar |
| 2012-05-12 | SPEAr: clk: Add Fractional Synthesizer clock | Viresh Kumar |
| 2012-05-12 | SPEAr: clk: Add Auxiliary Synthesizer clock | Viresh Kumar |
| 2012-05-12 | SPEAr: clk: Add VCO-PLL Synthesizer clock | Viresh Kumar |
