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path: root/arch/x86/kernel/cpu
AgeCommit message (Expand)Author
2011-06-23x86, amd: Use _safe() msr access for GartTlbWlk disable codeRoedel, Joerg
2011-06-23x86, amd: Do not enable ARAT feature on AMD processors below family 0x12Boris Ostrovsky
2011-05-23x86, mce, AMD: Fix leaving freed data in a listJulia Lawall
2011-05-23x86, apic: Fix spurious error interrupts triggering on all non-boot APsYouquan Song
2011-05-23x86, AMD: Fix ARAT feature setting againBorislav Petkov
2011-05-23Revert "x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processors"Borislav Petkov
2011-05-09x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processorsBoris Ostrovsky
2011-04-22x86, cpu: Fix regression in AMD errata checking codeHans Rosenfeld
2011-04-22x86, amd: Disable GartTlbWlkErr when BIOS forgets itJoerg Roedel
2011-04-22x86, AMD: Set ARAT feature on AMD processorsBoris Ostrovsky
2011-04-22x86, cpu: Clean up AMD erratum 400 workaroundHans Rosenfeld
2011-04-22x86, cpu: AMD errata checking frameworkHans Rosenfeld
2011-04-14x86, mtrr, pat: Fix one cpu getting out of sync during resumeSuresh Siddha
2011-02-17x86, mtrr: Avoid MTRR reprogramming on BP during boot on UP platformsSuresh Siddha
2011-01-07x86, amd: Fix panic on AMD CPU family 0x15Andreas Herrmann
2010-12-09acpi-cpufreq: fix a memleak when unloading driverZhang Rui
2010-11-22x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUsAndreas Herrmann
2010-10-28x86: detect scattered cpuid features earlierJacob Pan
2010-10-28x86, AMD, MCE thresholding: Fix the MCi_MISCj iteration orderBorislav Petkov
2010-10-28x86, cpu: After uncapping CPUID, re-run CPU feature detectionH. Peter Anvin
2010-08-13x86, vmware: Preset lpj values when on VMware.Alok Kataria
2010-07-05perf_events: Fix resource leak in x86 __hw_perf_event_init()Stephane Eranian
2010-05-26x86, cacheinfo: Turn off L3 cache index disable feature in virtualized enviro...Frank Arnold
2010-05-12x86, AMD: Fix stale cpuid4_info shared_map data in shared_cpu_map cpumasksPrarit Bhargava
2010-05-12x86: Disable large pages on CPUs with Atom erratum AAE44H. Peter Anvin
2010-05-12powernow-k8: Fix frequency reportingMark Langsdorf
2010-04-26perf_events, x86: Implement Intel Westmere/Nehalem-EX supportPeter Zijlstra
2010-04-26x86, cacheinfo: Enable L3 CID only on AMDBorislav Petkov
2010-04-26x86, cacheinfo: Remove NUMA dependency, fix for AMD Fam10h rev D1Borislav Petkov
2010-04-26x86, cacheinfo: Calculate L3 indicesBorislav Petkov
2010-04-26x86, cacheinfo: Add cache index disable sysfs attrs only to L3 cachesBorislav Petkov
2010-04-26x86, cacheinfo: Fix disabling of L3 cache indicesBorislav Petkov
2010-04-26x86, amd: Get multi-node CPU info from NodeId MSR instead of PCI config spaceAndreas Herrmann
2010-04-01x86: Fix sched_clock_cpu for systems with unsynchronized TSCDimitri Sivanich
2010-02-23CPUFREQ: Fix use after free of struct powernow_k8_dataThomas Renninger
2010-02-09x86: Remove "x86 CPU features in debugfs" (CONFIG_X86_CPU_DEBUG)H. Peter Anvin
2010-01-28x86: Reenable TSC sync check at boot, even with NONSTOP_TSCPallipadi, Venkatesh
2010-01-22x86, mce: Thermal monitoring depends on APIC being enabledCyrill Gorcunov
2009-12-18x86: Under BIOS control, restore AP's APIC_LVTTHMR to the BSP valueYong Wang
2009-12-18x86: Fix typo in Intel CPU cache size descriptorDave Jones
2009-12-18x86: Add new Intel CPU cache size descriptorsDave Jones
2009-12-18x86/mce: Set up timer unconditionallyJan Beulich
2009-12-18x86, mce: don't restart timer if disabledHidetoshi Seto
2009-12-18x86, apic: Enable lapic nmi watchdog on AMD Family 11hMikael Pettersson
2009-11-17[CPUFREQ] speedstep-ich: fix error caused by 394122ab144dae4b276d74644a2f11c4...Rusty Russell
2009-11-17[CPUFREQ] acpi-cpufreq: blacklist Intel 0f68: Fix HT detection and put in not...John Villalovos
2009-11-17[CPUFREQ] powernow-k8: Fix test in get_transition_latency()Roel Kluin
2009-11-17[CPUFREQ] longhaul: select Longhaul version 2 for capable CPUsKrzysztof Helt
2009-11-02x86: Fix printk message typo in mtrr cleanup codeDave Jones
2009-10-16x86: Don't print number of MCE banks for every CPURoland Dreier