diff options
Diffstat (limited to 'include/video')
29 files changed, 1783 insertions, 1658 deletions
diff --git a/include/video/Kbuild b/include/video/Kbuild index ad3e622c533..e69de29bb2d 100644 --- a/include/video/Kbuild +++ b/include/video/Kbuild @@ -1,3 +0,0 @@ -header-y += edid.h -header-y += sisfb.h -header-y += uvesafb.h diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h index 28447f1594f..c79f3813192 100644 --- a/include/video/atmel_lcdc.h +++ b/include/video/atmel_lcdc.h @@ -30,38 +30,21 @@ */ #define ATMEL_LCDC_WIRING_BGR 0 #define ATMEL_LCDC_WIRING_RGB 1 -#define ATMEL_LCDC_WIRING_RGB555 2 /* LCD Controller info data structure, stored in device platform_data */ -struct atmel_lcdfb_info { - spinlock_t lock; - struct fb_info *info; - void __iomem *mmio; - int irq_base; - struct work_struct task; - +struct atmel_lcdfb_pdata { unsigned int guard_time; - unsigned int smem_len; - struct platform_device *pdev; - struct clk *bus_clk; - struct clk *lcdc_clk; - -#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC - struct backlight_device *backlight; - u8 bl_power; -#endif bool lcdcon_is_backlight; bool lcdcon_pol_negative; - u8 saved_lcdcon; - u8 default_bpp; u8 lcd_wiring_mode; unsigned int default_lcdcon2; unsigned int default_dmacon; - void (*atmel_lcdfb_power_control)(int on); + void (*atmel_lcdfb_power_control)(struct atmel_lcdfb_pdata *pdata, int on); struct fb_monspecs *default_monspecs; - u32 pseudo_palette[16]; + + struct list_head pwr_gpios; }; #define ATMEL_LCDC_DMABADDR1 0x00 diff --git a/include/video/auo_k190xfb.h b/include/video/auo_k190xfb.h index 609efe8c686..ac329ee1d75 100644 --- a/include/video/auo_k190xfb.h +++ b/include/video/auo_k190xfb.h @@ -22,6 +22,8 @@ */ #define AUOK190X_RESOLUTION_800_600 0 #define AUOK190X_RESOLUTION_1024_768 1 +#define AUOK190X_RESOLUTION_600_800 4 +#define AUOK190X_RESOLUTION_768_1024 5 /* * struct used by auok190x. board specific stuff comes from *board @@ -98,7 +100,6 @@ struct auok190x_board { int gpio_nbusy; int resolution; - int rotation; int quirks; int fps; }; diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h index 5a0e4f9efb5..efed3c3383d 100644 --- a/include/video/da8xx-fb.h +++ b/include/video/da8xx-fb.h @@ -12,10 +12,6 @@ #ifndef DA8XX_FB_H #define DA8XX_FB_H -enum panel_type { - QVGA = 0 -}; - enum panel_shade { MONOCHROME = 0, COLOR_ACTIVE, @@ -27,11 +23,9 @@ enum raster_load_mode { LOAD_PALETTE, }; -struct display_panel { - enum panel_type panel_type; /* QVGA */ - int max_bpp; - int min_bpp; - enum panel_shade panel_shade; +enum da8xx_frame_complete { + DA8XX_FRAME_WAIT, + DA8XX_FRAME_NOWAIT, }; struct da8xx_lcdc_platform_data { @@ -42,7 +36,7 @@ struct da8xx_lcdc_platform_data { }; struct lcd_ctrl_config { - const struct display_panel *p_disp_panel; + enum panel_shade panel_shade; /* AC Bias Pin Frequency */ int ac_bias; @@ -68,18 +62,9 @@ struct lcd_ctrl_config { /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ unsigned char mono_8bit_mode; - /* Invert line clock */ - unsigned char invert_line_clock; - - /* Invert frame clock */ - unsigned char invert_frm_clock; - /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ unsigned char sync_edge; - /* Horizontal and Vertical Sync: Control: 0=ignore */ - unsigned char sync_ctrl; - /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ unsigned char raster_order; @@ -103,5 +88,8 @@ struct lcd_sync_arg { #define FBIPUT_HSYNC _IOW('F', 9, int) #define FBIPUT_VSYNC _IOW('F', 10, int) +/* Proprietary FB_SYNC_ flags */ +#define FB_SYNC_CLK_INVERT 0x40000000 + #endif /* ifndef DA8XX_FB_H */ diff --git a/include/video/display_timing.h b/include/video/display_timing.h new file mode 100644 index 00000000000..28d9d0d566c --- /dev/null +++ b/include/video/display_timing.h @@ -0,0 +1,102 @@ +/* + * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * description of display timings + * + * This file is released under the GPLv2 + */ + +#ifndef __LINUX_DISPLAY_TIMING_H +#define __LINUX_DISPLAY_TIMING_H + +#include <linux/bitops.h> +#include <linux/types.h> + +enum display_flags { + DISPLAY_FLAGS_HSYNC_LOW = BIT(0), + DISPLAY_FLAGS_HSYNC_HIGH = BIT(1), + DISPLAY_FLAGS_VSYNC_LOW = BIT(2), + DISPLAY_FLAGS_VSYNC_HIGH = BIT(3), + + /* data enable flag */ + DISPLAY_FLAGS_DE_LOW = BIT(4), + DISPLAY_FLAGS_DE_HIGH = BIT(5), + /* drive data on pos. edge */ + DISPLAY_FLAGS_PIXDATA_POSEDGE = BIT(6), + /* drive data on neg. edge */ + DISPLAY_FLAGS_PIXDATA_NEGEDGE = BIT(7), + DISPLAY_FLAGS_INTERLACED = BIT(8), + DISPLAY_FLAGS_DOUBLESCAN = BIT(9), + DISPLAY_FLAGS_DOUBLECLK = BIT(10), +}; + +/* + * A single signal can be specified via a range of minimal and maximal values + * with a typical value, that lies somewhere inbetween. + */ +struct timing_entry { + u32 min; + u32 typ; + u32 max; +}; + +/* + * Single "mode" entry. This describes one set of signal timings a display can + * have in one setting. This struct can later be converted to struct videomode + * (see include/video/videomode.h). As each timing_entry can be defined as a + * range, one struct display_timing may become multiple struct videomodes. + * + * Example: hsync active high, vsync active low + * + * Active Video + * Video ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________ + * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync.. + * | | porch | | porch | + * + * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯ + * + * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________ + */ +struct display_timing { + struct timing_entry pixelclock; + + struct timing_entry hactive; /* hor. active video */ + struct timing_entry hfront_porch; /* hor. front porch */ + struct timing_entry hback_porch; /* hor. back porch */ + struct timing_entry hsync_len; /* hor. sync len */ + + struct timing_entry vactive; /* ver. active video */ + struct timing_entry vfront_porch; /* ver. front porch */ + struct timing_entry vback_porch; /* ver. back porch */ + struct timing_entry vsync_len; /* ver. sync len */ + + enum display_flags flags; /* display flags */ +}; + +/* + * This describes all timing settings a display provides. + * The native_mode is the default setting for this display. + * Drivers that can handle multiple videomodes should work with this struct and + * convert each entry to the desired end result. + */ +struct display_timings { + unsigned int num_timings; + unsigned int native_mode; + + struct display_timing **timings; +}; + +/* get one entry from struct display_timings */ +static inline struct display_timing *display_timings_get(const struct + display_timings *disp, + unsigned int index) +{ + if (disp->num_timings > index) + return disp->timings[index]; + else + return NULL; +} + +void display_timings_release(struct display_timings *disp); + +#endif diff --git a/include/video/edid.h b/include/video/edid.h index c5f19870491..0cb8b2a92b7 100644 --- a/include/video/edid.h +++ b/include/video/edid.h @@ -1,14 +1,9 @@ #ifndef __linux_video_edid_h__ #define __linux_video_edid_h__ -struct edid_info { - unsigned char dummy[128]; -}; +#include <uapi/video/edid.h> -#ifdef __KERNEL__ #ifdef CONFIG_X86 extern struct edid_info edid_info; #endif -#endif - #endif /* __linux_video_edid_h__ */ diff --git a/include/video/exynos_dp.h b/include/video/exynos_dp.h deleted file mode 100644 index bd8cabd344d..00000000000 --- a/include/video/exynos_dp.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Samsung SoC DP device support - * - * Copyright (C) 2012 Samsung Electronics Co., Ltd. - * Author: Jingoo Han <jg1.han@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _EXYNOS_DP_H -#define _EXYNOS_DP_H - -#define DP_TIMEOUT_LOOP_COUNT 100 -#define MAX_CR_LOOP 5 -#define MAX_EQ_LOOP 5 - -enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a -}; - -enum link_lane_count_type { - LANE_COUNT1 = 1, - LANE_COUNT2 = 2, - LANE_COUNT4 = 4 -}; - -enum link_training_state { - START, - CLOCK_RECOVERY, - EQUALIZER_TRAINING, - FINISHED, - FAILED -}; - -enum voltage_swing_level { - VOLTAGE_LEVEL_0, - VOLTAGE_LEVEL_1, - VOLTAGE_LEVEL_2, - VOLTAGE_LEVEL_3, -}; - -enum pre_emphasis_level { - PRE_EMPHASIS_LEVEL_0, - PRE_EMPHASIS_LEVEL_1, - PRE_EMPHASIS_LEVEL_2, - PRE_EMPHASIS_LEVEL_3, -}; - -enum pattern_set { - PRBS7, - D10_2, - TRAINING_PTN1, - TRAINING_PTN2, - DP_NONE -}; - -enum color_space { - COLOR_RGB, - COLOR_YCBCR422, - COLOR_YCBCR444 -}; - -enum color_depth { - COLOR_6, - COLOR_8, - COLOR_10, - COLOR_12 -}; - -enum color_coefficient { - COLOR_YCBCR601, - COLOR_YCBCR709 -}; - -enum dynamic_range { - VESA, - CEA -}; - -enum pll_status { - PLL_UNLOCKED, - PLL_LOCKED -}; - -enum clock_recovery_m_value_type { - CALCULATED_M, - REGISTER_M -}; - -enum video_timing_recognition_type { - VIDEO_TIMING_FROM_CAPTURE, - VIDEO_TIMING_FROM_REGISTER -}; - -enum analog_power_block { - AUX_BLOCK, - CH0_BLOCK, - CH1_BLOCK, - CH2_BLOCK, - CH3_BLOCK, - ANALOG_TOTAL, - POWER_ALL -}; - -struct video_info { - char *name; - - bool h_sync_polarity; - bool v_sync_polarity; - bool interlaced; - - enum color_space color_space; - enum dynamic_range dynamic_range; - enum color_coefficient ycbcr_coeff; - enum color_depth color_depth; - - enum link_rate_type link_rate; - enum link_lane_count_type lane_count; -}; - -struct exynos_dp_platdata { - struct video_info *video_info; - - void (*phy_init)(void); - void (*phy_exit)(void); -}; - -#endif /* _EXYNOS_DP_H */ diff --git a/include/video/exynos_mipi_dsim.h b/include/video/exynos_mipi_dsim.h index 83ce5e667d4..6a578f8a1b3 100644 --- a/include/video/exynos_mipi_dsim.h +++ b/include/video/exynos_mipi_dsim.h @@ -216,11 +216,11 @@ struct mipi_dsim_config { * automatically. * @e_clk_src: select byte clock source. * @pd: pointer to MIPI-DSI driver platform data. + * @phy: pointer to the MIPI-DSI PHY */ struct mipi_dsim_device { struct device *dev; int id; - struct resource *res; struct clk *clock; unsigned int irq; void __iomem *reg_base; @@ -237,6 +237,7 @@ struct mipi_dsim_device { bool suspended; struct mipi_dsim_platform_data *pd; + struct phy *phy; }; /* @@ -249,7 +250,6 @@ struct mipi_dsim_device { * @enabled: indicate whether mipi controller got enabled or not. * @lcd_panel_info: pointer for lcd panel specific structure. * this structure specifies width, height, timing and polarity and so on. - * @phy_enable: pointer to a callback controlling D-PHY enable/reset */ struct mipi_dsim_platform_data { char lcd_panel_name[PANEL_NAME_SIZE]; @@ -257,8 +257,6 @@ struct mipi_dsim_platform_data { struct mipi_dsim_config *dsim_config; unsigned int enabled; void *lcd_panel_info; - - int (*phy_enable)(struct platform_device *pdev, bool on); }; /* diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h new file mode 100644 index 00000000000..3e43e22cdff --- /dev/null +++ b/include/video/imx-ipu-v3.h @@ -0,0 +1,347 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef __DRM_IPU_H__ +#define __DRM_IPU_H__ + +#include <linux/types.h> +#include <linux/videodev2.h> +#include <linux/bitmap.h> +#include <linux/fb.h> + +struct ipu_soc; + +enum ipuv3_type { + IPUV3EX, + IPUV3M, + IPUV3H, +}; + +#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3') + +/* + * Bitfield of Display Interface signal polarities. + */ +struct ipu_di_signal_cfg { + unsigned datamask_en:1; + unsigned interlaced:1; + unsigned odd_field_first:1; + unsigned clksel_en:1; + unsigned clkidle_en:1; + unsigned data_pol:1; /* true = inverted */ + unsigned clk_pol:1; /* true = rising edge */ + unsigned enable_pol:1; + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; + + u16 width; + u16 height; + u32 pixel_fmt; + u16 h_start_width; + u16 h_sync_width; + u16 h_end_width; + u16 v_start_width; + u16 v_sync_width; + u16 v_end_width; + u32 v_to_h_sync; + unsigned long pixelclock; +#define IPU_DI_CLKMODE_SYNC (1 << 0) +#define IPU_DI_CLKMODE_EXT (1 << 1) + unsigned long clkflags; + + u8 hsync_pin; + u8 vsync_pin; +}; + +enum ipu_color_space { + IPUV3_COLORSPACE_RGB, + IPUV3_COLORSPACE_YUV, + IPUV3_COLORSPACE_UNKNOWN, +}; + +struct ipuv3_channel; + +enum ipu_channel_irq { + IPU_IRQ_EOF = 0, + IPU_IRQ_NFACK = 64, + IPU_IRQ_NFB4EOF = 128, + IPU_IRQ_EOS = 192, +}; + +int ipu_map_irq(struct ipu_soc *ipu, int irq); +int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, + enum ipu_channel_irq irq); + +#define IPU_IRQ_DP_SF_START (448 + 2) +#define IPU_IRQ_DP_SF_END (448 + 3) +#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END, +#define IPU_IRQ_DC_FC_0 (448 + 8) +#define IPU_IRQ_DC_FC_1 (448 + 9) +#define IPU_IRQ_DC_FC_2 (448 + 10) +#define IPU_IRQ_DC_FC_3 (448 + 11) +#define IPU_IRQ_DC_FC_4 (448 + 12) +#define IPU_IRQ_DC_FC_6 (448 + 13) +#define IPU_IRQ_VSYNC_PRE_0 (448 + 14) +#define IPU_IRQ_VSYNC_PRE_1 (448 + 15) + +/* + * IPU Image DMA Controller (idmac) functions + */ +struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel); +void ipu_idmac_put(struct ipuv3_channel *); + +int ipu_idmac_enable_channel(struct ipuv3_channel *channel); +int ipu_idmac_disable_channel(struct ipuv3_channel *channel); +int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms); + +void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, + bool doublebuffer); +int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel); +void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num); + +/* + * IPU Display Controller (dc) functions + */ +struct ipu_dc; +struct ipu_di; +struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel); +void ipu_dc_put(struct ipu_dc *dc); +int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, + u32 pixel_fmt, u32 width); +void ipu_dc_enable(struct ipu_soc *ipu); +void ipu_dc_enable_channel(struct ipu_dc *dc); +void ipu_dc_disable_channel(struct ipu_dc *dc); +void ipu_dc_disable(struct ipu_soc *ipu); + +/* + * IPU Display Interface (di) functions + */ +struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); +void ipu_di_put(struct ipu_di *); +int ipu_di_disable(struct ipu_di *); +int ipu_di_enable(struct ipu_di *); +int ipu_di_get_num(struct ipu_di *); +int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig); + +/* + * IPU Display Multi FIFO Controller (dmfc) functions + */ +struct dmfc_channel; +int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc); +void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc); +int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc, + unsigned long bandwidth_mbs, int burstsize); +void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc); +int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width); +struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); +void ipu_dmfc_put(struct dmfc_channel *dmfc); + +/* + * IPU Display Processor (dp) functions + */ +#define IPU_DP_FLOW_SYNC_BG 0 +#define IPU_DP_FLOW_SYNC_FG 1 +#define IPU_DP_FLOW_ASYNC0_BG 2 +#define IPU_DP_FLOW_ASYNC0_FG 3 +#define IPU_DP_FLOW_ASYNC1_BG 4 +#define IPU_DP_FLOW_ASYNC1_FG 5 + +struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); +void ipu_dp_put(struct ipu_dp *); +int ipu_dp_enable(struct ipu_soc *ipu); +int ipu_dp_enable_channel(struct ipu_dp *dp); +void ipu_dp_disable_channel(struct ipu_dp *dp); +void ipu_dp_disable(struct ipu_soc *ipu); +int ipu_dp_setup_channel(struct ipu_dp *dp, + enum ipu_color_space in, enum ipu_color_space out); +int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos); +int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha, + bool bg_chan); + +/* + * IPU CMOS Sensor Interface (csi) functions + */ +int ipu_csi_enable(struct ipu_soc *ipu, int csi); +int ipu_csi_disable(struct ipu_soc *ipu, int csi); + +/* + * IPU Sensor Multiple FIFO Controller (SMFC) functions + */ +int ipu_smfc_enable(struct ipu_soc *ipu); +int ipu_smfc_disable(struct ipu_soc *ipu); +int ipu_smfc_map_channel(struct ipu_soc *ipu, int channel, int csi_id, int mipi_id); +int ipu_smfc_set_burstsize(struct ipu_soc *ipu, int channel, int burstsize); + +#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size)) + +#define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22) +#define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22) +#define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4) +#define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1) +#define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1) +#define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14) +#define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14) + +#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10) +#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9) +#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13) +#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12) +#define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1) +#define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1) +#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12) +#define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11) +#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10) +#define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7) +#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10) +#define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1) +#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1) +#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7) +#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1) +#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1) +#define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3) +#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2) +#define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1) +#define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3) +#define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2) +#define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1) +#define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1) +#define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1) +#define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1) +#define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1) +#define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1) +#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13) +#define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12) +#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29) +#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29) +#define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20) +#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7) +#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4) +#define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1) +#define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3) +#define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2) +#define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7) +#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14) +#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3) +#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3) +#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3) +#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3) +#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5) +#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5) +#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5) +#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5) +#define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1) +#define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1) +#define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1) + +struct ipu_cpmem_word { + u32 data[5]; + u32 res[3]; +}; + +struct ipu_ch_param { + struct ipu_cpmem_word word[2]; +}; + +void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v); +u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs); +struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel); +void ipu_ch_param_dump(struct ipu_ch_param __iomem *p); + +static inline void ipu_ch_param_zero(struct ipu_ch_param __iomem *p) +{ + int i; + void __iomem *base = p; + + for (i = 0; i < sizeof(*p) / sizeof(u32); i++) + writel(0, base + i * sizeof(u32)); +} + +static inline void ipu_cpmem_set_buffer(struct ipu_ch_param __iomem *p, + int bufnum, dma_addr_t buf) +{ + if (bufnum) + ipu_ch_param_write_field(p, IPU_FIELD_EBA1, buf >> 3); + else + ipu_ch_param_write_field(p, IPU_FIELD_EBA0, buf >> 3); +} + +static inline void ipu_cpmem_set_resolution(struct ipu_ch_param __iomem *p, + int xres, int yres) +{ + ipu_ch_param_write_field(p, IPU_FIELD_FW, xres - 1); + ipu_ch_param_write_field(p, IPU_FIELD_FH, yres - 1); +} + +static inline void ipu_cpmem_set_stride(struct ipu_ch_param __iomem *p, + int stride) +{ + ipu_ch_param_write_field(p, IPU_FIELD_SLY, stride - 1); +} + +void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel); + +struct ipu_rgb { + struct fb_bitfield red; + struct fb_bitfield green; + struct fb_bitfield blue; + struct fb_bitfield transp; + int bits_per_pixel; +}; + +struct ipu_image { + struct v4l2_pix_format pix; + struct v4l2_rect rect; + dma_addr_t phys; +}; + +int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p, + int width); + +int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *, + const struct ipu_rgb *rgb); + +static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param *p, + int stride) +{ + ipu_ch_param_write_field(p, IPU_FIELD_SO, 1); + ipu_ch_param_write_field(p, IPU_FIELD_ILO, stride / 8); + ipu_ch_param_write_field(p, IPU_FIELD_SLY, (stride * 2) - 1); +}; + +void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format, + int stride, int height); +void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p, + u32 pixel_format); +void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p, + u32 pixel_format, int stride, int u_offset, int v_offset); +int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat); +int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem, + struct ipu_image *image); + +enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc); +enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat); + +static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem *p, + int burstsize) +{ + ipu_ch_param_write_field(p, IPU_FIELD_NPB, burstsize - 1); +}; + +struct ipu_client_platformdata { + int csi; + int di; + int dc; + int dp; + int dmfc; + int dma[2]; +}; + +#endif /* __DRM_IPU_H__ */ diff --git a/include/video/mmp_disp.h b/include/video/mmp_disp.h new file mode 100644 index 00000000000..9fd9398368d --- /dev/null +++ b/include/video/mmp_disp.h @@ -0,0 +1,358 @@ +/* + * linux/include/video/mmp_disp.h + * Header file for Marvell MMP Display Controller + * + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Authors: Zhou Zhu <zzhu3@marvell.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#ifndef _MMP_DISP_H_ +#define _MMP_DISP_H_ +#include <linux/kthread.h> + +enum { + PIXFMT_UYVY = 0, + PIXFMT_VYUY, + PIXFMT_YUYV, + PIXFMT_YUV422P, + PIXFMT_YVU422P, + PIXFMT_YUV420P, + PIXFMT_YVU420P, + PIXFMT_RGB565 = 0x100, + PIXFMT_BGR565, + PIXFMT_RGB1555, + PIXFMT_BGR1555, + PIXFMT_RGB888PACK, + PIXFMT_BGR888PACK, + PIXFMT_RGB888UNPACK, + PIXFMT_BGR888UNPACK, + PIXFMT_RGBA888, + PIXFMT_BGRA888, + PIXFMT_RGB666, /* for output usage */ + PIXFMT_PSEUDOCOLOR = 0x200, +}; + +static inline int pixfmt_to_stride(int pix_fmt) +{ + switch (pix_fmt) { + case PIXFMT_RGB565: + case PIXFMT_BGR565: + case PIXFMT_RGB1555: + case PIXFMT_BGR1555: + case PIXFMT_UYVY: + case PIXFMT_VYUY: + case PIXFMT_YUYV: + return 2; + case PIXFMT_RGB888UNPACK: + case PIXFMT_BGR888UNPACK: + case PIXFMT_RGBA888: + case PIXFMT_BGRA888: + return 4; + case PIXFMT_RGB888PACK: + case PIXFMT_BGR888PACK: + return 3; + case PIXFMT_YUV422P: + case PIXFMT_YVU422P: + case PIXFMT_YUV420P: + case PIXFMT_YVU420P: + case PIXFMT_PSEUDOCOLOR: + return 1; + default: + return 0; + } +} + +/* parameters used by path/overlay */ +/* overlay related para: win/addr */ +struct mmp_win { + /* position/size of window */ + u16 xsrc; + u16 ysrc; + u16 xdst; + u16 ydst; + u16 xpos; + u16 ypos; + u16 left_crop; + u16 right_crop; + u16 up_crop; + u16 bottom_crop; + int pix_fmt; + /* + * pitch[0]: graphics/video layer line length or y pitch + * pitch[1]/pitch[2]: video u/v pitch if non-zero + */ + u32 pitch[3]; +}; + +struct mmp_addr { + /* phys address */ + u32 phys[6]; +}; + +/* path related para: mode */ +struct mmp_mode { + const char *name; + u32 refresh; + u32 xres; + u32 yres; + u32 left_margin; + u32 right_margin; + u32 upper_margin; + u32 lower_margin; + u32 hsync_len; + u32 vsync_len; + u32 hsync_invert; + u32 vsync_invert; + u32 invert_pixclock; + u32 pixclock_freq; + int pix_fmt_out; +}; + +/* main structures */ +struct mmp_path; +struct mmp_overlay; +struct mmp_panel; + +/* status types */ +enum { + MMP_OFF = 0, + MMP_ON, +}; + +static inline const char *stat_name(int stat) +{ + switch (stat) { + case MMP_OFF: + return "OFF"; + case MMP_ON: + return "ON"; + default: + return "UNKNOWNSTAT"; + } +} + +struct mmp_overlay_ops { + /* should be provided by driver */ + void (*set_fetch)(struct mmp_overlay *overlay, int fetch_id); + void (*set_onoff)(struct mmp_overlay *overlay, int status); + void (*set_win)(struct mmp_overlay *overlay, struct mmp_win *win); + int (*set_addr)(struct mmp_overlay *overlay, struct mmp_addr *addr); +}; + +/* overlay describes a z-order indexed slot in each path. */ +struct mmp_overlay { + int id; + const char *name; + struct mmp_path *path; + + /* overlay info: private data */ + int dmafetch_id; + struct mmp_addr addr; + struct mmp_win win; + + /* state */ + int open_count; + int status; + struct mutex access_ok; + + struct mmp_overlay_ops *ops; +}; + +/* panel type */ +enum { + PANELTYPE_ACTIVE = 0, + PANELTYPE_SMART, + PANELTYPE_TV, + PANELTYPE_DSI_CMD, + PANELTYPE_DSI_VIDEO, +}; + +struct mmp_panel { + /* use node to register to list */ + struct list_head node; + const char *name; + /* path name used to connect to proper path configed */ + const char *plat_path_name; + struct device *dev; + int panel_type; + void *plat_data; + int (*get_modelist)(struct mmp_panel *panel, + struct mmp_mode **modelist); + void (*set_mode)(struct mmp_panel *panel, + struct mmp_mode *mode); + void (*set_onoff)(struct mmp_panel *panel, + int status); +}; + +struct mmp_path_ops { + int (*check_status)(struct mmp_path *path); + struct mmp_overlay *(*get_overlay)(struct mmp_path *path, + int overlay_id); + int (*get_modelist)(struct mmp_path *path, + struct mmp_mode **modelist); + + /* follow ops should be provided by driver */ + void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode); + void (*set_onoff)(struct mmp_path *path, int status); + /* todo: add query */ +}; + +/* path output types */ +enum { + PATH_OUT_PARALLEL, + PATH_OUT_DSI, + PATH_OUT_HDMI, +}; + +/* path is main part of mmp-disp */ +struct mmp_path { + /* use node to register to list */ + struct list_head node; + + /* init data */ + struct device *dev; + + int id; + const char *name; + int output_type; + struct mmp_panel *panel; + void *plat_data; + + /* dynamic use */ + struct mmp_mode mode; + + /* state */ + int open_count; + int status; + struct mutex access_ok; + + struct mmp_path_ops ops; + + /* layers */ + int overlay_num; + struct mmp_overlay overlays[0]; +}; + +extern struct mmp_path *mmp_get_path(const char *name); +static inline void mmp_path_set_mode(struct mmp_path *path, + struct mmp_mode *mode) +{ + if (path) + path->ops.set_mode(path, mode); +} +static inline void mmp_path_set_onoff(struct mmp_path *path, int status) +{ + if (path) + path->ops.set_onoff(path, status); +} +static inline int mmp_path_get_modelist(struct mmp_path *path, + struct mmp_mode **modelist) +{ + if (path) + return path->ops.get_modelist(path, modelist); + return 0; +} +static inline struct mmp_overlay *mmp_path_get_overlay( + struct mmp_path *path, int overlay_id) +{ + if (path) + return path->ops.get_overlay(path, overlay_id); + return NULL; +} +static inline void mmp_overlay_set_fetch(struct mmp_overlay *overlay, + int fetch_id) +{ + if (overlay) + overlay->ops->set_fetch(overlay, fetch_id); +} +static inline void mmp_overlay_set_onoff(struct mmp_overlay *overlay, + int status) +{ + if (overlay) + overlay->ops->set_onoff(overlay, status); +} +static inline void mmp_overlay_set_win(struct mmp_overlay *overlay, + struct mmp_win *win) +{ + if (overlay) + overlay->ops->set_win(overlay, win); +} +static inline int mmp_overlay_set_addr(struct mmp_overlay *overlay, + struct mmp_addr *addr) +{ + if (overlay) + return overlay->ops->set_addr(overlay, addr); + return 0; +} + +/* + * driver data is set from each detailed ctrl driver for path usage + * it defined a common interface that plat driver need to implement + */ +struct mmp_path_info { + /* driver data, set when registed*/ + const char *name; + struct device *dev; + int id; + int output_type; + int overlay_num; + void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode); + void (*set_onoff)(struct mmp_path *path, int status); + struct mmp_overlay_ops *overlay_ops; + void *plat_data; +}; + +extern struct mmp_path *mmp_register_path( + struct mmp_path_info *info); +extern void mmp_unregister_path(struct mmp_path *path); +extern void mmp_register_panel(struct mmp_panel *panel); +extern void mmp_unregister_panel(struct mmp_panel *panel); + +/* defintions for platform data */ +/* interface for buffer driver */ +struct mmp_buffer_driver_mach_info { + const char *name; + const char *path_name; + int overlay_id; + int dmafetch_id; + int default_pixfmt; +}; + +/* interface for controllers driver */ +struct mmp_mach_path_config { + const char *name; + int overlay_num; + int output_type; + u32 path_config; + u32 link_config; + u32 dsi_rbswap; +}; + +struct mmp_mach_plat_info { + const char *name; + const char *clk_name; + int path_num; + struct mmp_mach_path_config *paths; +}; + +/* interface for panel drivers */ +struct mmp_mach_panel_info { + const char *name; + void (*plat_set_onoff)(int status); + const char *plat_path_name; +}; +#endif /* _MMP_DISP_H_ */ diff --git a/include/video/of_display_timing.h b/include/video/of_display_timing.h new file mode 100644 index 00000000000..79e6697af6c --- /dev/null +++ b/include/video/of_display_timing.h @@ -0,0 +1,23 @@ +/* + * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * display timings of helpers + * + * This file is released under the GPLv2 + */ + +#ifndef __LINUX_OF_DISPLAY_TIMING_H +#define __LINUX_OF_DISPLAY_TIMING_H + +struct device_node; +struct display_timing; +struct display_timings; + +#define OF_USE_NATIVE_MODE -1 + +int of_get_display_timing(struct device_node *np, const char *name, + struct display_timing *dt); +struct display_timings *of_get_display_timings(struct device_node *np); +int of_display_timings_exist(struct device_node *np); + +#endif diff --git a/include/video/of_videomode.h b/include/video/of_videomode.h new file mode 100644 index 00000000000..a07efcc5142 --- /dev/null +++ b/include/video/of_videomode.h @@ -0,0 +1,18 @@ +/* + * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * videomode of-helpers + * + * This file is released under the GPLv2 + */ + +#ifndef __LINUX_OF_VIDEOMODE_H +#define __LINUX_OF_VIDEOMODE_H + +struct device_node; +struct videomode; + +int of_get_videomode(struct device_node *np, struct videomode *vm, + int index); + +#endif /* __LINUX_OF_VIDEOMODE_H */ diff --git a/include/video/omap-panel-data.h b/include/video/omap-panel-data.h new file mode 100644 index 00000000000..69279c013ac --- /dev/null +++ b/include/video/omap-panel-data.h @@ -0,0 +1,254 @@ +/* + * Header containing platform_data structs for omap panels + * + * Copyright (C) 2013 Texas Instruments + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + * Archit Taneja <archit@ti.com> + * + * Copyright (C) 2011 Texas Instruments + * Author: Mayuresh Janorkar <mayur@ti.com> + * + * Copyright (C) 2010 Canonical Ltd. + * Author: Bryan Wu <bryan.wu@canonical.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __OMAP_PANEL_DATA_H +#define __OMAP_PANEL_DATA_H + +#include <video/omapdss.h> +#include <video/display_timing.h> + +struct omap_dss_device; + +/** + * encoder_tfp410 platform data + * @name: name for this display entity + * @power_down_gpio: gpio number for PD pin (or -1 if not available) + * @data_lines: number of DPI datalines + */ +struct encoder_tfp410_platform_data { + const char *name; + const char *source; + int power_down_gpio; + int data_lines; +}; + +/** + * encoder_tpd12s015 platform data + * @name: name for this display entity + * @ct_cp_hpd_gpio: CT_CP_HPD gpio number + * @ls_oe_gpio: LS_OE gpio number + * @hpd_gpio: HPD gpio number + */ +struct encoder_tpd12s015_platform_data { + const char *name; + const char *source; + + int ct_cp_hpd_gpio; + int ls_oe_gpio; + int hpd_gpio; +}; + +/** + * connector_dvi platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + * @i2c_bus_num: i2c bus number to be used for reading EDID + */ +struct connector_dvi_platform_data { + const char *name; + const char *source; + int i2c_bus_num; +}; + +/** + * connector_hdmi platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + */ +struct connector_hdmi_platform_data { + const char *name; + const char *source; +}; + +/** + * connector_atv platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + * @connector_type: composite/svideo + * @invert_polarity: invert signal polarity + */ +struct connector_atv_platform_data { + const char *name; + const char *source; + + enum omap_dss_venc_type connector_type; + bool invert_polarity; +}; + +/** + * panel_dpi platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + * @data_lines: number of DPI datalines + * @display_timing: timings for this panel + * @backlight_gpio: gpio to enable/disable the backlight (or -1) + * @enable_gpio: gpio to enable/disable the panel (or -1) + */ +struct panel_dpi_platform_data { + const char *name; + const char *source; + + int data_lines; + + const struct display_timing *display_timing; + + int backlight_gpio; + int enable_gpio; +}; + +/** + * panel_dsicm platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + * @reset_gpio: gpio to reset the panel (or -1) + * @use_ext_te: use external TE GPIO + * @ext_te_gpio: external TE GPIO + * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms) + * @use_dsi_backlight: true if panel uses DSI command to control backlight + * @pin_config: DSI pin configuration + */ +struct panel_dsicm_platform_data { + const char *name; + const char *source; + + int reset_gpio; + + bool use_ext_te; + int ext_te_gpio; + + unsigned ulps_timeout; + + bool use_dsi_backlight; + + struct omap_dsi_pin_config pin_config; +}; + +/** + * panel_acx565akm platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + * @reset_gpio: gpio to reset the panel (or -1) + * @datapairs: number of SDI datapairs + */ +struct panel_acx565akm_platform_data { + const char *name; + const char *source; + + int reset_gpio; + + int datapairs; +}; + +/** + * panel_lb035q02 platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + * @data_lines: number of DPI datalines + * @backlight_gpio: gpio to enable/disable the backlight (or -1) + * @enable_gpio: gpio to enable/disable the panel (or -1) + */ +struct panel_lb035q02_platform_data { + const char *name; + const char *source; + + int data_lines; + + int backlight_gpio; + int enable_gpio; +}; + +/** + * panel_sharp_ls037v7dw01 platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + * @data_lines: number of DPI datalines + * @resb_gpio: reset signal GPIO + * @ini_gpio: power on control GPIO + * @mo_gpio: selection for resolution(VGA/QVGA) GPIO + * @lr_gpio: selection for horizontal scanning direction GPIO + * @ud_gpio: selection for vertical scanning direction GPIO + */ +struct panel_sharp_ls037v7dw01_platform_data { + const char *name; + const char *source; + + int data_lines; + + int resb_gpio; + int ini_gpio; + int mo_gpio; + int lr_gpio; + int ud_gpio; +}; + +/** + * panel-tpo-td043mtea1 platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + * @data_lines: number of DPI datalines + * @nreset_gpio: reset signal + */ +struct panel_tpo_td043mtea1_platform_data { + const char *name; + const char *source; + + int data_lines; + + int nreset_gpio; +}; + +/** + * panel-nec-nl8048hl11 platform data + * @name: name for this display entity + * @source: name of the display entity used as a video source + * @data_lines: number of DPI datalines + * @res_gpio: reset signal + * @qvga_gpio: selection for resolution(QVGA/WVGA) + */ +struct panel_nec_nl8048hl11_platform_data { + const char *name; + const char *source; + + int data_lines; + + int res_gpio; + int qvga_gpio; +}; + +/** + * panel-tpo-td028ttec1 platform data + * @name: name for display entity + * @source: name of the display entity used as a video source + * @data_lines: number of DPI datalines + */ +struct panel_tpo_td028ttec1_platform_data { + const char *name; + const char *source; + + int data_lines; +}; + +#endif /* __OMAP_PANEL_DATA_H */ diff --git a/include/video/omap-panel-generic-dpi.h b/include/video/omap-panel-generic-dpi.h deleted file mode 100644 index 127e3f20328..00000000000 --- a/include/video/omap-panel-generic-dpi.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Header for generic DPI panel driver - * - * Copyright (C) 2010 Canonical Ltd. - * Author: Bryan Wu <bryan.wu@canonical.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __OMAP_PANEL_GENERIC_DPI_H -#define __OMAP_PANEL_GENERIC_DPI_H - -struct omap_dss_device; - -/** - * struct panel_generic_dpi_data - panel driver configuration data - * @name: panel name - * @platform_enable: platform specific panel enable function - * @platform_disable: platform specific panel disable function - */ -struct panel_generic_dpi_data { - const char *name; - int (*platform_enable)(struct omap_dss_device *dssdev); - void (*platform_disable)(struct omap_dss_device *dssdev); -}; - -#endif /* __OMAP_PANEL_GENERIC_DPI_H */ diff --git a/include/video/omap-panel-n8x0.h b/include/video/omap-panel-n8x0.h deleted file mode 100644 index 50a1302e2cf..00000000000 --- a/include/video/omap-panel-n8x0.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef __OMAP_PANEL_N8X0_H -#define __OMAP_PANEL_N8X0_H - -struct omap_dss_device; - -struct panel_n8x0_data { - int (*platform_enable)(struct omap_dss_device *dssdev); - void (*platform_disable)(struct omap_dss_device *dssdev); - int panel_reset; - int ctrl_pwrdown; - - int (*set_backlight)(struct omap_dss_device *dssdev, int level); -}; - -#endif diff --git a/include/video/omap-panel-nokia-dsi.h b/include/video/omap-panel-nokia-dsi.h deleted file mode 100644 index 04219a29553..00000000000 --- a/include/video/omap-panel-nokia-dsi.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef __OMAP_NOKIA_DSI_PANEL_H -#define __OMAP_NOKIA_DSI_PANEL_H - -struct omap_dss_device; - -/** - * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration - * @name: panel name - * @use_ext_te: use external TE - * @ext_te_gpio: external TE GPIO - * @esd_interval: interval of ESD checks, 0 = disabled (ms) - * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms) - * @use_dsi_backlight: true if panel uses DSI command to control backlight - * @pin_config: DSI pin configuration - */ -struct nokia_dsi_panel_data { - const char *name; - - int reset_gpio; - - bool use_ext_te; - int ext_te_gpio; - - unsigned esd_interval; - unsigned ulps_timeout; - - bool use_dsi_backlight; - - struct omap_dsi_pin_config pin_config; -}; - -#endif /* __OMAP_NOKIA_DSI_PANEL_H */ diff --git a/include/video/omap-panel-picodlp.h b/include/video/omap-panel-picodlp.h deleted file mode 100644 index 1c342ef6f3a..00000000000 --- a/include/video/omap-panel-picodlp.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * panel data for picodlp panel - * - * Copyright (C) 2011 Texas Instruments - * - * Author: Mayuresh Janorkar <mayur@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __PANEL_PICODLP_H -#define __PANEL_PICODLP_H -/** - * struct : picodlp panel data - * picodlp_adapter_id: i2c_adapter number for picodlp - */ -struct picodlp_panel_data { - int picodlp_adapter_id; - int emu_done_gpio; - int pwrgood_gpio; -}; -#endif /* __PANEL_PICODLP_H */ diff --git a/include/video/omap-panel-tfp410.h b/include/video/omap-panel-tfp410.h deleted file mode 100644 index 68c31d79c57..00000000000 --- a/include/video/omap-panel-tfp410.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Header for TFP410 chip driver - * - * Copyright (C) 2011 Texas Instruments Inc - * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __OMAP_PANEL_TFP410_H -#define __OMAP_PANEL_TFP410_H - -struct omap_dss_device; - -/** - * struct tfp410_platform_data - panel driver configuration data - * @i2c_bus_num: i2c bus id for the panel - * @power_down_gpio: gpio number for PD pin (or -1 if not available) - */ -struct tfp410_platform_data { - u16 i2c_bus_num; - int power_down_gpio; -}; - -#endif /* __OMAP_PANEL_TFP410_H */ diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 3729173b7fb..fc06c5b5f12 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -21,6 +21,9 @@ #include <linux/list.h> #include <linux/kobject.h> #include <linux/device.h> +#include <linux/interrupt.h> + +#include <video/videomode.h> #define DISPC_IRQ_FRAMEDONE (1 << 0) #define DISPC_IRQ_VSYNC (1 << 1) @@ -55,6 +58,7 @@ struct omap_dss_device; struct omap_overlay_manager; +struct dss_lcd_mgr_config; struct snd_aes_iec958; struct snd_cea_861_aud_if; @@ -66,6 +70,7 @@ enum omap_display_type { OMAP_DISPLAY_TYPE_DSI = 1 << 3, OMAP_DISPLAY_TYPE_VENC = 1 << 4, OMAP_DISPLAY_TYPE_HDMI = 1 << 5, + OMAP_DISPLAY_TYPE_DVI = 1 << 6, }; enum omap_plane { @@ -158,7 +163,6 @@ enum omap_display_caps { enum omap_dss_display_state { OMAP_DSS_DISPLAY_DISABLED = 0, OMAP_DSS_DISPLAY_ACTIVE, - OMAP_DSS_DISPLAY_SUSPENDED, }; enum omap_dss_audio_state { @@ -168,6 +172,11 @@ enum omap_dss_audio_state { OMAP_DSS_AUDIO_PLAYING, }; +struct omap_dss_audio { + struct snd_aes_iec958 *iec; + struct snd_cea_861_aud_if *cea; +}; + enum omap_dss_rotation_type { OMAP_DSS_ROT_DMA = 1 << 0, OMAP_DSS_ROT_VRFB = 1 << 1, @@ -241,25 +250,33 @@ struct rfbi_timings { int converted; }; -void omap_rfbi_write_command(const void *buf, u32 len); -void omap_rfbi_read_data(void *buf, u32 len); -void omap_rfbi_write_data(const void *buf, u32 len); -void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, - u16 x, u16 y, - u16 w, u16 h); -int omap_rfbi_enable_te(bool enable, unsigned line); -int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, - unsigned hs_pulse_time, unsigned vs_pulse_time, - int hs_pol_inv, int vs_pol_inv, int extif_div); -void rfbi_bus_lock(void); -void rfbi_bus_unlock(void); - /* DSI */ +enum omap_dss_dsi_trans_mode { + /* Sync Pulses: both sync start and end packets sent */ + OMAP_DSS_DSI_PULSE_MODE, + /* Sync Events: only sync start packets sent */ + OMAP_DSS_DSI_EVENT_MODE, + /* Burst: only sync start packets sent, pixels are time compressed */ + OMAP_DSS_DSI_BURST_MODE, +}; + struct omap_dss_dsi_videomode_timings { + unsigned long hsclk; + + unsigned ndl; + unsigned bitspp; + + /* pixels */ + u16 hact; + /* lines */ + u16 vact; + /* DSI video mode blanking data */ /* Unit: byte clock cycles */ + u16 hss; u16 hsa; + u16 hse; u16 hfp; u16 hbp; /* Unit: line clocks */ @@ -273,56 +290,48 @@ struct omap_dss_dsi_videomode_timings { int hbp_blanking_mode; int hfp_blanking_mode; - /* Video port sync events */ - bool vp_vsync_end; - bool vp_hsync_end; + enum omap_dss_dsi_trans_mode trans_mode; bool ddr_clk_always_on; int window_sync; }; -void dsi_bus_lock(struct omap_dss_device *dssdev); -void dsi_bus_unlock(struct omap_dss_device *dssdev); -int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, - int len); -int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, - int len); -int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd); -int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel); -int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, - u8 param); -int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, - u8 param); -int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, - u8 param1, u8 param2); -int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, - u8 *data, int len); -int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, - u8 *data, int len); -int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, - u8 *buf, int buflen); -int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, - int buflen); -int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, - u8 *buf, int buflen); -int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, - u8 param1, u8 param2, u8 *buf, int buflen); -int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, - u16 len); -int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); -int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); -int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel); -void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel); +struct omap_dss_dsi_config { + enum omap_dss_dsi_mode mode; + enum omap_dss_dsi_pixel_format pixel_format; + const struct omap_video_timings *timings; + + unsigned long hs_clk_min, hs_clk_max; + unsigned long lp_clk_min, lp_clk_max; + + bool ddr_clk_always_on; + enum omap_dss_dsi_trans_mode trans_mode; +}; + +enum omapdss_version { + OMAPDSS_VER_UNKNOWN = 0, + OMAPDSS_VER_OMAP24xx, + OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */ + OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */ + OMAPDSS_VER_OMAP3630, + OMAPDSS_VER_AM35xx, + OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */ + OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */ + OMAPDSS_VER_OMAP4, /* All other OMAP4s */ + OMAPDSS_VER_OMAP5, + OMAPDSS_VER_AM43xx, +}; /* Board specific data */ struct omap_dss_board_info { - int (*get_context_loss_count)(struct device *dev); int num_devices; struct omap_dss_device **devices; struct omap_dss_device *default_device; + const char *default_display_name; int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask); int (*set_min_bus_tput)(struct device *dev, unsigned long r); + enum omapdss_version version; }; /* Init with the board info */ @@ -335,8 +344,8 @@ struct omap_video_timings { u16 x_res; /* Unit: pixels */ u16 y_res; - /* Unit: KHz */ - u32 pixel_clock; + /* Unit: Hz */ + u32 pixelclock; /* Unit: pixel clocks */ u16 hsw; /* Horizontal synchronization pulse width */ /* Unit: pixel clocks */ @@ -380,8 +389,8 @@ struct omap_dss_cpr_coefs { }; struct omap_overlay_info { - u32 paddr; - u32 p_uv_addr; /* for NV12 format */ + dma_addr_t paddr; + dma_addr_t p_uv_addr; /* for NV12 format */ u16 screen_width; u16 width; u16 height; @@ -466,7 +475,7 @@ struct omap_overlay_manager { enum omap_dss_output_id supported_outputs; /* dynamic fields */ - struct omap_dss_output *output; + struct omap_dss_device *output; /* * The following functions do not block: @@ -480,7 +489,7 @@ struct omap_overlay_manager { */ int (*set_output)(struct omap_overlay_manager *mgr, - struct omap_dss_output *output); + struct omap_dss_device *output); int (*unset_output)(struct omap_overlay_manager *mgr); int (*set_manager_info)(struct omap_overlay_manager *mgr, @@ -523,30 +532,188 @@ struct omap_dss_writeback_info { u8 pre_mult_alpha; }; -struct omap_dss_output { - struct list_head list; +struct omapdss_dpi_ops { + int (*connect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + void (*disconnect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); - /* display type supported by the output */ - enum omap_display_type type; + int (*enable)(struct omap_dss_device *dssdev); + void (*disable)(struct omap_dss_device *dssdev); - /* output instance */ - enum omap_dss_output_id id; + int (*check_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*set_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*get_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); - /* output's platform device pointer */ - struct platform_device *pdev; + void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines); +}; - /* dynamic fields */ - struct omap_overlay_manager *manager; +struct omapdss_sdi_ops { + int (*connect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + void (*disconnect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); - struct omap_dss_device *device; + int (*enable)(struct omap_dss_device *dssdev); + void (*disable)(struct omap_dss_device *dssdev); + + int (*check_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*set_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*get_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + + void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs); +}; + +struct omapdss_dvi_ops { + int (*connect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + void (*disconnect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + + int (*enable)(struct omap_dss_device *dssdev); + void (*disable)(struct omap_dss_device *dssdev); + + int (*check_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*set_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*get_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); +}; + +struct omapdss_atv_ops { + int (*connect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + void (*disconnect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + + int (*enable)(struct omap_dss_device *dssdev); + void (*disable)(struct omap_dss_device *dssdev); + + int (*check_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*set_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*get_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + + void (*set_type)(struct omap_dss_device *dssdev, + enum omap_dss_venc_type type); + void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev, + bool invert_polarity); + + int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); + u32 (*get_wss)(struct omap_dss_device *dssdev); +}; + +struct omapdss_hdmi_ops { + int (*connect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + void (*disconnect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + + int (*enable)(struct omap_dss_device *dssdev); + void (*disable)(struct omap_dss_device *dssdev); + + int (*check_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*set_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + void (*get_timings)(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); + + int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); + bool (*detect)(struct omap_dss_device *dssdev); + + /* + * Note: These functions might sleep. Do not call while + * holding a spinlock/readlock. + */ + int (*audio_enable)(struct omap_dss_device *dssdev); + void (*audio_disable)(struct omap_dss_device *dssdev); + bool (*audio_supported)(struct omap_dss_device *dssdev); + int (*audio_config)(struct omap_dss_device *dssdev, + struct omap_dss_audio *audio); + /* Note: These functions may not sleep */ + int (*audio_start)(struct omap_dss_device *dssdev); + void (*audio_stop)(struct omap_dss_device *dssdev); +}; + +struct omapdss_dsi_ops { + int (*connect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + void (*disconnect)(struct omap_dss_device *dssdev, + struct omap_dss_device *dst); + + int (*enable)(struct omap_dss_device *dssdev); + void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes, + bool enter_ulps); + + /* bus configuration */ + int (*set_config)(struct omap_dss_device *dssdev, + const struct omap_dss_dsi_config *cfg); + int (*configure_pins)(struct omap_dss_device *dssdev, + const struct omap_dsi_pin_config *pin_cfg); + + void (*enable_hs)(struct omap_dss_device *dssdev, int channel, + bool enable); + int (*enable_te)(struct omap_dss_device *dssdev, bool enable); + + int (*update)(struct omap_dss_device *dssdev, int channel, + void (*callback)(int, void *), void *data); + + void (*bus_lock)(struct omap_dss_device *dssdev); + void (*bus_unlock)(struct omap_dss_device *dssdev); + + int (*enable_video_output)(struct omap_dss_device *dssdev, int channel); + void (*disable_video_output)(struct omap_dss_device *dssdev, + int channel); + + int (*request_vc)(struct omap_dss_device *dssdev, int *channel); + int (*set_vc_id)(struct omap_dss_device *dssdev, int channel, + int vc_id); + void (*release_vc)(struct omap_dss_device *dssdev, int channel); + + /* data transfer */ + int (*dcs_write)(struct omap_dss_device *dssdev, int channel, + u8 *data, int len); + int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel, + u8 *data, int len); + int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, + u8 *data, int len); + + int (*gen_write)(struct omap_dss_device *dssdev, int channel, + u8 *data, int len); + int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel, + u8 *data, int len); + int (*gen_read)(struct omap_dss_device *dssdev, int channel, + u8 *reqdata, int reqlen, + u8 *data, int len); + + int (*bta_sync)(struct omap_dss_device *dssdev, int channel); + + int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev, + int channel, u16 plen); }; struct omap_dss_device { - struct device dev; + struct device *dev; - enum omap_display_type type; + struct module *owner; + + struct list_head panel_list; - enum omap_channel channel; + /* alias in the form of "display%d" */ + char alias[16]; + + enum omap_display_type type; + enum omap_display_type output_type; union { struct { @@ -564,9 +731,6 @@ struct omap_dss_device { struct { int module; - - bool ext_te; - u8 ext_te_gpio; } dsi; struct { @@ -576,44 +740,10 @@ struct omap_dss_device { } phy; struct { - struct { - struct { - u16 lck_div; - u16 pck_div; - enum omap_dss_clk_source lcd_clk_src; - } channel; - - enum omap_dss_clk_source dispc_fclk_src; - } dispc; - - struct { - /* regn is one greater than TRM's REGN value */ - u16 regn; - u16 regm; - u16 regm_dispc; - u16 regm_dsi; - - u16 lp_clk_div; - enum omap_dss_clk_source dsi_fclk_src; - } dsi; - - struct { - /* regn is one greater than TRM's REGN value */ - u16 regn; - u16 regm2; - } hdmi; - } clocks; - - struct { struct omap_video_timings timings; - int acbi; /* ac-bias pin transitions per interrupt */ - /* Unit: line clocks */ - int acb; /* ac-bias pin frequency */ - enum omap_dss_dsi_pixel_format dsi_pix_fmt; enum omap_dss_dsi_mode dsi_mode; - struct omap_dss_dsi_videomode_timings dsi_vm_timings; } panel; struct { @@ -621,10 +751,6 @@ struct omap_dss_device { struct rfbi_timings rfbi_timings; } ctrl; - int reset_gpio; - - int max_backlight_level; - const char *name; /* used to match device to driver */ @@ -634,22 +760,40 @@ struct omap_dss_device { struct omap_dss_driver *driver; + union { + const struct omapdss_dpi_ops *dpi; + const struct omapdss_sdi_ops *sdi; + const struct omapdss_dvi_ops *dvi; + const struct omapdss_hdmi_ops *hdmi; + const struct omapdss_atv_ops *atv; + const struct omapdss_dsi_ops *dsi; + } ops; + /* helper variable for driver suspend/resume */ bool activate_after_resume; enum omap_display_caps caps; - struct omap_dss_output *output; + struct omap_dss_device *src; enum omap_dss_display_state state; enum omap_dss_audio_state audio_state; - /* platform specific */ - int (*platform_enable)(struct omap_dss_device *dssdev); - void (*platform_disable)(struct omap_dss_device *dssdev); - int (*set_backlight)(struct omap_dss_device *dssdev, int level); - int (*get_backlight)(struct omap_dss_device *dssdev); + /* OMAP DSS output specific fields */ + + struct list_head list; + + /* DISPC channel for this output */ + enum omap_channel dispc_channel; + + /* output instance */ + enum omap_dss_output_id id; + + /* dynamic fields */ + struct omap_overlay_manager *manager; + + struct omap_dss_device *dst; }; struct omap_dss_hdmi_data @@ -659,21 +803,15 @@ struct omap_dss_hdmi_data int hpd_gpio; }; -struct omap_dss_audio { - struct snd_aes_iec958 *iec; - struct snd_cea_861_aud_if *cea; -}; - struct omap_dss_driver { - struct device_driver driver; - int (*probe)(struct omap_dss_device *); void (*remove)(struct omap_dss_device *); + int (*connect)(struct omap_dss_device *dssdev); + void (*disconnect)(struct omap_dss_device *dssdev); + int (*enable)(struct omap_dss_device *display); void (*disable)(struct omap_dss_device *display); - int (*suspend)(struct omap_dss_device *display); - int (*resume)(struct omap_dss_device *display); int (*run_test)(struct omap_dss_device *display, int test); int (*update)(struct omap_dss_device *dssdev, @@ -731,18 +869,35 @@ struct omap_dss_driver { }; +enum omapdss_version omapdss_get_version(void); +bool omapdss_is_initialized(void); + int omap_dss_register_driver(struct omap_dss_driver *); void omap_dss_unregister_driver(struct omap_dss_driver *); -void omap_dss_get_device(struct omap_dss_device *dssdev); +int omapdss_register_display(struct omap_dss_device *dssdev); +void omapdss_unregister_display(struct omap_dss_device *dssdev); + +struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev); void omap_dss_put_device(struct omap_dss_device *dssdev); #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); struct omap_dss_device *omap_dss_find_device(void *data, int (*match)(struct omap_dss_device *dssdev, void *data)); +const char *omapdss_get_default_display_name(void); + +void videomode_to_omap_video_timings(const struct videomode *vm, + struct omap_video_timings *ovt); +void omap_video_timings_to_videomode(const struct omap_video_timings *ovt, + struct videomode *vm); + +int dss_feat_get_num_mgrs(void); +int dss_feat_get_num_ovls(void); +enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); +enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); +enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); + -int omap_dss_start_device(struct omap_dss_device *dssdev); -void omap_dss_stop_device(struct omap_dss_device *dssdev); int omap_dss_get_num_overlay_managers(void); struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); @@ -750,10 +905,17 @@ struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); int omap_dss_get_num_overlays(void); struct omap_overlay *omap_dss_get_overlay(int num); -struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id); -int omapdss_output_set_device(struct omap_dss_output *out, +int omapdss_register_output(struct omap_dss_device *output); +void omapdss_unregister_output(struct omap_dss_device *output); +struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id); +struct omap_dss_device *omap_dss_find_output(const char *name); +struct omap_dss_device *omap_dss_find_output_by_node(struct device_node *node); +int omapdss_output_set_device(struct omap_dss_device *out, struct omap_dss_device *dssdev); -int omapdss_output_unset_device(struct omap_dss_output *out); +int omapdss_output_unset_device(struct omap_dss_device *out); + +struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev); +struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev); void omapdss_default_get_resolution(struct omap_dss_device *dssdev, u16 *xres, u16 *yres); @@ -765,65 +927,107 @@ typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); -int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout); -int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, - unsigned long timeout); +u32 dispc_read_irqstatus(void); +void dispc_clear_irqstatus(u32 mask); +u32 dispc_read_irqenable(void); +void dispc_write_irqenable(u32 mask); + +int dispc_request_irq(irq_handler_t handler, void *dev_id); +void dispc_free_irq(void *dev_id); + +int dispc_runtime_get(void); +void dispc_runtime_put(void); + +void dispc_mgr_enable(enum omap_channel channel, bool enable); +bool dispc_mgr_is_enabled(enum omap_channel channel); +u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); +u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); +u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel); +bool dispc_mgr_go_busy(enum omap_channel channel); +void dispc_mgr_go(enum omap_channel channel); +void dispc_mgr_set_lcd_config(enum omap_channel channel, + const struct dss_lcd_mgr_config *config); +void dispc_mgr_set_timings(enum omap_channel channel, + const struct omap_video_timings *timings); +void dispc_mgr_setup(enum omap_channel channel, + const struct omap_overlay_manager_info *info); + +int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, + const struct omap_overlay_info *oi, + const struct omap_video_timings *timings, + int *x_predecim, int *y_predecim); + +int dispc_ovl_enable(enum omap_plane plane, bool enable); +bool dispc_ovl_enabled(enum omap_plane plane); +void dispc_ovl_set_channel_out(enum omap_plane plane, + enum omap_channel channel); +int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, + bool replication, const struct omap_video_timings *mgr_timings, + bool mem_to_mem); + +int omapdss_compat_init(void); +void omapdss_compat_uninit(void); + +struct dss_mgr_ops { + int (*connect)(struct omap_overlay_manager *mgr, + struct omap_dss_device *dst); + void (*disconnect)(struct omap_overlay_manager *mgr, + struct omap_dss_device *dst); + + void (*start_update)(struct omap_overlay_manager *mgr); + int (*enable)(struct omap_overlay_manager *mgr); + void (*disable)(struct omap_overlay_manager *mgr); + void (*set_timings)(struct omap_overlay_manager *mgr, + const struct omap_video_timings *timings); + void (*set_lcd_config)(struct omap_overlay_manager *mgr, + const struct dss_lcd_mgr_config *config); + int (*register_framedone_handler)(struct omap_overlay_manager *mgr, + void (*handler)(void *), void *data); + void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr, + void (*handler)(void *), void *data); +}; + +int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops); +void dss_uninstall_mgr_ops(void); + +int dss_mgr_connect(struct omap_overlay_manager *mgr, + struct omap_dss_device *dst); +void dss_mgr_disconnect(struct omap_overlay_manager *mgr, + struct omap_dss_device *dst); +void dss_mgr_set_timings(struct omap_overlay_manager *mgr, + const struct omap_video_timings *timings); +void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr, + const struct dss_lcd_mgr_config *config); +int dss_mgr_enable(struct omap_overlay_manager *mgr); +void dss_mgr_disable(struct omap_overlay_manager *mgr); +void dss_mgr_start_update(struct omap_overlay_manager *mgr); +int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr, + void (*handler)(void *), void *data); +void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr, + void (*handler)(void *), void *data); + +static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev) +{ + return dssdev->src; +} -#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) -#define to_dss_device(x) container_of((x), struct omap_dss_device, dev) +static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev) +{ + return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; +} -void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, - bool enable); -int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); -void omapdss_dsi_set_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); -void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h); -void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev, - enum omap_dss_dsi_pixel_format fmt); -void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev, - enum omap_dss_dsi_mode mode); -void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev, - struct omap_dss_dsi_videomode_timings *timings); - -int omap_dsi_update(struct omap_dss_device *dssdev, int channel, - void (*callback)(int, void *), void *data); -int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); -int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); -void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); -int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev, - const struct omap_dsi_pin_config *pin_cfg); -int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev, - unsigned long ddr_clk, unsigned long lp_clk); - -int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); -void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, - bool disconnect_lanes, bool enter_ulps); - -int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); -void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); -void omapdss_dpi_set_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); -int dpi_check_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); -void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines); +struct device_node * +omapdss_of_get_next_port(const struct device_node *parent, + struct device_node *prev); -int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); -void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); -void omapdss_sdi_set_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); -void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs); - -int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); -void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); -int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *), - void *data); -int omap_rfbi_configure(struct omap_dss_device *dssdev); -void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h); -void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev, - int pixel_size); -void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev, - int data_lines); -void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev, - struct rfbi_timings *timings); +struct device_node * +omapdss_of_get_next_endpoint(const struct device_node *parent, + struct device_node *prev); + +struct device_node * +omapdss_of_get_first_endpoint(const struct device_node *parent); + +struct omap_dss_device * +omapdss_of_find_source_for_first_ep(struct device_node *node); #endif diff --git a/include/video/omapvrfb.h b/include/video/omapvrfb.h new file mode 100644 index 00000000000..bb0bd89f8bc --- /dev/null +++ b/include/video/omapvrfb.h @@ -0,0 +1,68 @@ +/* + * VRFB Rotation Engine + * + * Copyright (C) 2009 Nokia Corporation + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __OMAP_VRFB_H__ +#define __OMAP_VRFB_H__ + +#define OMAP_VRFB_LINE_LEN 2048 + +struct vrfb { + u8 context; + void __iomem *vaddr[4]; + unsigned long paddr[4]; + u16 xres; + u16 yres; + u16 xoffset; + u16 yoffset; + u8 bytespp; + bool yuv_mode; +}; + +#ifdef CONFIG_OMAP2_VRFB +extern bool omap_vrfb_supported(void); +extern int omap_vrfb_request_ctx(struct vrfb *vrfb); +extern void omap_vrfb_release_ctx(struct vrfb *vrfb); +extern void omap_vrfb_adjust_size(u16 *width, u16 *height, + u8 bytespp); +extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp); +extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp); +extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, + u16 width, u16 height, + unsigned bytespp, bool yuv_mode); +extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot); +extern void omap_vrfb_restore_context(void); + +#else +static inline bool omap_vrfb_supported(void) { return false; } +static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; } +static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {} +static inline void omap_vrfb_adjust_size(u16 *width, u16 *height, + u8 bytespp) {} +static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp) + { return 0; } +static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp) + { return 0; } +static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, + u16 width, u16 height, unsigned bytespp, bool yuv_mode) {} +static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot) + { return 0; } +static inline void omap_vrfb_restore_context(void) {} +#endif +#endif /* __VRFB_H */ diff --git a/include/video/platform_lcd.h b/include/video/platform_lcd.h index ad3bdfe743b..23864b28414 100644 --- a/include/video/platform_lcd.h +++ b/include/video/platform_lcd.h @@ -15,6 +15,7 @@ struct plat_lcd_data; struct fb_info; struct plat_lcd_data { + int (*probe)(struct plat_lcd_data *); void (*set_power)(struct plat_lcd_data *, unsigned int power); int (*match_fb)(struct plat_lcd_data *, struct fb_info *); }; diff --git a/include/video/pxa168fb.h b/include/video/pxa168fb.h index 8c2f385a90e..84cbb1f69ea 100644 --- a/include/video/pxa168fb.h +++ b/include/video/pxa168fb.h @@ -1,6 +1,4 @@ /* - * linux/arch/arm/mach-mmp/include/mach/pxa168fb.h - * * Copyright (C) 2009 Marvell International Ltd. * * This program is free software; you can redistribute it and/or modify diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index 7ae6c07f2ef..b0393209679 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -8,12 +8,8 @@ * S3C Platform - new-style fimd and framebuffer register definitions * * This is the register set for the fimd and new style framebuffer interface - * found from the S3C2443 onwards into the S3C2416, S3C2450 and the - * S3C64XX series such as the S3C6400 and S3C6410. - * - * The file does not contain the cpu specific items which are based on - * whichever architecture is selected, it only contains the core of the - * register set. See <mach/regs-fb.h> to get the specifics. + * found from the S3C2443 onwards into the S3C2416, S3C2450, the + * S3C64XX series such as the S3C6400 and S3C6410, and EXYNOS series. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -22,17 +18,20 @@ /* VIDCON0 */ -#define VIDCON0 (0x00) +#define VIDCON0 0x00 #define VIDCON0_INTERLACE (1 << 29) -#define VIDCON0_VIDOUT_MASK (0x3 << 26) -#define VIDCON0_VIDOUT_SHIFT (26) +#define VIDCON0_VIDOUT_MASK (0x7 << 26) +#define VIDCON0_VIDOUT_SHIFT 26 #define VIDCON0_VIDOUT_RGB (0x0 << 26) #define VIDCON0_VIDOUT_TV (0x1 << 26) #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) +#define VIDCON0_VIDOUT_WB_RGB (0x4 << 26) +#define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26) +#define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26) #define VIDCON0_L1_DATA_MASK (0x7 << 23) -#define VIDCON0_L1_DATA_SHIFT (23) +#define VIDCON0_L1_DATA_SHIFT 23 #define VIDCON0_L1_DATA_16BPP (0x0 << 23) #define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) @@ -41,7 +40,7 @@ #define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) #define VIDCON0_L0_DATA_MASK (0x7 << 20) -#define VIDCON0_L0_DATA_SHIFT (20) +#define VIDCON0_L0_DATA_SHIFT 20 #define VIDCON0_L0_DATA_16BPP (0x0 << 20) #define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) @@ -50,7 +49,7 @@ #define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) #define VIDCON0_PNRMODE_MASK (0x3 << 17) -#define VIDCON0_PNRMODE_SHIFT (17) +#define VIDCON0_PNRMODE_SHIFT 17 #define VIDCON0_PNRMODE_RGB (0x0 << 17) #define VIDCON0_PNRMODE_BGR (0x1 << 17) #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) @@ -58,14 +57,14 @@ #define VIDCON0_CLKVALUP (1 << 16) #define VIDCON0_CLKVAL_F_MASK (0xff << 6) -#define VIDCON0_CLKVAL_F_SHIFT (6) -#define VIDCON0_CLKVAL_F_LIMIT (0xff) +#define VIDCON0_CLKVAL_F_SHIFT 6 +#define VIDCON0_CLKVAL_F_LIMIT 0xff #define VIDCON0_CLKVAL_F(_x) ((_x) << 6) #define VIDCON0_VLCKFREE (1 << 5) #define VIDCON0_CLKDIR (1 << 4) #define VIDCON0_CLKSEL_MASK (0x3 << 2) -#define VIDCON0_CLKSEL_SHIFT (2) +#define VIDCON0_CLKSEL_SHIFT 2 #define VIDCON0_CLKSEL_HCLK (0x0 << 2) #define VIDCON0_CLKSEL_LCD (0x1 << 2) #define VIDCON0_CLKSEL_27M (0x3 << 2) @@ -73,16 +72,17 @@ #define VIDCON0_ENVID (1 << 1) #define VIDCON0_ENVID_F (1 << 0) -#define VIDCON1 (0x04) +#define VIDCON1 0x04 #define VIDCON1_LINECNT_MASK (0x7ff << 16) -#define VIDCON1_LINECNT_SHIFT (16) +#define VIDCON1_LINECNT_SHIFT 16 #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) +#define VIDCON1_FSTATUS_EVEN (1 << 15) #define VIDCON1_VSTATUS_MASK (0x3 << 13) -#define VIDCON1_VSTATUS_SHIFT (13) +#define VIDCON1_VSTATUS_SHIFT 13 #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) -#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) +#define VIDCON1_VSTATUS_FRONTPORCH (0x3 << 13) #define VIDCON1_VCLK_MASK (0x3 << 9) #define VIDCON1_VCLK_HOLD (0x0 << 9) #define VIDCON1_VCLK_RUN (0x1 << 9) @@ -94,12 +94,12 @@ /* VIDCON2 */ -#define VIDCON2 (0x08) +#define VIDCON2 0x08 #define VIDCON2_EN601 (1 << 23) #define VIDCON2_TVFMTSEL_SW (1 << 14) #define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) -#define VIDCON2_TVFMTSEL1_SHIFT (12) +#define VIDCON2_TVFMTSEL1_SHIFT 12 #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) @@ -111,82 +111,95 @@ * Might not be present in the S3C6410 documentation, * but tests prove it's there almost for sure; shouldn't hurt in any case. */ -#define PRTCON (0x0c) +#define PRTCON 0x0c #define PRTCON_PROTECT (1 << 11) /* VIDTCON0 */ +#define VIDTCON0 0x10 #define VIDTCON0_VBPDE_MASK (0xff << 24) -#define VIDTCON0_VBPDE_SHIFT (24) -#define VIDTCON0_VBPDE_LIMIT (0xff) +#define VIDTCON0_VBPDE_SHIFT 24 +#define VIDTCON0_VBPDE_LIMIT 0xff #define VIDTCON0_VBPDE(_x) ((_x) << 24) #define VIDTCON0_VBPD_MASK (0xff << 16) -#define VIDTCON0_VBPD_SHIFT (16) -#define VIDTCON0_VBPD_LIMIT (0xff) +#define VIDTCON0_VBPD_SHIFT 16 +#define VIDTCON0_VBPD_LIMIT 0xff #define VIDTCON0_VBPD(_x) ((_x) << 16) #define VIDTCON0_VFPD_MASK (0xff << 8) -#define VIDTCON0_VFPD_SHIFT (8) -#define VIDTCON0_VFPD_LIMIT (0xff) +#define VIDTCON0_VFPD_SHIFT 8 +#define VIDTCON0_VFPD_LIMIT 0xff #define VIDTCON0_VFPD(_x) ((_x) << 8) #define VIDTCON0_VSPW_MASK (0xff << 0) -#define VIDTCON0_VSPW_SHIFT (0) -#define VIDTCON0_VSPW_LIMIT (0xff) +#define VIDTCON0_VSPW_SHIFT 0 +#define VIDTCON0_VSPW_LIMIT 0xff #define VIDTCON0_VSPW(_x) ((_x) << 0) /* VIDTCON1 */ +#define VIDTCON1 0x14 #define VIDTCON1_VFPDE_MASK (0xff << 24) -#define VIDTCON1_VFPDE_SHIFT (24) -#define VIDTCON1_VFPDE_LIMIT (0xff) +#define VIDTCON1_VFPDE_SHIFT 24 +#define VIDTCON1_VFPDE_LIMIT 0xff #define VIDTCON1_VFPDE(_x) ((_x) << 24) #define VIDTCON1_HBPD_MASK (0xff << 16) -#define VIDTCON1_HBPD_SHIFT (16) -#define VIDTCON1_HBPD_LIMIT (0xff) +#define VIDTCON1_HBPD_SHIFT 16 +#define VIDTCON1_HBPD_LIMIT 0xff #define VIDTCON1_HBPD(_x) ((_x) << 16) #define VIDTCON1_HFPD_MASK (0xff << 8) -#define VIDTCON1_HFPD_SHIFT (8) -#define VIDTCON1_HFPD_LIMIT (0xff) +#define VIDTCON1_HFPD_SHIFT 8 +#define VIDTCON1_HFPD_LIMIT 0xff #define VIDTCON1_HFPD(_x) ((_x) << 8) #define VIDTCON1_HSPW_MASK (0xff << 0) -#define VIDTCON1_HSPW_SHIFT (0) -#define VIDTCON1_HSPW_LIMIT (0xff) +#define VIDTCON1_HSPW_SHIFT 0 +#define VIDTCON1_HSPW_LIMIT 0xff #define VIDTCON1_HSPW(_x) ((_x) << 0) -#define VIDTCON2 (0x18) +#define VIDTCON2 0x18 #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) -#define VIDTCON2_LINEVAL_SHIFT (11) -#define VIDTCON2_LINEVAL_LIMIT (0x7ff) +#define VIDTCON2_LINEVAL_SHIFT 11 +#define VIDTCON2_LINEVAL_LIMIT 0x7ff #define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11) #define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22) #define VIDTCON2_HOZVAL_MASK (0x7ff << 0) -#define VIDTCON2_HOZVAL_SHIFT (0) -#define VIDTCON2_HOZVAL_LIMIT (0x7ff) +#define VIDTCON2_HOZVAL_SHIFT 0 +#define VIDTCON2_HOZVAL_LIMIT 0x7ff #define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0) /* WINCONx */ - +#define WINCON(_win) (0x20 + ((_win) * 4)) +#define WINCONx_CSCCON_EQ601 (0x0 << 28) +#define WINCONx_CSCCON_EQ709 (0x1 << 28) +#define WINCONx_CSCWIDTH_MASK (0x3 << 26) +#define WINCONx_CSCWIDTH_SHIFT 26 +#define WINCONx_CSCWIDTH_WIDE (0x0 << 26) +#define WINCONx_CSCWIDTH_NARROW (0x3 << 26) +#define WINCONx_ENLOCAL (1 << 22) +#define WINCONx_BUFSTATUS (1 << 21) +#define WINCONx_BUFSEL (1 << 20) +#define WINCONx_BUFAUTOEN (1 << 19) #define WINCONx_BITSWP (1 << 18) #define WINCONx_BYTSWP (1 << 17) #define WINCONx_HAWSWP (1 << 16) #define WINCONx_WSWP (1 << 15) +#define WINCONx_YCbCr (1 << 13) #define WINCONx_BURSTLEN_MASK (0x3 << 9) -#define WINCONx_BURSTLEN_SHIFT (9) +#define WINCONx_BURSTLEN_SHIFT 9 #define WINCONx_BURSTLEN_16WORD (0x0 << 9) #define WINCONx_BURSTLEN_8WORD (0x1 << 9) #define WINCONx_BURSTLEN_4WORD (0x2 << 9) - #define WINCONx_ENWIN (1 << 0) + #define WINCON0_BPPMODE_MASK (0xf << 2) -#define WINCON0_BPPMODE_SHIFT (2) +#define WINCON0_BPPMODE_SHIFT 2 #define WINCON0_BPPMODE_1BPP (0x0 << 2) #define WINCON0_BPPMODE_2BPP (0x1 << 2) #define WINCON0_BPPMODE_4BPP (0x2 << 2) @@ -196,11 +209,10 @@ #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) +#define WINCON1_LOCALSEL_CAMIF (1 << 23) #define WINCON1_BLD_PIX (1 << 6) - -#define WINCON1_ALPHA_SEL (1 << 1) #define WINCON1_BPPMODE_MASK (0xf << 2) -#define WINCON1_BPPMODE_SHIFT (2) +#define WINCON1_BPPMODE_SHIFT 2 #define WINCON1_BPPMODE_1BPP (0x0 << 2) #define WINCON1_BPPMODE_2BPP (0x1 << 2) #define WINCON1_BPPMODE_4BPP (0x2 << 2) @@ -216,60 +228,64 @@ #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) +#define WINCON1_ALPHA_SEL (1 << 1) /* S5PV210 */ -#define SHADOWCON (0x34) +#define SHADOWCON 0x34 #define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win))) /* DMA channels (all windows) */ #define SHADOWCON_CHx_ENABLE(_win) (1 << (_win)) /* Local input channels (windows 0-2) */ #define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) +/* VIDOSDx */ + +#define VIDOSD_BASE 0x40 #define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) -#define VIDOSDxA_TOPLEFT_X_SHIFT (11) -#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) +#define VIDOSDxA_TOPLEFT_X_SHIFT 11 +#define VIDOSDxA_TOPLEFT_X_LIMIT 0x7ff #define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11) #define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) #define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) -#define VIDOSDxA_TOPLEFT_Y_SHIFT (0) -#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) +#define VIDOSDxA_TOPLEFT_Y_SHIFT 0 +#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x7ff #define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0) #define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) -#define VIDOSDxB_BOTRIGHT_X_SHIFT (11) -#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) +#define VIDOSDxB_BOTRIGHT_X_SHIFT 11 +#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x7ff #define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11) #define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) #define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) -#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) -#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) +#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0 +#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x7ff #define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0) /* For VIDOSD[1..4]C */ #define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) #define VIDISD14C_ALPHA0_G_MASK (0xf << 16) -#define VIDISD14C_ALPHA0_G_SHIFT (16) -#define VIDISD14C_ALPHA0_G_LIMIT (0xf) +#define VIDISD14C_ALPHA0_G_SHIFT 16 +#define VIDISD14C_ALPHA0_G_LIMIT 0xf #define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) #define VIDISD14C_ALPHA0_B_MASK (0xf << 12) -#define VIDISD14C_ALPHA0_B_SHIFT (12) -#define VIDISD14C_ALPHA0_B_LIMIT (0xf) +#define VIDISD14C_ALPHA0_B_SHIFT 12 +#define VIDISD14C_ALPHA0_B_LIMIT 0xf #define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) #define VIDISD14C_ALPHA1_R_MASK (0xf << 8) -#define VIDISD14C_ALPHA1_R_SHIFT (8) -#define VIDISD14C_ALPHA1_R_LIMIT (0xf) +#define VIDISD14C_ALPHA1_R_SHIFT 8 +#define VIDISD14C_ALPHA1_R_LIMIT 0xf #define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) #define VIDISD14C_ALPHA1_G_MASK (0xf << 4) -#define VIDISD14C_ALPHA1_G_SHIFT (4) -#define VIDISD14C_ALPHA1_G_LIMIT (0xf) +#define VIDISD14C_ALPHA1_G_SHIFT 4 +#define VIDISD14C_ALPHA1_G_LIMIT 0xf #define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) #define VIDISD14C_ALPHA1_B_MASK (0xf << 0) -#define VIDISD14C_ALPHA1_B_SHIFT (0) -#define VIDISD14C_ALPHA1_B_LIMIT (0xf) +#define VIDISD14C_ALPHA1_B_SHIFT 0 +#define VIDISD14C_ALPHA1_B_LIMIT 0xf #define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) /* Video buffer addresses */ @@ -281,21 +297,22 @@ #define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27) #define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) -#define VIDW_BUF_SIZE_OFFSET_SHIFT (13) -#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) +#define VIDW_BUF_SIZE_OFFSET_SHIFT 13 +#define VIDW_BUF_SIZE_OFFSET_LIMIT 0x1fff #define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13) #define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26) #define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) -#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) -#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) +#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT 0 +#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT 0x1fff #define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0) /* Interrupt controls and status */ +#define VIDINTCON0 0x130 #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) -#define VIDINTCON0_FIFOINTERVAL_SHIFT (20) -#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) +#define VIDINTCON0_FIFOINTERVAL_SHIFT 20 +#define VIDINTCON0_FIFOINTERVAL_LIMIT 0x3f #define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) #define VIDINTCON0_INT_SYSMAINCON (1 << 19) @@ -303,7 +320,7 @@ #define VIDINTCON0_INT_I80IFDONE (1 << 17) #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) -#define VIDINTCON0_FRAMESEL0_SHIFT (15) +#define VIDINTCON0_FRAMESEL0_SHIFT 15 #define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) @@ -318,12 +335,15 @@ #define VIDINTCON0_INT_FRAME (1 << 12) #define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) -#define VIDINTCON0_FIFIOSEL_SHIFT (5) +#define VIDINTCON0_FIFIOSEL_SHIFT 5 #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) -#define VIDINTCON0_FIFOLEVEL_SHIFT (2) +#define VIDINTCON0_FIFOLEVEL_SHIFT 2 #define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) #define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) #define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) @@ -331,44 +351,67 @@ #define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) #define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) -#define VIDINTCON0_INT_FIFO_SHIFT (0) +#define VIDINTCON0_INT_FIFO_SHIFT 0 #define VIDINTCON0_INT_ENABLE (1 << 0) -#define VIDINTCON1 (0x134) +#define VIDINTCON1 0x134 #define VIDINTCON1_INT_I180 (1 << 2) #define VIDINTCON1_INT_FRAME (1 << 1) #define VIDINTCON1_INT_FIFO (1 << 0) /* Window colour-key control registers */ -#define WKEYCON (0x140) /* 6410,V210 */ +#define WKEYCON 0x140 -#define WKEYCON0 (0x00) -#define WKEYCON1 (0x04) +#define WKEYCON0 0x00 +#define WKEYCON1 0x04 #define WxKEYCON0_KEYBL_EN (1 << 26) #define WxKEYCON0_KEYEN_F (1 << 25) #define WxKEYCON0_DIRCON (1 << 24) #define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) -#define WxKEYCON0_COMPKEY_SHIFT (0) -#define WxKEYCON0_COMPKEY_LIMIT (0xffffff) +#define WxKEYCON0_COMPKEY_SHIFT 0 +#define WxKEYCON0_COMPKEY_LIMIT 0xffffff #define WxKEYCON0_COMPKEY(_x) ((_x) << 0) #define WxKEYCON1_COLVAL_MASK (0xffffff << 0) -#define WxKEYCON1_COLVAL_SHIFT (0) -#define WxKEYCON1_COLVAL_LIMIT (0xffffff) +#define WxKEYCON1_COLVAL_SHIFT 0 +#define WxKEYCON1_COLVAL_LIMIT 0xffffff #define WxKEYCON1_COLVAL(_x) ((_x) << 0) +/* Dithering control */ +#define DITHMODE 0x170 +#define DITHMODE_R_POS_MASK (0x3 << 5) +#define DITHMODE_R_POS_SHIFT 5 +#define DITHMODE_R_POS_8BIT (0x0 << 5) +#define DITHMODE_R_POS_6BIT (0x1 << 5) +#define DITHMODE_R_POS_5BIT (0x2 << 5) +#define DITHMODE_G_POS_MASK (0x3 << 3) +#define DITHMODE_G_POS_SHIFT 3 +#define DITHMODE_G_POS_8BIT (0x0 << 3) +#define DITHMODE_G_POS_6BIT (0x1 << 3) +#define DITHMODE_G_POS_5BIT (0x2 << 3) +#define DITHMODE_B_POS_MASK (0x3 << 1) +#define DITHMODE_B_POS_SHIFT 1 +#define DITHMODE_B_POS_8BIT (0x0 << 1) +#define DITHMODE_B_POS_6BIT (0x1 << 1) +#define DITHMODE_B_POS_5BIT (0x2 << 1) +#define DITHMODE_DITH_EN (1 << 0) /* Window blanking (MAP) */ - +#define WINxMAP(_win) (0x180 + ((_win) * 4)) #define WINxMAP_MAP (1 << 24) #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) -#define WINxMAP_MAP_COLOUR_SHIFT (0) -#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) +#define WINxMAP_MAP_COLOUR_SHIFT 0 +#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) +/* Winodw palette control */ +#define WPALCON 0x1A0 #define WPALCON_PAL_UPDATE (1 << 9) +#define WPALCON_W4PAL_16BPP_A555 (1 << 8) +#define WPALCON_W3PAL_16BPP_A555 (1 << 7) +#define WPALCON_W2PAL_16BPP_A555 (1 << 6) #define WPALCON_W1PAL_MASK (0x7 << 3) -#define WPALCON_W1PAL_SHIFT (3) +#define WPALCON_W1PAL_SHIFT 3 #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) #define WPALCON_W1PAL_24BPP (0x1 << 3) #define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) @@ -376,9 +419,8 @@ #define WPALCON_W1PAL_18BPP (0x4 << 3) #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) - #define WPALCON_W0PAL_MASK (0x7 << 0) -#define WPALCON_W0PAL_SHIFT (0) +#define WPALCON_W0PAL_SHIFT 0 #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) #define WPALCON_W0PAL_24BPP (0x1 << 0) #define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) @@ -388,122 +430,11 @@ #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) /* Blending equation control */ -#define BLENDCON (0x260) +#define BLENDCON 0x260 #define BLENDCON_NEW_MASK (1 << 0) #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) -#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ -#define VIDCON1_FSTATUS_EVEN (1 << 15) - -/* Video timing controls */ -#define VIDTCON0 (0x10) -#define VIDTCON1 (0x14) -#define VIDTCON2 (0x18) - -/* Window position controls */ - -#define WINCON(_win) (0x20 + ((_win) * 4)) - -/* OSD1 and OSD4 do not have register D */ - -#define VIDOSD_BASE (0x40) - -#define VIDINTCON0 (0x130) - -/* WINCONx */ - -#define WINCONx_CSCWIDTH_MASK (0x3 << 26) -#define WINCONx_CSCWIDTH_SHIFT (26) -#define WINCONx_CSCWIDTH_WIDE (0x0 << 26) -#define WINCONx_CSCWIDTH_NARROW (0x3 << 26) - -#define WINCONx_ENLOCAL (1 << 22) -#define WINCONx_BUFSTATUS (1 << 21) -#define WINCONx_BUFSEL (1 << 20) -#define WINCONx_BUFAUTOEN (1 << 19) -#define WINCONx_YCbCr (1 << 13) - -#define WINCON1_LOCALSEL_CAMIF (1 << 23) - -#define WINCON2_LOCALSEL_CAMIF (1 << 23) -#define WINCON2_BLD_PIX (1 << 6) - -#define WINCON2_ALPHA_SEL (1 << 1) -#define WINCON2_BPPMODE_MASK (0xf << 2) -#define WINCON2_BPPMODE_SHIFT (2) -#define WINCON2_BPPMODE_1BPP (0x0 << 2) -#define WINCON2_BPPMODE_2BPP (0x1 << 2) -#define WINCON2_BPPMODE_4BPP (0x2 << 2) -#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) -#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON2_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) - -#define WINCON3_BLD_PIX (1 << 6) - -#define WINCON3_ALPHA_SEL (1 << 1) -#define WINCON3_BPPMODE_MASK (0xf << 2) -#define WINCON3_BPPMODE_SHIFT (2) -#define WINCON3_BPPMODE_1BPP (0x0 << 2) -#define WINCON3_BPPMODE_2BPP (0x1 << 2) -#define WINCON3_BPPMODE_4BPP (0x2 << 2) -#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON3_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) - -#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) - -#define DITHMODE (0x170) -#define WINxMAP(_win) (0x180 + ((_win) * 4)) - - -#define DITHMODE_R_POS_MASK (0x3 << 5) -#define DITHMODE_R_POS_SHIFT (5) -#define DITHMODE_R_POS_8BIT (0x0 << 5) -#define DITHMODE_R_POS_6BIT (0x1 << 5) -#define DITHMODE_R_POS_5BIT (0x2 << 5) - -#define DITHMODE_G_POS_MASK (0x3 << 3) -#define DITHMODE_G_POS_SHIFT (3) -#define DITHMODE_G_POS_8BIT (0x0 << 3) -#define DITHMODE_G_POS_6BIT (0x1 << 3) -#define DITHMODE_G_POS_5BIT (0x2 << 3) - -#define DITHMODE_B_POS_MASK (0x3 << 1) -#define DITHMODE_B_POS_SHIFT (1) -#define DITHMODE_B_POS_8BIT (0x0 << 1) -#define DITHMODE_B_POS_6BIT (0x1 << 1) -#define DITHMODE_B_POS_5BIT (0x2 << 1) - -#define DITHMODE_DITH_EN (1 << 0) - -#define WPALCON (0x1A0) - -/* Palette control */ -/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L), - * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */ -#define WPALCON_W4PAL_16BPP_A555 (1 << 8) -#define WPALCON_W3PAL_16BPP_A555 (1 << 7) -#define WPALCON_W2PAL_16BPP_A555 (1 << 6) - - /* Notes on per-window bpp settings * * Value Win0 Win1 Win2 Win3 Win 4 @@ -526,8 +457,8 @@ */ /* FIMD Version 8 register offset definitions */ -#define FIMD_V8_VIDTCON0 (0x20010) -#define FIMD_V8_VIDTCON1 (0x20014) -#define FIMD_V8_VIDTCON2 (0x20018) -#define FIMD_V8_VIDTCON3 (0x2001C) -#define FIMD_V8_VIDCON1 (0x20004) +#define FIMD_V8_VIDTCON0 0x20010 +#define FIMD_V8_VIDTCON1 0x20014 +#define FIMD_V8_VIDTCON2 0x20018 +#define FIMD_V8_VIDTCON3 0x2001C +#define FIMD_V8_VIDCON1 0x20004 diff --git a/include/video/sgivw.h b/include/video/sgivw.h deleted file mode 100644 index f6aa5692e74..00000000000 --- a/include/video/sgivw.h +++ /dev/null @@ -1,681 +0,0 @@ -/* - * linux/drivers/video/sgivw.h -- SGI DBE frame buffer device header - * - * Copyright (C) 1999 Silicon Graphics, Inc. - * Jeffrey Newquist, newquist@engr.sgi.som - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef __SGIVWFB_H__ -#define __SGIVWFB_H__ - -#define DBE_GETREG(reg, dest) ((dest) = DBE_REG_BASE->reg) -#define DBE_SETREG(reg, src) DBE_REG_BASE->reg = (src) -#define DBE_IGETREG(reg, idx, dest) ((dest) = DBE_REG_BASE->reg[idx]) -#define DBE_ISETREG(reg, idx, src) (DBE_REG_BASE->reg[idx] = (src)) - -#define MASK(msb, lsb) ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) ) -#define GET(v, msb, lsb) ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) ) -#define SET(v, f, msb, lsb) ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) ) - -#define GET_DBE_FIELD(reg, field, v) GET((v), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB) -#define SET_DBE_FIELD(reg, field, v, f) SET((v), (f), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB) - -/* NOTE: All loads/stores must be 32 bits and uncached */ - -#define DBE_REG_PHYS 0xd0000000 -#define DBE_REG_SIZE 0x01000000 - -struct asregs { - volatile u32 ctrlstat; /* 0x000000 general control */ - volatile u32 dotclock; /* 0x000004 dot clock PLL control */ - volatile u32 i2c; /* 0x000008 crt I2C control */ - volatile u32 sysclk; /* 0x00000c system clock PLL control */ - volatile u32 i2cfp; /* 0x000010 flat panel I2C control */ - volatile u32 id; /* 0x000014 device id/chip revision */ - volatile u32 config; /* 0x000018 power on configuration */ - volatile u32 bist; /* 0x00001c internal bist status */ - - char _pad0[ 0x010000 - 0x000020 ]; - - volatile u32 vt_xy; /* 0x010000 current dot coords */ - volatile u32 vt_xymax; /* 0x010004 maximum dot coords */ - volatile u32 vt_vsync; /* 0x010008 vsync on/off */ - volatile u32 vt_hsync; /* 0x01000c hsync on/off */ - volatile u32 vt_vblank; /* 0x010010 vblank on/off */ - volatile u32 vt_hblank; /* 0x010014 hblank on/off */ - volatile u32 vt_flags; /* 0x010018 polarity of vt signals */ - volatile u32 vt_f2rf_lock; /* 0x01001c f2rf & framelck y coord */ - volatile u32 vt_intr01; /* 0x010020 intr 0,1 y coords */ - volatile u32 vt_intr23; /* 0x010024 intr 2,3 y coords */ - volatile u32 fp_hdrv; /* 0x010028 flat panel hdrv on/off */ - volatile u32 fp_vdrv; /* 0x01002c flat panel vdrv on/off */ - volatile u32 fp_de; /* 0x010030 flat panel de on/off */ - volatile u32 vt_hpixen; /* 0x010034 intrnl horiz pixel on/off*/ - volatile u32 vt_vpixen; /* 0x010038 intrnl vert pixel on/off */ - volatile u32 vt_hcmap; /* 0x01003c cmap write (horiz) */ - volatile u32 vt_vcmap; /* 0x010040 cmap write (vert) */ - volatile u32 did_start_xy; /* 0x010044 eol/f did/xy reset val */ - volatile u32 crs_start_xy; /* 0x010048 eol/f crs/xy reset val */ - volatile u32 vc_start_xy; /* 0x01004c eol/f vc/xy reset val */ - - char _pad1[ 0x020000 - 0x010050 ]; - - volatile u32 ovr_width_tile; /* 0x020000 overlay plane ctrl 0 */ - volatile u32 ovr_inhwctrl; /* 0x020004 overlay plane ctrl 1 */ - volatile u32 ovr_control; /* 0x020008 overlay plane ctrl 1 */ - - char _pad2[ 0x030000 - 0x02000C ]; - - volatile u32 frm_size_tile; /* 0x030000 normal plane ctrl 0 */ - volatile u32 frm_size_pixel; /* 0x030004 normal plane ctrl 1 */ - volatile u32 frm_inhwctrl; /* 0x030008 normal plane ctrl 2 */ - volatile u32 frm_control; /* 0x03000C normal plane ctrl 3 */ - - char _pad3[ 0x040000 - 0x030010 ]; - - volatile u32 did_inhwctrl; /* 0x040000 DID control */ - volatile u32 did_control; /* 0x040004 DID shadow */ - - char _pad4[ 0x048000 - 0x040008 ]; - - volatile u32 mode_regs[32]; /* 0x048000 - 0x04807c WID table */ - - char _pad5[ 0x050000 - 0x048080 ]; - - volatile u32 cmap[6144]; /* 0x050000 - 0x055ffc color map */ - - char _pad6[ 0x058000 - 0x056000 ]; - - volatile u32 cm_fifo; /* 0x058000 color map fifo status */ - - char _pad7[ 0x060000 - 0x058004 ]; - - volatile u32 gmap[256]; /* 0x060000 - 0x0603fc gamma map */ - - char _pad8[ 0x068000 - 0x060400 ]; - - volatile u32 gmap10[1024]; /* 0x068000 - 0x068ffc gamma map */ - - char _pad9[ 0x070000 - 0x069000 ]; - - volatile u32 crs_pos; /* 0x070000 cusror control 0 */ - volatile u32 crs_ctl; /* 0x070004 cusror control 1 */ - volatile u32 crs_cmap[3]; /* 0x070008 - 0x070010 crs cmap */ - - char _pad10[ 0x078000 - 0x070014 ]; - - volatile u32 crs_glyph[64]; /* 0x078000 - 0x0780fc crs glyph */ - - char _pad11[ 0x080000 - 0x078100 ]; - - volatile u32 vc_0; /* 0x080000 video capture crtl 0 */ - volatile u32 vc_1; /* 0x080004 video capture crtl 1 */ - volatile u32 vc_2; /* 0x080008 video capture crtl 2 */ - volatile u32 vc_3; /* 0x08000c video capture crtl 3 */ - volatile u32 vc_4; /* 0x080010 video capture crtl 3 */ - volatile u32 vc_5; /* 0x080014 video capture crtl 3 */ - volatile u32 vc_6; /* 0x080018 video capture crtl 3 */ - volatile u32 vc_7; /* 0x08001c video capture crtl 3 */ - volatile u32 vc_8; /* 0x08000c video capture crtl 3 */ -}; - -/* Bit mask information */ - -#define DBE_CTRLSTAT_CHIPID_MSB 3 -#define DBE_CTRLSTAT_CHIPID_LSB 0 -#define DBE_CTRLSTAT_SENSE_N_MSB 4 -#define DBE_CTRLSTAT_SENSE_N_LSB 4 -#define DBE_CTRLSTAT_PCLKSEL_MSB 29 -#define DBE_CTRLSTAT_PCLKSEL_LSB 28 - -#define DBE_DOTCLK_M_MSB 7 -#define DBE_DOTCLK_M_LSB 0 -#define DBE_DOTCLK_N_MSB 13 -#define DBE_DOTCLK_N_LSB 8 -#define DBE_DOTCLK_P_MSB 15 -#define DBE_DOTCLK_P_LSB 14 -#define DBE_DOTCLK_RUN_MSB 20 -#define DBE_DOTCLK_RUN_LSB 20 - -#define DBE_VT_XY_VT_FREEZE_MSB 31 -#define DBE_VT_XY_VT_FREEZE_LSB 31 - -#define DBE_FP_VDRV_FP_VDRV_ON_MSB 23 -#define DBE_FP_VDRV_FP_VDRV_ON_LSB 12 -#define DBE_FP_VDRV_FP_VDRV_OFF_MSB 11 -#define DBE_FP_VDRV_FP_VDRV_OFF_LSB 0 - -#define DBE_FP_HDRV_FP_HDRV_ON_MSB 23 -#define DBE_FP_HDRV_FP_HDRV_ON_LSB 12 -#define DBE_FP_HDRV_FP_HDRV_OFF_MSB 11 -#define DBE_FP_HDRV_FP_HDRV_OFF_LSB 0 - -#define DBE_FP_DE_FP_DE_ON_MSB 23 -#define DBE_FP_DE_FP_DE_ON_LSB 12 -#define DBE_FP_DE_FP_DE_OFF_MSB 11 -#define DBE_FP_DE_FP_DE_OFF_LSB 0 - -#define DBE_VT_VSYNC_VT_VSYNC_ON_MSB 23 -#define DBE_VT_VSYNC_VT_VSYNC_ON_LSB 12 -#define DBE_VT_VSYNC_VT_VSYNC_OFF_MSB 11 -#define DBE_VT_VSYNC_VT_VSYNC_OFF_LSB 0 - -#define DBE_VT_HSYNC_VT_HSYNC_ON_MSB 23 -#define DBE_VT_HSYNC_VT_HSYNC_ON_LSB 12 -#define DBE_VT_HSYNC_VT_HSYNC_OFF_MSB 11 -#define DBE_VT_HSYNC_VT_HSYNC_OFF_LSB 0 - -#define DBE_VT_VBLANK_VT_VBLANK_ON_MSB 23 -#define DBE_VT_VBLANK_VT_VBLANK_ON_LSB 12 -#define DBE_VT_VBLANK_VT_VBLANK_OFF_MSB 11 -#define DBE_VT_VBLANK_VT_VBLANK_OFF_LSB 0 - -#define DBE_VT_HBLANK_VT_HBLANK_ON_MSB 23 -#define DBE_VT_HBLANK_VT_HBLANK_ON_LSB 12 -#define DBE_VT_HBLANK_VT_HBLANK_OFF_MSB 11 -#define DBE_VT_HBLANK_VT_HBLANK_OFF_LSB 0 - -#define DBE_VT_FLAGS_VDRV_INVERT_MSB 0 -#define DBE_VT_FLAGS_VDRV_INVERT_LSB 0 -#define DBE_VT_FLAGS_HDRV_INVERT_MSB 2 -#define DBE_VT_FLAGS_HDRV_INVERT_LSB 2 - -#define DBE_VT_VCMAP_VT_VCMAP_ON_MSB 23 -#define DBE_VT_VCMAP_VT_VCMAP_ON_LSB 12 -#define DBE_VT_VCMAP_VT_VCMAP_OFF_MSB 11 -#define DBE_VT_VCMAP_VT_VCMAP_OFF_LSB 0 - -#define DBE_VT_HCMAP_VT_HCMAP_ON_MSB 23 -#define DBE_VT_HCMAP_VT_HCMAP_ON_LSB 12 -#define DBE_VT_HCMAP_VT_HCMAP_OFF_MSB 11 -#define DBE_VT_HCMAP_VT_HCMAP_OFF_LSB 0 - -#define DBE_VT_XYMAX_VT_MAXX_MSB 11 -#define DBE_VT_XYMAX_VT_MAXX_LSB 0 -#define DBE_VT_XYMAX_VT_MAXY_MSB 23 -#define DBE_VT_XYMAX_VT_MAXY_LSB 12 - -#define DBE_VT_HPIXEN_VT_HPIXEN_ON_MSB 23 -#define DBE_VT_HPIXEN_VT_HPIXEN_ON_LSB 12 -#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_MSB 11 -#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_LSB 0 - -#define DBE_VT_VPIXEN_VT_VPIXEN_ON_MSB 23 -#define DBE_VT_VPIXEN_VT_VPIXEN_ON_LSB 12 -#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_MSB 11 -#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_LSB 0 - -#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0 -#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0 - -#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0 -#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0 - -#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13 -#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13 - -#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0 -#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0 -#define DBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31 -#define DBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9 -#define DBE_FRM_CONTROL_FRM_LINEAR_MSB 1 -#define DBE_FRM_CONTROL_FRM_LINEAR_LSB 1 - -#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0 -#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0 - -#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12 -#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5 -#define DBE_FRM_SIZE_TILE_FRM_RHS_MSB 4 -#define DBE_FRM_SIZE_TILE_FRM_RHS_LSB 0 -#define DBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14 -#define DBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13 -#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15 -#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15 - -#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31 -#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16 - -#define DBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0 -#define DBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0 -#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0 -#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0 - -#define DBE_DID_START_XY_DID_STARTY_MSB 23 -#define DBE_DID_START_XY_DID_STARTY_LSB 12 -#define DBE_DID_START_XY_DID_STARTX_MSB 11 -#define DBE_DID_START_XY_DID_STARTX_LSB 0 - -#define DBE_CRS_START_XY_CRS_STARTY_MSB 23 -#define DBE_CRS_START_XY_CRS_STARTY_LSB 12 -#define DBE_CRS_START_XY_CRS_STARTX_MSB 11 -#define DBE_CRS_START_XY_CRS_STARTX_LSB 0 - -#define DBE_WID_TYP_MSB 4 -#define DBE_WID_TYP_LSB 2 -#define DBE_WID_BUF_MSB 1 -#define DBE_WID_BUF_LSB 0 - -#define DBE_VC_START_XY_VC_STARTY_MSB 23 -#define DBE_VC_START_XY_VC_STARTY_LSB 12 -#define DBE_VC_START_XY_VC_STARTX_MSB 11 -#define DBE_VC_START_XY_VC_STARTX_LSB 0 - -/* Constants */ - -#define DBE_FRM_DEPTH_8 0 -#define DBE_FRM_DEPTH_16 1 -#define DBE_FRM_DEPTH_32 2 - -#define DBE_CMODE_I8 0 -#define DBE_CMODE_I12 1 -#define DBE_CMODE_RG3B2 2 -#define DBE_CMODE_RGB4 3 -#define DBE_CMODE_ARGB5 4 -#define DBE_CMODE_RGB8 5 -#define DBE_CMODE_RGBA5 6 -#define DBE_CMODE_RGB10 7 - -#define DBE_BMODE_BOTH 3 - -#define DBE_CRS_MAGIC 54 - -#define DBE_CLOCK_REF_KHZ 27000 - -/* Config Register (DBE Only) Definitions */ - -#define DBE_CONFIG_VDAC_ENABLE 0x00000001 -#define DBE_CONFIG_VDAC_GSYNC 0x00000002 -#define DBE_CONFIG_VDAC_PBLANK 0x00000004 -#define DBE_CONFIG_FPENABLE 0x00000008 -#define DBE_CONFIG_LENDIAN 0x00000020 -#define DBE_CONFIG_TILEHIST 0x00000040 -#define DBE_CONFIG_EXT_ADDR 0x00000080 - -#define DBE_CONFIG_FBDEV ( DBE_CONFIG_VDAC_ENABLE | \ - DBE_CONFIG_VDAC_GSYNC | \ - DBE_CONFIG_VDAC_PBLANK | \ - DBE_CONFIG_LENDIAN | \ - DBE_CONFIG_EXT_ADDR ) - -/* - * Available Video Timings and Corresponding Indices - */ - -typedef enum { - DBE_VT_640_480_60, - - DBE_VT_800_600_60, - DBE_VT_800_600_75, - DBE_VT_800_600_120, - - DBE_VT_1024_768_50, - DBE_VT_1024_768_60, - DBE_VT_1024_768_75, - DBE_VT_1024_768_85, - DBE_VT_1024_768_120, - - DBE_VT_1280_1024_50, - DBE_VT_1280_1024_60, - DBE_VT_1280_1024_75, - DBE_VT_1280_1024_85, - - DBE_VT_1600_1024_53, - DBE_VT_1600_1024_60, - - DBE_VT_1600_1200_50, - DBE_VT_1600_1200_60, - DBE_VT_1600_1200_75, - - DBE_VT_1920_1080_50, - DBE_VT_1920_1080_60, - DBE_VT_1920_1080_72, - - DBE_VT_1920_1200_50, - DBE_VT_1920_1200_60, - DBE_VT_1920_1200_66, - - DBE_VT_UNKNOWN -} dbe_timing_t; - - - -/* - * Crime Video Timing Data Structure - */ - -struct dbe_timing_info -{ - dbe_timing_t type; - int flags; - short width; /* Monitor resolution */ - short height; - int fields_sec; /* fields/sec (Hz -3 dec. places */ - int cfreq; /* pixel clock frequency (MHz -3 dec. places) */ - short htotal; /* Horizontal total pixels */ - short hblank_start; /* Horizontal blank start */ - short hblank_end; /* Horizontal blank end */ - short hsync_start; /* Horizontal sync start */ - short hsync_end; /* Horizontal sync end */ - short vtotal; /* Vertical total lines */ - short vblank_start; /* Vertical blank start */ - short vblank_end; /* Vertical blank end */ - short vsync_start; /* Vertical sync start */ - short vsync_end; /* Vertical sync end */ - short pll_m; /* PLL M parameter */ - short pll_n; /* PLL P parameter */ - short pll_p; /* PLL N parameter */ -}; - -/* Defines for dbe_vof_info_t flags */ - -#define DBE_VOF_UNKNOWNMON 1 -#define DBE_VOF_STEREO 2 -#define DBE_VOF_DO_GENSYNC 4 /* enable incoming sync */ -#define DBE_VOF_SYNC_ON_GREEN 8 /* sync on green */ -#define DBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */ -#define DBE_VOF_MAGICKEY 0x2000 /* Backdoor key */ - -/* - * DBE Timing Tables - */ - -#ifdef INCLUDE_TIMING_TABLE_DATA -struct dbe_timing_info dbeVTimings[] = { - { - DBE_VT_640_480_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 640, 480, 59940, 25175, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 800, 640, 800, 656, 752, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 525, 480, 525, 490, 492, - /* pll_m, pll_n, pll_p */ - 15, 2, 3 - }, - - { - DBE_VT_800_600_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 800, 600, 60317, 40000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1056, 800, 1056, 840, 968, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 628, 600, 628, 601, 605, - /* pll_m, pll_n, pll_p */ - 3, 1, 1 - }, - - { - DBE_VT_800_600_75, - /* flags, width, height, fields_sec, cfreq */ - 0, 800, 600, 75000, 49500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1056, 800, 1056, 816, 896, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 625, 600, 625, 601, 604, - /* pll_m, pll_n, pll_p */ - 11, 3, 1 - }, - - { - DBE_VT_800_600_120, - /* flags, width, height, fields_sec, cfreq */ - DBE_VOF_STEREO, 800, 600, 119800, 82978, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1040, 800, 1040, 856, 976, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 666, 600, 666, 637, 643, - /* pll_m, pll_n, pll_p */ - 31, 5, 1 - }, - - { - DBE_VT_1024_768_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1024, 768, 50000, 54163, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1344, 1024, 1344, 1048, 1184, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 806, 768, 806, 771, 777, - /* pll_m, pll_n, pll_p */ - 4, 1, 1 - }, - - { - DBE_VT_1024_768_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1024, 768, 60004, 65000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1344, 1024, 1344, 1048, 1184, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 806, 768, 806, 771, 777, - /* pll_m, pll_n, pll_p */ - 12, 5, 0 - }, - - { - DBE_VT_1024_768_75, - /* flags, width, height, fields_sec, cfreq */ - 0, 1024, 768, 75029, 78750, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1312, 1024, 1312, 1040, 1136, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 800, 768, 800, 769, 772, - /* pll_m, pll_n, pll_p */ - 29, 5, 1 - }, - - { - DBE_VT_1024_768_85, - /* flags, width, height, fields_sec, cfreq */ - 0, 1024, 768, 84997, 94500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1376, 1024, 1376, 1072, 1168, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 808, 768, 808, 769, 772, - /* pll_m, pll_n, pll_p */ - 7, 2, 0 - }, - - { - DBE_VT_1024_768_120, - /* flags, width, height, fields_sec, cfreq */ - DBE_VOF_STEREO, 1024, 768, 119800, 133195, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1376, 1024, 1376, 1072, 1168, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 808, 768, 808, 769, 772, - /* pll_m, pll_n, pll_p */ - 5, 1, 0 - }, - - { - DBE_VT_1280_1024_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1280, 1024, 50000, 89460, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1680, 1280, 1680, 1360, 1480, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1065, 1024, 1065, 1027, 1030, - /* pll_m, pll_n, pll_p */ - 10, 3, 0 - }, - - { - DBE_VT_1280_1024_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1280, 1024, 60020, 108000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1688, 1280, 1688, 1328, 1440, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1066, 1024, 1066, 1025, 1028, - /* pll_m, pll_n, pll_p */ - 4, 1, 0 - }, - - { - DBE_VT_1280_1024_75, - /* flags, width, height, fields_sec, cfreq */ - 0, 1280, 1024, 75025, 135000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1688, 1280, 1688, 1296, 1440, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1066, 1024, 1066, 1025, 1028, - /* pll_m, pll_n, pll_p */ - 5, 1, 0 - }, - - { - DBE_VT_1280_1024_85, - /* flags, width, height, fields_sec, cfreq */ - 0, 1280, 1024, 85024, 157500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1728, 1280, 1728, 1344, 1504, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1072, 1024, 1072, 1025, 1028, - /* pll_m, pll_n, pll_p */ - 29, 5, 0 - }, - - { - DBE_VT_1600_1024_53, - /* flags, width, height, fields_sec, cfreq */ - DBE_VOF_FLATPANEL | DBE_VOF_MAGICKEY, - 1600, 1024, 53000, 107447, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1900, 1600, 1900, 1630, 1730, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1067, 1024, 1067, 1027, 1030, - /* pll_m, pll_n, pll_p */ - 4, 1, 0 - }, - - { - DBE_VT_1600_1024_60, - /* flags, width, height, fields_sec, cfreq */ - DBE_VOF_FLATPANEL, 1600, 1024, 60000, 106913, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1670, 1600, 1670, 1630, 1650, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1067, 1024, 1067, 1027, 1030, - /* pll_m, pll_n, pll_p */ - 4, 1, 0 - }, - - { - DBE_VT_1600_1200_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1600, 1200, 50000, 130500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2088, 1600, 2088, 1644, 1764, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1205, 1211, - /* pll_m, pll_n, pll_p */ - 24, 5, 0 - }, - - { - DBE_VT_1600_1200_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1600, 1200, 59940, 162000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2160, 1600, 2160, 1644, 1856, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1201, 1204, - /* pll_m, pll_n, pll_p */ - 6, 1, 0 - }, - - { - DBE_VT_1600_1200_75, - /* flags, width, height, fields_sec, cfreq */ - 0, 1600, 1200, 75000, 202500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2160, 1600, 2160, 1644, 1856, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1201, 1204, - /* pll_m, pll_n, pll_p */ - 15, 2, 0 - }, - - { - DBE_VT_1920_1080_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1080, 50000, 133200, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2368, 1920, 2368, 1952, 2096, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1125, 1080, 1125, 1083, 1086, - /* pll_m, pll_n, pll_p */ - 5, 1, 0 - }, - - { - DBE_VT_1920_1080_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1080, 59940, 159840, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2368, 1920, 2368, 1952, 2096, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1125, 1080, 1125, 1083, 1086, - /* pll_m, pll_n, pll_p */ - 6, 1, 0 - }, - - { - DBE_VT_1920_1080_72, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1080, 72000, 216023, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2560, 1920, 2560, 1968, 2184, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1172, 1080, 1172, 1083, 1086, - /* pll_m, pll_n, pll_p */ - 8, 1, 0 - }, - - { - DBE_VT_1920_1200_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1200, 50000, 161500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2584, 1920, 2584, 1984, 2240, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1203, 1206, - /* pll_m, pll_n, pll_p */ - 6, 1, 0 - }, - - { - DBE_VT_1920_1200_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1200, 59940, 193800, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2584, 1920, 2584, 1984, 2240, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1203, 1206, - /* pll_m, pll_n, pll_p */ - 29, 4, 0 - }, - - { - DBE_VT_1920_1200_66, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1200, 66000, 213180, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2584, 1920, 2584, 1984, 2240, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1203, 1206, - /* pll_m, pll_n, pll_p */ - 8, 1, 0 - } -}; - -#endif // INCLUDE_TIMING_TABLE_DATA - -#endif // ! __SGIVWFB_H__ diff --git a/include/video/sh_mipi_dsi.h b/include/video/sh_mipi_dsi.h index 06c67fbc4ee..a01f197e6ac 100644 --- a/include/video/sh_mipi_dsi.h +++ b/include/video/sh_mipi_dsi.h @@ -25,8 +25,6 @@ enum sh_mipi_dsi_data_fmt { MIPI_YUV420, }; -struct sh_mobile_lcdc_chan_cfg; - #define SH_MIPI_DSI_HSABM (1 << 0) #define SH_MIPI_DSI_HBPBM (1 << 1) #define SH_MIPI_DSI_HFPBM (1 << 2) @@ -47,7 +45,7 @@ struct sh_mobile_lcdc_chan_cfg; struct sh_mipi_dsi_info { enum sh_mipi_dsi_data_fmt data_format; - struct sh_mobile_lcdc_chan_cfg *lcd_chan; + int channel; int lane; unsigned long flags; u32 clksrc; diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h index ff43ffc1aab..2605fa8adb9 100644 --- a/include/video/sh_mobile_lcdc.h +++ b/include/video/sh_mobile_lcdc.h @@ -163,7 +163,6 @@ struct sh_mobile_lcdc_bl_info { const char *name; int max_brightness; int (*set_brightness)(int brightness); - int (*get_brightness)(void); }; struct sh_mobile_lcdc_overlay_cfg { diff --git a/include/video/sisfb.h b/include/video/sisfb.h index 6dc5df9e43f..6ddff93108f 100644 --- a/include/video/sisfb.h +++ b/include/video/sisfb.h @@ -17,197 +17,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA */ - #ifndef _LINUX_SISFB_H_ #define _LINUX_SISFB_H_ -#include <linux/types.h> -#include <asm/ioctl.h> - -/**********************************************/ -/* PUBLIC */ -/**********************************************/ - -/* vbflags, public (others in sis.h) */ -#define CRT2_DEFAULT 0x00000001 -#define CRT2_LCD 0x00000002 -#define CRT2_TV 0x00000004 -#define CRT2_VGA 0x00000008 -#define TV_NTSC 0x00000010 -#define TV_PAL 0x00000020 -#define TV_HIVISION 0x00000040 -#define TV_YPBPR 0x00000080 -#define TV_AVIDEO 0x00000100 -#define TV_SVIDEO 0x00000200 -#define TV_SCART 0x00000400 -#define TV_PALM 0x00001000 -#define TV_PALN 0x00002000 -#define TV_NTSCJ 0x00001000 -#define TV_CHSCART 0x00008000 -#define TV_CHYPBPR525I 0x00010000 -#define CRT1_VGA 0x00000000 -#define CRT1_LCDA 0x00020000 -#define VGA2_CONNECTED 0x00040000 -#define VB_DISPTYPE_CRT1 0x00080000 /* CRT1 connected and used */ -#define VB_SINGLE_MODE 0x20000000 /* CRT1 or CRT2; determined by DISPTYPE_CRTx */ -#define VB_MIRROR_MODE 0x40000000 /* CRT1 + CRT2 identical (mirror mode) */ -#define VB_DUALVIEW_MODE 0x80000000 /* CRT1 + CRT2 independent (dual head mode) */ - -/* Aliases: */ -#define CRT2_ENABLE (CRT2_LCD | CRT2_TV | CRT2_VGA) -#define TV_STANDARD (TV_NTSC | TV_PAL | TV_PALM | TV_PALN | TV_NTSCJ) -#define TV_INTERFACE (TV_AVIDEO|TV_SVIDEO|TV_SCART|TV_HIVISION|TV_YPBPR|TV_CHSCART|TV_CHYPBPR525I) - -/* Only if TV_YPBPR is set: */ -#define TV_YPBPR525I TV_NTSC -#define TV_YPBPR525P TV_PAL -#define TV_YPBPR750P TV_PALM -#define TV_YPBPR1080I TV_PALN -#define TV_YPBPRALL (TV_YPBPR525I | TV_YPBPR525P | TV_YPBPR750P | TV_YPBPR1080I) - -#define VB_DISPTYPE_DISP2 CRT2_ENABLE -#define VB_DISPTYPE_CRT2 CRT2_ENABLE -#define VB_DISPTYPE_DISP1 VB_DISPTYPE_CRT1 -#define VB_DISPMODE_SINGLE VB_SINGLE_MODE -#define VB_DISPMODE_MIRROR VB_MIRROR_MODE -#define VB_DISPMODE_DUAL VB_DUALVIEW_MODE -#define VB_DISPLAY_MODE (SINGLE_MODE | MIRROR_MODE | DUALVIEW_MODE) - -/* Structure argument for SISFB_GET_INFO ioctl */ -struct sisfb_info { - __u32 sisfb_id; /* for identifying sisfb */ -#ifndef SISFB_ID -#define SISFB_ID 0x53495346 /* Identify myself with 'SISF' */ -#endif - __u32 chip_id; /* PCI-ID of detected chip */ - __u32 memory; /* total video memory in KB */ - __u32 heapstart; /* heap start offset in KB */ - __u8 fbvidmode; /* current sisfb mode */ - - __u8 sisfb_version; - __u8 sisfb_revision; - __u8 sisfb_patchlevel; - - __u8 sisfb_caps; /* sisfb capabilities */ - - __u32 sisfb_tqlen; /* turbo queue length (in KB) */ - - __u32 sisfb_pcibus; /* The card's PCI ID */ - __u32 sisfb_pcislot; - __u32 sisfb_pcifunc; - - __u8 sisfb_lcdpdc; /* PanelDelayCompensation */ - - __u8 sisfb_lcda; /* Detected status of LCDA for low res/text modes */ - - __u32 sisfb_vbflags; - __u32 sisfb_currentvbflags; - - __u32 sisfb_scalelcd; - __u32 sisfb_specialtiming; - - __u8 sisfb_haveemi; - __u8 sisfb_emi30,sisfb_emi31,sisfb_emi32,sisfb_emi33; - __u8 sisfb_haveemilcd; - - __u8 sisfb_lcdpdca; /* PanelDelayCompensation for LCD-via-CRT1 */ - - __u16 sisfb_tvxpos, sisfb_tvypos; /* Warning: Values + 32 ! */ - - __u32 sisfb_heapsize; /* heap size (in KB) */ - __u32 sisfb_videooffset; /* Offset of viewport in video memory (in bytes) */ - - __u32 sisfb_curfstn; /* currently running FSTN/DSTN mode */ - __u32 sisfb_curdstn; - - __u16 sisfb_pci_vendor; /* PCI vendor (SiS or XGI) */ - - __u32 sisfb_vbflags2; /* ivideo->vbflags2 */ - - __u8 sisfb_can_post; /* sisfb can POST this card */ - __u8 sisfb_card_posted; /* card is POSTED */ - __u8 sisfb_was_boot_device; /* This card was the boot video device (ie is primary) */ - - __u8 reserved[183]; /* for future use */ -}; - -#define SISFB_CMD_GETVBFLAGS 0x55AA0001 /* no arg; result[1] = vbflags */ -#define SISFB_CMD_SWITCHCRT1 0x55AA0010 /* arg[0]: 99 = query, 0 = off, 1 = on */ -/* more to come */ - -#define SISFB_CMD_ERR_OK 0x80000000 /* command succeeded */ -#define SISFB_CMD_ERR_LOCKED 0x80000001 /* sisfb is locked */ -#define SISFB_CMD_ERR_EARLY 0x80000002 /* request before sisfb took over gfx system */ -#define SISFB_CMD_ERR_NOVB 0x80000003 /* No video bridge */ -#define SISFB_CMD_ERR_NOCRT2 0x80000004 /* can't change CRT1 status, CRT2 disabled */ -/* more to come */ -#define SISFB_CMD_ERR_UNKNOWN 0x8000ffff /* Unknown command */ -#define SISFB_CMD_ERR_OTHER 0x80010000 /* Other error */ - -/* Argument for SISFB_CMD ioctl */ -struct sisfb_cmd { - __u32 sisfb_cmd; - __u32 sisfb_arg[16]; - __u32 sisfb_result[4]; -}; - -/* Additional IOCTLs for communication sisfb <> X driver */ -/* If changing this, vgatypes.h must also be changed (for X driver) */ - -/* ioctl for identifying and giving some info (esp. memory heap start) */ -#define SISFB_GET_INFO_SIZE _IOR(0xF3,0x00,__u32) -#define SISFB_GET_INFO _IOR(0xF3,0x01,struct sisfb_info) - -/* ioctrl to get current vertical retrace status */ -#define SISFB_GET_VBRSTATUS _IOR(0xF3,0x02,__u32) - -/* ioctl to enable/disable panning auto-maximize (like nomax parameter) */ -#define SISFB_GET_AUTOMAXIMIZE _IOR(0xF3,0x03,__u32) -#define SISFB_SET_AUTOMAXIMIZE _IOW(0xF3,0x03,__u32) - -/* ioctls to relocate TV output (x=D[31:16], y=D[15:0], + 32)*/ -#define SISFB_GET_TVPOSOFFSET _IOR(0xF3,0x04,__u32) -#define SISFB_SET_TVPOSOFFSET _IOW(0xF3,0x04,__u32) - -/* ioctl for internal sisfb commands (sisfbctrl) */ -#define SISFB_COMMAND _IOWR(0xF3,0x05,struct sisfb_cmd) - -/* ioctl for locking sisfb (no register access during lock) */ -/* As of now, only used to avoid register access during - * the ioctls listed above. - */ -#define SISFB_SET_LOCK _IOW(0xF3,0x06,__u32) - -/* ioctls 0xF3 up to 0x3F reserved for sisfb */ - -/****************************************************************/ -/* The following are deprecated and should not be used anymore: */ -/****************************************************************/ -/* ioctl for identifying and giving some info (esp. memory heap start) */ -#define SISFB_GET_INFO_OLD _IOR('n',0xF8,__u32) -/* ioctrl to get current vertical retrace status */ -#define SISFB_GET_VBRSTATUS_OLD _IOR('n',0xF9,__u32) -/* ioctl to enable/disable panning auto-maximize (like nomax parameter) */ -#define SISFB_GET_AUTOMAXIMIZE_OLD _IOR('n',0xFA,__u32) -#define SISFB_SET_AUTOMAXIMIZE_OLD _IOW('n',0xFA,__u32) -/****************************************************************/ -/* End of deprecated ioctl numbers */ -/****************************************************************/ - -/* For fb memory manager (FBIO_ALLOC, FBIO_FREE) */ -struct sis_memreq { - __u32 offset; - __u32 size; -}; - -/**********************************************/ -/* PRIVATE */ -/* (for IN-KERNEL usage only) */ -/**********************************************/ - -#ifdef __KERNEL__ #include <linux/pci.h> +#include <uapi/video/sisfb.h> #define UNKNOWN_VGA 0 #define SIS_300_VGA 1 @@ -220,5 +35,3 @@ extern void sis_malloc_new(struct pci_dev *pdev, struct sis_memreq *req); extern void sis_free(u32 base); extern void sis_free_new(struct pci_dev *pdev, u32 base); #endif - -#endif diff --git a/include/video/uvesafb.h b/include/video/uvesafb.h index 0993a220a3e..30f53625415 100644 --- a/include/video/uvesafb.h +++ b/include/video/uvesafb.h @@ -1,63 +1,8 @@ #ifndef _UVESAFB_H #define _UVESAFB_H -#include <linux/types.h> - -struct v86_regs { - __u32 ebx; - __u32 ecx; - __u32 edx; - __u32 esi; - __u32 edi; - __u32 ebp; - __u32 eax; - __u32 eip; - __u32 eflags; - __u32 esp; - __u16 cs; - __u16 ss; - __u16 es; - __u16 ds; - __u16 fs; - __u16 gs; -}; - -/* Task flags */ -#define TF_VBEIB 0x01 -#define TF_BUF_ESDI 0x02 -#define TF_BUF_ESBX 0x04 -#define TF_BUF_RET 0x08 -#define TF_EXIT 0x10 - -struct uvesafb_task { - __u8 flags; - int buf_len; - struct v86_regs regs; -}; - -/* Constants for the capabilities field - * in vbe_ib */ -#define VBE_CAP_CAN_SWITCH_DAC 0x01 -#define VBE_CAP_VGACOMPAT 0x02 - -/* The VBE Info Block */ -struct vbe_ib { - char vbe_signature[4]; - __u16 vbe_version; - __u32 oem_string_ptr; - __u32 capabilities; - __u32 mode_list_ptr; - __u16 total_memory; - __u16 oem_software_rev; - __u32 oem_vendor_name_ptr; - __u32 oem_product_name_ptr; - __u32 oem_product_rev_ptr; - __u8 reserved[222]; - char oem_data[256]; - char misc_data[512]; -} __attribute__ ((packed)); +#include <uapi/video/uvesafb.h> -#ifdef __KERNEL__ /* VBE CRTC Info Block */ struct vbe_crtc_ib { @@ -189,7 +134,7 @@ struct uvesafb_par { int mode_idx; struct vbe_crtc_ib crtc; + int mtrr_handle; }; -#endif /* __KERNEL__ */ #endif /* _UVESAFB_H */ diff --git a/include/video/videomode.h b/include/video/videomode.h new file mode 100644 index 00000000000..3f1049d870d --- /dev/null +++ b/include/video/videomode.h @@ -0,0 +1,58 @@ +/* + * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * generic videomode description + * + * This file is released under the GPLv2 + */ + +#ifndef __LINUX_VIDEOMODE_H +#define __LINUX_VIDEOMODE_H + +#include <linux/types.h> +#include <video/display_timing.h> + +/* + * Subsystem independent description of a videomode. + * Can be generated from struct display_timing. + */ +struct videomode { + unsigned long pixelclock; /* pixelclock in Hz */ + + u32 hactive; + u32 hfront_porch; + u32 hback_porch; + u32 hsync_len; + + u32 vactive; + u32 vfront_porch; + u32 vback_porch; + u32 vsync_len; + + enum display_flags flags; /* display flags */ +}; + +/** + * videomode_from_timing - convert display timing to videomode + * @dt: display_timing structure + * @vm: return value + * + * DESCRIPTION: + * This function converts a struct display_timing to a struct videomode. + */ +void videomode_from_timing(const struct display_timing *dt, + struct videomode *vm); + +/** + * videomode_from_timings - convert one display timings entry to videomode + * @disp: structure with all possible timing entries + * @vm: return value + * @index: index into the list of display timings in devicetree + * + * DESCRIPTION: + * This function converts one struct display_timing entry to a struct videomode. + */ +int videomode_from_timings(const struct display_timings *disp, + struct videomode *vm, unsigned int index); + +#endif |