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-rw-r--r--include/video/atmel_lcdc.h25
-rw-r--r--include/video/auo_k190xfb.h3
-rw-r--r--include/video/da8xx-fb.h5
-rw-r--r--include/video/display_timing.h58
-rw-r--r--include/video/exynos_dp.h131
-rw-r--r--include/video/exynos_mipi_dsim.h5
-rw-r--r--include/video/imx-ipu-v3.h347
-rw-r--r--include/video/mmp_disp.h6
-rw-r--r--include/video/of_display_timing.h3
-rw-r--r--include/video/omap-panel-data.h254
-rw-r--r--include/video/omap-panel-generic-dpi.h37
-rw-r--r--include/video/omap-panel-n8x0.h15
-rw-r--r--include/video/omap-panel-nokia-dsi.h32
-rw-r--r--include/video/omap-panel-picodlp.h23
-rw-r--r--include/video/omap-panel-tfp410.h35
-rw-r--r--include/video/omapdss.h483
-rw-r--r--include/video/platform_lcd.h1
-rw-r--r--include/video/pxa168fb.h2
-rw-r--r--include/video/sgivw.h681
-rw-r--r--include/video/uvesafb.h1
-rw-r--r--include/video/videomode.h18
21 files changed, 958 insertions, 1207 deletions
diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
index 28447f1594f..c79f3813192 100644
--- a/include/video/atmel_lcdc.h
+++ b/include/video/atmel_lcdc.h
@@ -30,38 +30,21 @@
*/
#define ATMEL_LCDC_WIRING_BGR 0
#define ATMEL_LCDC_WIRING_RGB 1
-#define ATMEL_LCDC_WIRING_RGB555 2
/* LCD Controller info data structure, stored in device platform_data */
-struct atmel_lcdfb_info {
- spinlock_t lock;
- struct fb_info *info;
- void __iomem *mmio;
- int irq_base;
- struct work_struct task;
-
+struct atmel_lcdfb_pdata {
unsigned int guard_time;
- unsigned int smem_len;
- struct platform_device *pdev;
- struct clk *bus_clk;
- struct clk *lcdc_clk;
-
-#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
- struct backlight_device *backlight;
- u8 bl_power;
-#endif
bool lcdcon_is_backlight;
bool lcdcon_pol_negative;
- u8 saved_lcdcon;
-
u8 default_bpp;
u8 lcd_wiring_mode;
unsigned int default_lcdcon2;
unsigned int default_dmacon;
- void (*atmel_lcdfb_power_control)(int on);
+ void (*atmel_lcdfb_power_control)(struct atmel_lcdfb_pdata *pdata, int on);
struct fb_monspecs *default_monspecs;
- u32 pseudo_palette[16];
+
+ struct list_head pwr_gpios;
};
#define ATMEL_LCDC_DMABADDR1 0x00
diff --git a/include/video/auo_k190xfb.h b/include/video/auo_k190xfb.h
index 609efe8c686..ac329ee1d75 100644
--- a/include/video/auo_k190xfb.h
+++ b/include/video/auo_k190xfb.h
@@ -22,6 +22,8 @@
*/
#define AUOK190X_RESOLUTION_800_600 0
#define AUOK190X_RESOLUTION_1024_768 1
+#define AUOK190X_RESOLUTION_600_800 4
+#define AUOK190X_RESOLUTION_768_1024 5
/*
* struct used by auok190x. board specific stuff comes from *board
@@ -98,7 +100,6 @@ struct auok190x_board {
int gpio_nbusy;
int resolution;
- int rotation;
int quirks;
int fps;
};
diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h
index f88825928dd..efed3c3383d 100644
--- a/include/video/da8xx-fb.h
+++ b/include/video/da8xx-fb.h
@@ -23,6 +23,11 @@ enum raster_load_mode {
LOAD_PALETTE,
};
+enum da8xx_frame_complete {
+ DA8XX_FRAME_WAIT,
+ DA8XX_FRAME_NOWAIT,
+};
+
struct da8xx_lcdc_platform_data {
const char manu_name[10];
void *controller_data;
diff --git a/include/video/display_timing.h b/include/video/display_timing.h
index 71e9a383a98..28d9d0d566c 100644
--- a/include/video/display_timing.h
+++ b/include/video/display_timing.h
@@ -12,19 +12,23 @@
#include <linux/bitops.h>
#include <linux/types.h>
-/* VESA display monitor timing parameters */
-#define VESA_DMT_HSYNC_LOW BIT(0)
-#define VESA_DMT_HSYNC_HIGH BIT(1)
-#define VESA_DMT_VSYNC_LOW BIT(2)
-#define VESA_DMT_VSYNC_HIGH BIT(3)
-
-/* display specific flags */
-#define DISPLAY_FLAGS_DE_LOW BIT(0) /* data enable flag */
-#define DISPLAY_FLAGS_DE_HIGH BIT(1)
-#define DISPLAY_FLAGS_PIXDATA_POSEDGE BIT(2) /* drive data on pos. edge */
-#define DISPLAY_FLAGS_PIXDATA_NEGEDGE BIT(3) /* drive data on neg. edge */
-#define DISPLAY_FLAGS_INTERLACED BIT(4)
-#define DISPLAY_FLAGS_DOUBLESCAN BIT(5)
+enum display_flags {
+ DISPLAY_FLAGS_HSYNC_LOW = BIT(0),
+ DISPLAY_FLAGS_HSYNC_HIGH = BIT(1),
+ DISPLAY_FLAGS_VSYNC_LOW = BIT(2),
+ DISPLAY_FLAGS_VSYNC_HIGH = BIT(3),
+
+ /* data enable flag */
+ DISPLAY_FLAGS_DE_LOW = BIT(4),
+ DISPLAY_FLAGS_DE_HIGH = BIT(5),
+ /* drive data on pos. edge */
+ DISPLAY_FLAGS_PIXDATA_POSEDGE = BIT(6),
+ /* drive data on neg. edge */
+ DISPLAY_FLAGS_PIXDATA_NEGEDGE = BIT(7),
+ DISPLAY_FLAGS_INTERLACED = BIT(8),
+ DISPLAY_FLAGS_DOUBLESCAN = BIT(9),
+ DISPLAY_FLAGS_DOUBLECLK = BIT(10),
+};
/*
* A single signal can be specified via a range of minimal and maximal values
@@ -36,12 +40,6 @@ struct timing_entry {
u32 max;
};
-enum timing_entry_index {
- TE_MIN = 0,
- TE_TYP = 1,
- TE_MAX = 2,
-};
-
/*
* Single "mode" entry. This describes one set of signal timings a display can
* have in one setting. This struct can later be converted to struct videomode
@@ -72,8 +70,7 @@ struct display_timing {
struct timing_entry vback_porch; /* ver. back porch */
struct timing_entry vsync_len; /* ver. sync len */
- unsigned int dmt_flags; /* VESA DMT flags */
- unsigned int data_flags; /* video data flags */
+ enum display_flags flags; /* display flags */
};
/*
@@ -89,25 +86,6 @@ struct display_timings {
struct display_timing **timings;
};
-/* get value specified by index from struct timing_entry */
-static inline u32 display_timing_get_value(const struct timing_entry *te,
- enum timing_entry_index index)
-{
- switch (index) {
- case TE_MIN:
- return te->min;
- break;
- case TE_TYP:
- return te->typ;
- break;
- case TE_MAX:
- return te->max;
- break;
- default:
- return te->typ;
- }
-}
-
/* get one entry from struct display_timings */
static inline struct display_timing *display_timings_get(const struct
display_timings *disp,
diff --git a/include/video/exynos_dp.h b/include/video/exynos_dp.h
deleted file mode 100644
index bd8cabd344d..00000000000
--- a/include/video/exynos_dp.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Samsung SoC DP device support
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _EXYNOS_DP_H
-#define _EXYNOS_DP_H
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-
-enum link_rate_type {
- LINK_RATE_1_62GBPS = 0x06,
- LINK_RATE_2_70GBPS = 0x0a
-};
-
-enum link_lane_count_type {
- LANE_COUNT1 = 1,
- LANE_COUNT2 = 2,
- LANE_COUNT4 = 4
-};
-
-enum link_training_state {
- START,
- CLOCK_RECOVERY,
- EQUALIZER_TRAINING,
- FINISHED,
- FAILED
-};
-
-enum voltage_swing_level {
- VOLTAGE_LEVEL_0,
- VOLTAGE_LEVEL_1,
- VOLTAGE_LEVEL_2,
- VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
- PRE_EMPHASIS_LEVEL_0,
- PRE_EMPHASIS_LEVEL_1,
- PRE_EMPHASIS_LEVEL_2,
- PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
- PRBS7,
- D10_2,
- TRAINING_PTN1,
- TRAINING_PTN2,
- DP_NONE
-};
-
-enum color_space {
- COLOR_RGB,
- COLOR_YCBCR422,
- COLOR_YCBCR444
-};
-
-enum color_depth {
- COLOR_6,
- COLOR_8,
- COLOR_10,
- COLOR_12
-};
-
-enum color_coefficient {
- COLOR_YCBCR601,
- COLOR_YCBCR709
-};
-
-enum dynamic_range {
- VESA,
- CEA
-};
-
-enum pll_status {
- PLL_UNLOCKED,
- PLL_LOCKED
-};
-
-enum clock_recovery_m_value_type {
- CALCULATED_M,
- REGISTER_M
-};
-
-enum video_timing_recognition_type {
- VIDEO_TIMING_FROM_CAPTURE,
- VIDEO_TIMING_FROM_REGISTER
-};
-
-enum analog_power_block {
- AUX_BLOCK,
- CH0_BLOCK,
- CH1_BLOCK,
- CH2_BLOCK,
- CH3_BLOCK,
- ANALOG_TOTAL,
- POWER_ALL
-};
-
-struct video_info {
- char *name;
-
- bool h_sync_polarity;
- bool v_sync_polarity;
- bool interlaced;
-
- enum color_space color_space;
- enum dynamic_range dynamic_range;
- enum color_coefficient ycbcr_coeff;
- enum color_depth color_depth;
-
- enum link_rate_type link_rate;
- enum link_lane_count_type lane_count;
-};
-
-struct exynos_dp_platdata {
- struct video_info *video_info;
-
- void (*phy_init)(void);
- void (*phy_exit)(void);
-};
-
-#endif /* _EXYNOS_DP_H */
diff --git a/include/video/exynos_mipi_dsim.h b/include/video/exynos_mipi_dsim.h
index 89dc88a171a..6a578f8a1b3 100644
--- a/include/video/exynos_mipi_dsim.h
+++ b/include/video/exynos_mipi_dsim.h
@@ -216,6 +216,7 @@ struct mipi_dsim_config {
* automatically.
* @e_clk_src: select byte clock source.
* @pd: pointer to MIPI-DSI driver platform data.
+ * @phy: pointer to the MIPI-DSI PHY
*/
struct mipi_dsim_device {
struct device *dev;
@@ -236,6 +237,7 @@ struct mipi_dsim_device {
bool suspended;
struct mipi_dsim_platform_data *pd;
+ struct phy *phy;
};
/*
@@ -248,7 +250,6 @@ struct mipi_dsim_device {
* @enabled: indicate whether mipi controller got enabled or not.
* @lcd_panel_info: pointer for lcd panel specific structure.
* this structure specifies width, height, timing and polarity and so on.
- * @phy_enable: pointer to a callback controlling D-PHY enable/reset
*/
struct mipi_dsim_platform_data {
char lcd_panel_name[PANEL_NAME_SIZE];
@@ -256,8 +257,6 @@ struct mipi_dsim_platform_data {
struct mipi_dsim_config *dsim_config;
unsigned int enabled;
void *lcd_panel_info;
-
- int (*phy_enable)(struct platform_device *pdev, bool on);
};
/*
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
new file mode 100644
index 00000000000..3e43e22cdff
--- /dev/null
+++ b/include/video/imx-ipu-v3.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright 2005-2009 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License. You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+#ifndef __DRM_IPU_H__
+#define __DRM_IPU_H__
+
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/bitmap.h>
+#include <linux/fb.h>
+
+struct ipu_soc;
+
+enum ipuv3_type {
+ IPUV3EX,
+ IPUV3M,
+ IPUV3H,
+};
+
+#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
+
+/*
+ * Bitfield of Display Interface signal polarities.
+ */
+struct ipu_di_signal_cfg {
+ unsigned datamask_en:1;
+ unsigned interlaced:1;
+ unsigned odd_field_first:1;
+ unsigned clksel_en:1;
+ unsigned clkidle_en:1;
+ unsigned data_pol:1; /* true = inverted */
+ unsigned clk_pol:1; /* true = rising edge */
+ unsigned enable_pol:1;
+ unsigned Hsync_pol:1; /* true = active high */
+ unsigned Vsync_pol:1;
+
+ u16 width;
+ u16 height;
+ u32 pixel_fmt;
+ u16 h_start_width;
+ u16 h_sync_width;
+ u16 h_end_width;
+ u16 v_start_width;
+ u16 v_sync_width;
+ u16 v_end_width;
+ u32 v_to_h_sync;
+ unsigned long pixelclock;
+#define IPU_DI_CLKMODE_SYNC (1 << 0)
+#define IPU_DI_CLKMODE_EXT (1 << 1)
+ unsigned long clkflags;
+
+ u8 hsync_pin;
+ u8 vsync_pin;
+};
+
+enum ipu_color_space {
+ IPUV3_COLORSPACE_RGB,
+ IPUV3_COLORSPACE_YUV,
+ IPUV3_COLORSPACE_UNKNOWN,
+};
+
+struct ipuv3_channel;
+
+enum ipu_channel_irq {
+ IPU_IRQ_EOF = 0,
+ IPU_IRQ_NFACK = 64,
+ IPU_IRQ_NFB4EOF = 128,
+ IPU_IRQ_EOS = 192,
+};
+
+int ipu_map_irq(struct ipu_soc *ipu, int irq);
+int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
+ enum ipu_channel_irq irq);
+
+#define IPU_IRQ_DP_SF_START (448 + 2)
+#define IPU_IRQ_DP_SF_END (448 + 3)
+#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
+#define IPU_IRQ_DC_FC_0 (448 + 8)
+#define IPU_IRQ_DC_FC_1 (448 + 9)
+#define IPU_IRQ_DC_FC_2 (448 + 10)
+#define IPU_IRQ_DC_FC_3 (448 + 11)
+#define IPU_IRQ_DC_FC_4 (448 + 12)
+#define IPU_IRQ_DC_FC_6 (448 + 13)
+#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
+#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
+
+/*
+ * IPU Image DMA Controller (idmac) functions
+ */
+struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
+void ipu_idmac_put(struct ipuv3_channel *);
+
+int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
+int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
+int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
+
+void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
+ bool doublebuffer);
+int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
+void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
+
+/*
+ * IPU Display Controller (dc) functions
+ */
+struct ipu_dc;
+struct ipu_di;
+struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
+void ipu_dc_put(struct ipu_dc *dc);
+int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
+ u32 pixel_fmt, u32 width);
+void ipu_dc_enable(struct ipu_soc *ipu);
+void ipu_dc_enable_channel(struct ipu_dc *dc);
+void ipu_dc_disable_channel(struct ipu_dc *dc);
+void ipu_dc_disable(struct ipu_soc *ipu);
+
+/*
+ * IPU Display Interface (di) functions
+ */
+struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
+void ipu_di_put(struct ipu_di *);
+int ipu_di_disable(struct ipu_di *);
+int ipu_di_enable(struct ipu_di *);
+int ipu_di_get_num(struct ipu_di *);
+int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
+
+/*
+ * IPU Display Multi FIFO Controller (dmfc) functions
+ */
+struct dmfc_channel;
+int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
+void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
+int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
+ unsigned long bandwidth_mbs, int burstsize);
+void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
+int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
+struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
+void ipu_dmfc_put(struct dmfc_channel *dmfc);
+
+/*
+ * IPU Display Processor (dp) functions
+ */
+#define IPU_DP_FLOW_SYNC_BG 0
+#define IPU_DP_FLOW_SYNC_FG 1
+#define IPU_DP_FLOW_ASYNC0_BG 2
+#define IPU_DP_FLOW_ASYNC0_FG 3
+#define IPU_DP_FLOW_ASYNC1_BG 4
+#define IPU_DP_FLOW_ASYNC1_FG 5
+
+struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
+void ipu_dp_put(struct ipu_dp *);
+int ipu_dp_enable(struct ipu_soc *ipu);
+int ipu_dp_enable_channel(struct ipu_dp *dp);
+void ipu_dp_disable_channel(struct ipu_dp *dp);
+void ipu_dp_disable(struct ipu_soc *ipu);
+int ipu_dp_setup_channel(struct ipu_dp *dp,
+ enum ipu_color_space in, enum ipu_color_space out);
+int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
+int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
+ bool bg_chan);
+
+/*
+ * IPU CMOS Sensor Interface (csi) functions
+ */
+int ipu_csi_enable(struct ipu_soc *ipu, int csi);
+int ipu_csi_disable(struct ipu_soc *ipu, int csi);
+
+/*
+ * IPU Sensor Multiple FIFO Controller (SMFC) functions
+ */
+int ipu_smfc_enable(struct ipu_soc *ipu);
+int ipu_smfc_disable(struct ipu_soc *ipu);
+int ipu_smfc_map_channel(struct ipu_soc *ipu, int channel, int csi_id, int mipi_id);
+int ipu_smfc_set_burstsize(struct ipu_soc *ipu, int channel, int burstsize);
+
+#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
+
+#define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
+#define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
+#define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
+#define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
+#define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
+#define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
+#define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
+
+#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
+#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
+#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
+#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
+#define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
+#define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
+#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
+#define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
+#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
+#define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
+#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
+#define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
+#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
+#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
+#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
+#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
+#define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
+#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
+#define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
+#define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
+#define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
+#define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
+#define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
+#define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
+#define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
+#define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
+#define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
+#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
+#define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
+#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
+#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
+#define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
+#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
+#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
+#define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
+#define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
+#define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
+#define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
+#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
+#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
+#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
+#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
+#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
+#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
+#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
+#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
+#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
+#define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
+#define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
+#define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
+
+struct ipu_cpmem_word {
+ u32 data[5];
+ u32 res[3];
+};
+
+struct ipu_ch_param {
+ struct ipu_cpmem_word word[2];
+};
+
+void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v);
+u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs);
+struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel);
+void ipu_ch_param_dump(struct ipu_ch_param __iomem *p);
+
+static inline void ipu_ch_param_zero(struct ipu_ch_param __iomem *p)
+{
+ int i;
+ void __iomem *base = p;
+
+ for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
+ writel(0, base + i * sizeof(u32));
+}
+
+static inline void ipu_cpmem_set_buffer(struct ipu_ch_param __iomem *p,
+ int bufnum, dma_addr_t buf)
+{
+ if (bufnum)
+ ipu_ch_param_write_field(p, IPU_FIELD_EBA1, buf >> 3);
+ else
+ ipu_ch_param_write_field(p, IPU_FIELD_EBA0, buf >> 3);
+}
+
+static inline void ipu_cpmem_set_resolution(struct ipu_ch_param __iomem *p,
+ int xres, int yres)
+{
+ ipu_ch_param_write_field(p, IPU_FIELD_FW, xres - 1);
+ ipu_ch_param_write_field(p, IPU_FIELD_FH, yres - 1);
+}
+
+static inline void ipu_cpmem_set_stride(struct ipu_ch_param __iomem *p,
+ int stride)
+{
+ ipu_ch_param_write_field(p, IPU_FIELD_SLY, stride - 1);
+}
+
+void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel);
+
+struct ipu_rgb {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+ int bits_per_pixel;
+};
+
+struct ipu_image {
+ struct v4l2_pix_format pix;
+ struct v4l2_rect rect;
+ dma_addr_t phys;
+};
+
+int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p,
+ int width);
+
+int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *,
+ const struct ipu_rgb *rgb);
+
+static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param *p,
+ int stride)
+{
+ ipu_ch_param_write_field(p, IPU_FIELD_SO, 1);
+ ipu_ch_param_write_field(p, IPU_FIELD_ILO, stride / 8);
+ ipu_ch_param_write_field(p, IPU_FIELD_SLY, (stride * 2) - 1);
+};
+
+void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format,
+ int stride, int height);
+void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p,
+ u32 pixel_format);
+void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p,
+ u32 pixel_format, int stride, int u_offset, int v_offset);
+int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat);
+int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
+ struct ipu_image *image);
+
+enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
+enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
+
+static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem *p,
+ int burstsize)
+{
+ ipu_ch_param_write_field(p, IPU_FIELD_NPB, burstsize - 1);
+};
+
+struct ipu_client_platformdata {
+ int csi;
+ int di;
+ int dc;
+ int dp;
+ int dmfc;
+ int dma[2];
+};
+
+#endif /* __DRM_IPU_H__ */
diff --git a/include/video/mmp_disp.h b/include/video/mmp_disp.h
index b9dd1fbb008..9fd9398368d 100644
--- a/include/video/mmp_disp.h
+++ b/include/video/mmp_disp.h
@@ -91,6 +91,11 @@ struct mmp_win {
u16 up_crop;
u16 bottom_crop;
int pix_fmt;
+ /*
+ * pitch[0]: graphics/video layer line length or y pitch
+ * pitch[1]/pitch[2]: video u/v pitch if non-zero
+ */
+ u32 pitch[3];
};
struct mmp_addr {
@@ -334,6 +339,7 @@ struct mmp_mach_path_config {
int output_type;
u32 path_config;
u32 link_config;
+ u32 dsi_rbswap;
};
struct mmp_mach_plat_info {
diff --git a/include/video/of_display_timing.h b/include/video/of_display_timing.h
index 8016eb727cf..79e6697af6c 100644
--- a/include/video/of_display_timing.h
+++ b/include/video/of_display_timing.h
@@ -10,10 +10,13 @@
#define __LINUX_OF_DISPLAY_TIMING_H
struct device_node;
+struct display_timing;
struct display_timings;
#define OF_USE_NATIVE_MODE -1
+int of_get_display_timing(struct device_node *np, const char *name,
+ struct display_timing *dt);
struct display_timings *of_get_display_timings(struct device_node *np);
int of_display_timings_exist(struct device_node *np);
diff --git a/include/video/omap-panel-data.h b/include/video/omap-panel-data.h
new file mode 100644
index 00000000000..69279c013ac
--- /dev/null
+++ b/include/video/omap-panel-data.h
@@ -0,0 +1,254 @@
+/*
+ * Header containing platform_data structs for omap panels
+ *
+ * Copyright (C) 2013 Texas Instruments
+ * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
+ * Archit Taneja <archit@ti.com>
+ *
+ * Copyright (C) 2011 Texas Instruments
+ * Author: Mayuresh Janorkar <mayur@ti.com>
+ *
+ * Copyright (C) 2010 Canonical Ltd.
+ * Author: Bryan Wu <bryan.wu@canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __OMAP_PANEL_DATA_H
+#define __OMAP_PANEL_DATA_H
+
+#include <video/omapdss.h>
+#include <video/display_timing.h>
+
+struct omap_dss_device;
+
+/**
+ * encoder_tfp410 platform data
+ * @name: name for this display entity
+ * @power_down_gpio: gpio number for PD pin (or -1 if not available)
+ * @data_lines: number of DPI datalines
+ */
+struct encoder_tfp410_platform_data {
+ const char *name;
+ const char *source;
+ int power_down_gpio;
+ int data_lines;
+};
+
+/**
+ * encoder_tpd12s015 platform data
+ * @name: name for this display entity
+ * @ct_cp_hpd_gpio: CT_CP_HPD gpio number
+ * @ls_oe_gpio: LS_OE gpio number
+ * @hpd_gpio: HPD gpio number
+ */
+struct encoder_tpd12s015_platform_data {
+ const char *name;
+ const char *source;
+
+ int ct_cp_hpd_gpio;
+ int ls_oe_gpio;
+ int hpd_gpio;
+};
+
+/**
+ * connector_dvi platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ * @i2c_bus_num: i2c bus number to be used for reading EDID
+ */
+struct connector_dvi_platform_data {
+ const char *name;
+ const char *source;
+ int i2c_bus_num;
+};
+
+/**
+ * connector_hdmi platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ */
+struct connector_hdmi_platform_data {
+ const char *name;
+ const char *source;
+};
+
+/**
+ * connector_atv platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ * @connector_type: composite/svideo
+ * @invert_polarity: invert signal polarity
+ */
+struct connector_atv_platform_data {
+ const char *name;
+ const char *source;
+
+ enum omap_dss_venc_type connector_type;
+ bool invert_polarity;
+};
+
+/**
+ * panel_dpi platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ * @data_lines: number of DPI datalines
+ * @display_timing: timings for this panel
+ * @backlight_gpio: gpio to enable/disable the backlight (or -1)
+ * @enable_gpio: gpio to enable/disable the panel (or -1)
+ */
+struct panel_dpi_platform_data {
+ const char *name;
+ const char *source;
+
+ int data_lines;
+
+ const struct display_timing *display_timing;
+
+ int backlight_gpio;
+ int enable_gpio;
+};
+
+/**
+ * panel_dsicm platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ * @reset_gpio: gpio to reset the panel (or -1)
+ * @use_ext_te: use external TE GPIO
+ * @ext_te_gpio: external TE GPIO
+ * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms)
+ * @use_dsi_backlight: true if panel uses DSI command to control backlight
+ * @pin_config: DSI pin configuration
+ */
+struct panel_dsicm_platform_data {
+ const char *name;
+ const char *source;
+
+ int reset_gpio;
+
+ bool use_ext_te;
+ int ext_te_gpio;
+
+ unsigned ulps_timeout;
+
+ bool use_dsi_backlight;
+
+ struct omap_dsi_pin_config pin_config;
+};
+
+/**
+ * panel_acx565akm platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ * @reset_gpio: gpio to reset the panel (or -1)
+ * @datapairs: number of SDI datapairs
+ */
+struct panel_acx565akm_platform_data {
+ const char *name;
+ const char *source;
+
+ int reset_gpio;
+
+ int datapairs;
+};
+
+/**
+ * panel_lb035q02 platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ * @data_lines: number of DPI datalines
+ * @backlight_gpio: gpio to enable/disable the backlight (or -1)
+ * @enable_gpio: gpio to enable/disable the panel (or -1)
+ */
+struct panel_lb035q02_platform_data {
+ const char *name;
+ const char *source;
+
+ int data_lines;
+
+ int backlight_gpio;
+ int enable_gpio;
+};
+
+/**
+ * panel_sharp_ls037v7dw01 platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ * @data_lines: number of DPI datalines
+ * @resb_gpio: reset signal GPIO
+ * @ini_gpio: power on control GPIO
+ * @mo_gpio: selection for resolution(VGA/QVGA) GPIO
+ * @lr_gpio: selection for horizontal scanning direction GPIO
+ * @ud_gpio: selection for vertical scanning direction GPIO
+ */
+struct panel_sharp_ls037v7dw01_platform_data {
+ const char *name;
+ const char *source;
+
+ int data_lines;
+
+ int resb_gpio;
+ int ini_gpio;
+ int mo_gpio;
+ int lr_gpio;
+ int ud_gpio;
+};
+
+/**
+ * panel-tpo-td043mtea1 platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ * @data_lines: number of DPI datalines
+ * @nreset_gpio: reset signal
+ */
+struct panel_tpo_td043mtea1_platform_data {
+ const char *name;
+ const char *source;
+
+ int data_lines;
+
+ int nreset_gpio;
+};
+
+/**
+ * panel-nec-nl8048hl11 platform data
+ * @name: name for this display entity
+ * @source: name of the display entity used as a video source
+ * @data_lines: number of DPI datalines
+ * @res_gpio: reset signal
+ * @qvga_gpio: selection for resolution(QVGA/WVGA)
+ */
+struct panel_nec_nl8048hl11_platform_data {
+ const char *name;
+ const char *source;
+
+ int data_lines;
+
+ int res_gpio;
+ int qvga_gpio;
+};
+
+/**
+ * panel-tpo-td028ttec1 platform data
+ * @name: name for display entity
+ * @source: name of the display entity used as a video source
+ * @data_lines: number of DPI datalines
+ */
+struct panel_tpo_td028ttec1_platform_data {
+ const char *name;
+ const char *source;
+
+ int data_lines;
+};
+
+#endif /* __OMAP_PANEL_DATA_H */
diff --git a/include/video/omap-panel-generic-dpi.h b/include/video/omap-panel-generic-dpi.h
deleted file mode 100644
index 127e3f20328..00000000000
--- a/include/video/omap-panel-generic-dpi.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Header for generic DPI panel driver
- *
- * Copyright (C) 2010 Canonical Ltd.
- * Author: Bryan Wu <bryan.wu@canonical.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __OMAP_PANEL_GENERIC_DPI_H
-#define __OMAP_PANEL_GENERIC_DPI_H
-
-struct omap_dss_device;
-
-/**
- * struct panel_generic_dpi_data - panel driver configuration data
- * @name: panel name
- * @platform_enable: platform specific panel enable function
- * @platform_disable: platform specific panel disable function
- */
-struct panel_generic_dpi_data {
- const char *name;
- int (*platform_enable)(struct omap_dss_device *dssdev);
- void (*platform_disable)(struct omap_dss_device *dssdev);
-};
-
-#endif /* __OMAP_PANEL_GENERIC_DPI_H */
diff --git a/include/video/omap-panel-n8x0.h b/include/video/omap-panel-n8x0.h
deleted file mode 100644
index 50a1302e2cf..00000000000
--- a/include/video/omap-panel-n8x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __OMAP_PANEL_N8X0_H
-#define __OMAP_PANEL_N8X0_H
-
-struct omap_dss_device;
-
-struct panel_n8x0_data {
- int (*platform_enable)(struct omap_dss_device *dssdev);
- void (*platform_disable)(struct omap_dss_device *dssdev);
- int panel_reset;
- int ctrl_pwrdown;
-
- int (*set_backlight)(struct omap_dss_device *dssdev, int level);
-};
-
-#endif
diff --git a/include/video/omap-panel-nokia-dsi.h b/include/video/omap-panel-nokia-dsi.h
deleted file mode 100644
index 04219a29553..00000000000
--- a/include/video/omap-panel-nokia-dsi.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __OMAP_NOKIA_DSI_PANEL_H
-#define __OMAP_NOKIA_DSI_PANEL_H
-
-struct omap_dss_device;
-
-/**
- * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration
- * @name: panel name
- * @use_ext_te: use external TE
- * @ext_te_gpio: external TE GPIO
- * @esd_interval: interval of ESD checks, 0 = disabled (ms)
- * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms)
- * @use_dsi_backlight: true if panel uses DSI command to control backlight
- * @pin_config: DSI pin configuration
- */
-struct nokia_dsi_panel_data {
- const char *name;
-
- int reset_gpio;
-
- bool use_ext_te;
- int ext_te_gpio;
-
- unsigned esd_interval;
- unsigned ulps_timeout;
-
- bool use_dsi_backlight;
-
- struct omap_dsi_pin_config pin_config;
-};
-
-#endif /* __OMAP_NOKIA_DSI_PANEL_H */
diff --git a/include/video/omap-panel-picodlp.h b/include/video/omap-panel-picodlp.h
deleted file mode 100644
index 1c342ef6f3a..00000000000
--- a/include/video/omap-panel-picodlp.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * panel data for picodlp panel
- *
- * Copyright (C) 2011 Texas Instruments
- *
- * Author: Mayuresh Janorkar <mayur@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __PANEL_PICODLP_H
-#define __PANEL_PICODLP_H
-/**
- * struct : picodlp panel data
- * picodlp_adapter_id: i2c_adapter number for picodlp
- */
-struct picodlp_panel_data {
- int picodlp_adapter_id;
- int emu_done_gpio;
- int pwrgood_gpio;
-};
-#endif /* __PANEL_PICODLP_H */
diff --git a/include/video/omap-panel-tfp410.h b/include/video/omap-panel-tfp410.h
deleted file mode 100644
index aef35e48bc7..00000000000
--- a/include/video/omap-panel-tfp410.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Header for TFP410 chip driver
- *
- * Copyright (C) 2011 Texas Instruments Inc
- * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __OMAP_PANEL_TFP410_H
-#define __OMAP_PANEL_TFP410_H
-
-struct omap_dss_device;
-
-/**
- * struct tfp410_platform_data - panel driver configuration data
- * @i2c_bus_num: i2c bus id for the panel
- * @power_down_gpio: gpio number for PD pin (or -1 if not available)
- */
-struct tfp410_platform_data {
- int i2c_bus_num;
- int power_down_gpio;
-};
-
-#endif /* __OMAP_PANEL_TFP410_H */
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index caefa093337..fc06c5b5f12 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -23,6 +23,8 @@
#include <linux/device.h>
#include <linux/interrupt.h>
+#include <video/videomode.h>
+
#define DISPC_IRQ_FRAMEDONE (1 << 0)
#define DISPC_IRQ_VSYNC (1 << 1)
#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
@@ -68,6 +70,7 @@ enum omap_display_type {
OMAP_DISPLAY_TYPE_DSI = 1 << 3,
OMAP_DISPLAY_TYPE_VENC = 1 << 4,
OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
+ OMAP_DISPLAY_TYPE_DVI = 1 << 6,
};
enum omap_plane {
@@ -169,6 +172,11 @@ enum omap_dss_audio_state {
OMAP_DSS_AUDIO_PLAYING,
};
+struct omap_dss_audio {
+ struct snd_aes_iec958 *iec;
+ struct snd_cea_861_aud_if *cea;
+};
+
enum omap_dss_rotation_type {
OMAP_DSS_ROT_DMA = 1 << 0,
OMAP_DSS_ROT_VRFB = 1 << 1,
@@ -242,25 +250,33 @@ struct rfbi_timings {
int converted;
};
-void omap_rfbi_write_command(const void *buf, u32 len);
-void omap_rfbi_read_data(void *buf, u32 len);
-void omap_rfbi_write_data(const void *buf, u32 len);
-void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
- u16 x, u16 y,
- u16 w, u16 h);
-int omap_rfbi_enable_te(bool enable, unsigned line);
-int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
- unsigned hs_pulse_time, unsigned vs_pulse_time,
- int hs_pol_inv, int vs_pol_inv, int extif_div);
-void rfbi_bus_lock(void);
-void rfbi_bus_unlock(void);
-
/* DSI */
+enum omap_dss_dsi_trans_mode {
+ /* Sync Pulses: both sync start and end packets sent */
+ OMAP_DSS_DSI_PULSE_MODE,
+ /* Sync Events: only sync start packets sent */
+ OMAP_DSS_DSI_EVENT_MODE,
+ /* Burst: only sync start packets sent, pixels are time compressed */
+ OMAP_DSS_DSI_BURST_MODE,
+};
+
struct omap_dss_dsi_videomode_timings {
+ unsigned long hsclk;
+
+ unsigned ndl;
+ unsigned bitspp;
+
+ /* pixels */
+ u16 hact;
+ /* lines */
+ u16 vact;
+
/* DSI video mode blanking data */
/* Unit: byte clock cycles */
+ u16 hss;
u16 hsa;
+ u16 hse;
u16 hfp;
u16 hbp;
/* Unit: line clocks */
@@ -274,46 +290,23 @@ struct omap_dss_dsi_videomode_timings {
int hbp_blanking_mode;
int hfp_blanking_mode;
- /* Video port sync events */
- bool vp_vsync_end;
- bool vp_hsync_end;
+ enum omap_dss_dsi_trans_mode trans_mode;
bool ddr_clk_always_on;
int window_sync;
};
-void dsi_bus_lock(struct omap_dss_device *dssdev);
-void dsi_bus_unlock(struct omap_dss_device *dssdev);
-int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
- int len);
-int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
- int len);
-int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
-int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
-int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
- u8 param);
-int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
- u8 param);
-int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
- u8 param1, u8 param2);
-int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
- u8 *data, int len);
-int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
- u8 *data, int len);
-int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
- u8 *buf, int buflen);
-int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
- int buflen);
-int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
- u8 *buf, int buflen);
-int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
- u8 param1, u8 param2, u8 *buf, int buflen);
-int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
- u16 len);
-int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
-int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
-int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
-void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
+struct omap_dss_dsi_config {
+ enum omap_dss_dsi_mode mode;
+ enum omap_dss_dsi_pixel_format pixel_format;
+ const struct omap_video_timings *timings;
+
+ unsigned long hs_clk_min, hs_clk_max;
+ unsigned long lp_clk_min, lp_clk_max;
+
+ bool ddr_clk_always_on;
+ enum omap_dss_dsi_trans_mode trans_mode;
+};
enum omapdss_version {
OMAPDSS_VER_UNKNOWN = 0,
@@ -326,14 +319,15 @@ enum omapdss_version {
OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
OMAPDSS_VER_OMAP4, /* All other OMAP4s */
OMAPDSS_VER_OMAP5,
+ OMAPDSS_VER_AM43xx,
};
/* Board specific data */
struct omap_dss_board_info {
- int (*get_context_loss_count)(struct device *dev);
int num_devices;
struct omap_dss_device **devices;
struct omap_dss_device *default_device;
+ const char *default_display_name;
int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
int (*set_min_bus_tput)(struct device *dev, unsigned long r);
@@ -350,8 +344,8 @@ struct omap_video_timings {
u16 x_res;
/* Unit: pixels */
u16 y_res;
- /* Unit: KHz */
- u32 pixel_clock;
+ /* Unit: Hz */
+ u32 pixelclock;
/* Unit: pixel clocks */
u16 hsw; /* Horizontal synchronization pulse width */
/* Unit: pixel clocks */
@@ -395,8 +389,8 @@ struct omap_dss_cpr_coefs {
};
struct omap_overlay_info {
- u32 paddr;
- u32 p_uv_addr; /* for NV12 format */
+ dma_addr_t paddr;
+ dma_addr_t p_uv_addr; /* for NV12 format */
u16 screen_width;
u16 width;
u16 height;
@@ -481,7 +475,7 @@ struct omap_overlay_manager {
enum omap_dss_output_id supported_outputs;
/* dynamic fields */
- struct omap_dss_output *output;
+ struct omap_dss_device *output;
/*
* The following functions do not block:
@@ -495,7 +489,7 @@ struct omap_overlay_manager {
*/
int (*set_output)(struct omap_overlay_manager *mgr,
- struct omap_dss_output *output);
+ struct omap_dss_device *output);
int (*unset_output)(struct omap_overlay_manager *mgr);
int (*set_manager_info)(struct omap_overlay_manager *mgr,
@@ -538,30 +532,188 @@ struct omap_dss_writeback_info {
u8 pre_mult_alpha;
};
-struct omap_dss_output {
- struct list_head list;
+struct omapdss_dpi_ops {
+ int (*connect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+ void (*disconnect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
- /* display type supported by the output */
- enum omap_display_type type;
+ int (*enable)(struct omap_dss_device *dssdev);
+ void (*disable)(struct omap_dss_device *dssdev);
- /* output instance */
- enum omap_dss_output_id id;
+ int (*check_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*set_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*get_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
- /* output's platform device pointer */
- struct platform_device *pdev;
+ void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
+};
- /* dynamic fields */
- struct omap_overlay_manager *manager;
+struct omapdss_sdi_ops {
+ int (*connect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+ void (*disconnect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+
+ int (*enable)(struct omap_dss_device *dssdev);
+ void (*disable)(struct omap_dss_device *dssdev);
+
+ int (*check_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*set_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*get_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
- struct omap_dss_device *device;
+ void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
+};
+
+struct omapdss_dvi_ops {
+ int (*connect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+ void (*disconnect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+
+ int (*enable)(struct omap_dss_device *dssdev);
+ void (*disable)(struct omap_dss_device *dssdev);
+
+ int (*check_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*set_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*get_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+};
+
+struct omapdss_atv_ops {
+ int (*connect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+ void (*disconnect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+
+ int (*enable)(struct omap_dss_device *dssdev);
+ void (*disable)(struct omap_dss_device *dssdev);
+
+ int (*check_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*set_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*get_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+
+ void (*set_type)(struct omap_dss_device *dssdev,
+ enum omap_dss_venc_type type);
+ void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
+ bool invert_polarity);
+
+ int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
+ u32 (*get_wss)(struct omap_dss_device *dssdev);
+};
+
+struct omapdss_hdmi_ops {
+ int (*connect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+ void (*disconnect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+
+ int (*enable)(struct omap_dss_device *dssdev);
+ void (*disable)(struct omap_dss_device *dssdev);
+
+ int (*check_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*set_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*get_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+
+ int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
+ bool (*detect)(struct omap_dss_device *dssdev);
+
+ /*
+ * Note: These functions might sleep. Do not call while
+ * holding a spinlock/readlock.
+ */
+ int (*audio_enable)(struct omap_dss_device *dssdev);
+ void (*audio_disable)(struct omap_dss_device *dssdev);
+ bool (*audio_supported)(struct omap_dss_device *dssdev);
+ int (*audio_config)(struct omap_dss_device *dssdev,
+ struct omap_dss_audio *audio);
+ /* Note: These functions may not sleep */
+ int (*audio_start)(struct omap_dss_device *dssdev);
+ void (*audio_stop)(struct omap_dss_device *dssdev);
+};
+
+struct omapdss_dsi_ops {
+ int (*connect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+ void (*disconnect)(struct omap_dss_device *dssdev,
+ struct omap_dss_device *dst);
+
+ int (*enable)(struct omap_dss_device *dssdev);
+ void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
+ bool enter_ulps);
+
+ /* bus configuration */
+ int (*set_config)(struct omap_dss_device *dssdev,
+ const struct omap_dss_dsi_config *cfg);
+ int (*configure_pins)(struct omap_dss_device *dssdev,
+ const struct omap_dsi_pin_config *pin_cfg);
+
+ void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
+ bool enable);
+ int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
+
+ int (*update)(struct omap_dss_device *dssdev, int channel,
+ void (*callback)(int, void *), void *data);
+
+ void (*bus_lock)(struct omap_dss_device *dssdev);
+ void (*bus_unlock)(struct omap_dss_device *dssdev);
+
+ int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
+ void (*disable_video_output)(struct omap_dss_device *dssdev,
+ int channel);
+
+ int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
+ int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
+ int vc_id);
+ void (*release_vc)(struct omap_dss_device *dssdev, int channel);
+
+ /* data transfer */
+ int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
+ u8 *data, int len);
+ int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
+ u8 *data, int len);
+ int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
+ u8 *data, int len);
+
+ int (*gen_write)(struct omap_dss_device *dssdev, int channel,
+ u8 *data, int len);
+ int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
+ u8 *data, int len);
+ int (*gen_read)(struct omap_dss_device *dssdev, int channel,
+ u8 *reqdata, int reqlen,
+ u8 *data, int len);
+
+ int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
+
+ int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
+ int channel, u16 plen);
};
struct omap_dss_device {
- struct device dev;
+ struct device *dev;
- enum omap_display_type type;
+ struct module *owner;
+
+ struct list_head panel_list;
- enum omap_channel channel;
+ /* alias in the form of "display%d" */
+ char alias[16];
+
+ enum omap_display_type type;
+ enum omap_display_type output_type;
union {
struct {
@@ -579,9 +731,6 @@ struct omap_dss_device {
struct {
int module;
-
- bool ext_te;
- u8 ext_te_gpio;
} dsi;
struct {
@@ -591,40 +740,10 @@ struct omap_dss_device {
} phy;
struct {
- struct {
- struct {
- u16 lck_div;
- u16 pck_div;
- enum omap_dss_clk_source lcd_clk_src;
- } channel;
-
- enum omap_dss_clk_source dispc_fclk_src;
- } dispc;
-
- struct {
- /* regn is one greater than TRM's REGN value */
- u16 regn;
- u16 regm;
- u16 regm_dispc;
- u16 regm_dsi;
-
- u16 lp_clk_div;
- enum omap_dss_clk_source dsi_fclk_src;
- } dsi;
-
- struct {
- /* regn is one greater than TRM's REGN value */
- u16 regn;
- u16 regm2;
- } hdmi;
- } clocks;
-
- struct {
struct omap_video_timings timings;
enum omap_dss_dsi_pixel_format dsi_pix_fmt;
enum omap_dss_dsi_mode dsi_mode;
- struct omap_dss_dsi_videomode_timings dsi_vm_timings;
} panel;
struct {
@@ -632,10 +751,6 @@ struct omap_dss_device {
struct rfbi_timings rfbi_timings;
} ctrl;
- int reset_gpio;
-
- int max_backlight_level;
-
const char *name;
/* used to match device to driver */
@@ -645,22 +760,40 @@ struct omap_dss_device {
struct omap_dss_driver *driver;
+ union {
+ const struct omapdss_dpi_ops *dpi;
+ const struct omapdss_sdi_ops *sdi;
+ const struct omapdss_dvi_ops *dvi;
+ const struct omapdss_hdmi_ops *hdmi;
+ const struct omapdss_atv_ops *atv;
+ const struct omapdss_dsi_ops *dsi;
+ } ops;
+
/* helper variable for driver suspend/resume */
bool activate_after_resume;
enum omap_display_caps caps;
- struct omap_dss_output *output;
+ struct omap_dss_device *src;
enum omap_dss_display_state state;
enum omap_dss_audio_state audio_state;
- /* platform specific */
- int (*platform_enable)(struct omap_dss_device *dssdev);
- void (*platform_disable)(struct omap_dss_device *dssdev);
- int (*set_backlight)(struct omap_dss_device *dssdev, int level);
- int (*get_backlight)(struct omap_dss_device *dssdev);
+ /* OMAP DSS output specific fields */
+
+ struct list_head list;
+
+ /* DISPC channel for this output */
+ enum omap_channel dispc_channel;
+
+ /* output instance */
+ enum omap_dss_output_id id;
+
+ /* dynamic fields */
+ struct omap_overlay_manager *manager;
+
+ struct omap_dss_device *dst;
};
struct omap_dss_hdmi_data
@@ -670,17 +803,13 @@ struct omap_dss_hdmi_data
int hpd_gpio;
};
-struct omap_dss_audio {
- struct snd_aes_iec958 *iec;
- struct snd_cea_861_aud_if *cea;
-};
-
struct omap_dss_driver {
- struct device_driver driver;
-
int (*probe)(struct omap_dss_device *);
void (*remove)(struct omap_dss_device *);
+ int (*connect)(struct omap_dss_device *dssdev);
+ void (*disconnect)(struct omap_dss_device *dssdev);
+
int (*enable)(struct omap_dss_device *display);
void (*disable)(struct omap_dss_device *display);
int (*run_test)(struct omap_dss_device *display, int test);
@@ -741,11 +870,15 @@ struct omap_dss_driver {
};
enum omapdss_version omapdss_get_version(void);
+bool omapdss_is_initialized(void);
int omap_dss_register_driver(struct omap_dss_driver *);
void omap_dss_unregister_driver(struct omap_dss_driver *);
-void omap_dss_get_device(struct omap_dss_device *dssdev);
+int omapdss_register_display(struct omap_dss_device *dssdev);
+void omapdss_unregister_display(struct omap_dss_device *dssdev);
+
+struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
void omap_dss_put_device(struct omap_dss_device *dssdev);
#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
@@ -753,8 +886,10 @@ struct omap_dss_device *omap_dss_find_device(void *data,
int (*match)(struct omap_dss_device *dssdev, void *data));
const char *omapdss_get_default_display_name(void);
-int omap_dss_start_device(struct omap_dss_device *dssdev);
-void omap_dss_stop_device(struct omap_dss_device *dssdev);
+void videomode_to_omap_video_timings(const struct videomode *vm,
+ struct omap_video_timings *ovt);
+void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
+ struct videomode *vm);
int dss_feat_get_num_mgrs(void);
int dss_feat_get_num_ovls(void);
@@ -770,10 +905,17 @@ struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
int omap_dss_get_num_overlays(void);
struct omap_overlay *omap_dss_get_overlay(int num);
-struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
-int omapdss_output_set_device(struct omap_dss_output *out,
+int omapdss_register_output(struct omap_dss_device *output);
+void omapdss_unregister_output(struct omap_dss_device *output);
+struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
+struct omap_dss_device *omap_dss_find_output(const char *name);
+struct omap_dss_device *omap_dss_find_output_by_node(struct device_node *node);
+int omapdss_output_set_device(struct omap_dss_device *out,
struct omap_dss_device *dssdev);
-int omapdss_output_unset_device(struct omap_dss_output *out);
+int omapdss_output_unset_device(struct omap_dss_device *out);
+
+struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
+struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
u16 *xres, u16 *yres);
@@ -823,67 +965,15 @@ int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
bool replication, const struct omap_video_timings *mgr_timings,
bool mem_to_mem);
-#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
-#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
-
-void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
- bool enable);
-int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
-void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
- struct omap_video_timings *timings);
-void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
-void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
- enum omap_dss_dsi_pixel_format fmt);
-void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
- enum omap_dss_dsi_mode mode);
-void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
- struct omap_dss_dsi_videomode_timings *timings);
-
-int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
- void (*callback)(int, void *), void *data);
-int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
-int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
-void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
-int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
- const struct omap_dsi_pin_config *pin_cfg);
-int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
- unsigned long ddr_clk, unsigned long lp_clk);
-
-int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
- bool disconnect_lanes, bool enter_ulps);
-
-int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
-void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
- struct omap_video_timings *timings);
-int dpi_check_timings(struct omap_dss_device *dssdev,
- struct omap_video_timings *timings);
-void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
-
-int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
-void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
- struct omap_video_timings *timings);
-void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
-
-int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
-int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
- void *data);
-int omap_rfbi_configure(struct omap_dss_device *dssdev);
-void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
-void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
- int pixel_size);
-void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
- int data_lines);
-void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
- struct rfbi_timings *timings);
-
int omapdss_compat_init(void);
void omapdss_compat_uninit(void);
struct dss_mgr_ops {
+ int (*connect)(struct omap_overlay_manager *mgr,
+ struct omap_dss_device *dst);
+ void (*disconnect)(struct omap_overlay_manager *mgr,
+ struct omap_dss_device *dst);
+
void (*start_update)(struct omap_overlay_manager *mgr);
int (*enable)(struct omap_overlay_manager *mgr);
void (*disable)(struct omap_overlay_manager *mgr);
@@ -900,6 +990,10 @@ struct dss_mgr_ops {
int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
void dss_uninstall_mgr_ops(void);
+int dss_mgr_connect(struct omap_overlay_manager *mgr,
+ struct omap_dss_device *dst);
+void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
+ struct omap_dss_device *dst);
void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
const struct omap_video_timings *timings);
void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
@@ -911,4 +1005,29 @@ int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
void (*handler)(void *), void *data);
void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
void (*handler)(void *), void *data);
+
+static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
+{
+ return dssdev->src;
+}
+
+static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
+{
+ return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
+}
+
+struct device_node *
+omapdss_of_get_next_port(const struct device_node *parent,
+ struct device_node *prev);
+
+struct device_node *
+omapdss_of_get_next_endpoint(const struct device_node *parent,
+ struct device_node *prev);
+
+struct device_node *
+omapdss_of_get_first_endpoint(const struct device_node *parent);
+
+struct omap_dss_device *
+omapdss_of_find_source_for_first_ep(struct device_node *node);
+
#endif
diff --git a/include/video/platform_lcd.h b/include/video/platform_lcd.h
index ad3bdfe743b..23864b28414 100644
--- a/include/video/platform_lcd.h
+++ b/include/video/platform_lcd.h
@@ -15,6 +15,7 @@ struct plat_lcd_data;
struct fb_info;
struct plat_lcd_data {
+ int (*probe)(struct plat_lcd_data *);
void (*set_power)(struct plat_lcd_data *, unsigned int power);
int (*match_fb)(struct plat_lcd_data *, struct fb_info *);
};
diff --git a/include/video/pxa168fb.h b/include/video/pxa168fb.h
index 8c2f385a90e..84cbb1f69ea 100644
--- a/include/video/pxa168fb.h
+++ b/include/video/pxa168fb.h
@@ -1,6 +1,4 @@
/*
- * linux/arch/arm/mach-mmp/include/mach/pxa168fb.h
- *
* Copyright (C) 2009 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
diff --git a/include/video/sgivw.h b/include/video/sgivw.h
deleted file mode 100644
index f6aa5692e74..00000000000
--- a/include/video/sgivw.h
+++ /dev/null
@@ -1,681 +0,0 @@
-/*
- * linux/drivers/video/sgivw.h -- SGI DBE frame buffer device header
- *
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Jeffrey Newquist, newquist@engr.sgi.som
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef __SGIVWFB_H__
-#define __SGIVWFB_H__
-
-#define DBE_GETREG(reg, dest) ((dest) = DBE_REG_BASE->reg)
-#define DBE_SETREG(reg, src) DBE_REG_BASE->reg = (src)
-#define DBE_IGETREG(reg, idx, dest) ((dest) = DBE_REG_BASE->reg[idx])
-#define DBE_ISETREG(reg, idx, src) (DBE_REG_BASE->reg[idx] = (src))
-
-#define MASK(msb, lsb) ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) )
-#define GET(v, msb, lsb) ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
-#define SET(v, f, msb, lsb) ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
-
-#define GET_DBE_FIELD(reg, field, v) GET((v), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB)
-#define SET_DBE_FIELD(reg, field, v, f) SET((v), (f), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB)
-
-/* NOTE: All loads/stores must be 32 bits and uncached */
-
-#define DBE_REG_PHYS 0xd0000000
-#define DBE_REG_SIZE 0x01000000
-
-struct asregs {
- volatile u32 ctrlstat; /* 0x000000 general control */
- volatile u32 dotclock; /* 0x000004 dot clock PLL control */
- volatile u32 i2c; /* 0x000008 crt I2C control */
- volatile u32 sysclk; /* 0x00000c system clock PLL control */
- volatile u32 i2cfp; /* 0x000010 flat panel I2C control */
- volatile u32 id; /* 0x000014 device id/chip revision */
- volatile u32 config; /* 0x000018 power on configuration */
- volatile u32 bist; /* 0x00001c internal bist status */
-
- char _pad0[ 0x010000 - 0x000020 ];
-
- volatile u32 vt_xy; /* 0x010000 current dot coords */
- volatile u32 vt_xymax; /* 0x010004 maximum dot coords */
- volatile u32 vt_vsync; /* 0x010008 vsync on/off */
- volatile u32 vt_hsync; /* 0x01000c hsync on/off */
- volatile u32 vt_vblank; /* 0x010010 vblank on/off */
- volatile u32 vt_hblank; /* 0x010014 hblank on/off */
- volatile u32 vt_flags; /* 0x010018 polarity of vt signals */
- volatile u32 vt_f2rf_lock; /* 0x01001c f2rf & framelck y coord */
- volatile u32 vt_intr01; /* 0x010020 intr 0,1 y coords */
- volatile u32 vt_intr23; /* 0x010024 intr 2,3 y coords */
- volatile u32 fp_hdrv; /* 0x010028 flat panel hdrv on/off */
- volatile u32 fp_vdrv; /* 0x01002c flat panel vdrv on/off */
- volatile u32 fp_de; /* 0x010030 flat panel de on/off */
- volatile u32 vt_hpixen; /* 0x010034 intrnl horiz pixel on/off*/
- volatile u32 vt_vpixen; /* 0x010038 intrnl vert pixel on/off */
- volatile u32 vt_hcmap; /* 0x01003c cmap write (horiz) */
- volatile u32 vt_vcmap; /* 0x010040 cmap write (vert) */
- volatile u32 did_start_xy; /* 0x010044 eol/f did/xy reset val */
- volatile u32 crs_start_xy; /* 0x010048 eol/f crs/xy reset val */
- volatile u32 vc_start_xy; /* 0x01004c eol/f vc/xy reset val */
-
- char _pad1[ 0x020000 - 0x010050 ];
-
- volatile u32 ovr_width_tile; /* 0x020000 overlay plane ctrl 0 */
- volatile u32 ovr_inhwctrl; /* 0x020004 overlay plane ctrl 1 */
- volatile u32 ovr_control; /* 0x020008 overlay plane ctrl 1 */
-
- char _pad2[ 0x030000 - 0x02000C ];
-
- volatile u32 frm_size_tile; /* 0x030000 normal plane ctrl 0 */
- volatile u32 frm_size_pixel; /* 0x030004 normal plane ctrl 1 */
- volatile u32 frm_inhwctrl; /* 0x030008 normal plane ctrl 2 */
- volatile u32 frm_control; /* 0x03000C normal plane ctrl 3 */
-
- char _pad3[ 0x040000 - 0x030010 ];
-
- volatile u32 did_inhwctrl; /* 0x040000 DID control */
- volatile u32 did_control; /* 0x040004 DID shadow */
-
- char _pad4[ 0x048000 - 0x040008 ];
-
- volatile u32 mode_regs[32]; /* 0x048000 - 0x04807c WID table */
-
- char _pad5[ 0x050000 - 0x048080 ];
-
- volatile u32 cmap[6144]; /* 0x050000 - 0x055ffc color map */
-
- char _pad6[ 0x058000 - 0x056000 ];
-
- volatile u32 cm_fifo; /* 0x058000 color map fifo status */
-
- char _pad7[ 0x060000 - 0x058004 ];
-
- volatile u32 gmap[256]; /* 0x060000 - 0x0603fc gamma map */
-
- char _pad8[ 0x068000 - 0x060400 ];
-
- volatile u32 gmap10[1024]; /* 0x068000 - 0x068ffc gamma map */
-
- char _pad9[ 0x070000 - 0x069000 ];
-
- volatile u32 crs_pos; /* 0x070000 cusror control 0 */
- volatile u32 crs_ctl; /* 0x070004 cusror control 1 */
- volatile u32 crs_cmap[3]; /* 0x070008 - 0x070010 crs cmap */
-
- char _pad10[ 0x078000 - 0x070014 ];
-
- volatile u32 crs_glyph[64]; /* 0x078000 - 0x0780fc crs glyph */
-
- char _pad11[ 0x080000 - 0x078100 ];
-
- volatile u32 vc_0; /* 0x080000 video capture crtl 0 */
- volatile u32 vc_1; /* 0x080004 video capture crtl 1 */
- volatile u32 vc_2; /* 0x080008 video capture crtl 2 */
- volatile u32 vc_3; /* 0x08000c video capture crtl 3 */
- volatile u32 vc_4; /* 0x080010 video capture crtl 3 */
- volatile u32 vc_5; /* 0x080014 video capture crtl 3 */
- volatile u32 vc_6; /* 0x080018 video capture crtl 3 */
- volatile u32 vc_7; /* 0x08001c video capture crtl 3 */
- volatile u32 vc_8; /* 0x08000c video capture crtl 3 */
-};
-
-/* Bit mask information */
-
-#define DBE_CTRLSTAT_CHIPID_MSB 3
-#define DBE_CTRLSTAT_CHIPID_LSB 0
-#define DBE_CTRLSTAT_SENSE_N_MSB 4
-#define DBE_CTRLSTAT_SENSE_N_LSB 4
-#define DBE_CTRLSTAT_PCLKSEL_MSB 29
-#define DBE_CTRLSTAT_PCLKSEL_LSB 28
-
-#define DBE_DOTCLK_M_MSB 7
-#define DBE_DOTCLK_M_LSB 0
-#define DBE_DOTCLK_N_MSB 13
-#define DBE_DOTCLK_N_LSB 8
-#define DBE_DOTCLK_P_MSB 15
-#define DBE_DOTCLK_P_LSB 14
-#define DBE_DOTCLK_RUN_MSB 20
-#define DBE_DOTCLK_RUN_LSB 20
-
-#define DBE_VT_XY_VT_FREEZE_MSB 31
-#define DBE_VT_XY_VT_FREEZE_LSB 31
-
-#define DBE_FP_VDRV_FP_VDRV_ON_MSB 23
-#define DBE_FP_VDRV_FP_VDRV_ON_LSB 12
-#define DBE_FP_VDRV_FP_VDRV_OFF_MSB 11
-#define DBE_FP_VDRV_FP_VDRV_OFF_LSB 0
-
-#define DBE_FP_HDRV_FP_HDRV_ON_MSB 23
-#define DBE_FP_HDRV_FP_HDRV_ON_LSB 12
-#define DBE_FP_HDRV_FP_HDRV_OFF_MSB 11
-#define DBE_FP_HDRV_FP_HDRV_OFF_LSB 0
-
-#define DBE_FP_DE_FP_DE_ON_MSB 23
-#define DBE_FP_DE_FP_DE_ON_LSB 12
-#define DBE_FP_DE_FP_DE_OFF_MSB 11
-#define DBE_FP_DE_FP_DE_OFF_LSB 0
-
-#define DBE_VT_VSYNC_VT_VSYNC_ON_MSB 23
-#define DBE_VT_VSYNC_VT_VSYNC_ON_LSB 12
-#define DBE_VT_VSYNC_VT_VSYNC_OFF_MSB 11
-#define DBE_VT_VSYNC_VT_VSYNC_OFF_LSB 0
-
-#define DBE_VT_HSYNC_VT_HSYNC_ON_MSB 23
-#define DBE_VT_HSYNC_VT_HSYNC_ON_LSB 12
-#define DBE_VT_HSYNC_VT_HSYNC_OFF_MSB 11
-#define DBE_VT_HSYNC_VT_HSYNC_OFF_LSB 0
-
-#define DBE_VT_VBLANK_VT_VBLANK_ON_MSB 23
-#define DBE_VT_VBLANK_VT_VBLANK_ON_LSB 12
-#define DBE_VT_VBLANK_VT_VBLANK_OFF_MSB 11
-#define DBE_VT_VBLANK_VT_VBLANK_OFF_LSB 0
-
-#define DBE_VT_HBLANK_VT_HBLANK_ON_MSB 23
-#define DBE_VT_HBLANK_VT_HBLANK_ON_LSB 12
-#define DBE_VT_HBLANK_VT_HBLANK_OFF_MSB 11
-#define DBE_VT_HBLANK_VT_HBLANK_OFF_LSB 0
-
-#define DBE_VT_FLAGS_VDRV_INVERT_MSB 0
-#define DBE_VT_FLAGS_VDRV_INVERT_LSB 0
-#define DBE_VT_FLAGS_HDRV_INVERT_MSB 2
-#define DBE_VT_FLAGS_HDRV_INVERT_LSB 2
-
-#define DBE_VT_VCMAP_VT_VCMAP_ON_MSB 23
-#define DBE_VT_VCMAP_VT_VCMAP_ON_LSB 12
-#define DBE_VT_VCMAP_VT_VCMAP_OFF_MSB 11
-#define DBE_VT_VCMAP_VT_VCMAP_OFF_LSB 0
-
-#define DBE_VT_HCMAP_VT_HCMAP_ON_MSB 23
-#define DBE_VT_HCMAP_VT_HCMAP_ON_LSB 12
-#define DBE_VT_HCMAP_VT_HCMAP_OFF_MSB 11
-#define DBE_VT_HCMAP_VT_HCMAP_OFF_LSB 0
-
-#define DBE_VT_XYMAX_VT_MAXX_MSB 11
-#define DBE_VT_XYMAX_VT_MAXX_LSB 0
-#define DBE_VT_XYMAX_VT_MAXY_MSB 23
-#define DBE_VT_XYMAX_VT_MAXY_LSB 12
-
-#define DBE_VT_HPIXEN_VT_HPIXEN_ON_MSB 23
-#define DBE_VT_HPIXEN_VT_HPIXEN_ON_LSB 12
-#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_MSB 11
-#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_LSB 0
-
-#define DBE_VT_VPIXEN_VT_VPIXEN_ON_MSB 23
-#define DBE_VT_VPIXEN_VT_VPIXEN_ON_LSB 12
-#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_MSB 11
-#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_LSB 0
-
-#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0
-#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0
-
-#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0
-#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0
-
-#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13
-#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13
-
-#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0
-#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0
-#define DBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31
-#define DBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9
-#define DBE_FRM_CONTROL_FRM_LINEAR_MSB 1
-#define DBE_FRM_CONTROL_FRM_LINEAR_LSB 1
-
-#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0
-#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0
-
-#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12
-#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5
-#define DBE_FRM_SIZE_TILE_FRM_RHS_MSB 4
-#define DBE_FRM_SIZE_TILE_FRM_RHS_LSB 0
-#define DBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14
-#define DBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13
-#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15
-#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15
-
-#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31
-#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16
-
-#define DBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0
-#define DBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0
-#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0
-#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0
-
-#define DBE_DID_START_XY_DID_STARTY_MSB 23
-#define DBE_DID_START_XY_DID_STARTY_LSB 12
-#define DBE_DID_START_XY_DID_STARTX_MSB 11
-#define DBE_DID_START_XY_DID_STARTX_LSB 0
-
-#define DBE_CRS_START_XY_CRS_STARTY_MSB 23
-#define DBE_CRS_START_XY_CRS_STARTY_LSB 12
-#define DBE_CRS_START_XY_CRS_STARTX_MSB 11
-#define DBE_CRS_START_XY_CRS_STARTX_LSB 0
-
-#define DBE_WID_TYP_MSB 4
-#define DBE_WID_TYP_LSB 2
-#define DBE_WID_BUF_MSB 1
-#define DBE_WID_BUF_LSB 0
-
-#define DBE_VC_START_XY_VC_STARTY_MSB 23
-#define DBE_VC_START_XY_VC_STARTY_LSB 12
-#define DBE_VC_START_XY_VC_STARTX_MSB 11
-#define DBE_VC_START_XY_VC_STARTX_LSB 0
-
-/* Constants */
-
-#define DBE_FRM_DEPTH_8 0
-#define DBE_FRM_DEPTH_16 1
-#define DBE_FRM_DEPTH_32 2
-
-#define DBE_CMODE_I8 0
-#define DBE_CMODE_I12 1
-#define DBE_CMODE_RG3B2 2
-#define DBE_CMODE_RGB4 3
-#define DBE_CMODE_ARGB5 4
-#define DBE_CMODE_RGB8 5
-#define DBE_CMODE_RGBA5 6
-#define DBE_CMODE_RGB10 7
-
-#define DBE_BMODE_BOTH 3
-
-#define DBE_CRS_MAGIC 54
-
-#define DBE_CLOCK_REF_KHZ 27000
-
-/* Config Register (DBE Only) Definitions */
-
-#define DBE_CONFIG_VDAC_ENABLE 0x00000001
-#define DBE_CONFIG_VDAC_GSYNC 0x00000002
-#define DBE_CONFIG_VDAC_PBLANK 0x00000004
-#define DBE_CONFIG_FPENABLE 0x00000008
-#define DBE_CONFIG_LENDIAN 0x00000020
-#define DBE_CONFIG_TILEHIST 0x00000040
-#define DBE_CONFIG_EXT_ADDR 0x00000080
-
-#define DBE_CONFIG_FBDEV ( DBE_CONFIG_VDAC_ENABLE | \
- DBE_CONFIG_VDAC_GSYNC | \
- DBE_CONFIG_VDAC_PBLANK | \
- DBE_CONFIG_LENDIAN | \
- DBE_CONFIG_EXT_ADDR )
-
-/*
- * Available Video Timings and Corresponding Indices
- */
-
-typedef enum {
- DBE_VT_640_480_60,
-
- DBE_VT_800_600_60,
- DBE_VT_800_600_75,
- DBE_VT_800_600_120,
-
- DBE_VT_1024_768_50,
- DBE_VT_1024_768_60,
- DBE_VT_1024_768_75,
- DBE_VT_1024_768_85,
- DBE_VT_1024_768_120,
-
- DBE_VT_1280_1024_50,
- DBE_VT_1280_1024_60,
- DBE_VT_1280_1024_75,
- DBE_VT_1280_1024_85,
-
- DBE_VT_1600_1024_53,
- DBE_VT_1600_1024_60,
-
- DBE_VT_1600_1200_50,
- DBE_VT_1600_1200_60,
- DBE_VT_1600_1200_75,
-
- DBE_VT_1920_1080_50,
- DBE_VT_1920_1080_60,
- DBE_VT_1920_1080_72,
-
- DBE_VT_1920_1200_50,
- DBE_VT_1920_1200_60,
- DBE_VT_1920_1200_66,
-
- DBE_VT_UNKNOWN
-} dbe_timing_t;
-
-
-
-/*
- * Crime Video Timing Data Structure
- */
-
-struct dbe_timing_info
-{
- dbe_timing_t type;
- int flags;
- short width; /* Monitor resolution */
- short height;
- int fields_sec; /* fields/sec (Hz -3 dec. places */
- int cfreq; /* pixel clock frequency (MHz -3 dec. places) */
- short htotal; /* Horizontal total pixels */
- short hblank_start; /* Horizontal blank start */
- short hblank_end; /* Horizontal blank end */
- short hsync_start; /* Horizontal sync start */
- short hsync_end; /* Horizontal sync end */
- short vtotal; /* Vertical total lines */
- short vblank_start; /* Vertical blank start */
- short vblank_end; /* Vertical blank end */
- short vsync_start; /* Vertical sync start */
- short vsync_end; /* Vertical sync end */
- short pll_m; /* PLL M parameter */
- short pll_n; /* PLL P parameter */
- short pll_p; /* PLL N parameter */
-};
-
-/* Defines for dbe_vof_info_t flags */
-
-#define DBE_VOF_UNKNOWNMON 1
-#define DBE_VOF_STEREO 2
-#define DBE_VOF_DO_GENSYNC 4 /* enable incoming sync */
-#define DBE_VOF_SYNC_ON_GREEN 8 /* sync on green */
-#define DBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */
-#define DBE_VOF_MAGICKEY 0x2000 /* Backdoor key */
-
-/*
- * DBE Timing Tables
- */
-
-#ifdef INCLUDE_TIMING_TABLE_DATA
-struct dbe_timing_info dbeVTimings[] = {
- {
- DBE_VT_640_480_60,
- /* flags, width, height, fields_sec, cfreq */
- 0, 640, 480, 59940, 25175,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 800, 640, 800, 656, 752,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 525, 480, 525, 490, 492,
- /* pll_m, pll_n, pll_p */
- 15, 2, 3
- },
-
- {
- DBE_VT_800_600_60,
- /* flags, width, height, fields_sec, cfreq */
- 0, 800, 600, 60317, 40000,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1056, 800, 1056, 840, 968,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 628, 600, 628, 601, 605,
- /* pll_m, pll_n, pll_p */
- 3, 1, 1
- },
-
- {
- DBE_VT_800_600_75,
- /* flags, width, height, fields_sec, cfreq */
- 0, 800, 600, 75000, 49500,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1056, 800, 1056, 816, 896,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 625, 600, 625, 601, 604,
- /* pll_m, pll_n, pll_p */
- 11, 3, 1
- },
-
- {
- DBE_VT_800_600_120,
- /* flags, width, height, fields_sec, cfreq */
- DBE_VOF_STEREO, 800, 600, 119800, 82978,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1040, 800, 1040, 856, 976,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 666, 600, 666, 637, 643,
- /* pll_m, pll_n, pll_p */
- 31, 5, 1
- },
-
- {
- DBE_VT_1024_768_50,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1024, 768, 50000, 54163,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1344, 1024, 1344, 1048, 1184,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 806, 768, 806, 771, 777,
- /* pll_m, pll_n, pll_p */
- 4, 1, 1
- },
-
- {
- DBE_VT_1024_768_60,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1024, 768, 60004, 65000,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1344, 1024, 1344, 1048, 1184,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 806, 768, 806, 771, 777,
- /* pll_m, pll_n, pll_p */
- 12, 5, 0
- },
-
- {
- DBE_VT_1024_768_75,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1024, 768, 75029, 78750,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1312, 1024, 1312, 1040, 1136,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 800, 768, 800, 769, 772,
- /* pll_m, pll_n, pll_p */
- 29, 5, 1
- },
-
- {
- DBE_VT_1024_768_85,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1024, 768, 84997, 94500,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1376, 1024, 1376, 1072, 1168,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 808, 768, 808, 769, 772,
- /* pll_m, pll_n, pll_p */
- 7, 2, 0
- },
-
- {
- DBE_VT_1024_768_120,
- /* flags, width, height, fields_sec, cfreq */
- DBE_VOF_STEREO, 1024, 768, 119800, 133195,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1376, 1024, 1376, 1072, 1168,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 808, 768, 808, 769, 772,
- /* pll_m, pll_n, pll_p */
- 5, 1, 0
- },
-
- {
- DBE_VT_1280_1024_50,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1280, 1024, 50000, 89460,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1680, 1280, 1680, 1360, 1480,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1065, 1024, 1065, 1027, 1030,
- /* pll_m, pll_n, pll_p */
- 10, 3, 0
- },
-
- {
- DBE_VT_1280_1024_60,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1280, 1024, 60020, 108000,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1688, 1280, 1688, 1328, 1440,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1066, 1024, 1066, 1025, 1028,
- /* pll_m, pll_n, pll_p */
- 4, 1, 0
- },
-
- {
- DBE_VT_1280_1024_75,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1280, 1024, 75025, 135000,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1688, 1280, 1688, 1296, 1440,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1066, 1024, 1066, 1025, 1028,
- /* pll_m, pll_n, pll_p */
- 5, 1, 0
- },
-
- {
- DBE_VT_1280_1024_85,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1280, 1024, 85024, 157500,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1728, 1280, 1728, 1344, 1504,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1072, 1024, 1072, 1025, 1028,
- /* pll_m, pll_n, pll_p */
- 29, 5, 0
- },
-
- {
- DBE_VT_1600_1024_53,
- /* flags, width, height, fields_sec, cfreq */
- DBE_VOF_FLATPANEL | DBE_VOF_MAGICKEY,
- 1600, 1024, 53000, 107447,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1900, 1600, 1900, 1630, 1730,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1067, 1024, 1067, 1027, 1030,
- /* pll_m, pll_n, pll_p */
- 4, 1, 0
- },
-
- {
- DBE_VT_1600_1024_60,
- /* flags, width, height, fields_sec, cfreq */
- DBE_VOF_FLATPANEL, 1600, 1024, 60000, 106913,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 1670, 1600, 1670, 1630, 1650,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1067, 1024, 1067, 1027, 1030,
- /* pll_m, pll_n, pll_p */
- 4, 1, 0
- },
-
- {
- DBE_VT_1600_1200_50,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1600, 1200, 50000, 130500,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 2088, 1600, 2088, 1644, 1764,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1250, 1200, 1250, 1205, 1211,
- /* pll_m, pll_n, pll_p */
- 24, 5, 0
- },
-
- {
- DBE_VT_1600_1200_60,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1600, 1200, 59940, 162000,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 2160, 1600, 2160, 1644, 1856,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1250, 1200, 1250, 1201, 1204,
- /* pll_m, pll_n, pll_p */
- 6, 1, 0
- },
-
- {
- DBE_VT_1600_1200_75,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1600, 1200, 75000, 202500,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 2160, 1600, 2160, 1644, 1856,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1250, 1200, 1250, 1201, 1204,
- /* pll_m, pll_n, pll_p */
- 15, 2, 0
- },
-
- {
- DBE_VT_1920_1080_50,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1920, 1080, 50000, 133200,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 2368, 1920, 2368, 1952, 2096,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1125, 1080, 1125, 1083, 1086,
- /* pll_m, pll_n, pll_p */
- 5, 1, 0
- },
-
- {
- DBE_VT_1920_1080_60,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1920, 1080, 59940, 159840,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 2368, 1920, 2368, 1952, 2096,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1125, 1080, 1125, 1083, 1086,
- /* pll_m, pll_n, pll_p */
- 6, 1, 0
- },
-
- {
- DBE_VT_1920_1080_72,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1920, 1080, 72000, 216023,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 2560, 1920, 2560, 1968, 2184,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1172, 1080, 1172, 1083, 1086,
- /* pll_m, pll_n, pll_p */
- 8, 1, 0
- },
-
- {
- DBE_VT_1920_1200_50,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1920, 1200, 50000, 161500,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 2584, 1920, 2584, 1984, 2240,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1250, 1200, 1250, 1203, 1206,
- /* pll_m, pll_n, pll_p */
- 6, 1, 0
- },
-
- {
- DBE_VT_1920_1200_60,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1920, 1200, 59940, 193800,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 2584, 1920, 2584, 1984, 2240,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1250, 1200, 1250, 1203, 1206,
- /* pll_m, pll_n, pll_p */
- 29, 4, 0
- },
-
- {
- DBE_VT_1920_1200_66,
- /* flags, width, height, fields_sec, cfreq */
- 0, 1920, 1200, 66000, 213180,
- /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
- 2584, 1920, 2584, 1984, 2240,
- /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
- 1250, 1200, 1250, 1203, 1206,
- /* pll_m, pll_n, pll_p */
- 8, 1, 0
- }
-};
-
-#endif // INCLUDE_TIMING_TABLE_DATA
-
-#endif // ! __SGIVWFB_H__
diff --git a/include/video/uvesafb.h b/include/video/uvesafb.h
index 1a91850cb96..30f53625415 100644
--- a/include/video/uvesafb.h
+++ b/include/video/uvesafb.h
@@ -134,6 +134,7 @@ struct uvesafb_par {
int mode_idx;
struct vbe_crtc_ib crtc;
+ int mtrr_handle;
};
#endif /* _UVESAFB_H */
diff --git a/include/video/videomode.h b/include/video/videomode.h
index a42156234dd..3f1049d870d 100644
--- a/include/video/videomode.h
+++ b/include/video/videomode.h
@@ -29,20 +29,30 @@ struct videomode {
u32 vback_porch;
u32 vsync_len;
- unsigned int dmt_flags; /* VESA DMT flags */
- unsigned int data_flags; /* video data flags */
+ enum display_flags flags; /* display flags */
};
/**
* videomode_from_timing - convert display timing to videomode
+ * @dt: display_timing structure
+ * @vm: return value
+ *
+ * DESCRIPTION:
+ * This function converts a struct display_timing to a struct videomode.
+ */
+void videomode_from_timing(const struct display_timing *dt,
+ struct videomode *vm);
+
+/**
+ * videomode_from_timings - convert one display timings entry to videomode
* @disp: structure with all possible timing entries
* @vm: return value
* @index: index into the list of display timings in devicetree
*
* DESCRIPTION:
- * This function converts a struct display_timing to a struct videomode.
+ * This function converts one struct display_timing entry to a struct videomode.
*/
-int videomode_from_timing(const struct display_timings *disp,
+int videomode_from_timings(const struct display_timings *disp,
struct videomode *vm, unsigned int index);
#endif
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-11-10 06:27:15 +0000