diff options
Diffstat (limited to 'include/asm-mips/ip32')
| -rw-r--r-- | include/asm-mips/ip32/crime.h | 161 | ||||
| -rw-r--r-- | include/asm-mips/ip32/ip32_ints.h | 94 | ||||
| -rw-r--r-- | include/asm-mips/ip32/mace.h | 368 | ||||
| -rw-r--r-- | include/asm-mips/ip32/machine.h | 20 |
4 files changed, 0 insertions, 643 deletions
diff --git a/include/asm-mips/ip32/crime.h b/include/asm-mips/ip32/crime.h deleted file mode 100644 index a13702fafa8..00000000000 --- a/include/asm-mips/ip32/crime.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory - * Engine) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - */ - -#ifndef __ASM_CRIME_H__ -#define __ASM_CRIME_H__ - -/* - * Address map - */ -#define CRIME_BASE 0x14000000 /* physical */ - -#undef BIT -#define BIT(x) (1UL << (x)) - -struct sgi_crime { - volatile unsigned long id; -#define CRIME_ID_MASK 0xff -#define CRIME_ID_IDBITS 0xf0 -#define CRIME_ID_IDVALUE 0xa0 -#define CRIME_ID_REV 0x0f -#define CRIME_REV_PETTY 0x00 -#define CRIME_REV_11 0x11 -#define CRIME_REV_13 0x13 -#define CRIME_REV_14 0x14 - - volatile unsigned long control; -#define CRIME_CONTROL_MASK 0x3fff -#define CRIME_CONTROL_TRITON_SYSADC 0x2000 -#define CRIME_CONTROL_CRIME_SYSADC 0x1000 -#define CRIME_CONTROL_HARD_RESET 0x0800 -#define CRIME_CONTROL_SOFT_RESET 0x0400 -#define CRIME_CONTROL_DOG_ENA 0x0200 -#define CRIME_CONTROL_ENDIANESS 0x0100 -#define CRIME_CONTROL_ENDIAN_BIG 0x0100 -#define CRIME_CONTROL_ENDIAN_LITTLE 0x0000 -#define CRIME_CONTROL_CQUEUE_HWM 0x000f -#define CRIME_CONTROL_CQUEUE_SHFT 0 -#define CRIME_CONTROL_WBUF_HWM 0x00f0 -#define CRIME_CONTROL_WBUF_SHFT 8 - - volatile unsigned long istat; - volatile unsigned long imask; - volatile unsigned long soft_int; - volatile unsigned long hard_int; -#define MACE_VID_IN1_INT BIT(0) -#define MACE_VID_IN2_INT BIT(1) -#define MACE_VID_OUT_INT BIT(2) -#define MACE_ETHERNET_INT BIT(3) -#define MACE_SUPERIO_INT BIT(4) -#define MACE_MISC_INT BIT(5) -#define MACE_AUDIO_INT BIT(6) -#define MACE_PCI_BRIDGE_INT BIT(7) -#define MACEPCI_SCSI0_INT BIT(8) -#define MACEPCI_SCSI1_INT BIT(9) -#define MACEPCI_SLOT0_INT BIT(10) -#define MACEPCI_SLOT1_INT BIT(11) -#define MACEPCI_SLOT2_INT BIT(12) -#define MACEPCI_SHARED0_INT BIT(13) -#define MACEPCI_SHARED1_INT BIT(14) -#define MACEPCI_SHARED2_INT BIT(15) -#define CRIME_GBE0_INT BIT(16) -#define CRIME_GBE1_INT BIT(17) -#define CRIME_GBE2_INT BIT(18) -#define CRIME_GBE3_INT BIT(19) -#define CRIME_CPUERR_INT BIT(20) -#define CRIME_MEMERR_INT BIT(21) -#define CRIME_RE_EMPTY_E_INT BIT(22) -#define CRIME_RE_FULL_E_INT BIT(23) -#define CRIME_RE_IDLE_E_INT BIT(24) -#define CRIME_RE_EMPTY_L_INT BIT(25) -#define CRIME_RE_FULL_L_INT BIT(26) -#define CRIME_RE_IDLE_L_INT BIT(27) -#define CRIME_SOFT0_INT BIT(28) -#define CRIME_SOFT1_INT BIT(29) -#define CRIME_SOFT2_INT BIT(30) -#define CRIME_SYSCORERR_INT CRIME_SOFT2_INT -#define CRIME_VICE_INT BIT(31) -/* Masks for deciding who handles the interrupt */ -#define CRIME_MACE_INT_MASK 0x8f -#define CRIME_MACEISA_INT_MASK 0x70 -#define CRIME_MACEPCI_INT_MASK 0xff00 -#define CRIME_CRIME_INT_MASK 0xffff0000 - - volatile unsigned long watchdog; -#define CRIME_DOG_POWER_ON_RESET 0x00010000 -#define CRIME_DOG_WARM_RESET 0x00080000 -#define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET) -#define CRIME_DOG_VALUE 0x00007fff - - volatile unsigned long timer; -#define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */ -#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */ - - volatile unsigned long cpu_error_addr; -#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff - - volatile unsigned long cpu_error_stat; -#define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */ -#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4 -#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2 -#define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1 - - unsigned long _pad0[54]; - - volatile unsigned long mc_ctrl; - volatile unsigned long bank_ctrl[8]; -#define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */ -#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f -#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100 -#define CRIME_MAXBANKS 8 - - volatile unsigned long mem_ref_counter; -#define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */ - - volatile unsigned long mem_error_stat; -#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */ -#define CRIME_MEM_ERROR_MACE_ID 0x0000007f -#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080 -#define CRIME_MEM_ERROR_RE_ID 0x00007f00 -#define CRIME_MEM_ERROR_RE_ACCESS 0x00008000 -#define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000 -#define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000 -#define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000 -#define CRIME_MEM_ERROR_RESERVED 0x00080000 -#define CRIME_MEM_ERROR_SOFT_ERR 0x00100000 -#define CRIME_MEM_ERROR_HARD_ERR 0x00200000 -#define CRIME_MEM_ERROR_MULTIPLE 0x00400000 -#define CRIME_MEM_ERROR_ECC 0x01800000 -#define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000 -#define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000 -#define CRIME_MEM_ERROR_INV 0x0e000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000 - - volatile unsigned long mem_error_addr; -#define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff - - volatile unsigned long mem_ecc_syn; -#define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff - - volatile unsigned long mem_ecc_chk; -#define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff - - volatile unsigned long mem_ecc_repl; -#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff -}; - -extern struct sgi_crime __iomem *crime; - -#define CRIME_HI_MEM_BASE 0x40000000 /* this is where whole 1G of RAM is mapped */ - -#endif /* __ASM_CRIME_H__ */ diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h deleted file mode 100644 index c3c280e3d59..00000000000 --- a/include/asm-mips/ip32/ip32_ints.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - */ - -#ifndef __ASM_IP32_INTS_H -#define __ASM_IP32_INTS_H - -/* - * This list reflects the assignment of interrupt numbers to - * interrupting events. Order is fairly irrelevant to handling - * priority. This differs from irix. - */ - -/* CPU */ -#define IP32_R4K_TIMER_IRQ 0 - -/* MACE */ -#define MACE_VID_IN1_IRQ 1 -#define MACE_VID_IN2_IRQ 2 -#define MACE_VID_OUT_IRQ 3 -#define MACE_ETHERNET_IRQ 4 -/* SUPERIO, MISC, and AUDIO are MACEISA */ -#define MACE_PCI_BRIDGE_IRQ 8 - -/* MACEPCI */ -#define MACEPCI_SCSI0_IRQ 9 -#define MACEPCI_SCSI1_IRQ 10 -#define MACEPCI_SLOT0_IRQ 11 -#define MACEPCI_SLOT1_IRQ 12 -#define MACEPCI_SLOT2_IRQ 13 -#define MACEPCI_SHARED0_IRQ 14 -#define MACEPCI_SHARED1_IRQ 15 -#define MACEPCI_SHARED2_IRQ 16 - -/* CRIME */ -#define CRIME_GBE0_IRQ 17 -#define CRIME_GBE1_IRQ 18 -#define CRIME_GBE2_IRQ 19 -#define CRIME_GBE3_IRQ 20 -#define CRIME_CPUERR_IRQ 21 -#define CRIME_MEMERR_IRQ 22 -#define CRIME_RE_EMPTY_E_IRQ 23 -#define CRIME_RE_FULL_E_IRQ 24 -#define CRIME_RE_IDLE_E_IRQ 25 -#define CRIME_RE_EMPTY_L_IRQ 26 -#define CRIME_RE_FULL_L_IRQ 27 -#define CRIME_RE_IDLE_L_IRQ 28 -#define CRIME_SOFT0_IRQ 29 -#define CRIME_SOFT1_IRQ 30 -#define CRIME_SOFT2_IRQ 31 -#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ -#define CRIME_VICE_IRQ 32 - -/* MACEISA */ -#define MACEISA_AUDIO_SW_IRQ 33 -#define MACEISA_AUDIO_SC_IRQ 34 -#define MACEISA_AUDIO1_DMAT_IRQ 35 -#define MACEISA_AUDIO1_OF_IRQ 36 -#define MACEISA_AUDIO2_DMAT_IRQ 37 -#define MACEISA_AUDIO2_MERR_IRQ 38 -#define MACEISA_AUDIO3_DMAT_IRQ 39 -#define MACEISA_AUDIO3_MERR_IRQ 40 -#define MACEISA_RTC_IRQ 41 -#define MACEISA_KEYB_IRQ 42 -/* MACEISA_KEYB_POLL is not an IRQ */ -#define MACEISA_MOUSE_IRQ 44 -/* MACEISA_MOUSE_POLL is not an IRQ */ -#define MACEISA_TIMER0_IRQ 46 -#define MACEISA_TIMER1_IRQ 47 -#define MACEISA_TIMER2_IRQ 48 -#define MACEISA_PARALLEL_IRQ 49 -#define MACEISA_PAR_CTXA_IRQ 50 -#define MACEISA_PAR_CTXB_IRQ 51 -#define MACEISA_PAR_MERR_IRQ 52 -#define MACEISA_SERIAL1_IRQ 53 -#define MACEISA_SERIAL1_TDMAT_IRQ 54 -#define MACEISA_SERIAL1_TDMAPR_IRQ 55 -#define MACEISA_SERIAL1_TDMAME_IRQ 56 -#define MACEISA_SERIAL1_RDMAT_IRQ 57 -#define MACEISA_SERIAL1_RDMAOR_IRQ 58 -#define MACEISA_SERIAL2_IRQ 59 -#define MACEISA_SERIAL2_TDMAT_IRQ 60 -#define MACEISA_SERIAL2_TDMAPR_IRQ 61 -#define MACEISA_SERIAL2_TDMAME_IRQ 62 -#define MACEISA_SERIAL2_RDMAT_IRQ 63 -#define MACEISA_SERIAL2_RDMAOR_IRQ 64 - -#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ - -#endif /* __ASM_IP32_INTS_H */ diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h deleted file mode 100644 index 990082c81f3..00000000000 --- a/include/asm-mips/ip32/mace.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - * Copyright (C) 2004 Ladislav Michl - */ - -#ifndef __ASM_MACE_H__ -#define __ASM_MACE_H__ - -/* - * Address map - */ -#define MACE_BASE 0x1f000000 /* physical */ - -#undef BIT -#define BIT(x) (1UL << (x)) - -/* - * PCI interface - */ -struct mace_pci { - volatile unsigned int error_addr; - volatile unsigned int error; -#define MACEPCI_ERROR_MASTER_ABORT BIT(31) -#define MACEPCI_ERROR_TARGET_ABORT BIT(30) -#define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29) -#define MACEPCI_ERROR_RETRY_ERR BIT(28) -#define MACEPCI_ERROR_ILLEGAL_CMD BIT(27) -#define MACEPCI_ERROR_SYSTEM_ERR BIT(26) -#define MACEPCI_ERROR_INTERRUPT_TEST BIT(25) -#define MACEPCI_ERROR_PARITY_ERR BIT(24) -#define MACEPCI_ERROR_OVERRUN BIT(23) -#define MACEPCI_ERROR_RSVD BIT(22) -#define MACEPCI_ERROR_MEMORY_ADDR BIT(21) -#define MACEPCI_ERROR_CONFIG_ADDR BIT(20) -#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19) -#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18) -#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17) -#define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16) -#define MACEPCI_ERROR_SIG_TABORT BIT(4) -#define MACEPCI_ERROR_DEVSEL_MASK 0xc0 -#define MACEPCI_ERROR_DEVSEL_FAST 0 -#define MACEPCI_ERROR_DEVSEL_MED 0x40 -#define MACEPCI_ERROR_DEVSEL_SLOW 0x80 -#define MACEPCI_ERROR_FBB BIT(1) -#define MACEPCI_ERROR_66MHZ BIT(0) - volatile unsigned int control; -#define MACEPCI_CONTROL_INT(x) BIT(x) -#define MACEPCI_CONTROL_INT_MASK 0xff -#define MACEPCI_CONTROL_SERR_ENA BIT(8) -#define MACEPCI_CONTROL_ARB_N6 BIT(9) -#define MACEPCI_CONTROL_PARITY_ERR BIT(10) -#define MACEPCI_CONTROL_MRMRA_ENA BIT(11) -#define MACEPCI_CONTROL_ARB_N3 BIT(12) -#define MACEPCI_CONTROL_ARB_N4 BIT(13) -#define MACEPCI_CONTROL_ARB_N5 BIT(14) -#define MACEPCI_CONTROL_PARK_LIU BIT(15) -#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x) -#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000 -#define MACEPCI_CONTROL_OVERRUN_INT BIT(24) -#define MACEPCI_CONTROL_PARITY_INT BIT(25) -#define MACEPCI_CONTROL_SERR_INT BIT(26) -#define MACEPCI_CONTROL_IT_INT BIT(27) -#define MACEPCI_CONTROL_RE_INT BIT(28) -#define MACEPCI_CONTROL_DPED_INT BIT(29) -#define MACEPCI_CONTROL_TAR_INT BIT(30) -#define MACEPCI_CONTROL_MAR_INT BIT(31) - volatile unsigned int rev; - unsigned int _pad[0xcf8/4 - 4]; - volatile unsigned int config_addr; - union { - volatile unsigned char b[4]; - volatile unsigned short w[2]; - volatile unsigned int l; - } config_data; -}; -#define MACEPCI_LOW_MEMORY 0x1a000000 -#define MACEPCI_LOW_IO 0x18000000 -#define MACEPCI_SWAPPED_VIEW 0 -#define MACEPCI_NATIVE_VIEW 0x40000000 -#define MACEPCI_IO 0x80000000 -#define MACEPCI_HI_MEMORY 0x280000000 -#define MACEPCI_HI_IO 0x100000000 - -/* - * Video interface - */ -struct mace_video { - unsigned long xxx; /* later... */ -}; - -/* - * Ethernet interface - */ -struct mace_ethernet { - volatile unsigned long mac_ctrl; - volatile unsigned long int_stat; - volatile unsigned long dma_ctrl; - volatile unsigned long timer; - volatile unsigned long tx_int_al; - volatile unsigned long rx_int_al; - volatile unsigned long tx_info; - volatile unsigned long tx_info_al; - volatile unsigned long rx_buff; - volatile unsigned long rx_buff_al1; - volatile unsigned long rx_buff_al2; - volatile unsigned long diag; - volatile unsigned long phy_data; - volatile unsigned long phy_regs; - volatile unsigned long phy_trans_go; - volatile unsigned long backoff_seed; - /*===================================*/ - volatile unsigned long imq_reserved[4]; - volatile unsigned long mac_addr; - volatile unsigned long mac_addr2; - volatile unsigned long mcast_filter; - volatile unsigned long tx_ring_base; - /* Following are read-only registers for debugging */ - volatile unsigned long tx_pkt1_hdr; - volatile unsigned long tx_pkt1_ptr[3]; - volatile unsigned long tx_pkt2_hdr; - volatile unsigned long tx_pkt2_ptr[3]; - /*===================================*/ - volatile unsigned long rx_fifo; -}; - -/* - * Peripherals - */ - -/* Audio registers */ -struct mace_audio { - volatile unsigned long control; - volatile unsigned long codec_control; /* codec status control */ - volatile unsigned long codec_mask; /* codec status input mask */ - volatile unsigned long codec_read; /* codec status read data */ - struct { - volatile unsigned long control; /* channel control */ - volatile unsigned long read_ptr; /* channel read pointer */ - volatile unsigned long write_ptr; /* channel write pointer */ - volatile unsigned long depth; /* channel depth */ - } chan[3]; -}; - - -/* register definitions for parallel port DMA */ -struct mace_parport { - /* 0 - do nothing, - * 1 - pulse terminal count to the device after buffer is drained */ -#define MACEPAR_CONTEXT_LASTFLAG BIT(63) - /* Should not cross 4K page boundary */ -#define MACEPAR_CONTEXT_DATA_BOUND 0x0000000000001000UL -#define MACEPAR_CONTEXT_DATALEN_MASK 0x00000fff00000000UL -#define MACEPAR_CONTEXT_DATALEN_SHIFT 32 - /* Can be arbitrarily aligned on any byte boundary on output, - * 64 byte aligned on input */ -#define MACEPAR_CONTEXT_BASEADDR_MASK 0x00000000ffffffffUL - volatile u64 context_a; - volatile u64 context_b; - /* 0 - mem->device, 1 - device->mem */ -#define MACEPAR_CTLSTAT_DIRECTION BIT(0) - /* 0 - channel frozen, 1 - channel enabled */ -#define MACEPAR_CTLSTAT_ENABLE BIT(1) - /* 0 - channel active, 1 - complete channel reset */ -#define MACEPAR_CTLSTAT_RESET BIT(2) -#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3) -#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4) - volatile u64 cntlstat; /* Control/Status register */ -#define MACEPAR_DIAG_CTXINUSE BIT(0) - /* 1 - Dma engine is enabled and processing something */ -#define MACEPAR_DIAG_DMACTIVE BIT(1) - /* Counter of bytes left */ -#define MACEPAR_DIAG_CTRMASK 0x0000000000003ffcUL -#define MACEPAR_DIAG_CTRSHIFT 2 - volatile u64 diagnostic; /* RO: diagnostic register */ -}; - -/* ISA Control and DMA registers */ -struct mace_isactrl { - volatile unsigned long ringbase; -#define MACEISA_RINGBUFFERS_SIZE (8 * 4096) - - volatile unsigned long misc; -#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */ -#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */ -#define MACEISA_NIC_DEASSERT BIT(2) -#define MACEISA_NIC_DATA BIT(3) -#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */ -#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */ -#define MACEISA_DP_RAM_ENABLE BIT(6) - - volatile unsigned long istat; - volatile unsigned long imask; -#define MACEISA_AUDIO_SW_INT BIT(0) -#define MACEISA_AUDIO_SC_INT BIT(1) -#define MACEISA_AUDIO1_DMAT_INT BIT(2) -#define MACEISA_AUDIO1_OF_INT BIT(3) -#define MACEISA_AUDIO2_DMAT_INT BIT(4) -#define MACEISA_AUDIO2_MERR_INT BIT(5) -#define MACEISA_AUDIO3_DMAT_INT BIT(6) -#define MACEISA_AUDIO3_MERR_INT BIT(7) -#define MACEISA_RTC_INT BIT(8) -#define MACEISA_KEYB_INT BIT(9) -#define MACEISA_KEYB_POLL_INT BIT(10) -#define MACEISA_MOUSE_INT BIT(11) -#define MACEISA_MOUSE_POLL_INT BIT(12) -#define MACEISA_TIMER0_INT BIT(13) -#define MACEISA_TIMER1_INT BIT(14) -#define MACEISA_TIMER2_INT BIT(15) -#define MACEISA_PARALLEL_INT BIT(16) -#define MACEISA_PAR_CTXA_INT BIT(17) -#define MACEISA_PAR_CTXB_INT BIT(18) -#define MACEISA_PAR_MERR_INT BIT(19) -#define MACEISA_SERIAL1_INT BIT(20) -#define MACEISA_SERIAL1_TDMAT_INT BIT(21) -#define MACEISA_SERIAL1_TDMAPR_INT BIT(22) -#define MACEISA_SERIAL1_TDMAME_INT BIT(23) -#define MACEISA_SERIAL1_RDMAT_INT BIT(24) -#define MACEISA_SERIAL1_RDMAOR_INT BIT(25) -#define MACEISA_SERIAL2_INT BIT(26) -#define MACEISA_SERIAL2_TDMAT_INT BIT(27) -#define MACEISA_SERIAL2_TDMAPR_INT BIT(28) -#define MACEISA_SERIAL2_TDMAME_INT BIT(29) -#define MACEISA_SERIAL2_RDMAT_INT BIT(30) -#define MACEISA_SERIAL2_RDMAOR_INT BIT(31) - - volatile unsigned long _pad[0x2000/8 - 4]; - - volatile unsigned long dp_ram[0x400]; - struct mace_parport parport; -}; - -/* Keyboard & Mouse registers - * -> drivers/input/serio/maceps2.c */ -struct mace_ps2port { - volatile unsigned long tx; - volatile unsigned long rx; - volatile unsigned long control; - volatile unsigned long status; -}; - -struct mace_ps2 { - struct mace_ps2port keyb; - struct mace_ps2port mouse; -}; - -/* I2C registers - * -> drivers/i2c/algos/i2c-algo-sgi.c */ -struct mace_i2c { - volatile unsigned long config; -#define MACEI2C_RESET BIT(0) -#define MACEI2C_FAST BIT(1) -#define MACEI2C_DATA_OVERRIDE BIT(2) -#define MACEI2C_CLOCK_OVERRIDE BIT(3) -#define MACEI2C_DATA_STATUS BIT(4) -#define MACEI2C_CLOCK_STATUS BIT(5) - volatile unsigned long control; - volatile unsigned long data; -}; - -/* Timer registers */ -typedef union { - volatile unsigned long ust_msc; - struct reg { - volatile unsigned int ust; - volatile unsigned int msc; - } reg; -} timer_reg; - -struct mace_timers { - volatile unsigned long ust; -#define MACE_UST_PERIOD_NS 960 - - volatile unsigned long compare1; - volatile unsigned long compare2; - volatile unsigned long compare3; - - timer_reg audio_in; - timer_reg audio_out1; - timer_reg audio_out2; - timer_reg video_in1; - timer_reg video_in2; - timer_reg video_out; -}; - -struct mace_perif { - struct mace_audio audio; - char _pad0[0x10000 - sizeof(struct mace_audio)]; - - struct mace_isactrl ctrl; - char _pad1[0x10000 - sizeof(struct mace_isactrl)]; - - struct mace_ps2 ps2; - char _pad2[0x10000 - sizeof(struct mace_ps2)]; - - struct mace_i2c i2c; - char _pad3[0x10000 - sizeof(struct mace_i2c)]; - - struct mace_timers timers; - char _pad4[0x10000 - sizeof(struct mace_timers)]; -}; - - -/* - * ISA peripherals - */ - -/* Parallel port */ -struct mace_parallel { -}; - -struct mace_ecp1284 { /* later... */ -}; - -/* Serial port */ -struct mace_serial { - volatile unsigned long xxx; /* later... */ -}; - -struct mace_isa { - struct mace_parallel parallel; - char _pad1[0x8000 - sizeof(struct mace_parallel)]; - - struct mace_ecp1284 ecp1284; - char _pad2[0x8000 - sizeof(struct mace_ecp1284)]; - - struct mace_serial serial1; - char _pad3[0x8000 - sizeof(struct mace_serial)]; - - struct mace_serial serial2; - char _pad4[0x8000 - sizeof(struct mace_serial)]; - - volatile unsigned char rtc[0x10000]; -}; - -struct sgi_mace { - char _reserved[0x80000]; - - struct mace_pci pci; - char _pad0[0x80000 - sizeof(struct mace_pci)]; - - struct mace_video video_in1; - char _pad1[0x80000 - sizeof(struct mace_video)]; - - struct mace_video video_in2; - char _pad2[0x80000 - sizeof(struct mace_video)]; - - struct mace_video video_out; - char _pad3[0x80000 - sizeof(struct mace_video)]; - - struct mace_ethernet eth; - char _pad4[0x80000 - sizeof(struct mace_ethernet)]; - - struct mace_perif perif; - char _pad5[0x80000 - sizeof(struct mace_perif)]; - - struct mace_isa isa; - char _pad6[0x80000 - sizeof(struct mace_isa)]; -}; - -extern struct sgi_mace __iomem *mace; - -#endif /* __ASM_MACE_H__ */ diff --git a/include/asm-mips/ip32/machine.h b/include/asm-mips/ip32/machine.h deleted file mode 100644 index 1b631b8da6f..00000000000 --- a/include/asm-mips/ip32/machine.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * machine.h -- Machine/group probing for ip32 - * - * Copyright (C) 2001 Keith M Wesolowski - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ -#ifndef _ASM_IP32_MACHINE_H -#define _ASM_IP32_MACHINE_H - - -#ifdef CONFIG_SGI_IP32 - -#define SGI_MACH_O2 0x3201 - -#endif /* CONFIG_SGI_IP32 */ - -#endif /* _ASM_SGI_MACHINE_H */ |