diff options
Diffstat (limited to 'drivers/video/riva')
| -rw-r--r-- | drivers/video/riva/Makefile | 11 | ||||
| -rw-r--r-- | drivers/video/riva/fbdev.c | 2307 | ||||
| -rw-r--r-- | drivers/video/riva/nv4ref.h | 2445 | ||||
| -rw-r--r-- | drivers/video/riva/nv_driver.c | 425 | ||||
| -rw-r--r-- | drivers/video/riva/nv_type.h | 58 | ||||
| -rw-r--r-- | drivers/video/riva/nvreg.h | 188 | ||||
| -rw-r--r-- | drivers/video/riva/riva_hw.c | 2259 | ||||
| -rw-r--r-- | drivers/video/riva/riva_hw.h | 548 | ||||
| -rw-r--r-- | drivers/video/riva/riva_tbl.h | 1008 | ||||
| -rw-r--r-- | drivers/video/riva/rivafb-i2c.c | 212 | ||||
| -rw-r--r-- | drivers/video/riva/rivafb.h | 78 |
11 files changed, 0 insertions, 9539 deletions
diff --git a/drivers/video/riva/Makefile b/drivers/video/riva/Makefile deleted file mode 100644 index 8898c9915b0..00000000000 --- a/drivers/video/riva/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for the Riva framebuffer driver -# - -obj-$(CONFIG_FB_RIVA) += rivafb.o - -rivafb-objs := fbdev.o riva_hw.o nv_driver.o - -ifdef CONFIG_FB_RIVA_I2C - rivafb-objs += rivafb-i2c.o -endif diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c deleted file mode 100644 index 4acde4f7dbf..00000000000 --- a/drivers/video/riva/fbdev.c +++ /dev/null @@ -1,2307 +0,0 @@ -/* - * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver - * - * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> - * - * Copyright 1999-2000 Jeff Garzik - * - * Contributors: - * - * Ani Joshi: Lots of debugging and cleanup work, really helped - * get the driver going - * - * Ferenc Bakonyi: Bug fixes, cleanup, modularization - * - * Jindrich Makovicka: Accel code help, hw cursor, mtrr - * - * Paul Richards: Bug fixes, updates - * - * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven - * Includes riva_hw.c from nVidia, see copyright below. - * KGI code provided the basis for state storage, init, and mode switching. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * Known bugs and issues: - * restoring text mode fails - * doublescan modes are broken - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/slab.h> -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/backlight.h> -#ifdef CONFIG_MTRR -#include <asm/mtrr.h> -#endif -#ifdef CONFIG_PPC_OF -#include <asm/prom.h> -#include <asm/pci-bridge.h> -#endif -#ifdef CONFIG_PMAC_BACKLIGHT -#include <asm/machdep.h> -#include <asm/backlight.h> -#endif - -#include "rivafb.h" -#include "nvreg.h" - -#ifndef CONFIG_PCI /* sanity check */ -#error This driver requires PCI support. -#endif - -/* version number of this driver */ -#define RIVAFB_VERSION "0.9.5b" - -/* ------------------------------------------------------------------------- * - * - * various helpful macros and constants - * - * ------------------------------------------------------------------------- */ -#ifdef CONFIG_FB_RIVA_DEBUG -#define NVTRACE printk -#else -#define NVTRACE if(0) printk -#endif - -#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__) -#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__) - -#ifdef CONFIG_FB_RIVA_DEBUG -#define assert(expr) \ - if(!(expr)) { \ - printk( "Assertion failed! %s,%s,%s,line=%d\n",\ - #expr,__FILE__,__FUNCTION__,__LINE__); \ - BUG(); \ - } -#else -#define assert(expr) -#endif - -#define PFX "rivafb: " - -/* macro that allows you to set overflow bits */ -#define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) -#define SetBit(n) (1<<(n)) -#define Set8Bits(value) ((value)&0xff) - -/* HW cursor parameters */ -#define MAX_CURS 32 - -/* ------------------------------------------------------------------------- * - * - * prototypes - * - * ------------------------------------------------------------------------- */ - -static int rivafb_blank(int blank, struct fb_info *info); - -/* ------------------------------------------------------------------------- * - * - * card identification - * - * ------------------------------------------------------------------------- */ - -static struct pci_device_id rivafb_pci_tbl[] = { - { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - // NF2/IGP version, GeForce 4 MX, NV18 - { PCI_VENDOR_ID_NVIDIA, 0x01f0, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { 0, } /* terminate list */ -}; -MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); - -/* ------------------------------------------------------------------------- * - * - * global variables - * - * ------------------------------------------------------------------------- */ - -/* command line data, set in rivafb_setup() */ -static int flatpanel __devinitdata = -1; /* Autodetect later */ -static int forceCRTC __devinitdata = -1; -static int noaccel __devinitdata = 0; -#ifdef CONFIG_MTRR -static int nomtrr __devinitdata = 0; -#endif - -static char *mode_option __devinitdata = NULL; -static int strictmode = 0; - -static struct fb_fix_screeninfo __devinitdata rivafb_fix = { - .type = FB_TYPE_PACKED_PIXELS, - .xpanstep = 1, - .ypanstep = 1, -}; - -static struct fb_var_screeninfo __devinitdata rivafb_default_var = { - .xres = 640, - .yres = 480, - .xres_virtual = 640, - .yres_virtual = 480, - .bits_per_pixel = 8, - .red = {0, 8, 0}, - .green = {0, 8, 0}, - .blue = {0, 8, 0}, - .transp = {0, 0, 0}, - .activate = FB_ACTIVATE_NOW, - .height = -1, - .width = -1, - .pixclock = 39721, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .vmode = FB_VMODE_NONINTERLACED -}; - -/* from GGI */ -static const struct riva_regs reg_template = { - {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, - 0x41, 0x01, 0x0F, 0x00, 0x00}, - {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ - 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, /* 0x40 */ - }, - {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ - 0xFF}, - {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ - 0xEB /* MISC */ -}; - -/* - * Backlight control - */ -#ifdef CONFIG_FB_RIVA_BACKLIGHT -/* We do not have any information about which values are allowed, thus - * we used safe values. - */ -#define MIN_LEVEL 0x158 -#define MAX_LEVEL 0x534 -#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) - -static struct backlight_properties riva_bl_data; - -/* Call with fb_info->bl_mutex held */ -static int riva_bl_get_level_brightness(struct riva_par *par, - int level) -{ - struct fb_info *info = pci_get_drvdata(par->pdev); - int nlevel; - - /* Get and convert the value */ - nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; - - if (nlevel < 0) - nlevel = 0; - else if (nlevel < MIN_LEVEL) - nlevel = MIN_LEVEL; - else if (nlevel > MAX_LEVEL) - nlevel = MAX_LEVEL; - - return nlevel; -} - -/* Call with fb_info->bl_mutex held */ -static int __riva_bl_update_status(struct backlight_device *bd) -{ - struct riva_par *par = class_get_devdata(&bd->class_dev); - U032 tmp_pcrt, tmp_pmc; - int level; - - if (bd->props->power != FB_BLANK_UNBLANK || - bd->props->fb_blank != FB_BLANK_UNBLANK) - level = 0; - else - level = bd->props->brightness; - - tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF; - tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC; - if(level > 0) { - tmp_pcrt |= 0x1; - tmp_pmc |= (1 << 31); /* backlight bit */ - tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ - } - par->riva.PCRTC0[0x081C/4] = tmp_pcrt; - par->riva.PMC[0x10F0/4] = tmp_pmc; - - return 0; -} - -static int riva_bl_update_status(struct backlight_device *bd) -{ - struct riva_par *par = class_get_devdata(&bd->class_dev); - struct fb_info *info = pci_get_drvdata(par->pdev); - int ret; - - mutex_lock(&info->bl_mutex); - ret = __riva_bl_update_status(bd); - mutex_unlock(&info->bl_mutex); - - return ret; -} - -static int riva_bl_get_brightness(struct backlight_device *bd) -{ - return bd->props->brightness; -} - -static struct backlight_properties riva_bl_data = { - .owner = THIS_MODULE, - .get_brightness = riva_bl_get_brightness, - .update_status = riva_bl_update_status, - .max_brightness = (FB_BACKLIGHT_LEVELS - 1), -}; - -static void riva_bl_set_power(struct fb_info *info, int power) -{ - mutex_lock(&info->bl_mutex); - - if (info->bl_dev) { - down(&info->bl_dev->sem); - info->bl_dev->props->power = power; - __riva_bl_update_status(info->bl_dev); - up(&info->bl_dev->sem); - } - - mutex_unlock(&info->bl_mutex); -} - -static void riva_bl_init(struct riva_par *par) -{ - struct fb_info *info = pci_get_drvdata(par->pdev); - struct backlight_device *bd; - char name[12]; - - if (!par->FlatPanel) - return; - -#ifdef CONFIG_PMAC_BACKLIGHT - if (!machine_is(powermac) || - !pmac_has_backlight_type("mnca")) - return; -#endif - - snprintf(name, sizeof(name), "rivabl%d", info->node); - - bd = backlight_device_register(name, par, &riva_bl_data); - if (IS_ERR(bd)) { - info->bl_dev = NULL; - printk(KERN_WARNING "riva: Backlight registration failed\n"); - goto error; - } - - mutex_lock(&info->bl_mutex); - info->bl_dev = bd; - fb_bl_default_curve(info, 0, - 0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL, - 0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL); - mutex_unlock(&info->bl_mutex); - - down(&bd->sem); - bd->props->brightness = riva_bl_data.max_brightness; - bd->props->power = FB_BLANK_UNBLANK; - bd->props->update_status(bd); - up(&bd->sem); - -#ifdef CONFIG_PMAC_BACKLIGHT - mutex_lock(&pmac_backlight_mutex); - if (!pmac_backlight) - pmac_backlight = bd; - mutex_unlock(&pmac_backlight_mutex); -#endif - - printk("riva: Backlight initialized (%s)\n", name); - - return; - -error: - return; -} - -static void riva_bl_exit(struct riva_par *par) -{ - struct fb_info *info = pci_get_drvdata(par->pdev); - -#ifdef CONFIG_PMAC_BACKLIGHT - mutex_lock(&pmac_backlight_mutex); -#endif - - mutex_lock(&info->bl_mutex); - if (info->bl_dev) { -#ifdef CONFIG_PMAC_BACKLIGHT - if (pmac_backlight == info->bl_dev) - pmac_backlight = NULL; -#endif - - backlight_device_unregister(info->bl_dev); - - printk("riva: Backlight unloaded\n"); - } - mutex_unlock(&info->bl_mutex); - -#ifdef CONFIG_PMAC_BACKLIGHT - mutex_unlock(&pmac_backlight_mutex); -#endif -} -#else -static inline void riva_bl_init(struct riva_par *par) {} -static inline void riva_bl_exit(struct riva_par *par) {} -static inline void riva_bl_set_power(struct fb_info *info, int power) {} -#endif /* CONFIG_FB_RIVA_BACKLIGHT */ - -/* ------------------------------------------------------------------------- * - * - * MMIO access macros - * - * ------------------------------------------------------------------------- */ - -static inline void CRTCout(struct riva_par *par, unsigned char index, - unsigned char val) -{ - VGA_WR08(par->riva.PCIO, 0x3d4, index); - VGA_WR08(par->riva.PCIO, 0x3d5, val); -} - -static inline unsigned char CRTCin(struct riva_par *par, - unsigned char index) -{ - VGA_WR08(par->riva.PCIO, 0x3d4, index); - return (VGA_RD08(par->riva.PCIO, 0x3d5)); -} - -static inline void GRAout(struct riva_par *par, unsigned char index, - unsigned char val) -{ - VGA_WR08(par->riva.PVIO, 0x3ce, index); - VGA_WR08(par->riva.PVIO, 0x3cf, val); -} - -static inline unsigned char GRAin(struct riva_par *par, - unsigned char index) -{ - VGA_WR08(par->riva.PVIO, 0x3ce, index); - return (VGA_RD08(par->riva.PVIO, 0x3cf)); -} - -static inline void SEQout(struct riva_par *par, unsigned char index, - unsigned char val) -{ - VGA_WR08(par->riva.PVIO, 0x3c4, index); - VGA_WR08(par->riva.PVIO, 0x3c5, val); -} - -static inline unsigned char SEQin(struct riva_par *par, - unsigned char index) -{ - VGA_WR08(par->riva.PVIO, 0x3c4, index); - return (VGA_RD08(par->riva.PVIO, 0x3c5)); -} - -static inline void ATTRout(struct riva_par *par, unsigned char index, - unsigned char val) -{ - VGA_WR08(par->riva.PCIO, 0x3c0, index); - VGA_WR08(par->riva.PCIO, 0x3c0, val); -} - -static inline unsigned char ATTRin(struct riva_par *par, - unsigned char index) -{ - VGA_WR08(par->riva.PCIO, 0x3c0, index); - return (VGA_RD08(par->riva.PCIO, 0x3c1)); -} - -static inline void MISCout(struct riva_par *par, unsigned char val) -{ - VGA_WR08(par->riva.PVIO, 0x3c2, val); -} - -static inline unsigned char MISCin(struct riva_par *par) -{ - return (VGA_RD08(par->riva.PVIO, 0x3cc)); -} - -static u8 byte_rev[256] = { - 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, - 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, - 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, - 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, - 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, - 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, - 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, - 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, - 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, - 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, - 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, - 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, - 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, - 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, - 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, - 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, - 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, - 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, - 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, - 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, - 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, - 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, - 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, - 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, - 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, - 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, - 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, - 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, - 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, - 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, - 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, - 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff, -}; - -static inline void reverse_order(u32 *l) -{ - u8 *a = (u8 *)l; - *a = byte_rev[*a], a++; - *a = byte_rev[*a], a++; - *a = byte_rev[*a], a++; - *a = byte_rev[*a]; -} - -/* ------------------------------------------------------------------------- * - * - * cursor stuff - * - * ------------------------------------------------------------------------- */ - -/** - * rivafb_load_cursor_image - load cursor image to hardware - * @data: address to monochrome bitmap (1 = foreground color, 0 = background) - * @par: pointer to private data - * @w: width of cursor image in pixels - * @h: height of cursor image in scanlines - * @bg: background color (ARGB1555) - alpha bit determines opacity - * @fg: foreground color (ARGB1555) - * - * DESCRIPTiON: - * Loads cursor image based on a monochrome source and mask bitmap. The - * image bits determines the color of the pixel, 0 for background, 1 for - * foreground. Only the affected region (as determined by @w and @h - * parameters) will be updated. - * - * CALLED FROM: - * rivafb_cursor() - */ -static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, - u16 bg, u16 fg, u32 w, u32 h) -{ - int i, j, k = 0; - u32 b, tmp; - u32 *data = (u32 *)data8; - bg = le16_to_cpu(bg); - fg = le16_to_cpu(fg); - - w = (w + 1) & ~1; - - for (i = 0; i < h; i++) { - b = *data++; - reverse_order(&b); - - for (j = 0; j < w/2; j++) { - tmp = 0; -#if defined (__BIG_ENDIAN) - tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; - b <<= 1; - tmp |= (b & (1 << 31)) ? fg : bg; - b <<= 1; -#else - tmp = (b & 1) ? fg : bg; - b >>= 1; - tmp |= (b & 1) ? fg << 16 : bg << 16; - b >>= 1; -#endif - writel(tmp, &par->riva.CURSOR[k++]); - } - k += (MAX_CURS - w)/2; - } -} - -/* ------------------------------------------------------------------------- * - * - * general utility functions - * - * ------------------------------------------------------------------------- */ - -/** - * riva_wclut - set CLUT entry - * @chip: pointer to RIVA_HW_INST object - * @regnum: register number - * @red: red component - * @green: green component - * @blue: blue component - * - * DESCRIPTION: - * Sets color register @regnum. - * - * CALLED FROM: - * rivafb_setcolreg() - */ -static void riva_wclut(RIVA_HW_INST *chip, - unsigned char regnum, unsigned char red, - unsigned char green, unsigned char blue) -{ - VGA_WR08(chip->PDIO, 0x3c8, regnum); - VGA_WR08(chip->PDIO, 0x3c9, red); - VGA_WR08(chip->PDIO, 0x3c9, green); - VGA_WR08(chip->PDIO, 0x3c9, blue); -} - -/** - * riva_rclut - read fromCLUT register - * @chip: pointer to RIVA_HW_INST object - * @regnum: register number - * @red: red component - * @green: green component - * @blue: blue component - * - * DESCRIPTION: - * Reads red, green, and blue from color register @regnum. - * - * CALLED FROM: - * rivafb_setcolreg() - */ -static void riva_rclut(RIVA_HW_INST *chip, - unsigned char regnum, unsigned char *red, - unsigned char *green, unsigned char *blue) -{ - - VGA_WR08(chip->PDIO, 0x3c7, regnum); - *red = VGA_RD08(chip->PDIO, 0x3c9); - *green = VGA_RD08(chip->PDIO, 0x3c9); - *blue = VGA_RD08(chip->PDIO, 0x3c9); -} - -/** - * riva_save_state - saves current chip state - * @par: pointer to riva_par object containing info for current riva board - * @regs: pointer to riva_regs object - * - * DESCRIPTION: - * Saves current chip state to @regs. - * - * CALLED FROM: - * rivafb_probe() - */ -/* from GGI */ -static void riva_save_state(struct riva_par *par, struct riva_regs *regs) -{ - int i; - - NVTRACE_ENTER(); - par->riva.LockUnlock(&par->riva, 0); - - par->riva.UnloadStateExt(&par->riva, ®s->ext); - - regs->misc_output = MISCin(par); - - for (i = 0; i < NUM_CRT_REGS; i++) - regs->crtc[i] = CRTCin(par, i); - - for (i = 0; i < NUM_ATC_REGS; i++) - regs->attr[i] = ATTRin(par, i); - - for (i = 0; i < NUM_GRC_REGS; i++) - regs->gra[i] = GRAin(par, i); - - for (i = 0; i < NUM_SEQ_REGS; i++) - regs->seq[i] = SEQin(par, i); - NVTRACE_LEAVE(); -} - -/** - * riva_load_state - loads current chip state - * @par: pointer to riva_par object containing info for current riva board - * @regs: pointer to riva_regs object - * - * DESCRIPTION: - * Loads chip state from @regs. - * - * CALLED FROM: - * riva_load_video_mode() - * rivafb_probe() - * rivafb_remove() - */ -/* from GGI */ -static void riva_load_state(struct riva_par *par, struct riva_regs *regs) -{ - RIVA_HW_STATE *state = ®s->ext; - int i; - - NVTRACE_ENTER(); - CRTCout(par, 0x11, 0x00); - - par->riva.LockUnlock(&par->riva, 0); - - par->riva.LoadStateExt(&par->riva, state); - - MISCout(par, regs->misc_output); - - for (i = 0; i < NUM_CRT_REGS; i++) { - switch (i) { - case 0x19: - case 0x20 ... 0x40: - break; - default: - CRTCout(par, i, regs->crtc[i]); - } - } - - for (i = 0; i < NUM_ATC_REGS; i++) - ATTRout(par, i, regs->attr[i]); - - for (i = 0; i < NUM_GRC_REGS; i++) - GRAout(par, i, regs->gra[i]); - - for (i = 0; i < NUM_SEQ_REGS; i++) - SEQout(par, i, regs->seq[i]); - NVTRACE_LEAVE(); -} - -/** - * riva_load_video_mode - calculate timings - * @info: pointer to fb_info object containing info for current riva board - * - * DESCRIPTION: - * Calculate some timings and then send em off to riva_load_state(). - * - * CALLED FROM: - * rivafb_set_par() - */ -static void riva_load_video_mode(struct fb_info *info) -{ - int bpp, width, hDisplaySize, hDisplay, hStart, - hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; - int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd; - struct riva_par *par = info->par; - struct riva_regs newmode; - - NVTRACE_ENTER(); - /* time to calculate */ - rivafb_blank(1, info); - - bpp = info->var.bits_per_pixel; - if (bpp == 16 && info->var.green.length == 5) - bpp = 15; - width = info->var.xres_virtual; - hDisplaySize = info->var.xres; - hDisplay = (hDisplaySize / 8) - 1; - hStart = (hDisplaySize + info->var.right_margin) / 8 - 1; - hEnd = (hDisplaySize + info->var.right_margin + - info->var.hsync_len) / 8 - 1; - hTotal = (hDisplaySize + info->var.right_margin + - info->var.hsync_len + info->var.left_margin) / 8 - 5; - hBlankStart = hDisplay; - hBlankEnd = hTotal + 4; - - height = info->var.yres_virtual; - vDisplay = info->var.yres - 1; - vStart = info->var.yres + info->var.lower_margin - 1; - vEnd = info->var.yres + info->var.lower_margin + - info->var.vsync_len - 1; - vTotal = info->var.yres + info->var.lower_margin + - info->var.vsync_len + info->var.upper_margin + 2; - vBlankStart = vDisplay; - vBlankEnd = vTotal + 1; - dotClock = 1000000000 / info->var.pixclock; - - memcpy(&newmode, ®_template, sizeof(struct riva_regs)); - - if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) - vTotal |= 1; - - if (par->FlatPanel) { - vStart = vTotal - 3; - vEnd = vTotal - 2; - vBlankStart = vStart; - hStart = hTotal - 3; - hEnd = hTotal - 2; - hBlankEnd = hTotal + 4; - } - - newmode.crtc[0x0] = Set8Bits (hTotal); - newmode.crtc[0x1] = Set8Bits (hDisplay); - newmode.crtc[0x2] = Set8Bits (hBlankStart); - newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7); - newmode.crtc[0x4] = Set8Bits (hStart); - newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7) - | SetBitField (hEnd, 4: 0, 4:0); - newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); - newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) - | SetBitField (vDisplay, 8: 8, 1:1) - | SetBitField (vStart, 8: 8, 2:2) - | SetBitField (vBlankStart, 8: 8, 3:3) - | SetBit (4) - | SetBitField (vTotal, 9: 9, 5:5) - | SetBitField (vDisplay, 9: 9, 6:6) - | SetBitField (vStart, 9: 9, 7:7); - newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5) - | SetBit (6); - newmode.crtc[0x10] = Set8Bits (vStart); - newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) - | SetBit (5); - newmode.crtc[0x12] = Set8Bits (vDisplay); - newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8); - newmode.crtc[0x15] = Set8Bits (vBlankStart); - newmode.crtc[0x16] = Set8Bits (vBlankEnd); - - newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4) - | SetBitField(vBlankStart,10:10,3:3) - | SetBitField(vStart,10:10,2:2) - | SetBitField(vDisplay,10:10,1:1) - | SetBitField(vTotal,10:10,0:0); - newmode.ext.horiz = SetBitField(hTotal,8:8,0:0) - | SetBitField(hDisplay,8:8,1:1) - | SetBitField(hBlankStart,8:8,2:2) - | SetBitField(hStart,8:8,3:3); - newmode.ext.extra = SetBitField(vTotal,11:11,0:0) - | SetBitField(vDisplay,11:11,2:2) - | SetBitField(vStart,11:11,4:4) - | SetBitField(vBlankStart,11:11,6:6); - - if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { - int tmp = (hTotal >> 1) & ~1; - newmode.ext.interlace = Set8Bits(tmp); - newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4); - } else - newmode.ext.interlace = 0xff; /* interlace off */ - - if (par->riva.Architecture >= NV_ARCH_10) - par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); - - if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) - newmode.misc_output &= ~0x40; - else - newmode.misc_output |= 0x40; - if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) - newmode.misc_output &= ~0x80; - else - newmode.misc_output |= 0x80; - - par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width, - hDisplaySize, height, dotClock); - - newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & - 0xfff000ff; - if (par->FlatPanel == 1) { - newmode.ext.pixel |= (1 << 7); - newmode.ext.scale |= (1 << 8); - } - if (par->SecondCRTC) { - newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & - ~0x00001000; - newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | - 0x00001000; - newmode.ext.crtcOwner = 3; - newmode.ext.pllsel |= 0x20000800; - newmode.ext.vpll2 = newmode.ext.vpll; - } else if (par->riva.twoHeads) { - newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | - 0x00001000; - newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & - ~0x00001000; - newmode.ext.crtcOwner = 0; - newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); - } - if (par->FlatPanel == 1) { - newmode.ext.pixel |= (1 << 7); - newmode.ext.scale |= (1 << 8); - } - newmode.ext.cursorConfig = 0x02000100; - par->current_state = newmode; - riva_load_state(par, &par->current_state); - par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */ - rivafb_blank(0, info); - NVTRACE_LEAVE(); -} - -static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb) -{ - NVTRACE_ENTER(); - var->xres = var->xres_virtual = modedb->xres; - var->yres = modedb->yres; - if (var->yres_virtual < var->yres) - var->yres_virtual = var->yres; - var->xoffset = var->yoffset = 0; - var->pixclock = modedb->pixclock; - var->left_margin = modedb->left_margin; - var->right_margin = modedb->right_margin; - var->upper_margin = modedb->upper_margin; - var->lower_margin = modedb->lower_margin; - var->hsync_len = modedb->hsync_len; - var->vsync_len = modedb->vsync_len; - var->sync = modedb->sync; - var->vmode = modedb->vmode; - NVTRACE_LEAVE(); -} - -/** - * rivafb_do_maximize - - * @info: pointer to fb_info object containing info for current riva board - * @var: - * @nom: - * @den: - * - * DESCRIPTION: - * . - * - * RETURNS: - * -EINVAL on failure, 0 on success - * - * - * CALLED FROM: - * rivafb_check_var() - */ -static int rivafb_do_maximize(struct fb_info *info, - struct fb_var_screeninfo *var, - int nom, int den) -{ - static struct { - int xres, yres; - } modes[] = { - {1600, 1280}, - {1280, 1024}, - {1024, 768}, - {800, 600}, - {640, 480}, - {-1, -1} - }; - int i; - - NVTRACE_ENTER(); - /* use highest possible virtual resolution */ - if (var->xres_virtual == -1 && var->yres_virtual == -1) { - printk(KERN_WARNING PFX - "using maximum available virtual resolution\n"); - for (i = 0; modes[i].xres != -1; i++) { - if (modes[i].xres * nom / den * modes[i].yres < - info->fix.smem_len) - break; - } - if (modes[i].xres == -1) { - printk(KERN_ERR PFX - "could not find a virtual resolution that fits into video memory!!\n"); - NVTRACE("EXIT - EINVAL error\n"); - return -EINVAL; - } - var->xres_virtual = modes[i].xres; - var->yres_virtual = modes[i].yres; - - printk(KERN_INFO PFX - "virtual resolution set to maximum of %dx%d\n", - var->xres_virtual, var->yres_virtual); - } else if (var->xres_virtual == -1) { - var->xres_virtual = (info->fix.smem_len * den / - (nom * var->yres_virtual)) & ~15; - printk(KERN_WARNING PFX - "setting virtual X resolution to %d\n", var->xres_virtual); - } else if (var->yres_virtual == -1) { - var->xres_virtual = (var->xres_virtual + 15) & ~15; - var->yres_virtual = info->fix.smem_len * den / - (nom * var->xres_virtual); - printk(KERN_WARNING PFX - "setting virtual Y resolution to %d\n", var->yres_virtual); - } else { - var->xres_virtual = (var->xres_virtual + 15) & ~15; - if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) { - printk(KERN_ERR PFX - "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", - var->xres, var->yres, var->bits_per_pixel); - NVTRACE("EXIT - EINVAL error\n"); - return -EINVAL; - } - } - - if (var->xres_virtual * nom / den >= 8192) { - printk(KERN_WARNING PFX - "virtual X resolution (%d) is too high, lowering to %d\n", - var->xres_virtual, 8192 * den / nom - 16); - var->xres_virtual = 8192 * den / nom - 16; - } - - if (var->xres_virtual < var->xres) { - printk(KERN_ERR PFX - "virtual X resolution (%d) is smaller than real\n", var->xres_virtual); - return -EINVAL; - } - - if (var->yres_virtual < var->yres) { - printk(KERN_ERR PFX - "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual); - return -EINVAL; - } - if (var->yres_virtual > 0x7fff/nom) - var->yres_virtual = 0x7fff/nom; - if (var->xres_virtual > 0x7fff/nom) - var->xres_virtual = 0x7fff/nom; - NVTRACE_LEAVE(); - return 0; -} - -static void -riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) -{ - RIVA_FIFO_FREE(par->riva, Patt, 4); - NV_WR32(&par->riva.Patt->Color0, 0, clr0); - NV_WR32(&par->riva.Patt->Color1, 0, clr1); - NV_WR32(par->riva.Patt->Monochrome, 0, pat0); - NV_WR32(par->riva.Patt->Monochrome, 4, pat1); -} - -/* acceleration routines */ -static inline void wait_for_idle(struct riva_par *par) -{ - while (par->riva.Busy(&par->riva)); -} - -/* - * Set ROP. Translate X rop into ROP3. Internal routine. - */ -static void -riva_set_rop_solid(struct riva_par *par, int rop) -{ - riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); - RIVA_FIFO_FREE(par->riva, Rop, 1); - NV_WR32(&par->riva.Rop->Rop3, 0, rop); - -} - -static void riva_setup_accel(struct fb_info *info) -{ - struct riva_par *par = info->par; - - RIVA_FIFO_FREE(par->riva, Clip, 2); - NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); - NV_WR32(&par->riva.Clip->WidthHeight, 0, - (info->var.xres_virtual & 0xffff) | - (info->var.yres_virtual << 16)); - riva_set_rop_solid(par, 0xcc); - wait_for_idle(par); -} - -/** - * riva_get_cmap_len - query current color map length - * @var: standard kernel fb changeable data - * - * DESCRIPTION: - * Get current color map length. - * - * RETURNS: - * Length of color map - * - * CALLED FROM: - * rivafb_setcolreg() - */ -static int riva_get_cmap_len(const struct fb_var_screeninfo *var) -{ - int rc = 256; /* reasonable default */ - - switch (var->green.length) { - case 8: - rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */ - break; - case 5: - rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */ - break; - case 6: - rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */ - break; - default: - /* should not occur */ - break; - } - return rc; -} - -/* ------------------------------------------------------------------------- * - * - * framebuffer operations - * - * ------------------------------------------------------------------------- */ - -static int rivafb_open(struct fb_info *info, int user) -{ - struct riva_par *par = info->par; - int cnt = atomic_read(&par->ref_count); - - NVTRACE_ENTER(); - if (!cnt) { -#ifdef CONFIG_X86 - memset(&par->state, 0, sizeof(struct vgastate)); - par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; - /* save the DAC for Riva128 */ - if (par->riva.Architecture == NV_ARCH_03) - par->state.flags |= VGA_SAVE_CMAP; - save_vga(&par->state); -#endif - /* vgaHWunlock() + riva unlock (0x7F) */ - CRTCout(par, 0x11, 0xFF); - par->riva.LockUnlock(&par->riva, 0); - - riva_save_state(par, &par->initial_state); - } - atomic_inc(&par->ref_count); - NVTRACE_LEAVE(); - return 0; -} - -static int rivafb_release(struct fb_info *info, int user) -{ - struct riva_par *par = info->par; - int cnt = atomic_read(&par->ref_count); - - NVTRACE_ENTER(); - if (!cnt) - return -EINVAL; - if (cnt == 1) { - par->riva.LockUnlock(&par->riva, 0); - par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); - riva_load_state(par, &par->initial_state); -#ifdef CONFIG_X86 - restore_vga(&par->state); -#endif - par->riva.LockUnlock(&par->riva, 1); - } - atomic_dec(&par->ref_count); - NVTRACE_LEAVE(); - return 0; -} - -static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) -{ - struct fb_videomode *mode; - struct riva_par *par = info->par; - int nom, den; /* translating from pixels->bytes */ - int mode_valid = 0; - - NVTRACE_ENTER(); - switch (var->bits_per_pixel) { - case 1 ... 8: - var->red.offset = var->green.offset = var->blue.offset = 0; - var->red.length = var->green.length = var->blue.length = 8; - var->bits_per_pixel = 8; - nom = den = 1; - break; - case 9 ... 15: - var->green.length = 5; - /* fall through */ - case 16: - var->bits_per_pixel = 16; - /* The Riva128 supports RGB555 only */ - if (par->riva.Architecture == NV_ARCH_03) - var->green.length = 5; - if (var->green.length == 5) { - /* 0rrrrrgg gggbbbbb */ - var->red.offset = 10; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 5; - var->blue.length = 5; - } else { - /* rrrrrggg gggbbbbb */ - var->red.offset = 11; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 6; - var->blue.length = 5; - } - nom = 2; - den = 1; - break; - case 17 ... 32: - var->red.length = var->green.length = var->blue.length = 8; - var->bits_per_pixel = 32; - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - nom = 4; - den = 1; - break; - default: - printk(KERN_ERR PFX - "mode %dx%dx%d rejected...color depth not supported.\n", - var->xres, var->yres, var->bits_per_pixel); - NVTRACE("EXIT, returning -EINVAL\n"); - return -EINVAL; - } - - if (!strictmode) { - if (!info->monspecs.vfmax || !info->monspecs.hfmax || - !info->monspecs.dclkmax || !fb_validate_mode(var, info)) - mode_valid = 1; - } - - /* calculate modeline if supported by monitor */ - if (!mode_valid && info->monspecs.gtf) { - if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) - mode_valid = 1; - } - - if (!mode_valid) { - mode = fb_find_best_mode(var, &info->modelist); - if (mode) { - riva_update_var(var, mode); - mode_valid = 1; - } - } - - if (!mode_valid && info->monspecs.modedb_len) - return -EINVAL; - - if (var->xres_virtual < var->xres) - var->xres_virtual = var->xres; - if (var->yres_virtual <= var->yres) - var->yres_virtual = -1; - if (rivafb_do_maximize(info, var, nom, den) < 0) - return -EINVAL; - - if (var->xoffset < 0) - var->xoffset = 0; - if (var->yoffset < 0) - var->yoffset = 0; - - /* truncate xoffset and yoffset to maximum if too high */ - if (var->xoffset > var->xres_virtual - var->xres) - var->xoffset = var->xres_virtual - var->xres - 1; - - if (var->yoffset > var->yres_virtual - var->yres) - var->yoffset = var->yres_virtual - var->yres - 1; - - var->red.msb_right = - var->green.msb_right = - var->blue.msb_right = - var->transp.offset = var->transp.length = var->transp.msb_right = 0; - NVTRACE_LEAVE(); - return 0; -} - -static int rivafb_set_par(struct fb_info *info) -{ - struct riva_par *par = info->par; - - NVTRACE_ENTER(); - /* vgaHWunlock() + riva unlock (0x7F) */ - CRTCout(par, 0x11, 0xFF); - par->riva.LockUnlock(&par->riva, 0); - riva_load_video_mode(info); - if(!(info->flags & FBINFO_HWACCEL_DISABLED)) - riva_setup_accel(info); - - par->cursor_reset = 1; - info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); - info->fix.visual = (info->var.bits_per_pixel == 8) ? - FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; - - if (info->flags & FBINFO_HWACCEL_DISABLED) - info->pixmap.scan_align = 1; - else - info->pixmap.scan_align = 4; - NVTRACE_LEAVE(); - return 0; -} - -/** - * rivafb_pan_display - * @var: standard kernel fb changeable data - * @con: TODO - * @info: pointer to fb_info object containing info for current riva board - * - * DESCRIPTION: - * Pan (or wrap, depending on the `vmode' field) the display using the - * `xoffset' and `yoffset' fields of the `var' structure. - * If the values don't fit, return -EINVAL. - * - * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag - */ -static int rivafb_pan_display(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct riva_par *par = info->par; - unsigned int base; - - NVTRACE_ENTER(); - base = var->yoffset * info->fix.line_length + var->xoffset; - par->riva.SetStartAddress(&par->riva, base); - NVTRACE_LEAVE(); - return 0; -} - -static int rivafb_blank(int blank, struct fb_info *info) -{ - struct riva_par *par= info->par; - unsigned char tmp, vesa; - - tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */ - vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ - - NVTRACE_ENTER(); - - if (blank) - tmp |= 0x20; - - switch (blank) { - case FB_BLANK_UNBLANK: - case FB_BLANK_NORMAL: - break; - case FB_BLANK_VSYNC_SUSPEND: - vesa |= 0x80; - break; - case FB_BLANK_HSYNC_SUSPEND: - vesa |= 0x40; - break; - case FB_BLANK_POWERDOWN: - vesa |= 0xc0; - break; - } - - SEQout(par, 0x01, tmp); - CRTCout(par, 0x1a, vesa); - - riva_bl_set_power(info, blank); - - NVTRACE_LEAVE(); - - return 0; -} - -/** - * rivafb_setcolreg - * @regno: register index - * @red: red component - * @green: green component - * @blue: blue component - * @transp: transparency - * @info: pointer to fb_info object containing info for current riva board - * - * DESCRIPTION: - * Set a single color register. The values supplied have a 16 bit - * magnitude. - * - * RETURNS: - * Return != 0 for invalid regno. - * - * CALLED FROM: - * fbcmap.c:fb_set_cmap() - */ -static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info) -{ - struct riva_par *par = info->par; - RIVA_HW_INST *chip = &par->riva; - int i; - - if (regno >= riva_get_cmap_len(&info->var)) - return -EINVAL; - - if (info->var.grayscale) { - /* gray = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = - (red * 77 + green * 151 + blue * 28) >> 8; - } - - if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { - ((u32 *) info->pseudo_palette)[regno] = - (regno << info->var.red.offset) | - (regno << info->var.green.offset) | - (regno << info->var.blue.offset); - /* - * The Riva128 2D engine requires color information in - * TrueColor format even if framebuffer is in DirectColor - */ - if (par->riva.Architecture == NV_ARCH_03) { - switch (info->var.bits_per_pixel) { - case 16: - par->palette[regno] = ((red & 0xf800) >> 1) | - ((green & 0xf800) >> 6) | - ((blue & 0xf800) >> 11); - break; - case 32: - par->palette[regno] = ((red & 0xff00) << 8) | - ((green & 0xff00)) | - ((blue & 0xff00) >> 8); - break; - } - } - } - - switch (info->var.bits_per_pixel) { - case 8: - /* "transparent" stuff is completely ignored. */ - riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); - break; - case 16: - if (info->var.green.length == 5) { - for (i = 0; i < 8; i++) { - riva_wclut(chip, regno*8+i, red >> 8, - green >> 8, blue >> 8); - } - } else { - u8 r, g, b; - - if (regno < 32) { - for (i = 0; i < 8; i++) { - riva_wclut(chip, regno*8+i, - red >> 8, green >> 8, - blue >> 8); - } - } - riva_rclut(chip, regno*4, &r, &g, &b); - for (i = 0; i < 4; i++) - riva_wclut(chip, regno*4+i, r, - green >> 8, b); - } - break; - case 32: - riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); - break; - default: - /* do nothing */ - break; - } - return 0; -} - -/** - * rivafb_fillrect - hardware accelerated color fill function - * @info: pointer to fb_info structure - * @rect: pointer to fb_fillrect structure - * - * DESCRIPTION: - * This function fills up a region of framebuffer memory with a solid - * color with a choice of two different ROP's, copy or invert. - * - * CALLED FROM: - * framebuffer hook - */ -static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) -{ - struct riva_par *par = info->par; - u_int color, rop = 0; - - if ((info->flags & FBINFO_HWACCEL_DISABLED)) { - cfb_fillrect(info, rect); - return; - } - - if (info->var.bits_per_pixel == 8) - color = rect->color; - else { - if (par->riva.Architecture != NV_ARCH_03) - color = ((u32 *)info->pseudo_palette)[rect->color]; - else - color = par->palette[rect->color]; - } - - switch (rect->rop) { - case ROP_XOR: - rop = 0x66; - break; - case ROP_COPY: - default: - rop = 0xCC; - break; - } - - riva_set_rop_solid(par, rop); - - RIVA_FIFO_FREE(par->riva, Bitmap, 1); - NV_WR32(&par->riva.Bitmap->Color1A, 0, color); - - RIVA_FIFO_FREE(par->riva, Bitmap, 2); - NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, - (rect->dx << 16) | rect->dy); - mb(); - NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, - (rect->width << 16) | rect->height); - mb(); - riva_set_rop_solid(par, 0xcc); - -} - -/** - * rivafb_copyarea - hardware accelerated blit function - * @info: pointer to fb_info structure - * @region: pointer to fb_copyarea structure - * - * DESCRIPTION: - * This copies an area of pixels from one location to another - * - * CALLED FROM: - * framebuffer hook - */ -static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) -{ - struct riva_par *par = info->par; - - if ((info->flags & FBINFO_HWACCEL_DISABLED)) { - cfb_copyarea(info, region); - return; - } - - RIVA_FIFO_FREE(par->riva, Blt, 3); - NV_WR32(&par->riva.Blt->TopLeftSrc, 0, - (region->sy << 16) | region->sx); - NV_WR32(&par->riva.Blt->TopLeftDst, 0, - (region->dy << 16) | region->dx); - mb(); - NV_WR32(&par->riva.Blt->WidthHeight, 0, - (region->height << 16) | region->width); - mb(); -} - -static inline void convert_bgcolor_16(u32 *col) -{ - *col = ((*col & 0x0000F800) << 8) - | ((*col & 0x00007E0) << 5) - | ((*col & 0x0000001F) << 3) - | 0xFF000000; - mb(); -} - -/** - * rivafb_imageblit: hardware accelerated color expand function - * @info: pointer to fb_info structure - * @image: pointer to fb_image structure - * - * DESCRIPTION: - * If the source is a monochrome bitmap, the function fills up a a region - * of framebuffer memory with pixels whose color is determined by the bit - * setting of the bitmap, 1 - foreground, 0 - background. - * - * If the source is not a monochrome bitmap, color expansion is not done. - * In this case, it is channeled to a software function. - * - * CALLED FROM: - * framebuffer hook - */ -static void rivafb_imageblit(struct fb_info *info, - const struct fb_image *image) -{ - struct riva_par *par = info->par; - u32 fgx = 0, bgx = 0, width, tmp; - u8 *cdat = (u8 *) image->data; - volatile u32 __iomem *d; - int i, size; - - if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { - cfb_imageblit(info, image); - return; - } - - switch (info->var.bits_per_pixel) { - case 8: - fgx = image->fg_color; - bgx = image->bg_color; - break; - case 16: - case 32: - if (par->riva.Architecture != NV_ARCH_03) { - fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; - bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; - } else { - fgx = par->palette[image->fg_color]; - bgx = par->palette[image->bg_color]; - } - if (info->var.green.length == 6) - convert_bgcolor_16(&bgx); - break; - } - - RIVA_FIFO_FREE(par->riva, Bitmap, 7); - NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, - (image->dy << 16) | (image->dx & 0xFFFF)); - NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, - (((image->dy + image->height) << 16) | - ((image->dx + image->width) & 0xffff))); - NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); - NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); - NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, - (image->height << 16) | ((image->width + 31) & ~31)); - NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, - (image->height << 16) | ((image->width + 31) & ~31)); - NV_WR32(&par->riva.Bitmap->PointE, 0, - (image->dy << 16) | (image->dx & 0xFFFF)); - - d = &par->riva.Bitmap->MonochromeData01E; - - width = (image->width + 31)/32; - size = width * image->height; - while (size >= 16) { - RIVA_FIFO_FREE(par->riva, Bitmap, 16); - for (i = 0; i < 16; i++) { - tmp = *((u32 *)cdat); - cdat = (u8 *)((u32 *)cdat + 1); - reverse_order(&tmp); - NV_WR32(d, i*4, tmp); - } - size -= 16; - } - if (size) { - RIVA_FIFO_FREE(par->riva, Bitmap, size); - for (i = 0; i < size; i++) { - tmp = *((u32 *) cdat); - cdat = (u8 *)((u32 *)cdat + 1); - reverse_order(&tmp); - NV_WR32(d, i*4, tmp); - } - } -} - -/** - * rivafb_cursor - hardware cursor function - * @info: pointer to info structure - * @cursor: pointer to fbcursor structure - * - * DESCRIPTION: - * A cursor function that supports displaying a cursor image via hardware. - * Within the kernel, copy and invert rops are supported. If exported - * to user space, only the copy rop will be supported. - * - * CALLED FROM - * framebuffer hook - */ -static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - struct riva_par *par = info->par; - u8 data[MAX_CURS * MAX_CURS/8]; - int i, set = cursor->set; - u16 fg, bg; - - if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) - return -ENXIO; - - par->riva.ShowHideCursor(&par->riva, 0); - - if (par->cursor_reset) { - set = FB_CUR_SETALL; - par->cursor_reset = 0; - } - - if (set & FB_CUR_SETSIZE) - memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); - - if (set & FB_CUR_SETPOS) { - u32 xx, yy, temp; - - yy = cursor->image.dy - info->var.yoffset; - xx = cursor->image.dx - info->var.xoffset; - temp = xx & 0xFFFF; - temp |= yy << 16; - - NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); - } - - - if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { - u32 bg_idx = cursor->image.bg_color; - u32 fg_idx = cursor->image.fg_color; - u32 s_pitch = (cursor->image.width+7) >> 3; - u32 d_pitch = MAX_CURS/8; - u8 *dat = (u8 *) cursor->image.data; - u8 *msk = (u8 *) cursor->mask; - u8 *src; - - src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); - - if (src) { - switch (cursor->rop) { - case ROP_XOR: - for (i = 0; i < s_pitch * cursor->image.height; i++) - src[i] = dat[i] ^ msk[i]; - break; - case ROP_COPY: - default: - for (i = 0; i < s_pitch * cursor->image.height; i++) - src[i] = dat[i] & msk[i]; - break; - } - - fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, - cursor->image.height); - - bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | - ((info->cmap.green[bg_idx] & 0xf8) << 2) | - ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | - 1 << 15; - - fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | - ((info->cmap.green[fg_idx] & 0xf8) << 2) | - ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | - 1 << 15; - - par->riva.LockUnlock(&par->riva, 0); - - rivafb_load_cursor_image(par, data, bg, fg, - cursor->image.width, - cursor->image.height); - kfree(src); - } - } - - if (cursor->enable) - par->riva.ShowHideCursor(&par->riva, 1); - - return 0; -} - -static int rivafb_sync(struct fb_info *info) -{ - struct riva_par *par = info->par; - - wait_for_idle(par); - return 0; -} - -/* ------------------------------------------------------------------------- * - * - * initialization helper functions - * - * ------------------------------------------------------------------------- */ - -/* kernel interface */ -static struct fb_ops riva_fb_ops = { - .owner = THIS_MODULE, - .fb_open = rivafb_open, - .fb_release = rivafb_release, - .fb_check_var = rivafb_check_var, - .fb_set_par = rivafb_set_par, - .fb_setcolreg = rivafb_setcolreg, - .fb_pan_display = rivafb_pan_display, - .fb_blank = rivafb_blank, - .fb_fillrect = rivafb_fillrect, - .fb_copyarea = rivafb_copyarea, - .fb_imageblit = rivafb_imageblit, - .fb_cursor = rivafb_cursor, - .fb_sync = rivafb_sync, -}; - -static int __devinit riva_set_fbinfo(struct fb_info *info) -{ - unsigned int cmap_len; - struct riva_par *par = info->par; - - NVTRACE_ENTER(); - info->flags = FBINFO_DEFAULT - | FBINFO_HWACCEL_XPAN - | FBINFO_HWACCEL_YPAN - | FBINFO_HWACCEL_COPYAREA - | FBINFO_HWACCEL_FILLRECT - | FBINFO_HWACCEL_IMAGEBLIT; - - /* Accel seems to not work properly on NV30 yet...*/ - if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { - printk(KERN_DEBUG PFX "disabling acceleration\n"); - info->flags |= FBINFO_HWACCEL_DISABLED; - } - - info->var = rivafb_default_var; - info->fix.visual = (info->var.bits_per_pixel == 8) ? - FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; - - info->pseudo_palette = par->pseudo_palette; - - cmap_len = riva_get_cmap_len(&info->var); - fb_alloc_cmap(&info->cmap, cmap_len, 0); - - info->pixmap.size = 8 * 1024; - info->pixmap.buf_align = 4; - info->pixmap.access_align = 32; - info->pixmap.flags = FB_PIXMAP_SYSTEM; - info->var.yres_virtual = -1; - NVTRACE_LEAVE(); - return (rivafb_check_var(&info->var, info)); -} - -#ifdef CONFIG_PPC_OF -static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) -{ - struct riva_par *par = info->par; - struct device_node *dp; - const unsigned char *pedid = NULL; - const unsigned char *disptype = NULL; - static char *propnames[] = { - "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL }; - int i; - - NVTRACE_ENTER(); - dp = pci_device_to_OF_node(pd); - for (; dp != NULL; dp = dp->child) { - disptype = get_property(dp, "display-type", NULL); - if (disptype == NULL) - continue; - if (strncmp(disptype, "LCD", 3) != 0) - continue; - for (i = 0; propnames[i] != NULL; ++i) { - pedid = get_property(dp, propnames[i], NULL); - if (pedid != NULL) { - par->EDID = pedid; - NVTRACE("LCD found.\n"); - return 1; - } - } - } - NVTRACE_LEAVE(); - return 0; -} -#endif /* CONFIG_PPC_OF */ - -#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF) -static int __devinit riva_get_EDID_i2c(struct fb_info *info) -{ - struct riva_par *par = info->par; - struct fb_var_screeninfo var; - int i; - - NVTRACE_ENTER(); - riva_create_i2c_busses(par); - for (i = 0; i < par->bus; i++) { - riva_probe_i2c_connector(par, i+1, &par->EDID); - if (par->EDID && !fb_parse_edid(par->EDID, &var)) { - printk(PFX "Found EDID Block from BUS %i\n", i); - break; - } - } - - NVTRACE_LEAVE(); - return (par->EDID) ? 1 : 0; -} -#endif /* CONFIG_FB_RIVA_I2C */ - -static void __devinit riva_update_default_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct fb_monspecs *specs = &info->monspecs; - struct fb_videomode modedb; - - NVTRACE_ENTER(); - /* respect mode options */ - if (mode_option) { - fb_find_mode(var, info, mode_option, - specs->modedb, specs->modedb_len, - NULL, 8); - } else if (specs->modedb != NULL) { - /* get preferred timing */ - if (info->monspecs.misc & FB_MISC_1ST_DETAIL) { - int i; - - for (i = 0; i < specs->modedb_len; i++) { - if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { - modedb = specs->modedb[i]; - break; - } - } - } else { - /* otherwise, get first mode in database */ - modedb = specs->modedb[0]; - } - var->bits_per_pixel = 8; - riva_update_var(var, &modedb); - } - NVTRACE_LEAVE(); -} - - -static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) -{ - NVTRACE_ENTER(); -#ifdef CONFIG_PPC_OF - if (!riva_get_EDID_OF(info, pdev)) - printk(PFX "could not retrieve EDID from OF\n"); -#elif defined(CONFIG_FB_RIVA_I2C) - if (!riva_get_EDID_i2c(info)) - printk(PFX "could not retrieve EDID from DDC/I2C\n"); -#endif - NVTRACE_LEAVE(); -} - - -static void __devinit riva_get_edidinfo(struct fb_info *info) -{ - struct fb_var_screeninfo *var = &rivafb_default_var; - struct riva_par *par = info->par; - - fb_edid_to_monspecs(par->EDID, &info->monspecs); - fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, - &info->modelist); - riva_update_default_var(var, info); - - /* if user specified flatpanel, we respect that */ - if (info->monspecs.input & FB_DISP_DDI) - par->FlatPanel = 1; -} - -/* ------------------------------------------------------------------------- * - * - * PCI bus - * - * ------------------------------------------------------------------------- */ - -static u32 __devinit riva_get_arch(struct pci_dev *pd) -{ - u32 arch = 0; - - switch (pd->device & 0x0ff0) { - case 0x0100: /* GeForce 256 */ - case 0x0110: /* GeForce2 MX */ - case 0x0150: /* GeForce2 */ - case 0x0170: /* GeForce4 MX */ - case 0x0180: /* GeForce4 MX (8x AGP) */ - case 0x01A0: /* nForce */ - case 0x01F0: /* nForce2 */ - arch = NV_ARCH_10; - break; - case 0x0200: /* GeForce3 */ - case 0x0250: /* GeForce4 Ti */ - case 0x0280: /* GeForce4 Ti (8x AGP) */ - arch = NV_ARCH_20; - break; - case 0x0300: /* GeForceFX 5800 */ - case 0x0310: /* GeForceFX 5600 */ - case 0x0320: /* GeForceFX 5200 */ - case 0x0330: /* GeForceFX 5900 */ - case 0x0340: /* GeForceFX 5700 */ - arch = NV_ARCH_30; - break; - case 0x0020: /* TNT, TNT2 */ - arch = NV_ARCH_04; - break; - case 0x0010: /* Riva128 */ - arch = NV_ARCH_03; - break; - default: /* unknown architecture */ - break; - } - return arch; -} - -static int __devinit rivafb_probe(struct pci_dev *pd, - const struct pci_device_id *ent) -{ - struct riva_par *default_par; - struct fb_info *info; - int ret; - - NVTRACE_ENTER(); - assert(pd != NULL); - - info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); - if (!info) { - printk (KERN_ERR PFX "could not allocate memory\n"); - ret = -ENOMEM; - goto err_ret; - } - default_par = info->par; - default_par->pdev = pd; - - info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL); - if (info->pixmap.addr == NULL) { - ret = -ENOMEM; - goto err_framebuffer_release; - } - memset(info->pixmap.addr, 0, 8 * 1024); - - ret = pci_enable_device(pd); - if (ret < 0) { - printk(KERN_ERR PFX "cannot enable PCI device\n"); - goto err_free_pixmap; - } - - ret = pci_request_regions(pd, "rivafb"); - if (ret < 0) { - printk(KERN_ERR PFX "cannot request PCI regions\n"); - goto err_disable_device; - } - - default_par->riva.Architecture = riva_get_arch(pd); - - default_par->Chipset = (pd->vendor << 16) | pd->device; - printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); - - if(default_par->riva.Architecture == 0) { - printk(KERN_ERR PFX "unknown NV_ARCH\n"); - ret=-ENODEV; - goto err_release_region; - } - if(default_par->riva.Architecture == NV_ARCH_10 || - default_par->riva.Architecture == NV_ARCH_20 || - default_par->riva.Architecture == NV_ARCH_30) { - sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); - } else { - sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); - } - - default_par->FlatPanel = flatpanel; - if (flatpanel == 1) - printk(KERN_INFO PFX "flatpanel support enabled\n"); - default_par->forceCRTC = forceCRTC; - - rivafb_fix.mmio_len = pci_resource_len(pd, 0); - rivafb_fix.smem_len = pci_resource_len(pd, 1); - - { - /* enable IO and mem if not already done */ - unsigned short cmd; - - pci_read_config_word(pd, PCI_COMMAND, &cmd); - cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); - pci_write_config_word(pd, PCI_COMMAND, cmd); - } - - rivafb_fix.mmio_start = pci_resource_start(pd, 0); - rivafb_fix.smem_start = pci_resource_start(pd, 1); - - default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, - rivafb_fix.mmio_len); - if (!default_par->ctrl_base) { - printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); - ret = -EIO; - goto err_release_region; - } - - switch (default_par->riva.Architecture) { - case NV_ARCH_03: - /* Riva128's PRAMIN is in the "framebuffer" space - * Since these cards were never made with more than 8 megabytes - * we can safely allocate this separately. - */ - default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); - if (!default_par->riva.PRAMIN) { - printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); - ret = -EIO; - goto err_iounmap_ctrl_base; - } - break; - case NV_ARCH_04: - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - default_par->riva.PCRTC0 = - (u32 __iomem *)(default_par->ctrl_base + 0x00600000); - default_par->riva.PRAMIN = - (u32 __iomem *)(default_par->ctrl_base + 0x00710000); - break; - } - riva_common_setup(default_par); - - if (default_par->riva.Architecture == NV_ARCH_03) { - default_par->riva.PCRTC = default_par->riva.PCRTC0 - = default_par->riva.PGRAPH; - } - - rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; - default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; - info->screen_base = ioremap(rivafb_fix.smem_start, - rivafb_fix.smem_len); - if (!info->screen_base) { - printk(KERN_ERR PFX "cannot ioremap FB base\n"); - ret = -EIO; - goto err_iounmap_pramin; - } - -#ifdef CONFIG_MTRR - if (!nomtrr) { - default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start, - rivafb_fix.smem_len, - MTRR_TYPE_WRCOMB, 1); - if (default_par->mtrr.vram < 0) { - printk(KERN_ERR PFX "unable to setup MTRR\n"); - } else { - default_par->mtrr.vram_valid = 1; - /* let there be speed */ - printk(KERN_INFO PFX "RIVA MTRR set to ON\n"); - } - } -#endif /* CONFIG_MTRR */ - - info->fbops = &riva_fb_ops; - info->fix = rivafb_fix; - riva_get_EDID(info, pd); - riva_get_edidinfo(info); - - ret=riva_set_fbinfo(info); - if (ret < 0) { - printk(KERN_ERR PFX "error setting initial video mode\n"); - goto err_iounmap_screen_base; - } - - fb_destroy_modedb(info->monspecs.modedb); - info->monspecs.modedb = NULL; - - pci_set_drvdata(pd, info); - riva_bl_init(info->par); - ret = register_framebuffer(info); - if (ret < 0) { - printk(KERN_ERR PFX - "error registering riva framebuffer\n"); - goto err_iounmap_screen_base; - } - - printk(KERN_INFO PFX - "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", - info->fix.id, - RIVAFB_VERSION, - info->fix.smem_len / (1024 * 1024), - info->fix.smem_start); - - NVTRACE_LEAVE(); - return 0; - -err_iounmap_screen_base: -#ifdef CONFIG_FB_RIVA_I2C - riva_delete_i2c_busses(info->par); -#endif - iounmap(info->screen_base); -err_iounmap_pramin: - if (default_par->riva.Architecture == NV_ARCH_03) - iounmap(default_par->riva.PRAMIN); -err_iounmap_ctrl_base: - iounmap(default_par->ctrl_base); -err_release_region: - pci_release_regions(pd); -err_disable_device: -err_free_pixmap: - kfree(info->pixmap.addr); -err_framebuffer_release: - framebuffer_release(info); -err_ret: - return ret; -} - -static void __exit rivafb_remove(struct pci_dev *pd) -{ - struct fb_info *info = pci_get_drvdata(pd); - struct riva_par *par = info->par; - - NVTRACE_ENTER(); - - riva_bl_exit(par); - -#ifdef CONFIG_FB_RIVA_I2C - riva_delete_i2c_busses(par); - kfree(par->EDID); -#endif - - unregister_framebuffer(info); -#ifdef CONFIG_MTRR - if (par->mtrr.vram_valid) - mtrr_del(par->mtrr.vram, info->fix.smem_start, - info->fix.smem_len); -#endif /* CONFIG_MTRR */ - - iounmap(par->ctrl_base); - iounmap(info->screen_base); - if (par->riva.Architecture == NV_ARCH_03) - iounmap(par->riva.PRAMIN); - pci_release_regions(pd); - kfree(info->pixmap.addr); - framebuffer_release(info); - pci_set_drvdata(pd, NULL); - NVTRACE_LEAVE(); -} - -/* ------------------------------------------------------------------------- * - * - * initialization - * - * ------------------------------------------------------------------------- */ - -#ifndef MODULE -static int __init rivafb_setup(char *options) -{ - char *this_opt; - - NVTRACE_ENTER(); - if (!options || !*options) - return 0; - - while ((this_opt = strsep(&options, ",")) != NULL) { - if (!strncmp(this_opt, "forceCRTC", 9)) { - char *p; - - p = this_opt + 9; - if (!*p || !*(++p)) continue; - forceCRTC = *p - '0'; - if (forceCRTC < 0 || forceCRTC > 1) - forceCRTC = -1; - } else if (!strncmp(this_opt, "flatpanel", 9)) { - flatpanel = 1; -#ifdef CONFIG_MTRR - } else if (!strncmp(this_opt, "nomtrr", 6)) { - nomtrr = 1; -#endif - } else if (!strncmp(this_opt, "strictmode", 10)) { - strictmode = 1; - } else if (!strncmp(this_opt, "noaccel", 7)) { - noaccel = 1; - } else - mode_option = this_opt; - } - NVTRACE_LEAVE(); - return 0; -} -#endif /* !MODULE */ - -static struct pci_driver rivafb_driver = { - .name = "rivafb", - .id_table = rivafb_pci_tbl, - .probe = rivafb_probe, - .remove = __exit_p(rivafb_remove), -}; - - - -/* ------------------------------------------------------------------------- * - * - * modularization - * - * ------------------------------------------------------------------------- */ - -static int __devinit rivafb_init(void) -{ -#ifndef MODULE - char *option = NULL; - - if (fb_get_options("rivafb", &option)) - return -ENODEV; - rivafb_setup(option); -#endif - return pci_register_driver(&rivafb_driver); -} - - -module_init(rivafb_init); - -#ifdef MODULE -static void __exit rivafb_exit(void) -{ - pci_unregister_driver(&rivafb_driver); -} - -module_exit(rivafb_exit); -#endif /* MODULE */ - -module_param(noaccel, bool, 0); -MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); -module_param(flatpanel, int, 0); -MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); -module_param(forceCRTC, int, 0); -MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); -#ifdef CONFIG_MTRR -module_param(nomtrr, bool, 0); -MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); -#endif -module_param(strictmode, bool, 0); -MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); - -MODULE_AUTHOR("Ani Joshi, maintainer"); -MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/riva/nv4ref.h b/drivers/video/riva/nv4ref.h deleted file mode 100644 index 3b5f9117c37..00000000000 --- a/drivers/video/riva/nv4ref.h +++ /dev/null @@ -1,2445 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - - /***************************************************************************\ -|* Modified 1999 by Fredrik Reite (fredrik@reite.com) *| - \***************************************************************************/ - - -#ifndef __NV4REF_H__ -#define __NV4REF_H__ - -/* Magic values to lock/unlock extended regs */ -#define NV_CIO_SR_LOCK_INDEX 0x0000001F /* */ -#define NV_CIO_SR_UNLOCK_RW_VALUE 0x00000057 /* */ -#define NV_CIO_SR_UNLOCK_RO_VALUE 0x00000075 /* */ -#define NV_CIO_SR_LOCK_VALUE 0x00000099 /* */ - -#define UNLOCK_EXT_MAGIC 0x57 -#define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */ - -#define LOCK_EXT_INDEX 0x6 - -#define NV_PCRTC_HORIZ_TOTAL 0x00 -#define NV_PCRTC_HORIZ_DISPLAY_END 0x01 -#define NV_PCRTC_HORIZ_BLANK_START 0x02 - -#define NV_PCRTC_HORIZ_BLANK_END 0x03 -#define NV_PCRTC_HORIZ_BLANK_END_EVRA 7:7 -#define NV_PCRTC_HORIZ_BLANK_END_DISPLAY_END_SKEW 6:5 -#define NV_PCRTC_HORIZ_BLANK_END_HORIZ_BLANK_END 4:0 - -#define NV_PCRTC_HORIZ_RETRACE_START 0x04 - -#define NV_PCRTC_HORIZ_RETRACE_END 0x05 -#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_BLANK_END_5 7:7 -#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_SKEW 6:5 -#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_END 4:0 - -#define NV_PCRTC_VERT_TOTAL 0x06 - -#define NV_PCRTC_OVERFLOW 0x07 -#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_9 7:7 -#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_9 6:6 -#define NV_PCRTC_OVERFLOW_VERT_TOTAL_9 5:5 -#define NV_PCRTC_OVERFLOW_LINE_COMPARE_8 4:4 -#define NV_PCRTC_OVERFLOW_VERT_BLANK_START_8 3:3 -#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_8 2:2 -#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_8 1:1 -#define NV_PCRTC_OVERFLOW_VERT_TOTAL_8 0:0 - -#define NV_PCRTC_PRESET_ROW_SCAN 0x08 - -#define NV_PCRTC_MAX_SCAN_LINE 0x09 -#define NV_PCRTC_MAX_SCAN_LINE_DOUBLE_SCAN 7:7 -#define NV_PCRTC_MAX_SCAN_LINE_LINE_COMPARE_9 6:6 -#define NV_PCRTC_MAX_SCAN_LINE_VERT_BLANK_START_9 5:5 -#define NV_PCRTC_MAX_SCAN_LINE_MAX_SCAN_LINE 4:0 - -#define NV_PCRTC_CURSOR_START 0x0A -#define NV_PCRTC_CURSOR_END 0x0B -#define NV_PCRTC_START_ADDR_HIGH 0x0C -#define NV_PCRTC_START_ADDR_LOW 0x0D -#define NV_PCRTC_CURSOR_LOCATION_HIGH 0x0E -#define NV_PCRTC_CURSOR_LOCATION_LOW 0x0F - -#define NV_PCRTC_VERT_RETRACE_START 0x10 -#define NV_PCRTC_VERT_RETRACE_END 0x11 -#define NV_PCRTC_VERT_DISPLAY_END 0x12 -#define NV_PCRTC_OFFSET 0x13 -#define NV_PCRTC_UNDERLINE_LOCATION 0x14 -#define NV_PCRTC_VERT_BLANK_START 0x15 -#define NV_PCRTC_VERT_BLANK_END 0x16 -#define NV_PCRTC_MODE_CONTROL 0x17 -#define NV_PCRTC_LINE_COMPARE 0x18 - -/* Extended offset and start address */ -#define NV_PCRTC_REPAINT0 0x19 -#define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5 -#define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0 - -/* Horizonal extended bits */ -#define NV_PCRTC_HORIZ_EXTRA 0x2d -#define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4 -#define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3 -#define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2 -#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1 -#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0 - -/* Assorted extra bits */ -#define NV_PCRTC_EXTRA 0x25 -#define NV_PCRTC_EXTRA_OFFSET_11 5:5 -#define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4 -#define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3 -#define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2 -#define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1 -#define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0 - -/* Controls how much data the refresh fifo requests */ -#define NV_PCRTC_FIFO_CONTROL 0x1b -#define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4 - -/* When the fifo occupancy falls below *twice* the watermark, - * the refresh fifo will start to be refilled. If this value is - * too low, you will get junk on the screen. Too high, and performance - * will suffer. Watermark in units of 8 bytes - */ -#define NV_PCRTC_FIFO 0x20 -#define NV_PCRTC_FIFO_RESET 7:7 -#define NV_PCRTC_FIFO_WATERMARK 5:0 - -/* Various flags */ -#define NV_PCRTC_REPAINT1 0x1a -#define NV_PCRTC_REPAINT1_HSYNC 7:7 -#define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01 -#define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00 -#define NV_PCRTC_REPAINT1_VSYNC 6:6 -#define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01 -#define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00 -#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4 -#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01 -#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00 -#define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2 -#define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01 -#define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */ -#define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1 -#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00 -#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01 - -#define NV_PCRTC_GRCURSOR0 0x30 -#define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0 - -#define NV_PCRTC_GRCURSOR1 0x31 -#define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3 -#define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1 -#define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0 -#define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1 -#define NV_PCRTC_GRCURSOR1_CURSOR 0:0 -#define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0 -#define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1 - -/* Controls what the format of the framebuffer is */ -#define NV_PCRTC_PIXEL 0x28 -#define NV_PCRTC_PIXEL_MODE 7:7 -#define NV_PCRTC_PIXEL_MODE_TV 0x01 -#define NV_PCRTC_PIXEL_MODE_VGA 0x00 -#define NV_PCRTC_PIXEL_TV_MODE 6:6 -#define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00 -#define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01 -#define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3 -#define NV_PCRTC_PIXEL_FORMAT 1:0 -#define NV_PCRTC_PIXEL_FORMAT_VGA 0x00 -#define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01 -#define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02 -#define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03 - -/* RAMDAC registers and fields */ -#define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */ -#define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */ -#define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */ -#define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */ -#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 /* RW-4R */ -#define NV_PRAMDAC_NVPLL_COEFF_MDIV 7:0 /* RWIUF */ -#define NV_PRAMDAC_NVPLL_COEFF_NDIV 15:8 /* RWIUF */ -#define NV_PRAMDAC_NVPLL_COEFF_PDIV 18:16 /* RWIVF */ -#define NV_PRAMDAC_MPLL_COEFF 0x00680504 /* RW-4R */ -#define NV_PRAMDAC_MPLL_COEFF_MDIV 7:0 /* RWIUF */ -#define NV_PRAMDAC_MPLL_COEFF_NDIV 15:8 /* RWIUF */ -#define NV_PRAMDAC_MPLL_COEFF_PDIV 18:16 /* RWIVF */ -#define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */ -#define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */ -#define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */ -#define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */ -#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */ - -/* Master Control */ -#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */ -#define NV_PMC_BOOT_0 0x00000000 /* R--4R */ -#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* C--VF */ -#define NV_PMC_BOOT_0_MINOR_REVISION_0 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* C--VF */ -#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_IMPLEMENTATION 11:8 /* C--VF */ -#define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_ARCHITECTURE 15:12 /* C--VF */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV0 0x00000000 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV1 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV2 0x00000002 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV3 0x00000003 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV4 0x00000004 /* C---V */ -#define NV_PMC_BOOT_0_FIB_REVISION 19:16 /* C--VF */ -#define NV_PMC_BOOT_0_FIB_REVISION_0 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MASK_REVISION 23:20 /* C--VF */ -#define NV_PMC_BOOT_0_MASK_REVISION_A 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MASK_REVISION_B 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_MANUFACTURER 27:24 /* C--UF */ -#define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_FOUNDRY 31:28 /* C--VF */ -#define NV_PMC_BOOT_0_FOUNDRY_SGS 0x00000000 /* ----V */ -#define NV_PMC_BOOT_0_FOUNDRY_HELIOS 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000002 /* C---V */ -#define NV_PMC_INTR_0 0x00000100 /* RW-4R */ -#define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */ -#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */ -#define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */ -#define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */ -#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */ -#define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PCRTC 24:24 /* R--VF */ -#define NV_PMC_INTR_0_PCRTC_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PCRTC_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */ -#define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */ -#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */ -#define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */ -#define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */ -#define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */ -#define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */ -#define NV_PMC_INTR_READ_0 0x00000160 /* R--4R */ -#define NV_PMC_INTR_READ_0_INTA 0:0 /* R--VF */ -#define NV_PMC_INTR_READ_0_INTA_LOW 0x00000000 /* R---V */ -#define NV_PMC_INTR_READ_0_INTA_HIGH 0x00000001 /* R---V */ -#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ -#define NV_PMC_ENABLE_PMEDIA 4:4 /* RWIVF */ -#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ -#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */ -#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PPMI 16:16 /* RWIVF */ -#define NV_PMC_ENABLE_PPMI_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PPMI_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PFB 20:20 /* RWIVF */ -#define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RW--V */ -#define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RWI-V */ -#define NV_PMC_ENABLE_PCRTC 24:24 /* RWIVF */ -#define NV_PMC_ENABLE_PCRTC_DISABLED 0x00000000 /* RW--V */ -#define NV_PMC_ENABLE_PCRTC_ENABLED 0x00000001 /* RWI-V */ -#define NV_PMC_ENABLE_PVIDEO 28:28 /* RWIVF */ -#define NV_PMC_ENABLE_PVIDEO_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PVIDEO_ENABLED 0x00000001 /* RW--V */ - -/* dev_timer.ref */ -#define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */ -#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */ -#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */ -#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */ -#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */ -#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */ -#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */ -#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */ -#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */ -#define NV_PTIMER_NUMERATOR 0x00009200 /* RW-4R */ -#define NV_PTIMER_NUMERATOR_VALUE 15:0 /* RWIUF */ -#define NV_PTIMER_NUMERATOR_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PTIMER_DENOMINATOR 0x00009210 /* RW-4R */ -#define NV_PTIMER_DENOMINATOR_VALUE 15:0 /* RWIUF */ -#define NV_PTIMER_DENOMINATOR_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */ -#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */ -#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */ -#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */ -#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */ -#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */ - -/* dev_fifo.ref */ -#define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */ -#define NV_PFIFO_DELAY_0 0x00002040 /* RW-4R */ -#define NV_PFIFO_DELAY_0_WAIT_RETRY 9:0 /* RWIUF */ -#define NV_PFIFO_DELAY_0_WAIT_RETRY_0 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_TIMESLICE 0x00002044 /* RW-4R */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT 16:0 /* RWIUF */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ -#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ -#define NV_PFIFO_PIO_TIMESLICE 0x00002048 /* RW-4R */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT 16:0 /* RWIUF */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ -#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ -#define NV_PFIFO_TIMESLICE 0x0000204C /* RW-4R */ -#define NV_PFIFO_TIMESLICE_TIMER 17:0 /* RWIUF */ -#define NV_PFIFO_TIMESLICE_TIMER_EXPIRED 0x0003FFFF /* RWI-V */ -#define NV_PFIFO_NEXT_CHANNEL 0x00002050 /* RW-4R */ -#define NV_PFIFO_NEXT_CHANNEL_CHID 3:0 /* RWXUF */ -#define NV_PFIFO_NEXT_CHANNEL_MODE 8:8 /* RWXVF */ -#define NV_PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 /* RW--V */ -#define NV_PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_NEXT_CHANNEL_SWITCH 12:12 /* RWIVF */ -#define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DEBUG_0 0x00002080 /* R--4R */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR0 0:0 /* R-XVF */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR1 4:4 /* R-XVF */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ -#define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */ -#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */ -#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */ -#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_DMA_PT 16:16 /* RWXVF */ -#define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PT_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PT_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ -#define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_DMA_PUSHER 12:12 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_DMA_PT 16:16 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */ -#define NV_PFIFO_RAMHT_BASE_ADDRESS 8:4 /* RWIUF */ -#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000 0x00000010 /* RWI-V */ -#define NV_PFIFO_RAMHT_SIZE 17:16 /* RWIUF */ -#define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */ -#define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */ -#define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */ -#define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */ -#define NV_PFIFO_RAMHT_SEARCH 25:24 /* RWIUF */ -#define NV_PFIFO_RAMHT_SEARCH_16 0x00000000 /* RWI-V */ -#define NV_PFIFO_RAMHT_SEARCH_32 0x00000001 /* RW--V */ -#define NV_PFIFO_RAMHT_SEARCH_64 0x00000002 /* RW--V */ -#define NV_PFIFO_RAMHT_SEARCH_128 0x00000003 /* RW--V */ -#define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */ -#define NV_PFIFO_RAMFC_BASE_ADDRESS 8:1 /* RWIUF */ -#define NV_PFIFO_RAMFC_BASE_ADDRESS_11000 0x00000088 /* RWI-V */ -#define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */ -#define NV_PFIFO_RAMRO_BASE_ADDRESS 8:1 /* RWIUF */ -#define NV_PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000089 /* RWI-V */ -#define NV_PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000090 /* RW--V */ -#define NV_PFIFO_RAMRO_SIZE 16:16 /* RWIVF */ -#define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */ -#define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHES 0x00002500 /* RW-4R */ -#define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */ -#define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHES_DMA_SUSPEND 4:4 /* R--VF */ -#define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000001 /* R---V */ -#define NV_PFIFO_MODE 0x00002504 /* RW-4R */ -#define NV_PFIFO_MODE_CHANNEL_0 0:0 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_0_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_0_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_1 1:1 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_1_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_1_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_2 2:2 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_2_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_2_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_3 3:3 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_3_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_3_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_4 4:4 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_4_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_4_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_5 5:5 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_5_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_5_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_6 6:6 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_6_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_6_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_7 7:7 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_7_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_7_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_8 8:8 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_8_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_8_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_9 9:9 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_9_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_9_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_10 10:10 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_10_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_10_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_11 11:11 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_11_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_11_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_12 12:12 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_12_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_12_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_13 13:13 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_13_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_13_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_14 14:14 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_14_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_14_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_15 15:15 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_15_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_15_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA 0x00002508 /* RW-4R */ -#define NV_PFIFO_DMA_CHANNEL_0 0:0 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_1 1:1 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_1_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_2 2:2 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_2_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_3 3:3 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_3_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_4 4:4 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_4_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_5 5:5 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_5_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_6 6:6 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_6_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_7 7:7 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_7_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_8 8:8 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_8_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_9 9:9 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_9_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_10 10:10 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_10_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_11 11:11 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_11_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_12 12:12 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_12_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_13 13:13 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_13_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_14 14:14 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_14_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_15 15:15 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_15_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE 0x0000250C /* RW-4R */ -#define NV_PFIFO_SIZE_CHANNEL_0 0:0 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_1 1:1 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_2 2:2 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_3 3:3 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_4 4:4 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_5 5:5 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_6 6:6 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_7 7:7 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_8 8:8 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_9 9:9 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_10 10:10 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_11 11:11 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_12 12:12 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_12_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_12_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_13 13:13 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_13_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_13_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_14 14:14 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_14_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_14_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_15 15:15 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_15_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_15_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */ -#define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */ -#define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */ -#define NV_PFIFO_CACHE0_PUSH1_CHID 3:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */ -#define NV_PFIFO_CACHE1_PUSH1_CHID 3:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_PUSH1_MODE 8:8 /* RWIVF */ -#define NV_PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_PUSH 0x00003220 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATE 4:4 /* R--VF */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER 8:8 /* R--VF */ -#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS 12:12 /* RWIVF */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH 0x00003224 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000003 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000004 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000005 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000006 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000007 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000008 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000009 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x0000000A /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x0000000B /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x0000000C /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x0000000D /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x0000000E /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x0000000F /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000010 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000011 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000012 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000013 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x00000014 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x00000015 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x00000016 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x00000017 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x00000018 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x00000019 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x0000001A /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x0000001B /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x0000001C /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x0000001D /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x0000001E /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x0000001F /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 15:13 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00000003 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00000004 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x00000005 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x00000006 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x00000007 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 19:16 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00000003 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00000004 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00000005 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00000006 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00000007 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00000008 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00000009 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x0000000A /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x0000000B /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x0000000C /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x0000000D /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x0000000E /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x0000000F /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_PUT 0x00003240 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_PUT_OFFSET 28:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_GET 0x00003244 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_GET_OFFSET 28:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_STATE 0x00003228 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_STATE_METHOD 12:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 15:13 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 28:18 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR 31:30 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x00000003 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000322C /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 15:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL 0x00003230 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12:12 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13:13 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 17:16 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00000003 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO 31:31 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x00000001 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_LIMIT 0x00003234 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_LIMIT_OFFSET 28:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0:0 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ -#define NV_PFIFO_CACHE0_PULL0 0x00003050 /* RW-4R */ -#define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_PULL0_HASH 4:4 /* R-XVF */ -#define NV_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_DEVICE 8:8 /* R-XVF */ -#define NV_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_HASH_STATE 12:12 /* R-XVF */ -#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0 0x00003250 /* RW-4R */ -#define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_PULL0_HASH 4:4 /* R-XVF */ -#define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_DEVICE 8:8 /* R-XVF */ -#define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_HASH_STATE 12:12 /* R-XVF */ -#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_PULL1 0x00003054 /* RW-4R */ -#define NV_PFIFO_CACHE0_PULL1_ENGINE 1:0 /* RWXUF */ -#define NV_PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_PULL1 0x00003254 /* RW-4R */ -#define NV_PFIFO_CACHE1_PULL1_ENGINE 1:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_HASH 0x00003058 /* RW-4R */ -#define NV_PFIFO_CACHE0_HASH_INSTANCE 15:0 /* RWXUF */ -#define NV_PFIFO_CACHE0_HASH_VALID 16:16 /* RWXVF */ -#define NV_PFIFO_CACHE1_HASH 0x00003258 /* RW-4R */ -#define NV_PFIFO_CACHE1_HASH_INSTANCE 15:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_HASH_VALID 16:16 /* RWXVF */ -#define NV_PFIFO_CACHE0_STATUS 0x00003014 /* R--4R */ -#define NV_PFIFO_CACHE0_STATUS_LOW_MARK 4:4 /* R--VF */ -#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK 8:8 /* R--VF */ -#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS 0x00003214 /* R--4R */ -#define NV_PFIFO_CACHE1_STATUS_LOW_MARK 4:4 /* R--VF */ -#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK 8:8 /* R--VF */ -#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS1 0x00003218 /* R--4R */ -#define NV_PFIFO_CACHE1_STATUS1_RANOUT 0:0 /* R-XVF */ -#define NV_PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_PUT 0x00003010 /* RW-4R */ -#define NV_PFIFO_CACHE0_PUT_ADDRESS 2:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */ -#define NV_PFIFO_CACHE1_PUT_ADDRESS 9:2 /* RWXUF */ -#define NV_PFIFO_CACHE0_GET 0x00003070 /* RW-4R */ -#define NV_PFIFO_CACHE0_GET_ADDRESS 2:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */ -#define NV_PFIFO_CACHE1_GET_ADDRESS 9:2 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE 0x00003080 /* RW-4R */ -#define NV_PFIFO_CACHE0_ENGINE_0 1:0 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_0_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_1 5:4 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_1_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_1_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_2 9:8 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_2_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_2_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_3 13:12 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_3_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_3_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_4 17:16 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_4_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_4_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_5 21:20 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_5_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_5_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_6 25:24 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_6_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_6_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_7 29:28 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_7_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_7_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE 0x00003280 /* RW-4R */ -#define NV_PFIFO_CACHE1_ENGINE_0 1:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_0_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_1 5:4 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_1_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_1_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_2 9:8 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_2_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_2_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_3 13:12 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_3_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_3_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_4 17:16 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_4_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_4_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_5 21:20 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_5_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_5_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_6 25:24 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_6_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_6_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_7 29:28 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_7_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_7_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_METHOD(i) (0x00003100+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE0_METHOD__SIZE_1 1 /* */ -#define NV_PFIFO_CACHE0_METHOD_ADDRESS 12:2 /* RWXUF */ -#define NV_PFIFO_CACHE0_METHOD_SUBCHANNEL 15:13 /* RWXUF */ -#define NV_PFIFO_CACHE1_METHOD(i) (0x00003800+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE1_METHOD__SIZE_1 128 /* */ -#define NV_PFIFO_CACHE1_METHOD_ADDRESS 12:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL 15:13 /* RWXUF */ -#define NV_PFIFO_CACHE1_METHOD_ALIAS(i) (0x00003C00+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE1_METHOD_ALIAS__SIZE_1 128 /* */ -#define NV_PFIFO_CACHE0_DATA(i) (0x00003104+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE0_DATA__SIZE_1 1 /* */ -#define NV_PFIFO_CACHE0_DATA_VALUE 31:0 /* RWXVF */ -#define NV_PFIFO_CACHE1_DATA(i) (0x00003804+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE1_DATA__SIZE_1 128 /* */ -#define NV_PFIFO_CACHE1_DATA_VALUE 31:0 /* RWXVF */ -#define NV_PFIFO_CACHE1_DATA_ALIAS(i) (0x00003C04+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE1_DATA_ALIAS__SIZE_1 128 /* */ -#define NV_PFIFO_DEVICE(i) (0x00002800+(i)*4) /* R--4A */ -#define NV_PFIFO_DEVICE__SIZE_1 128 /* */ -#define NV_PFIFO_DEVICE_CHID 3:0 /* R--UF */ -#define NV_PFIFO_DEVICE_SWITCH 24:24 /* R--VF */ -#define NV_PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 /* R---V */ -#define NV_PFIFO_DEVICE_SWITCH_AVAILABLE 0x00000001 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */ -#define NV_PFIFO_RUNOUT_STATUS_RANOUT 0:0 /* R--VF */ -#define NV_PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK 4:4 /* R--VF */ -#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK 8:8 /* R--VF */ -#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ -#define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */ -#define NV_PFIFO_RUNOUT_PUT_ADDRESS 12:3 /* RWXUF */ -#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_0 8:3 /* RWXUF */ -#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_1 12:3 /* RWXUF */ -#define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */ -#define NV_PFIFO_RUNOUT_GET_ADDRESS 13:3 /* RWXUF */ -/* dev_graphics.ref */ -#define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */ -#define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */ -#define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */ -#define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */ -#define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */ -#define NV_PGRAPH_INTR 0x00400100 /* RW-4R */ -#define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWIVF */ -#define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_NOTIFY_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_NOTIFY_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_MISSING_HW 4:4 /* RWIVF */ -#define NV_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_MISSING_HW_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_MISSING_HW_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_TLB_PRESENT_A 8:8 /* RWIVF */ -#define NV_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_TLB_PRESENT_B 9:9 /* RWIVF */ -#define NV_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_CONTEXT_SWITCH 12:12 /* RWIVF */ -#define NV_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWIVF */ -#define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_NSTATUS 0x00400104 /* RW-4R */ -#define NV_PGRAPH_NSTATUS_STATE_IN_USE 11:11 /* RWIVF */ -#define NV_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NSTATUS_INVALID_STATE 12:12 /* RWIVF */ -#define NV_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT 13:13 /* RWIVF */ -#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT 14:14 /* RWIVF */ -#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NSOURCE 0x00400108 /* R--4R */ -#define NV_PGRAPH_NSOURCE_NOTIFICATION 0:0 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_DATA_ERROR 1:1 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR 2:2 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION 3:3 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_LIMIT_COLOR 4:4 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_ 5:5 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD 6:6 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION 7:7 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION 8:8 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9:9 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION 10:10 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_STATE_INVALID 11:11 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12:12 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE 13:13 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_METHOD_CNT 14:14 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION 15:15 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_EN 0x00400140 /* RW-4R */ -#define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_MISSING_HW 4:4 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_MISSING_HW_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A 8:8 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B 9:9 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH 12:12 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1 0x00400160 /* RW-4R */ -#define NV_PGRAPH_CTX_SWITCH1_GRCLASS 7:0 /* RWXVF */ -#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12:12 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP 13:13 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE 14:14 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x00000002 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x00000003 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x00000004 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x00000005 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24:24 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25:25 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31:31 /* CWIVF */ -#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x00000000 /* CWI-V */ -#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x00000001 /* -W--T */ -#define NV_PGRAPH_CTX_SWITCH2 0x00400164 /* RW-4R */ -#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT 1:0 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 31:16 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x0000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH3 0x00400168 /* RW-4R */ -#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 15:0 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x0000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 31:16 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x0000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH4 0x0040016C /* RW-4R */ -#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE 15:0 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x0000 /* RW--V */ -#define NV_PGRAPH_CTX_CACHE1(i) (0x00400180+(i)*4) /* RW-4A */ -#define NV_PGRAPH_CTX_CACHE1__SIZE_1 8 /* */ -#define NV_PGRAPH_CTX_CACHE1_GRCLASS 7:0 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_CHROMA_KEY 12:12 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_USER_CLIP 13:13 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_SWIZZLE 14:14 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_SPARE1 20:20 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_PATCH_STATUS 24:24 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25:25 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE2(i) (0x004001a0+(i)*4) /* RW-4A */ -#define NV_PGRAPH_CTX_CACHE2__SIZE_1 8 /* */ -#define NV_PGRAPH_CTX_CACHE2_MONO_FORMAT 1:0 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 31:16 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE3(i) (0x004001c0+(i)*4) /* RW-4A */ -#define NV_PGRAPH_CTX_CACHE3__SIZE_1 8 /* */ -#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 15:0 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 31:16 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE4(i) (0x004001e0+(i)*4) /* RW-4A */ -#define NV_PGRAPH_CTX_CACHE4__SIZE_1 8 /* */ -#define NV_PGRAPH_CTX_CACHE4_USER_INSTANCE 15:0 /* RWXVF */ -#define NV_PGRAPH_CTX_CONTROL 0x00400170 /* RW-4R */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_CHANGE 20:20 /* R--VF */ -#define NV_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x00000000 /* R---V */ -#define NV_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x00000001 /* R---V */ -#define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_USER 0x00400174 /* RW-4R */ -#define NV_PGRAPH_CTX_USER_SUBCH 15:13 /* RWIVF */ -#define NV_PGRAPH_CTX_USER_SUBCH_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_USER_CHID 27:24 /* RWIVF */ -#define NV_PGRAPH_CTX_USER_CHID_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FIFO 0x00400720 /* RW-4R */ -#define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */ -#define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */ -#define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_FIFO_0(i) (0x00400730+(i)*4) /* RW-4A */ -#define NV_PGRAPH_FFINTFC_FIFO_0__SIZE_1 4 /* */ -#define NV_PGRAPH_FFINTFC_FIFO_0_TAG 0:0 /* RWXVF */ -#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x00000000 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH 3:1 /* RWXVF */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_1 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_2 0x00000002 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_3 0x00000003 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_4 0x00000004 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_5 0x00000005 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_6 0x00000006 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_7 0x00000007 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD 14:4 /* RWXVF */ -#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x00000000 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_1(i) (0x00400740+(i)*4) /* RW-4A */ -#define NV_PGRAPH_FFINTFC_FIFO_1__SIZE_1 4 /* */ -#define NV_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 31:0 /* RWXVF */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR 0x00400750 /* RW-4R */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE 2:0 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ 6:4 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2 0x00400754 /* RW-4R */ -#define NV_PGRAPH_FFINTFC_ST2_STATUS 0:0 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_MTHD 11:1 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH 14:12 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_1 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_2 0x00000002 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_3 0x00000003 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_4 0x00000004 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_5 0x00000005 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_6 0x00000006 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_7 0x00000007 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID 18:15 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_1 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_2 0x00000002 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_3 0x00000003 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_4 0x00000004 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_5 0x00000005 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_6 0x00000006 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_7 0x00000007 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_8 0x00000008 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_9 0x00000009 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_10 0x0000000A /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_11 0x0000000B /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_12 0x0000000C /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_13 0x0000000D /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_14 0x0000000E /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_15 0x0000000F /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS 19:19 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_D 0x00400758 /* RW-4R */ -#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT 31:0 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATUS 0x00400700 /* R--4R */ -#define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */ -#define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_XY_LOGIC 4:4 /* R-IVF */ -#define NV_PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_FE 5:5 /* R-IVF */ -#define NV_PGRAPH_STATUS_FE_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_FE_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_RASTERIZER 6:6 /* R-IVF */ -#define NV_PGRAPH_STATUS_RASTERIZER_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_RASTERIZER_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PORT_NOTIFY 8:8 /* R-IVF */ -#define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PORT_REGISTER 12:12 /* R-IVF */ -#define NV_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PORT_DMA 16:16 /* R-IVF */ -#define NV_PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PORT_DMA_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_DMA_ENGINE 17:17 /* R-IVF */ -#define NV_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_DMA_NOTIFY 20:20 /* R-IVF */ -#define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21:21 /* R-IVF */ -#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_D3D 24:24 /* R-IVF */ -#define NV_PGRAPH_STATUS_D3D_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_D3D_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_CACHE 25:25 /* R-IVF */ -#define NV_PGRAPH_STATUS_CACHE_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_CACHE_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_LIGHTING 26:26 /* R-IVF */ -#define NV_PGRAPH_STATUS_LIGHTING_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_LIGHTING_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PREROP 27:27 /* R-IVF */ -#define NV_PGRAPH_STATUS_PREROP_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PREROP_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_ROP 28:28 /* R-IVF */ -#define NV_PGRAPH_STATUS_ROP_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_ROP_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PORT_USER 29:29 /* R-IVF */ -#define NV_PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PORT_USER_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */ -#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 /* R-XUF */ -#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 15:13 /* R-XUF */ -#define NV_PGRAPH_TRAPPED_ADDR_CHID 27:24 /* R-XUF */ -#define NV_PGRAPH_TRAPPED_DATA 0x00400708 /* R--4R */ -#define NV_PGRAPH_TRAPPED_DATA_VALUE 31:0 /* R-XVF */ -#define NV_PGRAPH_SURFACE 0x0040070C /* RW-4R */ -#define NV_PGRAPH_SURFACE_TYPE 1:0 /* RWIVF */ -#define NV_PGRAPH_SURFACE_TYPE_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_SURFACE_TYPE_SWIZZLE 0x00000002 /* RW--V */ -#define NV_PGRAPH_NOTIFY 0x00400714 /* RW-4R */ -#define NV_PGRAPH_NOTIFY_BUFFER_REQ 0:0 /* RWIVF */ -#define NV_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NOTIFY_BUFFER_STYLE 8:8 /* RWIVF */ -#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ -#define NV_PGRAPH_NOTIFY_REQ 16:16 /* RWIVF */ -#define NV_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NOTIFY_REQ_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NOTIFY_STYLE 20:20 /* RWIVF */ -#define NV_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ -#define NV_PGRAPH_BOFFSET(i) (0x00400640+(i)*4) /* RW-4A */ -#define NV_PGRAPH_BOFFSET__SIZE_1 6 /* */ -#define NV_PGRAPH_BOFFSET_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET0 0x00400640 /* RW-4R */ -#define NV_PGRAPH_BOFFSET0__ALIAS_1 NV_PGRAPH_BOFFSET(0) /* */ -#define NV_PGRAPH_BOFFSET0_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET0_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET1 0x00400644 /* RW-4R */ -#define NV_PGRAPH_BOFFSET1__ALIAS_1 NV_PGRAPH_BOFFSET(1) /* */ -#define NV_PGRAPH_BOFFSET1_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET1_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET2 0x00400648 /* RW-4R */ -#define NV_PGRAPH_BOFFSET2__ALIAS_1 NV_PGRAPH_BOFFSET(2) /* */ -#define NV_PGRAPH_BOFFSET2_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET2_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET3 0x0040064C /* RW-4R */ -#define NV_PGRAPH_BOFFSET3__ALIAS_1 NV_PGRAPH_BOFFSET(3) /* */ -#define NV_PGRAPH_BOFFSET3_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET3_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET4 0x00400650 /* RW-4R */ -#define NV_PGRAPH_BOFFSET4__ALIAS_1 NV_PGRAPH_BOFFSET(4) /* */ -#define NV_PGRAPH_BOFFSET4_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET4_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET5 0x00400654 /* RW-4R */ -#define NV_PGRAPH_BOFFSET5__ALIAS_1 NV_PGRAPH_BOFFSET(5) /* */ -#define NV_PGRAPH_BOFFSET5_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET5_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE(i) (0x00400658+(i)*4) /* RW-4A */ -#define NV_PGRAPH_BBASE__SIZE_1 6 /* */ -#define NV_PGRAPH_BBASE_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE0 0x00400658 /* RW-4R */ -#define NV_PGRAPH_BBASE0__ALIAS_1 NV_PGRAPH_BBASE(0) /* */ -#define NV_PGRAPH_BBASE0_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE0_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE1 0x0040065c /* RW-4R */ -#define NV_PGRAPH_BBASE1__ALIAS_1 NV_PGRAPH_BBASE(1) /* */ -#define NV_PGRAPH_BBASE1_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE1_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE2 0x00400660 /* RW-4R */ -#define NV_PGRAPH_BBASE2__ALIAS_1 NV_PGRAPH_BBASE(2) /* */ -#define NV_PGRAPH_BBASE2_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE2_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE3 0x00400664 /* RW-4R */ -#define NV_PGRAPH_BBASE3__ALIAS_1 NV_PGRAPH_BBASE(3) /* */ -#define NV_PGRAPH_BBASE3_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE3_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE4 0x00400668 /* RW-4R */ -#define NV_PGRAPH_BBASE4__ALIAS_1 NV_PGRAPH_BBASE(4) /* */ -#define NV_PGRAPH_BBASE4_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE4_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE5 0x0040066C /* RW-4R */ -#define NV_PGRAPH_BBASE5__ALIAS_1 NV_PGRAPH_BBASE(5) /* */ -#define NV_PGRAPH_BBASE5_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE5_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH(i) (0x00400670+(i)*4) /* RW-4A */ -#define NV_PGRAPH_BPITCH__SIZE_1 5 /* */ -#define NV_PGRAPH_BPITCH_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH0 0x00400670 /* RW-4R */ -#define NV_PGRAPH_BPITCH0__ALIAS_1 NV_PGRAPH_BPITCH(0) /* */ -#define NV_PGRAPH_BPITCH0_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH0_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH1 0x00400674 /* RW-4R */ -#define NV_PGRAPH_BPITCH1__ALIAS_1 NV_PGRAPH_BPITCH(1) /* */ -#define NV_PGRAPH_BPITCH1_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH1_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH2 0x00400678 /* RW-4R */ -#define NV_PGRAPH_BPITCH2__ALIAS_1 NV_PGRAPH_BPITCH(2) /* */ -#define NV_PGRAPH_BPITCH2_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH2_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH3 0x0040067C /* RW-4R */ -#define NV_PGRAPH_BPITCH3__ALIAS_1 NV_PGRAPH_BPITCH(3) /* */ -#define NV_PGRAPH_BPITCH3_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH3_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH4 0x00400680 /* RW-4R */ -#define NV_PGRAPH_BPITCH4__ALIAS_1 NV_PGRAPH_BPITCH(4) /* */ -#define NV_PGRAPH_BPITCH4_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH4_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BLIMIT(i) (0x00400684+(i)*4) /* RW-4A */ -#define NV_PGRAPH_BLIMIT__SIZE_1 6 /* */ -#define NV_PGRAPH_BLIMIT_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT0 0x00400684 /* RW-4R */ -#define NV_PGRAPH_BLIMIT0__ALIAS_1 NV_PGRAPH_BLIMIT(0) /* */ -#define NV_PGRAPH_BLIMIT0_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT0_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT0_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT0_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT1 0x00400688 /* RW-4R */ -#define NV_PGRAPH_BLIMIT1__ALIAS_1 NV_PGRAPH_BLIMIT(1) /* */ -#define NV_PGRAPH_BLIMIT1_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT1_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT1_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT1_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT2 0x0040068c /* RW-4R */ -#define NV_PGRAPH_BLIMIT2__ALIAS_1 NV_PGRAPH_BLIMIT(2) /* */ -#define NV_PGRAPH_BLIMIT2_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT2_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT2_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT2_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT3 0x00400690 /* RW-4R */ -#define NV_PGRAPH_BLIMIT3__ALIAS_1 NV_PGRAPH_BLIMIT(3) /* */ -#define NV_PGRAPH_BLIMIT3_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT3_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT3_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT3_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT4 0x00400694 /* RW-4R */ -#define NV_PGRAPH_BLIMIT4__ALIAS_1 NV_PGRAPH_BLIMIT(4) /* */ -#define NV_PGRAPH_BLIMIT4_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT4_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT4_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT4_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT5 0x00400698 /* RW-4R */ -#define NV_PGRAPH_BLIMIT5__ALIAS_1 NV_PGRAPH_BLIMIT(5) /* */ -#define NV_PGRAPH_BLIMIT5_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT5_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT5_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT5_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BSWIZZLE2 0x0040069c /* RW-4R */ -#define NV_PGRAPH_BSWIZZLE2_WIDTH 19:16 /* RWIUF */ -#define NV_PGRAPH_BSWIZZLE2_WIDTH_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BSWIZZLE2_HEIGHT 27:24 /* RWIUF */ -#define NV_PGRAPH_BSWIZZLE2_HEIGHT_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BSWIZZLE5 0x004006a0 /* RW-4R */ -#define NV_PGRAPH_BSWIZZLE5_WIDTH 19:16 /* RWIUF */ -#define NV_PGRAPH_BSWIZZLE5_WIDTH_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BSWIZZLE5_HEIGHT 27:24 /* RWIUF */ -#define NV_PGRAPH_BSWIZZLE5_HEIGHT_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL 0x00400724 /* RW-4R */ -#define NV_PGRAPH_BPIXEL_DEPTH0 3:0 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1 7:4 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2 11:8 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH2_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3 15:12 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH3_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4 19:16 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH4_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5 23:20 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH5_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 /* RW-4R */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS 23:0 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT 29:29 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30:30 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31:31 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_Z 0x00400614 /* RW-4R */ -#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS 23:0 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT 30:30 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31:31 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE 0x00400710 /* RW-4R */ -#define NV_PGRAPH_STATE_BUFFER_0 0:0 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_0_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_1 1:1 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_1_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_2 2:2 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_2_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_2_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_3 3:3 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_3_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_3_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_4 4:4 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_4_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_4_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_5 5:5 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_5_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_5_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_0 8:8 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_0_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_1 9:9 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_1_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_2 10:10 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_2_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_2_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_3 11:11 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_3_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_3_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_4 12:12 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_4_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_4_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CHROMA_COLOR 16:16 /* RWIVF */ -#define NV_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CHROMA_COLOR_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CHROMA_COLORFMT 17:17 /* RWIVF */ -#define NV_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CPATTERN_COLORFMT 20:20 /* RWIVF */ -#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CPATTERN_MONOFMT 21:21 /* RWIVF */ -#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CPATTERN_SELECT 22:22 /* RWIVF */ -#define NV_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PATTERN_COLOR0 24:24 /* RWIVF */ -#define NV_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PATTERN_COLOR1 25:25 /* RWIVF */ -#define NV_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PATTERN_PATT0 26:26 /* RWIVF */ -#define NV_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PATTERN_PATT0_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PATTERN_PATT1 27:27 /* RWIVF */ -#define NV_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PATTERN_PATT1_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX 0x00400728 /* RW-4R */ -#define NV_PGRAPH_CACHE_INDEX_BANK 2:2 /* RWXVF */ -#define NV_PGRAPH_CACHE_INDEX_BANK_10 0x00000000 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_BANK_32 0x00000001 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_ADRS 12:3 /* RWXVF */ -#define NV_PGRAPH_CACHE_INDEX_ADRS_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_ADRS_1024 0x00000400 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_OP 14:13 /* RWXVF */ -#define NV_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x00000000 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x00000001 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x00000002 /* RW--V */ -#define NV_PGRAPH_CACHE_RAM 0x0040072c /* RW-4R */ -#define NV_PGRAPH_CACHE_RAM_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DMA_PITCH 0x00400760 /* RW-4R */ -#define NV_PGRAPH_DMA_PITCH_S0 15:0 /* RWXSF */ -#define NV_PGRAPH_DMA_PITCH_S1 31:16 /* RWXSF */ -#define NV_PGRAPH_DVD_COLORFMT 0x00400764 /* RW-4R */ -#define NV_PGRAPH_DVD_COLORFMT_IMAGE 5:0 /* RWNVF */ -#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 /* RWN-V */ -#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ -#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY 9:8 /* RWNVF */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 /* RWN-V */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 /* RW--V */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 /* RW--V */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 /* RW--V */ -#define NV_PGRAPH_SCALED_FORMAT 0x00400768 /* RW-4R */ -#define NV_PGRAPH_SCALED_FORMAT_ORIGIN 17:16 /* RWIVF */ -#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x00000001 /* RW--V */ -#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x00000002 /* RW--V */ -#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24:24 /* RWIVF */ -#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* RWI-V */ -#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x00000001 /* RW--V */ -#define NV_PGRAPH_PATT_COLOR0 0x00400800 /* RW-4R */ -#define NV_PGRAPH_PATT_COLOR0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_PATT_COLOR1 0x00400804 /* RW-4R */ -#define NV_PGRAPH_PATT_COLOR1_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_PATT_COLORRAM(i) (0x00400900+(i)*4) /* R--4A */ -#define NV_PGRAPH_PATT_COLORRAM__SIZE_1 64 /* */ -#define NV_PGRAPH_PATT_COLORRAM_VALUE 23:0 /* R--UF */ -#define NV_PGRAPH_PATTERN(i) (0x00400808+(i)*4) /* RW-4A */ -#define NV_PGRAPH_PATTERN__SIZE_1 2 /* */ -#define NV_PGRAPH_PATTERN_BITMAP 31:0 /* RWXVF */ -#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 /* RW-4R */ -#define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */ -#define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x00000000 /* RW--V */ -#define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x00000001 /* RW--V */ -#define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x00000002 /* RW--V */ -#define NV_PGRAPH_PATTERN_SHAPE_SELECT 4:4 /* RWXVF */ -#define NV_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x00000000 /* RW--V */ -#define NV_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x00000001 /* RW--V */ -#define NV_PGRAPH_MONO_COLOR0 0x00400600 /* RW-4R */ -#define NV_PGRAPH_MONO_COLOR0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_ROP3 0x00400604 /* RW-4R */ -#define NV_PGRAPH_ROP3_VALUE 7:0 /* RWXVF */ -#define NV_PGRAPH_CHROMA 0x00400814 /* RW-4R */ -#define NV_PGRAPH_CHROMA_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_BETA_AND 0x00400608 /* RW-4R */ -#define NV_PGRAPH_BETA_AND_VALUE_FRACTION 30:23 /* RWXUF */ -#define NV_PGRAPH_BETA_PREMULT 0x0040060c /* RW-4R */ -#define NV_PGRAPH_BETA_PREMULT_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_CONTROL0 0x00400818 /* RW-4R */ -#define NV_PGRAPH_CONTROL1 0x0040081c /* RW-4R */ -#define NV_PGRAPH_CONTROL2 0x00400820 /* RW-4R */ -#define NV_PGRAPH_BLEND 0x00400824 /* RW-4R */ -#define NV_PGRAPH_DPRAM_INDEX 0x00400828 /* RW-4R */ -#define NV_PGRAPH_DPRAM_INDEX_ADRS 6:0 /* RWIVF */ -#define NV_PGRAPH_DPRAM_INDEX_ADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT 10:8 /* RWIVF */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x00000001 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x00000002 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x00000003 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x00000004 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x00000005 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x00000006 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x00000007 /* RW--V */ -#define NV_PGRAPH_DPRAM_DATA 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_DATA_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_ADRS_0 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_ADRS_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_ADRS_0_VALUE 19:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_ADRS_1 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_ADRS_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_ADRS_1_VALUE 19:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_DATA_0 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_DATA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_DATA_0_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_DATA_1 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_DATA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_DATA_1_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_WE_0 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_WE_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_WE_0_VALUE 23:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_WE_1 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_WE_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_WE_1_VALUE 23:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_ALPHA_0 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_ALPHA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_ALPHA_0_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_ALPHA_1 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_ALPHA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_ALPHA_1_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_STORED_FMT 0x00400830 /* RW-4R */ -#define NV_PGRAPH_STORED_FMT_MONO0 5:0 /* RWXVF */ -#define NV_PGRAPH_STORED_FMT_PATT0 13:8 /* RWXVF */ -#define NV_PGRAPH_STORED_FMT_PATT1 21:16 /* RWXVF */ -#define NV_PGRAPH_STORED_FMT_CHROMA 29:24 /* RWXVF */ -#define NV_PGRAPH_FORMATS 0x00400618 /* RW-4R */ -#define NV_PGRAPH_FORMATS_ROP 2:0 /* R-XVF */ -#define NV_PGRAPH_FORMATS_ROP_Y8 0x00000000 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_RGB15 0x00000001 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_RGB16 0x00000002 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_Y16 0x00000003 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_INVALID 0x00000004 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_RGB24 0x00000005 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_RGB30 0x00000006 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_Y32 0x00000007 /* -W--V */ -#define NV_PGRAPH_FORMATS_SRC 9:4 /* R-XVF */ -#define NV_PGRAPH_FORMATS_SRC_INVALID 0x00000000 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x00000002 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X24Y8 0x00000003 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x00000006 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x00000007 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x00000008 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x00000009 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_R5G6B5 0x0000000A /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0x0000000B /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0x0000000C /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0x0000000D /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0x0000000E /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_Y16 0x0000000F /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_A16Y16 0x00000010 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X16Y16 0x00000011 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x00000012 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x00000013 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_Y32 0x00000014 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB 15:12 /* R-XVF */ -#define NV_PGRAPH_FORMATS_FB_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FORMATS_FB_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */ -#define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */ -#define NV_PGRAPH_ABS_X_RAM_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_X_RAM_BPORT(i) (0x00400c00+(i)*4) /* R--4A */ -#define NV_PGRAPH_X_RAM_BPORT__SIZE_1 32 /* */ -#define NV_PGRAPH_X_RAM_BPORT_VALUE 31:0 /* R--UF */ -#define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */ -#define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */ -#define NV_PGRAPH_ABS_Y_RAM_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_Y_RAM_BPORT(i) (0x00400c80+(i)*4) /* R--4A */ -#define NV_PGRAPH_Y_RAM_BPORT__SIZE_1 32 /* */ -#define NV_PGRAPH_Y_RAM_BPORT_VALUE 31:0 /* R--UF */ -#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */ -#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER 17:0 /* RWBUF */ -#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x00000000 /* RWB-V */ -#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20:20 /* RWVVF */ -#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x00000000 /* RWV-V */ -#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX 31:28 /* RWBUF */ -#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x00000000 /* RWB-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */ -#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL 0:0 /* RWNVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x00000000 /* RWN-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4:4 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5:5 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12:12 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16:16 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20:20 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */ -#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0:0 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4:4 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5:5 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12:12 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16:16 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20:20 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */ -#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0:0 /* RWXVF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x00000000 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4:4 /* RWXVF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x00000000 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8:8 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12:12 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 22:16 /* RWXUF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 30:24 /* RWXUF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */ -#define NV_PGRAPH_X_MISC_BIT33_0 0:0 /* RWNVF */ -#define NV_PGRAPH_X_MISC_BIT33_0_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_BIT33_1 1:1 /* RWNVF */ -#define NV_PGRAPH_X_MISC_BIT33_1_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_BIT33_2 2:2 /* RWNVF */ -#define NV_PGRAPH_X_MISC_BIT33_2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_BIT33_3 3:3 /* RWNVF */ -#define NV_PGRAPH_X_MISC_BIT33_3_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_RANGE_0 4:4 /* RWNVF */ -#define NV_PGRAPH_X_MISC_RANGE_0_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_RANGE_1 5:5 /* RWNVF */ -#define NV_PGRAPH_X_MISC_RANGE_1_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_RANGE_2 6:6 /* RWNVF */ -#define NV_PGRAPH_X_MISC_RANGE_2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_RANGE_3 7:7 /* RWNVF */ -#define NV_PGRAPH_X_MISC_RANGE_3_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ -#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ -#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ -#define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */ -#define NV_PGRAPH_Y_MISC_BIT33_0 0:0 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_BIT33_0_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_BIT33_1 1:1 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_BIT33_1_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_BIT33_2 2:2 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_BIT33_2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_BIT33_3 3:3 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_BIT33_3_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_RANGE_0 4:4 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_RANGE_0_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_RANGE_1 5:5 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_RANGE_1_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_RANGE_2 6:6 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_RANGE_2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_RANGE_3 7:7 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_RANGE_3_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ -#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ -#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ -#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE 15:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE 15:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE 15:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE 15:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */ -#define NV_PGRAPH_SOURCE_COLOR_VALUE 31:0 /* RWNVF */ -#define NV_PGRAPH_SOURCE_COLOR_VALUE_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_VALID1 0x00400508 /* RW-4R */ -#define NV_PGRAPH_VALID1_VLD 22:0 /* RWNVF */ -#define NV_PGRAPH_VALID1_VLD_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_VALID1_CLIP_MIN 28:28 /* RWIVF */ -#define NV_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x00000000 /* RWI-V */ -#define NV_PGRAPH_VALID1_CLIP_MIN_ONLY 0x00000001 /* RW--V */ -#define NV_PGRAPH_VALID1_CLIPA_MIN 29:29 /* RWIVF */ -#define NV_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x00000000 /* RWI-V */ -#define NV_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x00000001 /* RW--V */ -#define NV_PGRAPH_VALID1_CLIP_MAX 30:30 /* RWIVF */ -#define NV_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x00000000 /* RWI-V */ -#define NV_PGRAPH_VALID1_CLIP_MAX_ONLY 0x00000001 /* RW--V */ -#define NV_PGRAPH_VALID1_CLIPA_MAX 31:31 /* RWIVF */ -#define NV_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x00000000 /* RWI-V */ -#define NV_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x00000001 /* RW--V */ -#define NV_PGRAPH_VALID2 0x00400578 /* RW-4R */ -#define NV_PGRAPH_VALID2_VLD2 28:0 /* RWNVF */ -#define NV_PGRAPH_VALID2_VLD2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */ -#define NV_PGRAPH_ABS_ICLIP_XMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */ -#define NV_PGRAPH_ABS_ICLIP_YMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MIN 1:0 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MAX 3:2 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MIN 5:4 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MAX 7:6 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MIN 9:8 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MAX 11:10 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MIN 13:12 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MAX 15:14 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MIN 17:16 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MAX 19:18 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MIN 21:20 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MAX 23:22 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MIN 25:24 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MAX 27:26 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MIN 29:28 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MAX 31:30 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MIN 1:0 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MAX 3:2 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MIN 5:4 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MAX 7:6 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MIN 9:8 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MAX 11:10 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MIN 13:12 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MAX 15:14 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MIN 17:16 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MAX 19:18 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MIN 21:20 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MAX 23:22 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MIN 25:24 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MAX 27:26 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MIN 29:28 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MAX 31:30 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MIN 1:0 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MAX 3:2 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MIN 5:4 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MAX 7:6 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MIN 9:8 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MAX 11:10 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MIN 13:12 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MAX 15:14 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MIN 17:16 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MAX 19:18 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MIN 21:20 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MAX 23:22 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MIN 25:24 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MAX 27:26 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MIN 29:28 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MAX 31:30 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MIN 1:0 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MAX 3:2 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MIN 5:4 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MAX 7:6 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MIN 9:8 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MAX 11:10 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MIN 13:12 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MAX 15:14 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MIN 17:16 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MAX 19:18 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MIN 21:20 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MAX 23:22 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MIN 25:24 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MAX 27:26 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MIN 29:28 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MAX 31:30 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_MISC24_0 0x00400510 /* RW-4R */ -#define NV_PGRAPH_MISC24_0_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_MISC24_1 0x00400570 /* RW-4R */ -#define NV_PGRAPH_MISC24_1_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_MISC24_2 0x00400574 /* RW-4R */ -#define NV_PGRAPH_MISC24_2_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_PASSTHRU_0 0x0040057C /* RW-4R */ -#define NV_PGRAPH_PASSTHRU_0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_PASSTHRU_1 0x00400580 /* RW-4R */ -#define NV_PGRAPH_PASSTHRU_1_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_PASSTHRU_2 0x00400584 /* RW-4R */ -#define NV_PGRAPH_PASSTHRU_2_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_U_RAM(i) (0x00400d00+(i)*4) /* RW-4A */ -#define NV_PGRAPH_U_RAM__SIZE_1 16 /* */ -#define NV_PGRAPH_U_RAM_VALUE 31:6 /* RWXFF */ -#define NV_PGRAPH_V_RAM(i) (0x00400d40+(i)*4) /* RW-4A */ -#define NV_PGRAPH_V_RAM__SIZE_1 16 /* */ -#define NV_PGRAPH_V_RAM_VALUE 31:6 /* RWXFF */ -#define NV_PGRAPH_M_RAM(i) (0x00400d80+(i)*4) /* RW-4A */ -#define NV_PGRAPH_M_RAM__SIZE_1 16 /* */ -#define NV_PGRAPH_M_RAM_VALUE 31:6 /* RWXFF */ -#define NV_PGRAPH_DMA_START_0 0x00401000 /* RW-4R */ -#define NV_PGRAPH_DMA_START_0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_START_1 0x00401004 /* RW-4R */ -#define NV_PGRAPH_DMA_START_1_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_LENGTH 0x00401008 /* RW-4R */ -#define NV_PGRAPH_DMA_LENGTH_VALUE 21:0 /* RWXUF */ -#define NV_PGRAPH_DMA_MISC 0x0040100C /* RW-4R */ -#define NV_PGRAPH_DMA_MISC_COUNT 15:0 /* RWXUF */ -#define NV_PGRAPH_DMA_MISC_FMT_SRC 18:16 /* RWXVF */ -#define NV_PGRAPH_DMA_MISC_FMT_DST 22:20 /* RWXVF */ -#define NV_PGRAPH_DMA_DATA_0 0x00401020 /* RW-4R */ -#define NV_PGRAPH_DMA_DATA_0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_DATA_1 0x00401024 /* RW-4R */ -#define NV_PGRAPH_DMA_DATA_1_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_RM 0x00401030 /* RW-4R */ -#define NV_PGRAPH_DMA_RM_ASSIST_A 0:0 /* RWIVF */ -#define NV_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_DMA_RM_ASSIST_A_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_DMA_RM_ASSIST_B 1:1 /* RWIVF */ -#define NV_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_DMA_RM_ASSIST_B_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_DMA_RM_WRITE_REQ 4:4 /* CWIVF */ -#define NV_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x00000000 /* CWI-V */ -#define NV_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x00000001 /* -W--T */ -#define NV_PGRAPH_DMA_A_XLATE_INST 0x00401040 /* RW-4R */ -#define NV_PGRAPH_DMA_A_XLATE_INST_VALUE 15:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_CONTROL 0x00401044 /* RW-4R */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE 17:16 /* RWXUF */ -#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_ADJUST 31:20 /* RWXUF */ -#define NV_PGRAPH_DMA_A_LIMIT 0x00401048 /* RW-4R */ -#define NV_PGRAPH_DMA_A_LIMIT_OFFSET 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_TLB_PTE 0x0040104C /* RW-4R */ -#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS 1:1 /* RWXVF */ -#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ -#define NV_PGRAPH_DMA_A_TLB_TAG 0x00401050 /* RW-4R */ -#define NV_PGRAPH_DMA_A_TLB_TAG_ADDRESS 31:12 /* RWXUF */ -#define NV_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 /* RW-4R */ -#define NV_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_OFFSET 0x00401058 /* RW-4R */ -#define NV_PGRAPH_DMA_A_OFFSET_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_SIZE 0x0040105C /* RW-4R */ -#define NV_PGRAPH_DMA_A_SIZE_VALUE 24:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_Y_SIZE 0x00401060 /* RW-4R */ -#define NV_PGRAPH_DMA_A_Y_SIZE_VALUE 10:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_XLATE_INST 0x00401080 /* RW-4R */ -#define NV_PGRAPH_DMA_B_XLATE_INST_VALUE 15:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_CONTROL 0x00401084 /* RW-4R */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE 17:16 /* RWXUF */ -#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_ADJUST 31:20 /* RWXUF */ -#define NV_PGRAPH_DMA_B_LIMIT 0x00401088 /* RW-4R */ -#define NV_PGRAPH_DMA_B_LIMIT_OFFSET 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_TLB_PTE 0x0040108C /* RW-4R */ -#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS 1:1 /* RWXVF */ -#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ -#define NV_PGRAPH_DMA_B_TLB_TAG 0x00401090 /* RW-4R */ -#define NV_PGRAPH_DMA_B_TLB_TAG_ADDRESS 31:12 /* RWXUF */ -#define NV_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 /* RW-4R */ -#define NV_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_OFFSET 0x00401098 /* RW-4R */ -#define NV_PGRAPH_DMA_B_OFFSET_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_SIZE 0x0040109C /* RW-4R */ -#define NV_PGRAPH_DMA_B_SIZE_VALUE 24:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_Y_SIZE 0x004010A0 /* RW-4R */ -#define NV_PGRAPH_DMA_B_Y_SIZE_VALUE 10:0 /* RWXUF */ - -/* Framebuffer registers */ -#define NV_PFB 0x00100FFF:0x00100000 /* RW--D */ -#define NV_PFB_BOOT_0 0x00100000 /* RW-4R */ -#define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RW-VF */ -#define NV_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_WIDTH_128 2:2 /* RW-VF */ -#define NV_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x00000000 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_WIDTH_128_ON 0x00000001 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_TYPE 4:3 /* RW-VF */ -#define NV_PFB_BOOT_0_RAM_TYPE_256K 0x00000000 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x00000001 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x00000002 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x00000003 /* RW--V */ -#define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */ -#define NV_PFB_CONFIG_0_TYPE 14:0 /* RWIVF */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x00000120 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x00000220 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x00000320 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x00004120 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x00004220 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x00004320 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_TETRIS 0x00002000 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_NOTILING 0x00001114 /* RWI-V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE 17:15 /* RWI-F */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_PASS 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_1 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_2 0x00000002 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_3 0x00000003 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_4 0x00000004 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_5 0x00000005 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_6 0x00000006 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_7 0x00000007 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_SHIFT 19:18 /* RWI-F */ -#define NV_PFB_CONFIG_0_TETRIS_SHIFT_0 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_TETRIS_SHIFT_1 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_SHIFT_2 0x00000002 /* RW--V */ -#define NV_PFB_CONFIG_0_BANK_SWAP 22:20 /* RWI-F */ -#define NV_PFB_CONFIG_0_BANK_SWAP_OFF 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_BANK_SWAP_1M 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_BANK_SWAP_2M 0x00000005 /* RW--V */ -#define NV_PFB_CONFIG_0_BANK_SWAP_4M 0x00000007 /* RW--V */ -#define NV_PFB_CONFIG_0_UNUSED 23:23 /* RW-VF */ -#define NV_PFB_CONFIG_0_SCRAMBLE_EN 29:29 /* RWIVF */ -#define NV_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x00000000 /* RW--V */ -#define NV_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_PRAMIN_WR 28:28 /* RWIVF */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_INIT 0x00000000 /* RW--V */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK 27:24 /* RWIVF */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0x0000000f /* RWI-V */ -#define NV_PFB_CONFIG_1 0x00100204 /* RW-4R */ -#define NV_PFB_RTL 0x00100300 /* RW-4R */ -#define NV_PFB_RTL_H 0:0 /* RWIUF */ -#define NV_PFB_RTL_H_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_RTL_MC 1:1 /* RWIUF */ -#define NV_PFB_RTL_MC_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_RTL_V 2:2 /* RWIUF */ -#define NV_PFB_RTL_V_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_RTL_G 3:3 /* RWIUF */ -#define NV_PFB_RTL_G_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_RTL_GB 4:4 /* RWIUF */ -#define NV_PFB_RTL_GB_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */ -#define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */ -#define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */ -#define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */ -#define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */ -#define NV_PFB_CONFIG_1_SGRAM100 3:3 /* RWIVF */ -#define NV_PFB_CONFIG_1_SGRAM100_ENABLED 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_1_SGRAM100_DISABLED 0x00000001 /* RW--V */ -#define NV_PFB_DEBUG_0_CKE_ALWAYSON 29:29 /* RWIVF */ -#define NV_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x00000000 /* RW--V */ -#define NV_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x00000001 /* RWI-V */ - -#define NV_PEXTDEV 0x00101FFF:0x00101000 /* RW--D */ -#define NV_PEXTDEV_BOOT_0 0x00101000 /* R--4R */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0:0 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1:1 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 3:2 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x00000002 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x00000003 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4:4 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5:5 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6:6 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE 8:7 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x00000002 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x00000003 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11:11 /* RWIVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */ -#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */ - -/* Extras */ -#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */ -/*#define NV_PRAMIN 0x00FFFFFF:0x00C00000*/ -#define NV_PNVM 0x01FFFFFF:0x01000000 /* RW--M */ -/*#define NV_PNVM 0x00BFFFFF:0x00800000*/ -#define NV_CHAN0 0x0080ffff:0x00800000 - -/* FIFO subchannels */ -#define NV_UROP 0x43 -#define NV_UCHROMA 0x57 -#define NV_UCLIP 0x19 -#define NV_UPATT 0x18 -#define NV_ULIN 0x5C -#define NV_UTRI 0x5D -#define NV_URECT 0x5E -#define NV_UBLIT 0x5F -#define NV_UGLYPH 0x4B - -#endif /*__NV4REF_H__*/ - diff --git a/drivers/video/riva/nv_driver.c b/drivers/video/riva/nv_driver.c deleted file mode 100644 index be630a0ccfd..00000000000 --- a/drivers/video/riva/nv_driver.c +++ /dev/null @@ -1,425 +0,0 @@ -/* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */ -/* - * Copyright 1996-1997 David J. McKay - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - -/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen - <jpaana@s2.org> */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0 -5 20:47:06 mvojkovi Exp $ */ - -#include <linux/delay.h> -#include <linux/pci.h> -#include <linux/pci_ids.h> -#include "nv_type.h" -#include "rivafb.h" -#include "nvreg.h" - - -#ifndef CONFIG_PCI /* sanity check */ -#error This driver requires PCI support. -#endif - -#define PFX "rivafb: " - -static inline unsigned char MISCin(struct riva_par *par) -{ - return (VGA_RD08(par->riva.PVIO, 0x3cc)); -} - -static Bool -riva_is_connected(struct riva_par *par, Bool second) -{ - volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0; - U032 reg52C, reg608; - Bool present; - - if(second) PRAMDAC += 0x800; - - reg52C = NV_RD32(PRAMDAC, 0x052C); - reg608 = NV_RD32(PRAMDAC, 0x0608); - - NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000); - - NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE); - mdelay(1); - NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1); - - NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140); - NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000); - - mdelay(1); - - present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE; - - NV_WR32(par->riva.PRAMDAC0, 0x0608, - NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF); - - NV_WR32(PRAMDAC, 0x052C, reg52C); - NV_WR32(PRAMDAC, 0x0608, reg608); - - return present; -} - -static void -riva_override_CRTC(struct riva_par *par) -{ - printk(KERN_INFO PFX - "Detected CRTC controller %i being used\n", - par->SecondCRTC ? 1 : 0); - - if(par->forceCRTC != -1) { - printk(KERN_INFO PFX - "Forcing usage of CRTC %i\n", par->forceCRTC); - par->SecondCRTC = par->forceCRTC; - } -} - -static void -riva_is_second(struct riva_par *par) -{ - if (par->FlatPanel == 1) { - switch(par->Chipset & 0xffff) { - case 0x0174: - case 0x0175: - case 0x0176: - case 0x0177: - case 0x0179: - case 0x017C: - case 0x017D: - case 0x0186: - case 0x0187: - /* this might not be a good default for the chips below */ - case 0x0286: - case 0x028C: - case 0x0316: - case 0x0317: - case 0x031A: - case 0x031B: - case 0x031C: - case 0x031D: - case 0x031E: - case 0x031F: - case 0x0324: - case 0x0325: - case 0x0328: - case 0x0329: - case 0x032C: - case 0x032D: - par->SecondCRTC = TRUE; - break; - default: - par->SecondCRTC = FALSE; - break; - } - } else { - if(riva_is_connected(par, 0)) { - - if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100) - par->SecondCRTC = TRUE; - else - par->SecondCRTC = FALSE; - } else - if (riva_is_connected(par, 1)) { - if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100) - par->SecondCRTC = TRUE; - else - par->SecondCRTC = FALSE; - } else /* default */ - par->SecondCRTC = FALSE; - } - riva_override_CRTC(par); -} - -unsigned long riva_get_memlen(struct riva_par *par) -{ - RIVA_HW_INST *chip = &par->riva; - unsigned long memlen = 0; - unsigned int chipset = par->Chipset; - struct pci_dev* dev; - int amt; - - switch (chip->Architecture) { - case NV_ARCH_03: - if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) { - if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) - && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { - /* - * SDRAM 128 ZX. - */ - switch (NV_RD32(chip->PFB,0x00000000) & 0x03) { - case 2: - memlen = 1024 * 4; - break; - case 1: - memlen = 1024 * 2; - break; - default: - memlen = 1024 * 8; - break; - } - } else { - memlen = 1024 * 8; - } - } else { - /* - * SGRAM 128. - */ - switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) { - case 0: - memlen = 1024 * 8; - break; - case 2: - memlen = 1024 * 4; - break; - default: - memlen = 1024 * 2; - break; - } - } - break; - case NV_ARCH_04: - if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) { - memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) * - 1024 * 2 + 1024 * 2; - } else { - switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) { - case 0: - memlen = 1024 * 32; - break; - case 1: - memlen = 1024 * 4; - break; - case 2: - memlen = 1024 * 8; - break; - case 3: - default: - memlen = 1024 * 16; - break; - } - } - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - if(chipset == NV_CHIP_IGEFORCE2) { - - dev = pci_find_slot(0, 1); - pci_read_config_dword(dev, 0x7C, &amt); - memlen = (((amt >> 6) & 31) + 1) * 1024; - } else if (chipset == NV_CHIP_0x01F0) { - dev = pci_find_slot(0, 1); - pci_read_config_dword(dev, 0x84, &amt); - memlen = (((amt >> 4) & 127) + 1) * 1024; - } else { - switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & - 0x000000FF){ - case 0x02: - memlen = 1024 * 2; - break; - case 0x04: - memlen = 1024 * 4; - break; - case 0x08: - memlen = 1024 * 8; - break; - case 0x10: - memlen = 1024 * 16; - break; - case 0x20: - memlen = 1024 * 32; - break; - case 0x40: - memlen = 1024 * 64; - break; - case 0x80: - memlen = 1024 * 128; - break; - default: - memlen = 1024 * 16; - break; - } - } - break; - } - return memlen; -} - -unsigned long riva_get_maxdclk(struct riva_par *par) -{ - RIVA_HW_INST *chip = &par->riva; - unsigned long dclk = 0; - - switch (chip->Architecture) { - case NV_ARCH_03: - if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) { - if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) - && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { - /* - * SDRAM 128 ZX. - */ - dclk = 800000; - } else { - dclk = 1000000; - } - } else { - /* - * SGRAM 128. - */ - dclk = 1000000; - } - break; - case NV_ARCH_04: - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) { - case 3: - dclk = 800000; - break; - default: - dclk = 1000000; - break; - } - break; - } - return dclk; -} - -void -riva_common_setup(struct riva_par *par) -{ - par->riva.EnableIRQ = 0; - par->riva.PRAMDAC0 = - (volatile U032 __iomem *)(par->ctrl_base + 0x00680000); - par->riva.PFB = - (volatile U032 __iomem *)(par->ctrl_base + 0x00100000); - par->riva.PFIFO = - (volatile U032 __iomem *)(par->ctrl_base + 0x00002000); - par->riva.PGRAPH = - (volatile U032 __iomem *)(par->ctrl_base + 0x00400000); - par->riva.PEXTDEV = - (volatile U032 __iomem *)(par->ctrl_base + 0x00101000); - par->riva.PTIMER = - (volatile U032 __iomem *)(par->ctrl_base + 0x00009000); - par->riva.PMC = - (volatile U032 __iomem *)(par->ctrl_base + 0x00000000); - par->riva.FIFO = - (volatile U032 __iomem *)(par->ctrl_base + 0x00800000); - par->riva.PCIO0 = par->ctrl_base + 0x00601000; - par->riva.PDIO0 = par->ctrl_base + 0x00681000; - par->riva.PVIO = par->ctrl_base + 0x000C0000; - - par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0; - - if (par->FlatPanel == -1) { - switch (par->Chipset & 0xffff) { - case 0x0112: /* known laptop chips */ - case 0x0174: - case 0x0175: - case 0x0176: - case 0x0177: - case 0x0179: - case 0x017C: - case 0x017D: - case 0x0186: - case 0x0187: - case 0x0286: - case 0x028C: - case 0x0316: - case 0x0317: - case 0x031A: - case 0x031B: - case 0x031C: - case 0x031D: - case 0x031E: - case 0x031F: - case 0x0324: - case 0x0325: - case 0x0328: - case 0x0329: - case 0x032C: - case 0x032D: - printk(KERN_INFO PFX - "On a laptop. Assuming Digital Flat Panel\n"); - par->FlatPanel = 1; - break; - default: - break; - } - } - - switch (par->Chipset & 0x0ff0) { - case 0x0110: - if (par->Chipset == NV_CHIP_GEFORCE2_GO) - par->SecondCRTC = TRUE; -#if defined(__powerpc__) - if (par->FlatPanel == 1) - par->SecondCRTC = TRUE; -#endif - riva_override_CRTC(par); - break; - case 0x0170: - case 0x0180: - case 0x01F0: - case 0x0250: - case 0x0280: - case 0x0300: - case 0x0310: - case 0x0320: - case 0x0330: - case 0x0340: - riva_is_second(par); - break; - default: - break; - } - - if (par->SecondCRTC) { - par->riva.PCIO = par->riva.PCIO0 + 0x2000; - par->riva.PCRTC = par->riva.PCRTC0 + 0x800; - par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800; - par->riva.PDIO = par->riva.PDIO0 + 0x2000; - } else { - par->riva.PCIO = par->riva.PCIO0; - par->riva.PCRTC = par->riva.PCRTC0; - par->riva.PRAMDAC = par->riva.PRAMDAC0; - par->riva.PDIO = par->riva.PDIO0; - } - - if (par->FlatPanel == -1) { - /* Fix me, need x86 DDC code */ - par->FlatPanel = 0; - } - par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE; - - RivaGetConfig(&par->riva, par->Chipset); -} - diff --git a/drivers/video/riva/nv_type.h b/drivers/video/riva/nv_type.h deleted file mode 100644 index a69480c9a67..00000000000 --- a/drivers/video/riva/nv_type.h +++ /dev/null @@ -1,58 +0,0 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.35 2002/08/05 20:47:06 mvojkovi Exp $ */ - -#ifndef __NV_STRUCT_H__ -#define __NV_STRUCT_H__ - -#define NV_CHIP_RIVA_128 ((PCI_VENDOR_ID_NVIDIA_SGS << 16)| PCI_DEVICE_ID_NVIDIA_RIVA128) -#define NV_CHIP_TNT ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT) -#define NV_CHIP_TNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT2) -#define NV_CHIP_UTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UTNT2) -#define NV_CHIP_VTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_VTNT2) -#define NV_CHIP_UVTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UVTNT2) -#define NV_CHIP_ITNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_ITNT2) -#define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_256) -#define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR) -#define NV_CHIP_QUADRO ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_QUADRO) -#define NV_CHIP_GEFORCE2_MX ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX) -#define NV_CHIP_GEFORCE2_MX_100 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX_100) -#define NV_CHIP_QUADRO2_MXR ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR) -#define NV_CHIP_GEFORCE2_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO) -#define NV_CHIP_GEFORCE2_GTS ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS) -#define NV_CHIP_GEFORCE2_TI ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_TI) -#define NV_CHIP_GEFORCE2_ULTRA ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA) -#define NV_CHIP_QUADRO2_PRO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO) -#define NV_CHIP_GEFORCE4_MX_460 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460) -#define NV_CHIP_GEFORCE4_MX_440 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440) -#define NV_CHIP_GEFORCE4_MX_420 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420) -#define NV_CHIP_GEFORCE4_440_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO) -#define NV_CHIP_GEFORCE4_420_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO) -#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32) -#define NV_CHIP_QUADRO4_500XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL) -#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64) -#define NV_CHIP_QUADRO4_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_200) -#define NV_CHIP_QUADRO4_550XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL) -#define NV_CHIP_QUADRO4_500_GOGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL) -#define NV_CHIP_0x0180 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0180) -#define NV_CHIP_0x0181 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0181) -#define NV_CHIP_0x0182 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0182) -#define NV_CHIP_0x0188 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0188) -#define NV_CHIP_0x018A ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018A) -#define NV_CHIP_0x018B ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018B) -#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_IGEFORCE2) -#define NV_CHIP_0x01F0 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x01F0) -#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3) -#define NV_CHIP_GEFORCE3_TI_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_200) -#define NV_CHIP_GEFORCE3_TI_500 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_500) -#define NV_CHIP_QUADRO_DCC ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO_DCC) -#define NV_CHIP_GEFORCE4_TI_4600 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600) -#define NV_CHIP_GEFORCE4_TI_4400 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400) -#define NV_CHIP_GEFORCE4_TI_4200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200) -#define NV_CHIP_QUADRO4_900XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL) -#define NV_CHIP_QUADRO4_750XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL) -#define NV_CHIP_QUADRO4_700XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL) -#define NV_CHIP_0x0280 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0280) -#define NV_CHIP_0x0281 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0281) -#define NV_CHIP_0x0288 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0288) -#define NV_CHIP_0x0289 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0289) - -#endif /* __NV_STRUCT_H__ */ diff --git a/drivers/video/riva/nvreg.h b/drivers/video/riva/nvreg.h deleted file mode 100644 index abfc167ae8d..00000000000 --- a/drivers/video/riva/nvreg.h +++ /dev/null @@ -1,188 +0,0 @@ -/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */ -/* - * Copyright 1996-1997 David J. McKay - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */ - -#ifndef __NVREG_H_ -#define __NVREG_H_ - -/* Little macro to construct bitmask for contiguous ranges of bits */ -#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b)) -#define MASKEXPAND(mask) BITMASK(1?mask,0?mask) - -/* Macro to set specific bitfields (mask has to be a macro x:y) ! */ -#define SetBF(mask,value) ((value) << (0?mask)) -#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) - -#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ - | SetBF(mask,value))) - -#define DEVICE_BASE(device) (0?NV##_##device) -#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1) - -/* This is where we will have to have conditional compilation */ -#define DEVICE_ACCESS(device,reg) \ - nvCONTROL[(NV_##device##_##reg)/4] - -#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) -#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) -#define DEVICE_PRINT(device,reg) \ - ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) -#define DEVICE_DEF(device,mask,value) \ - SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value) -#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) -#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) - -#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) -#define PDAC_Read(reg) DEVICE_READ(PDAC,reg) -#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) -#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) -#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) -#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask) - -#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) -#define PFB_Read(reg) DEVICE_READ(PFB,reg) -#define PFB_Print(reg) DEVICE_PRINT(PFB,reg) -#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value) -#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value) -#define PFB_Mask(mask) DEVICE_MASK(PFB,mask) - -#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value) -#define PRM_Read(reg) DEVICE_READ(PRM,reg) -#define PRM_Print(reg) DEVICE_PRINT(PRM,reg) -#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value) -#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value) -#define PRM_Mask(mask) DEVICE_MASK(PRM,mask) - -#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value) -#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg) -#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg) -#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value) -#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value) -#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask) - -#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value) -#define PDMA_Read(reg) DEVICE_READ(PDMA,reg) -#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg) -#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value) -#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value) -#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask) - -#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value) -#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg) -#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg) -#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value) -#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value) -#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask) - -#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value) -#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg) -#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg) -#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value) -#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value) -#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask) - -#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value) -#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg) -#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg) -#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value) -#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value) -#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask) - -#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value) -#define PRAM_Read(reg) DEVICE_READ(PRAM,reg) -#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg) -#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value) -#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value) -#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask) - -#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value) -#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg) -#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg) -#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value) -#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value) -#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask) - -#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) -#define PMC_Read(reg) DEVICE_READ(PMC,reg) -#define PMC_Print(reg) DEVICE_PRINT(PMC,reg) -#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) -#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) -#define PMC_Mask(mask) DEVICE_MASK(PMC,mask) - -#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) -#define PMC_Read(reg) DEVICE_READ(PMC,reg) -#define PMC_Print(reg) DEVICE_PRINT(PMC,reg) -#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) -#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) -#define PMC_Mask(mask) DEVICE_MASK(PMC,mask) - - -#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value) -#define PBUS_Read(reg) DEVICE_READ(PBUS,reg) -#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg) -#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value) -#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value) -#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask) - - -#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value) -#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg) -#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg) -#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value) -#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value) -#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask) - - -#define PDAC_ReadExt(reg) \ - ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ - (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ - (PDAC_Read(INDEX_DATA))) - -#define PDAC_WriteExt(reg,value)\ - ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ - (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ - (PDAC_Write(INDEX_DATA,(value)))) - -#define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5) -#define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5)) - -#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value) -#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index) - -#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value) -#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value) -#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask) - -#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value) -#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5)) - -extern volatile unsigned *nvCONTROL; - -typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType; - -NVChipType GetChipType(void); - -#endif - - diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c deleted file mode 100644 index b6f8690b96c..00000000000 --- a/drivers/video/riva/riva_hw.c +++ /dev/null @@ -1,2259 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */ - -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/pci_ids.h> -#include "riva_hw.h" -#include "riva_tbl.h" -#include "nv_type.h" - -/* - * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT - * operate identically (except TNT has more memory and better 3D quality. - */ -static int nv3Busy -( - RIVA_HW_INST *chip -) -{ - return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || - NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); -} -static int nv4Busy -( - RIVA_HW_INST *chip -) -{ - return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || - NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); -} -static int nv10Busy -( - RIVA_HW_INST *chip -) -{ - return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || - NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); -} - -static void vgaLockUnlock -( - RIVA_HW_INST *chip, - int Lock -) -{ - U008 cr11; - VGA_WR08(chip->PCIO, 0x3D4, 0x11); - cr11 = VGA_RD08(chip->PCIO, 0x3D5); - if(Lock) cr11 |= 0x80; - else cr11 &= ~0x80; - VGA_WR08(chip->PCIO, 0x3D5, cr11); -} -static void nv3LockUnlock -( - RIVA_HW_INST *chip, - int Lock -) -{ - VGA_WR08(chip->PVIO, 0x3C4, 0x06); - VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); - vgaLockUnlock(chip, Lock); -} -static void nv4LockUnlock -( - RIVA_HW_INST *chip, - int Lock -) -{ - VGA_WR08(chip->PCIO, 0x3D4, 0x1F); - VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); - vgaLockUnlock(chip, Lock); -} - -static int ShowHideCursor -( - RIVA_HW_INST *chip, - int ShowHide -) -{ - int cursor; - cursor = chip->CurrentState->cursor1; - chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | - (ShowHide & 0x01); - VGA_WR08(chip->PCIO, 0x3D4, 0x31); - VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); - return (cursor & 0x01); -} - -/****************************************************************************\ -* * -* The video arbitration routines calculate some "magic" numbers. Fixes * -* the snow seen when accessing the framebuffer without it. * -* It just works (I hope). * -* * -\****************************************************************************/ - -#define DEFAULT_GR_LWM 100 -#define DEFAULT_VID_LWM 100 -#define DEFAULT_GR_BURST_SIZE 256 -#define DEFAULT_VID_BURST_SIZE 128 -#define VIDEO 0 -#define GRAPHICS 1 -#define MPORT 2 -#define ENGINE 3 -#define GFIFO_SIZE 320 -#define GFIFO_SIZE_128 256 -#define MFIFO_SIZE 120 -#define VFIFO_SIZE 256 - -typedef struct { - int gdrain_rate; - int vdrain_rate; - int mdrain_rate; - int gburst_size; - int vburst_size; - char vid_en; - char gr_en; - int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm; - int by_gfacc; - char vid_only_once; - char gr_only_once; - char first_vacc; - char first_gacc; - char first_macc; - int vocc; - int gocc; - int mocc; - char cur; - char engine_en; - char converged; - int priority; -} nv3_arb_info; -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int graphics_hi_priority; - int media_hi_priority; - int rtl_values; - int valid; -} nv3_fifo_info; -typedef struct { - char pix_bpp; - char enable_video; - char gr_during_vid; - char enable_mp; - int memory_width; - int video_scale; - int pclk_khz; - int mclk_khz; - int mem_page_miss; - int mem_latency; - char mem_aligned; -} nv3_sim_state; -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int valid; -} nv4_fifo_info; -typedef struct { - int pclk_khz; - int mclk_khz; - int nvclk_khz; - char mem_page_miss; - char mem_latency; - int memory_width; - char enable_video; - char gr_during_vid; - char pix_bpp; - char mem_aligned; - char enable_mp; -} nv4_sim_state; -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int valid; -} nv10_fifo_info; -typedef struct { - int pclk_khz; - int mclk_khz; - int nvclk_khz; - char mem_page_miss; - char mem_latency; - int memory_type; - int memory_width; - char enable_video; - char gr_during_vid; - char pix_bpp; - char mem_aligned; - char enable_mp; -} nv10_sim_state; -static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) -{ - int iter = 0; - int tmp; - int vfsize, mfsize, gfsize; - int mburst_size = 32; - int mmisses, gmisses, vmisses; - int misses; - int vlwm, glwm, mlwm; - int last, next, cur; - int max_gfsize ; - long ns; - - vlwm = 0; - glwm = 0; - mlwm = 0; - vfsize = 0; - gfsize = 0; - cur = ainfo->cur; - mmisses = 2; - gmisses = 2; - vmisses = 2; - if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128; - else max_gfsize = GFIFO_SIZE; - max_gfsize = GFIFO_SIZE; - while (1) - { - if (ainfo->vid_en) - { - if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc; - if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ; - ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; - vfsize = ns * ainfo->vdrain_rate / 1000000; - vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize; - } - if (state->enable_mp) - { - if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc; - } - if (ainfo->gr_en) - { - if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; - if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; - ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; - gfsize = (ns * (long) ainfo->gdrain_rate)/1000000; - gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; - } - mfsize = 0; - if (!state->gr_during_vid && ainfo->vid_en) - if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) - next = VIDEO; - else if (ainfo->mocc < 0) - next = MPORT; - else if (ainfo->gocc< ainfo->by_gfacc) - next = GRAPHICS; - else return (0); - else switch (ainfo->priority) - { - case VIDEO: - if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) - next = VIDEO; - else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) - next = GRAPHICS; - else if (ainfo->mocc<0) - next = MPORT; - else return (0); - break; - case GRAPHICS: - if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) - next = GRAPHICS; - else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) - next = VIDEO; - else if (ainfo->mocc<0) - next = MPORT; - else return (0); - break; - default: - if (ainfo->mocc<0) - next = MPORT; - else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) - next = GRAPHICS; - else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) - next = VIDEO; - else return (0); - break; - } - last = cur; - cur = next; - iter++; - switch (cur) - { - case VIDEO: - if (last==cur) misses = 0; - else if (ainfo->first_vacc) misses = vmisses; - else misses = 1; - ainfo->first_vacc = 0; - if (last!=cur) - { - ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; - vlwm = ns * ainfo->vdrain_rate/ 1000000; - vlwm = ainfo->vocc - vlwm; - } - ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz; - ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000; - ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000; - break; - case GRAPHICS: - if (last==cur) misses = 0; - else if (ainfo->first_gacc) misses = gmisses; - else misses = 1; - ainfo->first_gacc = 0; - if (last!=cur) - { - ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; - glwm = ns * ainfo->gdrain_rate/1000000; - glwm = ainfo->gocc - glwm; - } - ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; - ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000; - ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; - break; - default: - if (last==cur) misses = 0; - else if (ainfo->first_macc) misses = mmisses; - else misses = 1; - ainfo->first_macc = 0; - ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; - ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; - ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000; - break; - } - if (iter>100) - { - ainfo->converged = 0; - return (1); - } - ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; - tmp = ns * ainfo->gdrain_rate/1000000; - if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) - { - ainfo->converged = 0; - return (1); - } - ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; - tmp = ns * ainfo->vdrain_rate/1000000; - if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (abs(ainfo->gocc) > max_gfsize) - { - ainfo->converged = 0; - return (1); - } - if (abs(ainfo->vocc) > VFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (abs(ainfo->mocc) > MFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (abs(vfsize) > VFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (abs(gfsize) > max_gfsize) - { - ainfo->converged = 0; - return (1); - } - if (abs(mfsize) > MFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - } -} -static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) -{ - long ens, vns, mns, gns; - int mmisses, gmisses, vmisses, eburst_size, mburst_size; - int refresh_cycle; - - refresh_cycle = 0; - refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; - mmisses = 2; - if (state->mem_aligned) gmisses = 2; - else gmisses = 3; - vmisses = 2; - eburst_size = state->memory_width * 1; - mburst_size = 32; - gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; - ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000; - ainfo->wcmocc = 0; - ainfo->wcgocc = 0; - ainfo->wcvocc = 0; - ainfo->wcvlwm = 0; - ainfo->wcglwm = 0; - ainfo->engine_en = 1; - ainfo->converged = 1; - if (ainfo->engine_en) - { - ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz; - ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; - ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; - ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; - ainfo->cur = ENGINE; - ainfo->first_vacc = 1; - ainfo->first_gacc = 1; - ainfo->first_macc = 1; - nv3_iterate(res_info, state,ainfo); - } - if (state->enable_mp) - { - mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; - ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; - ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; - ainfo->cur = MPORT; - ainfo->first_vacc = 1; - ainfo->first_gacc = 1; - ainfo->first_macc = 0; - nv3_iterate(res_info, state,ainfo); - } - if (ainfo->gr_en) - { - ainfo->first_vacc = 1; - ainfo->first_gacc = 0; - ainfo->first_macc = 1; - gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; - ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000; - ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; - ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; - ainfo->cur = GRAPHICS; - nv3_iterate(res_info, state,ainfo); - } - if (ainfo->vid_en) - { - ainfo->first_vacc = 0; - ainfo->first_gacc = 1; - ainfo->first_macc = 1; - vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; - ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; - ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; - ainfo->cur = VIDEO; - nv3_iterate(res_info, state, ainfo); - } - if (ainfo->converged) - { - res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16; - res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32; - res_info->graphics_burst_size = ainfo->gburst_size; - res_info->video_burst_size = ainfo->vburst_size; - res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS); - res_info->media_hi_priority = (ainfo->priority == MPORT); - if (res_info->video_lwm > 160) - { - res_info->graphics_lwm = 256; - res_info->video_lwm = 128; - res_info->graphics_burst_size = 64; - res_info->video_burst_size = 64; - res_info->graphics_hi_priority = 0; - res_info->media_hi_priority = 0; - ainfo->converged = 0; - return (0); - } - if (res_info->video_lwm > 128) - { - res_info->video_lwm = 128; - } - return (1); - } - else - { - res_info->graphics_lwm = 256; - res_info->video_lwm = 128; - res_info->graphics_burst_size = 64; - res_info->video_burst_size = 64; - res_info->graphics_hi_priority = 0; - res_info->media_hi_priority = 0; - return (0); - } -} -static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) -{ - int done, g,v, p; - - done = 0; - for (p=0; p < 2; p++) - { - for (g=128 ; g > 32; g= g>> 1) - { - for (v=128; v >=32; v = v>> 1) - { - ainfo->priority = p; - ainfo->gburst_size = g; - ainfo->vburst_size = v; - done = nv3_arb(res_info, state,ainfo); - if (done && (g==128)) - if ((res_info->graphics_lwm + g) > 256) - done = 0; - if (done) - goto Done; - } - } - } - - Done: - return done; -} -static void nv3CalcArbitration -( - nv3_fifo_info * res_info, - nv3_sim_state * state -) -{ - nv3_fifo_info save_info; - nv3_arb_info ainfo; - char res_gr, res_vid; - - ainfo.gr_en = 1; - ainfo.vid_en = state->enable_video; - ainfo.vid_only_once = 0; - ainfo.gr_only_once = 0; - ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); - ainfo.vdrain_rate = (int) state->pclk_khz * 2; - if (state->video_scale != 0) - ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; - ainfo.mdrain_rate = 33000; - res_info->rtl_values = 0; - if (!state->gr_during_vid && state->enable_video) - { - ainfo.gr_only_once = 1; - ainfo.gr_en = 1; - ainfo.gdrain_rate = 0; - res_vid = nv3_get_param(res_info, state, &ainfo); - res_vid = ainfo.converged; - save_info.video_lwm = res_info->video_lwm; - save_info.video_burst_size = res_info->video_burst_size; - ainfo.vid_en = 1; - ainfo.vid_only_once = 1; - ainfo.gr_en = 1; - ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); - ainfo.vdrain_rate = 0; - res_gr = nv3_get_param(res_info, state, &ainfo); - res_gr = ainfo.converged; - res_info->video_lwm = save_info.video_lwm; - res_info->video_burst_size = save_info.video_burst_size; - res_info->valid = res_gr & res_vid; - } - else - { - if (!ainfo.gr_en) ainfo.gdrain_rate = 0; - if (!ainfo.vid_en) ainfo.vdrain_rate = 0; - res_gr = nv3_get_param(res_info, state, &ainfo); - res_info->valid = ainfo.converged; - } -} -static void nv3UpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip -) -{ - nv3_fifo_info fifo_data; - nv3_sim_state sim_data; - unsigned int M, N, P, pll, MClk; - - pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - MClk = (N * chip->CrystalFreqKHz / M) >> P; - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - sim_data.video_scale = 1; - sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? - 128 : 64; - sim_data.memory_width = 128; - - sim_data.mem_latency = 9; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = 11; - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - nv3CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } - else - { - *lwm = 0x24; - *burst = 0x2; - } -} -static void nv4CalcArbitration -( - nv4_fifo_info *fifo, - nv4_sim_state *arb -) -{ - int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; - int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; - int found, mclk_extra, mclk_loop, cbs, m1, p1; - int mclk_freq, pclk_freq, nvclk_freq, mp_enable; - int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; - int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm; - int craw, vraw; - - fifo->valid = 1; - pclk_freq = arb->pclk_khz; - mclk_freq = arb->mclk_khz; - nvclk_freq = arb->nvclk_khz; - pagemiss = arb->mem_page_miss; - cas = arb->mem_latency; - width = arb->memory_width >> 6; - video_enable = arb->enable_video; - color_key_enable = arb->gr_during_vid; - bpp = arb->pix_bpp; - align = arb->mem_aligned; - mp_enable = arb->enable_mp; - clwm = 0; - vlwm = 0; - cbs = 128; - pclks = 2; - nvclks = 2; - nvclks += 2; - nvclks += 1; - mclks = 5; - mclks += 3; - mclks += 1; - mclks += cas; - mclks += 1; - mclks += 1; - mclks += 1; - mclks += 1; - mclk_extra = 3; - nvclks += 2; - nvclks += 1; - nvclks += 1; - nvclks += 1; - if (mp_enable) - mclks+=4; - nvclks += 0; - pclks += 0; - found = 0; - vbs = 0; - while (found != 1) - { - fifo->valid = 1; - found = 1; - mclk_loop = mclks+mclk_extra; - us_m = mclk_loop *1000*1000 / mclk_freq; - us_n = nvclks*1000*1000 / nvclk_freq; - us_p = nvclks*1000*1000 / pclk_freq; - if (video_enable) - { - video_drain_rate = pclk_freq * 2; - crtc_drain_rate = pclk_freq * bpp/8; - vpagemiss = 2; - vpagemiss += 1; - crtpagemiss = 2; - vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; - if (nvclk_freq * 2 > mclk_freq * width) - video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ; - else - video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; - us_video = vpm_us + us_m + us_n + us_p + video_fill_us; - vlwm = us_video * video_drain_rate/(1000*1000); - vlwm++; - vbs = 128; - if (vlwm > 128) vbs = 64; - if (vlwm > (256-64)) vbs = 32; - if (nvclk_freq * 2 > mclk_freq * width) - video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ; - else - video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = - us_video - +video_fill_us - +cpm_us - +us_m + us_n +us_p - ; - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; - } - else - { - crtc_drain_rate = pclk_freq * bpp/8; - crtpagemiss = 2; - crtpagemiss += 1; - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = cpm_us + us_m + us_n + us_p ; - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; - } - m1 = clwm + cbs - 512; - p1 = m1 * pclk_freq / mclk_freq; - p1 = p1 * bpp / 8; - if ((p1 < m1) && (m1 > 0)) - { - fifo->valid = 0; - found = 0; - if (mclk_extra ==0) found = 1; - mclk_extra--; - } - else if (video_enable) - { - if ((clwm > 511) || (vlwm > 255)) - { - fifo->valid = 0; - found = 0; - if (mclk_extra ==0) found = 1; - mclk_extra--; - } - } - else - { - if (clwm > 519) - { - fifo->valid = 0; - found = 0; - if (mclk_extra ==0) found = 1; - mclk_extra--; - } - } - craw = clwm; - vraw = vlwm; - if (clwm < 384) clwm = 384; - if (vlwm < 128) vlwm = 128; - data = (int)(clwm); - fifo->graphics_lwm = data; - fifo->graphics_burst_size = 128; - data = (int)((vlwm+15)); - fifo->video_lwm = data; - fifo->video_burst_size = vbs; - } -} -static void nv4UpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip -) -{ - nv4_fifo_info fifo_data; - nv4_sim_state sim_data; - unsigned int M, N, P, pll, MClk, NVClk, cfg1; - - pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - MClk = (N * chip->CrystalFreqKHz / M) >> P; - pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - NVClk = (N * chip->CrystalFreqKHz / M) >> P; - cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? - 128 : 64; - sim_data.mem_latency = (char)cfg1 & 0x0F; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv4CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} -static void nv10CalcArbitration -( - nv10_fifo_info *fifo, - nv10_sim_state *arb -) -{ - int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; - int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; - int nvclk_fill, us_extra; - int found, mclk_extra, mclk_loop, cbs, m1; - int mclk_freq, pclk_freq, nvclk_freq, mp_enable; - int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate; - int vus_m, vus_n, vus_p; - int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm; - int clwm_rnd_down; - int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2; - int pclks_2_top_fifo, min_mclk_extra; - int us_min_mclk_extra; - - fifo->valid = 1; - pclk_freq = arb->pclk_khz; /* freq in KHz */ - mclk_freq = arb->mclk_khz; - nvclk_freq = arb->nvclk_khz; - pagemiss = arb->mem_page_miss; - cas = arb->mem_latency; - width = arb->memory_width/64; - video_enable = arb->enable_video; - color_key_enable = arb->gr_during_vid; - bpp = arb->pix_bpp; - align = arb->mem_aligned; - mp_enable = arb->enable_mp; - clwm = 0; - vlwm = 1024; - - cbs = 512; - vbs = 512; - - pclks = 4; /* lwm detect. */ - - nvclks = 3; /* lwm -> sync. */ - nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */ - - mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */ - - mclks += 1; /* arb_hp_req */ - mclks += 5; /* ap_hp_req tiling pipeline */ - - mclks += 2; /* tc_req latency fifo */ - mclks += 2; /* fb_cas_n_ memory request to fbio block */ - mclks += 7; /* sm_d_rdv data returned from fbio block */ - - /* fb.rd.d.Put_gc need to accumulate 256 bits for read */ - if (arb->memory_type == 0) - if (arb->memory_width == 64) /* 64 bit bus */ - mclks += 4; - else - mclks += 2; - else - if (arb->memory_width == 64) /* 64 bit bus */ - mclks += 2; - else - mclks += 1; - - if ((!video_enable) && (arb->memory_width == 128)) - { - mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ - min_mclk_extra = 17; - } - else - { - mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ - /* mclk_extra = 4; */ /* Margin of error */ - min_mclk_extra = 18; - } - - nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */ - nvclks += 1; /* fbi_d_rdv_n */ - nvclks += 1; /* Fbi_d_rdata */ - nvclks += 1; /* crtfifo load */ - - if(mp_enable) - mclks+=4; /* Mp can get in with a burst of 8. */ - /* Extra clocks determined by heuristics */ - - nvclks += 0; - pclks += 0; - found = 0; - while(found != 1) { - fifo->valid = 1; - found = 1; - mclk_loop = mclks+mclk_extra; - us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ - us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */ - us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq; - us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */ - us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */ - us_pipe = us_m + us_n + us_p; - us_pipe_min = us_m_min + us_n + us_p; - us_extra = 0; - - vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ - vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */ - vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */ - vus_pipe = vus_m + vus_n + vus_p; - - if(video_enable) { - video_drain_rate = pclk_freq * 4; /* MB/s */ - crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */ - - vpagemiss = 1; /* self generating page miss */ - vpagemiss += 1; /* One higher priority before */ - - crtpagemiss = 2; /* self generating page miss */ - if(mp_enable) - crtpagemiss += 1; /* if MA0 conflict */ - - vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; - - us_video = vpm_us + vus_m; /* Video has separate read return path */ - - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = - us_video /* Wait for video */ - +cpm_us /* CRT Page miss */ - +us_m + us_n +us_p /* other latency */ - ; - - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; /* fixed point <= float_point - 1. Fixes that */ - } else { - crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */ - - crtpagemiss = 1; /* self generating page miss */ - crtpagemiss += 1; /* MA0 page miss */ - if(mp_enable) - crtpagemiss += 1; /* if MA0 conflict */ - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = cpm_us + us_m + us_n + us_p ; - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; /* fixed point <= float_point - 1. Fixes that */ - - /* - // - // Another concern, only for high pclks so don't do this - // with video: - // What happens if the latency to fetch the cbs is so large that - // fifo empties. In that case we need to have an alternate clwm value - // based off the total burst fetch - // - us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; - us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq; - clwm_mt = us_crt * crtc_drain_rate/(1000*1000); - clwm_mt ++; - if(clwm_mt > clwm) - clwm = clwm_mt; - */ - /* Finally, a heuristic check when width == 64 bits */ - if(width == 1){ - nvclk_fill = nvclk_freq * 8; - if(crtc_drain_rate * 100 >= nvclk_fill * 102) - clwm = 0xfff; /*Large number to fail */ - - else if(crtc_drain_rate * 100 >= nvclk_fill * 98) { - clwm = 1024; - cbs = 512; - us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; - } - } - } - - - /* - Overfill check: - - */ - - clwm_rnd_down = ((int)clwm/8)*8; - if (clwm_rnd_down < clwm) - clwm += 8; - - m1 = clwm + cbs - 1024; /* Amount of overfill */ - m2us = us_pipe_min + us_min_mclk_extra; - pclks_2_top_fifo = (1024-clwm)/(8*width); - - /* pclk cycles to drain */ - p1clk = m2us * pclk_freq/(1000*1000); - p2 = p1clk * bpp / 8; /* bytes drained. */ - - if((p2 < m1) && (m1 > 0)) { - fifo->valid = 0; - found = 0; - if(min_mclk_extra == 0) { - if(cbs <= 32) { - found = 1; /* Can't adjust anymore! */ - } else { - cbs = cbs/2; /* reduce the burst size */ - } - } else { - min_mclk_extra--; - } - } else { - if (clwm > 1023){ /* Have some margin */ - fifo->valid = 0; - found = 0; - if(min_mclk_extra == 0) - found = 1; /* Can't adjust anymore! */ - else - min_mclk_extra--; - } - } - craw = clwm; - - if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8; - data = (int)(clwm); - /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */ - fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs; - - /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */ - fifo->video_lwm = 1024; fifo->video_burst_size = 512; - } -} -static void nv10UpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip -) -{ - nv10_fifo_info fifo_data; - nv10_sim_state sim_data; - unsigned int M, N, P, pll, MClk, NVClk, cfg1; - - pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - MClk = (N * chip->CrystalFreqKHz / M) >> P; - pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - NVClk = (N * chip->CrystalFreqKHz / M) >> P; - cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? - 1 : 0; - sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? - 128 : 64; - sim_data.mem_latency = (char)cfg1 & 0x0F; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv10CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} - -static void nForceUpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip -) -{ - nv10_fifo_info fifo_data; - nv10_sim_state sim_data; - unsigned int M, N, P, pll, MClk, NVClk; - unsigned int uMClkPostDiv; - struct pci_dev *dev; - - dev = pci_find_slot(0, 3); - pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); - uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; - - if(!uMClkPostDiv) uMClkPostDiv = 4; - MClk = 400000 / uMClkPostDiv; - - pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - NVClk = (N * chip->CrystalFreqKHz / M) >> P; - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - - dev = pci_find_slot(0, 1); - pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); - sim_data.memory_type = (sim_data.memory_type >> 12) & 1; - - sim_data.memory_width = 64; - sim_data.mem_latency = 3; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = 10; - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv10CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} - -/****************************************************************************\ -* * -* RIVA Mode State Routines * -* * -\****************************************************************************/ - -/* - * Calculate the Video Clock parameters for the PLL. - */ -static int CalcVClock -( - int clockIn, - int *clockOut, - int *mOut, - int *nOut, - int *pOut, - RIVA_HW_INST *chip -) -{ - unsigned lowM, highM, highP; - unsigned DeltaNew, DeltaOld; - unsigned VClk, Freq; - unsigned M, N, P; - - DeltaOld = 0xFFFFFFFF; - - VClk = (unsigned)clockIn; - - if (chip->CrystalFreqKHz == 13500) - { - lowM = 7; - highM = 13 - (chip->Architecture == NV_ARCH_03); - } - else - { - lowM = 8; - highM = 14 - (chip->Architecture == NV_ARCH_03); - } - - highP = 4 - (chip->Architecture == NV_ARCH_03); - for (P = 0; P <= highP; P ++) - { - Freq = VClk << P; - if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) - { - for (M = lowM; M <= highM; M++) - { - N = (VClk << P) * M / chip->CrystalFreqKHz; - if(N <= 255) { - Freq = (chip->CrystalFreqKHz * N / M) >> P; - if (Freq > VClk) - DeltaNew = Freq - VClk; - else - DeltaNew = VClk - Freq; - if (DeltaNew < DeltaOld) - { - *mOut = M; - *nOut = N; - *pOut = P; - *clockOut = Freq; - DeltaOld = DeltaNew; - } - } - } - } - } - return (DeltaOld != 0xFFFFFFFF); -} -/* - * Calculate extended mode parameters (SVGA) and save in a - * mode state structure. - */ -static void CalcStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state, - int bpp, - int width, - int hDisplaySize, - int height, - int dotClock -) -{ - int pixelDepth, VClk, m, n, p; - /* - * Save mode parameters. - */ - state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ - state->width = width; - state->height = height; - /* - * Extended RIVA registers. - */ - pixelDepth = (bpp + 1)/8; - CalcVClock(dotClock, &VClk, &m, &n, &p, chip); - - switch (chip->Architecture) - { - case NV_ARCH_03: - nv3UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip); - state->cursor0 = 0x00; - state->cursor1 = 0x78; - state->cursor2 = 0x00000000; - state->pllsel = 0x10010100; - state->config = ((width + 31)/32) - | (((pixelDepth > 2) ? 3 : pixelDepth) << 8) - | 0x1000; - state->general = 0x00100100; - state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; - break; - case NV_ARCH_04: - nv4UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip); - state->cursor0 = 0x00; - state->cursor1 = 0xFC; - state->cursor2 = 0x00000000; - state->pllsel = 0x10000700; - state->config = 0x00001114; - state->general = bpp == 16 ? 0x00101100 : 0x00100100; - state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - if((chip->Chipset == NV_CHIP_IGEFORCE2) || - (chip->Chipset == NV_CHIP_0x01F0)) - { - nForceUpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip); - } else { - nv10UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip); - } - state->cursor0 = 0x80 | (chip->CursorStart >> 17); - state->cursor1 = (chip->CursorStart >> 11) << 2; - state->cursor2 = chip->CursorStart >> 24; - state->pllsel = 0x10000700; - state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); - state->general = bpp == 16 ? 0x00101100 : 0x00100100; - state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; - break; - } - - /* Paul Richards: below if block borks things in kernel for some reason */ - /* Tony: Below is needed to set hardware in DirectColor */ - if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) - state->general |= 0x00000030; - - state->vpll = (p << 16) | (n << 8) | m; - state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; - state->pixel = pixelDepth > 2 ? 3 : pixelDepth; - state->offset0 = - state->offset1 = - state->offset2 = - state->offset3 = 0; - state->pitch0 = - state->pitch1 = - state->pitch2 = - state->pitch3 = pixelDepth * width; -} -/* - * Load fixed function state and pre-calculated/stored state. - */ -#if 0 -#define LOAD_FIXED_STATE(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ - chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1] -#define LOAD_FIXED_STATE_8BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ - chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1] -#define LOAD_FIXED_STATE_15BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ - chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1] -#define LOAD_FIXED_STATE_16BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ - chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1] -#define LOAD_FIXED_STATE_32BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ - chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1] -#endif - -#define LOAD_FIXED_STATE(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1]) -#define LOAD_FIXED_STATE_8BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1]) -#define LOAD_FIXED_STATE_15BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1]) -#define LOAD_FIXED_STATE_16BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1]) -#define LOAD_FIXED_STATE_32BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1]) - -static void UpdateFifoState -( - RIVA_HW_INST *chip -) -{ - int i; - - switch (chip->Architecture) - { - case NV_ARCH_04: - LOAD_FIXED_STATE(nv4,FIFO); - chip->Tri03 = NULL; - chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - /* - * Initialize state for the RivaTriangle3D05 routines. - */ - LOAD_FIXED_STATE(nv10tri05,PGRAPH); - LOAD_FIXED_STATE(nv10,FIFO); - chip->Tri03 = NULL; - chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - } -} -static void LoadStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state -) -{ - int i; - - /* - * Load HW fixed function state. - */ - LOAD_FIXED_STATE(Riva,PMC); - LOAD_FIXED_STATE(Riva,PTIMER); - switch (chip->Architecture) - { - case NV_ARCH_03: - /* - * Make sure frame buffer config gets set before loading PRAMIN. - */ - NV_WR32(chip->PFB, 0x00000200, state->config); - LOAD_FIXED_STATE(nv3,PFIFO); - LOAD_FIXED_STATE(nv3,PRAMIN); - LOAD_FIXED_STATE(nv3,PGRAPH); - switch (state->bpp) - { - case 15: - case 16: - LOAD_FIXED_STATE_15BPP(nv3,PRAMIN); - LOAD_FIXED_STATE_15BPP(nv3,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 24: - case 32: - LOAD_FIXED_STATE_32BPP(nv3,PRAMIN); - LOAD_FIXED_STATE_32BPP(nv3,PGRAPH); - chip->Tri03 = NULL; - break; - case 8: - default: - LOAD_FIXED_STATE_8BPP(nv3,PRAMIN); - LOAD_FIXED_STATE_8BPP(nv3,PGRAPH); - chip->Tri03 = NULL; - break; - } - for (i = 0x00000; i < 0x00800; i++) - NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); - NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); - NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); - NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); - NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); - NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); - NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); - NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); - NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); - break; - case NV_ARCH_04: - /* - * Make sure frame buffer config gets set before loading PRAMIN. - */ - NV_WR32(chip->PFB, 0x00000200, state->config); - LOAD_FIXED_STATE(nv4,PFIFO); - LOAD_FIXED_STATE(nv4,PRAMIN); - LOAD_FIXED_STATE(nv4,PGRAPH); - switch (state->bpp) - { - case 15: - LOAD_FIXED_STATE_15BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_15BPP(nv4,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 16: - LOAD_FIXED_STATE_16BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_16BPP(nv4,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 24: - case 32: - LOAD_FIXED_STATE_32BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_32BPP(nv4,PGRAPH); - chip->Tri03 = NULL; - break; - case 8: - default: - LOAD_FIXED_STATE_8BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_8BPP(nv4,PGRAPH); - chip->Tri03 = NULL; - break; - } - NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); - NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); - NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); - NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); - NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); - NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); - NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); - NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - if(chip->twoHeads) { - VGA_WR08(chip->PCIO, 0x03D4, 0x44); - VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); - chip->LockUnlock(chip, 0); - } - - LOAD_FIXED_STATE(nv10,PFIFO); - LOAD_FIXED_STATE(nv10,PRAMIN); - LOAD_FIXED_STATE(nv10,PGRAPH); - switch (state->bpp) - { - case 15: - LOAD_FIXED_STATE_15BPP(nv10,PRAMIN); - LOAD_FIXED_STATE_15BPP(nv10,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 16: - LOAD_FIXED_STATE_16BPP(nv10,PRAMIN); - LOAD_FIXED_STATE_16BPP(nv10,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 24: - case 32: - LOAD_FIXED_STATE_32BPP(nv10,PRAMIN); - LOAD_FIXED_STATE_32BPP(nv10,PGRAPH); - chip->Tri03 = NULL; - break; - case 8: - default: - LOAD_FIXED_STATE_8BPP(nv10,PRAMIN); - LOAD_FIXED_STATE_8BPP(nv10,PGRAPH); - chip->Tri03 = NULL; - break; - } - - if(chip->Architecture == NV_ARCH_10) { - NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); - NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); - NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); - NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); - NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); - NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); - NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); - NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); - NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); - } else { - NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); - NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); - NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); - NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); - NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); - NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); - NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); - NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); - NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); - NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); - NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); - NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); - } - if(chip->twoHeads) { - NV_WR32(chip->PCRTC0, 0x00000860, state->head); - NV_WR32(chip->PCRTC0, 0x00002860, state->head2); - } - NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); - - NV_WR32(chip->PMC, 0x00008704, 1); - NV_WR32(chip->PMC, 0x00008140, 0); - NV_WR32(chip->PMC, 0x00008920, 0); - NV_WR32(chip->PMC, 0x00008924, 0); - NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); - NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); - NV_WR32(chip->PMC, 0x00001588, 0); - - NV_WR32(chip->PFB, 0x00000240, 0); - NV_WR32(chip->PFB, 0x00000250, 0); - NV_WR32(chip->PFB, 0x00000260, 0); - NV_WR32(chip->PFB, 0x00000270, 0); - NV_WR32(chip->PFB, 0x00000280, 0); - NV_WR32(chip->PFB, 0x00000290, 0); - NV_WR32(chip->PFB, 0x000002A0, 0); - NV_WR32(chip->PFB, 0x000002B0, 0); - - NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); - NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); - NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); - NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); - NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); - NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); - NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); - NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); - NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); - NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); - NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); - NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); - NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); - NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); - NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); - NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); - NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); - NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); - NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); - NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); - NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); - NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); - NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); - NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); - NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); - NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); - NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); - NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); - NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); - NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); - NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); - NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); - NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); - NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); - for (i = 0; i < (3*16); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); - for (i = 0; i < (16*16); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); - NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); - for (i = 0; i < (59*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); - for (i = 0; i < (47*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); - for (i = 0; i < (3*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); - for (i = 0; i < (19*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); - for (i = 0; i < (12*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); - for (i = 0; i < (12*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); - for (i = 0; i < (8*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); - for (i = 0; i < 16; i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); - for (i = 0; i < 4; i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - - NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); - - if(chip->flatPanel) { - if((chip->Chipset & 0x0ff0) == 0x0110) { - NV_WR32(chip->PRAMDAC, 0x0528, state->dither); - } else - if((chip->Chipset & 0x0ff0) >= 0x0170) { - NV_WR32(chip->PRAMDAC, 0x083C, state->dither); - } - - VGA_WR08(chip->PCIO, 0x03D4, 0x53); - VGA_WR08(chip->PCIO, 0x03D5, 0); - VGA_WR08(chip->PCIO, 0x03D4, 0x54); - VGA_WR08(chip->PCIO, 0x03D5, 0); - VGA_WR08(chip->PCIO, 0x03D4, 0x21); - VGA_WR08(chip->PCIO, 0x03D5, 0xfa); - } - - VGA_WR08(chip->PCIO, 0x03D4, 0x41); - VGA_WR08(chip->PCIO, 0x03D5, state->extra); - } - LOAD_FIXED_STATE(Riva,FIFO); - UpdateFifoState(chip); - /* - * Load HW mode state. - */ - VGA_WR08(chip->PCIO, 0x03D4, 0x19); - VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); - VGA_WR08(chip->PCIO, 0x03D4, 0x1A); - VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); - VGA_WR08(chip->PCIO, 0x03D4, 0x25); - VGA_WR08(chip->PCIO, 0x03D5, state->screen); - VGA_WR08(chip->PCIO, 0x03D4, 0x28); - VGA_WR08(chip->PCIO, 0x03D5, state->pixel); - VGA_WR08(chip->PCIO, 0x03D4, 0x2D); - VGA_WR08(chip->PCIO, 0x03D5, state->horiz); - VGA_WR08(chip->PCIO, 0x03D4, 0x1B); - VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); - VGA_WR08(chip->PCIO, 0x03D4, 0x20); - VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); - VGA_WR08(chip->PCIO, 0x03D4, 0x30); - VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); - VGA_WR08(chip->PCIO, 0x03D4, 0x31); - VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); - VGA_WR08(chip->PCIO, 0x03D4, 0x2F); - VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); - VGA_WR08(chip->PCIO, 0x03D4, 0x39); - VGA_WR08(chip->PCIO, 0x03D5, state->interlace); - - if(!chip->flatPanel) { - NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); - NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); - if(chip->twoHeads) - NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); - } else { - NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); - } - NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); - - /* - * Turn off VBlank enable and reset. - */ - NV_WR32(chip->PCRTC, 0x00000140, 0); - NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); - /* - * Set interrupt enable. - */ - NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); - /* - * Set current state pointer. - */ - chip->CurrentState = state; - /* - * Reset FIFO free and empty counts. - */ - chip->FifoFreeCount = 0; - /* Free count from first subchannel */ - chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); -} -static void UnloadStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state -) -{ - /* - * Save current HW state. - */ - VGA_WR08(chip->PCIO, 0x03D4, 0x19); - state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x1A); - state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x25); - state->screen = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x28); - state->pixel = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x2D); - state->horiz = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x1B); - state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x20); - state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x30); - state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x31); - state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x2F); - state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x39); - state->interlace = VGA_RD08(chip->PCIO, 0x03D5); - state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); - state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); - state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); - state->general = NV_RD32(chip->PRAMDAC, 0x00000600); - state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); - state->config = NV_RD32(chip->PFB, 0x00000200); - switch (chip->Architecture) - { - case NV_ARCH_03: - state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); - state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); - state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); - state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); - state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); - state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); - state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); - state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); - break; - case NV_ARCH_04: - state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); - state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); - state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); - state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); - state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); - state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); - state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); - state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); - state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); - state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); - state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); - state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); - state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); - state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); - state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); - if(chip->twoHeads) { - state->head = NV_RD32(chip->PCRTC0, 0x00000860); - state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); - VGA_WR08(chip->PCIO, 0x03D4, 0x44); - state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); - } - VGA_WR08(chip->PCIO, 0x03D4, 0x41); - state->extra = VGA_RD08(chip->PCIO, 0x03D5); - state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); - - if((chip->Chipset & 0x0ff0) == 0x0110) { - state->dither = NV_RD32(chip->PRAMDAC, 0x0528); - } else - if((chip->Chipset & 0x0ff0) >= 0x0170) { - state->dither = NV_RD32(chip->PRAMDAC, 0x083C); - } - break; - } -} -static void SetStartAddress -( - RIVA_HW_INST *chip, - unsigned start -) -{ - NV_WR32(chip->PCRTC, 0x800, start); -} - -static void SetStartAddress3 -( - RIVA_HW_INST *chip, - unsigned start -) -{ - int offset = start >> 2; - int pan = (start & 3) << 1; - unsigned char tmp; - - /* - * Unlock extended registers. - */ - chip->LockUnlock(chip, 0); - /* - * Set start address. - */ - VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); - offset >>= 8; - VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); - offset >>= 8; - VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); - VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); - VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); - VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); - /* - * 4 pixel pan register. - */ - offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); - VGA_WR08(chip->PCIO, 0x3C0, 0x13); - VGA_WR08(chip->PCIO, 0x3C0, pan); -} -static void nv3SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - RIVA_FIFO_FREE(*chip,Tri03,5); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); -} -static void nv4SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); -} -static void nv10SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); -} -static void nv3SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - RIVA_FIFO_FREE(*chip,Tri03,5); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); -} -static void nv4SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); -} -static void nv10SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface3D __iomem *Surfaces3D = - (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); - - RIVA_FIFO_FREE(*chip,Tri03,4); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); - NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0); - NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); -} - -/****************************************************************************\ -* * -* Probe RIVA Chip Configuration * -* * -\****************************************************************************/ - -static void nv3GetConfig -( - RIVA_HW_INST *chip -) -{ - /* - * Fill in chip configuration. - */ - if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) - { - if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) - && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) - { - /* - * SDRAM 128 ZX. - */ - chip->RamBandwidthKBytesPerSec = 800000; - switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) - { - case 2: - chip->RamAmountKBytes = 1024 * 4; - break; - case 1: - chip->RamAmountKBytes = 1024 * 2; - break; - default: - chip->RamAmountKBytes = 1024 * 8; - break; - } - } - else - { - chip->RamBandwidthKBytesPerSec = 1000000; - chip->RamAmountKBytes = 1024 * 8; - } - } - else - { - /* - * SGRAM 128. - */ - chip->RamBandwidthKBytesPerSec = 1000000; - switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) - { - case 0: - chip->RamAmountKBytes = 1024 * 8; - break; - case 2: - chip->RamAmountKBytes = 1024 * 4; - break; - default: - chip->RamAmountKBytes = 1024 * 2; - break; - } - } - chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; - chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); - chip->VBlankBit = 0x00000100; - chip->MaxVClockFreqKHz = 256000; - /* - * Set chip functions. - */ - chip->Busy = nv3Busy; - chip->ShowHideCursor = ShowHideCursor; - chip->CalcStateExt = CalcStateExt; - chip->LoadStateExt = LoadStateExt; - chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress3; - chip->SetSurfaces2D = nv3SetSurfaces2D; - chip->SetSurfaces3D = nv3SetSurfaces3D; - chip->LockUnlock = nv3LockUnlock; -} -static void nv4GetConfig -( - RIVA_HW_INST *chip -) -{ - /* - * Fill in chip configuration. - */ - if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) - { - chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 - + 1024 * 2; - } - else - { - switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) - { - case 0: - chip->RamAmountKBytes = 1024 * 32; - break; - case 1: - chip->RamAmountKBytes = 1024 * 4; - break; - case 2: - chip->RamAmountKBytes = 1024 * 8; - break; - case 3: - default: - chip->RamAmountKBytes = 1024 * 16; - break; - } - } - switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) - { - case 3: - chip->RamBandwidthKBytesPerSec = 800000; - break; - default: - chip->RamBandwidthKBytesPerSec = 1000000; - break; - } - chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; - chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); - chip->VBlankBit = 0x00000001; - chip->MaxVClockFreqKHz = 350000; - /* - * Set chip functions. - */ - chip->Busy = nv4Busy; - chip->ShowHideCursor = ShowHideCursor; - chip->CalcStateExt = CalcStateExt; - chip->LoadStateExt = LoadStateExt; - chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv4SetSurfaces2D; - chip->SetSurfaces3D = nv4SetSurfaces3D; - chip->LockUnlock = nv4LockUnlock; -} -static void nv10GetConfig -( - RIVA_HW_INST *chip, - unsigned int chipset -) -{ - struct pci_dev* dev; - int amt; - -#ifdef __BIG_ENDIAN - /* turn on big endian register access */ - if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) - NV_WR32(chip->PMC, 0x00000004, 0x01000001); -#endif - - /* - * Fill in chip configuration. - */ - if(chipset == NV_CHIP_IGEFORCE2) { - dev = pci_find_slot(0, 1); - pci_read_config_dword(dev, 0x7C, &amt); - chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; - } else if(chipset == NV_CHIP_0x01F0) { - dev = pci_find_slot(0, 1); - pci_read_config_dword(dev, 0x84, &amt); - chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; - } else { - switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) - { - case 0x02: - chip->RamAmountKBytes = 1024 * 2; - break; - case 0x04: - chip->RamAmountKBytes = 1024 * 4; - break; - case 0x08: - chip->RamAmountKBytes = 1024 * 8; - break; - case 0x10: - chip->RamAmountKBytes = 1024 * 16; - break; - case 0x20: - chip->RamAmountKBytes = 1024 * 32; - break; - case 0x40: - chip->RamAmountKBytes = 1024 * 64; - break; - case 0x80: - chip->RamAmountKBytes = 1024 * 128; - break; - default: - chip->RamAmountKBytes = 1024 * 16; - break; - } - } - switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) - { - case 3: - chip->RamBandwidthKBytesPerSec = 800000; - break; - default: - chip->RamBandwidthKBytesPerSec = 1000000; - break; - } - chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? - 14318 : 13500; - - switch (chipset & 0x0ff0) { - case 0x0170: - case 0x0180: - case 0x01F0: - case 0x0250: - case 0x0280: - case 0x0300: - case 0x0310: - case 0x0320: - case 0x0330: - case 0x0340: - if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) - chip->CrystalFreqKHz = 27000; - break; - default: - break; - } - - chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; - chip->CURSOR = NULL; /* can't set this here */ - chip->VBlankBit = 0x00000001; - chip->MaxVClockFreqKHz = 350000; - /* - * Set chip functions. - */ - chip->Busy = nv10Busy; - chip->ShowHideCursor = ShowHideCursor; - chip->CalcStateExt = CalcStateExt; - chip->LoadStateExt = LoadStateExt; - chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv10SetSurfaces2D; - chip->SetSurfaces3D = nv10SetSurfaces3D; - chip->LockUnlock = nv4LockUnlock; - - switch(chipset & 0x0ff0) { - case 0x0110: - case 0x0170: - case 0x0180: - case 0x01F0: - case 0x0250: - case 0x0280: - case 0x0300: - case 0x0310: - case 0x0320: - case 0x0330: - case 0x0340: - chip->twoHeads = TRUE; - break; - default: - chip->twoHeads = FALSE; - break; - } -} -int RivaGetConfig -( - RIVA_HW_INST *chip, - unsigned int chipset -) -{ - /* - * Save this so future SW know whats it's dealing with. - */ - chip->Version = RIVA_SW_VERSION; - /* - * Chip specific configuration. - */ - switch (chip->Architecture) - { - case NV_ARCH_03: - nv3GetConfig(chip); - break; - case NV_ARCH_04: - nv4GetConfig(chip); - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - nv10GetConfig(chip, chipset); - break; - default: - return (-1); - } - chip->Chipset = chipset; - /* - * Fill in FIFO pointers. - */ - chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); - chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); - chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); - chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); - chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); - chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); - chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - return (0); -} - diff --git a/drivers/video/riva/riva_hw.h b/drivers/video/riva/riva_hw.h deleted file mode 100644 index a1e71a626df..00000000000 --- a/drivers/video/riva/riva_hw.h +++ /dev/null @@ -1,548 +0,0 @@ -/***************************************************************************\ -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| -\***************************************************************************/ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */ -#ifndef __RIVA_HW_H__ -#define __RIVA_HW_H__ -#define RIVA_SW_VERSION 0x00010003 - -#ifndef Bool -typedef int Bool; -#endif - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif -#ifndef NULL -#define NULL 0 -#endif - -/* - * Typedefs to force certain sized values. - */ -typedef unsigned char U008; -typedef unsigned short U016; -typedef unsigned int U032; - -/* - * HW access macros. - */ -#include <asm/io.h> - -#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i))) -#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i))) -#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i))) -#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i))) -#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i))) -#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) - -#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i))) -#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i))) - -/* - * Define different architectures. - */ -#define NV_ARCH_03 0x03 -#define NV_ARCH_04 0x04 -#define NV_ARCH_10 0x10 -#define NV_ARCH_20 0x20 -#define NV_ARCH_30 0x30 -#define NV_ARCH_40 0x40 - -/***************************************************************************\ -* * -* FIFO registers. * -* * -\***************************************************************************/ - -/* - * Raster OPeration. Windows style ROP3. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 Rop3; -} RivaRop; -/* - * 8X8 Monochrome pattern. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BD]; - U032 Shape; - U032 reserved03[0x001]; - U032 Color0; - U032 Color1; - U032 Monochrome[2]; -} RivaPattern; -/* - * Scissor clip rectangle. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 TopLeft; - U032 WidthHeight; -} RivaClip; -/* - * 2D filled rectangle. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop[1]; -#endif - U032 reserved01[0x0BC]; - U032 Color; - U032 reserved03[0x03E]; - U032 TopLeft; - U032 WidthHeight; -} RivaRectangle; -/* - * 2D screen-screen BLT. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 TopLeftSrc; - U032 TopLeftDst; - U032 WidthHeight; -} RivaScreenBlt; -/* - * 2D pixel BLT. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop[1]; -#endif - U032 reserved01[0x0BC]; - U032 TopLeft; - U032 WidthHeight; - U032 WidthHeightIn; - U032 reserved02[0x03C]; - U032 Pixels; -} RivaPixmap; -/* - * Filled rectangle combined with monochrome expand. Useful for glyphs. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 reserved03[(0x040)-1]; - U032 Color1A; - struct - { - U032 TopLeft; - U032 WidthHeight; - } UnclippedRectangle[64]; - U032 reserved04[(0x080)-3]; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClipB; - U032 Color1B; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClippedRectangle[64]; - U032 reserved05[(0x080)-5]; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClipC; - U032 Color1C; - U032 WidthHeightC; - U032 PointC; - U032 MonochromeData1C; - U032 reserved06[(0x080)+121]; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClipD; - U032 Color1D; - U032 WidthHeightInD; - U032 WidthHeightOutD; - U032 PointD; - U032 MonochromeData1D; - U032 reserved07[(0x080)+120]; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClipE; - U032 Color0E; - U032 Color1E; - U032 WidthHeightInE; - U032 WidthHeightOutE; - U032 PointE; - U032 MonochromeData01E; -} RivaBitmap; -/* - * 3D textured, Z buffered triangle. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BC]; - U032 TextureOffset; - U032 TextureFormat; - U032 TextureFilter; - U032 FogColor; -/* This is a problem on LynxOS */ -#ifdef Control -#undef Control -#endif - U032 Control; - U032 AlphaTest; - U032 reserved02[0x339]; - U032 FogAndIndex; - U032 Color; - float ScreenX; - float ScreenY; - float ScreenZ; - float EyeM; - float TextureS; - float TextureT; -} RivaTexturedTriangle03; -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 ColorKey; - U032 TextureOffset; - U032 TextureFormat; - U032 TextureFilter; - U032 Blend; -/* This is a problem on LynxOS */ -#ifdef Control -#undef Control -#endif - U032 Control; - U032 FogColor; - U032 reserved02[0x39]; - struct - { - float ScreenX; - float ScreenY; - float ScreenZ; - float EyeM; - U032 Color; - U032 Specular; - float TextureS; - float TextureT; - } Vertex[16]; - U032 DrawTriangle3D; -} RivaTexturedTriangle05; -/* - * 2D line. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop[1]; -#endif - U032 reserved01[0x0BC]; - U032 Color; /* source color 0304-0307*/ - U032 Reserved02[0x03e]; - struct { /* start aliased methods in array 0400- */ - U032 point0; /* y_x S16_S16 in pixels 0- 3*/ - U032 point1; /* y_x S16_S16 in pixels 4- 7*/ - } Lin[16]; /* end of aliased methods in array -047f*/ - struct { /* start aliased methods in array 0480- */ - U032 point0X; /* in pixels, 0 at left 0- 3*/ - U032 point0Y; /* in pixels, 0 at top 4- 7*/ - U032 point1X; /* in pixels, 0 at left 8- b*/ - U032 point1Y; /* in pixels, 0 at top c- f*/ - } Lin32[8]; /* end of aliased methods in array -04ff*/ - U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/ - struct { /* start aliased methods in array 0580- */ - U032 x; /* in pixels, 0 at left 0- 3*/ - U032 y; /* in pixels, 0 at top 4- 7*/ - } PolyLin32[16]; /* end of aliased methods in array -05ff*/ - struct { /* start aliased methods in array 0600- */ - U032 color; /* source color 0- 3*/ - U032 point; /* y_x S16_S16 in pixels 4- 7*/ - } ColorPolyLin[16]; /* end of aliased methods in array -067f*/ -} RivaLine; -/* - * 2D/3D surfaces - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BE]; - U032 Offset; -} RivaSurface; -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BD]; - U032 Pitch; - U032 RenderBufferOffset; - U032 ZBufferOffset; -} RivaSurface3D; - -/***************************************************************************\ -* * -* Virtualized RIVA H/W interface. * -* * -\***************************************************************************/ - -#define FP_ENABLE 1 -#define FP_DITHER 2 - -struct _riva_hw_inst; -struct _riva_hw_state; -/* - * Virtialized chip interface. Makes RIVA 128 and TNT look alike. - */ -typedef struct _riva_hw_inst -{ - /* - * Chip specific settings. - */ - U032 Architecture; - U032 Version; - U032 Chipset; - U032 CrystalFreqKHz; - U032 RamAmountKBytes; - U032 MaxVClockFreqKHz; - U032 RamBandwidthKBytesPerSec; - U032 EnableIRQ; - U032 IO; - U032 VBlankBit; - U032 FifoFreeCount; - U032 FifoEmptyCount; - U032 CursorStart; - U032 flatPanel; - Bool twoHeads; - /* - * Non-FIFO registers. - */ - volatile U032 __iomem *PCRTC0; - volatile U032 __iomem *PCRTC; - volatile U032 __iomem *PRAMDAC0; - volatile U032 __iomem *PFB; - volatile U032 __iomem *PFIFO; - volatile U032 __iomem *PGRAPH; - volatile U032 __iomem *PEXTDEV; - volatile U032 __iomem *PTIMER; - volatile U032 __iomem *PMC; - volatile U032 __iomem *PRAMIN; - volatile U032 __iomem *FIFO; - volatile U032 __iomem *CURSOR; - volatile U008 __iomem *PCIO0; - volatile U008 __iomem *PCIO; - volatile U008 __iomem *PVIO; - volatile U008 __iomem *PDIO0; - volatile U008 __iomem *PDIO; - volatile U032 __iomem *PRAMDAC; - /* - * Common chip functions. - */ - int (*Busy)(struct _riva_hw_inst *); - void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int); - void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); - void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); - void (*SetStartAddress)(struct _riva_hw_inst *,U032); - void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032); - void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032); - int (*ShowHideCursor)(struct _riva_hw_inst *,int); - void (*LockUnlock)(struct _riva_hw_inst *, int); - /* - * Current extended mode settings. - */ - struct _riva_hw_state *CurrentState; - /* - * FIFO registers. - */ - RivaRop __iomem *Rop; - RivaPattern __iomem *Patt; - RivaClip __iomem *Clip; - RivaPixmap __iomem *Pixmap; - RivaScreenBlt __iomem *Blt; - RivaBitmap __iomem *Bitmap; - RivaLine __iomem *Line; - RivaTexturedTriangle03 __iomem *Tri03; - RivaTexturedTriangle05 __iomem *Tri05; -} RIVA_HW_INST; -/* - * Extended mode state information. - */ -typedef struct _riva_hw_state -{ - U032 bpp; - U032 width; - U032 height; - U032 interlace; - U032 repaint0; - U032 repaint1; - U032 screen; - U032 scale; - U032 dither; - U032 extra; - U032 pixel; - U032 horiz; - U032 arbitration0; - U032 arbitration1; - U032 vpll; - U032 vpll2; - U032 pllsel; - U032 general; - U032 crtcOwner; - U032 head; - U032 head2; - U032 config; - U032 cursorConfig; - U032 cursor0; - U032 cursor1; - U032 cursor2; - U032 offset0; - U032 offset1; - U032 offset2; - U032 offset3; - U032 pitch0; - U032 pitch1; - U032 pitch2; - U032 pitch3; -} RIVA_HW_STATE; -/* - * External routines. - */ -int RivaGetConfig(RIVA_HW_INST *, unsigned int); -/* - * FIFO Free Count. Should attempt to yield processor if RIVA is busy. - */ - -#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \ -{ \ - while ((hwinst).FifoFreeCount < (cnt)) { \ - mb();mb(); \ - (hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \ - } \ - (hwinst).FifoFreeCount -= (cnt); \ -} -#endif /* __RIVA_HW_H__ */ - diff --git a/drivers/video/riva/riva_tbl.h b/drivers/video/riva/riva_tbl.h deleted file mode 100644 index 7ee7d72932d..00000000000 --- a/drivers/video/riva/riva_tbl.h +++ /dev/null @@ -1,1008 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.9 2002/01/30 01:35:03 mvojkovi Exp $ */ - - -/* - * RIVA Fixed Functionality Init Tables. - */ -static unsigned RivaTablePMC[][2] = -{ - {0x00000050, 0x00000000}, - {0x00000080, 0xFFFF00FF}, - {0x00000080, 0xFFFFFFFF} -}; -static unsigned RivaTablePTIMER[][2] = -{ - {0x00000080, 0x00000008}, - {0x00000084, 0x00000003}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF} -}; -static unsigned RivaTableFIFO[][2] = -{ - {0x00000000, 0x80000000}, - {0x00000800, 0x80000001}, - {0x00001000, 0x80000002}, - {0x00001800, 0x80000010}, - {0x00002000, 0x80000011}, - {0x00002800, 0x80000012}, - {0x00003000, 0x80000016}, - {0x00003800, 0x80000013} -}; -static unsigned nv3TablePFIFO[][2] = -{ - {0x00000140, 0x00000000}, - {0x00000480, 0x00000000}, - {0x00000490, 0x00000000}, - {0x00000494, 0x00000000}, - {0x00000481, 0x00000000}, - {0x00000084, 0x00000000}, - {0x00000086, 0x00002000}, - {0x00000085, 0x00002200}, - {0x00000484, 0x00000000}, - {0x0000049C, 0x00000000}, - {0x00000104, 0x00000000}, - {0x00000108, 0x00000000}, - {0x00000100, 0x00000000}, - {0x000004A0, 0x00000000}, - {0x000004A4, 0x00000000}, - {0x000004A8, 0x00000000}, - {0x000004AC, 0x00000000}, - {0x000004B0, 0x00000000}, - {0x000004B4, 0x00000000}, - {0x000004B8, 0x00000000}, - {0x000004BC, 0x00000000}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000480, 0x00000001}, - {0x00000490, 0x00000001}, - {0x00000140, 0x00000001} -}; -static unsigned nv3TablePGRAPH[][2] = -{ - {0x00000020, 0x1230001F}, - {0x00000021, 0x10113000}, - {0x00000022, 0x1131F101}, - {0x00000023, 0x0100F531}, - {0x00000060, 0x00000000}, - {0x00000065, 0x00000000}, - {0x00000068, 0x00000000}, - {0x00000069, 0x00000000}, - {0x0000006A, 0x00000000}, - {0x0000006B, 0x00000000}, - {0x0000006C, 0x00000000}, - {0x0000006D, 0x00000000}, - {0x0000006E, 0x00000000}, - {0x0000006F, 0x00000000}, - {0x000001A8, 0x00000000}, - {0x00000440, 0xFFFFFFFF}, - {0x00000480, 0x00000001}, - {0x000001A0, 0x00000000}, - {0x000001A2, 0x00000000}, - {0x0000018A, 0xFFFFFFFF}, - {0x00000190, 0x00000000}, - {0x00000142, 0x00000000}, - {0x00000154, 0x00000000}, - {0x00000155, 0xFFFFFFFF}, - {0x00000156, 0x00000000}, - {0x00000157, 0xFFFFFFFF}, - {0x00000064, 0x10010002}, - {0x00000050, 0x00000000}, - {0x00000051, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000041, 0xFFFFFFFF}, - {0x00000440, 0xFFFFFFFF}, - {0x000001A9, 0x00000001} -}; -static unsigned nv3TablePGRAPH_8BPP[][2] = -{ - {0x000001AA, 0x00001111} -}; -static unsigned nv3TablePGRAPH_15BPP[][2] = -{ - {0x000001AA, 0x00002222} -}; -static unsigned nv3TablePGRAPH_32BPP[][2] = -{ - {0x000001AA, 0x00003333} -}; -static unsigned nv3TablePRAMIN[][2] = -{ - {0x00000500, 0x00010000}, - {0x00000501, 0x007FFFFF}, - {0x00000200, 0x80000000}, - {0x00000201, 0x00C20341}, - {0x00000204, 0x80000001}, - {0x00000205, 0x00C50342}, - {0x00000208, 0x80000002}, - {0x00000209, 0x00C60343}, - {0x0000020C, 0x80000003}, - {0x0000020D, 0x00DC0348}, - {0x00000210, 0x80000004}, - {0x00000211, 0x00DC0349}, - {0x00000214, 0x80000005}, - {0x00000215, 0x00DC034A}, - {0x00000218, 0x80000006}, - {0x00000219, 0x00DC034B}, - {0x00000240, 0x80000010}, - {0x00000241, 0x00D10344}, - {0x00000244, 0x80000011}, - {0x00000245, 0x00D00345}, - {0x00000248, 0x80000012}, - {0x00000249, 0x00CC0346}, - {0x0000024C, 0x80000013}, - {0x0000024D, 0x00D70347}, - {0x00000258, 0x80000016}, - {0x00000259, 0x00CA034C}, - {0x00000D05, 0x00000000}, - {0x00000D06, 0x00000000}, - {0x00000D07, 0x00000000}, - {0x00000D09, 0x00000000}, - {0x00000D0A, 0x00000000}, - {0x00000D0B, 0x00000000}, - {0x00000D0D, 0x00000000}, - {0x00000D0E, 0x00000000}, - {0x00000D0F, 0x00000000}, - {0x00000D11, 0x00000000}, - {0x00000D12, 0x00000000}, - {0x00000D13, 0x00000000}, - {0x00000D15, 0x00000000}, - {0x00000D16, 0x00000000}, - {0x00000D17, 0x00000000}, - {0x00000D19, 0x00000000}, - {0x00000D1A, 0x00000000}, - {0x00000D1B, 0x00000000}, - {0x00000D1D, 0x00000140}, - {0x00000D1E, 0x00000000}, - {0x00000D1F, 0x00000000}, - {0x00000D20, 0x10100200}, - {0x00000D21, 0x00000000}, - {0x00000D22, 0x00000000}, - {0x00000D23, 0x00000000}, - {0x00000D24, 0x10210200}, - {0x00000D25, 0x00000000}, - {0x00000D26, 0x00000000}, - {0x00000D27, 0x00000000}, - {0x00000D28, 0x10420200}, - {0x00000D29, 0x00000000}, - {0x00000D2A, 0x00000000}, - {0x00000D2B, 0x00000000}, - {0x00000D2C, 0x10830200}, - {0x00000D2D, 0x00000000}, - {0x00000D2E, 0x00000000}, - {0x00000D2F, 0x00000000}, - {0x00000D31, 0x00000000}, - {0x00000D32, 0x00000000}, - {0x00000D33, 0x00000000} -}; -static unsigned nv3TablePRAMIN_8BPP[][2] = -{ - /* 0xXXXXX3XX For MSB mono format */ - /* 0xXXXXX2XX For LSB mono format */ - {0x00000D04, 0x10110203}, - {0x00000D08, 0x10110203}, - {0x00000D0C, 0x1011020B}, - {0x00000D10, 0x10118203}, - {0x00000D14, 0x10110203}, - {0x00000D18, 0x10110203}, - {0x00000D1C, 0x10419208}, - {0x00000D30, 0x10118203} -}; -static unsigned nv3TablePRAMIN_15BPP[][2] = -{ - /* 0xXXXXX2XX For MSB mono format */ - /* 0xXXXXX3XX For LSB mono format */ - {0x00000D04, 0x10110200}, - {0x00000D08, 0x10110200}, - {0x00000D0C, 0x10110208}, - {0x00000D10, 0x10118200}, - {0x00000D14, 0x10110200}, - {0x00000D18, 0x10110200}, - {0x00000D1C, 0x10419208}, - {0x00000D30, 0x10118200} -}; -static unsigned nv3TablePRAMIN_32BPP[][2] = -{ - /* 0xXXXXX3XX For MSB mono format */ - /* 0xXXXXX2XX For LSB mono format */ - {0x00000D04, 0x10110201}, - {0x00000D08, 0x10110201}, - {0x00000D0C, 0x10110209}, - {0x00000D10, 0x10118201}, - {0x00000D14, 0x10110201}, - {0x00000D18, 0x10110201}, - {0x00000D1C, 0x10419208}, - {0x00000D30, 0x10118201} -}; -static unsigned nv4TableFIFO[][2] = -{ - {0x00003800, 0x80000014} -}; -static unsigned nv4TablePFIFO[][2] = -{ - {0x00000140, 0x00000000}, - {0x00000480, 0x00000000}, - {0x00000494, 0x00000000}, - {0x00000481, 0x00000000}, - {0x0000048B, 0x00000000}, - {0x00000400, 0x00000000}, - {0x00000414, 0x00000000}, - {0x00000084, 0x03000100}, - {0x00000085, 0x00000110}, - {0x00000086, 0x00000112}, - {0x00000143, 0x0000FFFF}, - {0x00000496, 0x0000FFFF}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000415, 0x00000001}, - {0x00000480, 0x00000001}, - {0x00000494, 0x00000001}, - {0x00000495, 0x00000001}, - {0x00000140, 0x00000001} -}; -static unsigned nv4TablePGRAPH[][2] = -{ - {0x00000020, 0x1231C001}, - {0x00000021, 0x72111101}, - {0x00000022, 0x11D5F071}, - {0x00000023, 0x10D4FF31}, - {0x00000060, 0x00000000}, - {0x00000068, 0x00000000}, - {0x00000070, 0x00000000}, - {0x00000078, 0x00000000}, - {0x00000061, 0x00000000}, - {0x00000069, 0x00000000}, - {0x00000071, 0x00000000}, - {0x00000079, 0x00000000}, - {0x00000062, 0x00000000}, - {0x0000006A, 0x00000000}, - {0x00000072, 0x00000000}, - {0x0000007A, 0x00000000}, - {0x00000063, 0x00000000}, - {0x0000006B, 0x00000000}, - {0x00000073, 0x00000000}, - {0x0000007B, 0x00000000}, - {0x00000064, 0x00000000}, - {0x0000006C, 0x00000000}, - {0x00000074, 0x00000000}, - {0x0000007C, 0x00000000}, - {0x00000065, 0x00000000}, - {0x0000006D, 0x00000000}, - {0x00000075, 0x00000000}, - {0x0000007D, 0x00000000}, - {0x00000066, 0x00000000}, - {0x0000006E, 0x00000000}, - {0x00000076, 0x00000000}, - {0x0000007E, 0x00000000}, - {0x00000067, 0x00000000}, - {0x0000006F, 0x00000000}, - {0x00000077, 0x00000000}, - {0x0000007F, 0x00000000}, - {0x00000058, 0x00000000}, - {0x00000059, 0x00000000}, - {0x0000005A, 0x00000000}, - {0x0000005B, 0x00000000}, - {0x00000196, 0x00000000}, - {0x000001A1, 0x01FFFFFF}, - {0x00000197, 0x00000000}, - {0x000001A2, 0x01FFFFFF}, - {0x00000198, 0x00000000}, - {0x000001A3, 0x01FFFFFF}, - {0x00000199, 0x00000000}, - {0x000001A4, 0x01FFFFFF}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x0000005C, 0x10010100}, - {0x000001C4, 0xFFFFFFFF}, - {0x000001C8, 0x00000001}, - {0x00000204, 0x00000000}, - {0x000001C3, 0x00000001} -}; -static unsigned nv4TablePGRAPH_8BPP[][2] = -{ - {0x000001C9, 0x00111111}, - {0x00000186, 0x00001010}, - {0x0000020C, 0x03020202} -}; -static unsigned nv4TablePGRAPH_15BPP[][2] = -{ - {0x000001C9, 0x00226222}, - {0x00000186, 0x00002071}, - {0x0000020C, 0x09080808} -}; -static unsigned nv4TablePGRAPH_16BPP[][2] = -{ - {0x000001C9, 0x00556555}, - {0x00000186, 0x000050C2}, - {0x0000020C, 0x0C0B0B0B} -}; -static unsigned nv4TablePGRAPH_32BPP[][2] = -{ - {0x000001C9, 0x0077D777}, - {0x00000186, 0x000070E5}, - {0x0000020C, 0x0E0D0D0D} -}; -static unsigned nv4TablePRAMIN[][2] = -{ - {0x00000000, 0x80000010}, - {0x00000001, 0x80011145}, - {0x00000002, 0x80000011}, - {0x00000003, 0x80011146}, - {0x00000004, 0x80000012}, - {0x00000005, 0x80011147}, - {0x00000006, 0x80000013}, - {0x00000007, 0x80011148}, - {0x00000008, 0x80000014}, - {0x00000009, 0x80011149}, - {0x0000000A, 0x80000015}, - {0x0000000B, 0x8001114A}, - {0x0000000C, 0x80000016}, - {0x0000000D, 0x8001114F}, - {0x00000020, 0x80000000}, - {0x00000021, 0x80011142}, - {0x00000022, 0x80000001}, - {0x00000023, 0x80011143}, - {0x00000024, 0x80000002}, - {0x00000025, 0x80011144}, - {0x00000026, 0x80000003}, - {0x00000027, 0x8001114B}, - {0x00000028, 0x80000004}, - {0x00000029, 0x8001114C}, - {0x0000002A, 0x80000005}, - {0x0000002B, 0x8001114D}, - {0x0000002C, 0x80000006}, - {0x0000002D, 0x8001114E}, - {0x00000500, 0x00003000}, - {0x00000501, 0x01FFFFFF}, - {0x00000502, 0x00000002}, - {0x00000503, 0x00000002}, - {0x00000508, 0x01008043}, - {0x0000050A, 0x00000000}, - {0x0000050B, 0x00000000}, - {0x0000050C, 0x01008019}, - {0x0000050E, 0x00000000}, - {0x0000050F, 0x00000000}, -#if 1 - {0x00000510, 0x01008018}, -#else - {0x00000510, 0x01008044}, -#endif - {0x00000512, 0x00000000}, - {0x00000513, 0x00000000}, - {0x00000514, 0x01008021}, - {0x00000516, 0x00000000}, - {0x00000517, 0x00000000}, - {0x00000518, 0x0100805F}, - {0x0000051A, 0x00000000}, - {0x0000051B, 0x00000000}, -#if 1 - {0x0000051C, 0x0100804B}, -#else - {0x0000051C, 0x0100804A}, -#endif - {0x0000051E, 0x00000000}, - {0x0000051F, 0x00000000}, - {0x00000520, 0x0100A048}, - {0x00000521, 0x00000D01}, - {0x00000522, 0x11401140}, - {0x00000523, 0x00000000}, - {0x00000524, 0x0300A054}, - {0x00000525, 0x00000D01}, - {0x00000526, 0x11401140}, - {0x00000527, 0x00000000}, - {0x00000528, 0x0300A055}, - {0x00000529, 0x00000D01}, - {0x0000052A, 0x11401140}, - {0x0000052B, 0x00000000}, - {0x0000052C, 0x00000058}, - {0x0000052E, 0x11401140}, - {0x0000052F, 0x00000000}, - {0x00000530, 0x00000059}, - {0x00000532, 0x11401140}, - {0x00000533, 0x00000000}, - {0x00000534, 0x0000005A}, - {0x00000536, 0x11401140}, - {0x00000537, 0x00000000}, - {0x00000538, 0x0000005B}, - {0x0000053A, 0x11401140}, - {0x0000053B, 0x00000000}, - {0x0000053C, 0x0300A01C}, - {0x0000053E, 0x11401140}, - {0x0000053F, 0x00000000} -}; -static unsigned nv4TablePRAMIN_8BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000302}, - {0x0000050D, 0x00000302}, - {0x00000511, 0x00000202}, - {0x00000515, 0x00000302}, - {0x00000519, 0x00000302}, - {0x0000051D, 0x00000302}, - {0x0000052D, 0x00000302}, - {0x0000052E, 0x00000302}, - {0x00000535, 0x00000000}, - {0x00000539, 0x00000000}, - {0x0000053D, 0x00000302} -}; -static unsigned nv4TablePRAMIN_15BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000902}, - {0x0000050D, 0x00000902}, - {0x00000511, 0x00000802}, - {0x00000515, 0x00000902}, - {0x00000519, 0x00000902}, - {0x0000051D, 0x00000902}, - {0x0000052D, 0x00000902}, - {0x0000052E, 0x00000902}, - {0x00000535, 0x00000702}, - {0x00000539, 0x00000702}, - {0x0000053D, 0x00000902} -}; -static unsigned nv4TablePRAMIN_16BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000C02}, - {0x0000050D, 0x00000C02}, - {0x00000511, 0x00000B02}, - {0x00000515, 0x00000C02}, - {0x00000519, 0x00000C02}, - {0x0000051D, 0x00000C02}, - {0x0000052D, 0x00000C02}, - {0x0000052E, 0x00000C02}, - {0x00000535, 0x00000702}, - {0x00000539, 0x00000702}, - {0x0000053D, 0x00000C02} -}; -static unsigned nv4TablePRAMIN_32BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000E02}, - {0x0000050D, 0x00000E02}, - {0x00000511, 0x00000D02}, - {0x00000515, 0x00000E02}, - {0x00000519, 0x00000E02}, - {0x0000051D, 0x00000E02}, - {0x0000052D, 0x00000E02}, - {0x0000052E, 0x00000E02}, - {0x00000535, 0x00000E02}, - {0x00000539, 0x00000E02}, - {0x0000053D, 0x00000E02} -}; -static unsigned nv10TableFIFO[][2] = -{ - {0x00003800, 0x80000014} -}; -static unsigned nv10TablePFIFO[][2] = -{ - {0x00000140, 0x00000000}, - {0x00000480, 0x00000000}, - {0x00000494, 0x00000000}, - {0x00000481, 0x00000000}, - {0x0000048B, 0x00000000}, - {0x00000400, 0x00000000}, - {0x00000414, 0x00000000}, - {0x00000084, 0x03000100}, - {0x00000085, 0x00000110}, - {0x00000086, 0x00000112}, - {0x00000143, 0x0000FFFF}, - {0x00000496, 0x0000FFFF}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000415, 0x00000001}, - {0x00000480, 0x00000001}, - {0x00000494, 0x00000001}, - {0x00000495, 0x00000001}, - {0x00000140, 0x00000001} -}; -static unsigned nv10TablePGRAPH[][2] = -{ - {0x00000020, 0x0003FFFF}, - {0x00000021, 0x00118701}, - {0x00000022, 0x24F82AD9}, - {0x00000023, 0x55DE0030}, - {0x00000020, 0x00000000}, - {0x00000024, 0x00000000}, - {0x00000058, 0x00000000}, - {0x00000060, 0x00000000}, - {0x00000068, 0x00000000}, - {0x00000070, 0x00000000}, - {0x00000078, 0x00000000}, - {0x00000059, 0x00000000}, - {0x00000061, 0x00000000}, - {0x00000069, 0x00000000}, - {0x00000071, 0x00000000}, - {0x00000079, 0x00000000}, - {0x0000005A, 0x00000000}, - {0x00000062, 0x00000000}, - {0x0000006A, 0x00000000}, - {0x00000072, 0x00000000}, - {0x0000007A, 0x00000000}, - {0x0000005B, 0x00000000}, - {0x00000063, 0x00000000}, - {0x0000006B, 0x00000000}, - {0x00000073, 0x00000000}, - {0x0000007B, 0x00000000}, - {0x0000005C, 0x00000000}, - {0x00000064, 0x00000000}, - {0x0000006C, 0x00000000}, - {0x00000074, 0x00000000}, - {0x0000007C, 0x00000000}, - {0x0000005D, 0x00000000}, - {0x00000065, 0x00000000}, - {0x0000006D, 0x00000000}, - {0x00000075, 0x00000000}, - {0x0000007D, 0x00000000}, - {0x0000005E, 0x00000000}, - {0x00000066, 0x00000000}, - {0x0000006E, 0x00000000}, - {0x00000076, 0x00000000}, - {0x0000007E, 0x00000000}, - {0x0000005F, 0x00000000}, - {0x00000067, 0x00000000}, - {0x0000006F, 0x00000000}, - {0x00000077, 0x00000000}, - {0x0000007F, 0x00000000}, - {0x00000053, 0x00000000}, - {0x00000054, 0x00000000}, - {0x00000055, 0x00000000}, - {0x00000056, 0x00000000}, - {0x00000057, 0x00000000}, - {0x00000196, 0x00000000}, - {0x000001A1, 0x01FFFFFF}, - {0x00000197, 0x00000000}, - {0x000001A2, 0x01FFFFFF}, - {0x00000198, 0x00000000}, - {0x000001A3, 0x01FFFFFF}, - {0x00000199, 0x00000000}, - {0x000001A4, 0x01FFFFFF}, - {0x0000019A, 0x00000000}, - {0x000001A5, 0x01FFFFFF}, - {0x0000019B, 0x00000000}, - {0x000001A6, 0x01FFFFFF}, - {0x00000050, 0x01111111}, - {0x00000040, 0xFFFFFFFF}, - {0x00000051, 0x10010100}, - {0x000001C5, 0xFFFFFFFF}, - {0x000001C8, 0x00000001}, - {0x00000204, 0x00000000}, - {0x000001C4, 0x00000001} -}; -static unsigned nv10TablePGRAPH_8BPP[][2] = -{ - {0x000001C9, 0x00111111}, - {0x00000186, 0x00001010}, - {0x0000020C, 0x03020202} -}; -static unsigned nv10TablePGRAPH_15BPP[][2] = -{ - {0x000001C9, 0x00226222}, - {0x00000186, 0x00002071}, - {0x0000020C, 0x09080808} -}; -static unsigned nv10TablePGRAPH_16BPP[][2] = -{ - {0x000001C9, 0x00556555}, - {0x00000186, 0x000050C2}, - {0x0000020C, 0x000B0B0C} -}; -static unsigned nv10TablePGRAPH_32BPP[][2] = -{ - {0x000001C9, 0x0077D777}, - {0x00000186, 0x000070E5}, - {0x0000020C, 0x0E0D0D0D} -}; -static unsigned nv10tri05TablePGRAPH[][2] = -{ - {(0x00000E00/4), 0x00000000}, - {(0x00000E04/4), 0x00000000}, - {(0x00000E08/4), 0x00000000}, - {(0x00000E0C/4), 0x00000000}, - {(0x00000E10/4), 0x00001000}, - {(0x00000E14/4), 0x00001000}, - {(0x00000E18/4), 0x4003ff80}, - {(0x00000E1C/4), 0x00000000}, - {(0x00000E20/4), 0x00000000}, - {(0x00000E24/4), 0x00000000}, - {(0x00000E28/4), 0x00000000}, - {(0x00000E2C/4), 0x00000000}, - {(0x00000E30/4), 0x00080008}, - {(0x00000E34/4), 0x00080008}, - {(0x00000E38/4), 0x00000000}, - {(0x00000E3C/4), 0x00000000}, - {(0x00000E40/4), 0x00000000}, - {(0x00000E44/4), 0x00000000}, - {(0x00000E48/4), 0x00000000}, - {(0x00000E4C/4), 0x00000000}, - {(0x00000E50/4), 0x00000000}, - {(0x00000E54/4), 0x00000000}, - {(0x00000E58/4), 0x00000000}, - {(0x00000E5C/4), 0x00000000}, - {(0x00000E60/4), 0x00000000}, - {(0x00000E64/4), 0x10000000}, - {(0x00000E68/4), 0x00000000}, - {(0x00000E6C/4), 0x00000000}, - {(0x00000E70/4), 0x00000000}, - {(0x00000E74/4), 0x00000000}, - {(0x00000E78/4), 0x00000000}, - {(0x00000E7C/4), 0x00000000}, - {(0x00000E80/4), 0x00000000}, - {(0x00000E84/4), 0x00000000}, - {(0x00000E88/4), 0x08000000}, - {(0x00000E8C/4), 0x00000000}, - {(0x00000E90/4), 0x00000000}, - {(0x00000E94/4), 0x00000000}, - {(0x00000E98/4), 0x00000000}, - {(0x00000E9C/4), 0x4B7FFFFF}, - {(0x00000EA0/4), 0x00000000}, - {(0x00000EA4/4), 0x00000000}, - {(0x00000EA8/4), 0x00000000}, - {(0x00000F00/4), 0x07FF0800}, - {(0x00000F04/4), 0x07FF0800}, - {(0x00000F08/4), 0x07FF0800}, - {(0x00000F0C/4), 0x07FF0800}, - {(0x00000F10/4), 0x07FF0800}, - {(0x00000F14/4), 0x07FF0800}, - {(0x00000F18/4), 0x07FF0800}, - {(0x00000F1C/4), 0x07FF0800}, - {(0x00000F20/4), 0x07FF0800}, - {(0x00000F24/4), 0x07FF0800}, - {(0x00000F28/4), 0x07FF0800}, - {(0x00000F2C/4), 0x07FF0800}, - {(0x00000F30/4), 0x07FF0800}, - {(0x00000F34/4), 0x07FF0800}, - {(0x00000F38/4), 0x07FF0800}, - {(0x00000F3C/4), 0x07FF0800}, - {(0x00000F40/4), 0x10000000}, - {(0x00000F44/4), 0x00000000}, - {(0x00000F50/4), 0x00006740}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006750}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F50/4), 0x00006760}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006770}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006780}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000067A0}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006AB0}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006AC0}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006C10}, - {(0x00000F54/4), 0xBF800000}, - {(0x00000F50/4), 0x00007030}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007040}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007050}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007060}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007070}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007080}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007090}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x000070A0}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00006A80}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006AA0}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00000040}, - {(0x00000F54/4), 0x00000005}, - {(0x00000F50/4), 0x00006400}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x4B7FFFFF}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006410}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006420}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006430}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000064C0}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x477FFFFF}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x000064D0}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000064E0}, - {(0x00000F54/4), 0xC4FFF000}, - {(0x00000F54/4), 0xC4FFF000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000064F0}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F40/4), 0x30000000}, - {(0x00000F44/4), 0x00000004}, - {(0x00000F48/4), 0x10000000}, - {(0x00000F4C/4), 0x00000000} -}; -static unsigned nv10TablePRAMIN[][2] = -{ - {0x00000000, 0x80000010}, - {0x00000001, 0x80011145}, - {0x00000002, 0x80000011}, - {0x00000003, 0x80011146}, - {0x00000004, 0x80000012}, - {0x00000005, 0x80011147}, - {0x00000006, 0x80000013}, - {0x00000007, 0x80011148}, - {0x00000008, 0x80000014}, - {0x00000009, 0x80011149}, - {0x0000000A, 0x80000015}, - {0x0000000B, 0x8001114A}, - {0x0000000C, 0x80000016}, - {0x0000000D, 0x80011150}, - {0x00000020, 0x80000000}, - {0x00000021, 0x80011142}, - {0x00000022, 0x80000001}, - {0x00000023, 0x80011143}, - {0x00000024, 0x80000002}, - {0x00000025, 0x80011144}, - {0x00000026, 0x80000003}, - {0x00000027, 0x8001114B}, - {0x00000028, 0x80000004}, - {0x00000029, 0x8001114C}, - {0x0000002A, 0x80000005}, - {0x0000002B, 0x8001114D}, - {0x0000002C, 0x80000006}, - {0x0000002D, 0x8001114E}, - {0x0000002E, 0x80000007}, - {0x0000002F, 0x8001114F}, - {0x00000500, 0x00003000}, - {0x00000501, 0x01FFFFFF}, - {0x00000502, 0x00000002}, - {0x00000503, 0x00000002}, -#ifdef __BIG_ENDIAN - {0x00000508, 0x01088043}, -#else - {0x00000508, 0x01008043}, -#endif - {0x0000050A, 0x00000000}, - {0x0000050B, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x0000050C, 0x01088019}, -#else - {0x0000050C, 0x01008019}, -#endif - {0x0000050E, 0x00000000}, - {0x0000050F, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000510, 0x01088018}, -#else - {0x00000510, 0x01008018}, -#endif - {0x00000512, 0x00000000}, - {0x00000513, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000514, 0x01088021}, -#else - {0x00000514, 0x01008021}, -#endif - {0x00000516, 0x00000000}, - {0x00000517, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000518, 0x0108805F}, -#else - {0x00000518, 0x0100805F}, -#endif - {0x0000051A, 0x00000000}, - {0x0000051B, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x0000051C, 0x0108804B}, -#else - {0x0000051C, 0x0100804B}, -#endif - {0x0000051E, 0x00000000}, - {0x0000051F, 0x00000000}, - {0x00000520, 0x0100A048}, - {0x00000521, 0x00000D01}, - {0x00000522, 0x11401140}, - {0x00000523, 0x00000000}, - {0x00000524, 0x0300A094}, - {0x00000525, 0x00000D01}, - {0x00000526, 0x11401140}, - {0x00000527, 0x00000000}, - {0x00000528, 0x0300A095}, - {0x00000529, 0x00000D01}, - {0x0000052A, 0x11401140}, - {0x0000052B, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x0000052C, 0x00080058}, -#else - {0x0000052C, 0x00000058}, -#endif - {0x0000052E, 0x11401140}, - {0x0000052F, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000530, 0x00080059}, -#else - {0x00000530, 0x00000059}, -#endif - {0x00000532, 0x11401140}, - {0x00000533, 0x00000000}, - {0x00000534, 0x0000005A}, - {0x00000536, 0x11401140}, - {0x00000537, 0x00000000}, - {0x00000538, 0x0000005B}, - {0x0000053A, 0x11401140}, - {0x0000053B, 0x00000000}, - {0x0000053C, 0x00000093}, - {0x0000053E, 0x11401140}, - {0x0000053F, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000540, 0x0308A01C}, -#else - {0x00000540, 0x0300A01C}, -#endif - {0x00000542, 0x11401140}, - {0x00000543, 0x00000000} -}; -static unsigned nv10TablePRAMIN_8BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000302}, - {0x0000050D, 0x00000302}, - {0x00000511, 0x00000202}, - {0x00000515, 0x00000302}, - {0x00000519, 0x00000302}, - {0x0000051D, 0x00000302}, - {0x0000052D, 0x00000302}, - {0x0000052E, 0x00000302}, - {0x00000535, 0x00000000}, - {0x00000539, 0x00000000}, - {0x0000053D, 0x00000000}, - {0x00000541, 0x00000302} -}; -static unsigned nv10TablePRAMIN_15BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000902}, - {0x0000050D, 0x00000902}, - {0x00000511, 0x00000802}, - {0x00000515, 0x00000902}, - {0x00000519, 0x00000902}, - {0x0000051D, 0x00000902}, - {0x0000052D, 0x00000902}, - {0x0000052E, 0x00000902}, - {0x00000535, 0x00000902}, - {0x00000539, 0x00000902}, - {0x0000053D, 0x00000902}, - {0x00000541, 0x00000902} -}; -static unsigned nv10TablePRAMIN_16BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000C02}, - {0x0000050D, 0x00000C02}, - {0x00000511, 0x00000B02}, - {0x00000515, 0x00000C02}, - {0x00000519, 0x00000C02}, - {0x0000051D, 0x00000C02}, - {0x0000052D, 0x00000C02}, - {0x0000052E, 0x00000C02}, - {0x00000535, 0x00000C02}, - {0x00000539, 0x00000C02}, - {0x0000053D, 0x00000C02}, - {0x00000541, 0x00000C02} -}; -static unsigned nv10TablePRAMIN_32BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000E02}, - {0x0000050D, 0x00000E02}, - {0x00000511, 0x00000D02}, - {0x00000515, 0x00000E02}, - {0x00000519, 0x00000E02}, - {0x0000051D, 0x00000E02}, - {0x0000052D, 0x00000E02}, - {0x0000052E, 0x00000E02}, - {0x00000535, 0x00000E02}, - {0x00000539, 0x00000E02}, - {0x0000053D, 0x00000E02}, - {0x00000541, 0x00000E02} -}; - diff --git a/drivers/video/riva/rivafb-i2c.c b/drivers/video/riva/rivafb-i2c.c deleted file mode 100644 index 9751c37c0bf..00000000000 --- a/drivers/video/riva/rivafb-i2c.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * linux/drivers/video/riva/fbdev-i2c.c - nVidia i2c - * - * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> - * - * Copyright 2004 Antonino A. Daplas <adaplas @pol.net> - * - * Based on radeonfb-i2c.c - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/delay.h> -#include <linux/pci.h> -#include <linux/fb.h> -#include <linux/jiffies.h> - -#include <asm/io.h> - -#include "rivafb.h" -#include "../edid.h" - -#define RIVA_DDC 0x50 - -static void riva_gpio_setscl(void* data, int state) -{ - struct riva_i2c_chan *chan = data; - struct riva_par *par = chan->par; - u32 val; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); - val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; - - if (state) - val |= 0x20; - else - val &= ~0x20; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); - VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); -} - -static void riva_gpio_setsda(void* data, int state) -{ - struct riva_i2c_chan *chan = data; - struct riva_par *par = chan->par; - u32 val; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); - val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; - - if (state) - val |= 0x10; - else - val &= ~0x10; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); - VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); -} - -static int riva_gpio_getscl(void* data) -{ - struct riva_i2c_chan *chan = data; - struct riva_par *par = chan->par; - u32 val = 0; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); - if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04) - val = 1; - - val = VGA_RD08(par->riva.PCIO, 0x3d5); - - return val; -} - -static int riva_gpio_getsda(void* data) -{ - struct riva_i2c_chan *chan = data; - struct riva_par *par = chan->par; - u32 val = 0; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); - if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08) - val = 1; - - return val; -} - -static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name) -{ - int rc; - - strcpy(chan->adapter.name, name); - chan->adapter.owner = THIS_MODULE; - chan->adapter.id = I2C_HW_B_RIVA; - chan->adapter.algo_data = &chan->algo; - chan->adapter.dev.parent = &chan->par->pdev->dev; - chan->algo.setsda = riva_gpio_setsda; - chan->algo.setscl = riva_gpio_setscl; - chan->algo.getsda = riva_gpio_getsda; - chan->algo.getscl = riva_gpio_getscl; - chan->algo.udelay = 40; - chan->algo.timeout = msecs_to_jiffies(2); - chan->algo.data = chan; - - i2c_set_adapdata(&chan->adapter, chan); - - /* Raise SCL and SDA */ - riva_gpio_setsda(chan, 1); - riva_gpio_setscl(chan, 1); - udelay(20); - - rc = i2c_bit_add_bus(&chan->adapter); - if (rc == 0) - dev_dbg(&chan->par->pdev->dev, "I2C bus %s registered.\n", name); - else { - dev_warn(&chan->par->pdev->dev, - "Failed to register I2C bus %s.\n", name); - chan->par = NULL; - } - - return rc; -} - -void riva_create_i2c_busses(struct riva_par *par) -{ - par->bus = 3; - - par->chan[0].par = par; - par->chan[1].par = par; - par->chan[2].par = par; - - par->chan[0].ddc_base = 0x3e; - par->chan[1].ddc_base = 0x36; - par->chan[2].ddc_base = 0x50; - riva_setup_i2c_bus(&par->chan[0], "BUS1"); - riva_setup_i2c_bus(&par->chan[1], "BUS2"); - riva_setup_i2c_bus(&par->chan[2], "BUS3"); -} - -void riva_delete_i2c_busses(struct riva_par *par) -{ - if (par->chan[0].par) - i2c_bit_del_bus(&par->chan[0].adapter); - par->chan[0].par = NULL; - - if (par->chan[1].par) - i2c_bit_del_bus(&par->chan[1].adapter); - par->chan[1].par = NULL; - - if (par->chan[2].par) - i2c_bit_del_bus(&par->chan[2].adapter); - par->chan[2].par = NULL; -} - -static u8 *riva_do_probe_i2c_edid(struct riva_i2c_chan *chan) -{ - u8 start = 0x0; - struct i2c_msg msgs[] = { - { - .addr = RIVA_DDC, - .len = 1, - .buf = &start, - }, { - .addr = RIVA_DDC, - .flags = I2C_M_RD, - .len = EDID_LENGTH, - }, - }; - u8 *buf; - - if (!chan->par) - return NULL; - - buf = kmalloc(EDID_LENGTH, GFP_KERNEL); - if (!buf) { - dev_warn(&chan->par->pdev->dev, "Out of memory!\n"); - return NULL; - } - msgs[1].buf = buf; - - if (i2c_transfer(&chan->adapter, msgs, 2) == 2) - return buf; - dev_dbg(&chan->par->pdev->dev, "Unable to read EDID block.\n"); - kfree(buf); - return NULL; -} - -int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid) -{ - u8 *edid = NULL; - int i; - - for (i = 0; i < 3; i++) { - /* Do the real work */ - edid = riva_do_probe_i2c_edid(&par->chan[conn-1]); - if (edid) - break; - } - if (out_edid) - *out_edid = edid; - if (!edid) - return 1; - - return 0; -} - diff --git a/drivers/video/riva/rivafb.h b/drivers/video/riva/rivafb.h deleted file mode 100644 index 7fa13fc9c41..00000000000 --- a/drivers/video/riva/rivafb.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef __RIVAFB_H -#define __RIVAFB_H - -#include <linux/fb.h> -#include <video/vga.h> -#include <linux/i2c.h> -#include <linux/i2c-id.h> -#include <linux/i2c-algo-bit.h> - -#include "riva_hw.h" - -/* GGI compatibility macros */ -#define NUM_SEQ_REGS 0x05 -#define NUM_CRT_REGS 0x41 -#define NUM_GRC_REGS 0x09 -#define NUM_ATC_REGS 0x15 - -/* I2C */ -#define DDC_SCL_READ_MASK (1 << 2) -#define DDC_SCL_WRITE_MASK (1 << 5) -#define DDC_SDA_READ_MASK (1 << 3) -#define DDC_SDA_WRITE_MASK (1 << 4) - -/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. - * From KGI originally. */ -struct riva_regs { - u8 attr[NUM_ATC_REGS]; - u8 crtc[NUM_CRT_REGS]; - u8 gra[NUM_GRC_REGS]; - u8 seq[NUM_SEQ_REGS]; - u8 misc_output; - RIVA_HW_STATE ext; -}; - -struct riva_par; - -struct riva_i2c_chan { - struct riva_par *par; - unsigned long ddc_base; - struct i2c_adapter adapter; - struct i2c_algo_bit_data algo; -}; - -struct riva_par { - RIVA_HW_INST riva; /* interface to riva_hw.c */ - u32 pseudo_palette[16]; /* default palette */ - u32 palette[16]; /* for Riva128 */ - u8 __iomem *ctrl_base; /* virtual control register base addr */ - unsigned dclk_max; /* max DCLK */ - - struct riva_regs initial_state; /* initial startup video mode */ - struct riva_regs current_state; -#ifdef CONFIG_X86 - struct vgastate state; -#endif - atomic_t ref_count; - unsigned char *EDID; - unsigned int Chipset; - int forceCRTC; - Bool SecondCRTC; - int FlatPanel; - struct pci_dev *pdev; - int bus; - int cursor_reset; -#ifdef CONFIG_MTRR - struct { int vram; int vram_valid; } mtrr; -#endif - struct riva_i2c_chan chan[3]; -}; - -void riva_common_setup(struct riva_par *); -unsigned long riva_get_memlen(struct riva_par *); -unsigned long riva_get_maxdclk(struct riva_par *); -void riva_delete_i2c_busses(struct riva_par *par); -void riva_create_i2c_busses(struct riva_par *par); -int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid); - -#endif /* __RIVAFB_H */ |