diff options
Diffstat (limited to 'drivers/video/omap2/dss')
| -rw-r--r-- | drivers/video/omap2/dss/Kconfig | 120 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/Makefile | 7 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/core.c | 998 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/dispc.c | 3361 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/display.c | 635 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/dpi.c | 325 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/dsi.c | 3309 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/dss.c | 641 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/dss.h | 461 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/dss_features.c | 251 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/dss_features.h | 58 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/manager.c | 1606 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/overlay.c | 728 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/rfbi.c | 1058 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/sdi.c | 184 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/venc.c | 742 |
16 files changed, 0 insertions, 14484 deletions
diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig deleted file mode 100644 index 43b64403eaa..00000000000 --- a/drivers/video/omap2/dss/Kconfig +++ /dev/null @@ -1,120 +0,0 @@ -menuconfig OMAP2_DSS - tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)" - depends on ARCH_OMAP2 || ARCH_OMAP3 - help - OMAP2/3 Display Subsystem support. - -if OMAP2_DSS - -config OMAP2_VRAM_SIZE - int "VRAM size (MB)" - range 0 32 - default 0 - help - The amount of SDRAM to reserve at boot time for video RAM use. - This VRAM will be used by omapfb and other drivers that need - large continuous RAM area for video use. - - You can also set this with "vram=<bytes>" kernel argument, or - in the board file. - -config OMAP2_DSS_DEBUG_SUPPORT - bool "Debug support" - default y - help - This enables debug messages. You need to enable printing - with 'debug' module parameter. - -config OMAP2_DSS_COLLECT_IRQ_STATS - bool "Collect DSS IRQ statistics" - depends on OMAP2_DSS_DEBUG_SUPPORT - default n - help - Collect DSS IRQ statistics, printable via debugfs. - - The statistics can be found from - <debugfs>/omapdss/dispc_irq for DISPC interrupts, and - <debugfs>/omapdss/dsi_irq for DSI interrupts. - -config OMAP2_DSS_DPI - bool "DPI support" - default y - help - DPI Interface. This is the Parallel Display Interface. - -config OMAP2_DSS_RFBI - bool "RFBI support" - default n - help - MIPI DBI support (RFBI, Remote Framebuffer Interface, in Texas - Instrument's terminology). - - DBI is a bus between the host processor and a peripheral, - such as a display or a framebuffer chip. - - See http://www.mipi.org/ for DBI spesifications. - -config OMAP2_DSS_VENC - bool "VENC support" - default y - help - OMAP Video Encoder support for S-Video and composite TV-out. - -config OMAP2_DSS_SDI - bool "SDI support" - depends on ARCH_OMAP3 - default n - help - SDI (Serial Display Interface) support. - - SDI is a high speed one-way display serial bus between the host - processor and a display. - -config OMAP2_DSS_DSI - bool "DSI support" - depends on ARCH_OMAP3 - default n - help - MIPI DSI (Display Serial Interface) support. - - DSI is a high speed half-duplex serial interface between the host - processor and a peripheral, such as a display or a framebuffer chip. - - See http://www.mipi.org/ for DSI spesifications. - -config OMAP2_DSS_USE_DSI_PLL - bool "Use DSI PLL for PCLK (EXPERIMENTAL)" - default n - depends on OMAP2_DSS_DSI - help - Use DSI PLL to generate pixel clock. Currently only for DPI output. - DSI PLL can be used to generate higher and more precise pixel clocks. - -config OMAP2_DSS_FAKE_VSYNC - bool "Fake VSYNC irq from manual update displays" - default n - help - If this is selected, DSI will generate a fake DISPC VSYNC interrupt - when DSI has sent a frame. This is only needed with DSI or RFBI - displays using manual mode, and you want VSYNC to, for example, - time animation. - -config OMAP2_DSS_MIN_FCK_PER_PCK - int "Minimum FCK/PCK ratio (for scaling)" - range 0 32 - default 0 - help - This can be used to adjust the minimum FCK/PCK ratio. - - With this you can make sure that DISPC FCK is at least - n x PCK. Video plane scaling requires higher FCK than - normally. - - If this is set to 0, there's no extra constraint on the - DISPC FCK. However, the FCK will at minimum be - 2xPCK (if active matrix) or 3xPCK (if passive matrix). - - Max FCK is 173MHz, so this doesn't work if your PCK - is very high. - -endif diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile deleted file mode 100644 index 7db17b5e570..00000000000 --- a/drivers/video/omap2/dss/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -obj-$(CONFIG_OMAP2_DSS) += omapdss.o -omapdss-y := core.o dss.o dss_features.o dispc.o display.o manager.o overlay.o -omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o -omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o -omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o -omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o -omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c deleted file mode 100644 index 8e89f604928..00000000000 --- a/drivers/video/omap2/dss/core.c +++ /dev/null @@ -1,998 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/core.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "CORE" - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/seq_file.h> -#include <linux/debugfs.h> -#include <linux/io.h> -#include <linux/device.h> -#include <linux/regulator/consumer.h> - -#include <plat/display.h> -#include <plat/clock.h> - -#include "dss.h" -#include "dss_features.h" - -static struct { - struct platform_device *pdev; - int ctx_id; - - struct clk *dss_ick; - struct clk *dss1_fck; - struct clk *dss2_fck; - struct clk *dss_54m_fck; - struct clk *dss_96m_fck; - unsigned num_clks_enabled; - - struct regulator *vdds_dsi_reg; - struct regulator *vdds_sdi_reg; - struct regulator *vdda_dac_reg; -} core; - -static void dss_clk_enable_all_no_ctx(void); -static void dss_clk_disable_all_no_ctx(void); -static void dss_clk_enable_no_ctx(enum dss_clock clks); -static void dss_clk_disable_no_ctx(enum dss_clock clks); - -static char *def_disp_name; -module_param_named(def_disp, def_disp_name, charp, 0); -MODULE_PARM_DESC(def_disp_name, "default display name"); - -#ifdef DEBUG -unsigned int dss_debug; -module_param_named(debug, dss_debug, bool, 0644); -#endif - -/* CONTEXT */ -static int dss_get_ctx_id(void) -{ - struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; - int r; - - if (!pdata->get_last_off_on_transaction_id) - return 0; - r = pdata->get_last_off_on_transaction_id(&core.pdev->dev); - if (r < 0) { - dev_err(&core.pdev->dev, "getting transaction ID failed, " - "will force context restore\n"); - r = -1; - } - return r; -} - -int dss_need_ctx_restore(void) -{ - int id = dss_get_ctx_id(); - - if (id < 0 || id != core.ctx_id) { - DSSDBG("ctx id %d -> id %d\n", - core.ctx_id, id); - core.ctx_id = id; - return 1; - } else { - return 0; - } -} - -static void save_all_ctx(void) -{ - DSSDBG("save context\n"); - - dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); - - dss_save_context(); - dispc_save_context(); -#ifdef CONFIG_OMAP2_DSS_DSI - dsi_save_context(); -#endif - - dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); -} - -static void restore_all_ctx(void) -{ - DSSDBG("restore context\n"); - - dss_clk_enable_all_no_ctx(); - - dss_restore_context(); - dispc_restore_context(); -#ifdef CONFIG_OMAP2_DSS_DSI - dsi_restore_context(); -#endif - - dss_clk_disable_all_no_ctx(); -} - -#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -/* CLOCKS */ -static void core_dump_clocks(struct seq_file *s) -{ - int i; - struct clk *clocks[5] = { - core.dss_ick, - core.dss1_fck, - core.dss2_fck, - core.dss_54m_fck, - core.dss_96m_fck - }; - - seq_printf(s, "- CORE -\n"); - - seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled); - - for (i = 0; i < 5; i++) { - if (!clocks[i]) - continue; - seq_printf(s, "%-15s\t%lu\t%d\n", - clocks[i]->name, - clk_get_rate(clocks[i]), - clocks[i]->usecount); - } -} -#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ - -static int dss_get_clock(struct clk **clock, const char *clk_name) -{ - struct clk *clk; - - clk = clk_get(&core.pdev->dev, clk_name); - - if (IS_ERR(clk)) { - DSSERR("can't get clock %s", clk_name); - return PTR_ERR(clk); - } - - *clock = clk; - - DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); - - return 0; -} - -static int dss_get_clocks(void) -{ - int r; - - core.dss_ick = NULL; - core.dss1_fck = NULL; - core.dss2_fck = NULL; - core.dss_54m_fck = NULL; - core.dss_96m_fck = NULL; - - r = dss_get_clock(&core.dss_ick, "ick"); - if (r) - goto err; - - r = dss_get_clock(&core.dss1_fck, "dss1_fck"); - if (r) - goto err; - - r = dss_get_clock(&core.dss2_fck, "dss2_fck"); - if (r) - goto err; - - r = dss_get_clock(&core.dss_54m_fck, "tv_fck"); - if (r) - goto err; - - r = dss_get_clock(&core.dss_96m_fck, "video_fck"); - if (r) - goto err; - - return 0; - -err: - if (core.dss_ick) - clk_put(core.dss_ick); - if (core.dss1_fck) - clk_put(core.dss1_fck); - if (core.dss2_fck) - clk_put(core.dss2_fck); - if (core.dss_54m_fck) - clk_put(core.dss_54m_fck); - if (core.dss_96m_fck) - clk_put(core.dss_96m_fck); - - return r; -} - -static void dss_put_clocks(void) -{ - if (core.dss_96m_fck) - clk_put(core.dss_96m_fck); - clk_put(core.dss_54m_fck); - clk_put(core.dss1_fck); - clk_put(core.dss2_fck); - clk_put(core.dss_ick); -} - -unsigned long dss_clk_get_rate(enum dss_clock clk) -{ - switch (clk) { - case DSS_CLK_ICK: - return clk_get_rate(core.dss_ick); - case DSS_CLK_FCK1: - return clk_get_rate(core.dss1_fck); - case DSS_CLK_FCK2: - return clk_get_rate(core.dss2_fck); - case DSS_CLK_54M: - return clk_get_rate(core.dss_54m_fck); - case DSS_CLK_96M: - return clk_get_rate(core.dss_96m_fck); - } - - BUG(); - return 0; -} - -static unsigned count_clk_bits(enum dss_clock clks) -{ - unsigned num_clks = 0; - - if (clks & DSS_CLK_ICK) - ++num_clks; - if (clks & DSS_CLK_FCK1) - ++num_clks; - if (clks & DSS_CLK_FCK2) - ++num_clks; - if (clks & DSS_CLK_54M) - ++num_clks; - if (clks & DSS_CLK_96M) - ++num_clks; - - return num_clks; -} - -static void dss_clk_enable_no_ctx(enum dss_clock clks) -{ - unsigned num_clks = count_clk_bits(clks); - - if (clks & DSS_CLK_ICK) - clk_enable(core.dss_ick); - if (clks & DSS_CLK_FCK1) - clk_enable(core.dss1_fck); - if (clks & DSS_CLK_FCK2) - clk_enable(core.dss2_fck); - if (clks & DSS_CLK_54M) - clk_enable(core.dss_54m_fck); - if (clks & DSS_CLK_96M) - clk_enable(core.dss_96m_fck); - - core.num_clks_enabled += num_clks; -} - -void dss_clk_enable(enum dss_clock clks) -{ - bool check_ctx = core.num_clks_enabled == 0; - - dss_clk_enable_no_ctx(clks); - - if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) - restore_all_ctx(); -} - -static void dss_clk_disable_no_ctx(enum dss_clock clks) -{ - unsigned num_clks = count_clk_bits(clks); - - if (clks & DSS_CLK_ICK) - clk_disable(core.dss_ick); - if (clks & DSS_CLK_FCK1) - clk_disable(core.dss1_fck); - if (clks & DSS_CLK_FCK2) - clk_disable(core.dss2_fck); - if (clks & DSS_CLK_54M) - clk_disable(core.dss_54m_fck); - if (clks & DSS_CLK_96M) - clk_disable(core.dss_96m_fck); - - core.num_clks_enabled -= num_clks; -} - -void dss_clk_disable(enum dss_clock clks) -{ - if (cpu_is_omap34xx()) { - unsigned num_clks = count_clk_bits(clks); - - BUG_ON(core.num_clks_enabled < num_clks); - - if (core.num_clks_enabled == num_clks) - save_all_ctx(); - } - - dss_clk_disable_no_ctx(clks); -} - -static void dss_clk_enable_all_no_ctx(void) -{ - enum dss_clock clks; - - clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; - if (cpu_is_omap34xx()) - clks |= DSS_CLK_96M; - dss_clk_enable_no_ctx(clks); -} - -static void dss_clk_disable_all_no_ctx(void) -{ - enum dss_clock clks; - - clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; - if (cpu_is_omap34xx()) - clks |= DSS_CLK_96M; - dss_clk_disable_no_ctx(clks); -} - -static void dss_clk_disable_all(void) -{ - enum dss_clock clks; - - clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; - if (cpu_is_omap34xx()) - clks |= DSS_CLK_96M; - dss_clk_disable(clks); -} - -/* REGULATORS */ - -struct regulator *dss_get_vdds_dsi(void) -{ - struct regulator *reg; - - if (core.vdds_dsi_reg != NULL) - return core.vdds_dsi_reg; - - reg = regulator_get(&core.pdev->dev, "vdds_dsi"); - if (!IS_ERR(reg)) - core.vdds_dsi_reg = reg; - - return reg; -} - -struct regulator *dss_get_vdds_sdi(void) -{ - struct regulator *reg; - - if (core.vdds_sdi_reg != NULL) - return core.vdds_sdi_reg; - - reg = regulator_get(&core.pdev->dev, "vdds_sdi"); - if (!IS_ERR(reg)) - core.vdds_sdi_reg = reg; - - return reg; -} - -struct regulator *dss_get_vdda_dac(void) -{ - struct regulator *reg; - - if (core.vdda_dac_reg != NULL) - return core.vdda_dac_reg; - - reg = regulator_get(&core.pdev->dev, "vdda_dac"); - if (!IS_ERR(reg)) - core.vdda_dac_reg = reg; - - return reg; -} - -/* DEBUGFS */ -#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -static void dss_debug_dump_clocks(struct seq_file *s) -{ - core_dump_clocks(s); - dss_dump_clocks(s); - dispc_dump_clocks(s); -#ifdef CONFIG_OMAP2_DSS_DSI - dsi_dump_clocks(s); -#endif -} - -static int dss_debug_show(struct seq_file *s, void *unused) -{ - void (*func)(struct seq_file *) = s->private; - func(s); - return 0; -} - -static int dss_debug_open(struct inode *inode, struct file *file) -{ - return single_open(file, dss_debug_show, inode->i_private); -} - -static const struct file_operations dss_debug_fops = { - .open = dss_debug_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static struct dentry *dss_debugfs_dir; - -static int dss_initialize_debugfs(void) -{ - dss_debugfs_dir = debugfs_create_dir("omapdss", NULL); - if (IS_ERR(dss_debugfs_dir)) { - int err = PTR_ERR(dss_debugfs_dir); - dss_debugfs_dir = NULL; - return err; - } - - debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir, - &dss_debug_dump_clocks, &dss_debug_fops); - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - debugfs_create_file("dispc_irq", S_IRUGO, dss_debugfs_dir, - &dispc_dump_irqs, &dss_debug_fops); -#endif - -#if defined(CONFIG_OMAP2_DSS_DSI) && defined(CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS) - debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir, - &dsi_dump_irqs, &dss_debug_fops); -#endif - - debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir, - &dss_dump_regs, &dss_debug_fops); - debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir, - &dispc_dump_regs, &dss_debug_fops); -#ifdef CONFIG_OMAP2_DSS_RFBI - debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir, - &rfbi_dump_regs, &dss_debug_fops); -#endif -#ifdef CONFIG_OMAP2_DSS_DSI - debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir, - &dsi_dump_regs, &dss_debug_fops); -#endif -#ifdef CONFIG_OMAP2_DSS_VENC - debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir, - &venc_dump_regs, &dss_debug_fops); -#endif - return 0; -} - -static void dss_uninitialize_debugfs(void) -{ - if (dss_debugfs_dir) - debugfs_remove_recursive(dss_debugfs_dir); -} -#else /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */ -static inline int dss_initialize_debugfs(void) -{ - return 0; -} -static inline void dss_uninitialize_debugfs(void) -{ -} -#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */ - -/* PLATFORM DEVICE */ -static int omap_dss_probe(struct platform_device *pdev) -{ - struct omap_dss_board_info *pdata = pdev->dev.platform_data; - int skip_init = 0; - int r; - int i; - - core.pdev = pdev; - - dss_features_init(); - - dss_init_overlay_managers(pdev); - dss_init_overlays(pdev); - - r = dss_get_clocks(); - if (r) - goto err_clocks; - - dss_clk_enable_all_no_ctx(); - - core.ctx_id = dss_get_ctx_id(); - DSSDBG("initial ctx id %u\n", core.ctx_id); - -#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT - /* DISPC_CONTROL */ - if (omap_readl(0x48050440) & 1) /* LCD enabled? */ - skip_init = 1; -#endif - - r = dss_init(skip_init); - if (r) { - DSSERR("Failed to initialize DSS\n"); - goto err_dss; - } - - r = rfbi_init(); - if (r) { - DSSERR("Failed to initialize rfbi\n"); - goto err_rfbi; - } - - r = dpi_init(pdev); - if (r) { - DSSERR("Failed to initialize dpi\n"); - goto err_dpi; - } - - r = dispc_init(); - if (r) { - DSSERR("Failed to initialize dispc\n"); - goto err_dispc; - } - - r = venc_init(pdev); - if (r) { - DSSERR("Failed to initialize venc\n"); - goto err_venc; - } - - if (cpu_is_omap34xx()) { - r = sdi_init(skip_init); - if (r) { - DSSERR("Failed to initialize SDI\n"); - goto err_sdi; - } - - r = dsi_init(pdev); - if (r) { - DSSERR("Failed to initialize DSI\n"); - goto err_dsi; - } - } - - r = dss_initialize_debugfs(); - if (r) - goto err_debugfs; - - for (i = 0; i < pdata->num_devices; ++i) { - struct omap_dss_device *dssdev = pdata->devices[i]; - - r = omap_dss_register_device(dssdev); - if (r) { - DSSERR("device %d %s register failed %d\n", i, - dssdev->name ?: "unnamed", r); - - while (--i >= 0) - omap_dss_unregister_device(pdata->devices[i]); - - goto err_register; - } - - if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0) - pdata->default_device = dssdev; - } - - dss_clk_disable_all(); - - return 0; - -err_register: - dss_uninitialize_debugfs(); -err_debugfs: - if (cpu_is_omap34xx()) - dsi_exit(); -err_dsi: - if (cpu_is_omap34xx()) - sdi_exit(); -err_sdi: - venc_exit(); -err_venc: - dispc_exit(); -err_dispc: - dpi_exit(); -err_dpi: - rfbi_exit(); -err_rfbi: - dss_exit(); -err_dss: - dss_clk_disable_all_no_ctx(); - dss_put_clocks(); -err_clocks: - - return r; -} - -static int omap_dss_remove(struct platform_device *pdev) -{ - struct omap_dss_board_info *pdata = pdev->dev.platform_data; - int i; - int c; - - dss_uninitialize_debugfs(); - - venc_exit(); - dispc_exit(); - dpi_exit(); - rfbi_exit(); - if (cpu_is_omap34xx()) { - dsi_exit(); - sdi_exit(); - } - - dss_exit(); - - /* these should be removed at some point */ - c = core.dss_ick->usecount; - if (c > 0) { - DSSERR("warning: dss_ick usecount %d, disabling\n", c); - while (c-- > 0) - clk_disable(core.dss_ick); - } - - c = core.dss1_fck->usecount; - if (c > 0) { - DSSERR("warning: dss1_fck usecount %d, disabling\n", c); - while (c-- > 0) - clk_disable(core.dss1_fck); - } - - c = core.dss2_fck->usecount; - if (c > 0) { - DSSERR("warning: dss2_fck usecount %d, disabling\n", c); - while (c-- > 0) - clk_disable(core.dss2_fck); - } - - c = core.dss_54m_fck->usecount; - if (c > 0) { - DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c); - while (c-- > 0) - clk_disable(core.dss_54m_fck); - } - - if (core.dss_96m_fck) { - c = core.dss_96m_fck->usecount; - if (c > 0) { - DSSERR("warning: dss_96m_fck usecount %d, disabling\n", - c); - while (c-- > 0) - clk_disable(core.dss_96m_fck); - } - } - - dss_put_clocks(); - - dss_uninit_overlays(pdev); - dss_uninit_overlay_managers(pdev); - - for (i = 0; i < pdata->num_devices; ++i) - omap_dss_unregister_device(pdata->devices[i]); - - return 0; -} - -static void omap_dss_shutdown(struct platform_device *pdev) -{ - DSSDBG("shutdown\n"); - dss_disable_all_devices(); -} - -static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state) -{ - DSSDBG("suspend %d\n", state.event); - - return dss_suspend_all_devices(); -} - -static int omap_dss_resume(struct platform_device *pdev) -{ - DSSDBG("resume\n"); - - return dss_resume_all_devices(); -} - -static struct platform_driver omap_dss_driver = { - .probe = omap_dss_probe, - .remove = omap_dss_remove, - .shutdown = omap_dss_shutdown, - .suspend = omap_dss_suspend, - .resume = omap_dss_resume, - .driver = { - .name = "omapdss", - .owner = THIS_MODULE, - }, -}; - -/* BUS */ -static int dss_bus_match(struct device *dev, struct device_driver *driver) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - - DSSDBG("bus_match. dev %s/%s, drv %s\n", - dev_name(dev), dssdev->driver_name, driver->name); - - return strcmp(dssdev->driver_name, driver->name) == 0; -} - -static ssize_t device_name_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - return snprintf(buf, PAGE_SIZE, "%s\n", - dssdev->name ? - dssdev->name : ""); -} - -static struct device_attribute default_dev_attrs[] = { - __ATTR(name, S_IRUGO, device_name_show, NULL), - __ATTR_NULL, -}; - -static ssize_t driver_name_show(struct device_driver *drv, char *buf) -{ - struct omap_dss_driver *dssdrv = to_dss_driver(drv); - return snprintf(buf, PAGE_SIZE, "%s\n", - dssdrv->driver.name ? - dssdrv->driver.name : ""); -} -static struct driver_attribute default_drv_attrs[] = { - __ATTR(name, S_IRUGO, driver_name_show, NULL), - __ATTR_NULL, -}; - -static struct bus_type dss_bus_type = { - .name = "omapdss", - .match = dss_bus_match, - .dev_attrs = default_dev_attrs, - .drv_attrs = default_drv_attrs, -}; - -static void dss_bus_release(struct device *dev) -{ - DSSDBG("bus_release\n"); -} - -static struct device dss_bus = { - .release = dss_bus_release, -}; - -struct bus_type *dss_get_bus(void) -{ - return &dss_bus_type; -} - -/* DRIVER */ -static int dss_driver_probe(struct device *dev) -{ - int r; - struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver); - struct omap_dss_device *dssdev = to_dss_device(dev); - struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; - bool force; - - DSSDBG("driver_probe: dev %s/%s, drv %s\n", - dev_name(dev), dssdev->driver_name, - dssdrv->driver.name); - - dss_init_device(core.pdev, dssdev); - - force = pdata->default_device == dssdev; - dss_recheck_connections(dssdev, force); - - r = dssdrv->probe(dssdev); - - if (r) { - DSSERR("driver probe failed: %d\n", r); - dss_uninit_device(core.pdev, dssdev); - return r; - } - - DSSDBG("probe done for device %s\n", dev_name(dev)); - - dssdev->driver = dssdrv; - - return 0; -} - -static int dss_driver_remove(struct device *dev) -{ - struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver); - struct omap_dss_device *dssdev = to_dss_device(dev); - - DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev), - dssdev->driver_name); - - dssdrv->remove(dssdev); - - dss_uninit_device(core.pdev, dssdev); - - dssdev->driver = NULL; - - return 0; -} - -int omap_dss_register_driver(struct omap_dss_driver *dssdriver) -{ - dssdriver->driver.bus = &dss_bus_type; - dssdriver->driver.probe = dss_driver_probe; - dssdriver->driver.remove = dss_driver_remove; - - if (dssdriver->get_resolution == NULL) - dssdriver->get_resolution = omapdss_default_get_resolution; - if (dssdriver->get_recommended_bpp == NULL) - dssdriver->get_recommended_bpp = - omapdss_default_get_recommended_bpp; - - return driver_register(&dssdriver->driver); -} -EXPORT_SYMBOL(omap_dss_register_driver); - -void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver) -{ - driver_unregister(&dssdriver->driver); -} -EXPORT_SYMBOL(omap_dss_unregister_driver); - -/* DEVICE */ -static void reset_device(struct device *dev, int check) -{ - u8 *dev_p = (u8 *)dev; - u8 *dev_end = dev_p + sizeof(*dev); - void *saved_pdata; - - saved_pdata = dev->platform_data; - if (check) { - /* - * Check if there is any other setting than platform_data - * in struct device; warn that these will be reset by our - * init. - */ - dev->platform_data = NULL; - while (dev_p < dev_end) { - if (*dev_p) { - WARN("%s: struct device fields will be " - "discarded\n", - __func__); - break; - } - dev_p++; - } - } - memset(dev, 0, sizeof(*dev)); - dev->platform_data = saved_pdata; -} - - -static void omap_dss_dev_release(struct device *dev) -{ - reset_device(dev, 0); -} - -int omap_dss_register_device(struct omap_dss_device *dssdev) -{ - static int dev_num; - - WARN_ON(!dssdev->driver_name); - - reset_device(&dssdev->dev, 1); - dssdev->dev.bus = &dss_bus_type; - dssdev->dev.parent = &dss_bus; - dssdev->dev.release = omap_dss_dev_release; - dev_set_name(&dssdev->dev, "display%d", dev_num++); - return device_register(&dssdev->dev); -} - -void omap_dss_unregister_device(struct omap_dss_device *dssdev) -{ - device_unregister(&dssdev->dev); -} - -/* BUS */ -static int omap_dss_bus_register(void) -{ - int r; - - r = bus_register(&dss_bus_type); - if (r) { - DSSERR("bus register failed\n"); - return r; - } - - dev_set_name(&dss_bus, "omapdss"); - r = device_register(&dss_bus); - if (r) { - DSSERR("bus driver register failed\n"); - bus_unregister(&dss_bus_type); - return r; - } - - return 0; -} - -/* INIT */ - -#ifdef CONFIG_OMAP2_DSS_MODULE -static void omap_dss_bus_unregister(void) -{ - device_unregister(&dss_bus); - - bus_unregister(&dss_bus_type); -} - -static int __init omap_dss_init(void) -{ - int r; - - r = omap_dss_bus_register(); - if (r) - return r; - - r = platform_driver_register(&omap_dss_driver); - if (r) { - omap_dss_bus_unregister(); - return r; - } - - return 0; -} - -static void __exit omap_dss_exit(void) -{ - if (core.vdds_dsi_reg != NULL) { - regulator_put(core.vdds_dsi_reg); - core.vdds_dsi_reg = NULL; - } - - if (core.vdds_sdi_reg != NULL) { - regulator_put(core.vdds_sdi_reg); - core.vdds_sdi_reg = NULL; - } - - if (core.vdda_dac_reg != NULL) { - regulator_put(core.vdda_dac_reg); - core.vdda_dac_reg = NULL; - } - - platform_driver_unregister(&omap_dss_driver); - - omap_dss_bus_unregister(); -} - -module_init(omap_dss_init); -module_exit(omap_dss_exit); -#else -static int __init omap_dss_init(void) -{ - return omap_dss_bus_register(); -} - -static int __init omap_dss_init2(void) -{ - return platform_driver_register(&omap_dss_driver); -} - -core_initcall(omap_dss_init); -device_initcall(omap_dss_init2); -#endif - -MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>"); -MODULE_DESCRIPTION("OMAP2/3 Display Subsystem"); -MODULE_LICENSE("GPL v2"); - diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c deleted file mode 100644 index 9f8c69f16e6..00000000000 --- a/drivers/video/omap2/dss/dispc.c +++ /dev/null @@ -1,3361 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/dispc.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "DISPC" - -#include <linux/kernel.h> -#include <linux/dma-mapping.h> -#include <linux/vmalloc.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/jiffies.h> -#include <linux/seq_file.h> -#include <linux/delay.h> -#include <linux/workqueue.h> -#include <linux/hardirq.h> - -#include <plat/sram.h> -#include <plat/clock.h> - -#include <plat/display.h> - -#include "dss.h" -#include "dss_features.h" - -/* DISPC */ -#define DISPC_BASE 0x48050400 - -#define DISPC_SZ_REGS SZ_4K - -struct dispc_reg { u16 idx; }; - -#define DISPC_REG(idx) ((const struct dispc_reg) { idx }) - -/* - * DISPC common registers and - * DISPC channel registers , ch = 0 for LCD, ch = 1 for - * DIGIT, and ch = 2 for LCD2 - */ -#define DISPC_REVISION DISPC_REG(0x0000) -#define DISPC_SYSCONFIG DISPC_REG(0x0010) -#define DISPC_SYSSTATUS DISPC_REG(0x0014) -#define DISPC_IRQSTATUS DISPC_REG(0x0018) -#define DISPC_IRQENABLE DISPC_REG(0x001C) -#define DISPC_CONTROL DISPC_REG(0x0040) -#define DISPC_CONTROL2 DISPC_REG(0x0238) -#define DISPC_CONFIG DISPC_REG(0x0044) -#define DISPC_CONFIG2 DISPC_REG(0x0620) -#define DISPC_CAPABLE DISPC_REG(0x0048) -#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \ - (ch == 1 ? 0x0050 : 0x03AC)) -#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \ - (ch == 1 ? 0x0058 : 0x03B0)) -#define DISPC_LINE_STATUS DISPC_REG(0x005C) -#define DISPC_LINE_NUMBER DISPC_REG(0x0060) -#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400) -#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404) -#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408) -#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C) -#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074) -#define DISPC_SIZE_DIG DISPC_REG(0x0078) -#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC) - -/* DISPC GFX plane */ -#define DISPC_GFX_BA0 DISPC_REG(0x0080) -#define DISPC_GFX_BA1 DISPC_REG(0x0084) -#define DISPC_GFX_POSITION DISPC_REG(0x0088) -#define DISPC_GFX_SIZE DISPC_REG(0x008C) -#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0) -#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4) -#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8) -#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC) -#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0) -#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4) -#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8) - -#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0) -#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4) -#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8) -#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC) -#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8) -#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4) - -#define DISPC_GFX_PRELOAD DISPC_REG(0x022C) - -/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */ -#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx) - -#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000) -#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004) -#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008) -#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C) -#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010) -#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014) -#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018) -#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C) -#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020) -#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024) -#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028) -#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C) -#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030) - -/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8) -/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8) -/* coef index i = {0, 1, 2, 3, 4} */ -#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4) -/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4) - -#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04) - - -#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ - DISPC_IRQ_OCP_ERR | \ - DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ - DISPC_IRQ_VID2_FIFO_UNDERFLOW | \ - DISPC_IRQ_SYNC_LOST | \ - DISPC_IRQ_SYNC_LOST_DIGIT) - -#define DISPC_MAX_NR_ISRS 8 - -struct omap_dispc_isr_data { - omap_dispc_isr_t isr; - void *arg; - u32 mask; -}; - -struct dispc_h_coef { - s8 hc4; - s8 hc3; - u8 hc2; - s8 hc1; - s8 hc0; -}; - -struct dispc_v_coef { - s8 vc22; - s8 vc2; - u8 vc1; - s8 vc0; - s8 vc00; -}; - -#define REG_GET(idx, start, end) \ - FLD_GET(dispc_read_reg(idx), start, end) - -#define REG_FLD_MOD(idx, val, start, end) \ - dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) - -static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES, - DISPC_VID_ATTRIBUTES(0), - DISPC_VID_ATTRIBUTES(1) }; - -struct dispc_irq_stats { - unsigned long last_reset; - unsigned irq_count; - unsigned irqs[32]; -}; - -static struct { - void __iomem *base; - - u32 fifo_size[3]; - - spinlock_t irq_lock; - u32 irq_error_mask; - struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; - u32 error_irqs; - struct work_struct error_work; - - u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spinlock_t irq_stats_lock; - struct dispc_irq_stats irq_stats; -#endif -} dispc; - -static void _omap_dispc_set_irqs(void); - -static inline void dispc_write_reg(const struct dispc_reg idx, u32 val) -{ - __raw_writel(val, dispc.base + idx.idx); -} - -static inline u32 dispc_read_reg(const struct dispc_reg idx) -{ - return __raw_readl(dispc.base + idx.idx); -} - -#define SR(reg) \ - dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg) -#define RR(reg) \ - dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)]) - -void dispc_save_context(void) -{ - if (cpu_is_omap24xx()) - return; - - SR(SYSCONFIG); - SR(IRQENABLE); - SR(CONTROL); - SR(CONFIG); - SR(DEFAULT_COLOR(0)); - SR(DEFAULT_COLOR(1)); - SR(TRANS_COLOR(0)); - SR(TRANS_COLOR(1)); - SR(LINE_NUMBER); - SR(TIMING_H(0)); - SR(TIMING_V(0)); - SR(POL_FREQ(0)); - SR(DIVISOR(0)); - SR(GLOBAL_ALPHA); - SR(SIZE_DIG); - SR(SIZE_LCD(0)); - if (dss_has_feature(FEAT_MGR_LCD2)) { - SR(CONTROL2); - SR(DEFAULT_COLOR(2)); - SR(TRANS_COLOR(2)); - SR(SIZE_LCD(2)); - SR(TIMING_H(2)); - SR(TIMING_V(2)); - SR(POL_FREQ(2)); - SR(DIVISOR(2)); - SR(CONFIG2); - } - - SR(GFX_BA0); - SR(GFX_BA1); - SR(GFX_POSITION); - SR(GFX_SIZE); - SR(GFX_ATTRIBUTES); - SR(GFX_FIFO_THRESHOLD); - SR(GFX_ROW_INC); - SR(GFX_PIXEL_INC); - SR(GFX_WINDOW_SKIP); - SR(GFX_TABLE_BA); - - SR(DATA_CYCLE1(0)); - SR(DATA_CYCLE2(0)); - SR(DATA_CYCLE3(0)); - - SR(CPR_COEF_R(0)); - SR(CPR_COEF_G(0)); - SR(CPR_COEF_B(0)); - if (dss_has_feature(FEAT_MGR_LCD2)) { - SR(CPR_COEF_B(2)); - SR(CPR_COEF_G(2)); - SR(CPR_COEF_R(2)); - - SR(DATA_CYCLE1(2)); - SR(DATA_CYCLE2(2)); - SR(DATA_CYCLE3(2)); - } - - SR(GFX_PRELOAD); - - /* VID1 */ - SR(VID_BA0(0)); - SR(VID_BA1(0)); - SR(VID_POSITION(0)); - SR(VID_SIZE(0)); - SR(VID_ATTRIBUTES(0)); - SR(VID_FIFO_THRESHOLD(0)); - SR(VID_ROW_INC(0)); - SR(VID_PIXEL_INC(0)); - SR(VID_FIR(0)); - SR(VID_PICTURE_SIZE(0)); - SR(VID_ACCU0(0)); - SR(VID_ACCU1(0)); - - SR(VID_FIR_COEF_H(0, 0)); - SR(VID_FIR_COEF_H(0, 1)); - SR(VID_FIR_COEF_H(0, 2)); - SR(VID_FIR_COEF_H(0, 3)); - SR(VID_FIR_COEF_H(0, 4)); - SR(VID_FIR_COEF_H(0, 5)); - SR(VID_FIR_COEF_H(0, 6)); - SR(VID_FIR_COEF_H(0, 7)); - - SR(VID_FIR_COEF_HV(0, 0)); - SR(VID_FIR_COEF_HV(0, 1)); - SR(VID_FIR_COEF_HV(0, 2)); - SR(VID_FIR_COEF_HV(0, 3)); - SR(VID_FIR_COEF_HV(0, 4)); - SR(VID_FIR_COEF_HV(0, 5)); - SR(VID_FIR_COEF_HV(0, 6)); - SR(VID_FIR_COEF_HV(0, 7)); - - SR(VID_CONV_COEF(0, 0)); - SR(VID_CONV_COEF(0, 1)); - SR(VID_CONV_COEF(0, 2)); - SR(VID_CONV_COEF(0, 3)); - SR(VID_CONV_COEF(0, 4)); - - SR(VID_FIR_COEF_V(0, 0)); - SR(VID_FIR_COEF_V(0, 1)); - SR(VID_FIR_COEF_V(0, 2)); - SR(VID_FIR_COEF_V(0, 3)); - SR(VID_FIR_COEF_V(0, 4)); - SR(VID_FIR_COEF_V(0, 5)); - SR(VID_FIR_COEF_V(0, 6)); - SR(VID_FIR_COEF_V(0, 7)); - - SR(VID_PRELOAD(0)); - - /* VID2 */ - SR(VID_BA0(1)); - SR(VID_BA1(1)); - SR(VID_POSITION(1)); - SR(VID_SIZE(1)); - SR(VID_ATTRIBUTES(1)); - SR(VID_FIFO_THRESHOLD(1)); - SR(VID_ROW_INC(1)); - SR(VID_PIXEL_INC(1)); - SR(VID_FIR(1)); - SR(VID_PICTURE_SIZE(1)); - SR(VID_ACCU0(1)); - SR(VID_ACCU1(1)); - - SR(VID_FIR_COEF_H(1, 0)); - SR(VID_FIR_COEF_H(1, 1)); - SR(VID_FIR_COEF_H(1, 2)); - SR(VID_FIR_COEF_H(1, 3)); - SR(VID_FIR_COEF_H(1, 4)); - SR(VID_FIR_COEF_H(1, 5)); - SR(VID_FIR_COEF_H(1, 6)); - SR(VID_FIR_COEF_H(1, 7)); - - SR(VID_FIR_COEF_HV(1, 0)); - SR(VID_FIR_COEF_HV(1, 1)); - SR(VID_FIR_COEF_HV(1, 2)); - SR(VID_FIR_COEF_HV(1, 3)); - SR(VID_FIR_COEF_HV(1, 4)); - SR(VID_FIR_COEF_HV(1, 5)); - SR(VID_FIR_COEF_HV(1, 6)); - SR(VID_FIR_COEF_HV(1, 7)); - - SR(VID_CONV_COEF(1, 0)); - SR(VID_CONV_COEF(1, 1)); - SR(VID_CONV_COEF(1, 2)); - SR(VID_CONV_COEF(1, 3)); - SR(VID_CONV_COEF(1, 4)); - - SR(VID_FIR_COEF_V(1, 0)); - SR(VID_FIR_COEF_V(1, 1)); - SR(VID_FIR_COEF_V(1, 2)); - SR(VID_FIR_COEF_V(1, 3)); - SR(VID_FIR_COEF_V(1, 4)); - SR(VID_FIR_COEF_V(1, 5)); - SR(VID_FIR_COEF_V(1, 6)); - SR(VID_FIR_COEF_V(1, 7)); - - SR(VID_PRELOAD(1)); -} - -void dispc_restore_context(void) -{ - RR(SYSCONFIG); - /*RR(IRQENABLE);*/ - /*RR(CONTROL);*/ - RR(CONFIG); - RR(DEFAULT_COLOR(0)); - RR(DEFAULT_COLOR(1)); - RR(TRANS_COLOR(0)); - RR(TRANS_COLOR(1)); - RR(LINE_NUMBER); - RR(TIMING_H(0)); - RR(TIMING_V(0)); - RR(POL_FREQ(0)); - RR(DIVISOR(0)); - RR(GLOBAL_ALPHA); - RR(SIZE_DIG); - RR(SIZE_LCD(0)); - if (dss_has_feature(FEAT_MGR_LCD2)) { - RR(DEFAULT_COLOR(2)); - RR(TRANS_COLOR(2)); - RR(SIZE_LCD(2)); - RR(TIMING_H(2)); - RR(TIMING_V(2)); - RR(POL_FREQ(2)); - RR(DIVISOR(2)); - RR(CONFIG2); - } - - RR(GFX_BA0); - RR(GFX_BA1); - RR(GFX_POSITION); - RR(GFX_SIZE); - RR(GFX_ATTRIBUTES); - RR(GFX_FIFO_THRESHOLD); - RR(GFX_ROW_INC); - RR(GFX_PIXEL_INC); - RR(GFX_WINDOW_SKIP); - RR(GFX_TABLE_BA); - - RR(DATA_CYCLE1(0)); - RR(DATA_CYCLE2(0)); - RR(DATA_CYCLE3(0)); - - RR(CPR_COEF_R(0)); - RR(CPR_COEF_G(0)); - RR(CPR_COEF_B(0)); - if (dss_has_feature(FEAT_MGR_LCD2)) { - RR(DATA_CYCLE1(2)); - RR(DATA_CYCLE2(2)); - RR(DATA_CYCLE3(2)); - - RR(CPR_COEF_B(2)); - RR(CPR_COEF_G(2)); - RR(CPR_COEF_R(2)); - } - - RR(GFX_PRELOAD); - - /* VID1 */ - RR(VID_BA0(0)); - RR(VID_BA1(0)); - RR(VID_POSITION(0)); - RR(VID_SIZE(0)); - RR(VID_ATTRIBUTES(0)); - RR(VID_FIFO_THRESHOLD(0)); - RR(VID_ROW_INC(0)); - RR(VID_PIXEL_INC(0)); - RR(VID_FIR(0)); - RR(VID_PICTURE_SIZE(0)); - RR(VID_ACCU0(0)); - RR(VID_ACCU1(0)); - - RR(VID_FIR_COEF_H(0, 0)); - RR(VID_FIR_COEF_H(0, 1)); - RR(VID_FIR_COEF_H(0, 2)); - RR(VID_FIR_COEF_H(0, 3)); - RR(VID_FIR_COEF_H(0, 4)); - RR(VID_FIR_COEF_H(0, 5)); - RR(VID_FIR_COEF_H(0, 6)); - RR(VID_FIR_COEF_H(0, 7)); - - RR(VID_FIR_COEF_HV(0, 0)); - RR(VID_FIR_COEF_HV(0, 1)); - RR(VID_FIR_COEF_HV(0, 2)); - RR(VID_FIR_COEF_HV(0, 3)); - RR(VID_FIR_COEF_HV(0, 4)); - RR(VID_FIR_COEF_HV(0, 5)); - RR(VID_FIR_COEF_HV(0, 6)); - RR(VID_FIR_COEF_HV(0, 7)); - - RR(VID_CONV_COEF(0, 0)); - RR(VID_CONV_COEF(0, 1)); - RR(VID_CONV_COEF(0, 2)); - RR(VID_CONV_COEF(0, 3)); - RR(VID_CONV_COEF(0, 4)); - - RR(VID_FIR_COEF_V(0, 0)); - RR(VID_FIR_COEF_V(0, 1)); - RR(VID_FIR_COEF_V(0, 2)); - RR(VID_FIR_COEF_V(0, 3)); - RR(VID_FIR_COEF_V(0, 4)); - RR(VID_FIR_COEF_V(0, 5)); - RR(VID_FIR_COEF_V(0, 6)); - RR(VID_FIR_COEF_V(0, 7)); - - RR(VID_PRELOAD(0)); - - /* VID2 */ - RR(VID_BA0(1)); - RR(VID_BA1(1)); - RR(VID_POSITION(1)); - RR(VID_SIZE(1)); - RR(VID_ATTRIBUTES(1)); - RR(VID_FIFO_THRESHOLD(1)); - RR(VID_ROW_INC(1)); - RR(VID_PIXEL_INC(1)); - RR(VID_FIR(1)); - RR(VID_PICTURE_SIZE(1)); - RR(VID_ACCU0(1)); - RR(VID_ACCU1(1)); - - RR(VID_FIR_COEF_H(1, 0)); - RR(VID_FIR_COEF_H(1, 1)); - RR(VID_FIR_COEF_H(1, 2)); - RR(VID_FIR_COEF_H(1, 3)); - RR(VID_FIR_COEF_H(1, 4)); - RR(VID_FIR_COEF_H(1, 5)); - RR(VID_FIR_COEF_H(1, 6)); - RR(VID_FIR_COEF_H(1, 7)); - - RR(VID_FIR_COEF_HV(1, 0)); - RR(VID_FIR_COEF_HV(1, 1)); - RR(VID_FIR_COEF_HV(1, 2)); - RR(VID_FIR_COEF_HV(1, 3)); - RR(VID_FIR_COEF_HV(1, 4)); - RR(VID_FIR_COEF_HV(1, 5)); - RR(VID_FIR_COEF_HV(1, 6)); - RR(VID_FIR_COEF_HV(1, 7)); - - RR(VID_CONV_COEF(1, 0)); - RR(VID_CONV_COEF(1, 1)); - RR(VID_CONV_COEF(1, 2)); - RR(VID_CONV_COEF(1, 3)); - RR(VID_CONV_COEF(1, 4)); - - RR(VID_FIR_COEF_V(1, 0)); - RR(VID_FIR_COEF_V(1, 1)); - RR(VID_FIR_COEF_V(1, 2)); - RR(VID_FIR_COEF_V(1, 3)); - RR(VID_FIR_COEF_V(1, 4)); - RR(VID_FIR_COEF_V(1, 5)); - RR(VID_FIR_COEF_V(1, 6)); - RR(VID_FIR_COEF_V(1, 7)); - - RR(VID_PRELOAD(1)); - - /* enable last, because LCD & DIGIT enable are here */ - RR(CONTROL); - if (dss_has_feature(FEAT_MGR_LCD2)) - RR(CONTROL2); - /* clear spurious SYNC_LOST_DIGIT interrupts */ - dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); - - /* - * enable last so IRQs won't trigger before - * the context is fully restored - */ - RR(IRQENABLE); -} - -#undef SR -#undef RR - -static inline void enable_clocks(bool enable) -{ - if (enable) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - else - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -} - -bool dispc_go_busy(enum omap_channel channel) -{ - int bit; - - if (channel == OMAP_DSS_CHANNEL_LCD || - channel == OMAP_DSS_CHANNEL_LCD2) - bit = 5; /* GOLCD */ - else - bit = 6; /* GODIGIT */ - - if (channel == OMAP_DSS_CHANNEL_LCD2) - return REG_GET(DISPC_CONTROL2, bit, bit) == 1; - else - return REG_GET(DISPC_CONTROL, bit, bit) == 1; -} - -void dispc_go(enum omap_channel channel) -{ - int bit; - bool enable_bit, go_bit; - - enable_clocks(1); - - if (channel == OMAP_DSS_CHANNEL_LCD || - channel == OMAP_DSS_CHANNEL_LCD2) - bit = 0; /* LCDENABLE */ - else - bit = 1; /* DIGITALENABLE */ - - /* if the channel is not enabled, we don't need GO */ - if (channel == OMAP_DSS_CHANNEL_LCD2) - enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1; - else - enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1; - - if (!enable_bit) - goto end; - - if (channel == OMAP_DSS_CHANNEL_LCD || - channel == OMAP_DSS_CHANNEL_LCD2) - bit = 5; /* GOLCD */ - else - bit = 6; /* GODIGIT */ - - if (channel == OMAP_DSS_CHANNEL_LCD2) - go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1; - else - go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1; - - if (go_bit) { - DSSERR("GO bit not down for channel %d\n", channel); - goto end; - } - - DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : - (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT")); - - if (channel == OMAP_DSS_CHANNEL_LCD2) - REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit); - else - REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit); -end: - enable_clocks(0); -} - -static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value) -{ - BUG_ON(plane == OMAP_DSS_GFX); - - dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value); -} - -static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value) -{ - BUG_ON(plane == OMAP_DSS_GFX); - - dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value); -} - -static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value) -{ - BUG_ON(plane == OMAP_DSS_GFX); - - dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value); -} - -static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup, - int vscaleup, int five_taps) -{ - /* Coefficients for horizontal up-sampling */ - static const struct dispc_h_coef coef_hup[8] = { - { 0, 0, 128, 0, 0 }, - { -1, 13, 124, -8, 0 }, - { -2, 30, 112, -11, -1 }, - { -5, 51, 95, -11, -2 }, - { 0, -9, 73, 73, -9 }, - { -2, -11, 95, 51, -5 }, - { -1, -11, 112, 30, -2 }, - { 0, -8, 124, 13, -1 }, - }; - - /* Coefficients for vertical up-sampling */ - static const struct dispc_v_coef coef_vup_3tap[8] = { - { 0, 0, 128, 0, 0 }, - { 0, 3, 123, 2, 0 }, - { 0, 12, 111, 5, 0 }, - { 0, 32, 89, 7, 0 }, - { 0, 0, 64, 64, 0 }, - { 0, 7, 89, 32, 0 }, - { 0, 5, 111, 12, 0 }, - { 0, 2, 123, 3, 0 }, - }; - - static const struct dispc_v_coef coef_vup_5tap[8] = { - { 0, 0, 128, 0, 0 }, - { -1, 13, 124, -8, 0 }, - { -2, 30, 112, -11, -1 }, - { -5, 51, 95, -11, -2 }, - { 0, -9, 73, 73, -9 }, - { -2, -11, 95, 51, -5 }, - { -1, -11, 112, 30, -2 }, - { 0, -8, 124, 13, -1 }, - }; - - /* Coefficients for horizontal down-sampling */ - static const struct dispc_h_coef coef_hdown[8] = { - { 0, 36, 56, 36, 0 }, - { 4, 40, 55, 31, -2 }, - { 8, 44, 54, 27, -5 }, - { 12, 48, 53, 22, -7 }, - { -9, 17, 52, 51, 17 }, - { -7, 22, 53, 48, 12 }, - { -5, 27, 54, 44, 8 }, - { -2, 31, 55, 40, 4 }, - }; - - /* Coefficients for vertical down-sampling */ - static const struct dispc_v_coef coef_vdown_3tap[8] = { - { 0, 36, 56, 36, 0 }, - { 0, 40, 57, 31, 0 }, - { 0, 45, 56, 27, 0 }, - { 0, 50, 55, 23, 0 }, - { 0, 18, 55, 55, 0 }, - { 0, 23, 55, 50, 0 }, - { 0, 27, 56, 45, 0 }, - { 0, 31, 57, 40, 0 }, - }; - - static const struct dispc_v_coef coef_vdown_5tap[8] = { - { 0, 36, 56, 36, 0 }, - { 4, 40, 55, 31, -2 }, - { 8, 44, 54, 27, -5 }, - { 12, 48, 53, 22, -7 }, - { -9, 17, 52, 51, 17 }, - { -7, 22, 53, 48, 12 }, - { -5, 27, 54, 44, 8 }, - { -2, 31, 55, 40, 4 }, - }; - - const struct dispc_h_coef *h_coef; - const struct dispc_v_coef *v_coef; - int i; - - if (hscaleup) - h_coef = coef_hup; - else - h_coef = coef_hdown; - - if (vscaleup) - v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap; - else - v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap; - - for (i = 0; i < 8; i++) { - u32 h, hv; - - h = FLD_VAL(h_coef[i].hc0, 7, 0) - | FLD_VAL(h_coef[i].hc1, 15, 8) - | FLD_VAL(h_coef[i].hc2, 23, 16) - | FLD_VAL(h_coef[i].hc3, 31, 24); - hv = FLD_VAL(h_coef[i].hc4, 7, 0) - | FLD_VAL(v_coef[i].vc0, 15, 8) - | FLD_VAL(v_coef[i].vc1, 23, 16) - | FLD_VAL(v_coef[i].vc2, 31, 24); - - _dispc_write_firh_reg(plane, i, h); - _dispc_write_firhv_reg(plane, i, hv); - } - - if (five_taps) { - for (i = 0; i < 8; i++) { - u32 v; - v = FLD_VAL(v_coef[i].vc00, 7, 0) - | FLD_VAL(v_coef[i].vc22, 15, 8); - _dispc_write_firv_reg(plane, i, v); - } - } -} - -static void _dispc_setup_color_conv_coef(void) -{ - const struct color_conv_coef { - int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; - int full_range; - } ctbl_bt601_5 = { - 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, - }; - - const struct color_conv_coef *ct; - -#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) - - ct = &ctbl_bt601_5; - - dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry)); - dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb)); - dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr)); - dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by)); - dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb)); - - dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry)); - dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb)); - dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr)); - dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by)); - dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb)); - -#undef CVAL - - REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11); - REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11); -} - - -static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr) -{ - const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0, - DISPC_VID_BA0(0), - DISPC_VID_BA0(1) }; - - dispc_write_reg(ba0_reg[plane], paddr); -} - -static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr) -{ - const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1, - DISPC_VID_BA1(0), - DISPC_VID_BA1(1) }; - - dispc_write_reg(ba1_reg[plane], paddr); -} - -static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y) -{ - const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION, - DISPC_VID_POSITION(0), - DISPC_VID_POSITION(1) }; - - u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); - dispc_write_reg(pos_reg[plane], val); -} - -static void _dispc_set_pic_size(enum omap_plane plane, int width, int height) -{ - const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE, - DISPC_VID_PICTURE_SIZE(0), - DISPC_VID_PICTURE_SIZE(1) }; - u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); - dispc_write_reg(siz_reg[plane], val); -} - -static void _dispc_set_vid_size(enum omap_plane plane, int width, int height) -{ - u32 val; - const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0), - DISPC_VID_SIZE(1) }; - - BUG_ON(plane == OMAP_DSS_GFX); - - val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); - dispc_write_reg(vsi_reg[plane-1], val); -} - -static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable) -{ - if (!dss_has_feature(FEAT_PRE_MULT_ALPHA)) - return; - - if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) && - plane == OMAP_DSS_VIDEO1) - return; - - REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28); -} - -static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha) -{ - if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) - return; - - if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) && - plane == OMAP_DSS_VIDEO1) - return; - - if (plane == OMAP_DSS_GFX) - REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0); - else if (plane == OMAP_DSS_VIDEO2) - REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16); -} - -static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc) -{ - const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC, - DISPC_VID_PIXEL_INC(0), - DISPC_VID_PIXEL_INC(1) }; - - dispc_write_reg(ri_reg[plane], inc); -} - -static void _dispc_set_row_inc(enum omap_plane plane, s32 inc) -{ - const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC, - DISPC_VID_ROW_INC(0), - DISPC_VID_ROW_INC(1) }; - - dispc_write_reg(ri_reg[plane], inc); -} - -static void _dispc_set_color_mode(enum omap_plane plane, - enum omap_color_mode color_mode) -{ - u32 m = 0; - - switch (color_mode) { - case OMAP_DSS_COLOR_CLUT1: - m = 0x0; break; - case OMAP_DSS_COLOR_CLUT2: - m = 0x1; break; - case OMAP_DSS_COLOR_CLUT4: - m = 0x2; break; - case OMAP_DSS_COLOR_CLUT8: - m = 0x3; break; - case OMAP_DSS_COLOR_RGB12U: - m = 0x4; break; - case OMAP_DSS_COLOR_ARGB16: - m = 0x5; break; - case OMAP_DSS_COLOR_RGB16: - m = 0x6; break; - case OMAP_DSS_COLOR_RGB24U: - m = 0x8; break; - case OMAP_DSS_COLOR_RGB24P: - m = 0x9; break; - case OMAP_DSS_COLOR_YUV2: - m = 0xa; break; - case OMAP_DSS_COLOR_UYVY: - m = 0xb; break; - case OMAP_DSS_COLOR_ARGB32: - m = 0xc; break; - case OMAP_DSS_COLOR_RGBA32: - m = 0xd; break; - case OMAP_DSS_COLOR_RGBX32: - m = 0xe; break; - default: - BUG(); break; - } - - REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1); -} - -static void _dispc_set_channel_out(enum omap_plane plane, - enum omap_channel channel) -{ - int shift; - u32 val; - int chan = 0, chan2 = 0; - - switch (plane) { - case OMAP_DSS_GFX: - shift = 8; - break; - case OMAP_DSS_VIDEO1: - case OMAP_DSS_VIDEO2: - shift = 16; - break; - default: - BUG(); - return; - } - - val = dispc_read_reg(dispc_reg_att[plane]); - if (dss_has_feature(FEAT_MGR_LCD2)) { - switch (channel) { - case OMAP_DSS_CHANNEL_LCD: - chan = 0; - chan2 = 0; - break; - case OMAP_DSS_CHANNEL_DIGIT: - chan = 1; - chan2 = 0; - break; - case OMAP_DSS_CHANNEL_LCD2: - chan = 0; - chan2 = 1; - break; - default: - BUG(); - } - - val = FLD_MOD(val, chan, shift, shift); - val = FLD_MOD(val, chan2, 31, 30); - } else { - val = FLD_MOD(val, channel, shift, shift); - } - dispc_write_reg(dispc_reg_att[plane], val); -} - -void dispc_set_burst_size(enum omap_plane plane, - enum omap_burst_size burst_size) -{ - int shift; - u32 val; - - enable_clocks(1); - - switch (plane) { - case OMAP_DSS_GFX: - shift = 6; - break; - case OMAP_DSS_VIDEO1: - case OMAP_DSS_VIDEO2: - shift = 14; - break; - default: - BUG(); - return; - } - - val = dispc_read_reg(dispc_reg_att[plane]); - val = FLD_MOD(val, burst_size, shift+1, shift); - dispc_write_reg(dispc_reg_att[plane], val); - - enable_clocks(0); -} - -static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable) -{ - u32 val; - - BUG_ON(plane == OMAP_DSS_GFX); - - val = dispc_read_reg(dispc_reg_att[plane]); - val = FLD_MOD(val, enable, 9, 9); - dispc_write_reg(dispc_reg_att[plane], val); -} - -void dispc_enable_replication(enum omap_plane plane, bool enable) -{ - int bit; - - if (plane == OMAP_DSS_GFX) - bit = 5; - else - bit = 10; - - enable_clocks(1); - REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit); - enable_clocks(0); -} - -void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height) -{ - u32 val; - BUG_ON((width > (1 << 11)) || (height > (1 << 11))); - val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); - enable_clocks(1); - dispc_write_reg(DISPC_SIZE_LCD(channel), val); - enable_clocks(0); -} - -void dispc_set_digit_size(u16 width, u16 height) -{ - u32 val; - BUG_ON((width > (1 << 11)) || (height > (1 << 11))); - val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); - enable_clocks(1); - dispc_write_reg(DISPC_SIZE_DIG, val); - enable_clocks(0); -} - -static void dispc_read_plane_fifo_sizes(void) -{ - const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS, - DISPC_VID_FIFO_SIZE_STATUS(0), - DISPC_VID_FIFO_SIZE_STATUS(1) }; - u32 size; - int plane; - u8 start, end; - - enable_clocks(1); - - dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); - - for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) { - size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end); - dispc.fifo_size[plane] = size; - } - - enable_clocks(0); -} - -u32 dispc_get_plane_fifo_size(enum omap_plane plane) -{ - return dispc.fifo_size[plane]; -} - -void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) -{ - const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD, - DISPC_VID_FIFO_THRESHOLD(0), - DISPC_VID_FIFO_THRESHOLD(1) }; - u8 hi_start, hi_end, lo_start, lo_end; - - enable_clocks(1); - - DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n", - plane, - REG_GET(ftrs_reg[plane], 11, 0), - REG_GET(ftrs_reg[plane], 27, 16), - low, high); - - dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); - dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); - - dispc_write_reg(ftrs_reg[plane], - FLD_VAL(high, hi_start, hi_end) | - FLD_VAL(low, lo_start, lo_end)); - - enable_clocks(0); -} - -void dispc_enable_fifomerge(bool enable) -{ - enable_clocks(1); - - DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); - REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); - - enable_clocks(0); -} - -static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc) -{ - u32 val; - const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0), - DISPC_VID_FIR(1) }; - u8 hinc_start, hinc_end, vinc_start, vinc_end; - - BUG_ON(plane == OMAP_DSS_GFX); - - dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end); - dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end); - - val = FLD_VAL(vinc, vinc_start, vinc_end) | - FLD_VAL(hinc, hinc_start, hinc_end); - - dispc_write_reg(fir_reg[plane-1], val); -} - -static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) -{ - u32 val; - const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0), - DISPC_VID_ACCU0(1) }; - - BUG_ON(plane == OMAP_DSS_GFX); - - val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); - dispc_write_reg(ac0_reg[plane-1], val); -} - -static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) -{ - u32 val; - const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0), - DISPC_VID_ACCU1(1) }; - - BUG_ON(plane == OMAP_DSS_GFX); - - val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); - dispc_write_reg(ac1_reg[plane-1], val); -} - - -static void _dispc_set_scaling(enum omap_plane plane, - u16 orig_width, u16 orig_height, - u16 out_width, u16 out_height, - bool ilace, bool five_taps, - bool fieldmode) -{ - int fir_hinc; - int fir_vinc; - int hscaleup, vscaleup; - int accu0 = 0; - int accu1 = 0; - u32 l; - - BUG_ON(plane == OMAP_DSS_GFX); - - hscaleup = orig_width <= out_width; - vscaleup = orig_height <= out_height; - - _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps); - - if (!orig_width || orig_width == out_width) - fir_hinc = 0; - else - fir_hinc = 1024 * orig_width / out_width; - - if (!orig_height || orig_height == out_height) - fir_vinc = 0; - else - fir_vinc = 1024 * orig_height / out_height; - - _dispc_set_fir(plane, fir_hinc, fir_vinc); - - l = dispc_read_reg(dispc_reg_att[plane]); - l &= ~((0x0f << 5) | (0x3 << 21)); - - l |= fir_hinc ? (1 << 5) : 0; - l |= fir_vinc ? (1 << 6) : 0; - - l |= hscaleup ? 0 : (1 << 7); - l |= vscaleup ? 0 : (1 << 8); - - l |= five_taps ? (1 << 21) : 0; - l |= five_taps ? (1 << 22) : 0; - - dispc_write_reg(dispc_reg_att[plane], l); - - /* - * field 0 = even field = bottom field - * field 1 = odd field = top field - */ - if (ilace && !fieldmode) { - accu1 = 0; - accu0 = (fir_vinc / 2) & 0x3ff; - if (accu0 >= 1024/2) { - accu1 = 1024/2; - accu0 -= accu1; - } - } - - _dispc_set_vid_accu0(plane, 0, accu0); - _dispc_set_vid_accu1(plane, 0, accu1); -} - -static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation, - bool mirroring, enum omap_color_mode color_mode) -{ - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) { - int vidrot = 0; - - if (mirroring) { - switch (rotation) { - case OMAP_DSS_ROT_0: - vidrot = 2; - break; - case OMAP_DSS_ROT_90: - vidrot = 1; - break; - case OMAP_DSS_ROT_180: - vidrot = 0; - break; - case OMAP_DSS_ROT_270: - vidrot = 3; - break; - } - } else { - switch (rotation) { - case OMAP_DSS_ROT_0: - vidrot = 0; - break; - case OMAP_DSS_ROT_90: - vidrot = 1; - break; - case OMAP_DSS_ROT_180: - vidrot = 2; - break; - case OMAP_DSS_ROT_270: - vidrot = 3; - break; - } - } - - REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12); - - if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) - REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18); - else - REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18); - } else { - REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12); - REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18); - } -} - -static int color_mode_to_bpp(enum omap_color_mode color_mode) -{ - switch (color_mode) { - case OMAP_DSS_COLOR_CLUT1: - return 1; - case OMAP_DSS_COLOR_CLUT2: - return 2; - case OMAP_DSS_COLOR_CLUT4: - return 4; - case OMAP_DSS_COLOR_CLUT8: - return 8; - case OMAP_DSS_COLOR_RGB12U: - case OMAP_DSS_COLOR_RGB16: - case OMAP_DSS_COLOR_ARGB16: - case OMAP_DSS_COLOR_YUV2: - case OMAP_DSS_COLOR_UYVY: - return 16; - case OMAP_DSS_COLOR_RGB24P: - return 24; - case OMAP_DSS_COLOR_RGB24U: - case OMAP_DSS_COLOR_ARGB32: - case OMAP_DSS_COLOR_RGBA32: - case OMAP_DSS_COLOR_RGBX32: - return 32; - default: - BUG(); - } -} - -static s32 pixinc(int pixels, u8 ps) -{ - if (pixels == 1) - return 1; - else if (pixels > 1) - return 1 + (pixels - 1) * ps; - else if (pixels < 0) - return 1 - (-pixels + 1) * ps; - else - BUG(); -} - -static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, - u16 screen_width, - u16 width, u16 height, - enum omap_color_mode color_mode, bool fieldmode, - unsigned int field_offset, - unsigned *offset0, unsigned *offset1, - s32 *row_inc, s32 *pix_inc) -{ - u8 ps; - - /* FIXME CLUT formats */ - switch (color_mode) { - case OMAP_DSS_COLOR_CLUT1: - case OMAP_DSS_COLOR_CLUT2: - case OMAP_DSS_COLOR_CLUT4: - case OMAP_DSS_COLOR_CLUT8: - BUG(); - return; - case OMAP_DSS_COLOR_YUV2: - case OMAP_DSS_COLOR_UYVY: - ps = 4; - break; - default: - ps = color_mode_to_bpp(color_mode) / 8; - break; - } - - DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, - width, height); - - /* - * field 0 = even field = bottom field - * field 1 = odd field = top field - */ - switch (rotation + mirror * 4) { - case OMAP_DSS_ROT_0: - case OMAP_DSS_ROT_180: - /* - * If the pixel format is YUV or UYVY divide the width - * of the image by 2 for 0 and 180 degree rotation. - */ - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) - width = width >> 1; - case OMAP_DSS_ROT_90: - case OMAP_DSS_ROT_270: - *offset1 = 0; - if (field_offset) - *offset0 = field_offset * screen_width * ps; - else - *offset0 = 0; - - *row_inc = pixinc(1 + (screen_width - width) + - (fieldmode ? screen_width : 0), - ps); - *pix_inc = pixinc(1, ps); - break; - - case OMAP_DSS_ROT_0 + 4: - case OMAP_DSS_ROT_180 + 4: - /* If the pixel format is YUV or UYVY divide the width - * of the image by 2 for 0 degree and 180 degree - */ - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) - width = width >> 1; - case OMAP_DSS_ROT_90 + 4: - case OMAP_DSS_ROT_270 + 4: - *offset1 = 0; - if (field_offset) - *offset0 = field_offset * screen_width * ps; - else - *offset0 = 0; - *row_inc = pixinc(1 - (screen_width + width) - - (fieldmode ? screen_width : 0), - ps); - *pix_inc = pixinc(1, ps); - break; - - default: - BUG(); - } -} - -static void calc_dma_rotation_offset(u8 rotation, bool mirror, - u16 screen_width, - u16 width, u16 height, - enum omap_color_mode color_mode, bool fieldmode, - unsigned int field_offset, - unsigned *offset0, unsigned *offset1, - s32 *row_inc, s32 *pix_inc) -{ - u8 ps; - u16 fbw, fbh; - - /* FIXME CLUT formats */ - switch (color_mode) { - case OMAP_DSS_COLOR_CLUT1: - case OMAP_DSS_COLOR_CLUT2: - case OMAP_DSS_COLOR_CLUT4: - case OMAP_DSS_COLOR_CLUT8: - BUG(); - return; - default: - ps = color_mode_to_bpp(color_mode) / 8; - break; - } - - DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, - width, height); - - /* width & height are overlay sizes, convert to fb sizes */ - - if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { - fbw = width; - fbh = height; - } else { - fbw = height; - fbh = width; - } - - /* - * field 0 = even field = bottom field - * field 1 = odd field = top field - */ - switch (rotation + mirror * 4) { - case OMAP_DSS_ROT_0: - *offset1 = 0; - if (field_offset) - *offset0 = *offset1 + field_offset * screen_width * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(1 + (screen_width - fbw) + - (fieldmode ? screen_width : 0), - ps); - *pix_inc = pixinc(1, ps); - break; - case OMAP_DSS_ROT_90: - *offset1 = screen_width * (fbh - 1) * ps; - if (field_offset) - *offset0 = *offset1 + field_offset * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(screen_width * (fbh - 1) + 1 + - (fieldmode ? 1 : 0), ps); - *pix_inc = pixinc(-screen_width, ps); - break; - case OMAP_DSS_ROT_180: - *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; - if (field_offset) - *offset0 = *offset1 - field_offset * screen_width * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(-1 - - (screen_width - fbw) - - (fieldmode ? screen_width : 0), - ps); - *pix_inc = pixinc(-1, ps); - break; - case OMAP_DSS_ROT_270: - *offset1 = (fbw - 1) * ps; - if (field_offset) - *offset0 = *offset1 - field_offset * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(-screen_width * (fbh - 1) - 1 - - (fieldmode ? 1 : 0), ps); - *pix_inc = pixinc(screen_width, ps); - break; - - /* mirroring */ - case OMAP_DSS_ROT_0 + 4: - *offset1 = (fbw - 1) * ps; - if (field_offset) - *offset0 = *offset1 + field_offset * screen_width * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(screen_width * 2 - 1 + - (fieldmode ? screen_width : 0), - ps); - *pix_inc = pixinc(-1, ps); - break; - - case OMAP_DSS_ROT_90 + 4: - *offset1 = 0; - if (field_offset) - *offset0 = *offset1 + field_offset * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(-screen_width * (fbh - 1) + 1 + - (fieldmode ? 1 : 0), - ps); - *pix_inc = pixinc(screen_width, ps); - break; - - case OMAP_DSS_ROT_180 + 4: - *offset1 = screen_width * (fbh - 1) * ps; - if (field_offset) - *offset0 = *offset1 - field_offset * screen_width * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(1 - screen_width * 2 - - (fieldmode ? screen_width : 0), - ps); - *pix_inc = pixinc(1, ps); - break; - - case OMAP_DSS_ROT_270 + 4: - *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; - if (field_offset) - *offset0 = *offset1 - field_offset * ps; - else - *offset0 = *offset1; - *row_inc = pixinc(screen_width * (fbh - 1) - 1 - - (fieldmode ? 1 : 0), - ps); - *pix_inc = pixinc(-screen_width, ps); - break; - - default: - BUG(); - } -} - -static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width, - u16 height, u16 out_width, u16 out_height, - enum omap_color_mode color_mode) -{ - u32 fclk = 0; - /* FIXME venc pclk? */ - u64 tmp, pclk = dispc_pclk_rate(channel); - - if (height > out_height) { - /* FIXME get real display PPL */ - unsigned int ppl = 800; - - tmp = pclk * height * out_width; - do_div(tmp, 2 * out_height * ppl); - fclk = tmp; - - if (height > 2 * out_height) { - if (ppl == out_width) - return 0; - - tmp = pclk * (height - 2 * out_height) * out_width; - do_div(tmp, 2 * out_height * (ppl - out_width)); - fclk = max(fclk, (u32) tmp); - } - } - - if (width > out_width) { - tmp = pclk * width; - do_div(tmp, out_width); - fclk = max(fclk, (u32) tmp); - - if (color_mode == OMAP_DSS_COLOR_RGB24U) - fclk <<= 1; - } - - return fclk; -} - -static unsigned long calc_fclk(enum omap_channel channel, u16 width, - u16 height, u16 out_width, u16 out_height) -{ - unsigned int hf, vf; - - /* - * FIXME how to determine the 'A' factor - * for the no downscaling case ? - */ - - if (width > 3 * out_width) - hf = 4; - else if (width > 2 * out_width) - hf = 3; - else if (width > out_width) - hf = 2; - else - hf = 1; - - if (height > out_height) - vf = 2; - else - vf = 1; - - /* FIXME venc pclk? */ - return dispc_pclk_rate(channel) * vf * hf; -} - -void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out) -{ - enable_clocks(1); - _dispc_set_channel_out(plane, channel_out); - enable_clocks(0); -} - -static int _dispc_setup_plane(enum omap_plane plane, - u32 paddr, u16 screen_width, - u16 pos_x, u16 pos_y, - u16 width, u16 height, - u16 out_width, u16 out_height, - enum omap_color_mode color_mode, - bool ilace, - enum omap_dss_rotation_type rotation_type, - u8 rotation, int mirror, - u8 global_alpha, u8 pre_mult_alpha, - enum omap_channel channel) -{ - const int maxdownscale = cpu_is_omap34xx() ? 4 : 2; - bool five_taps = 0; - bool fieldmode = 0; - int cconv = 0; - unsigned offset0, offset1; - s32 row_inc; - s32 pix_inc; - u16 frame_height = height; - unsigned int field_offset = 0; - - if (paddr == 0) - return -EINVAL; - - if (ilace && height == out_height) - fieldmode = 1; - - if (ilace) { - if (fieldmode) - height /= 2; - pos_y /= 2; - out_height /= 2; - - DSSDBG("adjusting for ilace: height %d, pos_y %d, " - "out_height %d\n", - height, pos_y, out_height); - } - - if (!dss_feat_color_mode_supported(plane, color_mode)) - return -EINVAL; - - if (plane == OMAP_DSS_GFX) { - if (width != out_width || height != out_height) - return -EINVAL; - } else { - /* video plane */ - - unsigned long fclk = 0; - - if (out_width < width / maxdownscale || - out_width > width * 8) - return -EINVAL; - - if (out_height < height / maxdownscale || - out_height > height * 8) - return -EINVAL; - - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) - cconv = 1; - - /* Must use 5-tap filter? */ - five_taps = height > out_height * 2; - - if (!five_taps) { - fclk = calc_fclk(channel, width, height, out_width, - out_height); - - /* Try 5-tap filter if 3-tap fclk is too high */ - if (cpu_is_omap34xx() && height > out_height && - fclk > dispc_fclk_rate()) - five_taps = true; - } - - if (width > (2048 >> five_taps)) { - DSSERR("failed to set up scaling, fclk too low\n"); - return -EINVAL; - } - - if (five_taps) - fclk = calc_fclk_five_taps(channel, width, height, - out_width, out_height, color_mode); - - DSSDBG("required fclk rate = %lu Hz\n", fclk); - DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate()); - - if (!fclk || fclk > dispc_fclk_rate()) { - DSSERR("failed to set up scaling, " - "required fclk rate = %lu Hz, " - "current fclk rate = %lu Hz\n", - fclk, dispc_fclk_rate()); - return -EINVAL; - } - } - - if (ilace && !fieldmode) { - /* - * when downscaling the bottom field may have to start several - * source lines below the top field. Unfortunately ACCUI - * registers will only hold the fractional part of the offset - * so the integer part must be added to the base address of the - * bottom field. - */ - if (!height || height == out_height) - field_offset = 0; - else - field_offset = height / out_height / 2; - } - - /* Fields are independent but interleaved in memory. */ - if (fieldmode) - field_offset = 1; - - if (rotation_type == OMAP_DSS_ROT_DMA) - calc_dma_rotation_offset(rotation, mirror, - screen_width, width, frame_height, color_mode, - fieldmode, field_offset, - &offset0, &offset1, &row_inc, &pix_inc); - else - calc_vrfb_rotation_offset(rotation, mirror, - screen_width, width, frame_height, color_mode, - fieldmode, field_offset, - &offset0, &offset1, &row_inc, &pix_inc); - - DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", - offset0, offset1, row_inc, pix_inc); - - _dispc_set_color_mode(plane, color_mode); - - _dispc_set_plane_ba0(plane, paddr + offset0); - _dispc_set_plane_ba1(plane, paddr + offset1); - - _dispc_set_row_inc(plane, row_inc); - _dispc_set_pix_inc(plane, pix_inc); - - DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height, - out_width, out_height); - - _dispc_set_plane_pos(plane, pos_x, pos_y); - - _dispc_set_pic_size(plane, width, height); - - if (plane != OMAP_DSS_GFX) { - _dispc_set_scaling(plane, width, height, - out_width, out_height, - ilace, five_taps, fieldmode); - _dispc_set_vid_size(plane, out_width, out_height); - _dispc_set_vid_color_conv(plane, cconv); - } - - _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode); - - _dispc_set_pre_mult_alpha(plane, pre_mult_alpha); - _dispc_setup_global_alpha(plane, global_alpha); - - return 0; -} - -static void _dispc_enable_plane(enum omap_plane plane, bool enable) -{ - REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0); -} - -static void dispc_disable_isr(void *data, u32 mask) -{ - struct completion *compl = data; - complete(compl); -} - -static void _enable_lcd_out(enum omap_channel channel, bool enable) -{ - if (channel == OMAP_DSS_CHANNEL_LCD2) - REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0); - else - REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0); -} - -static void dispc_enable_lcd_out(enum omap_channel channel, bool enable) -{ - struct completion frame_done_completion; - bool is_on; - int r; - u32 irq; - - enable_clocks(1); - - /* When we disable LCD output, we need to wait until frame is done. - * Otherwise the DSS is still working, and turning off the clocks - * prevents DSS from going to OFF mode */ - is_on = channel == OMAP_DSS_CHANNEL_LCD2 ? - REG_GET(DISPC_CONTROL2, 0, 0) : - REG_GET(DISPC_CONTROL, 0, 0); - - irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 : - DISPC_IRQ_FRAMEDONE; - - if (!enable && is_on) { - init_completion(&frame_done_completion); - - r = omap_dispc_register_isr(dispc_disable_isr, - &frame_done_completion, irq); - - if (r) - DSSERR("failed to register FRAMEDONE isr\n"); - } - - _enable_lcd_out(channel, enable); - - if (!enable && is_on) { - if (!wait_for_completion_timeout(&frame_done_completion, - msecs_to_jiffies(100))) - DSSERR("timeout waiting for FRAME DONE\n"); - - r = omap_dispc_unregister_isr(dispc_disable_isr, - &frame_done_completion, irq); - - if (r) - DSSERR("failed to unregister FRAMEDONE isr\n"); - } - - enable_clocks(0); -} - -static void _enable_digit_out(bool enable) -{ - REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1); -} - -static void dispc_enable_digit_out(bool enable) -{ - struct completion frame_done_completion; - int r; - - enable_clocks(1); - - if (REG_GET(DISPC_CONTROL, 1, 1) == enable) { - enable_clocks(0); - return; - } - - if (enable) { - unsigned long flags; - /* When we enable digit output, we'll get an extra digit - * sync lost interrupt, that we need to ignore */ - spin_lock_irqsave(&dispc.irq_lock, flags); - dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT; - _omap_dispc_set_irqs(); - spin_unlock_irqrestore(&dispc.irq_lock, flags); - } - - /* When we disable digit output, we need to wait until fields are done. - * Otherwise the DSS is still working, and turning off the clocks - * prevents DSS from going to OFF mode. And when enabling, we need to - * wait for the extra sync losts */ - init_completion(&frame_done_completion); - - r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion, - DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD); - if (r) - DSSERR("failed to register EVSYNC isr\n"); - - _enable_digit_out(enable); - - /* XXX I understand from TRM that we should only wait for the - * current field to complete. But it seems we have to wait - * for both fields */ - if (!wait_for_completion_timeout(&frame_done_completion, - msecs_to_jiffies(100))) - DSSERR("timeout waiting for EVSYNC\n"); - - if (!wait_for_completion_timeout(&frame_done_completion, - msecs_to_jiffies(100))) - DSSERR("timeout waiting for EVSYNC\n"); - - r = omap_dispc_unregister_isr(dispc_disable_isr, - &frame_done_completion, - DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD); - if (r) - DSSERR("failed to unregister EVSYNC isr\n"); - - if (enable) { - unsigned long flags; - spin_lock_irqsave(&dispc.irq_lock, flags); - dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR; - if (dss_has_feature(FEAT_MGR_LCD2)) - dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2; - dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); - _omap_dispc_set_irqs(); - spin_unlock_irqrestore(&dispc.irq_lock, flags); - } - - enable_clocks(0); -} - -bool dispc_is_channel_enabled(enum omap_channel channel) -{ - if (channel == OMAP_DSS_CHANNEL_LCD) - return !!REG_GET(DISPC_CONTROL, 0, 0); - else if (channel == OMAP_DSS_CHANNEL_DIGIT) - return !!REG_GET(DISPC_CONTROL, 1, 1); - else if (channel == OMAP_DSS_CHANNEL_LCD2) - return !!REG_GET(DISPC_CONTROL2, 0, 0); - else - BUG(); -} - -void dispc_enable_channel(enum omap_channel channel, bool enable) -{ - if (channel == OMAP_DSS_CHANNEL_LCD || - channel == OMAP_DSS_CHANNEL_LCD2) - dispc_enable_lcd_out(channel, enable); - else if (channel == OMAP_DSS_CHANNEL_DIGIT) - dispc_enable_digit_out(enable); - else - BUG(); -} - -void dispc_lcd_enable_signal_polarity(bool act_high) -{ - if (!dss_has_feature(FEAT_LCDENABLEPOL)) - return; - - enable_clocks(1); - REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); - enable_clocks(0); -} - -void dispc_lcd_enable_signal(bool enable) -{ - if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) - return; - - enable_clocks(1); - REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); - enable_clocks(0); -} - -void dispc_pck_free_enable(bool enable) -{ - if (!dss_has_feature(FEAT_PCKFREEENABLE)) - return; - - enable_clocks(1); - REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); - enable_clocks(0); -} - -void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable) -{ - enable_clocks(1); - if (channel == OMAP_DSS_CHANNEL_LCD2) - REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16); - else - REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16); - enable_clocks(0); -} - - -void dispc_set_lcd_display_type(enum omap_channel channel, - enum omap_lcd_display_type type) -{ - int mode; - - switch (type) { - case OMAP_DSS_LCD_DISPLAY_STN: - mode = 0; - break; - - case OMAP_DSS_LCD_DISPLAY_TFT: - mode = 1; - break; - - default: - BUG(); - return; - } - - enable_clocks(1); - if (channel == OMAP_DSS_CHANNEL_LCD2) - REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3); - else - REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3); - enable_clocks(0); -} - -void dispc_set_loadmode(enum omap_dss_load_mode mode) -{ - enable_clocks(1); - REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); - enable_clocks(0); -} - - -void dispc_set_default_color(enum omap_channel channel, u32 color) -{ - enable_clocks(1); - dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); - enable_clocks(0); -} - -u32 dispc_get_default_color(enum omap_channel channel) -{ - u32 l; - - BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT && - channel != OMAP_DSS_CHANNEL_LCD && - channel != OMAP_DSS_CHANNEL_LCD2); - - enable_clocks(1); - l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel)); - enable_clocks(0); - - return l; -} - -void dispc_set_trans_key(enum omap_channel ch, - enum omap_dss_trans_key_type type, - u32 trans_key) -{ - enable_clocks(1); - if (ch == OMAP_DSS_CHANNEL_LCD) - REG_FLD_MOD(DISPC_CONFIG, type, 11, 11); - else if (ch == OMAP_DSS_CHANNEL_DIGIT) - REG_FLD_MOD(DISPC_CONFIG, type, 13, 13); - else /* OMAP_DSS_CHANNEL_LCD2 */ - REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11); - - dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); - enable_clocks(0); -} - -void dispc_get_trans_key(enum omap_channel ch, - enum omap_dss_trans_key_type *type, - u32 *trans_key) -{ - enable_clocks(1); - if (type) { - if (ch == OMAP_DSS_CHANNEL_LCD) - *type = REG_GET(DISPC_CONFIG, 11, 11); - else if (ch == OMAP_DSS_CHANNEL_DIGIT) - *type = REG_GET(DISPC_CONFIG, 13, 13); - else if (ch == OMAP_DSS_CHANNEL_LCD2) - *type = REG_GET(DISPC_CONFIG2, 11, 11); - else - BUG(); - } - - if (trans_key) - *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch)); - enable_clocks(0); -} - -void dispc_enable_trans_key(enum omap_channel ch, bool enable) -{ - enable_clocks(1); - if (ch == OMAP_DSS_CHANNEL_LCD) - REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10); - else if (ch == OMAP_DSS_CHANNEL_DIGIT) - REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12); - else /* OMAP_DSS_CHANNEL_LCD2 */ - REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10); - enable_clocks(0); -} -void dispc_enable_alpha_blending(enum omap_channel ch, bool enable) -{ - if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) - return; - - enable_clocks(1); - if (ch == OMAP_DSS_CHANNEL_LCD) - REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); - else if (ch == OMAP_DSS_CHANNEL_DIGIT) - REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); - else /* OMAP_DSS_CHANNEL_LCD2 */ - REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18); - enable_clocks(0); -} -bool dispc_alpha_blending_enabled(enum omap_channel ch) -{ - bool enabled; - - if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) - return false; - - enable_clocks(1); - if (ch == OMAP_DSS_CHANNEL_LCD) - enabled = REG_GET(DISPC_CONFIG, 18, 18); - else if (ch == OMAP_DSS_CHANNEL_DIGIT) - enabled = REG_GET(DISPC_CONFIG, 19, 19); - else if (ch == OMAP_DSS_CHANNEL_LCD2) - enabled = REG_GET(DISPC_CONFIG2, 18, 18); - else - BUG(); - enable_clocks(0); - - return enabled; -} - - -bool dispc_trans_key_enabled(enum omap_channel ch) -{ - bool enabled; - - enable_clocks(1); - if (ch == OMAP_DSS_CHANNEL_LCD) - enabled = REG_GET(DISPC_CONFIG, 10, 10); - else if (ch == OMAP_DSS_CHANNEL_DIGIT) - enabled = REG_GET(DISPC_CONFIG, 12, 12); - else if (ch == OMAP_DSS_CHANNEL_LCD2) - enabled = REG_GET(DISPC_CONFIG2, 10, 10); - else - BUG(); - enable_clocks(0); - - return enabled; -} - - -void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines) -{ - int code; - - switch (data_lines) { - case 12: - code = 0; - break; - case 16: - code = 1; - break; - case 18: - code = 2; - break; - case 24: - code = 3; - break; - default: - BUG(); - return; - } - - enable_clocks(1); - if (channel == OMAP_DSS_CHANNEL_LCD2) - REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8); - else - REG_FLD_MOD(DISPC_CONTROL, code, 9, 8); - enable_clocks(0); -} - -void dispc_set_parallel_interface_mode(enum omap_channel channel, - enum omap_parallel_interface_mode mode) -{ - u32 l; - int stallmode; - int gpout0 = 1; - int gpout1; - - switch (mode) { - case OMAP_DSS_PARALLELMODE_BYPASS: - stallmode = 0; - gpout1 = 1; - break; - - case OMAP_DSS_PARALLELMODE_RFBI: - stallmode = 1; - gpout1 = 0; - break; - - case OMAP_DSS_PARALLELMODE_DSI: - stallmode = 1; - gpout1 = 1; - break; - - default: - BUG(); - return; - } - - enable_clocks(1); - - if (channel == OMAP_DSS_CHANNEL_LCD2) { - l = dispc_read_reg(DISPC_CONTROL2); - l = FLD_MOD(l, stallmode, 11, 11); - dispc_write_reg(DISPC_CONTROL2, l); - } else { - l = dispc_read_reg(DISPC_CONTROL); - l = FLD_MOD(l, stallmode, 11, 11); - l = FLD_MOD(l, gpout0, 15, 15); - l = FLD_MOD(l, gpout1, 16, 16); - dispc_write_reg(DISPC_CONTROL, l); - } - - enable_clocks(0); -} - -static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, - int vsw, int vfp, int vbp) -{ - if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) { - if (hsw < 1 || hsw > 64 || - hfp < 1 || hfp > 256 || - hbp < 1 || hbp > 256 || - vsw < 1 || vsw > 64 || - vfp < 0 || vfp > 255 || - vbp < 0 || vbp > 255) - return false; - } else { - if (hsw < 1 || hsw > 256 || - hfp < 1 || hfp > 4096 || - hbp < 1 || hbp > 4096 || - vsw < 1 || vsw > 256 || - vfp < 0 || vfp > 4095 || - vbp < 0 || vbp > 4095) - return false; - } - - return true; -} - -bool dispc_lcd_timings_ok(struct omap_video_timings *timings) -{ - return _dispc_lcd_timings_ok(timings->hsw, timings->hfp, - timings->hbp, timings->vsw, - timings->vfp, timings->vbp); -} - -static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw, - int hfp, int hbp, int vsw, int vfp, int vbp) -{ - u32 timing_h, timing_v; - - if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) { - timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) | - FLD_VAL(hbp-1, 27, 20); - - timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) | - FLD_VAL(vbp, 27, 20); - } else { - timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) | - FLD_VAL(hbp-1, 31, 20); - - timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) | - FLD_VAL(vbp, 31, 20); - } - - enable_clocks(1); - dispc_write_reg(DISPC_TIMING_H(channel), timing_h); - dispc_write_reg(DISPC_TIMING_V(channel), timing_v); - enable_clocks(0); -} - -/* change name to mode? */ -void dispc_set_lcd_timings(enum omap_channel channel, - struct omap_video_timings *timings) -{ - unsigned xtot, ytot; - unsigned long ht, vt; - - if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, - timings->hbp, timings->vsw, - timings->vfp, timings->vbp)) - BUG(); - - _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp, - timings->hbp, timings->vsw, timings->vfp, - timings->vbp); - - dispc_set_lcd_size(channel, timings->x_res, timings->y_res); - - xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp; - ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp; - - ht = (timings->pixel_clock * 1000) / xtot; - vt = (timings->pixel_clock * 1000) / xtot / ytot; - - DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res, - timings->y_res); - DSSDBG("pck %u\n", timings->pixel_clock); - DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", - timings->hsw, timings->hfp, timings->hbp, - timings->vsw, timings->vfp, timings->vbp); - - DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); -} - -static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div, - u16 pck_div) -{ - BUG_ON(lck_div < 1); - BUG_ON(pck_div < 2); - - enable_clocks(1); - dispc_write_reg(DISPC_DIVISOR(channel), - FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); - enable_clocks(0); -} - -static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div, - int *pck_div) -{ - u32 l; - l = dispc_read_reg(DISPC_DIVISOR(channel)); - *lck_div = FLD_GET(l, 23, 16); - *pck_div = FLD_GET(l, 7, 0); -} - -unsigned long dispc_fclk_rate(void) -{ - unsigned long r = 0; - - if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) - r = dss_clk_get_rate(DSS_CLK_FCK1); - else -#ifdef CONFIG_OMAP2_DSS_DSI - r = dsi_get_dsi1_pll_rate(); -#else - BUG(); -#endif - return r; -} - -unsigned long dispc_lclk_rate(enum omap_channel channel) -{ - int lcd; - unsigned long r; - u32 l; - - l = dispc_read_reg(DISPC_DIVISOR(channel)); - - lcd = FLD_GET(l, 23, 16); - - r = dispc_fclk_rate(); - - return r / lcd; -} - -unsigned long dispc_pclk_rate(enum omap_channel channel) -{ - int lcd, pcd; - unsigned long r; - u32 l; - - l = dispc_read_reg(DISPC_DIVISOR(channel)); - - lcd = FLD_GET(l, 23, 16); - pcd = FLD_GET(l, 7, 0); - - r = dispc_fclk_rate(); - - return r / lcd / pcd; -} - -void dispc_dump_clocks(struct seq_file *s) -{ - int lcd, pcd; - - enable_clocks(1); - - seq_printf(s, "- DISPC -\n"); - - seq_printf(s, "dispc fclk source = %s\n", - dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? - "dss1_alwon_fclk" : "dsi1_pll_fclk"); - - seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); - - seq_printf(s, "- LCD1 -\n"); - - dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd); - - seq_printf(s, "lck\t\t%-16lulck div\t%u\n", - dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd); - seq_printf(s, "pck\t\t%-16lupck div\t%u\n", - dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd); - if (dss_has_feature(FEAT_MGR_LCD2)) { - seq_printf(s, "- LCD2 -\n"); - - dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd); - - seq_printf(s, "lck\t\t%-16lulck div\t%u\n", - dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd); - seq_printf(s, "pck\t\t%-16lupck div\t%u\n", - dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd); - } - enable_clocks(0); -} - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS -void dispc_dump_irqs(struct seq_file *s) -{ - unsigned long flags; - struct dispc_irq_stats stats; - - spin_lock_irqsave(&dispc.irq_stats_lock, flags); - - stats = dispc.irq_stats; - memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats)); - dispc.irq_stats.last_reset = jiffies; - - spin_unlock_irqrestore(&dispc.irq_stats_lock, flags); - - seq_printf(s, "period %u ms\n", - jiffies_to_msecs(jiffies - stats.last_reset)); - - seq_printf(s, "irqs %d\n", stats.irq_count); -#define PIS(x) \ - seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]); - - PIS(FRAMEDONE); - PIS(VSYNC); - PIS(EVSYNC_EVEN); - PIS(EVSYNC_ODD); - PIS(ACBIAS_COUNT_STAT); - PIS(PROG_LINE_NUM); - PIS(GFX_FIFO_UNDERFLOW); - PIS(GFX_END_WIN); - PIS(PAL_GAMMA_MASK); - PIS(OCP_ERR); - PIS(VID1_FIFO_UNDERFLOW); - PIS(VID1_END_WIN); - PIS(VID2_FIFO_UNDERFLOW); - PIS(VID2_END_WIN); - PIS(SYNC_LOST); - PIS(SYNC_LOST_DIGIT); - PIS(WAKEUP); - if (dss_has_feature(FEAT_MGR_LCD2)) { - PIS(FRAMEDONE2); - PIS(VSYNC2); - PIS(ACBIAS_COUNT_STAT2); - PIS(SYNC_LOST2); - } -#undef PIS -} -#endif - -void dispc_dump_regs(struct seq_file *s) -{ -#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r)) - - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - - DUMPREG(DISPC_REVISION); - DUMPREG(DISPC_SYSCONFIG); - DUMPREG(DISPC_SYSSTATUS); - DUMPREG(DISPC_IRQSTATUS); - DUMPREG(DISPC_IRQENABLE); - DUMPREG(DISPC_CONTROL); - DUMPREG(DISPC_CONFIG); - DUMPREG(DISPC_CAPABLE); - DUMPREG(DISPC_DEFAULT_COLOR(0)); - DUMPREG(DISPC_DEFAULT_COLOR(1)); - DUMPREG(DISPC_TRANS_COLOR(0)); - DUMPREG(DISPC_TRANS_COLOR(1)); - DUMPREG(DISPC_LINE_STATUS); - DUMPREG(DISPC_LINE_NUMBER); - DUMPREG(DISPC_TIMING_H(0)); - DUMPREG(DISPC_TIMING_V(0)); - DUMPREG(DISPC_POL_FREQ(0)); - DUMPREG(DISPC_DIVISOR(0)); - DUMPREG(DISPC_GLOBAL_ALPHA); - DUMPREG(DISPC_SIZE_DIG); - DUMPREG(DISPC_SIZE_LCD(0)); - if (dss_has_feature(FEAT_MGR_LCD2)) { - DUMPREG(DISPC_CONTROL2); - DUMPREG(DISPC_CONFIG2); - DUMPREG(DISPC_DEFAULT_COLOR(2)); - DUMPREG(DISPC_TRANS_COLOR(2)); - DUMPREG(DISPC_TIMING_H(2)); - DUMPREG(DISPC_TIMING_V(2)); - DUMPREG(DISPC_POL_FREQ(2)); - DUMPREG(DISPC_DIVISOR(2)); - DUMPREG(DISPC_SIZE_LCD(2)); - } - - DUMPREG(DISPC_GFX_BA0); - DUMPREG(DISPC_GFX_BA1); - DUMPREG(DISPC_GFX_POSITION); - DUMPREG(DISPC_GFX_SIZE); - DUMPREG(DISPC_GFX_ATTRIBUTES); - DUMPREG(DISPC_GFX_FIFO_THRESHOLD); - DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS); - DUMPREG(DISPC_GFX_ROW_INC); - DUMPREG(DISPC_GFX_PIXEL_INC); - DUMPREG(DISPC_GFX_WINDOW_SKIP); - DUMPREG(DISPC_GFX_TABLE_BA); - - DUMPREG(DISPC_DATA_CYCLE1(0)); - DUMPREG(DISPC_DATA_CYCLE2(0)); - DUMPREG(DISPC_DATA_CYCLE3(0)); - - DUMPREG(DISPC_CPR_COEF_R(0)); - DUMPREG(DISPC_CPR_COEF_G(0)); - DUMPREG(DISPC_CPR_COEF_B(0)); - if (dss_has_feature(FEAT_MGR_LCD2)) { - DUMPREG(DISPC_DATA_CYCLE1(2)); - DUMPREG(DISPC_DATA_CYCLE2(2)); - DUMPREG(DISPC_DATA_CYCLE3(2)); - - DUMPREG(DISPC_CPR_COEF_R(2)); - DUMPREG(DISPC_CPR_COEF_G(2)); - DUMPREG(DISPC_CPR_COEF_B(2)); - } - - DUMPREG(DISPC_GFX_PRELOAD); - - DUMPREG(DISPC_VID_BA0(0)); - DUMPREG(DISPC_VID_BA1(0)); - DUMPREG(DISPC_VID_POSITION(0)); - DUMPREG(DISPC_VID_SIZE(0)); - DUMPREG(DISPC_VID_ATTRIBUTES(0)); - DUMPREG(DISPC_VID_FIFO_THRESHOLD(0)); - DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0)); - DUMPREG(DISPC_VID_ROW_INC(0)); - DUMPREG(DISPC_VID_PIXEL_INC(0)); - DUMPREG(DISPC_VID_FIR(0)); - DUMPREG(DISPC_VID_PICTURE_SIZE(0)); - DUMPREG(DISPC_VID_ACCU0(0)); - DUMPREG(DISPC_VID_ACCU1(0)); - - DUMPREG(DISPC_VID_BA0(1)); - DUMPREG(DISPC_VID_BA1(1)); - DUMPREG(DISPC_VID_POSITION(1)); - DUMPREG(DISPC_VID_SIZE(1)); - DUMPREG(DISPC_VID_ATTRIBUTES(1)); - DUMPREG(DISPC_VID_FIFO_THRESHOLD(1)); - DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1)); - DUMPREG(DISPC_VID_ROW_INC(1)); - DUMPREG(DISPC_VID_PIXEL_INC(1)); - DUMPREG(DISPC_VID_FIR(1)); - DUMPREG(DISPC_VID_PICTURE_SIZE(1)); - DUMPREG(DISPC_VID_ACCU0(1)); - DUMPREG(DISPC_VID_ACCU1(1)); - - DUMPREG(DISPC_VID_FIR_COEF_H(0, 0)); - DUMPREG(DISPC_VID_FIR_COEF_H(0, 1)); - DUMPREG(DISPC_VID_FIR_COEF_H(0, 2)); - DUMPREG(DISPC_VID_FIR_COEF_H(0, 3)); - DUMPREG(DISPC_VID_FIR_COEF_H(0, 4)); - DUMPREG(DISPC_VID_FIR_COEF_H(0, 5)); - DUMPREG(DISPC_VID_FIR_COEF_H(0, 6)); - DUMPREG(DISPC_VID_FIR_COEF_H(0, 7)); - DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0)); - DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1)); - DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2)); - DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3)); - DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4)); - DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5)); - DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6)); - DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7)); - DUMPREG(DISPC_VID_CONV_COEF(0, 0)); - DUMPREG(DISPC_VID_CONV_COEF(0, 1)); - DUMPREG(DISPC_VID_CONV_COEF(0, 2)); - DUMPREG(DISPC_VID_CONV_COEF(0, 3)); - DUMPREG(DISPC_VID_CONV_COEF(0, 4)); - DUMPREG(DISPC_VID_FIR_COEF_V(0, 0)); - DUMPREG(DISPC_VID_FIR_COEF_V(0, 1)); - DUMPREG(DISPC_VID_FIR_COEF_V(0, 2)); - DUMPREG(DISPC_VID_FIR_COEF_V(0, 3)); - DUMPREG(DISPC_VID_FIR_COEF_V(0, 4)); - DUMPREG(DISPC_VID_FIR_COEF_V(0, 5)); - DUMPREG(DISPC_VID_FIR_COEF_V(0, 6)); - DUMPREG(DISPC_VID_FIR_COEF_V(0, 7)); - - DUMPREG(DISPC_VID_FIR_COEF_H(1, 0)); - DUMPREG(DISPC_VID_FIR_COEF_H(1, 1)); - DUMPREG(DISPC_VID_FIR_COEF_H(1, 2)); - DUMPREG(DISPC_VID_FIR_COEF_H(1, 3)); - DUMPREG(DISPC_VID_FIR_COEF_H(1, 4)); - DUMPREG(DISPC_VID_FIR_COEF_H(1, 5)); - DUMPREG(DISPC_VID_FIR_COEF_H(1, 6)); - DUMPREG(DISPC_VID_FIR_COEF_H(1, 7)); - DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0)); - DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1)); - DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2)); - DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3)); - DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4)); - DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5)); - DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6)); - DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7)); - DUMPREG(DISPC_VID_CONV_COEF(1, 0)); - DUMPREG(DISPC_VID_CONV_COEF(1, 1)); - DUMPREG(DISPC_VID_CONV_COEF(1, 2)); - DUMPREG(DISPC_VID_CONV_COEF(1, 3)); - DUMPREG(DISPC_VID_CONV_COEF(1, 4)); - DUMPREG(DISPC_VID_FIR_COEF_V(1, 0)); - DUMPREG(DISPC_VID_FIR_COEF_V(1, 1)); - DUMPREG(DISPC_VID_FIR_COEF_V(1, 2)); - DUMPREG(DISPC_VID_FIR_COEF_V(1, 3)); - DUMPREG(DISPC_VID_FIR_COEF_V(1, 4)); - DUMPREG(DISPC_VID_FIR_COEF_V(1, 5)); - DUMPREG(DISPC_VID_FIR_COEF_V(1, 6)); - DUMPREG(DISPC_VID_FIR_COEF_V(1, 7)); - - DUMPREG(DISPC_VID_PRELOAD(0)); - DUMPREG(DISPC_VID_PRELOAD(1)); - - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -#undef DUMPREG -} - -static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf, - bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb) -{ - u32 l = 0; - - DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n", - onoff, rf, ieo, ipc, ihs, ivs, acbi, acb); - - l |= FLD_VAL(onoff, 17, 17); - l |= FLD_VAL(rf, 16, 16); - l |= FLD_VAL(ieo, 15, 15); - l |= FLD_VAL(ipc, 14, 14); - l |= FLD_VAL(ihs, 13, 13); - l |= FLD_VAL(ivs, 12, 12); - l |= FLD_VAL(acbi, 11, 8); - l |= FLD_VAL(acb, 7, 0); - - enable_clocks(1); - dispc_write_reg(DISPC_POL_FREQ(channel), l); - enable_clocks(0); -} - -void dispc_set_pol_freq(enum omap_channel channel, - enum omap_panel_config config, u8 acbi, u8 acb) -{ - _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0, - (config & OMAP_DSS_LCD_RF) != 0, - (config & OMAP_DSS_LCD_IEO) != 0, - (config & OMAP_DSS_LCD_IPC) != 0, - (config & OMAP_DSS_LCD_IHS) != 0, - (config & OMAP_DSS_LCD_IVS) != 0, - acbi, acb); -} - -/* with fck as input clock rate, find dispc dividers that produce req_pck */ -void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck, - struct dispc_clock_info *cinfo) -{ - u16 pcd_min = is_tft ? 2 : 3; - unsigned long best_pck; - u16 best_ld, cur_ld; - u16 best_pd, cur_pd; - - best_pck = 0; - best_ld = 0; - best_pd = 0; - - for (cur_ld = 1; cur_ld <= 255; ++cur_ld) { - unsigned long lck = fck / cur_ld; - - for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) { - unsigned long pck = lck / cur_pd; - long old_delta = abs(best_pck - req_pck); - long new_delta = abs(pck - req_pck); - - if (best_pck == 0 || new_delta < old_delta) { - best_pck = pck; - best_ld = cur_ld; - best_pd = cur_pd; - - if (pck == req_pck) - goto found; - } - - if (pck < req_pck) - break; - } - - if (lck / pcd_min < req_pck) - break; - } - -found: - cinfo->lck_div = best_ld; - cinfo->pck_div = best_pd; - cinfo->lck = fck / cinfo->lck_div; - cinfo->pck = cinfo->lck / cinfo->pck_div; -} - -/* calculate clock rates using dividers in cinfo */ -int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, - struct dispc_clock_info *cinfo) -{ - if (cinfo->lck_div > 255 || cinfo->lck_div == 0) - return -EINVAL; - if (cinfo->pck_div < 2 || cinfo->pck_div > 255) - return -EINVAL; - - cinfo->lck = dispc_fclk_rate / cinfo->lck_div; - cinfo->pck = cinfo->lck / cinfo->pck_div; - - return 0; -} - -int dispc_set_clock_div(enum omap_channel channel, - struct dispc_clock_info *cinfo) -{ - DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); - DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); - - dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); - - return 0; -} - -int dispc_get_clock_div(enum omap_channel channel, - struct dispc_clock_info *cinfo) -{ - unsigned long fck; - - fck = dispc_fclk_rate(); - - cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16); - cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0); - - cinfo->lck = fck / cinfo->lck_div; - cinfo->pck = cinfo->lck / cinfo->pck_div; - - return 0; -} - -/* dispc.irq_lock has to be locked by the caller */ -static void _omap_dispc_set_irqs(void) -{ - u32 mask; - u32 old_mask; - int i; - struct omap_dispc_isr_data *isr_data; - - mask = dispc.irq_error_mask; - - for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { - isr_data = &dispc.registered_isr[i]; - - if (isr_data->isr == NULL) - continue; - - mask |= isr_data->mask; - } - - enable_clocks(1); - - old_mask = dispc_read_reg(DISPC_IRQENABLE); - /* clear the irqstatus for newly enabled irqs */ - dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask); - - dispc_write_reg(DISPC_IRQENABLE, mask); - - enable_clocks(0); -} - -int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) -{ - int i; - int ret; - unsigned long flags; - struct omap_dispc_isr_data *isr_data; - - if (isr == NULL) - return -EINVAL; - - spin_lock_irqsave(&dispc.irq_lock, flags); - - /* check for duplicate entry */ - for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { - isr_data = &dispc.registered_isr[i]; - if (isr_data->isr == isr && isr_data->arg == arg && - isr_data->mask == mask) { - ret = -EINVAL; - goto err; - } - } - - isr_data = NULL; - ret = -EBUSY; - - for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { - isr_data = &dispc.registered_isr[i]; - - if (isr_data->isr != NULL) - continue; - - isr_data->isr = isr; - isr_data->arg = arg; - isr_data->mask = mask; - ret = 0; - - break; - } - - _omap_dispc_set_irqs(); - - spin_unlock_irqrestore(&dispc.irq_lock, flags); - - return 0; -err: - spin_unlock_irqrestore(&dispc.irq_lock, flags); - - return ret; -} -EXPORT_SYMBOL(omap_dispc_register_isr); - -int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask) -{ - int i; - unsigned long flags; - int ret = -EINVAL; - struct omap_dispc_isr_data *isr_data; - - spin_lock_irqsave(&dispc.irq_lock, flags); - - for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { - isr_data = &dispc.registered_isr[i]; - if (isr_data->isr != isr || isr_data->arg != arg || - isr_data->mask != mask) - continue; - - /* found the correct isr */ - - isr_data->isr = NULL; - isr_data->arg = NULL; - isr_data->mask = 0; - - ret = 0; - break; - } - - if (ret == 0) - _omap_dispc_set_irqs(); - - spin_unlock_irqrestore(&dispc.irq_lock, flags); - - return ret; -} -EXPORT_SYMBOL(omap_dispc_unregister_isr); - -#ifdef DEBUG -static void print_irq_status(u32 status) -{ - if ((status & dispc.irq_error_mask) == 0) - return; - - printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status); - -#define PIS(x) \ - if (status & DISPC_IRQ_##x) \ - printk(#x " "); - PIS(GFX_FIFO_UNDERFLOW); - PIS(OCP_ERR); - PIS(VID1_FIFO_UNDERFLOW); - PIS(VID2_FIFO_UNDERFLOW); - PIS(SYNC_LOST); - PIS(SYNC_LOST_DIGIT); - if (dss_has_feature(FEAT_MGR_LCD2)) - PIS(SYNC_LOST2); -#undef PIS - - printk("\n"); -} -#endif - -/* Called from dss.c. Note that we don't touch clocks here, - * but we presume they are on because we got an IRQ. However, - * an irq handler may turn the clocks off, so we may not have - * clock later in the function. */ -void dispc_irq_handler(void) -{ - int i; - u32 irqstatus; - u32 handledirqs = 0; - u32 unhandled_errors; - struct omap_dispc_isr_data *isr_data; - struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; - - spin_lock(&dispc.irq_lock); - - irqstatus = dispc_read_reg(DISPC_IRQSTATUS); - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spin_lock(&dispc.irq_stats_lock); - dispc.irq_stats.irq_count++; - dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs); - spin_unlock(&dispc.irq_stats_lock); -#endif - -#ifdef DEBUG - if (dss_debug) - print_irq_status(irqstatus); -#endif - /* Ack the interrupt. Do it here before clocks are possibly turned - * off */ - dispc_write_reg(DISPC_IRQSTATUS, irqstatus); - /* flush posted write */ - dispc_read_reg(DISPC_IRQSTATUS); - - /* make a copy and unlock, so that isrs can unregister - * themselves */ - memcpy(registered_isr, dispc.registered_isr, - sizeof(registered_isr)); - - spin_unlock(&dispc.irq_lock); - - for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { - isr_data = ®istered_isr[i]; - - if (!isr_data->isr) - continue; - - if (isr_data->mask & irqstatus) { - isr_data->isr(isr_data->arg, irqstatus); - handledirqs |= isr_data->mask; - } - } - - spin_lock(&dispc.irq_lock); - - unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask; - - if (unhandled_errors) { - dispc.error_irqs |= unhandled_errors; - - dispc.irq_error_mask &= ~unhandled_errors; - _omap_dispc_set_irqs(); - - schedule_work(&dispc.error_work); - } - - spin_unlock(&dispc.irq_lock); -} - -static void dispc_error_worker(struct work_struct *work) -{ - int i; - u32 errors; - unsigned long flags; - - spin_lock_irqsave(&dispc.irq_lock, flags); - errors = dispc.error_irqs; - dispc.error_irqs = 0; - spin_unlock_irqrestore(&dispc.irq_lock, flags); - - if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) { - DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n"); - for (i = 0; i < omap_dss_get_num_overlays(); ++i) { - struct omap_overlay *ovl; - ovl = omap_dss_get_overlay(i); - - if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) - continue; - - if (ovl->id == 0) { - dispc_enable_plane(ovl->id, 0); - dispc_go(ovl->manager->id); - mdelay(50); - break; - } - } - } - - if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) { - DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n"); - for (i = 0; i < omap_dss_get_num_overlays(); ++i) { - struct omap_overlay *ovl; - ovl = omap_dss_get_overlay(i); - - if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) - continue; - - if (ovl->id == 1) { - dispc_enable_plane(ovl->id, 0); - dispc_go(ovl->manager->id); - mdelay(50); - break; - } - } - } - - if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) { - DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n"); - for (i = 0; i < omap_dss_get_num_overlays(); ++i) { - struct omap_overlay *ovl; - ovl = omap_dss_get_overlay(i); - - if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) - continue; - - if (ovl->id == 2) { - dispc_enable_plane(ovl->id, 0); - dispc_go(ovl->manager->id); - mdelay(50); - break; - } - } - } - - if (errors & DISPC_IRQ_SYNC_LOST) { - struct omap_overlay_manager *manager = NULL; - bool enable = false; - - DSSERR("SYNC_LOST, disabling LCD\n"); - - for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { - struct omap_overlay_manager *mgr; - mgr = omap_dss_get_overlay_manager(i); - - if (mgr->id == OMAP_DSS_CHANNEL_LCD) { - manager = mgr; - enable = mgr->device->state == - OMAP_DSS_DISPLAY_ACTIVE; - mgr->device->driver->disable(mgr->device); - break; - } - } - - if (manager) { - struct omap_dss_device *dssdev = manager->device; - for (i = 0; i < omap_dss_get_num_overlays(); ++i) { - struct omap_overlay *ovl; - ovl = omap_dss_get_overlay(i); - - if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) - continue; - - if (ovl->id != 0 && ovl->manager == manager) - dispc_enable_plane(ovl->id, 0); - } - - dispc_go(manager->id); - mdelay(50); - if (enable) - dssdev->driver->enable(dssdev); - } - } - - if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) { - struct omap_overlay_manager *manager = NULL; - bool enable = false; - - DSSERR("SYNC_LOST_DIGIT, disabling TV\n"); - - for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { - struct omap_overlay_manager *mgr; - mgr = omap_dss_get_overlay_manager(i); - - if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) { - manager = mgr; - enable = mgr->device->state == - OMAP_DSS_DISPLAY_ACTIVE; - mgr->device->driver->disable(mgr->device); - break; - } - } - - if (manager) { - struct omap_dss_device *dssdev = manager->device; - for (i = 0; i < omap_dss_get_num_overlays(); ++i) { - struct omap_overlay *ovl; - ovl = omap_dss_get_overlay(i); - - if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) - continue; - - if (ovl->id != 0 && ovl->manager == manager) - dispc_enable_plane(ovl->id, 0); - } - - dispc_go(manager->id); - mdelay(50); - if (enable) - dssdev->driver->enable(dssdev); - } - } - - if (errors & DISPC_IRQ_SYNC_LOST2) { - struct omap_overlay_manager *manager = NULL; - bool enable = false; - - DSSERR("SYNC_LOST for LCD2, disabling LCD2\n"); - - for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { - struct omap_overlay_manager *mgr; - mgr = omap_dss_get_overlay_manager(i); - - if (mgr->id == OMAP_DSS_CHANNEL_LCD2) { - manager = mgr; - enable = mgr->device->state == - OMAP_DSS_DISPLAY_ACTIVE; - mgr->device->driver->disable(mgr->device); - break; - } - } - - if (manager) { - struct omap_dss_device *dssdev = manager->device; - for (i = 0; i < omap_dss_get_num_overlays(); ++i) { - struct omap_overlay *ovl; - ovl = omap_dss_get_overlay(i); - - if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) - continue; - - if (ovl->id != 0 && ovl->manager == manager) - dispc_enable_plane(ovl->id, 0); - } - - dispc_go(manager->id); - mdelay(50); - if (enable) - dssdev->driver->enable(dssdev); - } - } - - if (errors & DISPC_IRQ_OCP_ERR) { - DSSERR("OCP_ERR\n"); - for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { - struct omap_overlay_manager *mgr; - mgr = omap_dss_get_overlay_manager(i); - - if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC) - mgr->device->driver->disable(mgr->device); - } - } - - spin_lock_irqsave(&dispc.irq_lock, flags); - dispc.irq_error_mask |= errors; - _omap_dispc_set_irqs(); - spin_unlock_irqrestore(&dispc.irq_lock, flags); -} - -int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout) -{ - void dispc_irq_wait_handler(void *data, u32 mask) - { - complete((struct completion *)data); - } - - int r; - DECLARE_COMPLETION_ONSTACK(completion); - - r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, - irqmask); - - if (r) - return r; - - timeout = wait_for_completion_timeout(&completion, timeout); - - omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); - - if (timeout == 0) - return -ETIMEDOUT; - - if (timeout == -ERESTARTSYS) - return -ERESTARTSYS; - - return 0; -} - -int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, - unsigned long timeout) -{ - void dispc_irq_wait_handler(void *data, u32 mask) - { - complete((struct completion *)data); - } - - int r; - DECLARE_COMPLETION_ONSTACK(completion); - - r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, - irqmask); - - if (r) - return r; - - timeout = wait_for_completion_interruptible_timeout(&completion, - timeout); - - omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); - - if (timeout == 0) - return -ETIMEDOUT; - - if (timeout == -ERESTARTSYS) - return -ERESTARTSYS; - - return 0; -} - -#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC -void dispc_fake_vsync_irq(void) -{ - u32 irqstatus = DISPC_IRQ_VSYNC; - int i; - - WARN_ON(!in_interrupt()); - - for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { - struct omap_dispc_isr_data *isr_data; - isr_data = &dispc.registered_isr[i]; - - if (!isr_data->isr) - continue; - - if (isr_data->mask & irqstatus) - isr_data->isr(isr_data->arg, irqstatus); - } -} -#endif - -static void _omap_dispc_initialize_irq(void) -{ - unsigned long flags; - - spin_lock_irqsave(&dispc.irq_lock, flags); - - memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr)); - - dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR; - if (dss_has_feature(FEAT_MGR_LCD2)) - dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2; - - /* there's SYNC_LOST_DIGIT waiting after enabling the DSS, - * so clear it */ - dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS)); - - _omap_dispc_set_irqs(); - - spin_unlock_irqrestore(&dispc.irq_lock, flags); -} - -void dispc_enable_sidle(void) -{ - REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ -} - -void dispc_disable_sidle(void) -{ - REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ -} - -static void _omap_dispc_initial_config(void) -{ - u32 l; - - l = dispc_read_reg(DISPC_SYSCONFIG); - l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */ - l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */ - l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */ - l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */ - dispc_write_reg(DISPC_SYSCONFIG, l); - - /* FUNCGATED */ - if (dss_has_feature(FEAT_FUNCGATED)) - REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); - - /* L3 firewall setting: enable access to OCM RAM */ - /* XXX this should be somewhere in plat-omap */ - if (cpu_is_omap24xx()) - __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0)); - - _dispc_setup_color_conv_coef(); - - dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); - - dispc_read_plane_fifo_sizes(); -} - -int dispc_init(void) -{ - u32 rev; - - spin_lock_init(&dispc.irq_lock); - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spin_lock_init(&dispc.irq_stats_lock); - dispc.irq_stats.last_reset = jiffies; -#endif - - INIT_WORK(&dispc.error_work, dispc_error_worker); - - dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS); - if (!dispc.base) { - DSSERR("can't ioremap DISPC\n"); - return -ENOMEM; - } - - enable_clocks(1); - - _omap_dispc_initial_config(); - - _omap_dispc_initialize_irq(); - - dispc_save_context(); - - rev = dispc_read_reg(DISPC_REVISION); - printk(KERN_INFO "OMAP DISPC rev %d.%d\n", - FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); - - enable_clocks(0); - - return 0; -} - -void dispc_exit(void) -{ - iounmap(dispc.base); -} - -int dispc_enable_plane(enum omap_plane plane, bool enable) -{ - DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); - - enable_clocks(1); - _dispc_enable_plane(plane, enable); - enable_clocks(0); - - return 0; -} - -int dispc_setup_plane(enum omap_plane plane, - u32 paddr, u16 screen_width, - u16 pos_x, u16 pos_y, - u16 width, u16 height, - u16 out_width, u16 out_height, - enum omap_color_mode color_mode, - bool ilace, - enum omap_dss_rotation_type rotation_type, - u8 rotation, bool mirror, u8 global_alpha, - u8 pre_mult_alpha, enum omap_channel channel) -{ - int r = 0; - - DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> " - "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n", - plane, paddr, screen_width, pos_x, pos_y, - width, height, - out_width, out_height, - ilace, color_mode, - rotation, mirror, channel); - - enable_clocks(1); - - r = _dispc_setup_plane(plane, - paddr, screen_width, - pos_x, pos_y, - width, height, - out_width, out_height, - color_mode, ilace, - rotation_type, - rotation, mirror, - global_alpha, - pre_mult_alpha, channel); - - enable_clocks(0); - - return r; -} diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c deleted file mode 100644 index 22dd7a474f7..00000000000 --- a/drivers/video/omap2/dss/display.c +++ /dev/null @@ -1,635 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/display.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "DISPLAY" - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/jiffies.h> -#include <linux/list.h> -#include <linux/platform_device.h> - -#include <plat/display.h> -#include "dss.h" - -static LIST_HEAD(display_list); - -static ssize_t display_enabled_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - bool enabled = dssdev->state != OMAP_DSS_DISPLAY_DISABLED; - - return snprintf(buf, PAGE_SIZE, "%d\n", enabled); -} - -static ssize_t display_enabled_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - bool enabled, r; - - enabled = simple_strtoul(buf, NULL, 10); - - if (enabled != (dssdev->state != OMAP_DSS_DISPLAY_DISABLED)) { - if (enabled) { - r = dssdev->driver->enable(dssdev); - if (r) - return r; - } else { - dssdev->driver->disable(dssdev); - } - } - - return size; -} - -static ssize_t display_upd_mode_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - enum omap_dss_update_mode mode = OMAP_DSS_UPDATE_AUTO; - if (dssdev->driver->get_update_mode) - mode = dssdev->driver->get_update_mode(dssdev); - return snprintf(buf, PAGE_SIZE, "%d\n", mode); -} - -static ssize_t display_upd_mode_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - int val, r; - enum omap_dss_update_mode mode; - - if (!dssdev->driver->set_update_mode) - return -EINVAL; - - val = simple_strtoul(buf, NULL, 10); - - switch (val) { - case OMAP_DSS_UPDATE_DISABLED: - case OMAP_DSS_UPDATE_AUTO: - case OMAP_DSS_UPDATE_MANUAL: - mode = (enum omap_dss_update_mode)val; - break; - default: - return -EINVAL; - } - - r = dssdev->driver->set_update_mode(dssdev, mode); - if (r) - return r; - - return size; -} - -static ssize_t display_tear_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - return snprintf(buf, PAGE_SIZE, "%d\n", - dssdev->driver->get_te ? - dssdev->driver->get_te(dssdev) : 0); -} - -static ssize_t display_tear_store(struct device *dev, - struct device_attribute *attr, const char *buf, size_t size) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - unsigned long te; - int r; - - if (!dssdev->driver->enable_te || !dssdev->driver->get_te) - return -ENOENT; - - te = simple_strtoul(buf, NULL, 0); - - r = dssdev->driver->enable_te(dssdev, te); - if (r) - return r; - - return size; -} - -static ssize_t display_timings_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - struct omap_video_timings t; - - if (!dssdev->driver->get_timings) - return -ENOENT; - - dssdev->driver->get_timings(dssdev, &t); - - return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n", - t.pixel_clock, - t.x_res, t.hfp, t.hbp, t.hsw, - t.y_res, t.vfp, t.vbp, t.vsw); -} - -static ssize_t display_timings_store(struct device *dev, - struct device_attribute *attr, const char *buf, size_t size) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - struct omap_video_timings t; - int r, found; - - if (!dssdev->driver->set_timings || !dssdev->driver->check_timings) - return -ENOENT; - - found = 0; -#ifdef CONFIG_OMAP2_DSS_VENC - if (strncmp("pal", buf, 3) == 0) { - t = omap_dss_pal_timings; - found = 1; - } else if (strncmp("ntsc", buf, 4) == 0) { - t = omap_dss_ntsc_timings; - found = 1; - } -#endif - if (!found && sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu", - &t.pixel_clock, - &t.x_res, &t.hfp, &t.hbp, &t.hsw, - &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9) - return -EINVAL; - - r = dssdev->driver->check_timings(dssdev, &t); - if (r) - return r; - - dssdev->driver->set_timings(dssdev, &t); - - return size; -} - -static ssize_t display_rotate_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - int rotate; - if (!dssdev->driver->get_rotate) - return -ENOENT; - rotate = dssdev->driver->get_rotate(dssdev); - return snprintf(buf, PAGE_SIZE, "%u\n", rotate); -} - -static ssize_t display_rotate_store(struct device *dev, - struct device_attribute *attr, const char *buf, size_t size) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - unsigned long rot; - int r; - - if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate) - return -ENOENT; - - rot = simple_strtoul(buf, NULL, 0); - - r = dssdev->driver->set_rotate(dssdev, rot); - if (r) - return r; - - return size; -} - -static ssize_t display_mirror_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - int mirror; - if (!dssdev->driver->get_mirror) - return -ENOENT; - mirror = dssdev->driver->get_mirror(dssdev); - return snprintf(buf, PAGE_SIZE, "%u\n", mirror); -} - -static ssize_t display_mirror_store(struct device *dev, - struct device_attribute *attr, const char *buf, size_t size) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - unsigned long mirror; - int r; - - if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror) - return -ENOENT; - - mirror = simple_strtoul(buf, NULL, 0); - - r = dssdev->driver->set_mirror(dssdev, mirror); - if (r) - return r; - - return size; -} - -static ssize_t display_wss_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - unsigned int wss; - - if (!dssdev->driver->get_wss) - return -ENOENT; - - wss = dssdev->driver->get_wss(dssdev); - - return snprintf(buf, PAGE_SIZE, "0x%05x\n", wss); -} - -static ssize_t display_wss_store(struct device *dev, - struct device_attribute *attr, const char *buf, size_t size) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - unsigned long wss; - int r; - - if (!dssdev->driver->get_wss || !dssdev->driver->set_wss) - return -ENOENT; - - if (strict_strtoul(buf, 0, &wss)) - return -EINVAL; - - if (wss > 0xfffff) - return -EINVAL; - - r = dssdev->driver->set_wss(dssdev, wss); - if (r) - return r; - - return size; -} - -static DEVICE_ATTR(enabled, S_IRUGO|S_IWUSR, - display_enabled_show, display_enabled_store); -static DEVICE_ATTR(update_mode, S_IRUGO|S_IWUSR, - display_upd_mode_show, display_upd_mode_store); -static DEVICE_ATTR(tear_elim, S_IRUGO|S_IWUSR, - display_tear_show, display_tear_store); -static DEVICE_ATTR(timings, S_IRUGO|S_IWUSR, - display_timings_show, display_timings_store); -static DEVICE_ATTR(rotate, S_IRUGO|S_IWUSR, - display_rotate_show, display_rotate_store); -static DEVICE_ATTR(mirror, S_IRUGO|S_IWUSR, - display_mirror_show, display_mirror_store); -static DEVICE_ATTR(wss, S_IRUGO|S_IWUSR, - display_wss_show, display_wss_store); - -static struct device_attribute *display_sysfs_attrs[] = { - &dev_attr_enabled, - &dev_attr_update_mode, - &dev_attr_tear_elim, - &dev_attr_timings, - &dev_attr_rotate, - &dev_attr_mirror, - &dev_attr_wss, - NULL -}; - -void omapdss_default_get_resolution(struct omap_dss_device *dssdev, - u16 *xres, u16 *yres) -{ - *xres = dssdev->panel.timings.x_res; - *yres = dssdev->panel.timings.y_res; -} -EXPORT_SYMBOL(omapdss_default_get_resolution); - -void default_get_overlay_fifo_thresholds(enum omap_plane plane, - u32 fifo_size, enum omap_burst_size *burst_size, - u32 *fifo_low, u32 *fifo_high) -{ - unsigned burst_size_bytes; - - *burst_size = OMAP_DSS_BURST_16x32; - burst_size_bytes = 16 * 32 / 8; - - *fifo_high = fifo_size - 1; - *fifo_low = fifo_size - burst_size_bytes; -} - -int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev) -{ - switch (dssdev->type) { - case OMAP_DISPLAY_TYPE_DPI: - if (dssdev->phy.dpi.data_lines == 24) - return 24; - else - return 16; - - case OMAP_DISPLAY_TYPE_DBI: - case OMAP_DISPLAY_TYPE_DSI: - if (dssdev->ctrl.pixel_size == 24) - return 24; - else - return 16; - case OMAP_DISPLAY_TYPE_VENC: - case OMAP_DISPLAY_TYPE_SDI: - return 24; - default: - BUG(); - } -} -EXPORT_SYMBOL(omapdss_default_get_recommended_bpp); - -/* Checks if replication logic should be used. Only use for active matrix, - * when overlay is in RGB12U or RGB16 mode, and LCD interface is - * 18bpp or 24bpp */ -bool dss_use_replication(struct omap_dss_device *dssdev, - enum omap_color_mode mode) -{ - int bpp; - - if (mode != OMAP_DSS_COLOR_RGB12U && mode != OMAP_DSS_COLOR_RGB16) - return false; - - if (dssdev->type == OMAP_DISPLAY_TYPE_DPI && - (dssdev->panel.config & OMAP_DSS_LCD_TFT) == 0) - return false; - - switch (dssdev->type) { - case OMAP_DISPLAY_TYPE_DPI: - bpp = dssdev->phy.dpi.data_lines; - break; - case OMAP_DISPLAY_TYPE_VENC: - case OMAP_DISPLAY_TYPE_SDI: - bpp = 24; - break; - case OMAP_DISPLAY_TYPE_DBI: - case OMAP_DISPLAY_TYPE_DSI: - bpp = dssdev->ctrl.pixel_size; - break; - default: - BUG(); - } - - return bpp > 16; -} - -void dss_init_device(struct platform_device *pdev, - struct omap_dss_device *dssdev) -{ - struct device_attribute *attr; - int i; - int r; - - switch (dssdev->type) { -#ifdef CONFIG_OMAP2_DSS_DPI - case OMAP_DISPLAY_TYPE_DPI: -#endif -#ifdef CONFIG_OMAP2_DSS_RFBI - case OMAP_DISPLAY_TYPE_DBI: -#endif -#ifdef CONFIG_OMAP2_DSS_SDI - case OMAP_DISPLAY_TYPE_SDI: -#endif -#ifdef CONFIG_OMAP2_DSS_DSI - case OMAP_DISPLAY_TYPE_DSI: -#endif -#ifdef CONFIG_OMAP2_DSS_VENC - case OMAP_DISPLAY_TYPE_VENC: -#endif - break; - default: - DSSERR("Support for display '%s' not compiled in.\n", - dssdev->name); - return; - } - - switch (dssdev->type) { -#ifdef CONFIG_OMAP2_DSS_DPI - case OMAP_DISPLAY_TYPE_DPI: - r = dpi_init_display(dssdev); - break; -#endif -#ifdef CONFIG_OMAP2_DSS_RFBI - case OMAP_DISPLAY_TYPE_DBI: - r = rfbi_init_display(dssdev); - break; -#endif -#ifdef CONFIG_OMAP2_DSS_VENC - case OMAP_DISPLAY_TYPE_VENC: - r = venc_init_display(dssdev); - break; -#endif -#ifdef CONFIG_OMAP2_DSS_SDI - case OMAP_DISPLAY_TYPE_SDI: - r = sdi_init_display(dssdev); - break; -#endif -#ifdef CONFIG_OMAP2_DSS_DSI - case OMAP_DISPLAY_TYPE_DSI: - r = dsi_init_display(dssdev); - break; -#endif - default: - BUG(); - } - - if (r) { - DSSERR("failed to init display %s\n", dssdev->name); - return; - } - - /* create device sysfs files */ - i = 0; - while ((attr = display_sysfs_attrs[i++]) != NULL) { - r = device_create_file(&dssdev->dev, attr); - if (r) - DSSERR("failed to create sysfs file\n"); - } - - /* create display? sysfs links */ - r = sysfs_create_link(&pdev->dev.kobj, &dssdev->dev.kobj, - dev_name(&dssdev->dev)); - if (r) - DSSERR("failed to create sysfs display link\n"); -} - -void dss_uninit_device(struct platform_device *pdev, - struct omap_dss_device *dssdev) -{ - struct device_attribute *attr; - int i = 0; - - sysfs_remove_link(&pdev->dev.kobj, dev_name(&dssdev->dev)); - - while ((attr = display_sysfs_attrs[i++]) != NULL) - device_remove_file(&dssdev->dev, attr); - - if (dssdev->manager) - dssdev->manager->unset_device(dssdev->manager); -} - -static int dss_suspend_device(struct device *dev, void *data) -{ - int r; - struct omap_dss_device *dssdev = to_dss_device(dev); - - if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) { - dssdev->activate_after_resume = false; - return 0; - } - - if (!dssdev->driver->suspend) { - DSSERR("display '%s' doesn't implement suspend\n", - dssdev->name); - return -ENOSYS; - } - - r = dssdev->driver->suspend(dssdev); - if (r) - return r; - - dssdev->activate_after_resume = true; - - return 0; -} - -int dss_suspend_all_devices(void) -{ - int r; - struct bus_type *bus = dss_get_bus(); - - r = bus_for_each_dev(bus, NULL, NULL, dss_suspend_device); - if (r) { - /* resume all displays that were suspended */ - dss_resume_all_devices(); - return r; - } - - return 0; -} - -static int dss_resume_device(struct device *dev, void *data) -{ - int r; - struct omap_dss_device *dssdev = to_dss_device(dev); - - if (dssdev->activate_after_resume && dssdev->driver->resume) { - r = dssdev->driver->resume(dssdev); - if (r) - return r; - } - - dssdev->activate_after_resume = false; - - return 0; -} - -int dss_resume_all_devices(void) -{ - struct bus_type *bus = dss_get_bus(); - - return bus_for_each_dev(bus, NULL, NULL, dss_resume_device); -} - -static int dss_disable_device(struct device *dev, void *data) -{ - struct omap_dss_device *dssdev = to_dss_device(dev); - - if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) - dssdev->driver->disable(dssdev); - - return 0; -} - -void dss_disable_all_devices(void) -{ - struct bus_type *bus = dss_get_bus(); - bus_for_each_dev(bus, NULL, NULL, dss_disable_device); -} - - -void omap_dss_get_device(struct omap_dss_device *dssdev) -{ - get_device(&dssdev->dev); -} -EXPORT_SYMBOL(omap_dss_get_device); - -void omap_dss_put_device(struct omap_dss_device *dssdev) -{ - put_device(&dssdev->dev); -} -EXPORT_SYMBOL(omap_dss_put_device); - -/* ref count of the found device is incremented. ref count - * of from-device is decremented. */ -struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from) -{ - struct device *dev; - struct device *dev_start = NULL; - struct omap_dss_device *dssdev = NULL; - - int match(struct device *dev, void *data) - { - return 1; - } - - if (from) - dev_start = &from->dev; - dev = bus_find_device(dss_get_bus(), dev_start, NULL, match); - if (dev) - dssdev = to_dss_device(dev); - if (from) - put_device(&from->dev); - - return dssdev; -} -EXPORT_SYMBOL(omap_dss_get_next_device); - -struct omap_dss_device *omap_dss_find_device(void *data, - int (*match)(struct omap_dss_device *dssdev, void *data)) -{ - struct omap_dss_device *dssdev = NULL; - - while ((dssdev = omap_dss_get_next_device(dssdev)) != NULL) { - if (match(dssdev, data)) - return dssdev; - } - - return NULL; -} -EXPORT_SYMBOL(omap_dss_find_device); - -int omap_dss_start_device(struct omap_dss_device *dssdev) -{ - if (!dssdev->driver) { - DSSDBG("no driver\n"); - return -ENODEV; - } - - if (!try_module_get(dssdev->dev.driver->owner)) { - return -ENODEV; - } - - return 0; -} -EXPORT_SYMBOL(omap_dss_start_device); - -void omap_dss_stop_device(struct omap_dss_device *dssdev) -{ - module_put(dssdev->dev.driver->owner); -} -EXPORT_SYMBOL(omap_dss_stop_device); - diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c deleted file mode 100644 index 75fb0a51543..00000000000 --- a/drivers/video/omap2/dss/dpi.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/dpi.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "DPI" - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/errno.h> -#include <linux/platform_device.h> -#include <linux/regulator/consumer.h> - -#include <plat/display.h> -#include <plat/cpu.h> - -#include "dss.h" - -static struct { - struct regulator *vdds_dsi_reg; -} dpi; - -#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft, - unsigned long pck_req, unsigned long *fck, int *lck_div, - int *pck_div) -{ - struct dsi_clock_info dsi_cinfo; - struct dispc_clock_info dispc_cinfo; - int r; - - r = dsi_pll_calc_clock_div_pck(is_tft, pck_req, &dsi_cinfo, - &dispc_cinfo); - if (r) - return r; - - r = dsi_pll_set_clock_div(&dsi_cinfo); - if (r) - return r; - - dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK); - - r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); - if (r) - return r; - - *fck = dsi_cinfo.dsi1_pll_fclk; - *lck_div = dispc_cinfo.lck_div; - *pck_div = dispc_cinfo.pck_div; - - return 0; -} -#else -static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft, - unsigned long pck_req, unsigned long *fck, int *lck_div, - int *pck_div) -{ - struct dss_clock_info dss_cinfo; - struct dispc_clock_info dispc_cinfo; - int r; - - r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo); - if (r) - return r; - - r = dss_set_clock_div(&dss_cinfo); - if (r) - return r; - - r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); - if (r) - return r; - - *fck = dss_cinfo.fck; - *lck_div = dispc_cinfo.lck_div; - *pck_div = dispc_cinfo.pck_div; - - return 0; -} -#endif - -static int dpi_set_mode(struct omap_dss_device *dssdev) -{ - struct omap_video_timings *t = &dssdev->panel.timings; - int lck_div, pck_div; - unsigned long fck; - unsigned long pck; - bool is_tft; - int r = 0; - - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - - dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, - dssdev->panel.acbi, dssdev->panel.acb); - - is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; - -#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL - r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck, - &lck_div, &pck_div); -#else - r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck, - &lck_div, &pck_div); -#endif - if (r) - goto err0; - - pck = fck / lck_div / pck_div / 1000; - - if (pck != t->pixel_clock) { - DSSWARN("Could not find exact pixel clock. " - "Requested %d kHz, got %lu kHz\n", - t->pixel_clock, pck); - - t->pixel_clock = pck; - } - - dispc_set_lcd_timings(dssdev->manager->id, t); - -err0: - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); - return r; -} - -static int dpi_basic_init(struct omap_dss_device *dssdev) -{ - bool is_tft; - - is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; - - dispc_set_parallel_interface_mode(dssdev->manager->id, - OMAP_DSS_PARALLELMODE_BYPASS); - dispc_set_lcd_display_type(dssdev->manager->id, is_tft ? - OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN); - dispc_set_tft_data_lines(dssdev->manager->id, - dssdev->phy.dpi.data_lines); - - return 0; -} - -int omapdss_dpi_display_enable(struct omap_dss_device *dssdev) -{ - int r; - - r = omap_dss_start_device(dssdev); - if (r) { - DSSERR("failed to start device\n"); - goto err0; - } - - if (cpu_is_omap34xx()) { - r = regulator_enable(dpi.vdds_dsi_reg); - if (r) - goto err1; - } - - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - - r = dpi_basic_init(dssdev); - if (r) - goto err2; - -#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL - dss_clk_enable(DSS_CLK_FCK2); - r = dsi_pll_init(dssdev, 0, 1); - if (r) - goto err3; -#endif - r = dpi_set_mode(dssdev); - if (r) - goto err4; - - mdelay(2); - - dssdev->manager->enable(dssdev->manager); - - return 0; - -err4: -#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL - dsi_pll_uninit(); -err3: - dss_clk_disable(DSS_CLK_FCK2); -#endif -err2: - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); - if (cpu_is_omap34xx()) - regulator_disable(dpi.vdds_dsi_reg); -err1: - omap_dss_stop_device(dssdev); -err0: - return r; -} -EXPORT_SYMBOL(omapdss_dpi_display_enable); - -void omapdss_dpi_display_disable(struct omap_dss_device *dssdev) -{ - dssdev->manager->disable(dssdev->manager); - -#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL - dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); - dsi_pll_uninit(); - dss_clk_disable(DSS_CLK_FCK2); -#endif - - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); - - if (cpu_is_omap34xx()) - regulator_disable(dpi.vdds_dsi_reg); - - omap_dss_stop_device(dssdev); -} -EXPORT_SYMBOL(omapdss_dpi_display_disable); - -void dpi_set_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings) -{ - DSSDBG("dpi_set_timings\n"); - dssdev->panel.timings = *timings; - if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { - dpi_set_mode(dssdev); - dispc_go(dssdev->manager->id); - } -} -EXPORT_SYMBOL(dpi_set_timings); - -int dpi_check_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings) -{ - bool is_tft; - int r; - int lck_div, pck_div; - unsigned long fck; - unsigned long pck; - - if (!dispc_lcd_timings_ok(timings)) - return -EINVAL; - - if (timings->pixel_clock == 0) - return -EINVAL; - - is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; - -#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL - { - struct dsi_clock_info dsi_cinfo; - struct dispc_clock_info dispc_cinfo; - r = dsi_pll_calc_clock_div_pck(is_tft, - timings->pixel_clock * 1000, - &dsi_cinfo, &dispc_cinfo); - - if (r) - return r; - - fck = dsi_cinfo.dsi1_pll_fclk; - lck_div = dispc_cinfo.lck_div; - pck_div = dispc_cinfo.pck_div; - } -#else - { - struct dss_clock_info dss_cinfo; - struct dispc_clock_info dispc_cinfo; - r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000, - &dss_cinfo, &dispc_cinfo); - - if (r) - return r; - - fck = dss_cinfo.fck; - lck_div = dispc_cinfo.lck_div; - pck_div = dispc_cinfo.pck_div; - } -#endif - - pck = fck / lck_div / pck_div / 1000; - - timings->pixel_clock = pck; - - return 0; -} -EXPORT_SYMBOL(dpi_check_timings); - -int dpi_init_display(struct omap_dss_device *dssdev) -{ - DSSDBG("init_display\n"); - - return 0; -} - -int dpi_init(struct platform_device *pdev) -{ - if (cpu_is_omap34xx()) { - dpi.vdds_dsi_reg = dss_get_vdds_dsi(); - if (IS_ERR(dpi.vdds_dsi_reg)) { - DSSERR("can't get VDDS_DSI regulator\n"); - return PTR_ERR(dpi.vdds_dsi_reg); - } - } - - return 0; -} - -void dpi_exit(void) -{ -} - diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c deleted file mode 100644 index ddf3a056082..00000000000 --- a/drivers/video/omap2/dss/dsi.c +++ /dev/null @@ -1,3309 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/dsi.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "DSI" - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/device.h> -#include <linux/err.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/mutex.h> -#include <linux/semaphore.h> -#include <linux/seq_file.h> -#include <linux/platform_device.h> -#include <linux/regulator/consumer.h> -#include <linux/wait.h> -#include <linux/workqueue.h> - -#include <plat/display.h> -#include <plat/clock.h> - -#include "dss.h" - -/*#define VERBOSE_IRQ*/ -#define DSI_CATCH_MISSING_TE - -#define DSI_BASE 0x4804FC00 - -struct dsi_reg { u16 idx; }; - -#define DSI_REG(idx) ((const struct dsi_reg) { idx }) - -#define DSI_SZ_REGS SZ_1K -/* DSI Protocol Engine */ - -#define DSI_REVISION DSI_REG(0x0000) -#define DSI_SYSCONFIG DSI_REG(0x0010) -#define DSI_SYSSTATUS DSI_REG(0x0014) -#define DSI_IRQSTATUS DSI_REG(0x0018) -#define DSI_IRQENABLE DSI_REG(0x001C) -#define DSI_CTRL DSI_REG(0x0040) -#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) -#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) -#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) -#define DSI_CLK_CTRL DSI_REG(0x0054) -#define DSI_TIMING1 DSI_REG(0x0058) -#define DSI_TIMING2 DSI_REG(0x005C) -#define DSI_VM_TIMING1 DSI_REG(0x0060) -#define DSI_VM_TIMING2 DSI_REG(0x0064) -#define DSI_VM_TIMING3 DSI_REG(0x0068) -#define DSI_CLK_TIMING DSI_REG(0x006C) -#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) -#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) -#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) -#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) -#define DSI_VM_TIMING4 DSI_REG(0x0080) -#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) -#define DSI_VM_TIMING5 DSI_REG(0x0088) -#define DSI_VM_TIMING6 DSI_REG(0x008C) -#define DSI_VM_TIMING7 DSI_REG(0x0090) -#define DSI_STOPCLK_TIMING DSI_REG(0x0094) -#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) -#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) -#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) -#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) -#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) -#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) -#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) - -/* DSIPHY_SCP */ - -#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) -#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) -#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) -#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) - -/* DSI_PLL_CTRL_SCP */ - -#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) -#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) -#define DSI_PLL_GO DSI_REG(0x300 + 0x0008) -#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) -#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) - -#define REG_GET(idx, start, end) \ - FLD_GET(dsi_read_reg(idx), start, end) - -#define REG_FLD_MOD(idx, val, start, end) \ - dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end)) - -/* Global interrupts */ -#define DSI_IRQ_VC0 (1 << 0) -#define DSI_IRQ_VC1 (1 << 1) -#define DSI_IRQ_VC2 (1 << 2) -#define DSI_IRQ_VC3 (1 << 3) -#define DSI_IRQ_WAKEUP (1 << 4) -#define DSI_IRQ_RESYNC (1 << 5) -#define DSI_IRQ_PLL_LOCK (1 << 7) -#define DSI_IRQ_PLL_UNLOCK (1 << 8) -#define DSI_IRQ_PLL_RECALL (1 << 9) -#define DSI_IRQ_COMPLEXIO_ERR (1 << 10) -#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) -#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) -#define DSI_IRQ_TE_TRIGGER (1 << 16) -#define DSI_IRQ_ACK_TRIGGER (1 << 17) -#define DSI_IRQ_SYNC_LOST (1 << 18) -#define DSI_IRQ_LDO_POWER_GOOD (1 << 19) -#define DSI_IRQ_TA_TIMEOUT (1 << 20) -#define DSI_IRQ_ERROR_MASK \ - (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ - DSI_IRQ_TA_TIMEOUT) -#define DSI_IRQ_CHANNEL_MASK 0xf - -/* Virtual channel interrupts */ -#define DSI_VC_IRQ_CS (1 << 0) -#define DSI_VC_IRQ_ECC_CORR (1 << 1) -#define DSI_VC_IRQ_PACKET_SENT (1 << 2) -#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) -#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) -#define DSI_VC_IRQ_BTA (1 << 5) -#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) -#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) -#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) -#define DSI_VC_IRQ_ERROR_MASK \ - (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ - DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ - DSI_VC_IRQ_FIFO_TX_UDF) - -/* ComplexIO interrupts */ -#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) -#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) -#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) -#define DSI_CIO_IRQ_ERRESC1 (1 << 5) -#define DSI_CIO_IRQ_ERRESC2 (1 << 6) -#define DSI_CIO_IRQ_ERRESC3 (1 << 7) -#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) -#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) -#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) -#define DSI_CIO_IRQ_STATEULPS1 (1 << 15) -#define DSI_CIO_IRQ_STATEULPS2 (1 << 16) -#define DSI_CIO_IRQ_STATEULPS3 (1 << 17) -#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) -#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) -#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) -#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) -#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) -#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) -#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) -#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) -#define DSI_CIO_IRQ_ERROR_MASK \ - (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ - DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ - DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \ - DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \ - DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ - DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ - DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3) - -#define DSI_DT_DCS_SHORT_WRITE_0 0x05 -#define DSI_DT_DCS_SHORT_WRITE_1 0x15 -#define DSI_DT_DCS_READ 0x06 -#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37 -#define DSI_DT_NULL_PACKET 0x09 -#define DSI_DT_DCS_LONG_WRITE 0x39 - -#define DSI_DT_RX_ACK_WITH_ERR 0x02 -#define DSI_DT_RX_DCS_LONG_READ 0x1c -#define DSI_DT_RX_SHORT_READ_1 0x21 -#define DSI_DT_RX_SHORT_READ_2 0x22 - -#define FINT_MAX 2100000 -#define FINT_MIN 750000 -#define REGN_MAX (1 << 7) -#define REGM_MAX ((1 << 11) - 1) -#define REGM3_MAX (1 << 4) -#define REGM4_MAX (1 << 4) -#define LP_DIV_MAX ((1 << 13) - 1) - -enum fifo_size { - DSI_FIFO_SIZE_0 = 0, - DSI_FIFO_SIZE_32 = 1, - DSI_FIFO_SIZE_64 = 2, - DSI_FIFO_SIZE_96 = 3, - DSI_FIFO_SIZE_128 = 4, -}; - -enum dsi_vc_mode { - DSI_VC_MODE_L4 = 0, - DSI_VC_MODE_VP, -}; - -struct dsi_update_region { - u16 x, y, w, h; - struct omap_dss_device *device; -}; - -struct dsi_irq_stats { - unsigned long last_reset; - unsigned irq_count; - unsigned dsi_irqs[32]; - unsigned vc_irqs[4][32]; - unsigned cio_irqs[32]; -}; - -static struct -{ - void __iomem *base; - - struct dsi_clock_info current_cinfo; - - struct regulator *vdds_dsi_reg; - - struct { - enum dsi_vc_mode mode; - struct omap_dss_device *dssdev; - enum fifo_size fifo_size; - } vc[4]; - - struct mutex lock; - struct semaphore bus_lock; - - unsigned pll_locked; - - struct completion bta_completion; - void (*bta_callback)(void); - - int update_channel; - struct dsi_update_region update_region; - - bool te_enabled; - - struct workqueue_struct *workqueue; - - void (*framedone_callback)(int, void *); - void *framedone_data; - - struct delayed_work framedone_timeout_work; - -#ifdef DSI_CATCH_MISSING_TE - struct timer_list te_timer; -#endif - - unsigned long cache_req_pck; - unsigned long cache_clk_freq; - struct dsi_clock_info cache_cinfo; - - u32 errors; - spinlock_t errors_lock; -#ifdef DEBUG - ktime_t perf_setup_time; - ktime_t perf_start_time; -#endif - int debug_read; - int debug_write; - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spinlock_t irq_stats_lock; - struct dsi_irq_stats irq_stats; -#endif -} dsi; - -#ifdef DEBUG -static unsigned int dsi_perf; -module_param_named(dsi_perf, dsi_perf, bool, 0644); -#endif - -static inline void dsi_write_reg(const struct dsi_reg idx, u32 val) -{ - __raw_writel(val, dsi.base + idx.idx); -} - -static inline u32 dsi_read_reg(const struct dsi_reg idx) -{ - return __raw_readl(dsi.base + idx.idx); -} - - -void dsi_save_context(void) -{ -} - -void dsi_restore_context(void) -{ -} - -void dsi_bus_lock(void) -{ - down(&dsi.bus_lock); -} -EXPORT_SYMBOL(dsi_bus_lock); - -void dsi_bus_unlock(void) -{ - up(&dsi.bus_lock); -} -EXPORT_SYMBOL(dsi_bus_unlock); - -static bool dsi_bus_is_locked(void) -{ - return dsi.bus_lock.count == 0; -} - -static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum, - int value) -{ - int t = 100000; - - while (REG_GET(idx, bitnum, bitnum) != value) { - if (--t == 0) - return !value; - } - - return value; -} - -#ifdef DEBUG -static void dsi_perf_mark_setup(void) -{ - dsi.perf_setup_time = ktime_get(); -} - -static void dsi_perf_mark_start(void) -{ - dsi.perf_start_time = ktime_get(); -} - -static void dsi_perf_show(const char *name) -{ - ktime_t t, setup_time, trans_time; - u32 total_bytes; - u32 setup_us, trans_us, total_us; - - if (!dsi_perf) - return; - - t = ktime_get(); - - setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time); - setup_us = (u32)ktime_to_us(setup_time); - if (setup_us == 0) - setup_us = 1; - - trans_time = ktime_sub(t, dsi.perf_start_time); - trans_us = (u32)ktime_to_us(trans_time); - if (trans_us == 0) - trans_us = 1; - - total_us = setup_us + trans_us; - - total_bytes = dsi.update_region.w * - dsi.update_region.h * - dsi.update_region.device->ctrl.pixel_size / 8; - - printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " - "%u bytes, %u kbytes/sec\n", - name, - setup_us, - trans_us, - total_us, - 1000*1000 / total_us, - total_bytes, - total_bytes * 1000 / total_us); -} -#else -#define dsi_perf_mark_setup() -#define dsi_perf_mark_start() -#define dsi_perf_show(x) -#endif - -static void print_irq_status(u32 status) -{ -#ifndef VERBOSE_IRQ - if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) - return; -#endif - printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); - -#define PIS(x) \ - if (status & DSI_IRQ_##x) \ - printk(#x " "); -#ifdef VERBOSE_IRQ - PIS(VC0); - PIS(VC1); - PIS(VC2); - PIS(VC3); -#endif - PIS(WAKEUP); - PIS(RESYNC); - PIS(PLL_LOCK); - PIS(PLL_UNLOCK); - PIS(PLL_RECALL); - PIS(COMPLEXIO_ERR); - PIS(HS_TX_TIMEOUT); - PIS(LP_RX_TIMEOUT); - PIS(TE_TRIGGER); - PIS(ACK_TRIGGER); - PIS(SYNC_LOST); - PIS(LDO_POWER_GOOD); - PIS(TA_TIMEOUT); -#undef PIS - - printk("\n"); -} - -static void print_irq_status_vc(int channel, u32 status) -{ -#ifndef VERBOSE_IRQ - if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) - return; -#endif - printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); - -#define PIS(x) \ - if (status & DSI_VC_IRQ_##x) \ - printk(#x " "); - PIS(CS); - PIS(ECC_CORR); -#ifdef VERBOSE_IRQ - PIS(PACKET_SENT); -#endif - PIS(FIFO_TX_OVF); - PIS(FIFO_RX_OVF); - PIS(BTA); - PIS(ECC_NO_CORR); - PIS(FIFO_TX_UDF); - PIS(PP_BUSY_CHANGE); -#undef PIS - printk("\n"); -} - -static void print_irq_status_cio(u32 status) -{ - printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); - -#define PIS(x) \ - if (status & DSI_CIO_IRQ_##x) \ - printk(#x " "); - PIS(ERRSYNCESC1); - PIS(ERRSYNCESC2); - PIS(ERRSYNCESC3); - PIS(ERRESC1); - PIS(ERRESC2); - PIS(ERRESC3); - PIS(ERRCONTROL1); - PIS(ERRCONTROL2); - PIS(ERRCONTROL3); - PIS(STATEULPS1); - PIS(STATEULPS2); - PIS(STATEULPS3); - PIS(ERRCONTENTIONLP0_1); - PIS(ERRCONTENTIONLP1_1); - PIS(ERRCONTENTIONLP0_2); - PIS(ERRCONTENTIONLP1_2); - PIS(ERRCONTENTIONLP0_3); - PIS(ERRCONTENTIONLP1_3); - PIS(ULPSACTIVENOT_ALL0); - PIS(ULPSACTIVENOT_ALL1); -#undef PIS - - printk("\n"); -} - -static int debug_irq; - -/* called from dss */ -void dsi_irq_handler(void) -{ - u32 irqstatus, vcstatus, ciostatus; - int i; - - irqstatus = dsi_read_reg(DSI_IRQSTATUS); - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spin_lock(&dsi.irq_stats_lock); - dsi.irq_stats.irq_count++; - dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs); -#endif - - if (irqstatus & DSI_IRQ_ERROR_MASK) { - DSSERR("DSI error, irqstatus %x\n", irqstatus); - print_irq_status(irqstatus); - spin_lock(&dsi.errors_lock); - dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK; - spin_unlock(&dsi.errors_lock); - } else if (debug_irq) { - print_irq_status(irqstatus); - } - -#ifdef DSI_CATCH_MISSING_TE - if (irqstatus & DSI_IRQ_TE_TRIGGER) - del_timer(&dsi.te_timer); -#endif - - for (i = 0; i < 4; ++i) { - if ((irqstatus & (1<<i)) == 0) - continue; - - vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i)); - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]); -#endif - - if (vcstatus & DSI_VC_IRQ_BTA) { - complete(&dsi.bta_completion); - - if (dsi.bta_callback) - dsi.bta_callback(); - } - - if (vcstatus & DSI_VC_IRQ_ERROR_MASK) { - DSSERR("DSI VC(%d) error, vc irqstatus %x\n", - i, vcstatus); - print_irq_status_vc(i, vcstatus); - } else if (debug_irq) { - print_irq_status_vc(i, vcstatus); - } - - dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus); - /* flush posted write */ - dsi_read_reg(DSI_VC_IRQSTATUS(i)); - } - - if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { - ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs); -#endif - - dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus); - /* flush posted write */ - dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); - - if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { - DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); - print_irq_status_cio(ciostatus); - } else if (debug_irq) { - print_irq_status_cio(ciostatus); - } - } - - dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); - /* flush posted write */ - dsi_read_reg(DSI_IRQSTATUS); - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spin_unlock(&dsi.irq_stats_lock); -#endif -} - - -static void _dsi_initialize_irq(void) -{ - u32 l; - int i; - - /* disable all interrupts */ - dsi_write_reg(DSI_IRQENABLE, 0); - for (i = 0; i < 4; ++i) - dsi_write_reg(DSI_VC_IRQENABLE(i), 0); - dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0); - - /* clear interrupt status */ - l = dsi_read_reg(DSI_IRQSTATUS); - dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK); - - for (i = 0; i < 4; ++i) { - l = dsi_read_reg(DSI_VC_IRQSTATUS(i)); - dsi_write_reg(DSI_VC_IRQSTATUS(i), l); - } - - l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); - dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l); - - /* enable error irqs */ - l = DSI_IRQ_ERROR_MASK; -#ifdef DSI_CATCH_MISSING_TE - l |= DSI_IRQ_TE_TRIGGER; -#endif - dsi_write_reg(DSI_IRQENABLE, l); - - l = DSI_VC_IRQ_ERROR_MASK; - for (i = 0; i < 4; ++i) - dsi_write_reg(DSI_VC_IRQENABLE(i), l); - - l = DSI_CIO_IRQ_ERROR_MASK; - dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l); -} - -static u32 dsi_get_errors(void) -{ - unsigned long flags; - u32 e; - spin_lock_irqsave(&dsi.errors_lock, flags); - e = dsi.errors; - dsi.errors = 0; - spin_unlock_irqrestore(&dsi.errors_lock, flags); - return e; -} - -static void dsi_vc_enable_bta_irq(int channel) -{ - u32 l; - - dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA); - - l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); - l |= DSI_VC_IRQ_BTA; - dsi_write_reg(DSI_VC_IRQENABLE(channel), l); -} - -static void dsi_vc_disable_bta_irq(int channel) -{ - u32 l; - - l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); - l &= ~DSI_VC_IRQ_BTA; - dsi_write_reg(DSI_VC_IRQENABLE(channel), l); -} - -/* DSI func clock. this could also be DSI2_PLL_FCLK */ -static inline void enable_clocks(bool enable) -{ - if (enable) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - else - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -} - -/* source clock for DSI PLL. this could also be PCLKFREE */ -static inline void dsi_enable_pll_clock(bool enable) -{ - if (enable) - dss_clk_enable(DSS_CLK_FCK2); - else - dss_clk_disable(DSS_CLK_FCK2); - - if (enable && dsi.pll_locked) { - if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) - DSSERR("cannot lock PLL when enabling clocks\n"); - } -} - -#ifdef DEBUG -static void _dsi_print_reset_status(void) -{ - u32 l; - - if (!dss_debug) - return; - - /* A dummy read using the SCP interface to any DSIPHY register is - * required after DSIPHY reset to complete the reset of the DSI complex - * I/O. */ - l = dsi_read_reg(DSI_DSIPHY_CFG5); - - printk(KERN_DEBUG "DSI resets: "); - - l = dsi_read_reg(DSI_PLL_STATUS); - printk("PLL (%d) ", FLD_GET(l, 0, 0)); - - l = dsi_read_reg(DSI_COMPLEXIO_CFG1); - printk("CIO (%d) ", FLD_GET(l, 29, 29)); - - l = dsi_read_reg(DSI_DSIPHY_CFG5); - printk("PHY (%x, %d, %d, %d)\n", - FLD_GET(l, 28, 26), - FLD_GET(l, 29, 29), - FLD_GET(l, 30, 30), - FLD_GET(l, 31, 31)); -} -#else -#define _dsi_print_reset_status() -#endif - -static inline int dsi_if_enable(bool enable) -{ - DSSDBG("dsi_if_enable(%d)\n", enable); - - enable = enable ? 1 : 0; - REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */ - - if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) { - DSSERR("Failed to set dsi_if_enable to %d\n", enable); - return -EIO; - } - - return 0; -} - -unsigned long dsi_get_dsi1_pll_rate(void) -{ - return dsi.current_cinfo.dsi1_pll_fclk; -} - -static unsigned long dsi_get_dsi2_pll_rate(void) -{ - return dsi.current_cinfo.dsi2_pll_fclk; -} - -static unsigned long dsi_get_txbyteclkhs(void) -{ - return dsi.current_cinfo.clkin4ddr / 16; -} - -static unsigned long dsi_fclk_rate(void) -{ - unsigned long r; - - if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) { - /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */ - r = dss_clk_get_rate(DSS_CLK_FCK1); - } else { - /* DSI FCLK source is DSI2_PLL_FCLK */ - r = dsi_get_dsi2_pll_rate(); - } - - return r; -} - -static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) -{ - unsigned long dsi_fclk; - unsigned lp_clk_div; - unsigned long lp_clk; - - lp_clk_div = dssdev->phy.dsi.div.lp_clk_div; - - if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX) - return -EINVAL; - - dsi_fclk = dsi_fclk_rate(); - - lp_clk = dsi_fclk / 2 / lp_clk_div; - - DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); - dsi.current_cinfo.lp_clk = lp_clk; - dsi.current_cinfo.lp_clk_div = lp_clk_div; - - REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */ - - REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, - 21, 21); /* LP_RX_SYNCHRO_ENABLE */ - - return 0; -} - - -enum dsi_pll_power_state { - DSI_PLL_POWER_OFF = 0x0, - DSI_PLL_POWER_ON_HSCLK = 0x1, - DSI_PLL_POWER_ON_ALL = 0x2, - DSI_PLL_POWER_ON_DIV = 0x3, -}; - -static int dsi_pll_power(enum dsi_pll_power_state state) -{ - int t = 0; - - REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */ - - /* PLL_PWR_STATUS */ - while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) { - if (++t > 1000) { - DSSERR("Failed to set DSI PLL power mode to %d\n", - state); - return -ENODEV; - } - udelay(1); - } - - return 0; -} - -/* calculate clock rates using dividers in cinfo */ -static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, - struct dsi_clock_info *cinfo) -{ - if (cinfo->regn == 0 || cinfo->regn > REGN_MAX) - return -EINVAL; - - if (cinfo->regm == 0 || cinfo->regm > REGM_MAX) - return -EINVAL; - - if (cinfo->regm3 > REGM3_MAX) - return -EINVAL; - - if (cinfo->regm4 > REGM4_MAX) - return -EINVAL; - - if (cinfo->use_dss2_fck) { - cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2); - /* XXX it is unclear if highfreq should be used - * with DSS2_FCK source also */ - cinfo->highfreq = 0; - } else { - cinfo->clkin = dispc_pclk_rate(dssdev->manager->id); - - if (cinfo->clkin < 32000000) - cinfo->highfreq = 0; - else - cinfo->highfreq = 1; - } - - cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); - - if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN) - return -EINVAL; - - cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; - - if (cinfo->clkin4ddr > 1800 * 1000 * 1000) - return -EINVAL; - - if (cinfo->regm3 > 0) - cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3; - else - cinfo->dsi1_pll_fclk = 0; - - if (cinfo->regm4 > 0) - cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4; - else - cinfo->dsi2_pll_fclk = 0; - - return 0; -} - -int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, - struct dsi_clock_info *dsi_cinfo, - struct dispc_clock_info *dispc_cinfo) -{ - struct dsi_clock_info cur, best; - struct dispc_clock_info best_dispc; - int min_fck_per_pck; - int match = 0; - unsigned long dss_clk_fck2; - - dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2); - - if (req_pck == dsi.cache_req_pck && - dsi.cache_cinfo.clkin == dss_clk_fck2) { - DSSDBG("DSI clock info found from cache\n"); - *dsi_cinfo = dsi.cache_cinfo; - dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk, - dispc_cinfo); - return 0; - } - - min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; - - if (min_fck_per_pck && - req_pck * min_fck_per_pck > DISPC_MAX_FCK) { - DSSERR("Requested pixel clock not possible with the current " - "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " - "the constraint off.\n"); - min_fck_per_pck = 0; - } - - DSSDBG("dsi_pll_calc\n"); - -retry: - memset(&best, 0, sizeof(best)); - memset(&best_dispc, 0, sizeof(best_dispc)); - - memset(&cur, 0, sizeof(cur)); - cur.clkin = dss_clk_fck2; - cur.use_dss2_fck = 1; - cur.highfreq = 0; - - /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ - /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ - /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ - for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) { - if (cur.highfreq == 0) - cur.fint = cur.clkin / cur.regn; - else - cur.fint = cur.clkin / (2 * cur.regn); - - if (cur.fint > FINT_MAX || cur.fint < FINT_MIN) - continue; - - /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ - for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) { - unsigned long a, b; - - a = 2 * cur.regm * (cur.clkin/1000); - b = cur.regn * (cur.highfreq + 1); - cur.clkin4ddr = a / b * 1000; - - if (cur.clkin4ddr > 1800 * 1000 * 1000) - break; - - /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */ - for (cur.regm3 = 1; cur.regm3 < REGM3_MAX; - ++cur.regm3) { - struct dispc_clock_info cur_dispc; - cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3; - - /* this will narrow down the search a bit, - * but still give pixclocks below what was - * requested */ - if (cur.dsi1_pll_fclk < req_pck) - break; - - if (cur.dsi1_pll_fclk > DISPC_MAX_FCK) - continue; - - if (min_fck_per_pck && - cur.dsi1_pll_fclk < - req_pck * min_fck_per_pck) - continue; - - match = 1; - - dispc_find_clk_divs(is_tft, req_pck, - cur.dsi1_pll_fclk, - &cur_dispc); - - if (abs(cur_dispc.pck - req_pck) < - abs(best_dispc.pck - req_pck)) { - best = cur; - best_dispc = cur_dispc; - - if (cur_dispc.pck == req_pck) - goto found; - } - } - } - } -found: - if (!match) { - if (min_fck_per_pck) { - DSSERR("Could not find suitable clock settings.\n" - "Turning FCK/PCK constraint off and" - "trying again.\n"); - min_fck_per_pck = 0; - goto retry; - } - - DSSERR("Could not find suitable clock settings.\n"); - - return -EINVAL; - } - - /* DSI2_PLL_FCLK (regm4) is not used */ - best.regm4 = 0; - best.dsi2_pll_fclk = 0; - - if (dsi_cinfo) - *dsi_cinfo = best; - if (dispc_cinfo) - *dispc_cinfo = best_dispc; - - dsi.cache_req_pck = req_pck; - dsi.cache_clk_freq = 0; - dsi.cache_cinfo = best; - - return 0; -} - -int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) -{ - int r = 0; - u32 l; - int f; - - DSSDBGF(); - - dsi.current_cinfo.fint = cinfo->fint; - dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr; - dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk; - dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk; - - dsi.current_cinfo.regn = cinfo->regn; - dsi.current_cinfo.regm = cinfo->regm; - dsi.current_cinfo.regm3 = cinfo->regm3; - dsi.current_cinfo.regm4 = cinfo->regm4; - - DSSDBG("DSI Fint %ld\n", cinfo->fint); - - DSSDBG("clkin (%s) rate %ld, highfreq %d\n", - cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree", - cinfo->clkin, - cinfo->highfreq); - - /* DSIPHY == CLKIN4DDR */ - DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n", - cinfo->regm, - cinfo->regn, - cinfo->clkin, - cinfo->highfreq + 1, - cinfo->clkin4ddr); - - DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", - cinfo->clkin4ddr / 1000 / 1000 / 2); - - DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); - - DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n", - cinfo->regm3, cinfo->dsi1_pll_fclk); - DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n", - cinfo->regm4, cinfo->dsi2_pll_fclk); - - REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ - - l = dsi_read_reg(DSI_PLL_CONFIGURATION1); - l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ - l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ - l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ - l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0, - 22, 19); /* DSI_CLOCK_DIV */ - l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0, - 26, 23); /* DSIPROTO_CLOCK_DIV */ - dsi_write_reg(DSI_PLL_CONFIGURATION1, l); - - BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000); - if (cinfo->fint < 1000000) - f = 0x3; - else if (cinfo->fint < 1250000) - f = 0x4; - else if (cinfo->fint < 1500000) - f = 0x5; - else if (cinfo->fint < 1750000) - f = 0x6; - else - f = 0x7; - - l = dsi_read_reg(DSI_PLL_CONFIGURATION2); - l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ - l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, - 11, 11); /* DSI_PLL_CLKSEL */ - l = FLD_MOD(l, cinfo->highfreq, - 12, 12); /* DSI_PLL_HIGHFREQ */ - l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ - l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ - l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ - dsi_write_reg(DSI_PLL_CONFIGURATION2, l); - - REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ - - if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) { - DSSERR("dsi pll go bit not going down.\n"); - r = -EIO; - goto err; - } - - if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) { - DSSERR("cannot lock PLL\n"); - r = -EIO; - goto err; - } - - dsi.pll_locked = 1; - - l = dsi_read_reg(DSI_PLL_CONFIGURATION2); - l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ - l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ - l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ - l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ - l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ - l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ - l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ - l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ - l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ - l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ - l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ - l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ - l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ - l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ - dsi_write_reg(DSI_PLL_CONFIGURATION2, l); - - DSSDBG("PLL config done\n"); -err: - return r; -} - -int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk, - bool enable_hsdiv) -{ - int r = 0; - enum dsi_pll_power_state pwstate; - - DSSDBG("PLL init\n"); - - enable_clocks(1); - dsi_enable_pll_clock(1); - - r = regulator_enable(dsi.vdds_dsi_reg); - if (r) - goto err0; - - /* XXX PLL does not come out of reset without this... */ - dispc_pck_free_enable(1); - - if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) { - DSSERR("PLL not coming out of reset.\n"); - r = -ENODEV; - dispc_pck_free_enable(0); - goto err1; - } - - /* XXX ... but if left on, we get problems when planes do not - * fill the whole display. No idea about this */ - dispc_pck_free_enable(0); - - if (enable_hsclk && enable_hsdiv) - pwstate = DSI_PLL_POWER_ON_ALL; - else if (enable_hsclk) - pwstate = DSI_PLL_POWER_ON_HSCLK; - else if (enable_hsdiv) - pwstate = DSI_PLL_POWER_ON_DIV; - else - pwstate = DSI_PLL_POWER_OFF; - - r = dsi_pll_power(pwstate); - - if (r) - goto err1; - - DSSDBG("PLL init done\n"); - - return 0; -err1: - regulator_disable(dsi.vdds_dsi_reg); -err0: - enable_clocks(0); - dsi_enable_pll_clock(0); - return r; -} - -void dsi_pll_uninit(void) -{ - enable_clocks(0); - dsi_enable_pll_clock(0); - - dsi.pll_locked = 0; - dsi_pll_power(DSI_PLL_POWER_OFF); - regulator_disable(dsi.vdds_dsi_reg); - DSSDBG("PLL uninit done\n"); -} - -void dsi_dump_clocks(struct seq_file *s) -{ - int clksel; - struct dsi_clock_info *cinfo = &dsi.current_cinfo; - - enable_clocks(1); - - clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11); - - seq_printf(s, "- DSI PLL -\n"); - - seq_printf(s, "dsi pll source = %s\n", - clksel == 0 ? - "dss2_alwon_fclk" : "pclkfree"); - - seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); - - seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", - cinfo->clkin4ddr, cinfo->regm); - - seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n", - cinfo->dsi1_pll_fclk, - cinfo->regm3, - dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? - "off" : "on"); - - seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n", - cinfo->dsi2_pll_fclk, - cinfo->regm4, - dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? - "off" : "on"); - - seq_printf(s, "- DSI -\n"); - - seq_printf(s, "dsi fclk source = %s\n", - dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? - "dss1_alwon_fclk" : "dsi2_pll_fclk"); - - seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); - - seq_printf(s, "DDR_CLK\t\t%lu\n", - cinfo->clkin4ddr / 4); - - seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs()); - - seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); - - seq_printf(s, "VP_CLK\t\t%lu\n" - "VP_PCLK\t\t%lu\n", - dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), - dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD)); - - enable_clocks(0); -} - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS -void dsi_dump_irqs(struct seq_file *s) -{ - unsigned long flags; - struct dsi_irq_stats stats; - - spin_lock_irqsave(&dsi.irq_stats_lock, flags); - - stats = dsi.irq_stats; - memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats)); - dsi.irq_stats.last_reset = jiffies; - - spin_unlock_irqrestore(&dsi.irq_stats_lock, flags); - - seq_printf(s, "period %u ms\n", - jiffies_to_msecs(jiffies - stats.last_reset)); - - seq_printf(s, "irqs %d\n", stats.irq_count); -#define PIS(x) \ - seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); - - seq_printf(s, "-- DSI interrupts --\n"); - PIS(VC0); - PIS(VC1); - PIS(VC2); - PIS(VC3); - PIS(WAKEUP); - PIS(RESYNC); - PIS(PLL_LOCK); - PIS(PLL_UNLOCK); - PIS(PLL_RECALL); - PIS(COMPLEXIO_ERR); - PIS(HS_TX_TIMEOUT); - PIS(LP_RX_TIMEOUT); - PIS(TE_TRIGGER); - PIS(ACK_TRIGGER); - PIS(SYNC_LOST); - PIS(LDO_POWER_GOOD); - PIS(TA_TIMEOUT); -#undef PIS - -#define PIS(x) \ - seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ - stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ - stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ - stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ - stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); - - seq_printf(s, "-- VC interrupts --\n"); - PIS(CS); - PIS(ECC_CORR); - PIS(PACKET_SENT); - PIS(FIFO_TX_OVF); - PIS(FIFO_RX_OVF); - PIS(BTA); - PIS(ECC_NO_CORR); - PIS(FIFO_TX_UDF); - PIS(PP_BUSY_CHANGE); -#undef PIS - -#define PIS(x) \ - seq_printf(s, "%-20s %10d\n", #x, \ - stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); - - seq_printf(s, "-- CIO interrupts --\n"); - PIS(ERRSYNCESC1); - PIS(ERRSYNCESC2); - PIS(ERRSYNCESC3); - PIS(ERRESC1); - PIS(ERRESC2); - PIS(ERRESC3); - PIS(ERRCONTROL1); - PIS(ERRCONTROL2); - PIS(ERRCONTROL3); - PIS(STATEULPS1); - PIS(STATEULPS2); - PIS(STATEULPS3); - PIS(ERRCONTENTIONLP0_1); - PIS(ERRCONTENTIONLP1_1); - PIS(ERRCONTENTIONLP0_2); - PIS(ERRCONTENTIONLP1_2); - PIS(ERRCONTENTIONLP0_3); - PIS(ERRCONTENTIONLP1_3); - PIS(ULPSACTIVENOT_ALL0); - PIS(ULPSACTIVENOT_ALL1); -#undef PIS -} -#endif - -void dsi_dump_regs(struct seq_file *s) -{ -#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) - - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - - DUMPREG(DSI_REVISION); - DUMPREG(DSI_SYSCONFIG); - DUMPREG(DSI_SYSSTATUS); - DUMPREG(DSI_IRQSTATUS); - DUMPREG(DSI_IRQENABLE); - DUMPREG(DSI_CTRL); - DUMPREG(DSI_COMPLEXIO_CFG1); - DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); - DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); - DUMPREG(DSI_CLK_CTRL); - DUMPREG(DSI_TIMING1); - DUMPREG(DSI_TIMING2); - DUMPREG(DSI_VM_TIMING1); - DUMPREG(DSI_VM_TIMING2); - DUMPREG(DSI_VM_TIMING3); - DUMPREG(DSI_CLK_TIMING); - DUMPREG(DSI_TX_FIFO_VC_SIZE); - DUMPREG(DSI_RX_FIFO_VC_SIZE); - DUMPREG(DSI_COMPLEXIO_CFG2); - DUMPREG(DSI_RX_FIFO_VC_FULLNESS); - DUMPREG(DSI_VM_TIMING4); - DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); - DUMPREG(DSI_VM_TIMING5); - DUMPREG(DSI_VM_TIMING6); - DUMPREG(DSI_VM_TIMING7); - DUMPREG(DSI_STOPCLK_TIMING); - - DUMPREG(DSI_VC_CTRL(0)); - DUMPREG(DSI_VC_TE(0)); - DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); - DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); - DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); - DUMPREG(DSI_VC_IRQSTATUS(0)); - DUMPREG(DSI_VC_IRQENABLE(0)); - - DUMPREG(DSI_VC_CTRL(1)); - DUMPREG(DSI_VC_TE(1)); - DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); - DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); - DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); - DUMPREG(DSI_VC_IRQSTATUS(1)); - DUMPREG(DSI_VC_IRQENABLE(1)); - - DUMPREG(DSI_VC_CTRL(2)); - DUMPREG(DSI_VC_TE(2)); - DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); - DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); - DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); - DUMPREG(DSI_VC_IRQSTATUS(2)); - DUMPREG(DSI_VC_IRQENABLE(2)); - - DUMPREG(DSI_VC_CTRL(3)); - DUMPREG(DSI_VC_TE(3)); - DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); - DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); - DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); - DUMPREG(DSI_VC_IRQSTATUS(3)); - DUMPREG(DSI_VC_IRQENABLE(3)); - - DUMPREG(DSI_DSIPHY_CFG0); - DUMPREG(DSI_DSIPHY_CFG1); - DUMPREG(DSI_DSIPHY_CFG2); - DUMPREG(DSI_DSIPHY_CFG5); - - DUMPREG(DSI_PLL_CONTROL); - DUMPREG(DSI_PLL_STATUS); - DUMPREG(DSI_PLL_GO); - DUMPREG(DSI_PLL_CONFIGURATION1); - DUMPREG(DSI_PLL_CONFIGURATION2); - - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -#undef DUMPREG -} - -enum dsi_complexio_power_state { - DSI_COMPLEXIO_POWER_OFF = 0x0, - DSI_COMPLEXIO_POWER_ON = 0x1, - DSI_COMPLEXIO_POWER_ULPS = 0x2, -}; - -static int dsi_complexio_power(enum dsi_complexio_power_state state) -{ - int t = 0; - - /* PWR_CMD */ - REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27); - - /* PWR_STATUS */ - while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) { - if (++t > 1000) { - DSSERR("failed to set complexio power state to " - "%d\n", state); - return -ENODEV; - } - udelay(1); - } - - return 0; -} - -static void dsi_complexio_config(struct omap_dss_device *dssdev) -{ - u32 r; - - int clk_lane = dssdev->phy.dsi.clk_lane; - int data1_lane = dssdev->phy.dsi.data1_lane; - int data2_lane = dssdev->phy.dsi.data2_lane; - int clk_pol = dssdev->phy.dsi.clk_pol; - int data1_pol = dssdev->phy.dsi.data1_pol; - int data2_pol = dssdev->phy.dsi.data2_pol; - - r = dsi_read_reg(DSI_COMPLEXIO_CFG1); - r = FLD_MOD(r, clk_lane, 2, 0); - r = FLD_MOD(r, clk_pol, 3, 3); - r = FLD_MOD(r, data1_lane, 6, 4); - r = FLD_MOD(r, data1_pol, 7, 7); - r = FLD_MOD(r, data2_lane, 10, 8); - r = FLD_MOD(r, data2_pol, 11, 11); - dsi_write_reg(DSI_COMPLEXIO_CFG1, r); - - /* The configuration of the DSI complex I/O (number of data lanes, - position, differential order) should not be changed while - DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for - the hardware to take into account a new configuration of the complex - I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to - follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, - then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set - DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the - DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the - DSI complex I/O configuration is unknown. */ - - /* - REG_FLD_MOD(DSI_CTRL, 1, 0, 0); - REG_FLD_MOD(DSI_CTRL, 0, 0, 0); - REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); - REG_FLD_MOD(DSI_CTRL, 1, 0, 0); - */ -} - -static inline unsigned ns2ddr(unsigned ns) -{ - /* convert time in ns to ddr ticks, rounding up */ - unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; - return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; -} - -static inline unsigned ddr2ns(unsigned ddr) -{ - unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; - return ddr * 1000 * 1000 / (ddr_clk / 1000); -} - -static void dsi_complexio_timings(void) -{ - u32 r; - u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; - u32 tlpx_half, tclk_trail, tclk_zero; - u32 tclk_prepare; - - /* calculate timings */ - - /* 1 * DDR_CLK = 2 * UI */ - - /* min 40ns + 4*UI max 85ns + 6*UI */ - ths_prepare = ns2ddr(70) + 2; - - /* min 145ns + 10*UI */ - ths_prepare_ths_zero = ns2ddr(175) + 2; - - /* min max(8*UI, 60ns+4*UI) */ - ths_trail = ns2ddr(60) + 5; - - /* min 100ns */ - ths_exit = ns2ddr(145); - - /* tlpx min 50n */ - tlpx_half = ns2ddr(25); - - /* min 60ns */ - tclk_trail = ns2ddr(60) + 2; - - /* min 38ns, max 95ns */ - tclk_prepare = ns2ddr(65); - - /* min tclk-prepare + tclk-zero = 300ns */ - tclk_zero = ns2ddr(260); - - DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", - ths_prepare, ddr2ns(ths_prepare), - ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero)); - DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", - ths_trail, ddr2ns(ths_trail), - ths_exit, ddr2ns(ths_exit)); - - DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " - "tclk_zero %u (%uns)\n", - tlpx_half, ddr2ns(tlpx_half), - tclk_trail, ddr2ns(tclk_trail), - tclk_zero, ddr2ns(tclk_zero)); - DSSDBG("tclk_prepare %u (%uns)\n", - tclk_prepare, ddr2ns(tclk_prepare)); - - /* program timings */ - - r = dsi_read_reg(DSI_DSIPHY_CFG0); - r = FLD_MOD(r, ths_prepare, 31, 24); - r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); - r = FLD_MOD(r, ths_trail, 15, 8); - r = FLD_MOD(r, ths_exit, 7, 0); - dsi_write_reg(DSI_DSIPHY_CFG0, r); - - r = dsi_read_reg(DSI_DSIPHY_CFG1); - r = FLD_MOD(r, tlpx_half, 22, 16); - r = FLD_MOD(r, tclk_trail, 15, 8); - r = FLD_MOD(r, tclk_zero, 7, 0); - dsi_write_reg(DSI_DSIPHY_CFG1, r); - - r = dsi_read_reg(DSI_DSIPHY_CFG2); - r = FLD_MOD(r, tclk_prepare, 7, 0); - dsi_write_reg(DSI_DSIPHY_CFG2, r); -} - - -static int dsi_complexio_init(struct omap_dss_device *dssdev) -{ - int r = 0; - - DSSDBG("dsi_complexio_init\n"); - - /* CIO_CLK_ICG, enable L3 clk to CIO */ - REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); - - /* A dummy read using the SCP interface to any DSIPHY register is - * required after DSIPHY reset to complete the reset of the DSI complex - * I/O. */ - dsi_read_reg(DSI_DSIPHY_CFG5); - - if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) { - DSSERR("ComplexIO PHY not coming out of reset.\n"); - r = -ENODEV; - goto err; - } - - dsi_complexio_config(dssdev); - - r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON); - - if (r) - goto err; - - if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) { - DSSERR("ComplexIO not coming out of reset.\n"); - r = -ENODEV; - goto err; - } - - if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) { - DSSERR("ComplexIO LDO power down.\n"); - r = -ENODEV; - goto err; - } - - dsi_complexio_timings(); - - /* - The configuration of the DSI complex I/O (number of data lanes, - position, differential order) should not be changed while - DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the - hardware to recognize a new configuration of the complex I/O (done - in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow - this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next - reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20] - LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN - bit to 1. If the sequence is not followed, the DSi complex I/O - configuration is undetermined. - */ - dsi_if_enable(1); - dsi_if_enable(0); - REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ - dsi_if_enable(1); - dsi_if_enable(0); - - DSSDBG("CIO init done\n"); -err: - return r; -} - -static void dsi_complexio_uninit(void) -{ - dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF); -} - -static int _dsi_wait_reset(void) -{ - int t = 0; - - while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) { - if (++t > 5) { - DSSERR("soft reset failed\n"); - return -ENODEV; - } - udelay(1); - } - - return 0; -} - -static int _dsi_reset(void) -{ - /* Soft reset */ - REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1); - return _dsi_wait_reset(); -} - -static void dsi_reset_tx_fifo(int channel) -{ - u32 mask; - u32 l; - - /* set fifosize of the channel to 0, then return the old size */ - l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE); - - mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4); - dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask); - - dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l); -} - -static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, - enum fifo_size size3, enum fifo_size size4) -{ - u32 r = 0; - int add = 0; - int i; - - dsi.vc[0].fifo_size = size1; - dsi.vc[1].fifo_size = size2; - dsi.vc[2].fifo_size = size3; - dsi.vc[3].fifo_size = size4; - - for (i = 0; i < 4; i++) { - u8 v; - int size = dsi.vc[i].fifo_size; - - if (add + size > 4) { - DSSERR("Illegal FIFO configuration\n"); - BUG(); - } - - v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); - r |= v << (8 * i); - /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ - add += size; - } - - dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r); -} - -static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2, - enum fifo_size size3, enum fifo_size size4) -{ - u32 r = 0; - int add = 0; - int i; - - dsi.vc[0].fifo_size = size1; - dsi.vc[1].fifo_size = size2; - dsi.vc[2].fifo_size = size3; - dsi.vc[3].fifo_size = size4; - - for (i = 0; i < 4; i++) { - u8 v; - int size = dsi.vc[i].fifo_size; - - if (add + size > 4) { - DSSERR("Illegal FIFO configuration\n"); - BUG(); - } - - v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); - r |= v << (8 * i); - /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ - add += size; - } - - dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r); -} - -static int dsi_force_tx_stop_mode_io(void) -{ - u32 r; - - r = dsi_read_reg(DSI_TIMING1); - r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ - dsi_write_reg(DSI_TIMING1, r); - - if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) { - DSSERR("TX_STOP bit not going down\n"); - return -EIO; - } - - return 0; -} - -static int dsi_vc_enable(int channel, bool enable) -{ - DSSDBG("dsi_vc_enable channel %d, enable %d\n", - channel, enable); - - enable = enable ? 1 : 0; - - REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0); - - if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) { - DSSERR("Failed to set dsi_vc_enable to %d\n", enable); - return -EIO; - } - - return 0; -} - -static void dsi_vc_initial_config(int channel) -{ - u32 r; - - DSSDBGF("%d", channel); - - r = dsi_read_reg(DSI_VC_CTRL(channel)); - - if (FLD_GET(r, 15, 15)) /* VC_BUSY */ - DSSERR("VC(%d) busy when trying to configure it!\n", - channel); - - r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ - r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ - r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ - r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ - r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ - r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ - r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ - - r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ - r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ - - dsi_write_reg(DSI_VC_CTRL(channel), r); - - dsi.vc[channel].mode = DSI_VC_MODE_L4; -} - -static int dsi_vc_config_l4(int channel) -{ - if (dsi.vc[channel].mode == DSI_VC_MODE_L4) - return 0; - - DSSDBGF("%d", channel); - - dsi_vc_enable(channel, 0); - - /* VC_BUSY */ - if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { - DSSERR("vc(%d) busy when trying to config for L4\n", channel); - return -EIO; - } - - REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */ - - dsi_vc_enable(channel, 1); - - dsi.vc[channel].mode = DSI_VC_MODE_L4; - - return 0; -} - -static int dsi_vc_config_vp(int channel) -{ - if (dsi.vc[channel].mode == DSI_VC_MODE_VP) - return 0; - - DSSDBGF("%d", channel); - - dsi_vc_enable(channel, 0); - - /* VC_BUSY */ - if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { - DSSERR("vc(%d) busy when trying to config for VP\n", channel); - return -EIO; - } - - REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */ - - dsi_vc_enable(channel, 1); - - dsi.vc[channel].mode = DSI_VC_MODE_VP; - - return 0; -} - - -void omapdss_dsi_vc_enable_hs(int channel, bool enable) -{ - DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); - - WARN_ON(!dsi_bus_is_locked()); - - dsi_vc_enable(channel, 0); - dsi_if_enable(0); - - REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9); - - dsi_vc_enable(channel, 1); - dsi_if_enable(1); - - dsi_force_tx_stop_mode_io(); -} -EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); - -static void dsi_vc_flush_long_data(int channel) -{ - while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { - u32 val; - val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); - DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", - (val >> 0) & 0xff, - (val >> 8) & 0xff, - (val >> 16) & 0xff, - (val >> 24) & 0xff); - } -} - -static void dsi_show_rx_ack_with_err(u16 err) -{ - DSSERR("\tACK with ERROR (%#x):\n", err); - if (err & (1 << 0)) - DSSERR("\t\tSoT Error\n"); - if (err & (1 << 1)) - DSSERR("\t\tSoT Sync Error\n"); - if (err & (1 << 2)) - DSSERR("\t\tEoT Sync Error\n"); - if (err & (1 << 3)) - DSSERR("\t\tEscape Mode Entry Command Error\n"); - if (err & (1 << 4)) - DSSERR("\t\tLP Transmit Sync Error\n"); - if (err & (1 << 5)) - DSSERR("\t\tHS Receive Timeout Error\n"); - if (err & (1 << 6)) - DSSERR("\t\tFalse Control Error\n"); - if (err & (1 << 7)) - DSSERR("\t\t(reserved7)\n"); - if (err & (1 << 8)) - DSSERR("\t\tECC Error, single-bit (corrected)\n"); - if (err & (1 << 9)) - DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); - if (err & (1 << 10)) - DSSERR("\t\tChecksum Error\n"); - if (err & (1 << 11)) - DSSERR("\t\tData type not recognized\n"); - if (err & (1 << 12)) - DSSERR("\t\tInvalid VC ID\n"); - if (err & (1 << 13)) - DSSERR("\t\tInvalid Transmission Length\n"); - if (err & (1 << 14)) - DSSERR("\t\t(reserved14)\n"); - if (err & (1 << 15)) - DSSERR("\t\tDSI Protocol Violation\n"); -} - -static u16 dsi_vc_flush_receive_data(int channel) -{ - /* RX_FIFO_NOT_EMPTY */ - while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { - u32 val; - u8 dt; - val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); - DSSERR("\trawval %#08x\n", val); - dt = FLD_GET(val, 5, 0); - if (dt == DSI_DT_RX_ACK_WITH_ERR) { - u16 err = FLD_GET(val, 23, 8); - dsi_show_rx_ack_with_err(err); - } else if (dt == DSI_DT_RX_SHORT_READ_1) { - DSSERR("\tDCS short response, 1 byte: %#x\n", - FLD_GET(val, 23, 8)); - } else if (dt == DSI_DT_RX_SHORT_READ_2) { - DSSERR("\tDCS short response, 2 byte: %#x\n", - FLD_GET(val, 23, 8)); - } else if (dt == DSI_DT_RX_DCS_LONG_READ) { - DSSERR("\tDCS long response, len %d\n", - FLD_GET(val, 23, 8)); - dsi_vc_flush_long_data(channel); - } else { - DSSERR("\tunknown datatype 0x%02x\n", dt); - } - } - return 0; -} - -static int dsi_vc_send_bta(int channel) -{ - if (dsi.debug_write || dsi.debug_read) - DSSDBG("dsi_vc_send_bta %d\n", channel); - - WARN_ON(!dsi_bus_is_locked()); - - if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ - DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); - dsi_vc_flush_receive_data(channel); - } - - REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ - - return 0; -} - -int dsi_vc_send_bta_sync(int channel) -{ - int r = 0; - u32 err; - - INIT_COMPLETION(dsi.bta_completion); - - dsi_vc_enable_bta_irq(channel); - - r = dsi_vc_send_bta(channel); - if (r) - goto err; - - if (wait_for_completion_timeout(&dsi.bta_completion, - msecs_to_jiffies(500)) == 0) { - DSSERR("Failed to receive BTA\n"); - r = -EIO; - goto err; - } - - err = dsi_get_errors(); - if (err) { - DSSERR("Error while sending BTA: %x\n", err); - r = -EIO; - goto err; - } -err: - dsi_vc_disable_bta_irq(channel); - - return r; -} -EXPORT_SYMBOL(dsi_vc_send_bta_sync); - -static inline void dsi_vc_write_long_header(int channel, u8 data_type, - u16 len, u8 ecc) -{ - u32 val; - u8 data_id; - - WARN_ON(!dsi_bus_is_locked()); - - data_id = data_type | channel << 6; - - val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | - FLD_VAL(ecc, 31, 24); - - dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val); -} - -static inline void dsi_vc_write_long_payload(int channel, - u8 b1, u8 b2, u8 b3, u8 b4) -{ - u32 val; - - val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; - -/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", - b1, b2, b3, b4, val); */ - - dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val); -} - -static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len, - u8 ecc) -{ - /*u32 val; */ - int i; - u8 *p; - int r = 0; - u8 b1, b2, b3, b4; - - if (dsi.debug_write) - DSSDBG("dsi_vc_send_long, %d bytes\n", len); - - /* len + header */ - if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) { - DSSERR("unable to send long packet: packet too long.\n"); - return -EINVAL; - } - - dsi_vc_config_l4(channel); - - dsi_vc_write_long_header(channel, data_type, len, ecc); - - p = data; - for (i = 0; i < len >> 2; i++) { - if (dsi.debug_write) - DSSDBG("\tsending full packet %d\n", i); - - b1 = *p++; - b2 = *p++; - b3 = *p++; - b4 = *p++; - - dsi_vc_write_long_payload(channel, b1, b2, b3, b4); - } - - i = len % 4; - if (i) { - b1 = 0; b2 = 0; b3 = 0; - - if (dsi.debug_write) - DSSDBG("\tsending remainder bytes %d\n", i); - - switch (i) { - case 3: - b1 = *p++; - b2 = *p++; - b3 = *p++; - break; - case 2: - b1 = *p++; - b2 = *p++; - break; - case 1: - b1 = *p++; - break; - } - - dsi_vc_write_long_payload(channel, b1, b2, b3, 0); - } - - return r; -} - -static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc) -{ - u32 r; - u8 data_id; - - WARN_ON(!dsi_bus_is_locked()); - - if (dsi.debug_write) - DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", - channel, - data_type, data & 0xff, (data >> 8) & 0xff); - - dsi_vc_config_l4(channel); - - if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) { - DSSERR("ERROR FIFO FULL, aborting transfer\n"); - return -EINVAL; - } - - data_id = data_type | channel << 6; - - r = (data_id << 0) | (data << 8) | (ecc << 24); - - dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r); - - return 0; -} - -int dsi_vc_send_null(int channel) -{ - u8 nullpkg[] = {0, 0, 0, 0}; - return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0); -} -EXPORT_SYMBOL(dsi_vc_send_null); - -int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len) -{ - int r; - - BUG_ON(len == 0); - - if (len == 1) { - r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0, - data[0], 0); - } else if (len == 2) { - r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1, - data[0] | (data[1] << 8), 0); - } else { - /* 0x39 = DCS Long Write */ - r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE, - data, len, 0); - } - - return r; -} -EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); - -int dsi_vc_dcs_write(int channel, u8 *data, int len) -{ - int r; - - r = dsi_vc_dcs_write_nosync(channel, data, len); - if (r) - goto err; - - r = dsi_vc_send_bta_sync(channel); - if (r) - goto err; - - if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ - DSSERR("rx fifo not empty after write, dumping data:\n"); - dsi_vc_flush_receive_data(channel); - r = -EIO; - goto err; - } - - return 0; -err: - DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n", - channel, data[0], len); - return r; -} -EXPORT_SYMBOL(dsi_vc_dcs_write); - -int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd) -{ - return dsi_vc_dcs_write(channel, &dcs_cmd, 1); -} -EXPORT_SYMBOL(dsi_vc_dcs_write_0); - -int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param) -{ - u8 buf[2]; - buf[0] = dcs_cmd; - buf[1] = param; - return dsi_vc_dcs_write(channel, buf, 2); -} -EXPORT_SYMBOL(dsi_vc_dcs_write_1); - -int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen) -{ - u32 val; - u8 dt; - int r; - - if (dsi.debug_read) - DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd); - - r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0); - if (r) - goto err; - - r = dsi_vc_send_bta_sync(channel); - if (r) - goto err; - - /* RX_FIFO_NOT_EMPTY */ - if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { - DSSERR("RX fifo empty when trying to read.\n"); - r = -EIO; - goto err; - } - - val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); - if (dsi.debug_read) - DSSDBG("\theader: %08x\n", val); - dt = FLD_GET(val, 5, 0); - if (dt == DSI_DT_RX_ACK_WITH_ERR) { - u16 err = FLD_GET(val, 23, 8); - dsi_show_rx_ack_with_err(err); - r = -EIO; - goto err; - - } else if (dt == DSI_DT_RX_SHORT_READ_1) { - u8 data = FLD_GET(val, 15, 8); - if (dsi.debug_read) - DSSDBG("\tDCS short response, 1 byte: %02x\n", data); - - if (buflen < 1) { - r = -EIO; - goto err; - } - - buf[0] = data; - - return 1; - } else if (dt == DSI_DT_RX_SHORT_READ_2) { - u16 data = FLD_GET(val, 23, 8); - if (dsi.debug_read) - DSSDBG("\tDCS short response, 2 byte: %04x\n", data); - - if (buflen < 2) { - r = -EIO; - goto err; - } - - buf[0] = data & 0xff; - buf[1] = (data >> 8) & 0xff; - - return 2; - } else if (dt == DSI_DT_RX_DCS_LONG_READ) { - int w; - int len = FLD_GET(val, 23, 8); - if (dsi.debug_read) - DSSDBG("\tDCS long response, len %d\n", len); - - if (len > buflen) { - r = -EIO; - goto err; - } - - /* two byte checksum ends the packet, not included in len */ - for (w = 0; w < len + 2;) { - int b; - val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); - if (dsi.debug_read) - DSSDBG("\t\t%02x %02x %02x %02x\n", - (val >> 0) & 0xff, - (val >> 8) & 0xff, - (val >> 16) & 0xff, - (val >> 24) & 0xff); - - for (b = 0; b < 4; ++b) { - if (w < len) - buf[w] = (val >> (b * 8)) & 0xff; - /* we discard the 2 byte checksum */ - ++w; - } - } - - return len; - } else { - DSSERR("\tunknown datatype 0x%02x\n", dt); - r = -EIO; - goto err; - } - - BUG(); -err: - DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", - channel, dcs_cmd); - return r; - -} -EXPORT_SYMBOL(dsi_vc_dcs_read); - -int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data) -{ - int r; - - r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1); - - if (r < 0) - return r; - - if (r != 1) - return -EIO; - - return 0; -} -EXPORT_SYMBOL(dsi_vc_dcs_read_1); - -int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2) -{ - u8 buf[2]; - int r; - - r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2); - - if (r < 0) - return r; - - if (r != 2) - return -EIO; - - *data1 = buf[0]; - *data2 = buf[1]; - - return 0; -} -EXPORT_SYMBOL(dsi_vc_dcs_read_2); - -int dsi_vc_set_max_rx_packet_size(int channel, u16 len) -{ - return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE, - len, 0); -} -EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); - -static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16) -{ - unsigned long fck; - unsigned long total_ticks; - u32 r; - - BUG_ON(ticks > 0x1fff); - - /* ticks in DSI_FCK */ - fck = dsi_fclk_rate(); - - r = dsi_read_reg(DSI_TIMING2); - r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ - r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ - r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ - r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ - dsi_write_reg(DSI_TIMING2, r); - - total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); - - DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", - total_ticks, - ticks, x4 ? " x4" : "", x16 ? " x16" : "", - (total_ticks * 1000) / (fck / 1000 / 1000)); -} - -static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16) -{ - unsigned long fck; - unsigned long total_ticks; - u32 r; - - BUG_ON(ticks > 0x1fff); - - /* ticks in DSI_FCK */ - fck = dsi_fclk_rate(); - - r = dsi_read_reg(DSI_TIMING1); - r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ - r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ - r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ - r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ - dsi_write_reg(DSI_TIMING1, r); - - total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); - - DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", - total_ticks, - ticks, x8 ? " x8" : "", x16 ? " x16" : "", - (total_ticks * 1000) / (fck / 1000 / 1000)); -} - -static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16) -{ - unsigned long fck; - unsigned long total_ticks; - u32 r; - - BUG_ON(ticks > 0x1fff); - - /* ticks in DSI_FCK */ - fck = dsi_fclk_rate(); - - r = dsi_read_reg(DSI_TIMING1); - r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ - r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ - r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ - r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ - dsi_write_reg(DSI_TIMING1, r); - - total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); - - DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", - total_ticks, - ticks, x4 ? " x4" : "", x16 ? " x16" : "", - (total_ticks * 1000) / (fck / 1000 / 1000)); -} - -static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16) -{ - unsigned long fck; - unsigned long total_ticks; - u32 r; - - BUG_ON(ticks > 0x1fff); - - /* ticks in TxByteClkHS */ - fck = dsi_get_txbyteclkhs(); - - r = dsi_read_reg(DSI_TIMING2); - r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ - r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ - r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ - r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ - dsi_write_reg(DSI_TIMING2, r); - - total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); - - DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", - total_ticks, - ticks, x4 ? " x4" : "", x16 ? " x16" : "", - (total_ticks * 1000) / (fck / 1000 / 1000)); -} -static int dsi_proto_config(struct omap_dss_device *dssdev) -{ - u32 r; - int buswidth = 0; - - dsi_config_tx_fifo(DSI_FIFO_SIZE_32, - DSI_FIFO_SIZE_32, - DSI_FIFO_SIZE_32, - DSI_FIFO_SIZE_32); - - dsi_config_rx_fifo(DSI_FIFO_SIZE_32, - DSI_FIFO_SIZE_32, - DSI_FIFO_SIZE_32, - DSI_FIFO_SIZE_32); - - /* XXX what values for the timeouts? */ - dsi_set_stop_state_counter(0x1000, false, false); - dsi_set_ta_timeout(0x1fff, true, true); - dsi_set_lp_rx_timeout(0x1fff, true, true); - dsi_set_hs_tx_timeout(0x1fff, true, true); - - switch (dssdev->ctrl.pixel_size) { - case 16: - buswidth = 0; - break; - case 18: - buswidth = 1; - break; - case 24: - buswidth = 2; - break; - default: - BUG(); - } - - r = dsi_read_reg(DSI_CTRL); - r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ - r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ - r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ - r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ - r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ - r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ - r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */ - r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ - r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ - r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ - r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */ - - dsi_write_reg(DSI_CTRL, r); - - dsi_vc_initial_config(0); - dsi_vc_initial_config(1); - dsi_vc_initial_config(2); - dsi_vc_initial_config(3); - - return 0; -} - -static void dsi_proto_timings(struct omap_dss_device *dssdev) -{ - unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; - unsigned tclk_pre, tclk_post; - unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; - unsigned ths_trail, ths_exit; - unsigned ddr_clk_pre, ddr_clk_post; - unsigned enter_hs_mode_lat, exit_hs_mode_lat; - unsigned ths_eot; - u32 r; - - r = dsi_read_reg(DSI_DSIPHY_CFG0); - ths_prepare = FLD_GET(r, 31, 24); - ths_prepare_ths_zero = FLD_GET(r, 23, 16); - ths_zero = ths_prepare_ths_zero - ths_prepare; - ths_trail = FLD_GET(r, 15, 8); - ths_exit = FLD_GET(r, 7, 0); - - r = dsi_read_reg(DSI_DSIPHY_CFG1); - tlpx = FLD_GET(r, 22, 16) * 2; - tclk_trail = FLD_GET(r, 15, 8); - tclk_zero = FLD_GET(r, 7, 0); - - r = dsi_read_reg(DSI_DSIPHY_CFG2); - tclk_prepare = FLD_GET(r, 7, 0); - - /* min 8*UI */ - tclk_pre = 20; - /* min 60ns + 52*UI */ - tclk_post = ns2ddr(60) + 26; - - /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */ - if (dssdev->phy.dsi.data1_lane != 0 && - dssdev->phy.dsi.data2_lane != 0) - ths_eot = 2; - else - ths_eot = 4; - - ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, - 4); - ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; - - BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); - BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); - - r = dsi_read_reg(DSI_CLK_TIMING); - r = FLD_MOD(r, ddr_clk_pre, 15, 8); - r = FLD_MOD(r, ddr_clk_post, 7, 0); - dsi_write_reg(DSI_CLK_TIMING, r); - - DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", - ddr_clk_pre, - ddr_clk_post); - - enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + - DIV_ROUND_UP(ths_prepare, 4) + - DIV_ROUND_UP(ths_zero + 3, 4); - - exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; - - r = FLD_VAL(enter_hs_mode_lat, 31, 16) | - FLD_VAL(exit_hs_mode_lat, 15, 0); - dsi_write_reg(DSI_VM_TIMING7, r); - - DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", - enter_hs_mode_lat, exit_hs_mode_lat); -} - - -#define DSI_DECL_VARS \ - int __dsi_cb = 0; u32 __dsi_cv = 0; - -#define DSI_FLUSH(ch) \ - if (__dsi_cb > 0) { \ - /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \ - dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \ - __dsi_cb = __dsi_cv = 0; \ - } - -#define DSI_PUSH(ch, data) \ - do { \ - __dsi_cv |= (data) << (__dsi_cb * 8); \ - /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \ - if (++__dsi_cb > 3) \ - DSI_FLUSH(ch); \ - } while (0) - -static int dsi_update_screen_l4(struct omap_dss_device *dssdev, - int x, int y, int w, int h) -{ - /* Note: supports only 24bit colors in 32bit container */ - int first = 1; - int fifo_stalls = 0; - int max_dsi_packet_size; - int max_data_per_packet; - int max_pixels_per_packet; - int pixels_left; - int bytespp = dssdev->ctrl.pixel_size / 8; - int scr_width; - u32 __iomem *data; - int start_offset; - int horiz_inc; - int current_x; - struct omap_overlay *ovl; - - debug_irq = 0; - - DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n", - x, y, w, h); - - ovl = dssdev->manager->overlays[0]; - - if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U) - return -EINVAL; - - if (dssdev->ctrl.pixel_size != 24) - return -EINVAL; - - scr_width = ovl->info.screen_width; - data = ovl->info.vaddr; - - start_offset = scr_width * y + x; - horiz_inc = scr_width - w; - current_x = x; - - /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes - * in fifo */ - - /* When using CPU, max long packet size is TX buffer size */ - max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4; - - /* we seem to get better perf if we divide the tx fifo to half, - and while the other half is being sent, we fill the other half - max_dsi_packet_size /= 2; */ - - max_data_per_packet = max_dsi_packet_size - 4 - 1; - - max_pixels_per_packet = max_data_per_packet / bytespp; - - DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet); - - pixels_left = w * h; - - DSSDBG("total pixels %d\n", pixels_left); - - data += start_offset; - - while (pixels_left > 0) { - /* 0x2c = write_memory_start */ - /* 0x3c = write_memory_continue */ - u8 dcs_cmd = first ? 0x2c : 0x3c; - int pixels; - DSI_DECL_VARS; - first = 0; - -#if 1 - /* using fifo not empty */ - /* TX_FIFO_NOT_EMPTY */ - while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) { - fifo_stalls++; - if (fifo_stalls > 0xfffff) { - DSSERR("fifo stalls overflow, pixels left %d\n", - pixels_left); - dsi_if_enable(0); - return -EIO; - } - udelay(1); - } -#elif 1 - /* using fifo emptiness */ - while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 < - max_dsi_packet_size) { - fifo_stalls++; - if (fifo_stalls > 0xfffff) { - DSSERR("fifo stalls overflow, pixels left %d\n", - pixels_left); - dsi_if_enable(0); - return -EIO; - } - } -#else - while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) { - fifo_stalls++; - if (fifo_stalls > 0xfffff) { - DSSERR("fifo stalls overflow, pixels left %d\n", - pixels_left); - dsi_if_enable(0); - return -EIO; - } - } -#endif - pixels = min(max_pixels_per_packet, pixels_left); - - pixels_left -= pixels; - - dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE, - 1 + pixels * bytespp, 0); - - DSI_PUSH(0, dcs_cmd); - - while (pixels-- > 0) { - u32 pix = __raw_readl(data++); - - DSI_PUSH(0, (pix >> 16) & 0xff); - DSI_PUSH(0, (pix >> 8) & 0xff); - DSI_PUSH(0, (pix >> 0) & 0xff); - - current_x++; - if (current_x == x+w) { - current_x = x; - data += horiz_inc; - } - } - - DSI_FLUSH(0); - } - - return 0; -} - -static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, - u16 x, u16 y, u16 w, u16 h) -{ - unsigned bytespp; - unsigned bytespl; - unsigned bytespf; - unsigned total_len; - unsigned packet_payload; - unsigned packet_len; - u32 l; - int r; - const unsigned channel = dsi.update_channel; - /* line buffer is 1024 x 24bits */ - /* XXX: for some reason using full buffer size causes considerable TX - * slowdown with update sizes that fill the whole buffer */ - const unsigned line_buf_size = 1023 * 3; - - DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n", - x, y, w, h); - - dsi_vc_config_vp(channel); - - bytespp = dssdev->ctrl.pixel_size / 8; - bytespl = w * bytespp; - bytespf = bytespl * h; - - /* NOTE: packet_payload has to be equal to N * bytespl, where N is - * number of lines in a packet. See errata about VP_CLK_RATIO */ - - if (bytespf < line_buf_size) - packet_payload = bytespf; - else - packet_payload = (line_buf_size) / bytespl * bytespl; - - packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ - total_len = (bytespf / packet_payload) * packet_len; - - if (bytespf % packet_payload) - total_len += (bytespf % packet_payload) + 1; - - l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ - dsi_write_reg(DSI_VC_TE(channel), l); - - dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0); - - if (dsi.te_enabled) - l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ - else - l = FLD_MOD(l, 1, 31, 31); /* TE_START */ - dsi_write_reg(DSI_VC_TE(channel), l); - - /* We put SIDLEMODE to no-idle for the duration of the transfer, - * because DSS interrupts are not capable of waking up the CPU and the - * framedone interrupt could be delayed for quite a long time. I think - * the same goes for any DSS interrupts, but for some reason I have not - * seen the problem anywhere else than here. - */ - dispc_disable_sidle(); - - dsi_perf_mark_start(); - - r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work, - msecs_to_jiffies(250)); - BUG_ON(r == 0); - - dss_start_update(dssdev); - - if (dsi.te_enabled) { - /* disable LP_RX_TO, so that we can receive TE. Time to wait - * for TE is longer than the timer allows */ - REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ - - dsi_vc_send_bta(channel); - -#ifdef DSI_CATCH_MISSING_TE - mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250)); -#endif - } -} - -#ifdef DSI_CATCH_MISSING_TE -static void dsi_te_timeout(unsigned long arg) -{ - DSSERR("TE not received for 250ms!\n"); -} -#endif - -static void dsi_handle_framedone(int error) -{ - const int channel = dsi.update_channel; - - cancel_delayed_work(&dsi.framedone_timeout_work); - - dsi_vc_disable_bta_irq(channel); - - /* SIDLEMODE back to smart-idle */ - dispc_enable_sidle(); - - dsi.bta_callback = NULL; - - if (dsi.te_enabled) { - /* enable LP_RX_TO again after the TE */ - REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ - } - - /* RX_FIFO_NOT_EMPTY */ - if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { - DSSERR("Received error during frame transfer:\n"); - dsi_vc_flush_receive_data(channel); - if (!error) - error = -EIO; - } - - dsi.framedone_callback(error, dsi.framedone_data); - - if (!error) - dsi_perf_show("DISPC"); -} - -static void dsi_framedone_timeout_work_callback(struct work_struct *work) -{ - /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after - * 250ms which would conflict with this timeout work. What should be - * done is first cancel the transfer on the HW, and then cancel the - * possibly scheduled framedone work. However, cancelling the transfer - * on the HW is buggy, and would probably require resetting the whole - * DSI */ - - DSSERR("Framedone not received for 250ms!\n"); - - dsi_handle_framedone(-ETIMEDOUT); -} - -static void dsi_framedone_bta_callback(void) -{ - dsi_handle_framedone(0); - -#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC - dispc_fake_vsync_irq(); -#endif -} - -static void dsi_framedone_irq_callback(void *data, u32 mask) -{ - const int channel = dsi.update_channel; - int r; - - /* Note: We get FRAMEDONE when DISPC has finished sending pixels and - * turns itself off. However, DSI still has the pixels in its buffers, - * and is sending the data. - */ - - if (dsi.te_enabled) { - /* enable LP_RX_TO again after the TE */ - REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ - } - - /* Send BTA after the frame. We need this for the TE to work, as TE - * trigger is only sent for BTAs without preceding packet. Thus we need - * to BTA after the pixel packets so that next BTA will cause TE - * trigger. - * - * This is not needed when TE is not in use, but we do it anyway to - * make sure that the transfer has been completed. It would be more - * optimal, but more complex, to wait only just before starting next - * transfer. - * - * Also, as there's no interrupt telling when the transfer has been - * done and the channel could be reconfigured, the only way is to - * busyloop until TE_SIZE is zero. With BTA we can do this - * asynchronously. - * */ - - dsi.bta_callback = dsi_framedone_bta_callback; - - barrier(); - - dsi_vc_enable_bta_irq(channel); - - r = dsi_vc_send_bta(channel); - if (r) { - DSSERR("BTA after framedone failed\n"); - dsi_handle_framedone(-EIO); - } -} - -int omap_dsi_prepare_update(struct omap_dss_device *dssdev, - u16 *x, u16 *y, u16 *w, u16 *h, - bool enlarge_update_area) -{ - u16 dw, dh; - - dssdev->driver->get_resolution(dssdev, &dw, &dh); - - if (*x > dw || *y > dh) - return -EINVAL; - - if (*x + *w > dw) - return -EINVAL; - - if (*y + *h > dh) - return -EINVAL; - - if (*w == 1) - return -EINVAL; - - if (*w == 0 || *h == 0) - return -EINVAL; - - dsi_perf_mark_setup(); - - if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { - dss_setup_partial_planes(dssdev, x, y, w, h, - enlarge_update_area); - dispc_set_lcd_size(dssdev->manager->id, *w, *h); - } - - return 0; -} -EXPORT_SYMBOL(omap_dsi_prepare_update); - -int omap_dsi_update(struct omap_dss_device *dssdev, - int channel, - u16 x, u16 y, u16 w, u16 h, - void (*callback)(int, void *), void *data) -{ - dsi.update_channel = channel; - - /* OMAP DSS cannot send updates of odd widths. - * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON - * here to make sure we catch erroneous updates. Otherwise we'll only - * see rather obscure HW error happening, as DSS halts. */ - BUG_ON(x % 2 == 1); - - if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { - dsi.framedone_callback = callback; - dsi.framedone_data = data; - - dsi.update_region.x = x; - dsi.update_region.y = y; - dsi.update_region.w = w; - dsi.update_region.h = h; - dsi.update_region.device = dssdev; - - dsi_update_screen_dispc(dssdev, x, y, w, h); - } else { - int r; - - r = dsi_update_screen_l4(dssdev, x, y, w, h); - if (r) - return r; - - dsi_perf_show("L4"); - callback(0, data); - } - - return 0; -} -EXPORT_SYMBOL(omap_dsi_update); - -/* Display funcs */ - -static int dsi_display_init_dispc(struct omap_dss_device *dssdev) -{ - int r; - - r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL, - DISPC_IRQ_FRAMEDONE); - if (r) { - DSSERR("can't get FRAMEDONE irq\n"); - return r; - } - - dispc_set_lcd_display_type(dssdev->manager->id, - OMAP_DSS_LCD_DISPLAY_TFT); - - dispc_set_parallel_interface_mode(dssdev->manager->id, - OMAP_DSS_PARALLELMODE_DSI); - dispc_enable_fifohandcheck(dssdev->manager->id, 1); - - dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size); - - { - struct omap_video_timings timings = { - .hsw = 1, - .hfp = 1, - .hbp = 1, - .vsw = 1, - .vfp = 0, - .vbp = 0, - }; - - dispc_set_lcd_timings(dssdev->manager->id, &timings); - } - - return 0; -} - -static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) -{ - omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL, - DISPC_IRQ_FRAMEDONE); -} - -static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) -{ - struct dsi_clock_info cinfo; - int r; - - /* we always use DSS2_FCK as input clock */ - cinfo.use_dss2_fck = true; - cinfo.regn = dssdev->phy.dsi.div.regn; - cinfo.regm = dssdev->phy.dsi.div.regm; - cinfo.regm3 = dssdev->phy.dsi.div.regm3; - cinfo.regm4 = dssdev->phy.dsi.div.regm4; - r = dsi_calc_clock_rates(dssdev, &cinfo); - if (r) { - DSSERR("Failed to calc dsi clocks\n"); - return r; - } - - r = dsi_pll_set_clock_div(&cinfo); - if (r) { - DSSERR("Failed to set dsi clocks\n"); - return r; - } - - return 0; -} - -static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) -{ - struct dispc_clock_info dispc_cinfo; - int r; - unsigned long long fck; - - fck = dsi_get_dsi1_pll_rate(); - - dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div; - dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div; - - r = dispc_calc_clock_rates(fck, &dispc_cinfo); - if (r) { - DSSERR("Failed to calc dispc clocks\n"); - return r; - } - - r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); - if (r) { - DSSERR("Failed to set dispc clocks\n"); - return r; - } - - return 0; -} - -static int dsi_display_init_dsi(struct omap_dss_device *dssdev) -{ - int r; - - _dsi_print_reset_status(); - - r = dsi_pll_init(dssdev, true, true); - if (r) - goto err0; - - r = dsi_configure_dsi_clocks(dssdev); - if (r) - goto err1; - - dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK); - dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK); - - DSSDBG("PLL OK\n"); - - r = dsi_configure_dispc_clocks(dssdev); - if (r) - goto err2; - - r = dsi_complexio_init(dssdev); - if (r) - goto err2; - - _dsi_print_reset_status(); - - dsi_proto_timings(dssdev); - dsi_set_lp_clk_divisor(dssdev); - - if (1) - _dsi_print_reset_status(); - - r = dsi_proto_config(dssdev); - if (r) - goto err3; - - /* enable interface */ - dsi_vc_enable(0, 1); - dsi_vc_enable(1, 1); - dsi_vc_enable(2, 1); - dsi_vc_enable(3, 1); - dsi_if_enable(1); - dsi_force_tx_stop_mode_io(); - - return 0; -err3: - dsi_complexio_uninit(); -err2: - dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); - dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); -err1: - dsi_pll_uninit(); -err0: - return r; -} - -static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev) -{ - /* disable interface */ - dsi_if_enable(0); - dsi_vc_enable(0, 0); - dsi_vc_enable(1, 0); - dsi_vc_enable(2, 0); - dsi_vc_enable(3, 0); - - dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); - dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); - dsi_complexio_uninit(); - dsi_pll_uninit(); -} - -static int dsi_core_init(void) -{ - /* Autoidle */ - REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0); - - /* ENWAKEUP */ - REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2); - - /* SIDLEMODE smart-idle */ - REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3); - - _dsi_initialize_irq(); - - return 0; -} - -int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) -{ - int r = 0; - - DSSDBG("dsi_display_enable\n"); - - WARN_ON(!dsi_bus_is_locked()); - - mutex_lock(&dsi.lock); - - r = omap_dss_start_device(dssdev); - if (r) { - DSSERR("failed to start device\n"); - goto err0; - } - - enable_clocks(1); - dsi_enable_pll_clock(1); - - r = _dsi_reset(); - if (r) - goto err1; - - dsi_core_init(); - - r = dsi_display_init_dispc(dssdev); - if (r) - goto err1; - - r = dsi_display_init_dsi(dssdev); - if (r) - goto err2; - - mutex_unlock(&dsi.lock); - - return 0; - -err2: - dsi_display_uninit_dispc(dssdev); -err1: - enable_clocks(0); - dsi_enable_pll_clock(0); - omap_dss_stop_device(dssdev); -err0: - mutex_unlock(&dsi.lock); - DSSDBG("dsi_display_enable FAILED\n"); - return r; -} -EXPORT_SYMBOL(omapdss_dsi_display_enable); - -void omapdss_dsi_display_disable(struct omap_dss_device *dssdev) -{ - DSSDBG("dsi_display_disable\n"); - - WARN_ON(!dsi_bus_is_locked()); - - mutex_lock(&dsi.lock); - - dsi_display_uninit_dispc(dssdev); - - dsi_display_uninit_dsi(dssdev); - - enable_clocks(0); - dsi_enable_pll_clock(0); - - omap_dss_stop_device(dssdev); - - mutex_unlock(&dsi.lock); -} -EXPORT_SYMBOL(omapdss_dsi_display_disable); - -int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) -{ - dsi.te_enabled = enable; - return 0; -} -EXPORT_SYMBOL(omapdss_dsi_enable_te); - -void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, - u32 fifo_size, enum omap_burst_size *burst_size, - u32 *fifo_low, u32 *fifo_high) -{ - unsigned burst_size_bytes; - - *burst_size = OMAP_DSS_BURST_16x32; - burst_size_bytes = 16 * 32 / 8; - - *fifo_high = fifo_size - burst_size_bytes; - *fifo_low = fifo_size - burst_size_bytes * 2; -} - -int dsi_init_display(struct omap_dss_device *dssdev) -{ - DSSDBG("DSI init\n"); - - /* XXX these should be figured out dynamically */ - dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | - OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; - - dsi.vc[0].dssdev = dssdev; - dsi.vc[1].dssdev = dssdev; - - return 0; -} - -void dsi_wait_dsi1_pll_active(void) -{ - if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) - DSSERR("DSI1 PLL clock not active\n"); -} - -void dsi_wait_dsi2_pll_active(void) -{ - if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) - DSSERR("DSI2 PLL clock not active\n"); -} - -int dsi_init(struct platform_device *pdev) -{ - u32 rev; - int r; - - spin_lock_init(&dsi.errors_lock); - dsi.errors = 0; - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spin_lock_init(&dsi.irq_stats_lock); - dsi.irq_stats.last_reset = jiffies; -#endif - - init_completion(&dsi.bta_completion); - - mutex_init(&dsi.lock); - sema_init(&dsi.bus_lock, 1); - - dsi.workqueue = create_singlethread_workqueue("dsi"); - if (dsi.workqueue == NULL) - return -ENOMEM; - - INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work, - dsi_framedone_timeout_work_callback); - -#ifdef DSI_CATCH_MISSING_TE - init_timer(&dsi.te_timer); - dsi.te_timer.function = dsi_te_timeout; - dsi.te_timer.data = 0; -#endif - dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS); - if (!dsi.base) { - DSSERR("can't ioremap DSI\n"); - r = -ENOMEM; - goto err1; - } - - dsi.vdds_dsi_reg = dss_get_vdds_dsi(); - if (IS_ERR(dsi.vdds_dsi_reg)) { - DSSERR("can't get VDDS_DSI regulator\n"); - r = PTR_ERR(dsi.vdds_dsi_reg); - goto err2; - } - - enable_clocks(1); - - rev = dsi_read_reg(DSI_REVISION); - printk(KERN_INFO "OMAP DSI rev %d.%d\n", - FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); - - enable_clocks(0); - - return 0; -err2: - iounmap(dsi.base); -err1: - destroy_workqueue(dsi.workqueue); - return r; -} - -void dsi_exit(void) -{ - iounmap(dsi.base); - - destroy_workqueue(dsi.workqueue); - - DSSDBG("omap_dsi_exit\n"); -} - diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c deleted file mode 100644 index 77c3621c917..00000000000 --- a/drivers/video/omap2/dss/dss.c +++ /dev/null @@ -1,641 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/dss.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "DSS" - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/delay.h> -#include <linux/interrupt.h> -#include <linux/seq_file.h> -#include <linux/clk.h> - -#include <plat/display.h> -#include "dss.h" - -#define DSS_BASE 0x48050000 - -#define DSS_SZ_REGS SZ_512 - -struct dss_reg { - u16 idx; -}; - -#define DSS_REG(idx) ((const struct dss_reg) { idx }) - -#define DSS_REVISION DSS_REG(0x0000) -#define DSS_SYSCONFIG DSS_REG(0x0010) -#define DSS_SYSSTATUS DSS_REG(0x0014) -#define DSS_IRQSTATUS DSS_REG(0x0018) -#define DSS_CONTROL DSS_REG(0x0040) -#define DSS_SDI_CONTROL DSS_REG(0x0044) -#define DSS_PLL_CONTROL DSS_REG(0x0048) -#define DSS_SDI_STATUS DSS_REG(0x005C) - -#define REG_GET(idx, start, end) \ - FLD_GET(dss_read_reg(idx), start, end) - -#define REG_FLD_MOD(idx, val, start, end) \ - dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) - -static struct { - void __iomem *base; - - struct clk *dpll4_m4_ck; - - unsigned long cache_req_pck; - unsigned long cache_prate; - struct dss_clock_info cache_dss_cinfo; - struct dispc_clock_info cache_dispc_cinfo; - - enum dss_clk_source dsi_clk_source; - enum dss_clk_source dispc_clk_source; - - u32 ctx[DSS_SZ_REGS / sizeof(u32)]; -} dss; - -static int _omap_dss_wait_reset(void); - -static inline void dss_write_reg(const struct dss_reg idx, u32 val) -{ - __raw_writel(val, dss.base + idx.idx); -} - -static inline u32 dss_read_reg(const struct dss_reg idx) -{ - return __raw_readl(dss.base + idx.idx); -} - -#define SR(reg) \ - dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) -#define RR(reg) \ - dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) - -void dss_save_context(void) -{ - if (cpu_is_omap24xx()) - return; - - SR(SYSCONFIG); - SR(CONTROL); - -#ifdef CONFIG_OMAP2_DSS_SDI - SR(SDI_CONTROL); - SR(PLL_CONTROL); -#endif -} - -void dss_restore_context(void) -{ - if (_omap_dss_wait_reset()) - DSSERR("DSS not coming out of reset after sleep\n"); - - RR(SYSCONFIG); - RR(CONTROL); - -#ifdef CONFIG_OMAP2_DSS_SDI - RR(SDI_CONTROL); - RR(PLL_CONTROL); -#endif -} - -#undef SR -#undef RR - -void dss_sdi_init(u8 datapairs) -{ - u32 l; - - BUG_ON(datapairs > 3 || datapairs < 1); - - l = dss_read_reg(DSS_SDI_CONTROL); - l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ - l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ - l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ - dss_write_reg(DSS_SDI_CONTROL, l); - - l = dss_read_reg(DSS_PLL_CONTROL); - l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ - l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ - l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ - dss_write_reg(DSS_PLL_CONTROL, l); -} - -int dss_sdi_enable(void) -{ - unsigned long timeout; - - dispc_pck_free_enable(1); - - /* Reset SDI PLL */ - REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ - udelay(1); /* wait 2x PCLK */ - - /* Lock SDI PLL */ - REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ - - /* Waiting for PLL lock request to complete */ - timeout = jiffies + msecs_to_jiffies(500); - while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { - if (time_after_eq(jiffies, timeout)) { - DSSERR("PLL lock request timed out\n"); - goto err1; - } - } - - /* Clearing PLL_GO bit */ - REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); - - /* Waiting for PLL to lock */ - timeout = jiffies + msecs_to_jiffies(500); - while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { - if (time_after_eq(jiffies, timeout)) { - DSSERR("PLL lock timed out\n"); - goto err1; - } - } - - dispc_lcd_enable_signal(1); - - /* Waiting for SDI reset to complete */ - timeout = jiffies + msecs_to_jiffies(500); - while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { - if (time_after_eq(jiffies, timeout)) { - DSSERR("SDI reset timed out\n"); - goto err2; - } - } - - return 0; - - err2: - dispc_lcd_enable_signal(0); - err1: - /* Reset SDI PLL */ - REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ - - dispc_pck_free_enable(0); - - return -ETIMEDOUT; -} - -void dss_sdi_disable(void) -{ - dispc_lcd_enable_signal(0); - - dispc_pck_free_enable(0); - - /* Reset SDI PLL */ - REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ -} - -void dss_dump_clocks(struct seq_file *s) -{ - unsigned long dpll4_ck_rate; - unsigned long dpll4_m4_ck_rate; - - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - - dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); - dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); - - seq_printf(s, "- DSS -\n"); - - seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); - - if (cpu_is_omap3630()) - seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", - dpll4_ck_rate, - dpll4_ck_rate / dpll4_m4_ck_rate, - dss_clk_get_rate(DSS_CLK_FCK1)); - else - seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", - dpll4_ck_rate, - dpll4_ck_rate / dpll4_m4_ck_rate, - dss_clk_get_rate(DSS_CLK_FCK1)); - - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -} - -void dss_dump_regs(struct seq_file *s) -{ -#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) - - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - - DUMPREG(DSS_REVISION); - DUMPREG(DSS_SYSCONFIG); - DUMPREG(DSS_SYSSTATUS); - DUMPREG(DSS_IRQSTATUS); - DUMPREG(DSS_CONTROL); - DUMPREG(DSS_SDI_CONTROL); - DUMPREG(DSS_PLL_CONTROL); - DUMPREG(DSS_SDI_STATUS); - - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -#undef DUMPREG -} - -void dss_select_dispc_clk_source(enum dss_clk_source clk_src) -{ - int b; - - BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK && - clk_src != DSS_SRC_DSS1_ALWON_FCLK); - - b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; - - if (clk_src == DSS_SRC_DSI1_PLL_FCLK) - dsi_wait_dsi1_pll_active(); - - REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ - - dss.dispc_clk_source = clk_src; -} - -void dss_select_dsi_clk_source(enum dss_clk_source clk_src) -{ - int b; - - BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK && - clk_src != DSS_SRC_DSS1_ALWON_FCLK); - - b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; - - if (clk_src == DSS_SRC_DSI2_PLL_FCLK) - dsi_wait_dsi2_pll_active(); - - REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ - - dss.dsi_clk_source = clk_src; -} - -enum dss_clk_source dss_get_dispc_clk_source(void) -{ - return dss.dispc_clk_source; -} - -enum dss_clk_source dss_get_dsi_clk_source(void) -{ - return dss.dsi_clk_source; -} - -/* calculate clock rates using dividers in cinfo */ -int dss_calc_clock_rates(struct dss_clock_info *cinfo) -{ - unsigned long prate; - - if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) || - cinfo->fck_div == 0) - return -EINVAL; - - prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); - - cinfo->fck = prate / cinfo->fck_div; - - return 0; -} - -int dss_set_clock_div(struct dss_clock_info *cinfo) -{ - unsigned long prate; - int r; - - if (cpu_is_omap34xx()) { - prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); - DSSDBG("dpll4_m4 = %ld\n", prate); - - r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); - if (r) - return r; - } - - DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); - - return 0; -} - -int dss_get_clock_div(struct dss_clock_info *cinfo) -{ - cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1); - - if (cpu_is_omap34xx()) { - unsigned long prate; - prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); - if (cpu_is_omap3630()) - cinfo->fck_div = prate / (cinfo->fck); - else - cinfo->fck_div = prate / (cinfo->fck / 2); - } else { - cinfo->fck_div = 0; - } - - return 0; -} - -unsigned long dss_get_dpll4_rate(void) -{ - if (cpu_is_omap34xx()) - return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); - else - return 0; -} - -int dss_calc_clock_div(bool is_tft, unsigned long req_pck, - struct dss_clock_info *dss_cinfo, - struct dispc_clock_info *dispc_cinfo) -{ - unsigned long prate; - struct dss_clock_info best_dss; - struct dispc_clock_info best_dispc; - - unsigned long fck; - - u16 fck_div; - - int match = 0; - int min_fck_per_pck; - - prate = dss_get_dpll4_rate(); - - fck = dss_clk_get_rate(DSS_CLK_FCK1); - if (req_pck == dss.cache_req_pck && - ((cpu_is_omap34xx() && prate == dss.cache_prate) || - dss.cache_dss_cinfo.fck == fck)) { - DSSDBG("dispc clock info found from cache.\n"); - *dss_cinfo = dss.cache_dss_cinfo; - *dispc_cinfo = dss.cache_dispc_cinfo; - return 0; - } - - min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; - - if (min_fck_per_pck && - req_pck * min_fck_per_pck > DISPC_MAX_FCK) { - DSSERR("Requested pixel clock not possible with the current " - "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " - "the constraint off.\n"); - min_fck_per_pck = 0; - } - -retry: - memset(&best_dss, 0, sizeof(best_dss)); - memset(&best_dispc, 0, sizeof(best_dispc)); - - if (cpu_is_omap24xx()) { - struct dispc_clock_info cur_dispc; - /* XXX can we change the clock on omap2? */ - fck = dss_clk_get_rate(DSS_CLK_FCK1); - fck_div = 1; - - dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); - match = 1; - - best_dss.fck = fck; - best_dss.fck_div = fck_div; - - best_dispc = cur_dispc; - - goto found; - } else if (cpu_is_omap34xx()) { - for (fck_div = (cpu_is_omap3630() ? 32 : 16); - fck_div > 0; --fck_div) { - struct dispc_clock_info cur_dispc; - - if (cpu_is_omap3630()) - fck = prate / fck_div; - else - fck = prate / fck_div * 2; - - if (fck > DISPC_MAX_FCK) - continue; - - if (min_fck_per_pck && - fck < req_pck * min_fck_per_pck) - continue; - - match = 1; - - dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); - - if (abs(cur_dispc.pck - req_pck) < - abs(best_dispc.pck - req_pck)) { - - best_dss.fck = fck; - best_dss.fck_div = fck_div; - - best_dispc = cur_dispc; - - if (cur_dispc.pck == req_pck) - goto found; - } - } - } else { - BUG(); - } - -found: - if (!match) { - if (min_fck_per_pck) { - DSSERR("Could not find suitable clock settings.\n" - "Turning FCK/PCK constraint off and" - "trying again.\n"); - min_fck_per_pck = 0; - goto retry; - } - - DSSERR("Could not find suitable clock settings.\n"); - - return -EINVAL; - } - - if (dss_cinfo) - *dss_cinfo = best_dss; - if (dispc_cinfo) - *dispc_cinfo = best_dispc; - - dss.cache_req_pck = req_pck; - dss.cache_prate = prate; - dss.cache_dss_cinfo = best_dss; - dss.cache_dispc_cinfo = best_dispc; - - return 0; -} - - - -static irqreturn_t dss_irq_handler_omap2(int irq, void *arg) -{ - dispc_irq_handler(); - - return IRQ_HANDLED; -} - -static irqreturn_t dss_irq_handler_omap3(int irq, void *arg) -{ - u32 irqstatus; - - irqstatus = dss_read_reg(DSS_IRQSTATUS); - - if (irqstatus & (1<<0)) /* DISPC_IRQ */ - dispc_irq_handler(); -#ifdef CONFIG_OMAP2_DSS_DSI - if (irqstatus & (1<<1)) /* DSI_IRQ */ - dsi_irq_handler(); -#endif - - return IRQ_HANDLED; -} - -static int _omap_dss_wait_reset(void) -{ - int t = 0; - - while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) { - if (++t > 1000) { - DSSERR("soft reset failed\n"); - return -ENODEV; - } - udelay(1); - } - - return 0; -} - -static int _omap_dss_reset(void) -{ - /* Soft reset */ - REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1); - return _omap_dss_wait_reset(); -} - -void dss_set_venc_output(enum omap_dss_venc_type type) -{ - int l = 0; - - if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) - l = 0; - else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) - l = 1; - else - BUG(); - - /* venc out selection. 0 = comp, 1 = svideo */ - REG_FLD_MOD(DSS_CONTROL, l, 6, 6); -} - -void dss_set_dac_pwrdn_bgz(bool enable) -{ - REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ -} - -int dss_init(bool skip_init) -{ - int r; - u32 rev; - - dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); - if (!dss.base) { - DSSERR("can't ioremap DSS\n"); - r = -ENOMEM; - goto fail0; - } - - if (!skip_init) { - /* disable LCD and DIGIT output. This seems to fix the synclost - * problem that we get, if the bootloader starts the DSS and - * the kernel resets it */ - omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); - - /* We need to wait here a bit, otherwise we sometimes start to - * get synclost errors, and after that only power cycle will - * restore DSS functionality. I have no idea why this happens. - * And we have to wait _before_ resetting the DSS, but after - * enabling clocks. - */ - msleep(50); - - _omap_dss_reset(); - } - - /* autoidle */ - REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); - - /* Select DPLL */ - REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); - -#ifdef CONFIG_OMAP2_DSS_VENC - REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ - REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ - REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ -#endif - - r = request_irq(INT_24XX_DSS_IRQ, - cpu_is_omap24xx() - ? dss_irq_handler_omap2 - : dss_irq_handler_omap3, - 0, "OMAP DSS", NULL); - - if (r < 0) { - DSSERR("omap2 dss: request_irq failed\n"); - goto fail1; - } - - if (cpu_is_omap34xx()) { - dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); - if (IS_ERR(dss.dpll4_m4_ck)) { - DSSERR("Failed to get dpll4_m4_ck\n"); - r = PTR_ERR(dss.dpll4_m4_ck); - goto fail2; - } - } - - dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK; - dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; - - dss_save_context(); - - rev = dss_read_reg(DSS_REVISION); - printk(KERN_INFO "OMAP DSS rev %d.%d\n", - FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); - - return 0; - -fail2: - free_irq(INT_24XX_DSS_IRQ, NULL); -fail1: - iounmap(dss.base); -fail0: - return r; -} - -void dss_exit(void) -{ - if (cpu_is_omap34xx()) - clk_put(dss.dpll4_m4_ck); - - free_irq(INT_24XX_DSS_IRQ, NULL); - - iounmap(dss.base); -} - diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h deleted file mode 100644 index b394951120a..00000000000 --- a/drivers/video/omap2/dss/dss.h +++ /dev/null @@ -1,461 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/dss.h - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __OMAP2_DSS_H -#define __OMAP2_DSS_H - -#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT -#define DEBUG -#endif - -#ifdef DEBUG -extern unsigned int dss_debug; -#ifdef DSS_SUBSYS_NAME -#define DSSDBG(format, ...) \ - if (dss_debug) \ - printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \ - ## __VA_ARGS__) -#else -#define DSSDBG(format, ...) \ - if (dss_debug) \ - printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__) -#endif - -#ifdef DSS_SUBSYS_NAME -#define DSSDBGF(format, ...) \ - if (dss_debug) \ - printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \ - ": %s(" format ")\n", \ - __func__, \ - ## __VA_ARGS__) -#else -#define DSSDBGF(format, ...) \ - if (dss_debug) \ - printk(KERN_DEBUG "omapdss: " \ - ": %s(" format ")\n", \ - __func__, \ - ## __VA_ARGS__) -#endif - -#else /* DEBUG */ -#define DSSDBG(format, ...) -#define DSSDBGF(format, ...) -#endif - - -#ifdef DSS_SUBSYS_NAME -#define DSSERR(format, ...) \ - printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \ - ## __VA_ARGS__) -#else -#define DSSERR(format, ...) \ - printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__) -#endif - -#ifdef DSS_SUBSYS_NAME -#define DSSINFO(format, ...) \ - printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \ - ## __VA_ARGS__) -#else -#define DSSINFO(format, ...) \ - printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__) -#endif - -#ifdef DSS_SUBSYS_NAME -#define DSSWARN(format, ...) \ - printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \ - ## __VA_ARGS__) -#else -#define DSSWARN(format, ...) \ - printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__) -#endif - -/* OMAP TRM gives bitfields as start:end, where start is the higher bit - number. For example 7:0 */ -#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) -#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) -#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) -#define FLD_MOD(orig, val, start, end) \ - (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) - -#define DISPC_MAX_FCK 173000000 - -enum omap_burst_size { - OMAP_DSS_BURST_4x32 = 0, - OMAP_DSS_BURST_8x32 = 1, - OMAP_DSS_BURST_16x32 = 2, -}; - -enum omap_parallel_interface_mode { - OMAP_DSS_PARALLELMODE_BYPASS, /* MIPI DPI */ - OMAP_DSS_PARALLELMODE_RFBI, /* MIPI DBI */ - OMAP_DSS_PARALLELMODE_DSI, -}; - -enum dss_clock { - DSS_CLK_ICK = 1 << 0, - DSS_CLK_FCK1 = 1 << 1, - DSS_CLK_FCK2 = 1 << 2, - DSS_CLK_54M = 1 << 3, - DSS_CLK_96M = 1 << 4, -}; - -enum dss_clk_source { - DSS_SRC_DSI1_PLL_FCLK, - DSS_SRC_DSI2_PLL_FCLK, - DSS_SRC_DSS1_ALWON_FCLK, -}; - -struct dss_clock_info { - /* rates that we get with dividers below */ - unsigned long fck; - - /* dividers */ - u16 fck_div; -}; - -struct dispc_clock_info { - /* rates that we get with dividers below */ - unsigned long lck; - unsigned long pck; - - /* dividers */ - u16 lck_div; - u16 pck_div; -}; - -struct dsi_clock_info { - /* rates that we get with dividers below */ - unsigned long fint; - unsigned long clkin4ddr; - unsigned long clkin; - unsigned long dsi1_pll_fclk; - unsigned long dsi2_pll_fclk; - - unsigned long lp_clk; - - /* dividers */ - u16 regn; - u16 regm; - u16 regm3; - u16 regm4; - - u16 lp_clk_div; - - u8 highfreq; - bool use_dss2_fck; -}; - -struct seq_file; -struct platform_device; - -/* core */ -void dss_clk_enable(enum dss_clock clks); -void dss_clk_disable(enum dss_clock clks); -unsigned long dss_clk_get_rate(enum dss_clock clk); -int dss_need_ctx_restore(void); -void dss_dump_clocks(struct seq_file *s); -struct bus_type *dss_get_bus(void); -struct regulator *dss_get_vdds_dsi(void); -struct regulator *dss_get_vdds_sdi(void); -struct regulator *dss_get_vdda_dac(void); - -/* display */ -int dss_suspend_all_devices(void); -int dss_resume_all_devices(void); -void dss_disable_all_devices(void); - -void dss_init_device(struct platform_device *pdev, - struct omap_dss_device *dssdev); -void dss_uninit_device(struct platform_device *pdev, - struct omap_dss_device *dssdev); -bool dss_use_replication(struct omap_dss_device *dssdev, - enum omap_color_mode mode); -void default_get_overlay_fifo_thresholds(enum omap_plane plane, - u32 fifo_size, enum omap_burst_size *burst_size, - u32 *fifo_low, u32 *fifo_high); - -/* manager */ -int dss_init_overlay_managers(struct platform_device *pdev); -void dss_uninit_overlay_managers(struct platform_device *pdev); -int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl); -void dss_setup_partial_planes(struct omap_dss_device *dssdev, - u16 *x, u16 *y, u16 *w, u16 *h, - bool enlarge_update_area); -void dss_start_update(struct omap_dss_device *dssdev); - -/* overlay */ -void dss_init_overlays(struct platform_device *pdev); -void dss_uninit_overlays(struct platform_device *pdev); -int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev); -void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr); -#ifdef L4_EXAMPLE -void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr); -#endif -void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); - -/* DSS */ -int dss_init(bool skip_init); -void dss_exit(void); - -void dss_save_context(void); -void dss_restore_context(void); - -void dss_dump_regs(struct seq_file *s); - -void dss_sdi_init(u8 datapairs); -int dss_sdi_enable(void); -void dss_sdi_disable(void); - -void dss_select_dispc_clk_source(enum dss_clk_source clk_src); -void dss_select_dsi_clk_source(enum dss_clk_source clk_src); -enum dss_clk_source dss_get_dispc_clk_source(void); -enum dss_clk_source dss_get_dsi_clk_source(void); - -void dss_set_venc_output(enum omap_dss_venc_type type); -void dss_set_dac_pwrdn_bgz(bool enable); - -unsigned long dss_get_dpll4_rate(void); -int dss_calc_clock_rates(struct dss_clock_info *cinfo); -int dss_set_clock_div(struct dss_clock_info *cinfo); -int dss_get_clock_div(struct dss_clock_info *cinfo); -int dss_calc_clock_div(bool is_tft, unsigned long req_pck, - struct dss_clock_info *dss_cinfo, - struct dispc_clock_info *dispc_cinfo); - -/* SDI */ -#ifdef CONFIG_OMAP2_DSS_SDI -int sdi_init(bool skip_init); -void sdi_exit(void); -int sdi_init_display(struct omap_dss_device *display); -#else -static inline int sdi_init(bool skip_init) -{ - return 0; -} -static inline void sdi_exit(void) -{ -} -#endif - -/* DSI */ -#ifdef CONFIG_OMAP2_DSS_DSI -int dsi_init(struct platform_device *pdev); -void dsi_exit(void); - -void dsi_dump_clocks(struct seq_file *s); -void dsi_dump_irqs(struct seq_file *s); -void dsi_dump_regs(struct seq_file *s); - -void dsi_save_context(void); -void dsi_restore_context(void); - -int dsi_init_display(struct omap_dss_device *display); -void dsi_irq_handler(void); -unsigned long dsi_get_dsi1_pll_rate(void); -int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo); -int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, - struct dsi_clock_info *cinfo, - struct dispc_clock_info *dispc_cinfo); -int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk, - bool enable_hsdiv); -void dsi_pll_uninit(void); -void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, - u32 fifo_size, enum omap_burst_size *burst_size, - u32 *fifo_low, u32 *fifo_high); -void dsi_wait_dsi1_pll_active(void); -void dsi_wait_dsi2_pll_active(void); -#else -static inline int dsi_init(struct platform_device *pdev) -{ - return 0; -} -static inline void dsi_exit(void) -{ -} -static inline void dsi_wait_dsi1_pll_active(void) -{ -} -static inline void dsi_wait_dsi2_pll_active(void) -{ -} -#endif - -/* DPI */ -#ifdef CONFIG_OMAP2_DSS_DPI -int dpi_init(struct platform_device *pdev); -void dpi_exit(void); -int dpi_init_display(struct omap_dss_device *dssdev); -#else -static inline int dpi_init(struct platform_device *pdev) -{ - return 0; -} -static inline void dpi_exit(void) -{ -} -#endif - -/* DISPC */ -int dispc_init(void); -void dispc_exit(void); -void dispc_dump_clocks(struct seq_file *s); -void dispc_dump_irqs(struct seq_file *s); -void dispc_dump_regs(struct seq_file *s); -void dispc_irq_handler(void); -void dispc_fake_vsync_irq(void); - -void dispc_save_context(void); -void dispc_restore_context(void); - -void dispc_enable_sidle(void); -void dispc_disable_sidle(void); - -void dispc_lcd_enable_signal_polarity(bool act_high); -void dispc_lcd_enable_signal(bool enable); -void dispc_pck_free_enable(bool enable); -void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable); - -void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height); -void dispc_set_digit_size(u16 width, u16 height); -u32 dispc_get_plane_fifo_size(enum omap_plane plane); -void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high); -void dispc_enable_fifomerge(bool enable); -void dispc_set_burst_size(enum omap_plane plane, - enum omap_burst_size burst_size); - -void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr); -void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr); -void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y); -void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height); -void dispc_set_channel_out(enum omap_plane plane, - enum omap_channel channel_out); - -int dispc_setup_plane(enum omap_plane plane, - u32 paddr, u16 screen_width, - u16 pos_x, u16 pos_y, - u16 width, u16 height, - u16 out_width, u16 out_height, - enum omap_color_mode color_mode, - bool ilace, - enum omap_dss_rotation_type rotation_type, - u8 rotation, bool mirror, - u8 global_alpha, u8 pre_mult_alpha, - enum omap_channel channel); - -bool dispc_go_busy(enum omap_channel channel); -void dispc_go(enum omap_channel channel); -void dispc_enable_channel(enum omap_channel channel, bool enable); -bool dispc_is_channel_enabled(enum omap_channel channel); -int dispc_enable_plane(enum omap_plane plane, bool enable); -void dispc_enable_replication(enum omap_plane plane, bool enable); - -void dispc_set_parallel_interface_mode(enum omap_channel channel, - enum omap_parallel_interface_mode mode); -void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines); -void dispc_set_lcd_display_type(enum omap_channel channel, - enum omap_lcd_display_type type); -void dispc_set_loadmode(enum omap_dss_load_mode mode); - -void dispc_set_default_color(enum omap_channel channel, u32 color); -u32 dispc_get_default_color(enum omap_channel channel); -void dispc_set_trans_key(enum omap_channel ch, - enum omap_dss_trans_key_type type, - u32 trans_key); -void dispc_get_trans_key(enum omap_channel ch, - enum omap_dss_trans_key_type *type, - u32 *trans_key); -void dispc_enable_trans_key(enum omap_channel ch, bool enable); -void dispc_enable_alpha_blending(enum omap_channel ch, bool enable); -bool dispc_trans_key_enabled(enum omap_channel ch); -bool dispc_alpha_blending_enabled(enum omap_channel ch); - -bool dispc_lcd_timings_ok(struct omap_video_timings *timings); -void dispc_set_lcd_timings(enum omap_channel channel, - struct omap_video_timings *timings); -unsigned long dispc_fclk_rate(void); -unsigned long dispc_lclk_rate(enum omap_channel channel); -unsigned long dispc_pclk_rate(enum omap_channel channel); -void dispc_set_pol_freq(enum omap_channel channel, - enum omap_panel_config config, u8 acbi, u8 acb); -void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck, - struct dispc_clock_info *cinfo); -int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, - struct dispc_clock_info *cinfo); -int dispc_set_clock_div(enum omap_channel channel, - struct dispc_clock_info *cinfo); -int dispc_get_clock_div(enum omap_channel channel, - struct dispc_clock_info *cinfo); - - -/* VENC */ -#ifdef CONFIG_OMAP2_DSS_VENC -int venc_init(struct platform_device *pdev); -void venc_exit(void); -void venc_dump_regs(struct seq_file *s); -int venc_init_display(struct omap_dss_device *display); -#else -static inline int venc_init(struct platform_device *pdev) -{ - return 0; -} -static inline void venc_exit(void) -{ -} -#endif - -/* RFBI */ -#ifdef CONFIG_OMAP2_DSS_RFBI -int rfbi_init(void); -void rfbi_exit(void); -void rfbi_dump_regs(struct seq_file *s); - -int rfbi_configure(int rfbi_module, int bpp, int lines); -void rfbi_enable_rfbi(bool enable); -void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width, - u16 height, void (callback)(void *data), void *data); -void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t); -unsigned long rfbi_get_max_tx_rate(void); -int rfbi_init_display(struct omap_dss_device *display); -#else -static inline int rfbi_init(void) -{ - return 0; -} -static inline void rfbi_exit(void) -{ -} -#endif - - -#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS -static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr) -{ - int b; - for (b = 0; b < 32; ++b) { - if (irqstatus & (1 << b)) - irq_arr[b]++; - } -} -#endif - -#endif diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c deleted file mode 100644 index cf3ef696e14..00000000000 --- a/drivers/video/omap2/dss/dss_features.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/dss_features.c - * - * Copyright (C) 2010 Texas Instruments - * Author: Archit Taneja <archit@ti.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/err.h> -#include <linux/slab.h> - -#include <plat/display.h> -#include <plat/cpu.h> - -#include "dss_features.h" - -/* Defines a generic omap register field */ -struct dss_reg_field { - enum dss_feat_reg_field id; - u8 start, end; -}; - -struct omap_dss_features { - const struct dss_reg_field *reg_fields; - const int num_reg_fields; - - const u32 has_feature; - - const int num_mgrs; - const int num_ovls; - const enum omap_display_type *supported_displays; - const enum omap_color_mode *supported_color_modes; -}; - -/* This struct is assigned to one of the below during initialization */ -static struct omap_dss_features *omap_current_dss_features; - -static const struct dss_reg_field omap2_dss_reg_fields[] = { - { FEAT_REG_FIRHINC, 11, 0 }, - { FEAT_REG_FIRVINC, 27, 16 }, - { FEAT_REG_FIFOLOWTHRESHOLD, 8, 0 }, - { FEAT_REG_FIFOHIGHTHRESHOLD, 24, 16 }, - { FEAT_REG_FIFOSIZE, 8, 0 }, -}; - -static const struct dss_reg_field omap3_dss_reg_fields[] = { - { FEAT_REG_FIRHINC, 12, 0 }, - { FEAT_REG_FIRVINC, 28, 16 }, - { FEAT_REG_FIFOLOWTHRESHOLD, 11, 0 }, - { FEAT_REG_FIFOHIGHTHRESHOLD, 27, 16 }, - { FEAT_REG_FIFOSIZE, 10, 0 }, -}; - -static const enum omap_display_type omap2_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_VENC, -}; - -static const enum omap_display_type omap3_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_VENC, -}; - -static const enum omap_display_type omap4_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_VENC, - - /* OMAP_DSS_CHANNEL_LCD2 */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_DSI, -}; - -static const enum omap_color_mode omap2_dss_supported_color_modes[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | - OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 | - OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | - OMAP_DSS_COLOR_UYVY, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | - OMAP_DSS_COLOR_UYVY, -}; - -static const enum omap_color_mode omap3_dss_supported_color_modes[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | - OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P | - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 | - OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | - OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, -}; - -/* OMAP2 DSS Features */ -static struct omap_dss_features omap2_dss_features = { - .reg_fields = omap2_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields), - - .has_feature = - FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL | - FEAT_PCKFREEENABLE | FEAT_FUNCGATED, - - .num_mgrs = 2, - .num_ovls = 3, - .supported_displays = omap2_dss_supported_displays, - .supported_color_modes = omap2_dss_supported_color_modes, -}; - -/* OMAP3 DSS Features */ -static struct omap_dss_features omap3430_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), - - .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | - FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | - FEAT_FUNCGATED, - - .num_mgrs = 2, - .num_ovls = 3, - .supported_displays = omap3_dss_supported_displays, - .supported_color_modes = omap3_dss_supported_color_modes, -}; - -static struct omap_dss_features omap3630_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), - - .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | - FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | - FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED, - - .num_mgrs = 2, - .num_ovls = 3, - .supported_displays = omap3_dss_supported_displays, - .supported_color_modes = omap3_dss_supported_color_modes, -}; - -/* OMAP4 DSS Features */ -static struct omap_dss_features omap4_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), - - .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA | - FEAT_MGR_LCD2, - - .num_mgrs = 3, - .num_ovls = 3, - .supported_displays = omap4_dss_supported_displays, - .supported_color_modes = omap3_dss_supported_color_modes, -}; - -/* Functions returning values related to a DSS feature */ -int dss_feat_get_num_mgrs(void) -{ - return omap_current_dss_features->num_mgrs; -} - -int dss_feat_get_num_ovls(void) -{ - return omap_current_dss_features->num_ovls; -} - -enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel) -{ - return omap_current_dss_features->supported_displays[channel]; -} - -enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane) -{ - return omap_current_dss_features->supported_color_modes[plane]; -} - -bool dss_feat_color_mode_supported(enum omap_plane plane, - enum omap_color_mode color_mode) -{ - return omap_current_dss_features->supported_color_modes[plane] & - color_mode; -} - -/* DSS has_feature check */ -bool dss_has_feature(enum dss_feat_id id) -{ - return omap_current_dss_features->has_feature & id; -} - -void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end) -{ - if (id >= omap_current_dss_features->num_reg_fields) - BUG(); - - *start = omap_current_dss_features->reg_fields[id].start; - *end = omap_current_dss_features->reg_fields[id].end; -} - -void dss_features_init(void) -{ - if (cpu_is_omap24xx()) - omap_current_dss_features = &omap2_dss_features; - else if (cpu_is_omap3630()) - omap_current_dss_features = &omap3630_dss_features; - else if (cpu_is_omap34xx()) - omap_current_dss_features = &omap3430_dss_features; - else - omap_current_dss_features = &omap4_dss_features; -} diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h deleted file mode 100644 index b9c70be9258..00000000000 --- a/drivers/video/omap2/dss/dss_features.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/dss_features.h - * - * Copyright (C) 2010 Texas Instruments - * Author: Archit Taneja <archit@ti.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __OMAP2_DSS_FEATURES_H -#define __OMAP2_DSS_FEATURES_H - -#define MAX_DSS_MANAGERS 3 -#define MAX_DSS_OVERLAYS 3 - -/* DSS has feature id */ -enum dss_feat_id { - FEAT_GLOBAL_ALPHA = 1 << 0, - FEAT_GLOBAL_ALPHA_VID1 = 1 << 1, - FEAT_PRE_MULT_ALPHA = 1 << 2, - FEAT_LCDENABLEPOL = 1 << 3, - FEAT_LCDENABLESIGNAL = 1 << 4, - FEAT_PCKFREEENABLE = 1 << 5, - FEAT_FUNCGATED = 1 << 6, - FEAT_MGR_LCD2 = 1 << 7, -}; - -/* DSS register field id */ -enum dss_feat_reg_field { - FEAT_REG_FIRHINC, - FEAT_REG_FIRVINC, - FEAT_REG_FIFOHIGHTHRESHOLD, - FEAT_REG_FIFOLOWTHRESHOLD, - FEAT_REG_FIFOSIZE, -}; - -/* DSS Feature Functions */ -int dss_feat_get_num_mgrs(void); -int dss_feat_get_num_ovls(void); -enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); -enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); -bool dss_feat_color_mode_supported(enum omap_plane plane, - enum omap_color_mode color_mode); - -bool dss_has_feature(enum dss_feat_id id); -void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); -void dss_features_init(void); -#endif diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c deleted file mode 100644 index 172d4e69730..00000000000 --- a/drivers/video/omap2/dss/manager.c +++ /dev/null @@ -1,1606 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/manager.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "MANAGER" - -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/spinlock.h> -#include <linux/jiffies.h> - -#include <plat/display.h> -#include <plat/cpu.h> - -#include "dss.h" -#include "dss_features.h" - -static int num_managers; -static struct list_head manager_list; - -static ssize_t manager_name_show(struct omap_overlay_manager *mgr, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%s\n", mgr->name); -} - -static ssize_t manager_display_show(struct omap_overlay_manager *mgr, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%s\n", - mgr->device ? mgr->device->name : "<none>"); -} - -static ssize_t manager_display_store(struct omap_overlay_manager *mgr, - const char *buf, size_t size) -{ - int r = 0; - size_t len = size; - struct omap_dss_device *dssdev = NULL; - - int match(struct omap_dss_device *dssdev, void *data) - { - const char *str = data; - return sysfs_streq(dssdev->name, str); - } - - if (buf[size-1] == '\n') - --len; - - if (len > 0) - dssdev = omap_dss_find_device((void *)buf, match); - - if (len > 0 && dssdev == NULL) - return -EINVAL; - - if (dssdev) - DSSDBG("display %s found\n", dssdev->name); - - if (mgr->device) { - r = mgr->unset_device(mgr); - if (r) { - DSSERR("failed to unset display\n"); - goto put_device; - } - } - - if (dssdev) { - r = mgr->set_device(mgr, dssdev); - if (r) { - DSSERR("failed to set manager\n"); - goto put_device; - } - - r = mgr->apply(mgr); - if (r) { - DSSERR("failed to apply dispc config\n"); - goto put_device; - } - } - -put_device: - if (dssdev) - omap_dss_put_device(dssdev); - - return r ? r : size; -} - -static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr, - char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.default_color); -} - -static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr, - const char *buf, size_t size) -{ - struct omap_overlay_manager_info info; - u32 color; - int r; - - if (sscanf(buf, "%d", &color) != 1) - return -EINVAL; - - mgr->get_manager_info(mgr, &info); - - info.default_color = color; - - r = mgr->set_manager_info(mgr, &info); - if (r) - return r; - - r = mgr->apply(mgr); - if (r) - return r; - - return size; -} - -static const char *trans_key_type_str[] = { - "gfx-destination", - "video-source", -}; - -static ssize_t manager_trans_key_type_show(struct omap_overlay_manager *mgr, - char *buf) -{ - enum omap_dss_trans_key_type key_type; - - key_type = mgr->info.trans_key_type; - BUG_ON(key_type >= ARRAY_SIZE(trans_key_type_str)); - - return snprintf(buf, PAGE_SIZE, "%s\n", trans_key_type_str[key_type]); -} - -static ssize_t manager_trans_key_type_store(struct omap_overlay_manager *mgr, - const char *buf, size_t size) -{ - enum omap_dss_trans_key_type key_type; - struct omap_overlay_manager_info info; - int r; - - for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST; - key_type < ARRAY_SIZE(trans_key_type_str); key_type++) { - if (sysfs_streq(buf, trans_key_type_str[key_type])) - break; - } - - if (key_type == ARRAY_SIZE(trans_key_type_str)) - return -EINVAL; - - mgr->get_manager_info(mgr, &info); - - info.trans_key_type = key_type; - - r = mgr->set_manager_info(mgr, &info); - if (r) - return r; - - r = mgr->apply(mgr); - if (r) - return r; - - return size; -} - -static ssize_t manager_trans_key_value_show(struct omap_overlay_manager *mgr, - char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.trans_key); -} - -static ssize_t manager_trans_key_value_store(struct omap_overlay_manager *mgr, - const char *buf, size_t size) -{ - struct omap_overlay_manager_info info; - u32 key_value; - int r; - - if (sscanf(buf, "%d", &key_value) != 1) - return -EINVAL; - - mgr->get_manager_info(mgr, &info); - - info.trans_key = key_value; - - r = mgr->set_manager_info(mgr, &info); - if (r) - return r; - - r = mgr->apply(mgr); - if (r) - return r; - - return size; -} - -static ssize_t manager_trans_key_enabled_show(struct omap_overlay_manager *mgr, - char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.trans_enabled); -} - -static ssize_t manager_trans_key_enabled_store(struct omap_overlay_manager *mgr, - const char *buf, size_t size) -{ - struct omap_overlay_manager_info info; - int enable; - int r; - - if (sscanf(buf, "%d", &enable) != 1) - return -EINVAL; - - mgr->get_manager_info(mgr, &info); - - info.trans_enabled = enable ? true : false; - - r = mgr->set_manager_info(mgr, &info); - if (r) - return r; - - r = mgr->apply(mgr); - if (r) - return r; - - return size; -} - -static ssize_t manager_alpha_blending_enabled_show( - struct omap_overlay_manager *mgr, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.alpha_enabled); -} - -static ssize_t manager_alpha_blending_enabled_store( - struct omap_overlay_manager *mgr, - const char *buf, size_t size) -{ - struct omap_overlay_manager_info info; - int enable; - int r; - - if (sscanf(buf, "%d", &enable) != 1) - return -EINVAL; - - mgr->get_manager_info(mgr, &info); - - info.alpha_enabled = enable ? true : false; - - r = mgr->set_manager_info(mgr, &info); - if (r) - return r; - - r = mgr->apply(mgr); - if (r) - return r; - - return size; -} - -struct manager_attribute { - struct attribute attr; - ssize_t (*show)(struct omap_overlay_manager *, char *); - ssize_t (*store)(struct omap_overlay_manager *, const char *, size_t); -}; - -#define MANAGER_ATTR(_name, _mode, _show, _store) \ - struct manager_attribute manager_attr_##_name = \ - __ATTR(_name, _mode, _show, _store) - -static MANAGER_ATTR(name, S_IRUGO, manager_name_show, NULL); -static MANAGER_ATTR(display, S_IRUGO|S_IWUSR, - manager_display_show, manager_display_store); -static MANAGER_ATTR(default_color, S_IRUGO|S_IWUSR, - manager_default_color_show, manager_default_color_store); -static MANAGER_ATTR(trans_key_type, S_IRUGO|S_IWUSR, - manager_trans_key_type_show, manager_trans_key_type_store); -static MANAGER_ATTR(trans_key_value, S_IRUGO|S_IWUSR, - manager_trans_key_value_show, manager_trans_key_value_store); -static MANAGER_ATTR(trans_key_enabled, S_IRUGO|S_IWUSR, - manager_trans_key_enabled_show, - manager_trans_key_enabled_store); -static MANAGER_ATTR(alpha_blending_enabled, S_IRUGO|S_IWUSR, - manager_alpha_blending_enabled_show, - manager_alpha_blending_enabled_store); - - -static struct attribute *manager_sysfs_attrs[] = { - &manager_attr_name.attr, - &manager_attr_display.attr, - &manager_attr_default_color.attr, - &manager_attr_trans_key_type.attr, - &manager_attr_trans_key_value.attr, - &manager_attr_trans_key_enabled.attr, - &manager_attr_alpha_blending_enabled.attr, - NULL -}; - -static ssize_t manager_attr_show(struct kobject *kobj, struct attribute *attr, - char *buf) -{ - struct omap_overlay_manager *manager; - struct manager_attribute *manager_attr; - - manager = container_of(kobj, struct omap_overlay_manager, kobj); - manager_attr = container_of(attr, struct manager_attribute, attr); - - if (!manager_attr->show) - return -ENOENT; - - return manager_attr->show(manager, buf); -} - -static ssize_t manager_attr_store(struct kobject *kobj, struct attribute *attr, - const char *buf, size_t size) -{ - struct omap_overlay_manager *manager; - struct manager_attribute *manager_attr; - - manager = container_of(kobj, struct omap_overlay_manager, kobj); - manager_attr = container_of(attr, struct manager_attribute, attr); - - if (!manager_attr->store) - return -ENOENT; - - return manager_attr->store(manager, buf, size); -} - -static const struct sysfs_ops manager_sysfs_ops = { - .show = manager_attr_show, - .store = manager_attr_store, -}; - -static struct kobj_type manager_ktype = { - .sysfs_ops = &manager_sysfs_ops, - .default_attrs = manager_sysfs_attrs, -}; - -/* - * We have 4 levels of cache for the dispc settings. First two are in SW and - * the latter two in HW. - * - * +--------------------+ - * |overlay/manager_info| - * +--------------------+ - * v - * apply() - * v - * +--------------------+ - * | dss_cache | - * +--------------------+ - * v - * configure() - * v - * +--------------------+ - * | shadow registers | - * +--------------------+ - * v - * VFP or lcd/digit_enable - * v - * +--------------------+ - * | registers | - * +--------------------+ - */ - -struct overlay_cache_data { - /* If true, cache changed, but not written to shadow registers. Set - * in apply(), cleared when registers written. */ - bool dirty; - /* If true, shadow registers contain changed values not yet in real - * registers. Set when writing to shadow registers, cleared at - * VSYNC/EVSYNC */ - bool shadow_dirty; - - bool enabled; - - u32 paddr; - void __iomem *vaddr; - u16 screen_width; - u16 width; - u16 height; - enum omap_color_mode color_mode; - u8 rotation; - enum omap_dss_rotation_type rotation_type; - bool mirror; - - u16 pos_x; - u16 pos_y; - u16 out_width; /* if 0, out_width == width */ - u16 out_height; /* if 0, out_height == height */ - u8 global_alpha; - u8 pre_mult_alpha; - - enum omap_channel channel; - bool replication; - bool ilace; - - enum omap_burst_size burst_size; - u32 fifo_low; - u32 fifo_high; - - bool manual_update; -}; - -struct manager_cache_data { - /* If true, cache changed, but not written to shadow registers. Set - * in apply(), cleared when registers written. */ - bool dirty; - /* If true, shadow registers contain changed values not yet in real - * registers. Set when writing to shadow registers, cleared at - * VSYNC/EVSYNC */ - bool shadow_dirty; - - u32 default_color; - - enum omap_dss_trans_key_type trans_key_type; - u32 trans_key; - bool trans_enabled; - - bool alpha_enabled; - - bool manual_upd_display; - bool manual_update; - bool do_manual_update; - - /* manual update region */ - u16 x, y, w, h; - - /* enlarge the update area if the update area contains scaled - * overlays */ - bool enlarge_update_area; -}; - -static struct { - spinlock_t lock; - struct overlay_cache_data overlay_cache[MAX_DSS_OVERLAYS]; - struct manager_cache_data manager_cache[MAX_DSS_MANAGERS]; - - bool irq_enabled; -} dss_cache; - - - -static int omap_dss_set_device(struct omap_overlay_manager *mgr, - struct omap_dss_device *dssdev) -{ - int i; - int r; - - if (dssdev->manager) { - DSSERR("display '%s' already has a manager '%s'\n", - dssdev->name, dssdev->manager->name); - return -EINVAL; - } - - if ((mgr->supported_displays & dssdev->type) == 0) { - DSSERR("display '%s' does not support manager '%s'\n", - dssdev->name, mgr->name); - return -EINVAL; - } - - for (i = 0; i < mgr->num_overlays; i++) { - struct omap_overlay *ovl = mgr->overlays[i]; - - if (ovl->manager != mgr || !ovl->info.enabled) - continue; - - r = dss_check_overlay(ovl, dssdev); - if (r) - return r; - } - - dssdev->manager = mgr; - mgr->device = dssdev; - mgr->device_changed = true; - - return 0; -} - -static int omap_dss_unset_device(struct omap_overlay_manager *mgr) -{ - if (!mgr->device) { - DSSERR("failed to unset display, display not set.\n"); - return -EINVAL; - } - - mgr->device->manager = NULL; - mgr->device = NULL; - mgr->device_changed = true; - - return 0; -} - -static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr) -{ - unsigned long timeout = msecs_to_jiffies(500); - u32 irq; - - if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) { - irq = DISPC_IRQ_EVSYNC_ODD; - } else { - if (mgr->id == OMAP_DSS_CHANNEL_LCD) - irq = DISPC_IRQ_VSYNC; - else - irq = DISPC_IRQ_VSYNC2; - } - return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout); -} - -static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr) -{ - unsigned long timeout = msecs_to_jiffies(500); - struct manager_cache_data *mc; - u32 irq; - int r; - int i; - struct omap_dss_device *dssdev = mgr->device; - - if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) - return 0; - - if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { - irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; - } else { - if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { - enum omap_dss_update_mode mode; - mode = dssdev->driver->get_update_mode(dssdev); - if (mode != OMAP_DSS_UPDATE_AUTO) - return 0; - - irq = (dssdev->manager->id == OMAP_DSS_CHANNEL_LCD) ? - DISPC_IRQ_FRAMEDONE - : DISPC_IRQ_FRAMEDONE2; - } else { - irq = (dssdev->manager->id == OMAP_DSS_CHANNEL_LCD) ? - DISPC_IRQ_VSYNC - : DISPC_IRQ_VSYNC2; - } - } - - mc = &dss_cache.manager_cache[mgr->id]; - i = 0; - while (1) { - unsigned long flags; - bool shadow_dirty, dirty; - - spin_lock_irqsave(&dss_cache.lock, flags); - dirty = mc->dirty; - shadow_dirty = mc->shadow_dirty; - spin_unlock_irqrestore(&dss_cache.lock, flags); - - if (!dirty && !shadow_dirty) { - r = 0; - break; - } - - /* 4 iterations is the worst case: - * 1 - initial iteration, dirty = true (between VFP and VSYNC) - * 2 - first VSYNC, dirty = true - * 3 - dirty = false, shadow_dirty = true - * 4 - shadow_dirty = false */ - if (i++ == 3) { - DSSERR("mgr(%d)->wait_for_go() not finishing\n", - mgr->id); - r = 0; - break; - } - - r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout); - if (r == -ERESTARTSYS) - break; - - if (r) { - DSSERR("mgr(%d)->wait_for_go() timeout\n", mgr->id); - break; - } - } - - return r; -} - -int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl) -{ - unsigned long timeout = msecs_to_jiffies(500); - struct overlay_cache_data *oc; - struct omap_dss_device *dssdev; - u32 irq; - int r; - int i; - - if (!ovl->manager) - return 0; - - dssdev = ovl->manager->device; - - if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) - return 0; - - if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { - irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; - } else { - if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { - enum omap_dss_update_mode mode; - mode = dssdev->driver->get_update_mode(dssdev); - if (mode != OMAP_DSS_UPDATE_AUTO) - return 0; - - irq = (dssdev->manager->id == OMAP_DSS_CHANNEL_LCD) ? - DISPC_IRQ_FRAMEDONE - : DISPC_IRQ_FRAMEDONE2; - } else { - irq = (dssdev->manager->id == OMAP_DSS_CHANNEL_LCD) ? - DISPC_IRQ_VSYNC - : DISPC_IRQ_VSYNC2; - } - } - - oc = &dss_cache.overlay_cache[ovl->id]; - i = 0; - while (1) { - unsigned long flags; - bool shadow_dirty, dirty; - - spin_lock_irqsave(&dss_cache.lock, flags); - dirty = oc->dirty; - shadow_dirty = oc->shadow_dirty; - spin_unlock_irqrestore(&dss_cache.lock, flags); - - if (!dirty && !shadow_dirty) { - r = 0; - break; - } - - /* 4 iterations is the worst case: - * 1 - initial iteration, dirty = true (between VFP and VSYNC) - * 2 - first VSYNC, dirty = true - * 3 - dirty = false, shadow_dirty = true - * 4 - shadow_dirty = false */ - if (i++ == 3) { - DSSERR("ovl(%d)->wait_for_go() not finishing\n", - ovl->id); - r = 0; - break; - } - - r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout); - if (r == -ERESTARTSYS) - break; - - if (r) { - DSSERR("ovl(%d)->wait_for_go() timeout\n", ovl->id); - break; - } - } - - return r; -} - -static int overlay_enabled(struct omap_overlay *ovl) -{ - return ovl->info.enabled && ovl->manager && ovl->manager->device; -} - -/* Is rect1 a subset of rect2? */ -static bool rectangle_subset(int x1, int y1, int w1, int h1, - int x2, int y2, int w2, int h2) -{ - if (x1 < x2 || y1 < y2) - return false; - - if (x1 + w1 > x2 + w2) - return false; - - if (y1 + h1 > y2 + h2) - return false; - - return true; -} - -/* Do rect1 and rect2 overlap? */ -static bool rectangle_intersects(int x1, int y1, int w1, int h1, - int x2, int y2, int w2, int h2) -{ - if (x1 >= x2 + w2) - return false; - - if (x2 >= x1 + w1) - return false; - - if (y1 >= y2 + h2) - return false; - - if (y2 >= y1 + h1) - return false; - - return true; -} - -static bool dispc_is_overlay_scaled(struct overlay_cache_data *oc) -{ - if (oc->out_width != 0 && oc->width != oc->out_width) - return true; - - if (oc->out_height != 0 && oc->height != oc->out_height) - return true; - - return false; -} - -static int configure_overlay(enum omap_plane plane) -{ - struct overlay_cache_data *c; - struct manager_cache_data *mc; - u16 outw, outh; - u16 x, y, w, h; - u32 paddr; - int r; - u16 orig_w, orig_h, orig_outw, orig_outh; - - DSSDBGF("%d", plane); - - c = &dss_cache.overlay_cache[plane]; - - if (!c->enabled) { - dispc_enable_plane(plane, 0); - return 0; - } - - mc = &dss_cache.manager_cache[c->channel]; - - x = c->pos_x; - y = c->pos_y; - w = c->width; - h = c->height; - outw = c->out_width == 0 ? c->width : c->out_width; - outh = c->out_height == 0 ? c->height : c->out_height; - paddr = c->paddr; - - orig_w = w; - orig_h = h; - orig_outw = outw; - orig_outh = outh; - - if (c->manual_update && mc->do_manual_update) { - unsigned bpp; - unsigned scale_x_m = w, scale_x_d = outw; - unsigned scale_y_m = h, scale_y_d = outh; - - /* If the overlay is outside the update region, disable it */ - if (!rectangle_intersects(mc->x, mc->y, mc->w, mc->h, - x, y, outw, outh)) { - dispc_enable_plane(plane, 0); - return 0; - } - - switch (c->color_mode) { - case OMAP_DSS_COLOR_RGB16: - case OMAP_DSS_COLOR_ARGB16: - case OMAP_DSS_COLOR_YUV2: - case OMAP_DSS_COLOR_UYVY: - bpp = 16; - break; - - case OMAP_DSS_COLOR_RGB24P: - bpp = 24; - break; - - case OMAP_DSS_COLOR_RGB24U: - case OMAP_DSS_COLOR_ARGB32: - case OMAP_DSS_COLOR_RGBA32: - case OMAP_DSS_COLOR_RGBX32: - bpp = 32; - break; - - default: - BUG(); - } - - if (mc->x > c->pos_x) { - x = 0; - outw -= (mc->x - c->pos_x); - paddr += (mc->x - c->pos_x) * - scale_x_m / scale_x_d * bpp / 8; - } else { - x = c->pos_x - mc->x; - } - - if (mc->y > c->pos_y) { - y = 0; - outh -= (mc->y - c->pos_y); - paddr += (mc->y - c->pos_y) * - scale_y_m / scale_y_d * - c->screen_width * bpp / 8; - } else { - y = c->pos_y - mc->y; - } - - if (mc->w < (x + outw)) - outw -= (x + outw) - (mc->w); - - if (mc->h < (y + outh)) - outh -= (y + outh) - (mc->h); - - w = w * outw / orig_outw; - h = h * outh / orig_outh; - - /* YUV mode overlay's input width has to be even and the - * algorithm above may adjust the width to be odd. - * - * Here we adjust the width if needed, preferring to increase - * the width if the original width was bigger. - */ - if ((w & 1) && - (c->color_mode == OMAP_DSS_COLOR_YUV2 || - c->color_mode == OMAP_DSS_COLOR_UYVY)) { - if (orig_w > w) - w += 1; - else - w -= 1; - } - } - - r = dispc_setup_plane(plane, - paddr, - c->screen_width, - x, y, - w, h, - outw, outh, - c->color_mode, - c->ilace, - c->rotation_type, - c->rotation, - c->mirror, - c->global_alpha, - c->pre_mult_alpha, - c->channel); - - if (r) { - /* this shouldn't happen */ - DSSERR("dispc_setup_plane failed for ovl %d\n", plane); - dispc_enable_plane(plane, 0); - return r; - } - - dispc_enable_replication(plane, c->replication); - - dispc_set_burst_size(plane, c->burst_size); - dispc_setup_plane_fifo(plane, c->fifo_low, c->fifo_high); - - dispc_enable_plane(plane, 1); - - return 0; -} - -static void configure_manager(enum omap_channel channel) -{ - struct manager_cache_data *c; - - DSSDBGF("%d", channel); - - c = &dss_cache.manager_cache[channel]; - - dispc_set_default_color(channel, c->default_color); - dispc_set_trans_key(channel, c->trans_key_type, c->trans_key); - dispc_enable_trans_key(channel, c->trans_enabled); - dispc_enable_alpha_blending(channel, c->alpha_enabled); -} - -/* configure_dispc() tries to write values from cache to shadow registers. - * It writes only to those managers/overlays that are not busy. - * returns 0 if everything could be written to shadow registers. - * returns 1 if not everything could be written to shadow registers. */ -static int configure_dispc(void) -{ - struct overlay_cache_data *oc; - struct manager_cache_data *mc; - const int num_ovls = dss_feat_get_num_ovls(); - const int num_mgrs = dss_feat_get_num_mgrs(); - int i; - int r; - bool mgr_busy[MAX_DSS_MANAGERS]; - bool mgr_go[MAX_DSS_MANAGERS]; - bool busy; - - r = 0; - busy = false; - - for (i = 0; i < num_mgrs; i++) { - mgr_busy[i] = dispc_go_busy(i); - mgr_go[i] = false; - } - - /* Commit overlay settings */ - for (i = 0; i < num_ovls; ++i) { - oc = &dss_cache.overlay_cache[i]; - mc = &dss_cache.manager_cache[oc->channel]; - - if (!oc->dirty) - continue; - - if (oc->manual_update && !mc->do_manual_update) - continue; - - if (mgr_busy[oc->channel]) { - busy = true; - continue; - } - - r = configure_overlay(i); - if (r) - DSSERR("configure_overlay %d failed\n", i); - - oc->dirty = false; - oc->shadow_dirty = true; - mgr_go[oc->channel] = true; - } - - /* Commit manager settings */ - for (i = 0; i < num_mgrs; ++i) { - mc = &dss_cache.manager_cache[i]; - - if (!mc->dirty) - continue; - - if (mc->manual_update && !mc->do_manual_update) - continue; - - if (mgr_busy[i]) { - busy = true; - continue; - } - - configure_manager(i); - mc->dirty = false; - mc->shadow_dirty = true; - mgr_go[i] = true; - } - - /* set GO */ - for (i = 0; i < num_mgrs; ++i) { - mc = &dss_cache.manager_cache[i]; - - if (!mgr_go[i]) - continue; - - /* We don't need GO with manual update display. LCD iface will - * always be turned off after frame, and new settings will be - * taken in to use at next update */ - if (!mc->manual_upd_display) - dispc_go(i); - } - - if (busy) - r = 1; - else - r = 0; - - return r; -} - -/* Make the coordinates even. There are some strange problems with OMAP and - * partial DSI update when the update widths are odd. */ -static void make_even(u16 *x, u16 *w) -{ - u16 x1, x2; - - x1 = *x; - x2 = *x + *w; - - x1 &= ~1; - x2 = ALIGN(x2, 2); - - *x = x1; - *w = x2 - x1; -} - -/* Configure dispc for partial update. Return possibly modified update - * area */ -void dss_setup_partial_planes(struct omap_dss_device *dssdev, - u16 *xi, u16 *yi, u16 *wi, u16 *hi, bool enlarge_update_area) -{ - struct overlay_cache_data *oc; - struct manager_cache_data *mc; - const int num_ovls = dss_feat_get_num_ovls(); - struct omap_overlay_manager *mgr; - int i; - u16 x, y, w, h; - unsigned long flags; - bool area_changed; - - x = *xi; - y = *yi; - w = *wi; - h = *hi; - - DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n", - *xi, *yi, *wi, *hi); - - mgr = dssdev->manager; - - if (!mgr) { - DSSDBG("no manager\n"); - return; - } - - make_even(&x, &w); - - spin_lock_irqsave(&dss_cache.lock, flags); - - /* - * Execute the outer loop until the inner loop has completed - * once without increasing the update area. This will ensure that - * all scaled overlays end up completely within the update area. - */ - do { - area_changed = false; - - /* We need to show the whole overlay if it is scaled. So look - * for those, and make the update area larger if found. - * Also mark the overlay cache dirty */ - for (i = 0; i < num_ovls; ++i) { - unsigned x1, y1, x2, y2; - unsigned outw, outh; - - oc = &dss_cache.overlay_cache[i]; - - if (oc->channel != mgr->id) - continue; - - oc->dirty = true; - - if (!enlarge_update_area) - continue; - - if (!oc->enabled) - continue; - - if (!dispc_is_overlay_scaled(oc)) - continue; - - outw = oc->out_width == 0 ? - oc->width : oc->out_width; - outh = oc->out_height == 0 ? - oc->height : oc->out_height; - - /* is the overlay outside the update region? */ - if (!rectangle_intersects(x, y, w, h, - oc->pos_x, oc->pos_y, - outw, outh)) - continue; - - /* if the overlay totally inside the update region? */ - if (rectangle_subset(oc->pos_x, oc->pos_y, outw, outh, - x, y, w, h)) - continue; - - if (x > oc->pos_x) - x1 = oc->pos_x; - else - x1 = x; - - if (y > oc->pos_y) - y1 = oc->pos_y; - else - y1 = y; - - if ((x + w) < (oc->pos_x + outw)) - x2 = oc->pos_x + outw; - else - x2 = x + w; - - if ((y + h) < (oc->pos_y + outh)) - y2 = oc->pos_y + outh; - else - y2 = y + h; - - x = x1; - y = y1; - w = x2 - x1; - h = y2 - y1; - - make_even(&x, &w); - - DSSDBG("changing upd area due to ovl(%d) " - "scaling %d,%d %dx%d\n", - i, x, y, w, h); - - area_changed = true; - } - } while (area_changed); - - mc = &dss_cache.manager_cache[mgr->id]; - mc->do_manual_update = true; - mc->enlarge_update_area = enlarge_update_area; - mc->x = x; - mc->y = y; - mc->w = w; - mc->h = h; - - configure_dispc(); - - mc->do_manual_update = false; - - spin_unlock_irqrestore(&dss_cache.lock, flags); - - *xi = x; - *yi = y; - *wi = w; - *hi = h; -} - -void dss_start_update(struct omap_dss_device *dssdev) -{ - struct manager_cache_data *mc; - struct overlay_cache_data *oc; - const int num_ovls = dss_feat_get_num_ovls(); - const int num_mgrs = dss_feat_get_num_mgrs(); - struct omap_overlay_manager *mgr; - int i; - - mgr = dssdev->manager; - - for (i = 0; i < num_ovls; ++i) { - oc = &dss_cache.overlay_cache[i]; - if (oc->channel != mgr->id) - continue; - - oc->shadow_dirty = false; - } - - for (i = 0; i < num_mgrs; ++i) { - mc = &dss_cache.manager_cache[i]; - if (mgr->id != i) - continue; - - mc->shadow_dirty = false; - } - - dssdev->manager->enable(dssdev->manager); -} - -static void dss_apply_irq_handler(void *data, u32 mask) -{ - struct manager_cache_data *mc; - struct overlay_cache_data *oc; - const int num_ovls = dss_feat_get_num_ovls(); - const int num_mgrs = dss_feat_get_num_mgrs(); - int i, r; - bool mgr_busy[MAX_DSS_MANAGERS]; - u32 irq_mask; - - for (i = 0; i < num_mgrs; i++) - mgr_busy[i] = dispc_go_busy(i); - - spin_lock(&dss_cache.lock); - - for (i = 0; i < num_ovls; ++i) { - oc = &dss_cache.overlay_cache[i]; - if (!mgr_busy[oc->channel]) - oc->shadow_dirty = false; - } - - for (i = 0; i < num_mgrs; ++i) { - mc = &dss_cache.manager_cache[i]; - if (!mgr_busy[i]) - mc->shadow_dirty = false; - } - - r = configure_dispc(); - if (r == 1) - goto end; - - /* re-read busy flags */ - for (i = 0; i < num_mgrs; i++) - mgr_busy[i] = dispc_go_busy(i); - - /* keep running as long as there are busy managers, so that - * we can collect overlay-applied information */ - for (i = 0; i < num_mgrs; ++i) { - if (mgr_busy[i]) - goto end; - } - - irq_mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD | - DISPC_IRQ_EVSYNC_EVEN; - if (dss_has_feature(FEAT_MGR_LCD2)) - irq_mask |= DISPC_IRQ_VSYNC2; - - omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, irq_mask); - dss_cache.irq_enabled = false; - -end: - spin_unlock(&dss_cache.lock); -} - -static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) -{ - struct overlay_cache_data *oc; - struct manager_cache_data *mc; - int i; - struct omap_overlay *ovl; - int num_planes_enabled = 0; - bool use_fifomerge; - unsigned long flags; - int r; - - DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name); - - spin_lock_irqsave(&dss_cache.lock, flags); - - /* Configure overlays */ - for (i = 0; i < omap_dss_get_num_overlays(); ++i) { - struct omap_dss_device *dssdev; - - ovl = omap_dss_get_overlay(i); - - if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) - continue; - - oc = &dss_cache.overlay_cache[ovl->id]; - - if (!overlay_enabled(ovl)) { - if (oc->enabled) { - oc->enabled = false; - oc->dirty = true; - } - continue; - } - - if (!ovl->info_dirty) { - if (oc->enabled) - ++num_planes_enabled; - continue; - } - - dssdev = ovl->manager->device; - - if (dss_check_overlay(ovl, dssdev)) { - if (oc->enabled) { - oc->enabled = false; - oc->dirty = true; - } - continue; - } - - ovl->info_dirty = false; - oc->dirty = true; - - oc->paddr = ovl->info.paddr; - oc->vaddr = ovl->info.vaddr; - oc->screen_width = ovl->info.screen_width; - oc->width = ovl->info.width; - oc->height = ovl->info.height; - oc->color_mode = ovl->info.color_mode; - oc->rotation = ovl->info.rotation; - oc->rotation_type = ovl->info.rotation_type; - oc->mirror = ovl->info.mirror; - oc->pos_x = ovl->info.pos_x; - oc->pos_y = ovl->info.pos_y; - oc->out_width = ovl->info.out_width; - oc->out_height = ovl->info.out_height; - oc->global_alpha = ovl->info.global_alpha; - oc->pre_mult_alpha = ovl->info.pre_mult_alpha; - - oc->replication = - dss_use_replication(dssdev, ovl->info.color_mode); - - oc->ilace = dssdev->type == OMAP_DISPLAY_TYPE_VENC; - - oc->channel = ovl->manager->id; - - oc->enabled = true; - - oc->manual_update = - dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE && - dssdev->driver->get_update_mode(dssdev) != - OMAP_DSS_UPDATE_AUTO; - - ++num_planes_enabled; - } - - /* Configure managers */ - list_for_each_entry(mgr, &manager_list, list) { - struct omap_dss_device *dssdev; - - if (!(mgr->caps & OMAP_DSS_OVL_MGR_CAP_DISPC)) - continue; - - mc = &dss_cache.manager_cache[mgr->id]; - - if (mgr->device_changed) { - mgr->device_changed = false; - mgr->info_dirty = true; - } - - if (!mgr->info_dirty) - continue; - - if (!mgr->device) - continue; - - dssdev = mgr->device; - - mgr->info_dirty = false; - mc->dirty = true; - - mc->default_color = mgr->info.default_color; - mc->trans_key_type = mgr->info.trans_key_type; - mc->trans_key = mgr->info.trans_key; - mc->trans_enabled = mgr->info.trans_enabled; - mc->alpha_enabled = mgr->info.alpha_enabled; - - mc->manual_upd_display = - dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; - - mc->manual_update = - dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE && - dssdev->driver->get_update_mode(dssdev) != - OMAP_DSS_UPDATE_AUTO; - } - - /* XXX TODO: Try to get fifomerge working. The problem is that it - * affects both managers, not individually but at the same time. This - * means the change has to be well synchronized. I guess the proper way - * is to have a two step process for fifo merge: - * fifomerge enable: - * 1. disable other planes, leaving one plane enabled - * 2. wait until the planes are disabled on HW - * 3. config merged fifo thresholds, enable fifomerge - * fifomerge disable: - * 1. config unmerged fifo thresholds, disable fifomerge - * 2. wait until fifo changes are in HW - * 3. enable planes - */ - use_fifomerge = false; - - /* Configure overlay fifos */ - for (i = 0; i < omap_dss_get_num_overlays(); ++i) { - struct omap_dss_device *dssdev; - u32 size; - - ovl = omap_dss_get_overlay(i); - - if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) - continue; - - oc = &dss_cache.overlay_cache[ovl->id]; - - if (!oc->enabled) - continue; - - dssdev = ovl->manager->device; - - size = dispc_get_plane_fifo_size(ovl->id); - if (use_fifomerge) - size *= 3; - - switch (dssdev->type) { - case OMAP_DISPLAY_TYPE_DPI: - case OMAP_DISPLAY_TYPE_DBI: - case OMAP_DISPLAY_TYPE_SDI: - case OMAP_DISPLAY_TYPE_VENC: - default_get_overlay_fifo_thresholds(ovl->id, size, - &oc->burst_size, &oc->fifo_low, - &oc->fifo_high); - break; -#ifdef CONFIG_OMAP2_DSS_DSI - case OMAP_DISPLAY_TYPE_DSI: - dsi_get_overlay_fifo_thresholds(ovl->id, size, - &oc->burst_size, &oc->fifo_low, - &oc->fifo_high); - break; -#endif - default: - BUG(); - } - } - - r = 0; - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - if (!dss_cache.irq_enabled) { - u32 mask; - - mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD | - DISPC_IRQ_EVSYNC_EVEN; - if (dss_has_feature(FEAT_MGR_LCD2)) - mask |= DISPC_IRQ_VSYNC2; - - r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask); - dss_cache.irq_enabled = true; - } - configure_dispc(); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); - - spin_unlock_irqrestore(&dss_cache.lock, flags); - - return r; -} - -static int dss_check_manager(struct omap_overlay_manager *mgr) -{ - /* OMAP supports only graphics source transparency color key and alpha - * blending simultaneously. See TRM 15.4.2.4.2.2 Alpha Mode */ - - if (mgr->info.alpha_enabled && mgr->info.trans_enabled && - mgr->info.trans_key_type != OMAP_DSS_COLOR_KEY_GFX_DST) - return -EINVAL; - - return 0; -} - -static int omap_dss_mgr_set_info(struct omap_overlay_manager *mgr, - struct omap_overlay_manager_info *info) -{ - int r; - struct omap_overlay_manager_info old_info; - - old_info = mgr->info; - mgr->info = *info; - - r = dss_check_manager(mgr); - if (r) { - mgr->info = old_info; - return r; - } - - mgr->info_dirty = true; - - return 0; -} - -static void omap_dss_mgr_get_info(struct omap_overlay_manager *mgr, - struct omap_overlay_manager_info *info) -{ - *info = mgr->info; -} - -static int dss_mgr_enable(struct omap_overlay_manager *mgr) -{ - dispc_enable_channel(mgr->id, 1); - return 0; -} - -static int dss_mgr_disable(struct omap_overlay_manager *mgr) -{ - dispc_enable_channel(mgr->id, 0); - return 0; -} - -static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager) -{ - ++num_managers; - list_add_tail(&manager->list, &manager_list); -} - -int dss_init_overlay_managers(struct platform_device *pdev) -{ - int i, r; - - spin_lock_init(&dss_cache.lock); - - INIT_LIST_HEAD(&manager_list); - - num_managers = 0; - - for (i = 0; i < dss_feat_get_num_mgrs(); ++i) { - struct omap_overlay_manager *mgr; - mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); - - BUG_ON(mgr == NULL); - - switch (i) { - case 0: - mgr->name = "lcd"; - mgr->id = OMAP_DSS_CHANNEL_LCD; - break; - case 1: - mgr->name = "tv"; - mgr->id = OMAP_DSS_CHANNEL_DIGIT; - break; - case 2: - mgr->name = "lcd2"; - mgr->id = OMAP_DSS_CHANNEL_LCD2; - break; - } - - mgr->set_device = &omap_dss_set_device; - mgr->unset_device = &omap_dss_unset_device; - mgr->apply = &omap_dss_mgr_apply; - mgr->set_manager_info = &omap_dss_mgr_set_info; - mgr->get_manager_info = &omap_dss_mgr_get_info; - mgr->wait_for_go = &dss_mgr_wait_for_go; - mgr->wait_for_vsync = &dss_mgr_wait_for_vsync; - - mgr->enable = &dss_mgr_enable; - mgr->disable = &dss_mgr_disable; - - mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC; - mgr->supported_displays = - dss_feat_get_supported_displays(mgr->id); - - dss_overlay_setup_dispc_manager(mgr); - - omap_dss_add_overlay_manager(mgr); - - r = kobject_init_and_add(&mgr->kobj, &manager_ktype, - &pdev->dev.kobj, "manager%d", i); - - if (r) { - DSSERR("failed to create sysfs file\n"); - continue; - } - } - -#ifdef L4_EXAMPLE - { - int omap_dss_mgr_apply_l4(struct omap_overlay_manager *mgr) - { - DSSDBG("omap_dss_mgr_apply_l4(%s)\n", mgr->name); - - return 0; - } - - struct omap_overlay_manager *mgr; - mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); - - BUG_ON(mgr == NULL); - - mgr->name = "l4"; - mgr->supported_displays = - OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI; - - mgr->set_device = &omap_dss_set_device; - mgr->unset_device = &omap_dss_unset_device; - mgr->apply = &omap_dss_mgr_apply_l4; - mgr->set_manager_info = &omap_dss_mgr_set_info; - mgr->get_manager_info = &omap_dss_mgr_get_info; - - dss_overlay_setup_l4_manager(mgr); - - omap_dss_add_overlay_manager(mgr); - - r = kobject_init_and_add(&mgr->kobj, &manager_ktype, - &pdev->dev.kobj, "managerl4"); - - if (r) - DSSERR("failed to create sysfs file\n"); - } -#endif - - return 0; -} - -void dss_uninit_overlay_managers(struct platform_device *pdev) -{ - struct omap_overlay_manager *mgr; - - while (!list_empty(&manager_list)) { - mgr = list_first_entry(&manager_list, - struct omap_overlay_manager, list); - list_del(&mgr->list); - kobject_del(&mgr->kobj); - kobject_put(&mgr->kobj); - kfree(mgr); - } - - num_managers = 0; -} - -int omap_dss_get_num_overlay_managers(void) -{ - return num_managers; -} -EXPORT_SYMBOL(omap_dss_get_num_overlay_managers); - -struct omap_overlay_manager *omap_dss_get_overlay_manager(int num) -{ - int i = 0; - struct omap_overlay_manager *mgr; - - list_for_each_entry(mgr, &manager_list, list) { - if (i++ == num) - return mgr; - } - - return NULL; -} -EXPORT_SYMBOL(omap_dss_get_overlay_manager); - diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c deleted file mode 100644 index 456efef03c2..00000000000 --- a/drivers/video/omap2/dss/overlay.c +++ /dev/null @@ -1,728 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/overlay.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "OVERLAY" - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/err.h> -#include <linux/sysfs.h> -#include <linux/kobject.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/slab.h> - -#include <plat/display.h> -#include <plat/cpu.h> - -#include "dss.h" -#include "dss_features.h" - -static int num_overlays; -static struct list_head overlay_list; - -static ssize_t overlay_name_show(struct omap_overlay *ovl, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%s\n", ovl->name); -} - -static ssize_t overlay_manager_show(struct omap_overlay *ovl, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%s\n", - ovl->manager ? ovl->manager->name : "<none>"); -} - -static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf, - size_t size) -{ - int i, r; - struct omap_overlay_manager *mgr = NULL; - struct omap_overlay_manager *old_mgr; - int len = size; - - if (buf[size-1] == '\n') - --len; - - if (len > 0) { - for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { - mgr = omap_dss_get_overlay_manager(i); - - if (sysfs_streq(buf, mgr->name)) - break; - - mgr = NULL; - } - } - - if (len > 0 && mgr == NULL) - return -EINVAL; - - if (mgr) - DSSDBG("manager %s found\n", mgr->name); - - if (mgr == ovl->manager) - return size; - - old_mgr = ovl->manager; - - /* detach old manager */ - if (old_mgr) { - r = ovl->unset_manager(ovl); - if (r) { - DSSERR("detach failed\n"); - return r; - } - - r = old_mgr->apply(old_mgr); - if (r) - return r; - } - - if (mgr) { - r = ovl->set_manager(ovl, mgr); - if (r) { - DSSERR("Failed to attach overlay\n"); - return r; - } - - r = mgr->apply(mgr); - if (r) - return r; - } - - return size; -} - -static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d,%d\n", - ovl->info.width, ovl->info.height); -} - -static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.screen_width); -} - -static ssize_t overlay_position_show(struct omap_overlay *ovl, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d,%d\n", - ovl->info.pos_x, ovl->info.pos_y); -} - -static ssize_t overlay_position_store(struct omap_overlay *ovl, - const char *buf, size_t size) -{ - int r; - char *last; - struct omap_overlay_info info; - - ovl->get_overlay_info(ovl, &info); - - info.pos_x = simple_strtoul(buf, &last, 10); - ++last; - if (last - buf >= size) - return -EINVAL; - - info.pos_y = simple_strtoul(last, &last, 10); - - r = ovl->set_overlay_info(ovl, &info); - if (r) - return r; - - if (ovl->manager) { - r = ovl->manager->apply(ovl->manager); - if (r) - return r; - } - - return size; -} - -static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d,%d\n", - ovl->info.out_width, ovl->info.out_height); -} - -static ssize_t overlay_output_size_store(struct omap_overlay *ovl, - const char *buf, size_t size) -{ - int r; - char *last; - struct omap_overlay_info info; - - ovl->get_overlay_info(ovl, &info); - - info.out_width = simple_strtoul(buf, &last, 10); - ++last; - if (last - buf >= size) - return -EINVAL; - - info.out_height = simple_strtoul(last, &last, 10); - - r = ovl->set_overlay_info(ovl, &info); - if (r) - return r; - - if (ovl->manager) { - r = ovl->manager->apply(ovl->manager); - if (r) - return r; - } - - return size; -} - -static ssize_t overlay_enabled_show(struct omap_overlay *ovl, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.enabled); -} - -static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf, - size_t size) -{ - int r; - struct omap_overlay_info info; - - ovl->get_overlay_info(ovl, &info); - - info.enabled = simple_strtoul(buf, NULL, 10); - - r = ovl->set_overlay_info(ovl, &info); - if (r) - return r; - - if (ovl->manager) { - r = ovl->manager->apply(ovl->manager); - if (r) - return r; - } - - return size; -} - -static ssize_t overlay_global_alpha_show(struct omap_overlay *ovl, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", - ovl->info.global_alpha); -} - -static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl, - const char *buf, size_t size) -{ - int r; - struct omap_overlay_info info; - - ovl->get_overlay_info(ovl, &info); - - /* Video1 plane does not support global alpha - * to always make it 255 completely opaque - */ - if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) && - ovl->id == OMAP_DSS_VIDEO1) - info.global_alpha = 255; - else - info.global_alpha = simple_strtoul(buf, NULL, 10); - - r = ovl->set_overlay_info(ovl, &info); - if (r) - return r; - - if (ovl->manager) { - r = ovl->manager->apply(ovl->manager); - if (r) - return r; - } - - return size; -} - -static ssize_t overlay_pre_mult_alpha_show(struct omap_overlay *ovl, - char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", - ovl->info.pre_mult_alpha); -} - -static ssize_t overlay_pre_mult_alpha_store(struct omap_overlay *ovl, - const char *buf, size_t size) -{ - int r; - struct omap_overlay_info info; - - ovl->get_overlay_info(ovl, &info); - - /* only GFX and Video2 plane support pre alpha multiplied - * set zero for Video1 plane - */ - if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) && - ovl->id == OMAP_DSS_VIDEO1) - info.pre_mult_alpha = 0; - else - info.pre_mult_alpha = simple_strtoul(buf, NULL, 10); - - r = ovl->set_overlay_info(ovl, &info); - if (r) - return r; - - if (ovl->manager) { - r = ovl->manager->apply(ovl->manager); - if (r) - return r; - } - - return size; -} - -struct overlay_attribute { - struct attribute attr; - ssize_t (*show)(struct omap_overlay *, char *); - ssize_t (*store)(struct omap_overlay *, const char *, size_t); -}; - -#define OVERLAY_ATTR(_name, _mode, _show, _store) \ - struct overlay_attribute overlay_attr_##_name = \ - __ATTR(_name, _mode, _show, _store) - -static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL); -static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR, - overlay_manager_show, overlay_manager_store); -static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL); -static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL); -static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR, - overlay_position_show, overlay_position_store); -static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR, - overlay_output_size_show, overlay_output_size_store); -static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR, - overlay_enabled_show, overlay_enabled_store); -static OVERLAY_ATTR(global_alpha, S_IRUGO|S_IWUSR, - overlay_global_alpha_show, overlay_global_alpha_store); -static OVERLAY_ATTR(pre_mult_alpha, S_IRUGO|S_IWUSR, - overlay_pre_mult_alpha_show, - overlay_pre_mult_alpha_store); - -static struct attribute *overlay_sysfs_attrs[] = { - &overlay_attr_name.attr, - &overlay_attr_manager.attr, - &overlay_attr_input_size.attr, - &overlay_attr_screen_width.attr, - &overlay_attr_position.attr, - &overlay_attr_output_size.attr, - &overlay_attr_enabled.attr, - &overlay_attr_global_alpha.attr, - &overlay_attr_pre_mult_alpha.attr, - NULL -}; - -static ssize_t overlay_attr_show(struct kobject *kobj, struct attribute *attr, - char *buf) -{ - struct omap_overlay *overlay; - struct overlay_attribute *overlay_attr; - - overlay = container_of(kobj, struct omap_overlay, kobj); - overlay_attr = container_of(attr, struct overlay_attribute, attr); - - if (!overlay_attr->show) - return -ENOENT; - - return overlay_attr->show(overlay, buf); -} - -static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr, - const char *buf, size_t size) -{ - struct omap_overlay *overlay; - struct overlay_attribute *overlay_attr; - - overlay = container_of(kobj, struct omap_overlay, kobj); - overlay_attr = container_of(attr, struct overlay_attribute, attr); - - if (!overlay_attr->store) - return -ENOENT; - - return overlay_attr->store(overlay, buf, size); -} - -static const struct sysfs_ops overlay_sysfs_ops = { - .show = overlay_attr_show, - .store = overlay_attr_store, -}; - -static struct kobj_type overlay_ktype = { - .sysfs_ops = &overlay_sysfs_ops, - .default_attrs = overlay_sysfs_attrs, -}; - -/* Check if overlay parameters are compatible with display */ -int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev) -{ - struct omap_overlay_info *info; - u16 outw, outh; - u16 dw, dh; - - if (!dssdev) - return 0; - - if (!ovl->info.enabled) - return 0; - - info = &ovl->info; - - if (info->paddr == 0) { - DSSDBG("check_overlay failed: paddr 0\n"); - return -EINVAL; - } - - dssdev->driver->get_resolution(dssdev, &dw, &dh); - - DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n", - ovl->id, - info->pos_x, info->pos_y, - info->width, info->height, - info->out_width, info->out_height, - dw, dh); - - if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) { - outw = info->width; - outh = info->height; - } else { - if (info->out_width == 0) - outw = info->width; - else - outw = info->out_width; - - if (info->out_height == 0) - outh = info->height; - else - outh = info->out_height; - } - - if (dw < info->pos_x + outw) { - DSSDBG("check_overlay failed 1: %d < %d + %d\n", - dw, info->pos_x, outw); - return -EINVAL; - } - - if (dh < info->pos_y + outh) { - DSSDBG("check_overlay failed 2: %d < %d + %d\n", - dh, info->pos_y, outh); - return -EINVAL; - } - - if ((ovl->supported_modes & info->color_mode) == 0) { - DSSERR("overlay doesn't support mode %d\n", info->color_mode); - return -EINVAL; - } - - return 0; -} - -static int dss_ovl_set_overlay_info(struct omap_overlay *ovl, - struct omap_overlay_info *info) -{ - int r; - struct omap_overlay_info old_info; - - old_info = ovl->info; - ovl->info = *info; - - if (ovl->manager) { - r = dss_check_overlay(ovl, ovl->manager->device); - if (r) { - ovl->info = old_info; - return r; - } - } - - ovl->info_dirty = true; - - return 0; -} - -static void dss_ovl_get_overlay_info(struct omap_overlay *ovl, - struct omap_overlay_info *info) -{ - *info = ovl->info; -} - -static int dss_ovl_wait_for_go(struct omap_overlay *ovl) -{ - return dss_mgr_wait_for_go_ovl(ovl); -} - -static int omap_dss_set_manager(struct omap_overlay *ovl, - struct omap_overlay_manager *mgr) -{ - if (!mgr) - return -EINVAL; - - if (ovl->manager) { - DSSERR("overlay '%s' already has a manager '%s'\n", - ovl->name, ovl->manager->name); - return -EINVAL; - } - - if (ovl->info.enabled) { - DSSERR("overlay has to be disabled to change the manager\n"); - return -EINVAL; - } - - ovl->manager = mgr; - - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - /* XXX: on manual update display, in auto update mode, a bug happens - * here. When an overlay is first enabled on LCD, then it's disabled, - * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT - * errors. Waiting before changing the channel_out fixes it. I'm - * guessing that the overlay is still somehow being used for the LCD, - * but I don't understand how or why. */ - msleep(40); - dispc_set_channel_out(ovl->id, mgr->id); - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); - - return 0; -} - -static int omap_dss_unset_manager(struct omap_overlay *ovl) -{ - int r; - - if (!ovl->manager) { - DSSERR("failed to detach overlay: manager not set\n"); - return -EINVAL; - } - - if (ovl->info.enabled) { - DSSERR("overlay has to be disabled to unset the manager\n"); - return -EINVAL; - } - - r = ovl->wait_for_go(ovl); - if (r) - return r; - - ovl->manager = NULL; - - return 0; -} - -int omap_dss_get_num_overlays(void) -{ - return num_overlays; -} -EXPORT_SYMBOL(omap_dss_get_num_overlays); - -struct omap_overlay *omap_dss_get_overlay(int num) -{ - int i = 0; - struct omap_overlay *ovl; - - list_for_each_entry(ovl, &overlay_list, list) { - if (i++ == num) - return ovl; - } - - return NULL; -} -EXPORT_SYMBOL(omap_dss_get_overlay); - -static void omap_dss_add_overlay(struct omap_overlay *overlay) -{ - ++num_overlays; - list_add_tail(&overlay->list, &overlay_list); -} - -static struct omap_overlay *dispc_overlays[MAX_DSS_OVERLAYS]; - -void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr) -{ - mgr->num_overlays = dss_feat_get_num_ovls(); - mgr->overlays = dispc_overlays; -} - -#ifdef L4_EXAMPLE -static struct omap_overlay *l4_overlays[1]; -void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr) -{ - mgr->num_overlays = 1; - mgr->overlays = l4_overlays; -} -#endif - -void dss_init_overlays(struct platform_device *pdev) -{ - int i, r; - - INIT_LIST_HEAD(&overlay_list); - - num_overlays = 0; - - for (i = 0; i < dss_feat_get_num_ovls(); ++i) { - struct omap_overlay *ovl; - ovl = kzalloc(sizeof(*ovl), GFP_KERNEL); - - BUG_ON(ovl == NULL); - - switch (i) { - case 0: - ovl->name = "gfx"; - ovl->id = OMAP_DSS_GFX; - ovl->caps = OMAP_DSS_OVL_CAP_DISPC; - ovl->info.global_alpha = 255; - break; - case 1: - ovl->name = "vid1"; - ovl->id = OMAP_DSS_VIDEO1; - ovl->caps = OMAP_DSS_OVL_CAP_SCALE | - OMAP_DSS_OVL_CAP_DISPC; - ovl->info.global_alpha = 255; - break; - case 2: - ovl->name = "vid2"; - ovl->id = OMAP_DSS_VIDEO2; - ovl->caps = OMAP_DSS_OVL_CAP_SCALE | - OMAP_DSS_OVL_CAP_DISPC; - ovl->info.global_alpha = 255; - break; - } - - ovl->set_manager = &omap_dss_set_manager; - ovl->unset_manager = &omap_dss_unset_manager; - ovl->set_overlay_info = &dss_ovl_set_overlay_info; - ovl->get_overlay_info = &dss_ovl_get_overlay_info; - ovl->wait_for_go = &dss_ovl_wait_for_go; - - ovl->supported_modes = - dss_feat_get_supported_color_modes(ovl->id); - - omap_dss_add_overlay(ovl); - - r = kobject_init_and_add(&ovl->kobj, &overlay_ktype, - &pdev->dev.kobj, "overlay%d", i); - - if (r) { - DSSERR("failed to create sysfs file\n"); - continue; - } - - dispc_overlays[i] = ovl; - } - -#ifdef L4_EXAMPLE - { - struct omap_overlay *ovl; - ovl = kzalloc(sizeof(*ovl), GFP_KERNEL); - - BUG_ON(ovl == NULL); - - ovl->name = "l4"; - ovl->supported_modes = OMAP_DSS_COLOR_RGB24U; - - ovl->set_manager = &omap_dss_set_manager; - ovl->unset_manager = &omap_dss_unset_manager; - ovl->set_overlay_info = &dss_ovl_set_overlay_info; - ovl->get_overlay_info = &dss_ovl_get_overlay_info; - - omap_dss_add_overlay(ovl); - - r = kobject_init_and_add(&ovl->kobj, &overlay_ktype, - &pdev->dev.kobj, "overlayl4"); - - if (r) - DSSERR("failed to create sysfs file\n"); - - l4_overlays[0] = ovl; - } -#endif -} - -/* connect overlays to the new device, if not already connected. if force - * selected, connect always. */ -void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) -{ - int i; - struct omap_overlay_manager *lcd_mgr; - struct omap_overlay_manager *tv_mgr; - struct omap_overlay_manager *lcd2_mgr = NULL; - struct omap_overlay_manager *mgr = NULL; - - lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD); - tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV); - if (dss_has_feature(FEAT_MGR_LCD2)) - lcd2_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD2); - - if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) { - if (!lcd2_mgr->device || force) { - if (lcd2_mgr->device) - lcd2_mgr->unset_device(lcd2_mgr); - lcd2_mgr->set_device(lcd2_mgr, dssdev); - mgr = lcd2_mgr; - } - } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) { - if (!lcd_mgr->device || force) { - if (lcd_mgr->device) - lcd_mgr->unset_device(lcd_mgr); - lcd_mgr->set_device(lcd_mgr, dssdev); - mgr = lcd_mgr; - } - } - - if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { - if (!tv_mgr->device || force) { - if (tv_mgr->device) - tv_mgr->unset_device(tv_mgr); - tv_mgr->set_device(tv_mgr, dssdev); - mgr = tv_mgr; - } - } - - if (mgr) { - for (i = 0; i < dss_feat_get_num_ovls(); i++) { - struct omap_overlay *ovl; - ovl = omap_dss_get_overlay(i); - if (!ovl->manager || force) { - if (ovl->manager) - omap_dss_unset_manager(ovl); - omap_dss_set_manager(ovl, mgr); - } - } - } -} - -void dss_uninit_overlays(struct platform_device *pdev) -{ - struct omap_overlay *ovl; - - while (!list_empty(&overlay_list)) { - ovl = list_first_entry(&overlay_list, - struct omap_overlay, list); - list_del(&ovl->list); - kobject_del(&ovl->kobj); - kobject_put(&ovl->kobj); - kfree(ovl); - } - - num_overlays = 0; -} - diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c deleted file mode 100644 index 10a2ffe0288..00000000000 --- a/drivers/video/omap2/dss/rfbi.c +++ /dev/null @@ -1,1058 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/rfbi.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "RFBI" - -#include <linux/kernel.h> -#include <linux/dma-mapping.h> -#include <linux/vmalloc.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/kfifo.h> -#include <linux/ktime.h> -#include <linux/hrtimer.h> -#include <linux/seq_file.h> - -#include <plat/display.h> -#include "dss.h" - -#define RFBI_BASE 0x48050800 - -struct rfbi_reg { u16 idx; }; - -#define RFBI_REG(idx) ((const struct rfbi_reg) { idx }) - -#define RFBI_REVISION RFBI_REG(0x0000) -#define RFBI_SYSCONFIG RFBI_REG(0x0010) -#define RFBI_SYSSTATUS RFBI_REG(0x0014) -#define RFBI_CONTROL RFBI_REG(0x0040) -#define RFBI_PIXEL_CNT RFBI_REG(0x0044) -#define RFBI_LINE_NUMBER RFBI_REG(0x0048) -#define RFBI_CMD RFBI_REG(0x004c) -#define RFBI_PARAM RFBI_REG(0x0050) -#define RFBI_DATA RFBI_REG(0x0054) -#define RFBI_READ RFBI_REG(0x0058) -#define RFBI_STATUS RFBI_REG(0x005c) - -#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18) -#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18) -#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18) -#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18) -#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18) -#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18) - -#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090) -#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094) - -#define REG_FLD_MOD(idx, val, start, end) \ - rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end)) - -/* To work around an RFBI transfer rate limitation */ -#define OMAP_RFBI_RATE_LIMIT 1 - -enum omap_rfbi_cycleformat { - OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0, - OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1, - OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2, - OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3, -}; - -enum omap_rfbi_datatype { - OMAP_DSS_RFBI_DATATYPE_12 = 0, - OMAP_DSS_RFBI_DATATYPE_16 = 1, - OMAP_DSS_RFBI_DATATYPE_18 = 2, - OMAP_DSS_RFBI_DATATYPE_24 = 3, -}; - -enum omap_rfbi_parallelmode { - OMAP_DSS_RFBI_PARALLELMODE_8 = 0, - OMAP_DSS_RFBI_PARALLELMODE_9 = 1, - OMAP_DSS_RFBI_PARALLELMODE_12 = 2, - OMAP_DSS_RFBI_PARALLELMODE_16 = 3, -}; - -enum update_cmd { - RFBI_CMD_UPDATE = 0, - RFBI_CMD_SYNC = 1, -}; - -static int rfbi_convert_timings(struct rfbi_timings *t); -static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div); - -static struct { - void __iomem *base; - - unsigned long l4_khz; - - enum omap_rfbi_datatype datatype; - enum omap_rfbi_parallelmode parallelmode; - - enum omap_rfbi_te_mode te_mode; - int te_enabled; - - void (*framedone_callback)(void *data); - void *framedone_callback_data; - - struct omap_dss_device *dssdev[2]; - - struct kfifo cmd_fifo; - spinlock_t cmd_lock; - struct completion cmd_done; - atomic_t cmd_fifo_full; - atomic_t cmd_pending; -} rfbi; - -struct update_region { - u16 x; - u16 y; - u16 w; - u16 h; -}; - -static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val) -{ - __raw_writel(val, rfbi.base + idx.idx); -} - -static inline u32 rfbi_read_reg(const struct rfbi_reg idx) -{ - return __raw_readl(rfbi.base + idx.idx); -} - -static void rfbi_enable_clocks(bool enable) -{ - if (enable) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - else - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -} - -void omap_rfbi_write_command(const void *buf, u32 len) -{ - rfbi_enable_clocks(1); - switch (rfbi.parallelmode) { - case OMAP_DSS_RFBI_PARALLELMODE_8: - { - const u8 *b = buf; - for (; len; len--) - rfbi_write_reg(RFBI_CMD, *b++); - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_16: - { - const u16 *w = buf; - BUG_ON(len & 1); - for (; len; len -= 2) - rfbi_write_reg(RFBI_CMD, *w++); - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_9: - case OMAP_DSS_RFBI_PARALLELMODE_12: - default: - BUG(); - } - rfbi_enable_clocks(0); -} -EXPORT_SYMBOL(omap_rfbi_write_command); - -void omap_rfbi_read_data(void *buf, u32 len) -{ - rfbi_enable_clocks(1); - switch (rfbi.parallelmode) { - case OMAP_DSS_RFBI_PARALLELMODE_8: - { - u8 *b = buf; - for (; len; len--) { - rfbi_write_reg(RFBI_READ, 0); - *b++ = rfbi_read_reg(RFBI_READ); - } - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_16: - { - u16 *w = buf; - BUG_ON(len & ~1); - for (; len; len -= 2) { - rfbi_write_reg(RFBI_READ, 0); - *w++ = rfbi_read_reg(RFBI_READ); - } - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_9: - case OMAP_DSS_RFBI_PARALLELMODE_12: - default: - BUG(); - } - rfbi_enable_clocks(0); -} -EXPORT_SYMBOL(omap_rfbi_read_data); - -void omap_rfbi_write_data(const void *buf, u32 len) -{ - rfbi_enable_clocks(1); - switch (rfbi.parallelmode) { - case OMAP_DSS_RFBI_PARALLELMODE_8: - { - const u8 *b = buf; - for (; len; len--) - rfbi_write_reg(RFBI_PARAM, *b++); - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_16: - { - const u16 *w = buf; - BUG_ON(len & 1); - for (; len; len -= 2) - rfbi_write_reg(RFBI_PARAM, *w++); - break; - } - - case OMAP_DSS_RFBI_PARALLELMODE_9: - case OMAP_DSS_RFBI_PARALLELMODE_12: - default: - BUG(); - - } - rfbi_enable_clocks(0); -} -EXPORT_SYMBOL(omap_rfbi_write_data); - -void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, - u16 x, u16 y, - u16 w, u16 h) -{ - int start_offset = scr_width * y + x; - int horiz_offset = scr_width - w; - int i; - - rfbi_enable_clocks(1); - - if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && - rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { - const u16 __iomem *pd = buf; - pd += start_offset; - - for (; h; --h) { - for (i = 0; i < w; ++i) { - const u8 __iomem *b = (const u8 __iomem *)pd; - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); - ++pd; - } - pd += horiz_offset; - } - } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 && - rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { - const u32 __iomem *pd = buf; - pd += start_offset; - - for (; h; --h) { - for (i = 0; i < w; ++i) { - const u8 __iomem *b = (const u8 __iomem *)pd; - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2)); - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); - rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); - ++pd; - } - pd += horiz_offset; - } - } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && - rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) { - const u16 __iomem *pd = buf; - pd += start_offset; - - for (; h; --h) { - for (i = 0; i < w; ++i) { - rfbi_write_reg(RFBI_PARAM, __raw_readw(pd)); - ++pd; - } - pd += horiz_offset; - } - } else { - BUG(); - } - - rfbi_enable_clocks(0); -} -EXPORT_SYMBOL(omap_rfbi_write_pixels); - -void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width, - u16 height, void (*callback)(void *data), void *data) -{ - u32 l; - - /*BUG_ON(callback == 0);*/ - BUG_ON(rfbi.framedone_callback != NULL); - - DSSDBG("rfbi_transfer_area %dx%d\n", width, height); - - dispc_set_lcd_size(dssdev->manager->id, width, height); - - dispc_enable_channel(dssdev->manager->id, true); - - rfbi.framedone_callback = callback; - rfbi.framedone_callback_data = data; - - rfbi_enable_clocks(1); - - rfbi_write_reg(RFBI_PIXEL_CNT, width * height); - - l = rfbi_read_reg(RFBI_CONTROL); - l = FLD_MOD(l, 1, 0, 0); /* enable */ - if (!rfbi.te_enabled) - l = FLD_MOD(l, 1, 4, 4); /* ITE */ - - rfbi_write_reg(RFBI_CONTROL, l); -} - -static void framedone_callback(void *data, u32 mask) -{ - void (*callback)(void *data); - - DSSDBG("FRAMEDONE\n"); - - REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); - - rfbi_enable_clocks(0); - - callback = rfbi.framedone_callback; - rfbi.framedone_callback = NULL; - - if (callback != NULL) - callback(rfbi.framedone_callback_data); - - atomic_set(&rfbi.cmd_pending, 0); -} - -#if 1 /* VERBOSE */ -static void rfbi_print_timings(void) -{ - u32 l; - u32 time; - - l = rfbi_read_reg(RFBI_CONFIG(0)); - time = 1000000000 / rfbi.l4_khz; - if (l & (1 << 4)) - time *= 2; - - DSSDBG("Tick time %u ps\n", time); - l = rfbi_read_reg(RFBI_ONOFF_TIME(0)); - DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, " - "REONTIME %d, REOFFTIME %d\n", - l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f, - (l >> 20) & 0x0f, (l >> 24) & 0x3f); - - l = rfbi_read_reg(RFBI_CYCLE_TIME(0)); - DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, " - "ACCESSTIME %d\n", - (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f, - (l >> 22) & 0x3f); -} -#else -static void rfbi_print_timings(void) {} -#endif - - - - -static u32 extif_clk_period; - -static inline unsigned long round_to_extif_ticks(unsigned long ps, int div) -{ - int bus_tick = extif_clk_period * div; - return (ps + bus_tick - 1) / bus_tick * bus_tick; -} - -static int calc_reg_timing(struct rfbi_timings *t, int div) -{ - t->clk_div = div; - - t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div); - - t->we_on_time = round_to_extif_ticks(t->we_on_time, div); - t->we_off_time = round_to_extif_ticks(t->we_off_time, div); - t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div); - - t->re_on_time = round_to_extif_ticks(t->re_on_time, div); - t->re_off_time = round_to_extif_ticks(t->re_off_time, div); - t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div); - - t->access_time = round_to_extif_ticks(t->access_time, div); - t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div); - t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div); - - DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n", - t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time); - DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n", - t->we_on_time, t->we_off_time, t->re_cycle_time, - t->we_cycle_time); - DSSDBG("[reg]rdaccess %d cspulse %d\n", - t->access_time, t->cs_pulse_width); - - return rfbi_convert_timings(t); -} - -static int calc_extif_timings(struct rfbi_timings *t) -{ - u32 max_clk_div; - int div; - - rfbi_get_clk_info(&extif_clk_period, &max_clk_div); - for (div = 1; div <= max_clk_div; div++) { - if (calc_reg_timing(t, div) == 0) - break; - } - - if (div <= max_clk_div) - return 0; - - DSSERR("can't setup timings\n"); - return -1; -} - - -void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t) -{ - int r; - - if (!t->converted) { - r = calc_extif_timings(t); - if (r < 0) - DSSERR("Failed to calc timings\n"); - } - - BUG_ON(!t->converted); - - rfbi_enable_clocks(1); - rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]); - rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]); - - /* TIMEGRANULARITY */ - REG_FLD_MOD(RFBI_CONFIG(rfbi_module), - (t->tim[2] ? 1 : 0), 4, 4); - - rfbi_print_timings(); - rfbi_enable_clocks(0); -} - -static int ps_to_rfbi_ticks(int time, int div) -{ - unsigned long tick_ps; - int ret; - - /* Calculate in picosecs to yield more exact results */ - tick_ps = 1000000000 / (rfbi.l4_khz) * div; - - ret = (time + tick_ps - 1) / tick_ps; - - return ret; -} - -#ifdef OMAP_RFBI_RATE_LIMIT -unsigned long rfbi_get_max_tx_rate(void) -{ - unsigned long l4_rate, dss1_rate; - int min_l4_ticks = 0; - int i; - - /* According to TI this can't be calculated so make the - * adjustments for a couple of known frequencies and warn for - * others. - */ - static const struct { - unsigned long l4_clk; /* HZ */ - unsigned long dss1_clk; /* HZ */ - unsigned long min_l4_ticks; - } ftab[] = { - { 55, 132, 7, }, /* 7.86 MPix/s */ - { 110, 110, 12, }, /* 9.16 MPix/s */ - { 110, 132, 10, }, /* 11 Mpix/s */ - { 120, 120, 10, }, /* 12 Mpix/s */ - { 133, 133, 10, }, /* 13.3 Mpix/s */ - }; - - l4_rate = rfbi.l4_khz / 1000; - dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000; - - for (i = 0; i < ARRAY_SIZE(ftab); i++) { - /* Use a window instead of an exact match, to account - * for different DPLL multiplier / divider pairs. - */ - if (abs(ftab[i].l4_clk - l4_rate) < 3 && - abs(ftab[i].dss1_clk - dss1_rate) < 3) { - min_l4_ticks = ftab[i].min_l4_ticks; - break; - } - } - if (i == ARRAY_SIZE(ftab)) { - /* Can't be sure, return anyway the maximum not - * rate-limited. This might cause a problem only for the - * tearing synchronisation. - */ - DSSERR("can't determine maximum RFBI transfer rate\n"); - return rfbi.l4_khz * 1000; - } - return rfbi.l4_khz * 1000 / min_l4_ticks; -} -#else -int rfbi_get_max_tx_rate(void) -{ - return rfbi.l4_khz * 1000; -} -#endif - -static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div) -{ - *clk_period = 1000000000 / rfbi.l4_khz; - *max_clk_div = 2; -} - -static int rfbi_convert_timings(struct rfbi_timings *t) -{ - u32 l; - int reon, reoff, weon, weoff, cson, csoff, cs_pulse; - int actim, recyc, wecyc; - int div = t->clk_div; - - if (div <= 0 || div > 2) - return -1; - - /* Make sure that after conversion it still holds that: - * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff, - * csoff > cson, csoff >= max(weoff, reoff), actim > reon - */ - weon = ps_to_rfbi_ticks(t->we_on_time, div); - weoff = ps_to_rfbi_ticks(t->we_off_time, div); - if (weoff <= weon) - weoff = weon + 1; - if (weon > 0x0f) - return -1; - if (weoff > 0x3f) - return -1; - - reon = ps_to_rfbi_ticks(t->re_on_time, div); - reoff = ps_to_rfbi_ticks(t->re_off_time, div); - if (reoff <= reon) - reoff = reon + 1; - if (reon > 0x0f) - return -1; - if (reoff > 0x3f) - return -1; - - cson = ps_to_rfbi_ticks(t->cs_on_time, div); - csoff = ps_to_rfbi_ticks(t->cs_off_time, div); - if (csoff <= cson) - csoff = cson + 1; - if (csoff < max(weoff, reoff)) - csoff = max(weoff, reoff); - if (cson > 0x0f) - return -1; - if (csoff > 0x3f) - return -1; - - l = cson; - l |= csoff << 4; - l |= weon << 10; - l |= weoff << 14; - l |= reon << 20; - l |= reoff << 24; - - t->tim[0] = l; - - actim = ps_to_rfbi_ticks(t->access_time, div); - if (actim <= reon) - actim = reon + 1; - if (actim > 0x3f) - return -1; - - wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div); - if (wecyc < weoff) - wecyc = weoff; - if (wecyc > 0x3f) - return -1; - - recyc = ps_to_rfbi_ticks(t->re_cycle_time, div); - if (recyc < reoff) - recyc = reoff; - if (recyc > 0x3f) - return -1; - - cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div); - if (cs_pulse > 0x3f) - return -1; - - l = wecyc; - l |= recyc << 6; - l |= cs_pulse << 12; - l |= actim << 22; - - t->tim[1] = l; - - t->tim[2] = div - 1; - - t->converted = 1; - - return 0; -} - -/* xxx FIX module selection missing */ -int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, - unsigned hs_pulse_time, unsigned vs_pulse_time, - int hs_pol_inv, int vs_pol_inv, int extif_div) -{ - int hs, vs; - int min; - u32 l; - - hs = ps_to_rfbi_ticks(hs_pulse_time, 1); - vs = ps_to_rfbi_ticks(vs_pulse_time, 1); - if (hs < 2) - return -EDOM; - if (mode == OMAP_DSS_RFBI_TE_MODE_2) - min = 2; - else /* OMAP_DSS_RFBI_TE_MODE_1 */ - min = 4; - if (vs < min) - return -EDOM; - if (vs == hs) - return -EINVAL; - rfbi.te_mode = mode; - DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n", - mode, hs, vs, hs_pol_inv, vs_pol_inv); - - rfbi_enable_clocks(1); - rfbi_write_reg(RFBI_HSYNC_WIDTH, hs); - rfbi_write_reg(RFBI_VSYNC_WIDTH, vs); - - l = rfbi_read_reg(RFBI_CONFIG(0)); - if (hs_pol_inv) - l &= ~(1 << 21); - else - l |= 1 << 21; - if (vs_pol_inv) - l &= ~(1 << 20); - else - l |= 1 << 20; - rfbi_enable_clocks(0); - - return 0; -} -EXPORT_SYMBOL(omap_rfbi_setup_te); - -/* xxx FIX module selection missing */ -int omap_rfbi_enable_te(bool enable, unsigned line) -{ - u32 l; - - DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode); - if (line > (1 << 11) - 1) - return -EINVAL; - - rfbi_enable_clocks(1); - l = rfbi_read_reg(RFBI_CONFIG(0)); - l &= ~(0x3 << 2); - if (enable) { - rfbi.te_enabled = 1; - l |= rfbi.te_mode << 2; - } else - rfbi.te_enabled = 0; - rfbi_write_reg(RFBI_CONFIG(0), l); - rfbi_write_reg(RFBI_LINE_NUMBER, line); - rfbi_enable_clocks(0); - - return 0; -} -EXPORT_SYMBOL(omap_rfbi_enable_te); - -#if 0 -static void rfbi_enable_config(int enable1, int enable2) -{ - u32 l; - int cs = 0; - - if (enable1) - cs |= 1<<0; - if (enable2) - cs |= 1<<1; - - rfbi_enable_clocks(1); - - l = rfbi_read_reg(RFBI_CONTROL); - - l = FLD_MOD(l, cs, 3, 2); - l = FLD_MOD(l, 0, 1, 1); - - rfbi_write_reg(RFBI_CONTROL, l); - - - l = rfbi_read_reg(RFBI_CONFIG(0)); - l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */ - /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */ - /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */ - - l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */ - l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */ - l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */ - - l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0); - rfbi_write_reg(RFBI_CONFIG(0), l); - - rfbi_enable_clocks(0); -} -#endif - -int rfbi_configure(int rfbi_module, int bpp, int lines) -{ - u32 l; - int cycle1 = 0, cycle2 = 0, cycle3 = 0; - enum omap_rfbi_cycleformat cycleformat; - enum omap_rfbi_datatype datatype; - enum omap_rfbi_parallelmode parallelmode; - - switch (bpp) { - case 12: - datatype = OMAP_DSS_RFBI_DATATYPE_12; - break; - case 16: - datatype = OMAP_DSS_RFBI_DATATYPE_16; - break; - case 18: - datatype = OMAP_DSS_RFBI_DATATYPE_18; - break; - case 24: - datatype = OMAP_DSS_RFBI_DATATYPE_24; - break; - default: - BUG(); - return 1; - } - rfbi.datatype = datatype; - - switch (lines) { - case 8: - parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8; - break; - case 9: - parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9; - break; - case 12: - parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12; - break; - case 16: - parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16; - break; - default: - BUG(); - return 1; - } - rfbi.parallelmode = parallelmode; - - if ((bpp % lines) == 0) { - switch (bpp / lines) { - case 1: - cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1; - break; - case 2: - cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1; - break; - case 3: - cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1; - break; - default: - BUG(); - return 1; - } - } else if ((2 * bpp % lines) == 0) { - if ((2 * bpp / lines) == 3) - cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2; - else { - BUG(); - return 1; - } - } else { - BUG(); - return 1; - } - - switch (cycleformat) { - case OMAP_DSS_RFBI_CYCLEFORMAT_1_1: - cycle1 = lines; - break; - - case OMAP_DSS_RFBI_CYCLEFORMAT_2_1: - cycle1 = lines; - cycle2 = lines; - break; - - case OMAP_DSS_RFBI_CYCLEFORMAT_3_1: - cycle1 = lines; - cycle2 = lines; - cycle3 = lines; - break; - - case OMAP_DSS_RFBI_CYCLEFORMAT_3_2: - cycle1 = lines; - cycle2 = (lines / 2) | ((lines / 2) << 16); - cycle3 = (lines << 16); - break; - } - - rfbi_enable_clocks(1); - - REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */ - - l = 0; - l |= FLD_VAL(parallelmode, 1, 0); - l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */ - l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */ - l |= FLD_VAL(datatype, 6, 5); - /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */ - l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */ - l |= FLD_VAL(cycleformat, 10, 9); - l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */ - l |= FLD_VAL(0, 16, 16); /* A0POLARITY */ - l |= FLD_VAL(0, 17, 17); /* REPOLARITY */ - l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */ - l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */ - l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */ - l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */ - rfbi_write_reg(RFBI_CONFIG(rfbi_module), l); - - rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1); - rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2); - rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3); - - - l = rfbi_read_reg(RFBI_CONTROL); - l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */ - l = FLD_MOD(l, 0, 1, 1); /* clear bypass */ - rfbi_write_reg(RFBI_CONTROL, l); - - - DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n", - bpp, lines, cycle1, cycle2, cycle3); - - rfbi_enable_clocks(0); - - return 0; -} -EXPORT_SYMBOL(rfbi_configure); - -int omap_rfbi_prepare_update(struct omap_dss_device *dssdev, - u16 *x, u16 *y, u16 *w, u16 *h) -{ - u16 dw, dh; - - dssdev->driver->get_resolution(dssdev, &dw, &dh); - - if (*x > dw || *y > dh) - return -EINVAL; - - if (*x + *w > dw) - return -EINVAL; - - if (*y + *h > dh) - return -EINVAL; - - if (*w == 1) - return -EINVAL; - - if (*w == 0 || *h == 0) - return -EINVAL; - - if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { - dss_setup_partial_planes(dssdev, x, y, w, h, true); - dispc_set_lcd_size(dssdev->manager->id, *w, *h); - } - - return 0; -} -EXPORT_SYMBOL(omap_rfbi_prepare_update); - -int omap_rfbi_update(struct omap_dss_device *dssdev, - u16 x, u16 y, u16 w, u16 h, - void (*callback)(void *), void *data) -{ - if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { - rfbi_transfer_area(dssdev, w, h, callback, data); - } else { - struct omap_overlay *ovl; - void __iomem *addr; - int scr_width; - - ovl = dssdev->manager->overlays[0]; - scr_width = ovl->info.screen_width; - addr = ovl->info.vaddr; - - omap_rfbi_write_pixels(addr, scr_width, x, y, w, h); - - callback(data); - } - - return 0; -} -EXPORT_SYMBOL(omap_rfbi_update); - -void rfbi_dump_regs(struct seq_file *s) -{ -#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) - - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - - DUMPREG(RFBI_REVISION); - DUMPREG(RFBI_SYSCONFIG); - DUMPREG(RFBI_SYSSTATUS); - DUMPREG(RFBI_CONTROL); - DUMPREG(RFBI_PIXEL_CNT); - DUMPREG(RFBI_LINE_NUMBER); - DUMPREG(RFBI_CMD); - DUMPREG(RFBI_PARAM); - DUMPREG(RFBI_DATA); - DUMPREG(RFBI_READ); - DUMPREG(RFBI_STATUS); - - DUMPREG(RFBI_CONFIG(0)); - DUMPREG(RFBI_ONOFF_TIME(0)); - DUMPREG(RFBI_CYCLE_TIME(0)); - DUMPREG(RFBI_DATA_CYCLE1(0)); - DUMPREG(RFBI_DATA_CYCLE2(0)); - DUMPREG(RFBI_DATA_CYCLE3(0)); - - DUMPREG(RFBI_CONFIG(1)); - DUMPREG(RFBI_ONOFF_TIME(1)); - DUMPREG(RFBI_CYCLE_TIME(1)); - DUMPREG(RFBI_DATA_CYCLE1(1)); - DUMPREG(RFBI_DATA_CYCLE2(1)); - DUMPREG(RFBI_DATA_CYCLE3(1)); - - DUMPREG(RFBI_VSYNC_WIDTH); - DUMPREG(RFBI_HSYNC_WIDTH); - - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -#undef DUMPREG -} - -int rfbi_init(void) -{ - u32 rev; - u32 l; - - spin_lock_init(&rfbi.cmd_lock); - - init_completion(&rfbi.cmd_done); - atomic_set(&rfbi.cmd_fifo_full, 0); - atomic_set(&rfbi.cmd_pending, 0); - - rfbi.base = ioremap(RFBI_BASE, SZ_256); - if (!rfbi.base) { - DSSERR("can't ioremap RFBI\n"); - return -ENOMEM; - } - - rfbi_enable_clocks(1); - - msleep(10); - - rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000; - - /* Enable autoidle and smart-idle */ - l = rfbi_read_reg(RFBI_SYSCONFIG); - l |= (1 << 0) | (2 << 3); - rfbi_write_reg(RFBI_SYSCONFIG, l); - - rev = rfbi_read_reg(RFBI_REVISION); - printk(KERN_INFO "OMAP RFBI rev %d.%d\n", - FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); - - rfbi_enable_clocks(0); - - return 0; -} - -void rfbi_exit(void) -{ - DSSDBG("rfbi_exit\n"); - - iounmap(rfbi.base); -} - -int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev) -{ - int r; - - r = omap_dss_start_device(dssdev); - if (r) { - DSSERR("failed to start device\n"); - goto err0; - } - - r = omap_dispc_register_isr(framedone_callback, NULL, - DISPC_IRQ_FRAMEDONE); - if (r) { - DSSERR("can't get FRAMEDONE irq\n"); - goto err1; - } - - dispc_set_lcd_display_type(dssdev->manager->id, - OMAP_DSS_LCD_DISPLAY_TFT); - - dispc_set_parallel_interface_mode(dssdev->manager->id, - OMAP_DSS_PARALLELMODE_RFBI); - - dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size); - - rfbi_configure(dssdev->phy.rfbi.channel, - dssdev->ctrl.pixel_size, - dssdev->phy.rfbi.data_lines); - - rfbi_set_timings(dssdev->phy.rfbi.channel, - &dssdev->ctrl.rfbi_timings); - - - return 0; -err1: - omap_dss_stop_device(dssdev); -err0: - return r; -} -EXPORT_SYMBOL(omapdss_rfbi_display_enable); - -void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev) -{ - omap_dispc_unregister_isr(framedone_callback, NULL, - DISPC_IRQ_FRAMEDONE); - omap_dss_stop_device(dssdev); -} -EXPORT_SYMBOL(omapdss_rfbi_display_disable); - -int rfbi_init_display(struct omap_dss_device *dssdev) -{ - rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev; - dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; - return 0; -} diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c deleted file mode 100644 index b64adf7dfc8..00000000000 --- a/drivers/video/omap2/dss/sdi.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/sdi.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "SDI" - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/regulator/consumer.h> - -#include <plat/display.h> -#include <plat/cpu.h> -#include "dss.h" - -static struct { - bool skip_init; - bool update_enabled; - struct regulator *vdds_sdi_reg; -} sdi; - -static void sdi_basic_init(struct omap_dss_device *dssdev) - -{ - dispc_set_parallel_interface_mode(dssdev->manager->id, - OMAP_DSS_PARALLELMODE_BYPASS); - - dispc_set_lcd_display_type(dssdev->manager->id, - OMAP_DSS_LCD_DISPLAY_TFT); - - dispc_set_tft_data_lines(dssdev->manager->id, 24); - dispc_lcd_enable_signal_polarity(1); -} - -int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) -{ - struct omap_video_timings *t = &dssdev->panel.timings; - struct dss_clock_info dss_cinfo; - struct dispc_clock_info dispc_cinfo; - u16 lck_div, pck_div; - unsigned long fck; - unsigned long pck; - int r; - - r = omap_dss_start_device(dssdev); - if (r) { - DSSERR("failed to start device\n"); - goto err0; - } - - r = regulator_enable(sdi.vdds_sdi_reg); - if (r) - goto err1; - - /* In case of skip_init sdi_init has already enabled the clocks */ - if (!sdi.skip_init) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - - sdi_basic_init(dssdev); - - /* 15.5.9.1.2 */ - dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF; - - dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, - dssdev->panel.acbi, dssdev->panel.acb); - - if (!sdi.skip_init) { - r = dss_calc_clock_div(1, t->pixel_clock * 1000, - &dss_cinfo, &dispc_cinfo); - } else { - r = dss_get_clock_div(&dss_cinfo); - r = dispc_get_clock_div(dssdev->manager->id, &dispc_cinfo); - } - - if (r) - goto err2; - - fck = dss_cinfo.fck; - lck_div = dispc_cinfo.lck_div; - pck_div = dispc_cinfo.pck_div; - - pck = fck / lck_div / pck_div / 1000; - - if (pck != t->pixel_clock) { - DSSWARN("Could not find exact pixel clock. Requested %d kHz, " - "got %lu kHz\n", - t->pixel_clock, pck); - - t->pixel_clock = pck; - } - - - dispc_set_lcd_timings(dssdev->manager->id, t); - - r = dss_set_clock_div(&dss_cinfo); - if (r) - goto err2; - - r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); - if (r) - goto err2; - - if (!sdi.skip_init) { - dss_sdi_init(dssdev->phy.sdi.datapairs); - r = dss_sdi_enable(); - if (r) - goto err1; - mdelay(2); - } - - dssdev->manager->enable(dssdev->manager); - - sdi.skip_init = 0; - - return 0; -err2: - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); - regulator_disable(sdi.vdds_sdi_reg); -err1: - omap_dss_stop_device(dssdev); -err0: - return r; -} -EXPORT_SYMBOL(omapdss_sdi_display_enable); - -void omapdss_sdi_display_disable(struct omap_dss_device *dssdev) -{ - dssdev->manager->disable(dssdev->manager); - - dss_sdi_disable(); - - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); - - regulator_disable(sdi.vdds_sdi_reg); - - omap_dss_stop_device(dssdev); -} -EXPORT_SYMBOL(omapdss_sdi_display_disable); - -int sdi_init_display(struct omap_dss_device *dssdev) -{ - DSSDBG("SDI init\n"); - - return 0; -} - -int sdi_init(bool skip_init) -{ - /* we store this for first display enable, then clear it */ - sdi.skip_init = skip_init; - - sdi.vdds_sdi_reg = dss_get_vdds_sdi(); - if (IS_ERR(sdi.vdds_sdi_reg)) { - DSSERR("can't get VDDS_SDI regulator\n"); - return PTR_ERR(sdi.vdds_sdi_reg); - } - /* - * Enable clocks already here, otherwise there would be a toggle - * of them until sdi_display_enable is called. - */ - if (skip_init) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - return 0; -} - -void sdi_exit(void) -{ -} diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c deleted file mode 100644 index eff35050e28..00000000000 --- a/drivers/video/omap2/dss/venc.c +++ /dev/null @@ -1,742 +0,0 @@ -/* - * linux/drivers/video/omap2/dss/venc.c - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * VENC settings from TI's DSS driver - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define DSS_SUBSYS_NAME "VENC" - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/mutex.h> -#include <linux/completion.h> -#include <linux/delay.h> -#include <linux/string.h> -#include <linux/seq_file.h> -#include <linux/platform_device.h> -#include <linux/regulator/consumer.h> - -#include <plat/display.h> -#include <plat/cpu.h> - -#include "dss.h" - -#define VENC_BASE 0x48050C00 - -/* Venc registers */ -#define VENC_REV_ID 0x00 -#define VENC_STATUS 0x04 -#define VENC_F_CONTROL 0x08 -#define VENC_VIDOUT_CTRL 0x10 -#define VENC_SYNC_CTRL 0x14 -#define VENC_LLEN 0x1C -#define VENC_FLENS 0x20 -#define VENC_HFLTR_CTRL 0x24 -#define VENC_CC_CARR_WSS_CARR 0x28 -#define VENC_C_PHASE 0x2C -#define VENC_GAIN_U 0x30 -#define VENC_GAIN_V 0x34 -#define VENC_GAIN_Y 0x38 -#define VENC_BLACK_LEVEL 0x3C -#define VENC_BLANK_LEVEL 0x40 -#define VENC_X_COLOR 0x44 -#define VENC_M_CONTROL 0x48 -#define VENC_BSTAMP_WSS_DATA 0x4C -#define VENC_S_CARR 0x50 -#define VENC_LINE21 0x54 -#define VENC_LN_SEL 0x58 -#define VENC_L21__WC_CTL 0x5C -#define VENC_HTRIGGER_VTRIGGER 0x60 -#define VENC_SAVID__EAVID 0x64 -#define VENC_FLEN__FAL 0x68 -#define VENC_LAL__PHASE_RESET 0x6C -#define VENC_HS_INT_START_STOP_X 0x70 -#define VENC_HS_EXT_START_STOP_X 0x74 -#define VENC_VS_INT_START_X 0x78 -#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C -#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 -#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 -#define VENC_VS_EXT_STOP_Y 0x88 -#define VENC_AVID_START_STOP_X 0x90 -#define VENC_AVID_START_STOP_Y 0x94 -#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 -#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 -#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 -#define VENC_TVDETGP_INT_START_STOP_X 0xB0 -#define VENC_TVDETGP_INT_START_STOP_Y 0xB4 -#define VENC_GEN_CTRL 0xB8 -#define VENC_OUTPUT_CONTROL 0xC4 -#define VENC_OUTPUT_TEST 0xC8 -#define VENC_DAC_B__DAC_C 0xC8 - -struct venc_config { - u32 f_control; - u32 vidout_ctrl; - u32 sync_ctrl; - u32 llen; - u32 flens; - u32 hfltr_ctrl; - u32 cc_carr_wss_carr; - u32 c_phase; - u32 gain_u; - u32 gain_v; - u32 gain_y; - u32 black_level; - u32 blank_level; - u32 x_color; - u32 m_control; - u32 bstamp_wss_data; - u32 s_carr; - u32 line21; - u32 ln_sel; - u32 l21__wc_ctl; - u32 htrigger_vtrigger; - u32 savid__eavid; - u32 flen__fal; - u32 lal__phase_reset; - u32 hs_int_start_stop_x; - u32 hs_ext_start_stop_x; - u32 vs_int_start_x; - u32 vs_int_stop_x__vs_int_start_y; - u32 vs_int_stop_y__vs_ext_start_x; - u32 vs_ext_stop_x__vs_ext_start_y; - u32 vs_ext_stop_y; - u32 avid_start_stop_x; - u32 avid_start_stop_y; - u32 fid_int_start_x__fid_int_start_y; - u32 fid_int_offset_y__fid_ext_start_x; - u32 fid_ext_start_y__fid_ext_offset_y; - u32 tvdetgp_int_start_stop_x; - u32 tvdetgp_int_start_stop_y; - u32 gen_ctrl; -}; - -/* from TRM */ -static const struct venc_config venc_config_pal_trm = { - .f_control = 0, - .vidout_ctrl = 1, - .sync_ctrl = 0x40, - .llen = 0x35F, /* 863 */ - .flens = 0x270, /* 624 */ - .hfltr_ctrl = 0, - .cc_carr_wss_carr = 0x2F7225ED, - .c_phase = 0, - .gain_u = 0x111, - .gain_v = 0x181, - .gain_y = 0x140, - .black_level = 0x3B, - .blank_level = 0x3B, - .x_color = 0x7, - .m_control = 0x2, - .bstamp_wss_data = 0x3F, - .s_carr = 0x2A098ACB, - .line21 = 0, - .ln_sel = 0x01290015, - .l21__wc_ctl = 0x0000F603, - .htrigger_vtrigger = 0, - - .savid__eavid = 0x06A70108, - .flen__fal = 0x00180270, - .lal__phase_reset = 0x00040135, - .hs_int_start_stop_x = 0x00880358, - .hs_ext_start_stop_x = 0x000F035F, - .vs_int_start_x = 0x01A70000, - .vs_int_stop_x__vs_int_start_y = 0x000001A7, - .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, - .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, - .vs_ext_stop_y = 0x00000025, - .avid_start_stop_x = 0x03530083, - .avid_start_stop_y = 0x026C002E, - .fid_int_start_x__fid_int_start_y = 0x0001008A, - .fid_int_offset_y__fid_ext_start_x = 0x002E0138, - .fid_ext_start_y__fid_ext_offset_y = 0x01380001, - - .tvdetgp_int_start_stop_x = 0x00140001, - .tvdetgp_int_start_stop_y = 0x00010001, - .gen_ctrl = 0x00FF0000, -}; - -/* from TRM */ -static const struct venc_config venc_config_ntsc_trm = { - .f_control = 0, - .vidout_ctrl = 1, - .sync_ctrl = 0x8040, - .llen = 0x359, - .flens = 0x20C, - .hfltr_ctrl = 0, - .cc_carr_wss_carr = 0x043F2631, - .c_phase = 0, - .gain_u = 0x102, - .gain_v = 0x16C, - .gain_y = 0x12F, - .black_level = 0x43, - .blank_level = 0x38, - .x_color = 0x7, - .m_control = 0x1, - .bstamp_wss_data = 0x38, - .s_carr = 0x21F07C1F, - .line21 = 0, - .ln_sel = 0x01310011, - .l21__wc_ctl = 0x0000F003, - .htrigger_vtrigger = 0, - - .savid__eavid = 0x069300F4, - .flen__fal = 0x0016020C, - .lal__phase_reset = 0x00060107, - .hs_int_start_stop_x = 0x008E0350, - .hs_ext_start_stop_x = 0x000F0359, - .vs_int_start_x = 0x01A00000, - .vs_int_stop_x__vs_int_start_y = 0x020701A0, - .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, - .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, - .vs_ext_stop_y = 0x00000006, - .avid_start_stop_x = 0x03480078, - .avid_start_stop_y = 0x02060024, - .fid_int_start_x__fid_int_start_y = 0x0001008A, - .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, - .fid_ext_start_y__fid_ext_offset_y = 0x01060006, - - .tvdetgp_int_start_stop_x = 0x00140001, - .tvdetgp_int_start_stop_y = 0x00010001, - .gen_ctrl = 0x00F90000, -}; - -static const struct venc_config venc_config_pal_bdghi = { - .f_control = 0, - .vidout_ctrl = 0, - .sync_ctrl = 0, - .hfltr_ctrl = 0, - .x_color = 0, - .line21 = 0, - .ln_sel = 21, - .htrigger_vtrigger = 0, - .tvdetgp_int_start_stop_x = 0x00140001, - .tvdetgp_int_start_stop_y = 0x00010001, - .gen_ctrl = 0x00FB0000, - - .llen = 864-1, - .flens = 625-1, - .cc_carr_wss_carr = 0x2F7625ED, - .c_phase = 0xDF, - .gain_u = 0x111, - .gain_v = 0x181, - .gain_y = 0x140, - .black_level = 0x3e, - .blank_level = 0x3e, - .m_control = 0<<2 | 1<<1, - .bstamp_wss_data = 0x42, - .s_carr = 0x2a098acb, - .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, - .savid__eavid = 0x06A70108, - .flen__fal = 23<<16 | 624<<0, - .lal__phase_reset = 2<<17 | 310<<0, - .hs_int_start_stop_x = 0x00920358, - .hs_ext_start_stop_x = 0x000F035F, - .vs_int_start_x = 0x1a7<<16, - .vs_int_stop_x__vs_int_start_y = 0x000601A7, - .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, - .vs_ext_stop_x__vs_ext_start_y = 0x27101af, - .vs_ext_stop_y = 0x05, - .avid_start_stop_x = 0x03530082, - .avid_start_stop_y = 0x0270002E, - .fid_int_start_x__fid_int_start_y = 0x0005008A, - .fid_int_offset_y__fid_ext_start_x = 0x002E0138, - .fid_ext_start_y__fid_ext_offset_y = 0x01380005, -}; - -const struct omap_video_timings omap_dss_pal_timings = { - .x_res = 720, - .y_res = 574, - .pixel_clock = 13500, - .hsw = 64, - .hfp = 12, - .hbp = 68, - .vsw = 5, - .vfp = 5, - .vbp = 41, -}; -EXPORT_SYMBOL(omap_dss_pal_timings); - -const struct omap_video_timings omap_dss_ntsc_timings = { - .x_res = 720, - .y_res = 482, - .pixel_clock = 13500, - .hsw = 64, - .hfp = 16, - .hbp = 58, - .vsw = 6, - .vfp = 6, - .vbp = 31, -}; -EXPORT_SYMBOL(omap_dss_ntsc_timings); - -static struct { - void __iomem *base; - struct mutex venc_lock; - u32 wss_data; - struct regulator *vdda_dac_reg; -} venc; - -static inline void venc_write_reg(int idx, u32 val) -{ - __raw_writel(val, venc.base + idx); -} - -static inline u32 venc_read_reg(int idx) -{ - u32 l = __raw_readl(venc.base + idx); - return l; -} - -static void venc_write_config(const struct venc_config *config) -{ - DSSDBG("write venc conf\n"); - - venc_write_reg(VENC_LLEN, config->llen); - venc_write_reg(VENC_FLENS, config->flens); - venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); - venc_write_reg(VENC_C_PHASE, config->c_phase); - venc_write_reg(VENC_GAIN_U, config->gain_u); - venc_write_reg(VENC_GAIN_V, config->gain_v); - venc_write_reg(VENC_GAIN_Y, config->gain_y); - venc_write_reg(VENC_BLACK_LEVEL, config->black_level); - venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); - venc_write_reg(VENC_M_CONTROL, config->m_control); - venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | - venc.wss_data); - venc_write_reg(VENC_S_CARR, config->s_carr); - venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); - venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); - venc_write_reg(VENC_FLEN__FAL, config->flen__fal); - venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); - venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); - venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); - venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); - venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, - config->vs_int_stop_x__vs_int_start_y); - venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, - config->vs_int_stop_y__vs_ext_start_x); - venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, - config->vs_ext_stop_x__vs_ext_start_y); - venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); - venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); - venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); - venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, - config->fid_int_start_x__fid_int_start_y); - venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, - config->fid_int_offset_y__fid_ext_start_x); - venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, - config->fid_ext_start_y__fid_ext_offset_y); - - venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); - venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); - venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); - venc_write_reg(VENC_X_COLOR, config->x_color); - venc_write_reg(VENC_LINE21, config->line21); - venc_write_reg(VENC_LN_SEL, config->ln_sel); - venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); - venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, - config->tvdetgp_int_start_stop_x); - venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, - config->tvdetgp_int_start_stop_y); - venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); - venc_write_reg(VENC_F_CONTROL, config->f_control); - venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); -} - -static void venc_reset(void) -{ - int t = 1000; - - venc_write_reg(VENC_F_CONTROL, 1<<8); - while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { - if (--t == 0) { - DSSERR("Failed to reset venc\n"); - return; - } - } - - /* the magical sleep that makes things work */ - msleep(20); -} - -static void venc_enable_clocks(int enable) -{ - if (enable) - dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | - DSS_CLK_96M); - else - dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | - DSS_CLK_96M); -} - -static const struct venc_config *venc_timings_to_config( - struct omap_video_timings *timings) -{ - if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) - return &venc_config_pal_trm; - - if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) - return &venc_config_ntsc_trm; - - BUG(); -} - -static void venc_power_on(struct omap_dss_device *dssdev) -{ - u32 l; - - venc_enable_clocks(1); - - venc_reset(); - venc_write_config(venc_timings_to_config(&dssdev->panel.timings)); - - dss_set_venc_output(dssdev->phy.venc.type); - dss_set_dac_pwrdn_bgz(1); - - l = 0; - - if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) - l |= 1 << 1; - else /* S-Video */ - l |= (1 << 0) | (1 << 2); - - if (dssdev->phy.venc.invert_polarity == false) - l |= 1 << 3; - - venc_write_reg(VENC_OUTPUT_CONTROL, l); - - dispc_set_digit_size(dssdev->panel.timings.x_res, - dssdev->panel.timings.y_res/2); - - regulator_enable(venc.vdda_dac_reg); - - if (dssdev->platform_enable) - dssdev->platform_enable(dssdev); - - dssdev->manager->enable(dssdev->manager); -} - -static void venc_power_off(struct omap_dss_device *dssdev) -{ - venc_write_reg(VENC_OUTPUT_CONTROL, 0); - dss_set_dac_pwrdn_bgz(0); - - dssdev->manager->disable(dssdev->manager); - - if (dssdev->platform_disable) - dssdev->platform_disable(dssdev); - - regulator_disable(venc.vdda_dac_reg); - - venc_enable_clocks(0); -} - - - - - -/* driver */ -static int venc_panel_probe(struct omap_dss_device *dssdev) -{ - dssdev->panel.timings = omap_dss_pal_timings; - - return 0; -} - -static void venc_panel_remove(struct omap_dss_device *dssdev) -{ -} - -static int venc_panel_enable(struct omap_dss_device *dssdev) -{ - int r = 0; - - DSSDBG("venc_enable_display\n"); - - mutex_lock(&venc.venc_lock); - - if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { - r = -EINVAL; - goto err1; - } - - venc_power_on(dssdev); - - venc.wss_data = 0; - - dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; - - /* wait couple of vsyncs until enabling the LCD */ - msleep(50); - -err1: - mutex_unlock(&venc.venc_lock); - - return r; -} - -static void venc_panel_disable(struct omap_dss_device *dssdev) -{ - DSSDBG("venc_disable_display\n"); - - mutex_lock(&venc.venc_lock); - - if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED) - goto end; - - if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) { - /* suspended is the same as disabled with venc */ - dssdev->state = OMAP_DSS_DISPLAY_DISABLED; - goto end; - } - - venc_power_off(dssdev); - - /* wait at least 5 vsyncs after disabling the LCD */ - msleep(100); - - dssdev->state = OMAP_DSS_DISPLAY_DISABLED; -end: - mutex_unlock(&venc.venc_lock); -} - -static int venc_panel_suspend(struct omap_dss_device *dssdev) -{ - venc_panel_disable(dssdev); - return 0; -} - -static int venc_panel_resume(struct omap_dss_device *dssdev) -{ - return venc_panel_enable(dssdev); -} - -static enum omap_dss_update_mode venc_get_update_mode( - struct omap_dss_device *dssdev) -{ - return OMAP_DSS_UPDATE_AUTO; -} - -static int venc_set_update_mode(struct omap_dss_device *dssdev, - enum omap_dss_update_mode mode) -{ - if (mode != OMAP_DSS_UPDATE_AUTO) - return -EINVAL; - return 0; -} - -static void venc_get_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings) -{ - *timings = dssdev->panel.timings; -} - -static void venc_set_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings) -{ - DSSDBG("venc_set_timings\n"); - - /* Reset WSS data when the TV standard changes. */ - if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings))) - venc.wss_data = 0; - - dssdev->panel.timings = *timings; - if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { - /* turn the venc off and on to get new timings to use */ - venc_panel_disable(dssdev); - venc_panel_enable(dssdev); - } -} - -static int venc_check_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings) -{ - DSSDBG("venc_check_timings\n"); - - if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) - return 0; - - if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) - return 0; - - return -EINVAL; -} - -static u32 venc_get_wss(struct omap_dss_device *dssdev) -{ - /* Invert due to VENC_L21_WC_CTL:INV=1 */ - return (venc.wss_data >> 8) ^ 0xfffff; -} - -static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) -{ - const struct venc_config *config; - - DSSDBG("venc_set_wss\n"); - - mutex_lock(&venc.venc_lock); - - config = venc_timings_to_config(&dssdev->panel.timings); - - /* Invert due to VENC_L21_WC_CTL:INV=1 */ - venc.wss_data = (wss ^ 0xfffff) << 8; - - venc_enable_clocks(1); - - venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | - venc.wss_data); - - venc_enable_clocks(0); - - mutex_unlock(&venc.venc_lock); - - return 0; -} - -static struct omap_dss_driver venc_driver = { - .probe = venc_panel_probe, - .remove = venc_panel_remove, - - .enable = venc_panel_enable, - .disable = venc_panel_disable, - .suspend = venc_panel_suspend, - .resume = venc_panel_resume, - - .get_resolution = omapdss_default_get_resolution, - .get_recommended_bpp = omapdss_default_get_recommended_bpp, - - .set_update_mode = venc_set_update_mode, - .get_update_mode = venc_get_update_mode, - - .get_timings = venc_get_timings, - .set_timings = venc_set_timings, - .check_timings = venc_check_timings, - - .get_wss = venc_get_wss, - .set_wss = venc_set_wss, - - .driver = { - .name = "venc", - .owner = THIS_MODULE, - }, -}; -/* driver end */ - - - -int venc_init(struct platform_device *pdev) -{ - u8 rev_id; - - mutex_init(&venc.venc_lock); - - venc.wss_data = 0; - - venc.base = ioremap(VENC_BASE, SZ_1K); - if (!venc.base) { - DSSERR("can't ioremap VENC\n"); - return -ENOMEM; - } - - venc.vdda_dac_reg = dss_get_vdda_dac(); - if (IS_ERR(venc.vdda_dac_reg)) { - iounmap(venc.base); - DSSERR("can't get VDDA_DAC regulator\n"); - return PTR_ERR(venc.vdda_dac_reg); - } - - venc_enable_clocks(1); - - rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); - printk(KERN_INFO "OMAP VENC rev %d\n", rev_id); - - venc_enable_clocks(0); - - return omap_dss_register_driver(&venc_driver); -} - -void venc_exit(void) -{ - omap_dss_unregister_driver(&venc_driver); - - iounmap(venc.base); -} - -int venc_init_display(struct omap_dss_device *dssdev) -{ - DSSDBG("init_display\n"); - - return 0; -} - -void venc_dump_regs(struct seq_file *s) -{ -#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) - - venc_enable_clocks(1); - - DUMPREG(VENC_F_CONTROL); - DUMPREG(VENC_VIDOUT_CTRL); - DUMPREG(VENC_SYNC_CTRL); - DUMPREG(VENC_LLEN); - DUMPREG(VENC_FLENS); - DUMPREG(VENC_HFLTR_CTRL); - DUMPREG(VENC_CC_CARR_WSS_CARR); - DUMPREG(VENC_C_PHASE); - DUMPREG(VENC_GAIN_U); - DUMPREG(VENC_GAIN_V); - DUMPREG(VENC_GAIN_Y); - DUMPREG(VENC_BLACK_LEVEL); - DUMPREG(VENC_BLANK_LEVEL); - DUMPREG(VENC_X_COLOR); - DUMPREG(VENC_M_CONTROL); - DUMPREG(VENC_BSTAMP_WSS_DATA); - DUMPREG(VENC_S_CARR); - DUMPREG(VENC_LINE21); - DUMPREG(VENC_LN_SEL); - DUMPREG(VENC_L21__WC_CTL); - DUMPREG(VENC_HTRIGGER_VTRIGGER); - DUMPREG(VENC_SAVID__EAVID); - DUMPREG(VENC_FLEN__FAL); - DUMPREG(VENC_LAL__PHASE_RESET); - DUMPREG(VENC_HS_INT_START_STOP_X); - DUMPREG(VENC_HS_EXT_START_STOP_X); - DUMPREG(VENC_VS_INT_START_X); - DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); - DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); - DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); - DUMPREG(VENC_VS_EXT_STOP_Y); - DUMPREG(VENC_AVID_START_STOP_X); - DUMPREG(VENC_AVID_START_STOP_Y); - DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); - DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); - DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); - DUMPREG(VENC_TVDETGP_INT_START_STOP_X); - DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); - DUMPREG(VENC_GEN_CTRL); - DUMPREG(VENC_OUTPUT_CONTROL); - DUMPREG(VENC_OUTPUT_TEST); - - venc_enable_clocks(0); - -#undef DUMPREG -} |