diff options
Diffstat (limited to 'drivers/usb/chipidea/ci.h')
| -rw-r--r-- | drivers/usb/chipidea/ci.h | 171 |
1 files changed, 110 insertions, 61 deletions
diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h index b0a6bce064c..9563cb56d56 100644 --- a/drivers/usb/chipidea/ci.h +++ b/drivers/usb/chipidea/ci.h @@ -17,19 +17,49 @@ #include <linux/irqreturn.h> #include <linux/usb.h> #include <linux/usb/gadget.h> +#include <linux/usb/otg-fsm.h> /****************************************************************************** * DEFINE *****************************************************************************/ #define TD_PAGE_COUNT 5 -#define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */ +#define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */ #define ENDPT_MAX 32 /****************************************************************************** + * REGISTERS + *****************************************************************************/ +/* register indices */ +enum ci_hw_regs { + CAP_CAPLENGTH, + CAP_HCCPARAMS, + CAP_DCCPARAMS, + CAP_TESTMODE, + CAP_LAST = CAP_TESTMODE, + OP_USBCMD, + OP_USBSTS, + OP_USBINTR, + OP_DEVICEADDR, + OP_ENDPTLISTADDR, + OP_PORTSC, + OP_DEVLC, + OP_OTGSC, + OP_USBMODE, + OP_ENDPTSETUPSTAT, + OP_ENDPTPRIME, + OP_ENDPTFLUSH, + OP_ENDPTSTAT, + OP_ENDPTCOMPLETE, + OP_ENDPTCTRL, + /* endptctrl1..15 follow */ + OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, +}; + +/****************************************************************************** * STRUCTURES *****************************************************************************/ /** - * struct ci13xxx_ep - endpoint representation + * struct ci_hw_ep - endpoint representation * @ep: endpoint structure for gadget drivers * @dir: endpoint direction (TX/RX) * @num: endpoint number @@ -41,7 +71,7 @@ * @lock: pointer to controller's spinlock * @td_pool: pointer to controller's TD pool */ -struct ci13xxx_ep { +struct ci_hw_ep { struct usb_ep ep; u8 dir; u8 num; @@ -49,15 +79,16 @@ struct ci13xxx_ep { char name[16]; struct { struct list_head queue; - struct ci13xxx_qh *ptr; + struct ci_hw_qh *ptr; dma_addr_t dma; } qh; int wedge; /* global resources */ - struct ci13xxx *ci; + struct ci_hdrc *ci; spinlock_t *lock; struct dma_pool *td_pool; + struct td_node *pending_td; }; enum ci_role { @@ -74,9 +105,9 @@ enum ci_role { * name: role name string (host/gadget) */ struct ci_role_driver { - int (*start)(struct ci13xxx *); - void (*stop)(struct ci13xxx *); - irqreturn_t (*irq)(struct ci13xxx *); + int (*start)(struct ci_hdrc *); + void (*stop)(struct ci_hdrc *); + irqreturn_t (*irq)(struct ci_hdrc *); const char *name; }; @@ -97,11 +128,11 @@ struct hw_bank { void __iomem *cap; void __iomem *op; size_t size; - void __iomem **regmap; + void __iomem *regmap[OP_LAST + 1]; }; /** - * struct ci13xxx - chipidea device representation + * struct ci_hdrc - chipidea device representation * @dev: pointer to parent device * @lock: access synchronization * @hw_bank: hardware register mapping @@ -109,6 +140,8 @@ struct hw_bank { * @roles: array of supported roles for this controller * @role: current role * @is_otg: if the device is otg-capable + * @fsm: otg finite state machine + * @fsm_timer: pointer to timer list of otg fsm * @work: work for role changing * @wq: workqueue thread * @qh_pool: allocation pool for queue heads @@ -116,7 +149,7 @@ struct hw_bank { * @gadget: device side representation for peripheral controller * @driver: gadget driver * @hw_ep_max: total number of endpoints supported by hardware - * @ci13xxx_ep: array of endpoints + * @ci_hw_ep: array of endpoints * @ep0_dir: ep0 direction * @ep0out: pointer to ep0 OUT endpoint * @ep0in: pointer to ep0 IN endpoint @@ -131,8 +164,12 @@ struct hw_bank { * @transceiver: pointer to USB PHY, if any * @hcd: pointer to usb_hcd for ehci host driver * @debugfs: root dentry for this controller in debugfs + * @id_event: indicates there is an id event, and handled at ci_otg_work + * @b_sess_valid_event: indicates there is a vbus event, and handled + * at ci_otg_work + * @imx28_write_fix: Freescale imx28 needs swp instruction for writing */ -struct ci13xxx { +struct ci_hdrc { struct device *dev; spinlock_t lock; struct hw_bank hw_bank; @@ -140,6 +177,8 @@ struct ci13xxx { struct ci_role_driver *roles[CI_ROLE_END]; enum ci_role role; bool is_otg; + struct otg_fsm fsm; + struct ci_otg_fsm_timer_list *fsm_timer; struct work_struct work; struct workqueue_struct *wq; @@ -149,9 +188,9 @@ struct ci13xxx { struct usb_gadget gadget; struct usb_gadget_driver *driver; unsigned hw_ep_max; - struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX]; + struct ci_hw_ep ci_hw_ep[ENDPT_MAX]; u32 ep0_dir; - struct ci13xxx_ep *ep0out, *ep0in; + struct ci_hw_ep *ep0out, *ep0in; struct usb_request *status; bool setaddr; @@ -160,22 +199,23 @@ struct ci13xxx { u8 suspended; u8 test_mode; - struct ci13xxx_platform_data *platdata; + struct ci_hdrc_platform_data *platdata; int vbus_active; - /* FIXME: some day, we'll not use global phy */ - bool global_phy; struct usb_phy *transceiver; struct usb_hcd *hcd; struct dentry *debugfs; + bool id_event; + bool b_sess_valid_event; + bool imx28_write_fix; }; -static inline struct ci_role_driver *ci_role(struct ci13xxx *ci) +static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) { BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]); return ci->roles[ci->role]; } -static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role) +static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) { int ret; @@ -191,7 +231,7 @@ static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role) return ret; } -static inline void ci_role_stop(struct ci13xxx *ci) +static inline void ci_role_stop(struct ci_hdrc *ci) { enum ci_role role = ci->role; @@ -203,38 +243,6 @@ static inline void ci_role_stop(struct ci13xxx *ci) ci->roles[role]->stop(ci); } -/****************************************************************************** - * REGISTERS - *****************************************************************************/ -/* register size */ -#define REG_BITS (32) - -/* register indices */ -enum ci13xxx_regs { - CAP_CAPLENGTH, - CAP_HCCPARAMS, - CAP_DCCPARAMS, - CAP_TESTMODE, - CAP_LAST = CAP_TESTMODE, - OP_USBCMD, - OP_USBSTS, - OP_USBINTR, - OP_DEVICEADDR, - OP_ENDPTLISTADDR, - OP_PORTSC, - OP_DEVLC, - OP_OTGSC, - OP_USBMODE, - OP_ENDPTSETUPSTAT, - OP_ENDPTPRIME, - OP_ENDPTFLUSH, - OP_ENDPTSTAT, - OP_ENDPTCOMPLETE, - OP_ENDPTCTRL, - /* endptctrl1..15 follow */ - OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, -}; - /** * hw_read: reads from a hw register * @reg: register index @@ -242,25 +250,45 @@ enum ci13xxx_regs { * * This function returns register contents */ -static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask) +static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) { return ioread32(ci->hw_bank.regmap[reg]) & mask; } +#ifdef CONFIG_SOC_IMX28 +static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) +{ + __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); +} +#else +static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) +{ +} +#endif + +static inline void __hw_write(struct ci_hdrc *ci, u32 val, + void __iomem *addr) +{ + if (ci->imx28_write_fix) + imx28_ci_writel(val, addr); + else + iowrite32(val, addr); +} + /** * hw_write: writes to a hw register * @reg: register index * @mask: bitfield mask * @data: new value */ -static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg, +static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, u32 data) { if (~mask) data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) | (data & mask); - iowrite32(data, ci->hw_bank.regmap[reg]); + __hw_write(ci, data, ci->hw_bank.regmap[reg]); } /** @@ -270,12 +298,12 @@ static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg, * * This function returns register contents */ -static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg, +static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) { u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; - iowrite32(val, ci->hw_bank.regmap[reg]); + __hw_write(ci, val, ci->hw_bank.regmap[reg]); return val; } @@ -287,7 +315,7 @@ static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg, * * This function returns register contents */ -static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg, +static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, u32 data) { u32 val = hw_read(ci, reg, ~0); @@ -296,10 +324,31 @@ static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg, return (val & mask) >> __ffs(mask); } -int hw_device_reset(struct ci13xxx *ci, u32 mode); +/** + * ci_otg_is_fsm_mode: runtime check if otg controller + * is in otg fsm mode. + */ +static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci) +{ +#ifdef CONFIG_USB_OTG_FSM + return ci->is_otg && ci->roles[CI_ROLE_HOST] && + ci->roles[CI_ROLE_GADGET]; +#else + return false; +#endif +} + +u32 hw_read_intr_enable(struct ci_hdrc *ci); + +u32 hw_read_intr_status(struct ci_hdrc *ci); + +int hw_device_reset(struct ci_hdrc *ci, u32 mode); + +int hw_port_test_set(struct ci_hdrc *ci, u8 mode); -int hw_port_test_set(struct ci13xxx *ci, u8 mode); +u8 hw_port_test_get(struct ci_hdrc *ci); -u8 hw_port_test_get(struct ci13xxx *ci); +int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, + u32 value, unsigned int timeout_ms); #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */ |