diff options
Diffstat (limited to 'drivers/staging/winbond')
34 files changed, 1489 insertions, 2985 deletions
diff --git a/drivers/staging/winbond/Kconfig b/drivers/staging/winbond/Kconfig index 132671d96d0..db5b053d9bc 100644 --- a/drivers/staging/winbond/Kconfig +++ b/drivers/staging/winbond/Kconfig @@ -1,6 +1,6 @@ config W35UND tristate "IS89C35 WLAN USB driver" - depends on MAC80211 && WLAN && USB && EXPERIMENTAL + depends on MAC80211 && WLAN && USB default n ---help--- This is highly experimental driver for Winbond WIFI card. @@ -8,4 +8,4 @@ config W35UND Hardware is present in some Kohjinsha subnotebooks, and in some stand-alone USB modules. Chipset name seems to be w89c35d. - Check http://code.google.com/p/winbondport/ for new version. + Check <http://code.google.com/p/winbondport/> for new version. diff --git a/drivers/staging/winbond/Makefile b/drivers/staging/winbond/Makefile index fb2b7d432b4..081d48db04c 100644 --- a/drivers/staging/winbond/Makefile +++ b/drivers/staging/winbond/Makefile @@ -1,6 +1,5 @@ -w35und-objs := \ +w35und-y := \ mds.o \ - mlmetxrx.o \ mto.o \ phy_calibration.o \ reg.o \ diff --git a/drivers/staging/winbond/TODO b/drivers/staging/winbond/TODO index 8c1baaf6d8a..b4c592a9684 100644 --- a/drivers/staging/winbond/TODO +++ b/drivers/staging/winbond/TODO @@ -3,10 +3,10 @@ TODO: - checkpatch cleanups - kerneldoc cleanups - fix severeCamelCaseInfestation - - remove typedefs - remove unused ioctls - use cfg80211 for regulatory stuff - fix 4k stack problems + - fix locking problems (it's done using atomics...) Please send patches to Greg Kroah-Hartman <greg@kroah.com> and Pavel Machek <pavel@ucw.cz> diff --git a/drivers/staging/winbond/core.h b/drivers/staging/winbond/core.h index b87d6c07600..fc0ef24fad3 100644 --- a/drivers/staging/winbond/core.h +++ b/drivers/staging/winbond/core.h @@ -2,41 +2,59 @@ #define __WINBOND_CORE_H #include <linux/wireless.h> +#include <linux/types.h> +#include <linux/delay.h> -#include "mlme_s.h" -#include "wbhal_s.h" +#include "wbhal.h" #include "mto.h" +#include "mac_structures.h" +#include "mds_s.h" + +#define MAX_NUM_TX_MMPDU 2 +#define MAX_MMPDU_SIZE 1512 +#define MAX_NUM_RX_MMPDU 6 + +struct mlme_frame { + s8 *pMMPDU; + u16 len; + u8 data_type; + u8 is_in_used; + + u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE]; + u8 TxMMPDUInUse[(MAX_NUM_TX_MMPDU + 3) & ~0x03]; + + u16 wNumTxMMPDU; + u16 wNumTxMMPDUDiscarded; + + u8 RxMMPDU[MAX_NUM_RX_MMPDU][MAX_MMPDU_SIZE]; + u8 SaveRxBufSlotInUse[(MAX_NUM_RX_MMPDU + 3) & ~0x03]; + + u16 wNumRxMMPDU; + u16 wNumRxMMPDUDiscarded; + + u16 wNumRxMMPDUInMLME; /* Number of the Rx MMPDU */ + u16 reserved_1; /* in MLME. */ + /* excluding the discarded */ +}; + #define WBLINUX_PACKET_ARRAY_SIZE (ETHERNET_TX_DESCRIPTORS*4) #define WB_MAX_LINK_NAME_LEN 40 struct wbsoft_priv { - u32 adapterIndex; /* 20060703.4 Add for using padapterContext - global adapter point */ - struct wb_local_para sLocalPara; /* Myself connected parameters */ - MLME_FRAME sMlmeFrame; /* connect to peerSTA parameters */ + struct mlme_frame sMlmeFrame; /* connect to peerSTA parameters */ struct wb35_mto_params sMtoPara; /* MTO_struct ... */ struct hw_data sHwData; /*For HAL */ struct wb35_mds Mds; - spinlock_t SpinLock; - - atomic_t ThreadCount; - u32 RxByteCount; u32 TxByteCount; - struct sk_buff *packet_return; - s32 netif_state_stop; /* 1: stop 0: normal */ - struct iw_statistics iw_stats; - - u8 LinkName[WB_MAX_LINK_NAME_LEN]; - bool enabled; }; diff --git a/drivers/staging/winbond/localpara.h b/drivers/staging/winbond/localpara.h index d7980575bed..8ca80ddda59 100644 --- a/drivers/staging/winbond/localpara.h +++ b/drivers/staging/winbond/localpara.h @@ -58,9 +58,13 @@ #define LOCAL_11B_BASIC_RATE_BITMAP 0x826 #define LOCAL_11B_OPERATION_RATE_BITMAP 0x826 #define LOCAL_11G_BASIC_RATE_BITMAP 0x826 /* 1, 2, 5.5, 11 */ -#define LOCAL_11G_OPERATION_RATE_BITMAP 0x130c1240 /* 6, 9, 12, 18, 24, 36, 48, 54 */ +#define LOCAL_11G_OPERATION_RATE_BITMAP 0x130c1240 /* 6, 9, 12, 18, + * 24, 36, 48, 54 + */ #define LOCAL_11A_BASIC_RATE_BITMAP 0x01001040 /* 6, 12, 24 */ -#define LOCAL_11A_OPERATION_RATE_BITMAP 0x120c0200 /* 9, 18, 36, 48, 54 */ +#define LOCAL_11A_OPERATION_RATE_BITMAP 0x120c0200 /* 9, 18, 36, + * 48, 54 + */ #define PWR_ACTIVE 0 @@ -137,10 +141,12 @@ struct wb_local_para { u8 iPowerSaveMode; /* 0 indicates on, 1 indicates off */ u8 ATIMmode; u8 ExcludeUnencrypted; - /* Unit ime count for the decision to enter PS mode */ + /* Unit time count for the decision to enter PS mode */ u16 CheckCountForPS; u8 boHasTxActivity;/* tx activity has occurred */ - u8 boMacPsValid; /* Power save mode obtained from H/W is valid or not */ + u8 boMacPsValid; /* Power save mode obtained + * from H/W is valid or not + */ /* Rate */ u8 TxRateMode; /* @@ -162,35 +168,57 @@ struct wb_local_para { u8 NumOfBRate; u8 NumOfSRate; - u8 NumOfDsssRateInSRate; /* number of DSSS rates in supported rate set */ + u8 NumOfDsssRateInSRate; /* number of DSSS rates in + * supported rate set + */ u8 reserved1; u32 dwBasicRateBitmap; /* bit map of basic rates */ - u32 dwSupportRateBitmap; /* bit map of all support rates including basic and operational rates */ + u32 dwSupportRateBitmap; /* bit map of all support rates + * including basic and operational + * rates + */ /* For SME/MLME handler */ - u16 wOldSTAindex; /* valid when boHandover=TRUE, store old connected STA index */ - u16 wConnectedSTAindex; /* Index of peerly connected AP or IBSS in the descriptionset. */ - u16 Association_ID; /* The Association ID in the (Re)Association Response frame. */ - u16 ListenInterval; /* The listen interval when SME invoking MLME_ (Re)Associate_Request(). */ + u16 wOldSTAindex; /* valid when boHandover=TRUE, + * store old connected STA index + */ + u16 wConnectedSTAindex; /* Index of peerly connected AP or + * IBSS in the descriptionset. + */ + u16 Association_ID; /* The Association ID in the + * (Re)Association Response frame. + */ + u16 ListenInterval; /* The listen interval when SME invoking + * MLME_ (Re)Associate_Request(). + */ struct radio_off RadioOffStatus; u8 Reserved0[2]; - u8 boMsRadioOff; /* Ndis demands to be true when set Disassoc. OID and be false when set SSID OID. */ + u8 boMsRadioOff; /* Ndis demands to be true when set + * Disassoc. OID and be false when + * set SSID OID. + */ u8 bAntennaNo; /* which antenna */ - u8 bConnectFlag; /* the connect status flag for roaming task */ + u8 bConnectFlag; /* the connect status flag for + * roaming task + */ u8 RoamStatus; u8 reserved7[3]; - struct chan_info CurrentChan; /* Current channel no. and channel band. It may be changed by scanning. */ - u8 boHandover; /* Roaming, Hnadover to other AP. */ + struct chan_info CurrentChan; /* Current channel no. and channel band. + * It may be changed by scanning. + */ + u8 boHandover; /* Roaming, Handover to other AP. */ u8 boCCAbusy; - u16 CWMax; /* It may not be the real value that H/W used */ + u16 CWMax; /* It may not be the real value + * that H/W used + */ u8 CWMin; /* 255: set according to 802.11 spec. */ u8 reserved2; @@ -200,7 +228,9 @@ struct wb_local_para { u8 bPreambleMode; /* AUTO, s32 */ u8 boNonERPpresent; - u8 boProtectMechanism; /* H/W will take the necessary action based on this variable */ + u8 boProtectMechanism; /* H/W will take the necessary action + * based on this variable + */ u8 boShortPreamble; /* Same here */ u8 boShortSlotTime; /* Same here */ u8 reserved_3; @@ -213,8 +243,12 @@ struct wb_local_para { u32 HwBssidValid; /* For scan list */ - u8 BssListCount; /* Total count of valid descriptor indexes */ - u8 boReceiveUncorrectInfo; /* important settings in beacon/probe resp. have been changed */ + u8 BssListCount; /* Total count of valid + * descriptor indexes + */ + u8 boReceiveUncorrectInfo; /* important settings in beacon/probe + * resp. have been changed + */ u8 NoOfJoinerInIbss; u8 reserved_4; @@ -228,7 +262,9 @@ struct wb_local_para { */ u8 JoinerInIbss[(MAX_BSS_DESCRIPT_ELEMENT + 3) & ~0x03]; - /* General Statistics, count at Rx_handler or Tx_callback interrupt handler */ + /* General Statistics, count at Rx_handler or + * Tx_callback interrupt handler + */ u64 GS_XMIT_OK; /* Good Frames Transmitted */ u64 GS_RCV_OK; /* Good Frames Received */ u32 GS_RCV_ERROR; /* Frames received with crc error */ @@ -248,10 +284,18 @@ struct wb_local_para { u32 _dot11WEPUndecryptableCount; u32 _dot11FrameDuplicateCount; - struct chan_info IbssChanSetting; /* 2B. Start IBSS Channel setting by registry or WWU. */ - u8 reserved_5[2]; /* It may not be used after considering RF type, region and modulation type. */ + struct chan_info IbssChanSetting; /* 2B. Start IBSS Channel + * setting by registry or + * WWU. + */ + u8 reserved_5[2]; /* It may not be used after + * considering RF type, region + * and modulation type. + */ - u8 reserved_6[2]; /* two variables are for wep key error detection */ + u8 reserved_6[2]; /* two variables are for wep + * key error detection + */ u32 bWepKeyError; u32 bToSelfPacketReceived; u32 WepKeyDetectTimerCount; diff --git a/drivers/staging/winbond/mac_structures.h b/drivers/staging/winbond/mac_structures.h index 7441015cb18..76c63c74d50 100644 --- a/drivers/staging/winbond/mac_structures.h +++ b/drivers/staging/winbond/mac_structures.h @@ -21,39 +21,23 @@ #ifndef _MAC_Structures_H_ #define _MAC_Structures_H_ -#include <linux/skbuff.h> - -/*========================================================= -// Some miscellaneous definitions -//-----*/ -#define MAX_CHANNELS 30 #define MAC_ADDR_LENGTH 6 -#define MAX_WEP_KEY_SIZE 16 /* 128 bits */ -#define MAX_802_11_FRAGMENT_NUMBER 10 /* By spec */ /* ======================================================== // 802.11 Frame define //----- */ -#define MASK_PROTOCOL_VERSION_TYPE 0x0F -#define MASK_FRAGMENT_NUMBER 0x000F -#define SEQUENCE_NUMBER_SHIFT 4 -#define DIFFER_11_TO_3 18 #define DOT_11_MAC_HEADER_SIZE 24 #define DOT_11_SNAP_SIZE 6 #define DOT_11_DURATION_OFFSET 2 -#define DOT_11_SEQUENCE_OFFSET 22 /* Sequence control offset */ -#define DOT_11_TYPE_OFFSET 30 /* The start offset of 802.11 Frame// */ +/* Sequence control offset */ +#define DOT_11_SEQUENCE_OFFSET 22 +/* The start offset of 802.11 Frame// */ +#define DOT_11_TYPE_OFFSET 30 #define DOT_11_DATA_OFFSET 24 #define DOT_11_DA_OFFSET 4 -#define DOT_3_TYPE_ARP 0x80F3 -#define DOT_3_TYPE_IPX 0x8137 -#define DOT_3_TYPE_OFFSET 12 - -#define ETHERNET_HEADER_SIZE 14 #define MAX_ETHERNET_PACKET_SIZE 1514 - /* ----- management : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) */ #define MAC_SUBTYPE_MNGMNT_ASSOC_REQUEST 0x00 #define MAC_SUBTYPE_MNGMNT_ASSOC_RESPONSE 0x10 @@ -67,146 +51,6 @@ #define MAC_SUBTYPE_MNGMNT_AUTHENTICATION 0xB0 #define MAC_SUBTYPE_MNGMNT_DEAUTHENTICATION 0xC0 -/* ----- control : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) */ -#define MAC_SUBTYPE_CONTROL_PSPOLL 0xA4 -#define MAC_SUBTYPE_CONTROL_RTS 0xB4 -#define MAC_SUBTYPE_CONTROL_CTS 0xC4 -#define MAC_SUBTYPE_CONTROL_ACK 0xD4 -#define MAC_SUBTYPE_CONTROL_CFEND 0xE4 -#define MAC_SUBTYPE_CONTROL_CFEND_CFACK 0xF4 - -/* ----- data : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) */ -#define MAC_SUBTYPE_DATA 0x08 -#define MAC_SUBTYPE_DATA_CFACK 0x18 -#define MAC_SUBTYPE_DATA_CFPOLL 0x28 -#define MAC_SUBTYPE_DATA_CFACK_CFPOLL 0x38 -#define MAC_SUBTYPE_DATA_NULL 0x48 -#define MAC_SUBTYPE_DATA_CFACK_NULL 0x58 -#define MAC_SUBTYPE_DATA_CFPOLL_NULL 0x68 -#define MAC_SUBTYPE_DATA_CFACK_CFPOLL_NULL 0x78 - -/* ----- Frame Type of Bits (2, 3) */ -#define MAC_TYPE_MANAGEMENT 0x00 -#define MAC_TYPE_CONTROL 0x04 -#define MAC_TYPE_DATA 0x08 - -/* ----- definitions for Management Frame Element ID (1 BYTE) */ -#define ELEMENT_ID_SSID 0 -#define ELEMENT_ID_SUPPORTED_RATES 1 -#define ELEMENT_ID_FH_PARAMETER_SET 2 -#define ELEMENT_ID_DS_PARAMETER_SET 3 -#define ELEMENT_ID_CF_PARAMETER_SET 4 -#define ELEMENT_ID_TIM 5 -#define ELEMENT_ID_IBSS_PARAMETER_SET 6 -// 7~15 reserverd -#define ELEMENT_ID_CHALLENGE_TEXT 16 -// 17~31 reserved for challenge text extension -// 32~255 reserved -//-- 11G -- -#define ELEMENT_ID_ERP_INFORMATION 42 -#define ELEMENT_ID_EXTENDED_SUPPORTED_RATES 50 - -//-- WPA -- - -#define ELEMENT_ID_RSN_WPA 221 -#ifdef _WPA2_ -#define ELEMENT_ID_RSN_WPA2 48 -#endif //endif WPA2 - -#define WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT ((u16) 6) -#define WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT ((u16) 2) - -//=================================================================== -// Reason Code (Table 18): indicate the reason of DisAssoc, DeAuthen -// length of ReasonCode is 2 Octs. -//=================================================================== -#define REASON_REASERED 0 -#define REASON_UNSPECIDIED 1 -#define REASON_PREAUTH_INVALID 2 -#define DEAUTH_REASON_LEFT_BSS 3 -#define DISASS_REASON_AP_INACTIVE 4 -#define DISASS_REASON_AP_BUSY 5 -#define REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 -#define REASON_CLASS3_FRAME_FROM_NONASSO_STA 7 -#define DISASS_REASON_LEFT_BSS 8 -#define REASON_NOT_AUTH_YET 9 -/* 802.11i define */ -#define REASON_INVALID_IE 13 -#define REASON_MIC_ERROR 14 -#define REASON_4WAY_HANDSHAKE_TIMEOUT 15 -#define REASON_GROUPKEY_UPDATE_TIMEOUT 16 -#define REASON_IE_DIFF_4WAY_ASSOC 17 -#define REASON_INVALID_MULTICAST_CIPHER 18 -#define REASON_INVALID_UNICAST_CIPHER 19 -#define REASON_INVALID_AKMP 20 -#define REASON_UNSUPPORTED_RSNIE_VERSION 21 -#define REASON_INVALID_RSNIE_CAPABILITY 22 -#define REASON_802_1X_AUTH_FAIL 23 -#define REASON_CIPHER_REJECT_PER_SEC_POLICY 14 - -/* -//=========================================================== -// enum_MMPDUResultCode -- -// Status code (2 Octs) in the MMPDU's frame body. Table.19 -// -//=========================================================== -enum enum_MMPDUResultCode -{ -// SUCCESS = 0, // Redefined - UNSPECIFIED_FAILURE = 1, - - // 2 - 9 Reserved - - NOT_SUPPROT_CAPABILITIES = 10, - - //REASSOCIATION_DENIED - // - REASSOC_DENIED_UNABLE_CFM_ASSOC_EXIST = 11, - - //ASSOCIATION_DENIED_NOT_IN_STANDARD - // - ASSOC_DENIED_REASON_NOT_IN_STANDARD = 12, - PEER_NOT_SUPPORT_AUTH_ALGORITHM = 13, - AUTH_SEQNUM_OUT_OF_EXPECT = 14, - AUTH_REJECT_REASON_CHALLENGE_FAIL = 15, - AUTH_REJECT_REASON_WAIT_TIMEOUT = 16, - ASSOC_DENIED_REASON_AP_BUSY = 17, - ASSOC_DENIED_REASON_NOT_SUPPORT_BASIC_RATE = 18 -} WB_MMPDURESULTCODE, *PWB_MMPDURESULTCODE; -*/ - -/*=========================================================== -// enum_TxRate -- -// Define the transmission constants based on W89C32 MAC -// target specification. -//===========================================================*/ -typedef enum enum_TxRate { - TXRATE_1M = 0, - TXRATE_2MLONG = 2, - TXRATE_2MSHORT = 3, - TXRATE_55MLONG = 4, - TXRATE_55MSHORT = 5, - TXRATE_11MLONG = 6, - TXRATE_11MSHORT = 7, - TXRATE_AUTO = 255 /* PD43 20021108 */ -} WB_TXRATE, *PWB_TXRATE; - - -#define RATE_BITMAP_1M 1 -#define RATE_BITMAP_2M 2 -#define RATE_BITMAP_5dot5M 5 -#define RATE_BITMAP_6M 6 -#define RATE_BITMAP_9M 9 -#define RATE_BITMAP_11M 11 -#define RATE_BITMAP_12M 12 -#define RATE_BITMAP_18M 18 -#define RATE_BITMAP_22M 22 -#define RATE_BITMAP_24M 24 -#define RATE_BITMAP_33M 17 -#define RATE_BITMAP_36M 19 -#define RATE_BITMAP_48M 25 -#define RATE_BITMAP_54M 28 - #define RATE_AUTO 0 #define RATE_1M 2 #define RATE_2M 4 @@ -224,414 +68,4 @@ typedef enum enum_TxRate { #define RATE_54M 108 #define RATE_MAX 255 -/* CAPABILITY */ -#define CAPABILITY_ESS_BIT 0x0001 -#define CAPABILITY_IBSS_BIT 0x0002 -#define CAPABILITY_CF_POLL_BIT 0x0004 -#define CAPABILITY_CF_POLL_REQ_BIT 0x0008 -#define CAPABILITY_PRIVACY_BIT 0x0010 -#define CAPABILITY_SHORT_PREAMBLE_BIT 0x0020 -#define CAPABILITY_PBCC_BIT 0x0040 -#define CAPABILITY_CHAN_AGILITY_BIT 0x0080 -#define CAPABILITY_SHORT_SLOT_TIME_BIT 0x0400 -#define CAPABILITY_DSSS_OFDM_BIT 0x2000 - - -struct Capability_Information_Element { - union { - u16 __attribute__ ((packed)) wValue; - #ifdef _BIG_ENDIAN_ /* 20060926 add by anson's endian */ - struct _Capability { - /* -- 11G -- */ - u8 Reserved3:2; - u8 DSSS_OFDM:1; - u8 Reserved2:2; - u8 Short_Slot_Time:1; - u8 Reserved1:2; - u8 Channel_Agility:1; - u8 PBCC:1; - u8 ShortPreamble:1; - u8 CF_Privacy:1; - u8 CF_Poll_Request:1; - u8 CF_Pollable:1; - u8 IBSS:1; - u8 ESS:1; - } __attribute__ ((packed)) Capability; - #else - struct _Capability { - u8 ESS:1; - u8 IBSS:1; - u8 CF_Pollable:1; - u8 CF_Poll_Request:1; - u8 CF_Privacy:1; - u8 ShortPreamble:1; - u8 PBCC:1; - u8 Channel_Agility:1; - u8 Reserved1:2; - /* -- 11G -- */ - u8 Short_Slot_Time:1; - u8 Reserved2:2; - u8 DSSS_OFDM:1; - u8 Reserved3:2; - } __attribute__ ((packed)) Capability; - #endif - } __attribute__ ((packed)) ; -} __attribute__ ((packed)); - -struct FH_Parameter_Set_Element { - u8 Element_ID; - u8 Length; - u8 Dwell_Time[2]; - u8 Hop_Set; - u8 Hop_Pattern; - u8 Hop_Index; -}; - -struct DS_Parameter_Set_Element { - u8 Element_ID; - u8 Length; - u8 Current_Channel; -}; - -struct Supported_Rates_Element { - u8 Element_ID; - u8 Length; - u8 SupportedRates[8]; -} __attribute__ ((packed)); - -struct SSID_Element { - u8 Element_ID; - u8 Length; - u8 SSID[32]; -} __attribute__ ((packed)) ; - -struct CF_Parameter_Set_Element { - u8 Element_ID; - u8 Length; - u8 CFP_Count; - u8 CFP_Period; - u8 CFP_MaxDuration[2]; /* in Time Units */ - u8 CFP_DurRemaining[2]; /* in time units */ -}; - -struct TIM_Element { - u8 Element_ID; - u8 Length; - u8 DTIM_Count; - u8 DTIM_Period; - u8 Bitmap_Control; - u8 Partial_Virtual_Bitmap[251]; -}; - -struct IBSS_Parameter_Set_Element { - u8 Element_ID; - u8 Length; - u8 ATIM_Window[2]; -}; - -struct Challenge_Text_Element { - u8 Element_ID; - u8 Length; - u8 Challenge_Text[253]; -}; - -struct PHY_Parameter_Set_Element { -/* int aSlotTime; */ -/* int aSifsTime; */ - s32 aCCATime; - s32 aRxTxTurnaroundTime; - s32 aTxPLCPDelay; - s32 RxPLCPDelay; - s32 aRxTxSwitchTime; - s32 aTxRampOntime; - s32 aTxRampOffTime; - s32 aTxRFDelay; - s32 aRxRFDelay; - s32 aAirPropagationTime; - s32 aMACProcessingDelay; - s32 aPreambleLength; - s32 aPLCPHeaderLength; - s32 aMPDUDurationFactor; - s32 aMPDUMaxLength; -/* int aCWmin; */ -/* int aCWmax; */ -}; - -/* -- 11G -- */ -struct ERP_Information_Element { - u8 Element_ID; - u8 Length; - #ifdef _BIG_ENDIAN_ /* 20060926 add by anson's endian */ - u8 Reserved:5; /* 20060926 add by anson */ - u8 Barker_Preamble_Mode:1; - u8 Use_Protection:1; - u8 NonERP_Present:1; - #else - u8 NonERP_Present:1; - u8 Use_Protection:1; - u8 Barker_Preamble_Mode:1; - u8 Reserved:5; - #endif -}; - -struct Extended_Supported_Rates_Element { - u8 Element_ID; - u8 Length; - u8 ExtendedSupportedRates[255]; -} __attribute__ ((packed)); - -/* WPA(802.11i draft 3.0) */ -#define VERSION_WPA 1 -#ifdef _WPA2_ -#define VERSION_WPA2 1 -#endif /* end def _WPA2_ */ -#define OUI_WPA 0x00F25000 /* WPA2.0 OUI=00:50:F2, the MSB is reserved for suite type */ -#ifdef _WPA2_ -#define OUI_WPA2 0x00AC0F00 /* for wpa2 change to 0x00ACOF04 by Ws 26/04/04 */ -#endif /* end def _WPA2_ */ - -#define OUI_WPA_ADDITIONAL 0x01 -#define WLAN_MIN_RSN_WPA_LENGTH 6 /* added by ws 09/10/04 */ -#ifdef _WPA2_ -#define WLAN_MIN_RSN_WPA2_LENGTH 2 /* Fix to 2 09/14/05 */ -#endif /* end def _WPA2_ */ - -#define oui_wpa (u32)(OUI_WPA|OUI_WPA_ADDITIONAL) - -#define WPA_OUI_BIG ((u32) 0x01F25000)/* added by ws 09/23/04 */ -#define WPA_OUI_LITTLE ((u32) 0x01F25001)/* added by ws 09/23/04 */ - -#define WPA_WPS_OUI cpu_to_le32(0x04F25000) /* 20061108 For WPS. It's little endian. Big endian is 0x0050F204 */ - -/* -----WPA2----- */ -#ifdef _WPA2_ -#define WPA2_OUI_BIG ((u32)0x01AC0F00) -#define WPA2_OUI_LITTLE ((u32)0x01AC0F01) -#endif /* end def _WPA2_ */ - -/* Authentication suite */ -#define OUI_AUTH_WPA_NONE 0x00 /* for WPA_NONE */ -#define OUI_AUTH_8021X 0x01 -#define OUI_AUTH_PSK 0x02 -/* Cipher suite */ -#define OUI_CIPHER_GROUP_KEY 0x00 /* added by ws 05/21/04 */ -#define OUI_CIPHER_WEP_40 0x01 -#define OUI_CIPHER_TKIP 0x02 -#define OUI_CIPHER_CCMP 0x04 -#define OUI_CIPHER_WEP_104 0x05 - -struct suite_selector -{ - union - { - u8 Value[4]; - struct _SUIT_ - { - u8 OUI[3]; - u8 Type; - }SuitSelector; - }; -}; - -//-- WPA -- -struct RSN_Information_Element -{ - u8 Element_ID; - u8 Length; - struct suite_selector OuiWPAAdditional; /* WPA version 2.0 additional field, and should be 00:50:F2:01 */ - u16 Version; - struct suite_selector GroupKeySuite; - u16 PairwiseKeySuiteCount; - struct suite_selector PairwiseKeySuite[1]; -}__attribute__ ((packed)); -struct RSN_Auth_Sub_Information_Element -{ - u16 AuthKeyMngtSuiteCount; - struct suite_selector AuthKeyMngtSuite[1]; -}__attribute__ ((packed)); - -/* -- WPA2 -- */ -struct RSN_Capability_Element -{ - union - { - u16 __attribute__ ((packed)) wValue; - #ifdef _BIG_ENDIAN_ /* 20060927 add by anson's endian */ - struct _RSN_Capability - { - u16 __attribute__ ((packed)) Reserved2 : 8; /* 20051201 */ - u16 __attribute__ ((packed)) Reserved1 : 2; - u16 __attribute__ ((packed)) GTK_Replay_Counter : 2; - u16 __attribute__ ((packed)) PTK_Replay_Counter : 2; - u16 __attribute__ ((packed)) No_Pairwise : 1; - u16 __attribute__ ((packed)) Pre_Auth : 1; - }__attribute__ ((packed)) RSN_Capability; - #else - struct _RSN_Capability - { - u16 __attribute__ ((packed)) Pre_Auth : 1; - u16 __attribute__ ((packed)) No_Pairwise : 1; - u16 __attribute__ ((packed)) PTK_Replay_Counter : 2; - u16 __attribute__ ((packed)) GTK_Replay_Counter : 2; - u16 __attribute__ ((packed)) Reserved1 : 2; - u16 __attribute__ ((packed)) Reserved2 : 8; /* 20051201 */ - }__attribute__ ((packed)) RSN_Capability; - #endif - - }__attribute__ ((packed)) ; -}__attribute__ ((packed)) ; - -#ifdef _WPA2_ -struct pmkid -{ - u8 pValue[16]; -}; - -struct WPA2_RSN_Information_Element -{ - u8 Element_ID; - u8 Length; - u16 Version; - struct suite_selector GroupKeySuite; - u16 PairwiseKeySuiteCount; - struct suite_selector PairwiseKeySuite[1]; - -}__attribute__ ((packed)); - -struct WPA2_RSN_Auth_Sub_Information_Element -{ - u16 AuthKeyMngtSuiteCount; - struct suite_selector AuthKeyMngtSuite[1]; -}__attribute__ ((packed)); - - -struct PMKID_Information_Element -{ - u16 PMKID_Count; - struct pmkid pmkid[16]; -}__attribute__ ((packed)); - -#endif /* enddef _WPA2_ */ -/*============================================================ -// MAC Frame structure (different type) and subfield structure -//============================================================*/ -struct MAC_frame_control -{ - u8 mac_frame_info; /* a combination of the [Protocol Version, Control Type, Control Subtype]*/ - #ifdef _BIG_ENDIAN_ /* 20060927 add by anson's endian */ - u8 order:1; - u8 WEP:1; - u8 more_data:1; - u8 pwr_mgt:1; - u8 retry:1; - u8 more_frag:1; - u8 from_ds:1; - u8 to_ds:1; - #else - u8 to_ds:1; - u8 from_ds:1; - u8 more_frag:1; - u8 retry:1; - u8 pwr_mgt:1; - u8 more_data:1; - u8 WEP:1; - u8 order:1; - #endif -} __attribute__ ((packed)); - -struct Management_Frame { - struct MAC_frame_control frame_control; /* 2B, ToDS,FromDS,MoreFrag,MoreData,Order=0 */ - u16 duration; - u8 DA[MAC_ADDR_LENGTH]; /* Addr1 */ - u8 SA[MAC_ADDR_LENGTH]; /* Addr2 */ - u8 BSSID[MAC_ADDR_LENGTH]; /* Addr3 */ - u16 Sequence_Control; - /* Management Frame Body <= 325 bytes */ - /* FCS 4 bytes */ -} __attribute__ ((packed)); - -/* SW-MAC don't Tx/Rx Control-Frame, HW-MAC do it. */ -struct Control_Frame { - struct MAC_frame_control frame_control; /* ToDS,FromDS,MoreFrag,Retry,MoreData,WEP,Order=0 */ - u16 duration; - u8 RA[MAC_ADDR_LENGTH]; - u8 TA[MAC_ADDR_LENGTH]; - u16 FCS; -} __attribute__ ((packed)); - -struct Data_Frame { - struct MAC_frame_control frame_control; - u16 duration; - u8 Addr1[MAC_ADDR_LENGTH]; - u8 Addr2[MAC_ADDR_LENGTH]; - u8 Addr3[MAC_ADDR_LENGTH]; - u16 Sequence_Control; - u8 Addr4[MAC_ADDR_LENGTH]; /* only exist when ToDS=FromDS=1 */ - /* Data Frame Body <= 2312 */ - /* FCS */ -} __attribute__ ((packed)); - -struct Disassociation_Frame_Body { - u16 reasonCode; -} __attribute__ ((packed)); - -struct Association_Request_Frame_Body { - u16 capability_information; - u16 listenInterval; - u8 Current_AP_Address[MAC_ADDR_LENGTH];/* for reassociation only */ - /* SSID (2+32 bytes) */ - /* Supported_Rates (2+8 bytes) */ -} __attribute__ ((packed)); - -struct Association_Response_Frame_Body { - u16 capability_information; - u16 statusCode; - u16 Association_ID; - struct Supported_Rates_Element supportedRates; -} __attribute__ ((packed)); - -/*struct Reassociation_Request_Frame_Body -{ - u16 capability_information; - u16 listenInterval; - u8 Current_AP_Address[MAC_ADDR_LENGTH]; - // SSID (2+32 bytes) - // Supported_Rates (2+8 bytes) -};*/ -/* eliminated by WS 07/22/04 comboined with associateion request frame. */ - -struct Reassociation_Response_Frame_Body { - u16 capability_information; - u16 statusCode; - u16 Association_ID; - struct Supported_Rates_Element supportedRates; -} __attribute__ ((packed)); - -struct Deauthentication_Frame_Body { - u16 reasonCode; -} __attribute__ ((packed)); - - -struct Probe_Response_Frame_Body { - u16 Timestamp; - u16 Beacon_Interval; - u16 Capability_Information; - /* SSID - // Supported_Rates - // PHY parameter Set (DS Parameters) - // CF parameter Set - // IBSS parameter Set */ -} __attribute__ ((packed)); - -struct Authentication_Frame_Body { - u16 algorithmNumber; - u16 sequenceNumber; - u16 statusCode; - /* NB: don't include ChallengeText in this structure - // struct Challenge_Text_Element sChallengeTextElement; // wkchen added */ -} __attribute__ ((packed)); - - #endif /* _MAC_Structure_H_ */ - - diff --git a/drivers/staging/winbond/mds.c b/drivers/staging/winbond/mds.c index e8320a6f59a..aef0855f4c6 100644 --- a/drivers/staging/winbond/mds.c +++ b/drivers/staging/winbond/mds.c @@ -1,9 +1,7 @@ #include "mds_f.h" -#include "mlmetxrx_f.h" #include "mto.h" -#include "sysdef.h" -#include "wbhal_f.h" -#include "wblinux_f.h" +#include "wbhal.h" +#include "wb35tx_f.h" unsigned char Mds_initial(struct wbsoft_priv *adapter) @@ -14,22 +12,18 @@ Mds_initial(struct wbsoft_priv *adapter) pMds->TxRTSThreshold = DEFAULT_RTSThreshold; pMds->TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; - return hal_get_tx_buffer( &adapter->sHwData, &pMds->pTxBuffer ); + return hal_get_tx_buffer(&adapter->sHwData, &pMds->pTxBuffer); } -void -Mds_Destroy(struct wbsoft_priv *adapter) +static void Mds_DurationSet(struct wbsoft_priv *adapter, + struct wb35_descriptor *pDes, u8 *buffer) { -} - -static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor *pDes, u8 *buffer) -{ - PT00_DESCRIPTOR pT00; - PT01_DESCRIPTOR pT01; + struct T00_descriptor *pT00; + struct T01_descriptor *pT01; u16 Duration, NextBodyLen, OffsetSize; u8 Rate, i; unsigned char CTS_on = false, RTS_on = false; - PT00_DESCRIPTOR pNextT00; + struct T00_descriptor *pNextT00; u16 BodyLen = 0; unsigned char boGroupAddr = false; @@ -39,87 +33,81 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor if (!Rate) Rate = 1; - pT00 = (PT00_DESCRIPTOR)buffer; - pT01 = (PT01_DESCRIPTOR)(buffer+4); - pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize); + pT00 = (struct T00_descriptor *)buffer; + pT01 = (struct T01_descriptor *)(buffer+4); + pNextT00 = (struct T00_descriptor *)(buffer+OffsetSize); - if( buffer[ DOT_11_DA_OFFSET+8 ] & 0x1 ) /* +8 for USB hdr */ + if (buffer[DOT_11_DA_OFFSET+8] & 0x1) /* +8 for USB hdr */ boGroupAddr = true; /****************************************** * Set RTS/CTS mechanism ******************************************/ - if (!boGroupAddr) - { - /* NOTE : If the protection mode is enabled and the MSDU will be fragmented, - * the tx rates of MPDUs will all be DSSS rates. So it will not use - * CTS-to-self in this case. CTS-To-self will only be used when without - * fragmentation. -- 20050112 */ + if (!boGroupAddr) { + /* NOTE : If the protection mode is enabled and the MSDU will + * be fragmented, the tx rates of MPDUs will all be DSSS + * rates. So it will not use CTS-to-self in this case. + * CTS-To-self will only be used when without + * fragmentation. -- 20050112 */ BodyLen = (u16)pT00->T00_frame_length; /* include 802.11 header */ BodyLen += 4; /* CRC */ - if( BodyLen >= CURRENT_RTS_THRESHOLD ) + if (BodyLen >= CURRENT_RTS_THRESHOLD) RTS_on = true; /* Using RTS */ - else - { - if( pT01->T01_modulation_type ) /* Is using OFDM */ - { - if( CURRENT_PROTECT_MECHANISM ) /* Is using protect */ + else { + if (pT01->T01_modulation_type) { /* Is using OFDM */ + /* Is using protect */ + if (CURRENT_PROTECT_MECHANISM) CTS_on = true; /* Using CTS */ } } } - if( RTS_on || CTS_on ) - { - if( pT01->T01_modulation_type) /* Is using OFDM */ - { - /* CTS duration + if (RTS_on || CTS_on) { + if (pT01->T01_modulation_type) { /* Is using OFDM */ + /* CTS duration * 2 SIFS + DATA transmit time + 1 ACK * ACK Rate : 24 Mega bps * ACK frame length = 14 bytes */ Duration = 2*DEFAULT_SIFSTIME + - 2*PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + - ((BodyLen*8 + 22 + Rate*4 - 1)/(Rate*4))*Tsym + - ((112 + 22 + 95)/96)*Tsym; - } - else /* DSSS */ - { + 2*PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + + ((BodyLen*8 + 22 + Rate*4 - 1)/(Rate*4))*Tsym + + ((112 + 22 + 95)/96)*Tsym; + } else { /* DSSS */ /* CTS duration * 2 SIFS + DATA transmit time + 1 ACK * Rate : ?? Mega bps * ACK frame length = 14 bytes */ - if( pT01->T01_plcp_header_length ) /* long preamble */ + if (pT01->T01_plcp_header_length) /* long preamble */ Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*2; else Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*2; - Duration += ( ((BodyLen + 14)*8 + Rate-1) / Rate + - DEFAULT_SIFSTIME*2 ); + Duration += (((BodyLen + 14)*8 + Rate-1) / Rate + + DEFAULT_SIFSTIME*2); } - if( RTS_on ) - { - if( pT01->T01_modulation_type ) /* Is using OFDM */ - { + if (RTS_on) { + if (pT01->T01_modulation_type) { /* Is using OFDM */ /* CTS + 1 SIFS + CTS duration * CTS Rate : 24 Mega bps * CTS frame length = 14 bytes */ Duration += (DEFAULT_SIFSTIME + - PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + - ((112 + 22 + 95)/96)*Tsym); - } - else - { + PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + + ((112 + 22 + 95)/96)*Tsym); + } else { /* CTS + 1 SIFS + CTS duration * CTS Rate : ?? Mega bps - * CTS frame length = 14 bytes */ - if( pT01->T01_plcp_header_length ) /* long preamble */ + * CTS frame length = 14 bytes + */ + /* long preamble */ + if (pT01->T01_plcp_header_length) Duration += LONG_PREAMBLE_PLUS_PLCPHEADER_TIME; else Duration += SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME; - Duration += ( ((112 + Rate-1) / Rate) + DEFAULT_SIFSTIME ); + Duration += (((112 + Rate-1) / Rate) + + DEFAULT_SIFSTIME); } } @@ -132,84 +120,81 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor /****************************************** * Fill the more fragment descriptor ******************************************/ - if( boGroupAddr ) + if (boGroupAddr) Duration = 0; - else - { - for( i=pDes->FragmentCount-1; i>0; i-- ) - { + else { + for (i = pDes->FragmentCount-1; i > 0; i--) { NextBodyLen = (u16)pNextT00->T00_frame_length; NextBodyLen += 4; /* CRC */ - if( pT01->T01_modulation_type ) - { + if (pT01->T01_modulation_type) { /* OFDM * data transmit time + 3 SIFS + 2 ACK * Rate : ??Mega bps * ACK frame length = 14 bytes, tx rate = 24M */ Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION * 3; - Duration += (((NextBodyLen*8 + 22 + Rate*4 - 1)/(Rate*4)) * Tsym + - (((2*14)*8 + 22 + 95)/96)*Tsym + - DEFAULT_SIFSTIME*3); - } - else - { + Duration += (((NextBodyLen*8 + 22 + Rate*4 - 1) + /(Rate*4)) * Tsym + + (((2*14)*8 + 22 + 95)/96)*Tsym + + DEFAULT_SIFSTIME*3); + } else { /* DSSS * data transmit time + 2 ACK + 3 SIFS * Rate : ??Mega bps * ACK frame length = 14 bytes * TODO : */ - if( pT01->T01_plcp_header_length ) /* long preamble */ + if (pT01->T01_plcp_header_length) /* long preamble */ Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*3; else Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*3; - Duration += ( ((NextBodyLen + (2*14))*8 + Rate-1) / Rate + - DEFAULT_SIFSTIME*3 ); + Duration += (((NextBodyLen + (2*14))*8 + + Rate-1) / Rate + + DEFAULT_SIFSTIME*3); } - - ((u16 *)buffer)[5] = cpu_to_le16(Duration); /* 4 USHOR for skip 8B USB, 2USHORT=FC + Duration */ + /* 4 USHOR for skip 8B USB, 2USHORT=FC + Duration */ + ((u16 *)buffer)[5] = cpu_to_le16(Duration); /* ----20061009 add by anson's endian */ pNextT00->value = cpu_to_le32(pNextT00->value); - pT01->value = cpu_to_le32( pT01->value ); + pT01->value = cpu_to_le32(pT01->value); /* ----end 20061009 add by anson's endian */ buffer += OffsetSize; - pT01 = (PT01_DESCRIPTOR)(buffer+4); - if (i != 1) /* The last fragment will not have the next fragment */ - pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize); + pT01 = (struct T01_descriptor *)(buffer+4); + /* The last fragment will not have the next fragment */ + if (i != 1) + pNextT00 = (struct T00_descriptor *)(buffer+OffsetSize); } /******************************************* * Fill the last fragment descriptor *******************************************/ - if( pT01->T01_modulation_type ) - { + if (pT01->T01_modulation_type) { /* OFDM * 1 SIFS + 1 ACK * Rate : 24 Mega bps * ACK frame length = 14 bytes */ Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION; /* The Tx rate of ACK use 24M */ - Duration += (((112 + 22 + 95)/96)*Tsym + DEFAULT_SIFSTIME ); - } - else - { + Duration += (((112 + 22 + 95)/96)*Tsym + + DEFAULT_SIFSTIME); + } else { /* DSSS * 1 ACK + 1 SIFS * Rate : ?? Mega bps * ACK frame length = 14 bytes(112 bits) */ - if( pT01->T01_plcp_header_length ) /* long preamble */ + if (pT01->T01_plcp_header_length) /* long preamble */ Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME; else Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME; - Duration += ( (112 + Rate-1)/Rate + DEFAULT_SIFSTIME ); + Duration += ((112 + Rate-1)/Rate + DEFAULT_SIFSTIME); } } - ((u16 *)buffer)[5] = cpu_to_le16(Duration); /* 4 USHOR for skip 8B USB, 2USHORT=FC + Duration */ + /* 4 USHOR for skip 8B USB, 2USHORT=FC + Duration */ + ((u16 *)buffer)[5] = cpu_to_le16(Duration); pT00->value = cpu_to_le32(pT00->value); pT01->value = cpu_to_le32(pT01->value); /* --end 20061009 add */ @@ -217,9 +202,10 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor } /* The function return the 4n size of usb pk */ -static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDes, u8 *TargetBuffer) +static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, + struct wb35_descriptor *pDes, u8 *TargetBuffer) { - PT00_DESCRIPTOR pT00; + struct T00_descriptor *pT00; struct wb35_mds *pMds = &adapter->Mds; u8 *buffer; u8 *src_buffer; @@ -234,23 +220,24 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe SizeLeft = pDes->buffer_total_size; buf_index = pDes->buffer_start_index; - pT00 = (PT00_DESCRIPTOR)buffer; + pT00 = (struct T00_descriptor *)buffer; while (SizeLeft) { - pT00 = (PT00_DESCRIPTOR)buffer; + pT00 = (struct T00_descriptor *)buffer; CopySize = SizeLeft; if (SizeLeft > pDes->FragmentThreshold) { CopySize = pDes->FragmentThreshold; - pT00->T00_frame_length = 24 + CopySize; /* Set USB length */ - } else - pT00->T00_frame_length = 24 + SizeLeft; /* Set USB length */ + /* Set USB length */ + pT00->T00_frame_length = 24 + CopySize; + } else /* Set USB length */ + pT00->T00_frame_length = 24 + SizeLeft; SizeLeft -= CopySize; /* 1 Byte operation */ - pctmp = (u8 *)( buffer + 8 + DOT_11_SEQUENCE_OFFSET ); + pctmp = (u8 *)(buffer + 8 + DOT_11_SEQUENCE_OFFSET); *pctmp &= 0xf0; *pctmp |= FragmentCount; /* 931130.5.m */ - if( !FragmentCount ) + if (!FragmentCount) pT00->T00_first_mpdu = 1; buffer += 32; /* 8B usb + 24B 802.11 header */ @@ -272,7 +259,7 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe buf_index++; buf_index %= MAX_DESCRIPTOR_BUFFER_INDEX; } else { - u8 *pctmp = pDes->buffer_address[buf_index]; + u8 *pctmp = pDes->buffer_address[buf_index]; pctmp += CopySize; pDes->buffer_address[buf_index] = pctmp; pDes->buffer_size[buf_index] -= CopySize; @@ -286,24 +273,28 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe /* 931130.5.n */ if (pMds->MicAdd) { if (!SizeLeft) { - pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - pMds->MicAdd; - pMds->MicWriteSize[ pMds->MicWriteIndex ] = pMds->MicAdd; + pMds->MicWriteAddress[pMds->MicWriteIndex] = + buffer - pMds->MicAdd; + pMds->MicWriteSize[pMds->MicWriteIndex] = + pMds->MicAdd; pMds->MicAdd = 0; - } - else if( SizeLeft < 8 ) /* 931130.5.p */ - { + } else if (SizeLeft < 8) { /* 931130.5.p */ pMds->MicAdd = SizeLeft; - pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - ( 8 - SizeLeft ); - pMds->MicWriteSize[ pMds->MicWriteIndex ] = 8 - SizeLeft; + pMds->MicWriteAddress[pMds->MicWriteIndex] = + buffer - (8 - SizeLeft); + pMds->MicWriteSize[pMds->MicWriteIndex] = + 8 - SizeLeft; pMds->MicWriteIndex++; } } /* Does it need to generate the new header for next mpdu? */ if (SizeLeft) { - buffer = TargetBuffer + Size; /* Get the next 4n start address */ - memcpy( buffer, TargetBuffer, 32 ); /* Copy 8B USB +24B 802.11 */ - pT00 = (PT00_DESCRIPTOR)buffer; + /* Get the next 4n start address */ + buffer = TargetBuffer + Size; + /* Copy 8B USB +24B 802.11 */ + memcpy(buffer, TargetBuffer, 32); + pT00 = (struct T00_descriptor *)buffer; pT00->T00_first_mpdu = 0; } @@ -314,16 +305,18 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe pT00->T00_IsLastMpdu = 1; buffer = (u8 *)pT00 + 8; /* +8 for USB hdr */ buffer[1] &= ~0x04; /* Clear more frag bit of 802.11 frame control */ - pDes->FragmentCount = FragmentCount; /* Update the correct fragment number */ + /* Update the correct fragment number */ + pDes->FragmentCount = FragmentCount; return Size; } -static void Mds_HeaderCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDes, u8 *TargetBuffer) +static void Mds_HeaderCopy(struct wbsoft_priv *adapter, + struct wb35_descriptor *pDes, u8 *TargetBuffer) { struct wb35_mds *pMds = &adapter->Mds; u8 *src_buffer = pDes->buffer_address[0]; /* 931130.5.g */ - PT00_DESCRIPTOR pT00; - PT01_DESCRIPTOR pT01; + struct T00_descriptor *pT00; + struct T01_descriptor *pT01; u16 stmp; u8 i, ctmp1, ctmp2, ctmpf; u16 FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD; @@ -333,9 +326,9 @@ static void Mds_HeaderCopy(struct wbsoft_priv *adapter, struct wb35_descriptor * /* * Set USB header 8 byte */ - pT00 = (PT00_DESCRIPTOR)TargetBuffer; + pT00 = (struct T00_descriptor *)TargetBuffer; TargetBuffer += 4; - pT01 = (PT01_DESCRIPTOR)TargetBuffer; + pT01 = (struct T01_descriptor *)TargetBuffer; TargetBuffer += 4; pT00->value = 0; /* Clear */ @@ -343,14 +336,15 @@ static void Mds_HeaderCopy(struct wbsoft_priv *adapter, struct wb35_descriptor * pT00->T00_tx_packet_id = pDes->Descriptor_ID; /* Set packet ID */ pT00->T00_header_length = 24; /* Set header length */ - pT01->T01_retry_abort_ebable = 1; /* 921013 931130.5.h */ + pT01->T01_retry_abort_enable = 1; /* 921013 931130.5.h */ /* Key ID setup */ pT01->T01_wep_id = 0; FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; /* Do not fragment */ /* Copy full data, the 1'st buffer contain all the data 931130.5.j */ - memcpy( TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE ); /* Copy header */ + /* Copy header */ + memcpy(TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE); pDes->buffer_address[0] = src_buffer + DOT_11_MAC_HEADER_SIZE; pDes->buffer_total_size -= DOT_11_MAC_HEADER_SIZE; pDes->buffer_size[0] = pDes->buffer_total_size; @@ -371,32 +365,42 @@ static void Mds_HeaderCopy(struct wbsoft_priv *adapter, struct wb35_descriptor * ctmp1 = ctmpf = CURRENT_TX_RATE_FOR_MNG; pDes->TxRate = ctmp1; - #ifdef _PE_TX_DUMP_ - printk("Tx rate =%x\n", ctmp1); - #endif + pr_debug("Tx rate =%x\n", ctmp1); pT01->T01_modulation_type = (ctmp1%3) ? 0 : 1; - for( i=0; i<2; i++ ) { - if( i == 1 ) + for (i = 0; i < 2; i++) { + if (i == 1) ctmp1 = ctmpf; + /* backup the ta rate and fall back rate */ + pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; + + if (ctmp1 == 108) + ctmp2 = 7; + else if (ctmp1 == 96) + ctmp2 = 6; /* Rate convert for USB */ + else if (ctmp1 == 72) + ctmp2 = 5; + else if (ctmp1 == 48) + ctmp2 = 4; + else if (ctmp1 == 36) + ctmp2 = 3; + else if (ctmp1 == 24) + ctmp2 = 2; + else if (ctmp1 == 18) + ctmp2 = 1; + else if (ctmp1 == 12) + ctmp2 = 0; + else if (ctmp1 == 22) + ctmp2 = 3; + else if (ctmp1 == 11) + ctmp2 = 2; + else if (ctmp1 == 4) + ctmp2 = 1; + else + ctmp2 = 0; /* if( ctmp1 == 2 ) or default */ - pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; /* backup the ta rate and fall back rate */ - - if( ctmp1 == 108) ctmp2 = 7; - else if( ctmp1 == 96 ) ctmp2 = 6; /* Rate convert for USB */ - else if( ctmp1 == 72 ) ctmp2 = 5; - else if( ctmp1 == 48 ) ctmp2 = 4; - else if( ctmp1 == 36 ) ctmp2 = 3; - else if( ctmp1 == 24 ) ctmp2 = 2; - else if( ctmp1 == 18 ) ctmp2 = 1; - else if( ctmp1 == 12 ) ctmp2 = 0; - else if( ctmp1 == 22 ) ctmp2 = 3; - else if( ctmp1 == 11 ) ctmp2 = 2; - else if( ctmp1 == 4 ) ctmp2 = 1; - else ctmp2 = 0; /* if( ctmp1 == 2 ) or default */ - - if( i == 0 ) + if (i == 0) pT01->T01_transmit_rate = ctmp2; else pT01->T01_fall_back_rate = ctmp2; @@ -405,12 +409,53 @@ static void Mds_HeaderCopy(struct wbsoft_priv *adapter, struct wb35_descriptor * /* * Set preamble type */ - if ((pT01->T01_modulation_type == 0) && (pT01->T01_transmit_rate == 0)) /* RATE_1M */ + /* RATE_1M */ + if ((pT01->T01_modulation_type == 0) && (pT01->T01_transmit_rate == 0)) pDes->PreambleMode = WLAN_PREAMBLE_TYPE_LONG; else pDes->PreambleMode = CURRENT_PREAMBLE_MODE; - pT01->T01_plcp_header_length = pDes->PreambleMode; /* Set preamble */ + pT01->T01_plcp_header_length = pDes->PreambleMode; /* Set preamble */ + +} + +static void MLME_GetNextPacket(struct wbsoft_priv *adapter, + struct wb35_descriptor *desc) +{ + desc->InternalUsed = desc->buffer_start_index + desc->buffer_number; + desc->InternalUsed %= MAX_DESCRIPTOR_BUFFER_INDEX; + desc->buffer_address[desc->InternalUsed] = adapter->sMlmeFrame.pMMPDU; + desc->buffer_size[desc->InternalUsed] = adapter->sMlmeFrame.len; + desc->buffer_total_size += adapter->sMlmeFrame.len; + desc->buffer_number++; + desc->Type = adapter->sMlmeFrame.data_type; +} + +static void MLMEfreeMMPDUBuffer(struct wbsoft_priv *adapter, s8 *pData) +{ + int i; + + /* Reclaim the data buffer */ + for (i = 0; i < MAX_NUM_TX_MMPDU; i++) { + if (pData == (s8 *)&(adapter->sMlmeFrame.TxMMPDU[i])) + break; + } + if (adapter->sMlmeFrame.TxMMPDUInUse[i]) + adapter->sMlmeFrame.TxMMPDUInUse[i] = false; + else { + /* Something wrong + PD43 Add debug code here??? */ + } +} + +static void MLME_SendComplete(struct wbsoft_priv *adapter, u8 PacketID, + unsigned char SendOK) +{ + /* Reclaim the data buffer */ + adapter->sMlmeFrame.len = 0; + MLMEfreeMMPDUBuffer(adapter, adapter->sMlmeFrame.pMMPDU); + /* Return resource */ + adapter->sMlmeFrame.is_in_used = PACKET_FREE_TO_USE; } void @@ -420,9 +465,9 @@ Mds_Tx(struct wbsoft_priv *adapter) struct wb35_mds *pMds = &adapter->Mds; struct wb35_descriptor TxDes; struct wb35_descriptor *pTxDes = &TxDes; - u8 *XmitBufAddress; - u16 XmitBufSize, PacketSize, stmp, CurrentSize, FragmentThreshold; - u8 FillIndex, TxDesIndex, FragmentCount, FillCount; + u8 *XmitBufAddress; + u16 XmitBufSize, PacketSize, stmp, CurrentSize, FragmentThreshold; + u8 FillIndex, TxDesIndex, FragmentCount, FillCount; unsigned char BufferFilled = false; @@ -438,14 +483,14 @@ Mds_Tx(struct wbsoft_priv *adapter) /* Start to fill the data */ do { FillIndex = pMds->TxFillIndex; - if (pMds->TxOwner[FillIndex]) { /* Is owned by software 0:Yes 1:No */ -#ifdef _PE_TX_DUMP_ - printk("[Mds_Tx] Tx Owner is H/W.\n"); -#endif + /* Is owned by software 0:Yes 1:No */ + if (pMds->TxOwner[FillIndex]) { + pr_debug("[Mds_Tx] Tx Owner is H/W.\n"); break; } - XmitBufAddress = pMds->pTxBuffer + (MAX_USB_TX_BUFFER * FillIndex); /* Get buffer */ + /* Get buffer */ + XmitBufAddress = pMds->pTxBuffer + (MAX_USB_TX_BUFFER * FillIndex); XmitBufSize = 0; FillCount = 0; do { @@ -457,12 +502,10 @@ Mds_Tx(struct wbsoft_priv *adapter) FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD; /* 931130.5.b */ FragmentCount = PacketSize/FragmentThreshold + 1; - stmp = PacketSize + FragmentCount*32 + 8; /* 931130.5.c 8:MIC */ - if ((XmitBufSize + stmp) >= MAX_USB_TX_BUFFER) { - printk("[Mds_Tx] Excess max tx buffer.\n"); + /* 931130.5.c 8:MIC */ + stmp = PacketSize + FragmentCount*32 + 8; + if ((XmitBufSize + stmp) >= MAX_USB_TX_BUFFER) break; /* buffer is not enough */ - } - /* * Start transmitting @@ -474,20 +517,23 @@ Mds_Tx(struct wbsoft_priv *adapter) TxDesIndex = pMds->TxDesIndex; /* Get the current ID */ pTxDes->Descriptor_ID = TxDesIndex; - pMds->TxDesFrom[ TxDesIndex ] = 2; /* Storing the information of source comming from */ + /* Storing the information of source coming from */ + pMds->TxDesFrom[TxDesIndex] = 2; pMds->TxDesIndex++; pMds->TxDesIndex %= MAX_USB_TX_DESCRIPTOR; - MLME_GetNextPacket( adapter, pTxDes ); + MLME_GetNextPacket(adapter, pTxDes); - /* Copy header. 8byte USB + 24byte 802.11Hdr. Set TxRate, Preamble type */ - Mds_HeaderCopy( adapter, pTxDes, XmitBufAddress ); + /* + * Copy header. 8byte USB + 24byte 802.11Hdr. + * Set TxRate, Preamble type + */ + Mds_HeaderCopy(adapter, pTxDes, XmitBufAddress); /* For speed up Key setting */ if (pTxDes->EapFix) { -#ifdef _PE_TX_DUMP_ - printk("35: EPA 4th frame detected. Size = %d\n", PacketSize); -#endif + pr_debug("35: EPA 4th frame detected. Size = %d\n", + PacketSize); pHwData->IsKeyPreSet = 1; } @@ -501,12 +547,9 @@ Mds_Tx(struct wbsoft_priv *adapter) XmitBufSize += CurrentSize; XmitBufAddress += CurrentSize; -#ifdef _IBSS_BEACON_SEQ_STICK_ - if ((XmitBufAddress[ DOT_11_DA_OFFSET+8 ] & 0xfc) != MAC_SUBTYPE_MNGMNT_PROBE_REQUEST) /* +8 for USB hdr */ -#endif - pMds->TxToggle = true; - - /* Get packet to transmit completed, 1:TESTSTA 2:MLME 3: Ndis data */ + /* Get packet to transmit completed, + * 1:TESTSTA 2:MLME 3: Ndis data + */ MLME_SendComplete(adapter, 0, true); /* Software TSC count 20060214 */ @@ -515,12 +558,17 @@ Mds_Tx(struct wbsoft_priv *adapter) pMds->TxTsc_2++; FillCount++; /* 20060928 */ - } while (HAL_USB_MODE_BURST(pHwData)); /* End of multiple MSDU copy loop. false = single true = multiple sending */ + /* + * End of multiple MSDU copy loop. + * false = single + * true = multiple sending + */ + } while (HAL_USB_MODE_BURST(pHwData)); /* Move to the next one, if necessary */ if (BufferFilled) { /* size setting */ - pMds->TxBufferSize[ FillIndex ] = XmitBufSize; + pMds->TxBufferSize[FillIndex] = XmitBufSize; /* 20060928 set Tx count */ pMds->TxCountInBuffer[FillIndex] = FillCount; @@ -537,7 +585,7 @@ Mds_Tx(struct wbsoft_priv *adapter) if (!PacketSize) /* No more pk for transmitting */ break; - } while(true); + } while (true); /* * Start to send by lower module @@ -545,12 +593,12 @@ Mds_Tx(struct wbsoft_priv *adapter) if (!pHwData->IsKeyPreSet) Wb35Tx_start(adapter); - cleanup: - atomic_dec(&pMds->TxThreadCount); +cleanup: + atomic_dec(&pMds->TxThreadCount); } void -Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02) +Mds_SendComplete(struct wbsoft_priv *adapter, struct T02_descriptor *pT02) { struct wb35_mds *pMds = &adapter->Mds; struct hw_data *pHwData = &adapter->sHwData; @@ -558,12 +606,12 @@ Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02) unsigned char SendOK = true; u8 RetryCount, TxRate; - if (pT02->T02_IgnoreResult) /* Don't care the result */ + if (pT02->T02_IgnoreResult) /* Don't care about the result */ return; if (pT02->T02_IsLastMpdu) { /* TODO: DTO -- get the retry count and fragment count */ /* Tx rate */ - TxRate = pMds->TxRate[ PacketId ][ 0 ]; + TxRate = pMds->TxRate[PacketId][0]; RetryCount = (u8)pT02->T02_MPDU_Cnt; if (pT02->value & FLAG_ERROR_TX_MASK) { SendOK = false; @@ -572,13 +620,12 @@ Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02) /* retry error */ pHwData->dto_tx_retry_count += (RetryCount+1); /* [for tx debug] */ - if (RetryCount<7) + if (RetryCount < 7) pHwData->tx_retry_count[RetryCount] += RetryCount; else pHwData->tx_retry_count[7] += RetryCount; - #ifdef _PE_STATE_DUMP_ - printk("dto_tx_retry_count =%d\n", pHwData->dto_tx_retry_count); - #endif + pr_debug("dto_tx_retry_count =%d\n", + pHwData->dto_tx_retry_count); MTO_SetTxCount(adapter, TxRate, RetryCount); } pHwData->dto_tx_frag_count += (RetryCount+1); @@ -597,7 +644,7 @@ Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02) } /* Clear send result buffer */ - pMds->TxResult[ PacketId ] = 0; + pMds->TxResult[PacketId] = 0; } else - pMds->TxResult[ PacketId ] |= ((u16)(pT02->value & 0x0ffff)); + pMds->TxResult[PacketId] |= ((u16)(pT02->value & 0x0ffff)); } diff --git a/drivers/staging/winbond/mds_f.h b/drivers/staging/winbond/mds_f.h index 20e97bfe01e..159b2eb366e 100644 --- a/drivers/staging/winbond/mds_f.h +++ b/drivers/staging/winbond/mds_f.h @@ -1,20 +1,22 @@ #ifndef __WINBOND_MDS_F_H #define __WINBOND_MDS_F_H -#include "wbhal_s.h" +#include "wbhal.h" #include "core.h" unsigned char Mds_initial(struct wbsoft_priv *adapter); -void Mds_Destroy(struct wbsoft_priv *adapter); void Mds_Tx(struct wbsoft_priv *adapter); -void Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pt02); -void Mds_MpduProcess(struct wbsoft_priv *adapter, struct wb35_descriptor *prxdes); -extern void DataDmp(u8 *pdata, u32 len, u32 offset); +void Mds_SendComplete(struct wbsoft_priv *adapter, struct T02_descriptor *pt02); +void Mds_MpduProcess(struct wbsoft_priv *adapter, + struct wb35_descriptor *prxdes); /* For data frame sending */ u16 MDS_GetPacketSize(struct wbsoft_priv *adapter); -void MDS_GetNextPacket(struct wbsoft_priv *adapter, struct wb35_descriptor *pdes); -void MDS_GetNextPacketComplete(struct wbsoft_priv *adapter, struct wb35_descriptor *pdes); -void MDS_SendResult(struct wbsoft_priv *adapter, u8 packetid, unsigned char sendok); +void MDS_GetNextPacket(struct wbsoft_priv *adapter, + struct wb35_descriptor *pdes); +void MDS_GetNextPacketComplete(struct wbsoft_priv *adapter, + struct wb35_descriptor *pdes); +void MDS_SendResult(struct wbsoft_priv *adapter, u8 packetid, + unsigned char sendok); #endif diff --git a/drivers/staging/winbond/mds_s.h b/drivers/staging/winbond/mds_s.h index 89328c5dbda..2972d66c943 100644 --- a/drivers/staging/winbond/mds_s.h +++ b/drivers/staging/winbond/mds_s.h @@ -3,11 +3,10 @@ #include <linux/timer.h> #include <linux/types.h> -#include <asm/atomic.h> +#include <linux/atomic.h> #include "localpara.h" #include "mac_structures.h" -#include "scan_s.h" /* Preamble_Type, see <SFS-802.11G-MIB-203> */ enum { @@ -41,7 +40,7 @@ enum { /* * ================================================================ - * Configration default value + * Configuration default value * ================================================================ */ #define DEFAULT_MULTICASTLISTMAX 32 /* standard */ @@ -108,10 +107,6 @@ struct wb35_mds { u8 TxRate[((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01)][2]; /* [0] current tx rate, [1] fall back rate */ u8 TxInfo[((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01)]; /*Store information for callback function */ - /* for scanning mechanism */ - u8 TxToggle; /* It is TRUE if there are tx activities in some time interval */ - u8 Reserved_[3]; - /* ---- for Tx Parameter */ u16 TxFragmentThreshold; /* For frame body only */ u16 TxRTSThreshold; diff --git a/drivers/staging/winbond/mlme_s.h b/drivers/staging/winbond/mlme_s.h deleted file mode 100644 index a7ef3c78022..00000000000 --- a/drivers/staging/winbond/mlme_s.h +++ /dev/null @@ -1,188 +0,0 @@ -#ifndef __WINBOND_MLME_H -#define __WINBOND_MLME_H - -#include <linux/types.h> -#include <linux/spinlock.h> - -#include "mac_structures.h" -#include "mds_s.h" - -/* - * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - * Mlme.h - * Define the related definitions of MLME module - * - * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - */ - -#define AUTH_REJECT_REASON_CHALLENGE_FAIL 1 - -/* the state of MLME module */ -#define INACTIVE 0x0 -#define IDLE_SCAN 0x1 - -/* the state of MLME/ESS module */ -#define STATE_1 0x2 -#define AUTH_REQ 0x3 -#define AUTH_WEP 0x4 -#define STATE_2 0x5 -#define ASSOC_REQ 0x6 -#define STATE_3 0x7 - -/* the state of MLME/IBSS module */ -#define IBSS_JOIN_SYNC 0x8 -#define IBSS_AUTH_REQ 0x9 -#define IBSS_AUTH_CHANLGE 0xa -#define IBSS_AUTH_WEP 0xb -#define IBSS_AUTH_IND 0xc -#define IBSS_STATE_2 0xd - - - -/* - * ========================================= - * depend on D5C(MAC timing control 03 register): - * MaxTxMSDULifeTime default 0x80000us - */ -#define AUTH_FAIL_TIMEOUT 550 -#define ASSOC_FAIL_TIMEOUT 550 -#define REASSOC_FAIL_TIMEOUT 550 - -/* MLME task global CONSTANTS, STRUCTURE, variables */ - -/* ========================================= - * enum_ResultCode -- - * Result code returned from MLME to SME. - * ========================================= - */ -#define MLME_SUCCESS 0 /* follow spec. */ -#define INVALID_PARAMETERS 1 /* Not following spec. */ -#define NOT_SUPPPORTED 2 -#define TIMEOUT 3 -#define TOO_MANY_SIMULTANEOUS_REQUESTS 4 -#define REFUSED 5 -#define BSS_ALREADY_STARTED_OR_JOINED 6 -#define TRANSMIT_FRAME_FAIL 7 -#define NO_BSS_FOUND 8 -#define RETRY 9 -#define GIVE_UP 10 - - -#define OPEN_AUTH 0 -#define SHARE_AUTH 1 -#define ANY_AUTH 2 -#define WPA_AUTH 3 /* for WPA */ -#define WPAPSK_AUTH 4 -#define WPANONE_AUTH 5 -#ifdef _WPA2_ -#define WPA2_AUTH 6 /* for WPA2 */ -#define WPA2PSK_AUTH 7 -#endif /* end def _WPA2_ */ - -/* - * ========================================= - * define the msg type of MLME module - * ========================================= - */ - -/* from SME */ -#define MLMEMSG_AUTH_REQ 0x0b -#define MLMEMSG_DEAUTH_REQ 0x0c -#define MLMEMSG_ASSOC_REQ 0x0d -#define MLMEMSG_REASSOC_REQ 0x0e -#define MLMEMSG_DISASSOC_REQ 0x0f -#define MLMEMSG_START_IBSS_REQ 0x10 -#define MLMEMSG_IBSS_NET_CFM 0x11 - -/* from RX */ -#define MLMEMSG_RCV_MLMEFRAME 0x20 -#define MLMEMSG_RCV_ASSOCRSP 0x22 -#define MLMEMSG_RCV_REASSOCRSP 0x24 -#define MLMEMSG_RCV_DISASSOC 0x2b -#define MLMEMSG_RCV_AUTH 0x2c -#define MLMEMSG_RCV_DEAUTH 0x2d - - -/* from TX callback */ -#define MLMEMSG_TX_CALLBACK 0x40 -#define MLMEMSG_ASSOCREQ_CALLBACK 0x41 -#define MLMEMSG_REASSOCREQ_CALLBACK 0x43 -#define MLMEMSG_DISASSOC_CALLBACK 0x4a -#define MLMEMSG_AUTH_CALLBACK 0x4c -#define MLMEMSG_DEAUTH_CALLBACK 0x4d - -#define MLMEMSG_TIMEOUT 0x50 - -/* - * ============================================== - * Global data structures - * ============================================== - */ -#define MAX_NUM_TX_MMPDU 2 -#define MAX_MMPDU_SIZE 1512 -#define MAX_NUM_RX_MMPDU 6 - - -/* - * ============================================== - * MACRO - * ============================================== - */ -#define boMLME_InactiveState(_AA_) (_AA_->wState == INACTIVE) -#define boMLME_IdleScanState(_BB_) (_BB_->wState == IDLE_SCAN) -#define boMLME_FoundSTAinfo(_CC_) (_CC_->wState >= IDLE_SCAN) - -typedef struct _MLME_FRAME { - s8 *pMMPDU; - u16 len; - u8 DataType; - u8 IsInUsed; - - spinlock_t MLMESpinLock; - - u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE]; - u8 TxMMPDUInUse[(MAX_NUM_TX_MMPDU + 3) & ~0x03]; - - u16 wNumTxMMPDU; - u16 wNumTxMMPDUDiscarded; - - u8 RxMMPDU[MAX_NUM_RX_MMPDU][MAX_MMPDU_SIZE]; - u8 SaveRxBufSlotInUse[(MAX_NUM_RX_MMPDU + 3) & ~0x03]; - - u16 wNumRxMMPDU; - u16 wNumRxMMPDUDiscarded; - - u16 wNumRxMMPDUInMLME; /* Number of the Rx MMPDU */ - u16 reserved_1; /* in MLME. */ - /* excluding the discarded */ -} MLME_FRAME, *psMLME_FRAME; - -typedef struct _AUTHREQ { - - u8 peerMACaddr[MAC_ADDR_LENGTH]; - u16 wAuthAlgorithm; -} MLME_AUTHREQ_PARA, *psMLME_AUTHREQ_PARA; - -typedef struct _ASSOCREQ { - u8 PeerSTAAddr[MAC_ADDR_LENGTH]; - u16 CapabilityInfo; - u16 ListenInterval; -} __attribute__ ((packed)) MLME_ASSOCREQ_PARA, *psMLME_ASSOCREQ_PARA; - -typedef struct _REASSOCREQ { - u8 NewAPAddr[MAC_ADDR_LENGTH]; - u16 CapabilityInfo; - u16 ListenInterval; -} __attribute__ ((packed)) MLME_REASSOCREQ_PARA, *psMLME_REASSOCREQ_PARA; - -typedef struct _MLMECALLBACK { - u8 *psFramePtr; - u8 bResult; -} MLME_TXCALLBACK, *psMLME_TXCALLBACK; - -typedef struct _RXDATA { - s32 FrameLength; - u8 __attribute__ ((packed)) *pbFramePtr; -} __attribute__ ((packed)) RXDATA, *psRXDATA; - -#endif diff --git a/drivers/staging/winbond/mlmetxrx.c b/drivers/staging/winbond/mlmetxrx.c deleted file mode 100644 index dcd8a11b5d0..00000000000 --- a/drivers/staging/winbond/mlmetxrx.c +++ /dev/null @@ -1,93 +0,0 @@ -/* ============================================================================ - Module Name: - MLMETxRx.C - - Description: - The interface between MDS (MAC Data Service) and MLME. - - Revision History: - -------------------------------------------------------------------------- - 200209 UN20 Jennifer Xu - Initial Release - 20021108 PD43 Austin Liu - 20030117 PD43 Austin Liu - Deleted MLMEReturnPacket and MLMEProcThread() - - Copyright (c) 1996-2002 Winbond Electronics Corp. All Rights Reserved. -============================================================================ */ -#include "sysdef.h" - -#include "mds_f.h" - -/* ============================================================================= */ -u8 MLMESendFrame(struct wbsoft_priv *adapter, u8 *pMMPDU, u16 len, u8 DataType) -/* DataType : FRAME_TYPE_802_11_MANAGEMENT, FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE, - FRAME_TYPE_802_11_DATA */ -{ - if (adapter->sMlmeFrame.IsInUsed != PACKET_FREE_TO_USE) { - adapter->sMlmeFrame.wNumTxMMPDUDiscarded++; - return false; - } - adapter->sMlmeFrame.IsInUsed = PACKET_COME_FROM_MLME; - - /* Keep information for sending */ - adapter->sMlmeFrame.pMMPDU = pMMPDU; - adapter->sMlmeFrame.DataType = DataType; - /* len must be the last setting due to QUERY_SIZE_SECOND of Mds */ - adapter->sMlmeFrame.len = len; - adapter->sMlmeFrame.wNumTxMMPDU++; - - /* H/W will enter power save by set the register. S/W don't send null frame - with PWRMgt bit enbled to enter power save now. */ - - /* Transmit NDIS packet */ - Mds_Tx(adapter); - return true; -} - -void MLME_GetNextPacket(struct wbsoft_priv *adapter, struct wb35_descriptor *desc) -{ - desc->InternalUsed = desc->buffer_start_index + desc->buffer_number; - desc->InternalUsed %= MAX_DESCRIPTOR_BUFFER_INDEX; - desc->buffer_address[desc->InternalUsed] = adapter->sMlmeFrame.pMMPDU; - desc->buffer_size[desc->InternalUsed] = adapter->sMlmeFrame.len; - desc->buffer_total_size += adapter->sMlmeFrame.len; - desc->buffer_number++; - desc->Type = adapter->sMlmeFrame.DataType; -} - -static void MLMEfreeMMPDUBuffer(struct wbsoft_priv *adapter, s8 *pData) -{ - int i; - - /* Reclaim the data buffer */ - for (i = 0; i < MAX_NUM_TX_MMPDU; i++) { - if (pData == (s8 *)&(adapter->sMlmeFrame.TxMMPDU[i])) - break; - } - if (adapter->sMlmeFrame.TxMMPDUInUse[i]) - adapter->sMlmeFrame.TxMMPDUInUse[i] = false; - else { - /* Something wrong - PD43 Add debug code here??? */ - } -} - -void -MLME_SendComplete(struct wbsoft_priv *adapter, u8 PacketID, unsigned char SendOK) -{ - MLME_TXCALLBACK TxCallback; - - /* Reclaim the data buffer */ - adapter->sMlmeFrame.len = 0; - MLMEfreeMMPDUBuffer(adapter, adapter->sMlmeFrame.pMMPDU); - - - TxCallback.bResult = MLME_SUCCESS; - - /* Return resource */ - adapter->sMlmeFrame.IsInUsed = PACKET_FREE_TO_USE; -} - - - diff --git a/drivers/staging/winbond/mlmetxrx_f.h b/drivers/staging/winbond/mlmetxrx_f.h deleted file mode 100644 index d1aa2617d24..00000000000 --- a/drivers/staging/winbond/mlmetxrx_f.h +++ /dev/null @@ -1,25 +0,0 @@ -/* ================================================================ -// MLMETxRx.H -- -// -// Functions defined in MLMETxRx.c. -// -// Copyright (c) 2002 Winbond Electrics Corp. All Rights Reserved. -//================================================================ */ -#ifndef _MLMETXRX_H -#define _MLMETXRX_H - -#include "core.h" - -void MLME_GetNextPacket(struct wbsoft_priv *adapter, struct wb35_descriptor *pDes); -u8 MLMESendFrame(struct wbsoft_priv *adapter, - u8 *pMMPDU, u16 len, u8 DataType); - -void -MLME_SendComplete(struct wbsoft_priv *adapter, u8 PacketID, - unsigned char SendOK); - -#ifdef _IBSS_BEACON_SEQ_STICK_ -s8 SendBCNullData(struct wbsoft_priv *adapter, u16 wIdx); -#endif - -#endif diff --git a/drivers/staging/winbond/mto.c b/drivers/staging/winbond/mto.c index 9cd212783d6..b031ecd4f3c 100644 --- a/drivers/staging/winbond/mto.c +++ b/drivers/staging/winbond/mto.c @@ -17,12 +17,14 @@ * ============================================================================ */ -#include "sysdef.h" #include "sme_api.h" -#include "wbhal_f.h" +#include "wbhal.h" +#include "wb35reg_f.h" +#include "core.h" +#include "mto.h" /* Declare SQ3 to rate and fragmentation threshold table */ -/* Declare fragmentation thresholds table */ +/* Declare fragmentation threshold table */ #define MTO_MAX_FRAG_TH_LEVELS 5 #define MTO_MAX_DATA_RATE_LEVELS 12 @@ -32,29 +34,18 @@ u16 MTO_Frag_Th_Tbl[MTO_MAX_FRAG_TH_LEVELS] = { /* * Declare data rate table: - * The following table will be changed at anytime if the opration rate + * The following table will be changed at anytime if the operation rate * supported by AP don't match the table */ static u8 MTO_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] = { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; -static int TotalTxPkt; -static int TotalTxPktRetry; /* this record the retry rate at different data rate */ static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS]; -static int PeriodTotalTxPkt; -static int PeriodTotalTxPktRetry; - static u8 boSparseTxTraffic; -void MTO_Init(struct wbsoft_priv *adapter); -void TxRateReductionCtrl(struct wbsoft_priv *adapter); -void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 t0, u8 index); -void MTO_TxFailed(struct wbsoft_priv *adapter); -void hal_get_dto_para(struct wbsoft_priv *adapter, char *buffer); - /* * =========================================================================== * MTO_Init -- @@ -173,9 +164,4 @@ void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 tx_rate, u8 index) MTO_HAL()->dto_tx_retry_count += index; MTO_HAL()->dto_tx_frag_count += (index + 1); } - TotalTxPkt++; - TotalTxPktRetry += (index + 1); - - PeriodTotalTxPkt++; - PeriodTotalTxPktRetry += (index + 1); } diff --git a/drivers/staging/winbond/mto.h b/drivers/staging/winbond/mto.h index a0f659cf99f..8d41eeda45b 100644 --- a/drivers/staging/winbond/mto.h +++ b/drivers/staging/winbond/mto.h @@ -127,12 +127,8 @@ extern u16 MTO_Frag_Th_Tbl[]; #define MTO_DATA_RATE() MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()] #define MTO_FRAG_TH() MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()] -extern void MTO_Init(struct wbsoft_priv *); -extern void MTO_PeriodicTimerExpired(struct wbsoft_priv *); -extern void MTO_SetDTORateRange(struct wbsoft_priv *, u8 *, u8); -extern u8 MTO_GetTxRate(struct wbsoft_priv *adapter, u32 fpdu_len); -extern u8 MTO_GetTxFallbackRate(struct wbsoft_priv *adapter); -extern void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 t0, u8 index); +void MTO_Init(struct wbsoft_priv *); +void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 t0, u8 index); #endif /* __MTO_H__ */ diff --git a/drivers/staging/winbond/phy_calibration.c b/drivers/staging/winbond/phy_calibration.c index 78935865df1..8aecced62dd 100644 --- a/drivers/staging/winbond/phy_calibration.c +++ b/drivers/staging/winbond/phy_calibration.c @@ -10,342 +10,264 @@ */ /****************** INCLUDE FILES SECTION ***********************************/ -#include "sysdef.h" #include "phy_calibration.h" -#include "wbhal_f.h" +#include "wbhal.h" +#include "wb35reg_f.h" +#include "core.h" /****************** DEBUG CONSTANT AND MACRO SECTION ************************/ /****************** LOCAL CONSTANT AND MACRO SECTION ************************/ #define LOOP_TIMES 20 -#define US 1000//MICROSECOND +#define US 1000/* MICROSECOND*/ #define AG_CONST 0.6072529350 #define FIXED(X) ((s32)((X) * 32768.0)) -#define DEG2RAD(X) 0.017453 * (X) - -static const s32 Angles[] = -{ - FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)), - FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)), - FIXED(DEG2RAD(0.895174)),FIXED(DEG2RAD(0.447614)),FIXED(DEG2RAD(0.223811)), - FIXED(DEG2RAD(0.111906)),FIXED(DEG2RAD(0.055953)),FIXED(DEG2RAD(0.027977)) +#define DEG2RAD(X) (0.017453 * (X)) + +static const s32 Angles[] = { + FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), + FIXED(DEG2RAD(14.0362)), FIXED(DEG2RAD(7.12502)), + FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)), + FIXED(DEG2RAD(0.895174)), FIXED(DEG2RAD(0.447614)), + FIXED(DEG2RAD(0.223811)), FIXED(DEG2RAD(0.111906)), + FIXED(DEG2RAD(0.055953)), FIXED(DEG2RAD(0.027977)) }; /****************** LOCAL FUNCTION DECLARATION SECTION **********************/ -//void _phy_rf_write_delay(struct hw_data *phw_data); -//void phy_init_rf(struct hw_data *phw_data); + +/* + * void _phy_rf_write_delay(struct hw_data *phw_data); + * void phy_init_rf(struct hw_data *phw_data); + */ /****************** FUNCTION DEFINITION SECTION *****************************/ -s32 _s13_to_s32(u32 data) +static s32 _s13_to_s32(u32 data) { - u32 val; + u32 val; - val = (data & 0x0FFF); + val = (data & 0x0FFF); - if ((data & BIT(12)) != 0) - { - val |= 0xFFFFF000; - } + if ((data & BIT(12)) != 0) + val |= 0xFFFFF000; - return ((s32) val); + return (s32) val; } -u32 _s32_to_s13(s32 data) +/****************************************************************************/ +static s32 _s4_to_s32(u32 data) { - u32 val; + s32 val; - if (data > 4095) - { - data = 4095; - } - else if (data < -4096) - { - data = -4096; - } + val = (data & 0x0007); - val = data & 0x1FFF; + if ((data & BIT(3)) != 0) + val |= 0xFFFFFFF8; - return val; + return val; } -/****************************************************************************/ -s32 _s4_to_s32(u32 data) +static u32 _s32_to_s4(s32 data) { - s32 val; + u32 val; - val = (data & 0x0007); + if (data > 7) + data = 7; + else if (data < -8) + data = -8; - if ((data & BIT(3)) != 0) - { - val |= 0xFFFFFFF8; - } + val = data & 0x000F; - return val; + return val; } -u32 _s32_to_s4(s32 data) +/****************************************************************************/ +static s32 _s5_to_s32(u32 data) { - u32 val; + s32 val; - if (data > 7) - { - data = 7; - } - else if (data < -8) - { - data = -8; - } + val = (data & 0x000F); - val = data & 0x000F; + if ((data & BIT(4)) != 0) + val |= 0xFFFFFFF0; - return val; + return val; } -/****************************************************************************/ -s32 _s5_to_s32(u32 data) +static u32 _s32_to_s5(s32 data) { - s32 val; + u32 val; - val = (data & 0x000F); + if (data > 15) + data = 15; + else if (data < -16) + data = -16; - if ((data & BIT(4)) != 0) - { - val |= 0xFFFFFFF0; - } + val = data & 0x001F; - return val; + return val; } -u32 _s32_to_s5(s32 data) +/****************************************************************************/ +static s32 _s6_to_s32(u32 data) { - u32 val; + s32 val; - if (data > 15) - { - data = 15; - } - else if (data < -16) - { - data = -16; - } + val = (data & 0x001F); - val = data & 0x001F; + if ((data & BIT(5)) != 0) + val |= 0xFFFFFFE0; - return val; + return val; } -/****************************************************************************/ -s32 _s6_to_s32(u32 data) +static u32 _s32_to_s6(s32 data) { - s32 val; + u32 val; - val = (data & 0x001F); + if (data > 31) + data = 31; + else if (data < -32) + data = -32; - if ((data & BIT(5)) != 0) - { - val |= 0xFFFFFFE0; - } + val = data & 0x003F; - return val; + return val; } -u32 _s32_to_s6(s32 data) +/****************************************************************************/ +static s32 _floor(s32 n) { - u32 val; - - if (data > 31) - { - data = 31; - } - else if (data < -32) - { - data = -32; - } - - val = data & 0x003F; + if (n > 0) + n += 5; + else + n -= 5; - return val; + return n/10; } /****************************************************************************/ -s32 _s9_to_s32(u32 data) +/* + * The following code is sqare-root function. + * sqsum is the input and the output is sq_rt; + * The maximum of sqsum = 2^27 -1; + */ +static u32 _sqrt(u32 sqsum) { - s32 val; + u32 sq_rt; + + int g0, g1, g2, g3, g4; + int seed; + int next; + int step; + + g4 = sqsum / 100000000; + g3 = (sqsum - g4*100000000) / 1000000; + g2 = (sqsum - g4*100000000 - g3*1000000) / 10000; + g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) / 100; + g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100); + + next = g4; + step = 0; + seed = 0; + while (((seed+1)*(step+1)) <= next) { + step++; + seed++; + } - val = data & 0x00FF; + sq_rt = seed * 10000; + next = (next-(seed*step))*100 + g3; - if ((data & BIT(8)) != 0) - { - val |= 0xFFFFFF00; - } + step = 0; + seed = 2 * seed * 10; + while (((seed+1)*(step+1)) <= next) { + step++; + seed++; + } - return val; -} + sq_rt = sq_rt + step * 1000; + next = (next - seed * step) * 100 + g2; + seed = (seed + step) * 10; + step = 0; + while (((seed+1)*(step+1)) <= next) { + step++; + seed++; + } -u32 _s32_to_s9(s32 data) -{ - u32 val; + sq_rt = sq_rt + step * 100; + next = (next - seed * step) * 100 + g1; + seed = (seed + step) * 10; + step = 0; - if (data > 255) - { - data = 255; - } - else if (data < -256) - { - data = -256; - } + while (((seed+1)*(step+1)) <= next) { + step++; + seed++; + } - val = data & 0x01FF; + sq_rt = sq_rt + step * 10; + next = (next - seed * step) * 100 + g0; + seed = (seed + step) * 10; + step = 0; - return val; -} + while (((seed+1)*(step+1)) <= next) { + step++; + seed++; + } -/****************************************************************************/ -s32 _floor(s32 n) -{ - if (n > 0) - { - n += 5; - } - else - { - n -= 5; - } - - return (n/10); -} + sq_rt = sq_rt + step; -/****************************************************************************/ -// The following code is sqare-root function. -// sqsum is the input and the output is sq_rt; -// The maximum of sqsum = 2^27 -1; -u32 _sqrt(u32 sqsum) -{ - u32 sq_rt; - - int g0, g1, g2, g3, g4; - int seed; - int next; - int step; - - g4 = sqsum / 100000000; - g3 = (sqsum - g4*100000000) /1000000; - g2 = (sqsum - g4*100000000 - g3*1000000) /10000; - g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) /100; - g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100); - - next = g4; - step = 0; - seed = 0; - while (((seed+1)*(step+1)) <= next) - { - step++; - seed++; - } - - sq_rt = seed * 10000; - next = (next-(seed*step))*100 + g3; - - step = 0; - seed = 2 * seed * 10; - while (((seed+1)*(step+1)) <= next) - { - step++; - seed++; - } - - sq_rt = sq_rt + step * 1000; - next = (next - seed * step) * 100 + g2; - seed = (seed + step) * 10; - step = 0; - while (((seed+1)*(step+1)) <= next) - { - step++; - seed++; - } - - sq_rt = sq_rt + step * 100; - next = (next - seed * step) * 100 + g1; - seed = (seed + step) * 10; - step = 0; - - while (((seed+1)*(step+1)) <= next) - { - step++; - seed++; - } - - sq_rt = sq_rt + step * 10; - next = (next - seed* step) * 100 + g0; - seed = (seed + step) * 10; - step = 0; - - while (((seed+1)*(step+1)) <= next) - { - step++; - seed++; - } - - sq_rt = sq_rt + step; - - return sq_rt; + return sq_rt; } /****************************************************************************/ -void _sin_cos(s32 angle, s32 *sin, s32 *cos) +static void _sin_cos(s32 angle, s32 *sin, s32 *cos) { - s32 X, Y, TargetAngle, CurrAngle; - unsigned Step; - - X=FIXED(AG_CONST); // AG_CONST * cos(0) - Y=0; // AG_CONST * sin(0) - TargetAngle=abs(angle); - CurrAngle=0; - - for (Step=0; Step < 12; Step++) - { - s32 NewX; - - if(TargetAngle > CurrAngle) - { - NewX=X - (Y >> Step); - Y=(X >> Step) + Y; - X=NewX; - CurrAngle += Angles[Step]; - } - else - { - NewX=X + (Y >> Step); - Y=-(X >> Step) + Y; - X=NewX; - CurrAngle -= Angles[Step]; - } - } - - if (angle > 0) - { - *cos = X; - *sin = Y; - } - else - { - *cos = X; - *sin = -Y; - } + s32 X, Y, TargetAngle, CurrAngle; + unsigned Step; + + X = FIXED(AG_CONST); /* AG_CONST * cos(0) */ + Y = 0; /* AG_CONST * sin(0) */ + TargetAngle = abs(angle); + CurrAngle = 0; + + for (Step = 0; Step < 12; Step++) { + s32 NewX; + + if (TargetAngle > CurrAngle) { + NewX = X - (Y >> Step); + Y = (X >> Step) + Y; + X = NewX; + CurrAngle += Angles[Step]; + } else { + NewX = X + (Y >> Step); + Y = -(X >> Step) + Y; + X = NewX; + CurrAngle -= Angles[Step]; + } + } + + if (angle > 0) { + *cos = X; + *sin = Y; + } else { + *cos = X; + *sin = -Y; + } } -static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number, u32 * pValue) +static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number, + u32 *pValue) { if (number < 0x1000) number += 0x1000; return Wb35Reg_ReadSync(pHwData, number, pValue); } -#define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (u32 *)_C ) +#define hw_get_dxx_reg(_A, _B, _C) hal_get_dxx_reg(_A, _B, (u32 *)_C) -static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, u32 value) +static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, + u32 value) { unsigned char ret; @@ -354,73 +276,64 @@ static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, u32 va ret = Wb35Reg_WriteSync(pHwData, number, value); return ret; } -#define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C ) +#define hw_set_dxx_reg(_A, _B, _C) hal_set_dxx_reg(_A, _B, (u32)_C) -void _reset_rx_cal(struct hw_data *phw_data) +static void _reset_rx_cal(struct hw_data *phw_data) { u32 val; hw_get_dxx_reg(phw_data, 0x54, &val); - if (phw_data->revision == 0x2002) // 1st-cut - { + if (phw_data->revision == 0x2002) /* 1st-cut */ val &= 0xFFFF0000; - } - else // 2nd-cut - { + else /* 2nd-cut */ val &= 0x000003FF; - } hw_set_dxx_reg(phw_data, 0x54, val); } -// ************for winbond calibration********* -// +/**************for winbond calibration*********/ + -// -// -// ********************************************* -void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency) + +/**********************************************/ +static void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency) { - u32 reg_agc_ctrl3; - u32 reg_a_acq_ctrl; - u32 reg_b_acq_ctrl; - u32 val; - - PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n")); - phy_init_rf(phw_data); - - // set calibration channel - if( (RF_WB_242 == phw_data->phy_type) || - (RF_WB_242_1 == phw_data->phy_type) ) // 20060619.5 Add - { - if ((frequency >= 2412) && (frequency <= 2484)) - { - // w89rf242 change frequency to 2390Mhz - PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n")); + u32 reg_agc_ctrl3; + u32 reg_a_acq_ctrl; + u32 reg_b_acq_ctrl; + u32 val; + + PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n")); + phy_init_rf(phw_data); + + /* set calibration channel */ + if ((RF_WB_242 == phw_data->phy_type) || + (RF_WB_242_1 == phw_data->phy_type)) /* 20060619.5 Add */{ + if ((frequency >= 2412) && (frequency <= 2484)) { + /* w89rf242 change frequency to 2390Mhz */ + PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n")); phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); - } - } - else - { + } + } else { } - // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel + /* reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel */ hw_get_dxx_reg(phw_data, 0x5C, &val); val &= ~(0x03FF); hw_set_dxx_reg(phw_data, 0x5C, val); - // reset the TX and RX IQ calibration data + /* reset the TX and RX IQ calibration data */ hw_set_dxx_reg(phw_data, 0x3C, 0); hw_set_dxx_reg(phw_data, 0x54, 0); - hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed + hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */ - // a. Disable AGC + /* a. Disable AGC */ hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3); reg_agc_ctrl3 &= ~BIT(2); reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); @@ -430,7 +343,7 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen val |= MASK_AGC_FIX_GAIN; hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); - // b. Turn off BB RX + /* b. Turn off BB RX */ hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl); reg_a_acq_ctrl |= MASK_AMER_OFF_REG; hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); @@ -439,9 +352,9 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen reg_b_acq_ctrl |= MASK_BMER_OFF_REG; hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); - // c. Make sure MAC is in receiving mode - // d. Turn ON ADC calibration - // - ADC calibrator is triggered by this signal rising from 0 to 1 + /* c. Make sure MAC is in receiving mode + * d. Turn ON ADC calibration + * - ADC calibrator is triggered by this signal rising from 0 to 1 */ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); val &= ~MASK_ADC_DC_CAL_STR; hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); @@ -449,7 +362,7 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen val |= MASK_ADC_DC_CAL_STR; hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); - // e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" + /* e. The results are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" */ #ifdef _DEBUG hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val); PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val)); @@ -457,292 +370,32 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen PHY_DEBUG(("[CAL] ** adc_dc_cal_i = %d (0x%04X)\n", _s9_to_s32(val&0x000001FF), val&0x000001FF)); PHY_DEBUG(("[CAL] ** adc_dc_cal_q = %d (0x%04X)\n", - _s9_to_s32((val&0x0003FE00)>>9), (val&0x0003FE00)>>9)); + _s9_to_s32((val&0x0003FE00)>>9), + (val&0x0003FE00)>>9)); #endif hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); val &= ~MASK_ADC_DC_CAL_STR; hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); - // f. Turn on BB RX - //hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl); + /* f. Turn on BB RX */ + /* hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl); */ reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG; hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); - //hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, ®_b_acq_ctrl); + /* hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, ®_b_acq_ctrl); */ reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG; hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); - // g. Enable AGC - //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); + /* g. Enable AGC */ + /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */ reg_agc_ctrl3 |= BIT(2); reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); } -//////////////////////////////////////////////////////// -void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data) -{ - u32 reg_agc_ctrl3; - u32 reg_mode_ctrl; - u32 reg_dc_cancel; - s32 iqcal_image_i; - s32 iqcal_image_q; - u32 sqsum; - s32 mag_0; - s32 mag_1; - s32 fix_cancel_dc_i = 0; - u32 val; - int loop; - - PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n")); - - // a. Set to "TX calibration mode" - - //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits - phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); - //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit - phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); - //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized - phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); - //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized - phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); - //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode - phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); - - hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed - - // a. Disable AGC - hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3); - reg_agc_ctrl3 &= ~BIT(2); - reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); - hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); - - hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); - val |= MASK_AGC_FIX_GAIN; - hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); - - // b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); - - PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); - reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); - - // mode=2, tone=0 - //reg_mode_ctrl |= (MASK_CALIB_START|2); - - // mode=2, tone=1 - //reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2)); - - // mode=2, tone=2 - reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2)); - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - - hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel); - PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); - - for (loop = 0; loop < LOOP_TIMES; loop++) - { - PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); - - // c. - // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel - reg_dc_cancel &= ~(0x03FF); - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); - - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); - - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); - sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; - mag_0 = (s32) _sqrt(sqsum); - PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", - mag_0, iqcal_image_i, iqcal_image_q)); - - // d. - reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT); - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); - - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); - - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); - sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; - mag_1 = (s32) _sqrt(sqsum); - PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", - mag_1, iqcal_image_i, iqcal_image_q)); - - // e. Calculate the correct DC offset cancellation value for I - if (mag_0 != mag_1) - { - fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000); - } - else - { - if (mag_0 == mag_1) - { - PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); - } - - fix_cancel_dc_i = 0; - } - - PHY_DEBUG(("[CAL] ** fix_cancel_dc_i = %d (0x%04X)\n", - fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i))); - - if ((abs(mag_1-mag_0)*6) > mag_0) - { - break; - } - } - - if ( loop >= 19 ) - fix_cancel_dc_i = 0; - - reg_dc_cancel &= ~(0x03FF); - reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_i) << CANCEL_DC_I_SHIFT); - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); - - // g. - reg_mode_ctrl &= ~MASK_CALIB_START; - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); -} - -/////////////////////////////////////////////////////// -void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data) -{ - u32 reg_agc_ctrl3; - u32 reg_mode_ctrl; - u32 reg_dc_cancel; - s32 iqcal_image_i; - s32 iqcal_image_q; - u32 sqsum; - s32 mag_0; - s32 mag_1; - s32 fix_cancel_dc_q = 0; - u32 val; - int loop; - - PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n")); - //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits - phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); - //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit - phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); - //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized - phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); - //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized - phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); - //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode - phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); - - hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed - - // a. Disable AGC - hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3); - reg_agc_ctrl3 &= ~BIT(2); - reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); - hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); - - hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); - val |= MASK_AGC_FIX_GAIN; - hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); - - // a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); - PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); - - //reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); - reg_mode_ctrl &= ~(MASK_IQCAL_MODE); - reg_mode_ctrl |= (MASK_CALIB_START|3); - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - - hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel); - PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); - - for (loop = 0; loop < LOOP_TIMES; loop++) - { - PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); - - // b. - // reset cancel_dc_q[4:0] in register DC_Cancel - reg_dc_cancel &= ~(0x001F); - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); - - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); - - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); - sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; - mag_0 = _sqrt(sqsum); - PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", - mag_0, iqcal_image_i, iqcal_image_q)); - - // c. - reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT); - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); - - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); - - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); - sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; - mag_1 = _sqrt(sqsum); - PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", - mag_1, iqcal_image_i, iqcal_image_q)); - - // d. Calculate the correct DC offset cancellation value for I - if (mag_0 != mag_1) - { - fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000); - } - else - { - if (mag_0 == mag_1) - { - PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); - } - - fix_cancel_dc_q = 0; - } - - PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n", - fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q))); - - if ((abs(mag_1-mag_0)*6) > mag_0) - { - break; - } - } - - if ( loop >= 19 ) - fix_cancel_dc_q = 0; - - reg_dc_cancel &= ~(0x001F); - reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_q) << CANCEL_DC_Q_SHIFT); - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); - - - // f. - reg_mode_ctrl &= ~MASK_CALIB_START; - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); -} - -//20060612.1.a 20060718.1 Modify -u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, +/* 20060612.1.a 20060718.1 Modify */ +static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, s32 a_2_threshold, s32 b_2_threshold) { @@ -765,7 +418,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, s32 temp1, temp2; u32 val; u16 loop; - s32 iqcal_tone_i_avg,iqcal_tone_q_avg; + s32 iqcal_tone_i_avg, iqcal_tone_q_avg; u8 verify_count; int capture_time; @@ -780,18 +433,19 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, loop = LOOP_TIMES; - while (loop > 0) - { - PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1))); + while (loop > 0) { + PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", + (LOOP_TIMES-loop+1))); - iqcal_tone_i_avg=0; - iqcal_tone_q_avg=0; - if( !hw_set_dxx_reg(phw_data, 0x3C, 0x00) ) // 20060718.1 modify + iqcal_tone_i_avg = 0; + iqcal_tone_q_avg = 0; + if (!hw_set_dxx_reg(phw_data, 0x3C, 0x00)) /* 20060718.1 modify */ return 0; - for(capture_time=0;capture_time<10;capture_time++) - { - // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to - // enable "IQ alibration Mode II" + for (capture_time = 0; capture_time < 10; capture_time++) { + /* + * a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" + * to 0x1 to enable "IQ calibration Mode II" + */ reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); reg_mode_ctrl &= ~MASK_IQCAL_MODE; reg_mode_ctrl |= (MASK_CALIB_START|0x02); @@ -799,7 +453,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - // b. + /* b. */ hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); @@ -813,36 +467,35 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, iq_mag_0_tx = (s32) _sqrt(sqsum); PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx)); - // c. Set "calib_start" to 0x0 + /* c. Set "calib_start" to 0x0 */ reg_mode_ctrl &= ~MASK_CALIB_START; hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - // d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to - // enable "IQ alibration Mode II" - //hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); + /* + * d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" + * to 0x1 to enable "IQ calibration Mode II" + */ + /* hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); */ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); reg_mode_ctrl &= ~MASK_IQCAL_MODE; reg_mode_ctrl |= (MASK_CALIB_START|0x03); hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - // e. + /* e. */ hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); iqcal_tone_i = _s13_to_s32(val & 0x00001FFF); iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", - iqcal_tone_i, iqcal_tone_q)); - if( capture_time == 0) - { + iqcal_tone_i, iqcal_tone_q)); + if (capture_time == 0) continue; - } - else - { - iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time; - iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time; + else { + iqcal_tone_i_avg = (iqcal_tone_i_avg*(capture_time-1) + iqcal_tone_i)/capture_time; + iqcal_tone_q_avg = (iqcal_tone_q_avg*(capture_time-1) + iqcal_tone_q)/capture_time; } } @@ -857,11 +510,10 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n", rot_i_b, rot_q_b)); - // f. + /* f. */ divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2; - if (divisor == 0) - { + if (divisor == 0) { PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n")); PHY_DEBUG(("[CAL] ******************************************\n")); @@ -876,18 +528,16 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, phw_data->iq_rsdl_gain_tx_d2 = a_2; phw_data->iq_rsdl_phase_tx_d2 = b_2; - //if ((abs(a_2) < 150) && (abs(b_2) < 100)) - //if ((abs(a_2) < 200) && (abs(b_2) < 200)) - if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold)) - { + /* if ((abs(a_2) < 150) && (abs(b_2) < 100)) */ + /* if ((abs(a_2) < 200) && (abs(b_2) < 200)) */ + if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold)) { verify_count++; PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); PHY_DEBUG(("[CAL] ******************************************\n")); - if (verify_count > 2) - { + if (verify_count > 2) { PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n")); PHY_DEBUG(("[CAL] **************************************\n")); @@ -895,37 +545,29 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, } continue; - } - else - { + } else verify_count = 0; - } _sin_cos(b_2, &sin_b, &cos_b); _sin_cos(b_2*2, &sin_2b, &cos_2b); PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); - if (cos_2b == 0) - { + if (cos_2b == 0) { PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); PHY_DEBUG(("[CAL] ******************************************\n")); break; } - // 1280 * 32768 = 41943040 + /* 1280 * 32768 = 41943040 */ temp1 = (41943040/cos_2b)*cos_b; - //temp2 = (41943040/cos_2b)*sin_b*(-1); - if (phw_data->revision == 0x2002) // 1st-cut - { + /* temp2 = (41943040/cos_2b)*sin_b*(-1); */ + if (phw_data->revision == 0x2002) /* 1st-cut */ temp2 = (41943040/cos_2b)*sin_b*(-1); - } - else // 2nd-cut - { + else /* 2nd-cut */ temp2 = (41943040*4/cos_2b)*sin_b*(-1); - } tx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); tx_cal_flt_b[1] = _floor(temp2/(32768+a_2)); @@ -937,37 +579,34 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b[3])); tx_cal[2] = tx_cal_flt_b[2]; - tx_cal[2] = tx_cal[2] +3; + tx_cal[2] = tx_cal[2] + 3; tx_cal[1] = tx_cal[2]; tx_cal[3] = tx_cal_flt_b[3] - 128; - tx_cal[0] = -tx_cal[3]+1; + tx_cal[0] = -tx_cal[3] + 1; PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal[0])); PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal[1])); PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2])); PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3])); - //if ((tx_cal[0] == 0) && (tx_cal[1] == 0) && - // (tx_cal[2] == 0) && (tx_cal[3] == 0)) - //{ - // PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); - // PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n")); - // PHY_DEBUG(("[CAL] ******************************************\n")); - // return 0; - //} - - // g. - if (phw_data->revision == 0x2002) // 1st-cut - { + /* if ((tx_cal[0] == 0) && (tx_cal[1] == 0) && + (tx_cal[2] == 0) && (tx_cal[3] == 0)) + { */ + /* PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); + * PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n")); + * PHY_DEBUG(("[CAL] ******************************************\n")); + * return 0; + } */ + + /* g. */ + if (phw_data->revision == 0x2002) /* 1st-cut */{ hw_get_dxx_reg(phw_data, 0x54, &val); PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); - } - else // 2nd-cut - { + } else /* 2nd-cut */{ hw_get_dxx_reg(phw_data, 0x3C, &val); PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); @@ -982,22 +621,17 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2])); PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3])); - if (phw_data->revision == 0x2002) // 1st-cut - { - if (((tx_cal_reg[0]==7) || (tx_cal_reg[0]==(-8))) && - ((tx_cal_reg[3]==7) || (tx_cal_reg[3]==(-8)))) - { + if (phw_data->revision == 0x2002) /* 1st-cut */{ + if (((tx_cal_reg[0] == 7) || (tx_cal_reg[0] == (-8))) && + ((tx_cal_reg[3] == 7) || (tx_cal_reg[3] == (-8)))) { PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); PHY_DEBUG(("[CAL] **************************************\n")); break; } - } - else // 2nd-cut - { - if (((tx_cal_reg[0]==31) || (tx_cal_reg[0]==(-32))) && - ((tx_cal_reg[3]==31) || (tx_cal_reg[3]==(-32)))) - { + } else /* 2nd-cut */{ + if (((tx_cal_reg[0] == 31) || (tx_cal_reg[0] == (-32))) && + ((tx_cal_reg[3] == 31) || (tx_cal_reg[3] == (-32)))) { PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); PHY_DEBUG(("[CAL] **************************************\n")); @@ -1014,8 +648,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2])); PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3])); - if (phw_data->revision == 0x2002) // 1st-cut - { + if (phw_data->revision == 0x2002) /* 1st-cut */{ val &= 0x0000FFFF; val |= ((_s32_to_s4(tx_cal[0]) << 28)| (_s32_to_s4(tx_cal[1]) << 24)| @@ -1024,9 +657,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, hw_set_dxx_reg(phw_data, 0x54, val); PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); return 0; - } - else // 2nd-cut - { + } else /* 2nd-cut */{ val &= 0x000003FF; val |= ((_s32_to_s5(tx_cal[0]) << 27)| (_s32_to_s6(tx_cal[1]) << 21)| @@ -1037,7 +668,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, return 0; } - // i. Set "calib_start" to 0x0 + /* i. Set "calib_start" to 0x0 */ reg_mode_ctrl &= ~MASK_CALIB_START; hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); @@ -1048,7 +679,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, return 1; } -void _tx_iq_calibration_winbond(struct hw_data *phw_data) +static void _tx_iq_calibration_winbond(struct hw_data *phw_data) { u32 reg_agc_ctrl3; #ifdef _DEBUG @@ -1061,26 +692,26 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data) PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n")); - //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits + /* 0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */ phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); - //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit - phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); // 20060612.1.a 0x1905D6); - //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized - phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); //0x24C60A (high temperature) - //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized - phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); // 20060612.1.a 0x06890C); - //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode + /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */ + phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); /* 20060612.1.a 0x1905D6); */ + /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */ + phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); /* 0x24C60A (high temperature) */ + /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */ + phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); /* 20060612.1.a 0x06890C); */ + /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */ phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); - //; [BB-chip]: Calibration (6f).Send test pattern - //; [BB-chip]: Calibration (6g). Search RXGCL optimal value - //; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table - //phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); + /* ; [BB-chip]: Calibration (6f).Send test pattern */ + /* ; [BB-chip]: Calibration (6g). Search RXGCL optimal value */ + /* ; [BB-chip]: Calibration (6h). Calculate TX-path IQ imbalance and setting TX path IQ compensation table */ + /* phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); */ - msleep(30); // 20060612.1.a 30ms delay. Add the follow 2 lines - //To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750 - adjust_TXVGA_for_iq_mag( phw_data ); + msleep(30); /* 20060612.1.a 30ms delay. Add the follow 2 lines */ + /* To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750 */ + adjust_TXVGA_for_iq_mag(phw_data); - // a. Disable AGC + /* a. Disable AGC */ hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3); reg_agc_ctrl3 &= ~BIT(2); reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); @@ -1092,16 +723,12 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data) result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100); - if (result > 0) - { - if (phw_data->revision == 0x2002) // 1st-cut - { + if (result > 0) { + if (phw_data->revision == 0x2002) /* 1st-cut */{ hw_get_dxx_reg(phw_data, 0x54, &val); val &= 0x0000FFFF; hw_set_dxx_reg(phw_data, 0x54, val); - } - else // 2nd-cut - { + } else /* 2nd-cut*/{ hw_get_dxx_reg(phw_data, 0x3C, &val); val &= 0x000003FF; hw_set_dxx_reg(phw_data, 0x3C, val); @@ -1109,32 +736,24 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data) result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200); - if (result > 0) - { - if (phw_data->revision == 0x2002) // 1st-cut - { + if (result > 0) { + if (phw_data->revision == 0x2002) /* 1st-cut */{ hw_get_dxx_reg(phw_data, 0x54, &val); val &= 0x0000FFFF; hw_set_dxx_reg(phw_data, 0x54, val); - } - else // 2nd-cut - { + } else /* 2nd-cut*/{ hw_get_dxx_reg(phw_data, 0x3C, &val); val &= 0x000003FF; hw_set_dxx_reg(phw_data, 0x3C, val); } result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400); - if (result > 0) - { - if (phw_data->revision == 0x2002) // 1st-cut - { + if (result > 0) { + if (phw_data->revision == 0x2002) /* 1st-cut */{ hw_get_dxx_reg(phw_data, 0x54, &val); val &= 0x0000FFFF; hw_set_dxx_reg(phw_data, 0x54, val); - } - else // 2nd-cut - { + } else /* 2nd-cut */{ hw_get_dxx_reg(phw_data, 0x3C, &val); val &= 0x000003FF; hw_set_dxx_reg(phw_data, 0x3C, val); @@ -1143,20 +762,16 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data) result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500); - if (result > 0) - { + if (result > 0) { PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n")); PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n")); PHY_DEBUG(("[CAL] **************************************\n")); - if (phw_data->revision == 0x2002) // 1st-cut - { + if (phw_data->revision == 0x2002) /* 1st-cut */{ hw_get_dxx_reg(phw_data, 0x54, &val); val &= 0x0000FFFF; hw_set_dxx_reg(phw_data, 0x54, val); - } - else // 2nd-cut - { + } else /* 2nd-cut */{ hw_get_dxx_reg(phw_data, 0x3C, &val); val &= 0x000003FF; hw_set_dxx_reg(phw_data, 0x3C, val); @@ -1166,30 +781,27 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data) } } - // i. Set "calib_start" to 0x0 + /* i. Set "calib_start" to 0x0 */ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); reg_mode_ctrl &= ~MASK_CALIB_START; hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - // g. Enable AGC - //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); + /* g. Enable AGC */ + /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */ reg_agc_ctrl3 |= BIT(2); reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); #ifdef _DEBUG - if (phw_data->revision == 0x2002) // 1st-cut - { + if (phw_data->revision == 0x2002) /* 1st-cut */{ hw_get_dxx_reg(phw_data, 0x54, &val); PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); - } - else // 2nd-cut - { + } else /* 2nd-cut */ { hw_get_dxx_reg(phw_data, 0x3C, &val); PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); @@ -1206,12 +818,14 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data) #endif - // for test - BEN - // RF Control Override + /* + * for test - BEN + * RF Control Override + */ } -///////////////////////////////////////////////////////////////////////////////////////// -u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency) +/*****************************************************/ +static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency) { u32 reg_mode_ctrl; s32 iqcal_tone_i; @@ -1236,85 +850,69 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre u32 pwr_image; u8 verify_count; - s32 iqcal_tone_i_avg,iqcal_tone_q_avg; - s32 iqcal_image_i_avg,iqcal_image_q_avg; - u16 capture_time; + s32 iqcal_tone_i_avg, iqcal_tone_q_avg; + s32 iqcal_image_i_avg, iqcal_image_q_avg; + u16 capture_time; PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n")); PHY_DEBUG(("[CAL] ** factor = %d\n", factor)); + hw_set_dxx_reg(phw_data, 0x58, 0x44444444); /* IQ_Alpha */ -// RF Control Override - hw_get_cxx_reg(phw_data, 0x80, &val); - val |= BIT(19); - hw_set_cxx_reg(phw_data, 0x80, val); - -// RF_Ctrl - hw_get_cxx_reg(phw_data, 0xE4, &val); - val |= BIT(0); - hw_set_cxx_reg(phw_data, 0xE4, val); - PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val)); - - hw_set_dxx_reg(phw_data, 0x58, 0x44444444); // IQ_Alpha - - // b. + /* b. */ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); verify_count = 0; - //for (loop = 0; loop < 1; loop++) - //for (loop = 0; loop < LOOP_TIMES; loop++) + /* for (loop = 0; loop < 1; loop++) */ + /* for (loop = 0; loop < LOOP_TIMES; loop++) */ loop = LOOP_TIMES; - while (loop > 0) - { - PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1))); - iqcal_tone_i_avg=0; - iqcal_tone_q_avg=0; - iqcal_image_i_avg=0; - iqcal_image_q_avg=0; - capture_time=0; - - for(capture_time=0; capture_time<10; capture_time++) - { - // i. Set "calib_start" to 0x0 - reg_mode_ctrl &= ~MASK_CALIB_START; - if( !hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl) )//20060718.1 modify - return 0; - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); + while (loop > 0) { + PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", + (LOOP_TIMES-loop+1))); + iqcal_tone_i_avg = 0; + iqcal_tone_q_avg = 0; + iqcal_image_i_avg = 0; + iqcal_image_q_avg = 0; + capture_time = 0; + + for (capture_time = 0; capture_time < 10; capture_time++) { + /* i. Set "calib_start" to 0x0 */ + reg_mode_ctrl &= ~MASK_CALIB_START; + if (!hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl))/*20060718.1 modify */ + return 0; + PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - reg_mode_ctrl &= ~MASK_IQCAL_MODE; - reg_mode_ctrl |= (MASK_CALIB_START|0x1); - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); + reg_mode_ctrl &= ~MASK_IQCAL_MODE; + reg_mode_ctrl |= (MASK_CALIB_START|0x1); + hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); + PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - // c. - hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); - PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); + /* c. */ + hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); + PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); - iqcal_tone_i = _s13_to_s32(val & 0x00001FFF); - iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); - PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", - iqcal_tone_i, iqcal_tone_q)); + iqcal_tone_i = _s13_to_s32(val & 0x00001FFF); + iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); + PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", + iqcal_tone_i, iqcal_tone_q)); - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); + hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); + PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); - PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n", - iqcal_image_i, iqcal_image_q)); - if( capture_time == 0) - { + iqcal_image_i = _s13_to_s32(val & 0x00001FFF); + iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); + PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n", + iqcal_image_i, iqcal_image_q)); + if (capture_time == 0) continue; - } - else - { - iqcal_image_i_avg=( iqcal_image_i_avg*(capture_time-1) +iqcal_image_i)/capture_time; - iqcal_image_q_avg=( iqcal_image_q_avg*(capture_time-1) +iqcal_image_q)/capture_time; - iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time; - iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time; + else { + iqcal_image_i_avg = (iqcal_image_i_avg*(capture_time-1) + iqcal_image_i)/capture_time; + iqcal_image_q_avg = (iqcal_image_q_avg*(capture_time-1) + iqcal_image_q)/capture_time; + iqcal_tone_i_avg = (iqcal_tone_i_avg*(capture_time-1) + iqcal_tone_i)/capture_time; + iqcal_tone_q_avg = (iqcal_tone_q_avg*(capture_time-1) + iqcal_tone_q)/capture_time; } } @@ -1324,24 +922,23 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre iqcal_tone_i = iqcal_tone_i_avg; iqcal_tone_q = iqcal_tone_q_avg; - // d. + /* d. */ rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i + - iqcal_tone_q * iqcal_tone_q) / 1024; + iqcal_tone_q * iqcal_tone_q) / 1024; rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) + - iqcal_tone_q * iqcal_tone_i) / 1024; + iqcal_tone_q * iqcal_tone_i) / 1024; rot_image_i_b = (iqcal_image_i * iqcal_tone_i - - iqcal_image_q * iqcal_tone_q) / 1024; + iqcal_image_q * iqcal_tone_q) / 1024; rot_image_q_b = (iqcal_image_i * iqcal_tone_q + - iqcal_image_q * iqcal_tone_i) / 1024; + iqcal_image_q * iqcal_tone_i) / 1024; PHY_DEBUG(("[CAL] ** rot_tone_i_b = %d\n", rot_tone_i_b)); PHY_DEBUG(("[CAL] ** rot_tone_q_b = %d\n", rot_tone_q_b)); PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b)); PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b)); - // f. - if (rot_tone_i_b == 0) - { + /* f. */ + if (rot_tone_i_b == 0) { PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n")); PHY_DEBUG(("[CAL] ******************************************\n")); @@ -1353,8 +950,10 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre b_2 = (rot_image_q_b * 32768) / rot_tone_i_b - phw_data->iq_rsdl_phase_tx_d2; - PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", phw_data->iq_rsdl_gain_tx_d2)); - PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", phw_data->iq_rsdl_phase_tx_d2)); + PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", + phw_data->iq_rsdl_gain_tx_d2)); + PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", + phw_data->iq_rsdl_phase_tx_d2)); PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2)); PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2)); @@ -1363,26 +962,21 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); - if (cos_2b == 0) - { + if (cos_2b == 0) { PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); PHY_DEBUG(("[CAL] ******************************************\n")); break; } - // 1280 * 32768 = 41943040 + /* 1280 * 32768 = 41943040 */ temp1 = (41943040/cos_2b)*cos_b; - //temp2 = (41943040/cos_2b)*sin_b*(-1); - if (phw_data->revision == 0x2002) // 1st-cut - { + /* temp2 = (41943040/cos_2b)*sin_b*(-1); */ + if (phw_data->revision == 0x2002)/* 1st-cut */ temp2 = (41943040/cos_2b)*sin_b*(-1); - } - else // 2nd-cut - { + else/* 2nd-cut */ temp2 = (41943040*4/cos_2b)*sin_b*(-1); - } rx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); rx_cal_flt_b[1] = _floor(temp2/(32768-a_2)); @@ -1403,23 +997,22 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2])); PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3])); - // e. + /* e. */ pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q); - pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor; + pwr_image = (iqcal_image_i*iqcal_image_i + + iqcal_image_q*iqcal_image_q)*factor; PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone)); PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image)); - if (pwr_tone > pwr_image) - { + if (pwr_tone > pwr_image) { verify_count++; PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n")); PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); PHY_DEBUG(("[CAL] ******************************************\n")); - if (verify_count > 2) - { + if (verify_count > 2) { PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n")); PHY_DEBUG(("[CAL] **************************************\n")); @@ -1428,19 +1021,16 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre continue; } - // g. + /* g. */ hw_get_dxx_reg(phw_data, 0x54, &val); PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); - if (phw_data->revision == 0x2002) // 1st-cut - { + if (phw_data->revision == 0x2002) /* 1st-cut */{ rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); - } - else // 2nd-cut - { + } else /* 2nd-cut */{ rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); @@ -1452,22 +1042,17 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2])); PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3])); - if (phw_data->revision == 0x2002) // 1st-cut - { - if (((rx_cal_reg[0]==7) || (rx_cal_reg[0]==(-8))) && - ((rx_cal_reg[3]==7) || (rx_cal_reg[3]==(-8)))) - { + if (phw_data->revision == 0x2002) /* 1st-cut */{ + if (((rx_cal_reg[0] == 7) || (rx_cal_reg[0] == (-8))) && + ((rx_cal_reg[3] == 7) || (rx_cal_reg[3] == (-8)))) { PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); PHY_DEBUG(("[CAL] **************************************\n")); break; } - } - else // 2nd-cut - { - if (((rx_cal_reg[0]==31) || (rx_cal_reg[0]==(-32))) && - ((rx_cal_reg[3]==31) || (rx_cal_reg[3]==(-32)))) - { + } else /* 2nd-cut */{ + if (((rx_cal_reg[0] == 31) || (rx_cal_reg[0] == (-32))) && + ((rx_cal_reg[3] == 31) || (rx_cal_reg[3] == (-32)))) { PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); PHY_DEBUG(("[CAL] **************************************\n")); @@ -1485,17 +1070,14 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3])); hw_get_dxx_reg(phw_data, 0x54, &val); - if (phw_data->revision == 0x2002) // 1st-cut - { + if (phw_data->revision == 0x2002) /* 1st-cut */{ val &= 0x0000FFFF; val |= ((_s32_to_s4(rx_cal[0]) << 12)| (_s32_to_s4(rx_cal[1]) << 8)| (_s32_to_s4(rx_cal[2]) << 4)| (_s32_to_s4(rx_cal[3]))); hw_set_dxx_reg(phw_data, 0x54, val); - } - else // 2nd-cut - { + } else /* 2nd-cut */{ val &= 0x000003FF; val |= ((_s32_to_s5(rx_cal[0]) << 27)| (_s32_to_s6(rx_cal[1]) << 21)| @@ -1503,8 +1085,8 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre (_s32_to_s5(rx_cal[3]) << 10)); hw_set_dxx_reg(phw_data, 0x54, val); - if( loop == 3 ) - return 0; + if (loop == 3) + return 0; } PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); @@ -1514,12 +1096,12 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre return 1; } -////////////////////////////////////////////////////////// +/*************************************************/ -////////////////////////////////////////////////////////////////////////// -void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) +/***************************************************************/ +static void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) { -// figo 20050523 marked thsi flag for can't compile for relesase +/* figo 20050523 marked this flag for can't compile for release */ #ifdef _DEBUG s32 rx_cal_reg[4]; u32 val; @@ -1528,37 +1110,34 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) u8 result; PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n")); -// a. Set RFIC to "RX calibration mode" - //; ----- Calibration (7). RX path IQ imbalance calibration loop - // 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits +/* a. Set RFIC to "RX calibration mode" */ + /* ; ----- Calibration (7). RX path IQ imbalance calibration loop */ + /* 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits */ phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2); - // 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit + /* 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuits */ phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6); - //0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized - phy_set_rf_data(phw_data, 5, (5<<24)| phw_data->txvga_setting_for_cal); - //0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized + /* 0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized */ + phy_set_rf_data(phw_data, 5, (5<<24) | phw_data->txvga_setting_for_cal); + /* 0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized */ phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C); - //0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode + /* 0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode */ phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0); - // ; [BB-chip]: Calibration (7f). Send test pattern - // ; [BB-chip]: Calibration (7g). Search RXGCL optimal value - // ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table + /* ; [BB-chip]: Calibration (7f). Send test pattern */ + /* ; [BB-chip]: Calibration (7g). Search RXGCL optimal value */ + /* ; [BB-chip]: Calibration (7h). Calculate RX-path IQ imbalance and setting RX path IQ compensation table */ result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency); - if (result > 0) - { + if (result > 0) { _reset_rx_cal(phw_data); result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency); - if (result > 0) - { + if (result > 0) { _reset_rx_cal(phw_data); result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency); - if (result > 0) - { + if (result > 0) { PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n")); PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n")); PHY_DEBUG(("[CAL] **************************************\n")); @@ -1571,15 +1150,12 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) hw_get_dxx_reg(phw_data, 0x54, &val); PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); - if (phw_data->revision == 0x2002) // 1st-cut - { + if (phw_data->revision == 0x2002) /* 1st-cut */{ rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); - } - else // 2nd-cut - { + } else /* 2nd-cut */{ rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); @@ -1594,7 +1170,7 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) } -//////////////////////////////////////////////////////////////////////// +/*******************************************************/ void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency) { u32 reg_mode_ctrl; @@ -1602,80 +1178,71 @@ void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency) PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n")); - // 20040701 1.1.25.1000 kevin - hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl); - hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl); hw_get_dxx_reg(phw_data, 0x58, &iq_alpha); - - _rxadc_dc_offset_cancellation_winbond(phw_data, frequency); - //_txidac_dc_offset_cancellation_winbond(phw_data); - //_txqdac_dc_offset_cacellation_winbond(phw_data); + /* _txidac_dc_offset_cancellation_winbond(phw_data); */ + /* _txqdac_dc_offset_cancellation_winbond(phw_data); */ _tx_iq_calibration_winbond(phw_data); _rx_iq_calibration_winbond(phw_data, frequency); - //------------------------------------------------------------------------ + /*********************************************************************/ hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl); - reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); // set when finish + reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); /* set when finish */ hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - // i. Set RFIC to "Normal mode" - hw_set_cxx_reg(phw_data, 0x80, mac_ctrl); - hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl); + /* i. Set RFIC to "Normal mode" */ hw_set_dxx_reg(phw_data, 0x58, iq_alpha); - - //------------------------------------------------------------------------ + /*********************************************************************/ phy_init_rf(phw_data); } -//=========================== -void phy_set_rf_data( struct hw_data * pHwData, u32 index, u32 value ) +/******************/ +void phy_set_rf_data(struct hw_data *pHwData, u32 index, u32 value) { - u32 ltmp=0; - - switch( pHwData->phy_type ) - { - case RF_MAXIM_2825: - case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); - break; - - case RF_MAXIM_2827: - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); - break; - - case RF_MAXIM_2828: - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); - break; - - case RF_MAXIM_2829: - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); - break; - - case RF_AIROHA_2230: - case RF_AIROHA_2230S: // 20060420 Add this - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( value, 20 ); - break; - - case RF_AIROHA_7230: - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff); - break; - - case RF_WB_242: - case RF_WB_242_1: // 20060619.5 Add - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( value, 24 ); - break; + u32 ltmp = 0; + + switch (pHwData->phy_type) { + case RF_MAXIM_2825: + case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */ + ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18); + break; + + case RF_MAXIM_2827: + ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18); + break; + + case RF_MAXIM_2828: + ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18); + break; + + case RF_MAXIM_2829: + ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18); + break; + + case RF_AIROHA_2230: + case RF_AIROHA_2230S: /* 20060420 Add this */ + ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(value, 20); + break; + + case RF_AIROHA_7230: + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff); + break; + + case RF_WB_242: + case RF_WB_242_1:/* 20060619.5 Add */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(value, 24); + break; } - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); } -// 20060717 modify as Bruce's mail +/* 20060717 modify as Bruce's mail */ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data) { int init_txvga = 0; @@ -1685,26 +1252,27 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data) s32 iqcal_tone_q0; u32 sqsum; s32 iq_mag_0_tx; - u8 reg_state; - int current_txvga; + u8 reg_state; + int current_txvga; reg_state = 0; - for( init_txvga=0; init_txvga<10; init_txvga++) - { - current_txvga = ( 0x24C40A|(init_txvga<<6) ); - phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga) ); + for (init_txvga = 0; init_txvga < 10; init_txvga++) { + current_txvga = (0x24C40A|(init_txvga<<6)); + phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga)); phw_data->txvga_setting_for_cal = current_txvga; - msleep(30); // 20060612.1.a + msleep(30);/* 20060612.1.a */ - if( !hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl) ) // 20060718.1 modify + if (!hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl))/* 20060718.1 modify */ return false; PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); - // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to - // enable "IQ alibration Mode II" + /* + * a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to + * enable "IQ alibration Mode II" + */ reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); reg_mode_ctrl &= ~MASK_IQCAL_MODE; reg_mode_ctrl |= (MASK_CALIB_START|0x02); @@ -1712,15 +1280,15 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data) hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); - udelay(1); // 20060612.1.a + udelay(1);/* 20060612.1.a */ - udelay(300); // 20060612.1.a + udelay(300);/* 20060612.1.a */ - // b. + /* b. */ hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); - udelay(300); // 20060612.1.a + udelay(300);/* 20060612.1.a */ iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF); iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13); @@ -1729,25 +1297,21 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data) sqsum = iqcal_tone_i0*iqcal_tone_i0 + iqcal_tone_q0*iqcal_tone_q0; iq_mag_0_tx = (s32) _sqrt(sqsum); - PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx)); + PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", + iq_mag_0_tx)); - if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 ) + if (iq_mag_0_tx >= 700 && iq_mag_0_tx <= 1750) break; - else if(iq_mag_0_tx > 1750) - { - init_txvga=-2; + else if (iq_mag_0_tx > 1750) { + init_txvga = -2; continue; - } - else + } else continue; } - if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 ) + if (iq_mag_0_tx >= 700 && iq_mag_0_tx <= 1750) return true; else return false; } - - - diff --git a/drivers/staging/winbond/phy_calibration.h b/drivers/staging/winbond/phy_calibration.h index 30320314883..78fc6805860 100644 --- a/drivers/staging/winbond/phy_calibration.h +++ b/drivers/staging/winbond/phy_calibration.h @@ -1,7 +1,7 @@ #ifndef __WINBOND_PHY_CALIBRATION_H #define __WINBOND_PHY_CALIBRATION_H -#include "wbhal_f.h" +#include "wbhal.h" #define REG_AGC_CTRL1 0x1000 #define REG_AGC_CTRL2 0x1004 @@ -79,6 +79,7 @@ #define SHIFT_IQCAL_TONE_Q(x) ((x) >> 13) void phy_set_rf_data(struct hw_data *pHwData, u32 index, u32 value); +void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency); #define phy_init_rf(_A) /* RFSynthesizer_initial(_A) */ #endif diff --git a/drivers/staging/winbond/reg.c b/drivers/staging/winbond/reg.c index d9a8128b21f..5fd4c4a72ee 100644 --- a/drivers/staging/winbond/reg.c +++ b/drivers/staging/winbond/reg.c @@ -1,5 +1,6 @@ -#include "sysdef.h" -#include "wbhal_f.h" +#include "wbhal.h" +#include "wb35reg_f.h" +#include "core.h" /* * ==================================================== @@ -42,7 +43,7 @@ */ /* MAX2825 (pure b/g) */ -u32 max2825_rf_data[] = { +static u32 max2825_rf_data[] = { (0x00<<18) | 0x000a2, (0x01<<18) | 0x21cc0, (0x02<<18) | 0x13806, @@ -58,7 +59,7 @@ u32 max2825_rf_data[] = { (0x0C<<18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */ }; -u32 max2825_channel_data_24[][3] = { +static u32 max2825_channel_data_24[][3] = { {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 01 */ {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 02 */ {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 03 */ @@ -75,11 +76,11 @@ u32 max2825_channel_data_24[][3] = { {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */ }; -u32 max2825_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; +static u32 max2825_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; /* ========================================== */ /* MAX2827 (a/b/g) */ -u32 max2827_rf_data[] = { +static u32 max2827_rf_data[] = { (0x00 << 18) | 0x000a2, (0x01 << 18) | 0x21cc0, (0x02 << 18) | 0x13806, @@ -95,7 +96,7 @@ u32 max2827_rf_data[] = { (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */ }; -u32 max2827_channel_data_24[][3] = { +static u32 max2827_channel_data_24[][3] = { {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */ {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */ {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */ @@ -112,7 +113,7 @@ u32 max2827_channel_data_24[][3] = { {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */ }; -u32 max2827_channel_data_50[][3] = { +static u32 max2827_channel_data_50[][3] = { {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 36 */ {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 40 */ {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6}, /* channel 44 */ @@ -123,12 +124,12 @@ u32 max2827_channel_data_50[][3] = { {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6} /* channel 64 */ }; -u32 max2827_power_data_24[] = {(0x0C << 18) | 0x0C000, (0x0C << 18) | 0x0D600, (0x0C << 18) | 0x0C100}; -u32 max2827_power_data_50[] = {(0x0C << 18) | 0x0C400, (0x0C << 18) | 0x0D500, (0x0C << 18) | 0x0C300}; +static u32 max2827_power_data_24[] = {(0x0C << 18) | 0x0C000, (0x0C << 18) | 0x0D600, (0x0C << 18) | 0x0C100}; +static u32 max2827_power_data_50[] = {(0x0C << 18) | 0x0C400, (0x0C << 18) | 0x0D500, (0x0C << 18) | 0x0C300}; /* ======================================================= */ /* MAX2828 (a/b/g) */ -u32 max2828_rf_data[] = { +static u32 max2828_rf_data[] = { (0x00 << 18) | 0x000a2, (0x01 << 18) | 0x21cc0, (0x02 << 18) | 0x13806, @@ -144,7 +145,7 @@ u32 max2828_rf_data[] = { (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */ }; -u32 max2828_channel_data_24[][3] = { +static u32 max2828_channel_data_24[][3] = { {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */ {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */ {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */ @@ -161,7 +162,7 @@ u32 max2828_channel_data_24[][3] = { {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */ }; -u32 max2828_channel_data_50[][3] = { +static u32 max2828_channel_data_50[][3] = { {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 36 */ {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 40 */ {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 44 */ @@ -172,12 +173,12 @@ u32 max2828_channel_data_50[][3] = { {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6} /* channel 64 */ }; -u32 max2828_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; -u32 max2828_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; +static u32 max2828_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; +static u32 max2828_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; /* ========================================================== */ /* MAX2829 (a/b/g) */ -u32 max2829_rf_data[] = { +static u32 max2829_rf_data[] = { (0x00 << 18) | 0x000a2, (0x01 << 18) | 0x23520, (0x02 << 18) | 0x13802, @@ -193,7 +194,7 @@ u32 max2829_rf_data[] = { (0x0C << 18) | 0x0F300 /* TXVGA=51, (MAX-6 dB) */ }; -u32 max2829_channel_data_24[][3] = { +static u32 max2829_channel_data_24[][3] = { {(3 << 18) | 0x30142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 01 (2412MHz) */ {(3 << 18) | 0x32141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 02 (2417MHz) */ {(3 << 18) | 0x32143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 03 (2422MHz) */ @@ -210,7 +211,7 @@ u32 max2829_channel_data_24[][3] = { {(3 << 18) | 0x32941, (4 << 18) | 0x09999, (5 << 18) | 0x289C6}, /* 14 (2484MHz) */ }; -u32 max2829_channel_data_50[][4] = { +static u32 max2829_channel_data_50[][4] = { {36, (3 << 18) | 0x33cc3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 36 (5.180GHz) */ {40, (3 << 18) | 0x302c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 40 (5.200GHz) */ {44, (3 << 18) | 0x302c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 44 (5.220GHz) */ @@ -295,51 +296,6 @@ u32 max2829_channel_data_50[][4] = { * 0x0c 0x0c000 * ==================================================================== */ -u32 maxim_317_rf_data[] = { - (0x00 << 18) | 0x000a2, - (0x01 << 18) | 0x214c0, - (0x02 << 18) | 0x13802, - (0x03 << 18) | 0x30143, - (0x04 << 18) | 0x0accc, - (0x05 << 18) | 0x28986, - (0x06 << 18) | 0x18008, - (0x07 << 18) | 0x38400, - (0x08 << 18) | 0x05108, - (0x09 << 18) | 0x27ff8, - (0x0A << 18) | 0x14000, - (0x0B << 18) | 0x37f99, - (0x0C << 18) | 0x0c000 -}; - -u32 maxim_317_channel_data_24[][3] = { - {(0x03 << 18) | 0x30143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 01 */ - {(0x03 << 18) | 0x32140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 02 */ - {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 03 */ - {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 04 */ - {(0x03 << 18) | 0x31140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 05 */ - {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 06 */ - {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 07 */ - {(0x03 << 18) | 0x33140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 08 */ - {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 09 */ - {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 10 */ - {(0x03 << 18) | 0x30940, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 11 */ - {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 12 */ - {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986} /* channe1 13 */ -}; - -u32 maxim_317_channel_data_50[][3] = { - {(0x03 << 18) | 0x33cc0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a986}, /* channel 36 */ - {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a986}, /* channel 40 */ - {(0x03 << 18) | 0x302c3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a986}, /* channel 44 */ - {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09666, (0x05 << 18) | 0x2a986}, /* channel 48 */ - {(0x03 << 18) | 0x312c2, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2a986}, /* channel 52 */ - {(0x03 << 18) | 0x332c0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a99e}, /* channel 56 */ - {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a99e}, /* channel 60 */ - {(0x03 << 18) | 0x30ac3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a99e} /* channel 64 */ -}; - -u32 maxim_317_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; -u32 maxim_317_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; /* * =================================================================== @@ -387,7 +343,7 @@ u32 maxim_317_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100} * 0x0f 0xf00a0 ; Restore Initial Setting * ================================================================== */ -u32 al2230_rf_data[] = { +static u32 al2230_rf_data[] = { (0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCC, (0x02 << 20) | 0x40058, @@ -405,7 +361,7 @@ u32 al2230_rf_data[] = { (0x0F << 20) | 0xF01A0 }; -u32 al2230s_rf_data[] = { +static u32 al2230s_rf_data[] = { (0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCC, (0x02 << 20) | 0x40058, @@ -423,7 +379,7 @@ u32 al2230s_rf_data[] = { (0x0F << 20) | 0xF01A0 }; -u32 al2230_channel_data_24[][2] = { +static u32 al2230_channel_data_24[][2] = { {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 01 */ {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 02 */ {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 03 */ @@ -445,7 +401,7 @@ u32 al2230_channel_data_24[][2] = { #define AIROHA_TXVGA_MIDDLE_INDEX 12 /* Index for 0x96602 */ #define AIROHA_TXVGA_HIGH_INDEX 8 /* Index for 0x97602 1.0.24.0 1.0.28.0 */ -u32 al2230_txvga_data[][2] = { +static u32 al2230_txvga_data[][2] = { /* value , index */ {0x090202, 0}, {0x094202, 2}, @@ -496,7 +452,7 @@ u32 al2230_txvga_data[][2] = { */ /* channel independent registers: */ -u32 al7230_rf_data_24[] = { +static u32 al7230_rf_data_24[] = { (0x00 << 24) | 0x003790, (0x01 << 24) | 0x133331, (0x02 << 24) | 0x841FF2, @@ -515,7 +471,7 @@ u32 al7230_rf_data_24[] = { (0x0F << 24) | 0x1ABA8F }; -u32 al7230_channel_data_24[][2] = { +static u32 al7230_channel_data_24[][2] = { {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x133331}, /* channe1 01 */ {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x1B3331}, /* channe1 02 */ {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x033331}, /* channe1 03 */ @@ -533,7 +489,7 @@ u32 al7230_channel_data_24[][2] = { }; /* channel independent registers: */ -u32 al7230_rf_data_50[] = { +static u32 al7230_rf_data_50[] = { (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x000001, (0x02 << 24) | 0x451FE2, @@ -552,7 +508,7 @@ u32 al7230_rf_data_50[] = { (0x0F << 24) | 0x12BACF /* 5Ghz default state */ }; -u32 al7230_channel_data_5[][4] = { +static u32 al7230_channel_data_5[][4] = { /* channel dependent registers: 0x00, 0x01 and 0x04 */ /* 11J =========== */ {184, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 184 */ @@ -602,7 +558,7 @@ u32 al7230_channel_data_5[][4] = { */ /* TXVGA Mapping Table <=== Register 0x0B */ -u32 al7230_txvga_data[][2] = { +static u32 al7230_txvga_data[][2] = { {0x08040B, 0}, /* TXVGA = 0; */ {0x08041B, 1}, /* TXVGA = 1; */ {0x08042B, 2}, /* TXVGA = 2; */ @@ -674,7 +630,7 @@ u32 al7230_txvga_data[][2] = { * W89RF242 RFIC SPI programming initial data * Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b */ -u32 w89rf242_rf_data[] = { +static u32 w89rf242_rf_data[] = { (0x00 << 24) | 0xF86100, /* 3E184; MODA (0x00) -- Normal mode ; calibration off */ (0x01 << 24) | 0xEFFFC2, /* 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on */ (0x02 << 24) | 0x102504, /* 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA */ @@ -692,10 +648,10 @@ u32 w89rf242_rf_data[] = { (0x0E << 24) | 0x5557DC, /* 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F */ (0x10 << 24) | 0x000C20, /* 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB */ (0x11 << 24) | 0x0C0022, /* 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C) */ - (0x12 << 24) | 0x000024 /* TMODC (0x12) -- Turn OFF Tempearure sensor */ + (0x12 << 24) | 0x000024 /* TMODC (0x12) -- Turn OFF Temperature sensor */ }; -u32 w89rf242_channel_data_24[][2] = { +static u32 w89rf242_channel_data_24[][2] = { {(0x03 << 24) | 0x025B06, (0x04 << 24) | 0x080408}, /* channe1 01 */ {(0x03 << 24) | 0x025C46, (0x04 << 24) | 0x080408}, /* channe1 02 */ {(0x03 << 24) | 0x025D86, (0x04 << 24) | 0x080408}, /* channe1 03 */ @@ -712,9 +668,7 @@ u32 w89rf242_channel_data_24[][2] = { {(0x03 << 24) | 0x026D06, (0x04 << 24) | 0x080408} /* channe1 14 */ }; -u32 w89rf242_power_data_24[] = {(0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A}; - -u32 w89rf242_txvga_old_mapping[][2] = { +static u32 w89rf242_txvga_old_mapping[][2] = { {0, 0} , /* New <-> Old */ {1, 1} , {2, 2} , @@ -737,7 +691,7 @@ u32 w89rf242_txvga_old_mapping[][2] = { {34, 19}, }; -u32 w89rf242_txvga_data[][5] = { +static u32 w89rf242_txvga_data[][5] = { /* low gain mode */ {(0x05 << 24) | 0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131}, /* min gain */ {(0x05 << 24) | 0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131}, @@ -919,20 +873,20 @@ void Uxx_power_on_procedure(struct hw_data *pHwData) Wb35Reg_WriteSync(pHwData, 0x03f8, 0x7ff); } -void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp , char number) +static void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp, + char number) { u8 i; - for (i = 0; i < number; i++) { pHwData->phy_para[i] = al7230_rf_data_24[i]; pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i] & 0xffffff); } } -void Set_ChanIndep_RfData_al7230_50(struct hw_data *pHwData, u32 *pltmp, char number) +static void Set_ChanIndep_RfData_al7230_50(struct hw_data *pHwData, u32 *pltmp, + char number) { u8 i; - for (i = 0; i < number; i++) { pHwData->phy_para[i] = al7230_rf_data_50[i]; pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i] & 0xffffff); @@ -966,42 +920,42 @@ void RFSynthesizer_initial(struct hw_data *pHwData) switch (pHwData->phy_type) { case RF_MAXIM_2825: case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */ - number = sizeof(max2825_rf_data) / sizeof(max2825_rf_data[0]); + number = ARRAY_SIZE(max2825_rf_data); for (i = 0; i < number; i++) { pHwData->phy_para[i] = max2825_rf_data[i]; /* Backup Rf parameter */ pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_rf_data[i], 18); } break; case RF_MAXIM_2827: - number = sizeof(max2827_rf_data) / sizeof(max2827_rf_data[0]); + number = ARRAY_SIZE(max2827_rf_data); for (i = 0; i < number; i++) { pHwData->phy_para[i] = max2827_rf_data[i]; pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_rf_data[i], 18); } break; case RF_MAXIM_2828: - number = sizeof(max2828_rf_data) / sizeof(max2828_rf_data[0]); + number = ARRAY_SIZE(max2828_rf_data); for (i = 0; i < number; i++) { pHwData->phy_para[i] = max2828_rf_data[i]; pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_rf_data[i], 18); } break; case RF_MAXIM_2829: - number = sizeof(max2829_rf_data) / sizeof(max2829_rf_data[0]); + number = ARRAY_SIZE(max2829_rf_data); for (i = 0; i < number; i++) { pHwData->phy_para[i] = max2829_rf_data[i]; pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_rf_data[i], 18); } break; case RF_AIROHA_2230: - number = sizeof(al2230_rf_data) / sizeof(al2230_rf_data[0]); + number = ARRAY_SIZE(al2230_rf_data); for (i = 0; i < number; i++) { pHwData->phy_para[i] = al2230_rf_data[i]; pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data[i], 20); } break; case RF_AIROHA_2230S: - number = sizeof(al2230s_rf_data) / sizeof(al2230s_rf_data[0]); + number = ARRAY_SIZE(al2230s_rf_data); for (i = 0; i < number; i++) { pHwData->phy_para[i] = al2230s_rf_data[i]; pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230s_rf_data[i], 20); @@ -1010,15 +964,13 @@ void RFSynthesizer_initial(struct hw_data *pHwData) case RF_AIROHA_7230: /* Start to fill RF parameters, PLL_ON should be pulled low. */ Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000); - #ifdef _PE_STATE_DUMP_ - printk("* PLL_ON low\n"); - #endif - number = sizeof(al7230_rf_data_24) / sizeof(al7230_rf_data_24[0]); + pr_debug("* PLL_ON low\n"); + number = ARRAY_SIZE(al7230_rf_data_24); Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); break; case RF_WB_242: case RF_WB_242_1: - number = sizeof(w89rf242_rf_data) / sizeof(w89rf242_rf_data[0]); + number = ARRAY_SIZE(w89rf242_rf_data); for (i = 0; i < number; i++) { ltmp = w89rf242_rf_data[i]; if (i == 4) { /* Update the VCO trim from EEPROM */ @@ -1089,7 +1041,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData) msleep(5); ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01A0, 20); - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp) ; + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C); pHwData->reg.BB50 &= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */ @@ -1098,9 +1050,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData) case RF_AIROHA_7230: /* RF parameters have filled completely, PLL_ON should be pulled high */ Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080); - #ifdef _PE_STATE_DUMP_ - printk("* PLL_ON high\n"); - #endif + pr_debug("* PLL_ON high\n"); /* 2.4GHz */ ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; @@ -1115,11 +1065,9 @@ void RFSynthesizer_initial(struct hw_data *pHwData) /* 5GHz */ Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000); - #ifdef _PE_STATE_DUMP_ - printk("* PLL_ON low\n"); - #endif + pr_debug("* PLL_ON low\n"); - number = sizeof(al7230_rf_data_50) / sizeof(al7230_rf_data_50[0]); + number = ARRAY_SIZE(al7230_rf_data_50); Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); /* Write to register. number must less and equal than 16 */ for (i = 0; i < number; i++) @@ -1127,9 +1075,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData) msleep(5); Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080); - #ifdef _PE_STATE_DUMP_ - printk("* PLL_ON high\n"); - #endif + pr_debug("* PLL_ON high\n"); ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); @@ -1270,7 +1216,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData) } } -void BBProcessor_AL7230_2400(struct hw_data *pHwData) +static void BBProcessor_AL7230_2400(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; u32 pltmp[12]; @@ -1311,7 +1257,7 @@ void BBProcessor_AL7230_2400(struct hw_data *pHwData) Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); } -void BBProcessor_AL7230_5000(struct hw_data *pHwData) +static void BBProcessor_AL7230_5000(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; u32 pltmp[12]; @@ -1627,22 +1573,24 @@ void BBProcessor_initial(struct hw_data *pHwData) reg->SQ3_filter[i] = 0x2f; /* half of Bit 0 ~ 6 */ } -void set_tx_power_per_channel_max2829(struct hw_data *pHwData, struct chan_info Channel) +static inline void set_tx_power_per_channel_max2829(struct hw_data *pHwData, + struct chan_info Channel) { RFSynthesizer_SetPowerIndex(pHwData, 100); } -void set_tx_power_per_channel_al2230(struct hw_data *pHwData, struct chan_info Channel) +static void set_tx_power_per_channel_al2230(struct hw_data *pHwData, + struct chan_info Channel) { u8 index = 100; - if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; RFSynthesizer_SetPowerIndex(pHwData, index); } -void set_tx_power_per_channel_al7230(struct hw_data *pHwData, struct chan_info Channel) +static void set_tx_power_per_channel_al7230(struct hw_data *pHwData, + struct chan_info Channel) { u8 i, index = 100; @@ -1665,7 +1613,8 @@ void set_tx_power_per_channel_al7230(struct hw_data *pHwData, struct chan_info RFSynthesizer_SetPowerIndex(pHwData, index); } -void set_tx_power_per_channel_wb242(struct hw_data *pHwData, struct chan_info Channel) +static void set_tx_power_per_channel_wb242(struct hw_data *pHwData, + struct chan_info Channel) { u8 index = 100; @@ -1747,7 +1696,7 @@ void RFSynthesizer_SwitchingChannel(struct hw_data *pHwData, struct chan_info C pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_24[Channel.ChanNo-1][i], 18); Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); } else if (Channel.band == BAND_TYPE_OFDM_5) { - count = sizeof(max2829_channel_data_50) / sizeof(max2829_channel_data_50[0]); + count = ARRAY_SIZE(max2829_channel_data_50); for (i = 0; i < count; i++) { if (max2829_channel_data_50[i][0] == Channel.ChanNo) { @@ -1783,21 +1732,19 @@ void RFSynthesizer_SwitchingChannel(struct hw_data *pHwData, struct chan_info C /* Update BB register */ BBProcessor_AL7230_2400(pHwData); - number = sizeof(al7230_rf_data_24) / sizeof(al7230_rf_data_24[0]); + number = ARRAY_SIZE(al7230_rf_data_24); Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); } else { /* Update BB register */ BBProcessor_AL7230_5000(pHwData); - number = sizeof(al7230_rf_data_50) / sizeof(al7230_rf_data_50[0]); + number = ARRAY_SIZE(al7230_rf_data_50); Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); } /* Write to register. number must less and equal than 16 */ Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, number, NO_INCREMENT); - #ifdef _PE_STATE_DUMP_ - printk("Band changed\n"); - #endif + pr_debug("Band changed\n"); } if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */ @@ -1814,7 +1761,7 @@ void RFSynthesizer_SwitchingChannel(struct hw_data *pHwData, struct chan_info C Wb35Reg_Write(pHwData, 0x0864, ltmp); } - count = sizeof(al7230_channel_data_5) / sizeof(al7230_channel_data_5[0]); + count = ARRAY_SIZE(al7230_channel_data_5); for (i = 0; i < count; i++) { if (al7230_channel_data_5[i][0] == Channel.ChanNo) { @@ -1978,7 +1925,7 @@ u8 RFSynthesizer_SetAiroha2230Power(struct hw_data *pHwData, u8 index) u32 PowerData; u8 i, count; - count = sizeof(al2230_txvga_data) / sizeof(al2230_txvga_data[0]); + count = ARRAY_SIZE(al2230_txvga_data); for (i = 0; i < count; i++) { if (al2230_txvga_data[i][1] >= index) break; @@ -1996,7 +1943,7 @@ u8 RFSynthesizer_SetAiroha7230Power(struct hw_data *pHwData, u8 index) u32 PowerData; u8 i, count; - count = sizeof(al7230_txvga_data) / sizeof(al7230_txvga_data[0]); + count = ARRAY_SIZE(al7230_txvga_data); for (i = 0; i < count; i++) { if (al7230_txvga_data[i][1] >= index) break; @@ -2013,7 +1960,7 @@ u8 RFSynthesizer_SetWinbond242Power(struct hw_data *pHwData, u8 index) u32 PowerData; u8 i, count; - count = sizeof(w89rf242_txvga_data) / sizeof(w89rf242_txvga_data[0]); + count = ARRAY_SIZE(w89rf242_txvga_data); for (i = 0; i < count; i++) { if (w89rf242_txvga_data[i][1] >= index) break; @@ -2073,11 +2020,7 @@ void Mxx_initial(struct hw_data *pHwData) */ /* M00 bit set */ - #ifdef _IBSS_BEACON_SEQ_STICK_ - reg->M00_MacControl = 0; /* Solve beacon sequence number stop by software */ - #else reg->M00_MacControl = 0x80000000; /* Solve beacon sequence number stop by hardware */ - #endif /* M24 disable enter power save, BB RxOn and enable NAV attack */ reg->M24_MacControl = 0x08040042; @@ -2106,7 +2049,7 @@ void Mxx_initial(struct hw_data *pHwData) pltmp[5] = reg->M38_MacControl; /* M3C */ - tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ; + tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST; reg->M3C_MacControl = tmp; pltmp[6] = tmp; @@ -2184,14 +2127,14 @@ void GetTxVgaFromEEPROM(struct hw_data *pHwData) /* Adjust WB_242 to WB_242_1 TxVga scale */ if (pHwData->phy_type == RF_WB_242) { for (i = 0; i < 4; i++) { /* Only 2412 2437 2462 2484 case must be modified */ - for (j = 0; j < (sizeof(w89rf242_txvga_old_mapping) / sizeof(w89rf242_txvga_old_mapping[0])); j++) { + for (j = 0; j < ARRAY_SIZE(w89rf242_txvga_old_mapping); j++) { if (pctmp[i] < (u8) w89rf242_txvga_old_mapping[j][1]) { pctmp[i] = (u8) w89rf242_txvga_old_mapping[j][0]; break; } } - if (j == (sizeof(w89rf242_txvga_old_mapping) / sizeof(w89rf242_txvga_old_mapping[0]))) + if (j == ARRAY_SIZE(w89rf242_txvga_old_mapping)) pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0]; } } @@ -2336,13 +2279,6 @@ void EEPROMTxVgaAdjust(struct hw_data *pHwData) pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp * 2 / 4; pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp * 3 / 4; } - - #ifdef _PE_STATE_DUMP_ - printk(" TxVgaFor24 :\n"); - DataDmp((u8 *)pHwData->TxVgaFor24, 14 , 0); - printk(" TxVgaFor50 :\n"); - DataDmp((u8 *)pHwData->TxVgaFor50, 70 , 0); - #endif } void BBProcessor_RateChanging(struct hw_data *pHwData, u8 rate) diff --git a/drivers/staging/winbond/scan_s.h b/drivers/staging/winbond/scan_s.h deleted file mode 100644 index 85e7523196d..00000000000 --- a/drivers/staging/winbond/scan_s.h +++ /dev/null @@ -1,110 +0,0 @@ -#ifndef __WINBOND_SCAN_S_H -#define __WINBOND_SCAN_S_H - -#include <linux/types.h> -#include "localpara.h" - -/* - * SCAN task global CONSTANTS, STRUCTURES, variables - */ - -/* define the msg type of SCAN module */ -#define SCANMSG_SCAN_REQ 0x01 -#define SCANMSG_BEACON 0x02 -#define SCANMSG_PROBE_RESPONSE 0x03 -#define SCANMSG_TIMEOUT 0x04 -#define SCANMSG_TXPROBE_FAIL 0x05 -#define SCANMSG_ENABLE_BGSCAN 0x06 -#define SCANMSG_STOP_SCAN 0x07 - -/* - * BSS Type =>conform to - * IBSS : ToDS/FromDS = 00 - * Infrastructure : ToDS/FromDS = 01 - */ -#define IBSS_NET 0 -#define ESS_NET 1 -#define ANYBSS_NET 2 - -/* Scan Type */ -#define ACTIVE_SCAN 0 -#define PASSIVE_SCAN 1 - -/* Global data structures, Initial Scan & Background Scan */ -typedef struct _SCAN_REQ_PARA { /* mandatory parameters for SCAN request */ - - u32 ScanType; /* passive/active scan */ - - u8 reserved_1[2]; - - struct SSID_Element sSSID; /* 34B. scan only for this SSID */ - u8 reserved_2[2]; - -} SCAN_REQ_PARA, *psSCAN_REQ_PARA; - -typedef struct _SCAN_PARAMETERS { - u16 wState; - u16 iCurrentChannelIndex; - - SCAN_REQ_PARA sScanReq; - - u8 BSSID[MAC_ADDR_LENGTH + 2]; /* scan only for this BSSID */ - - u32 BssType; /* scan only for this BSS type */ - - u16 ProbeDelay; - u16 MinChannelTime; - - u16 MaxChannelTime; - u16 reserved_1; - - s32 iBgScanPeriod; /* XP: 5 sec */ - - u8 boBgScan; /* Wb: enable BG scan, For XP, this value must be FALSE */ - u8 boFastScan; /* Wb: reserved */ - u8 boCCAbusy; /* Wb: HWMAC CCA busy status */ - u8 reserved_2; - - struct timer_list timer; - - u32 ScanTimeStamp; /* Increase 1 per background scan(1 minute) */ - u32 BssTimeStamp; /* Increase 1 per connect status check */ - u32 RxNumPerAntenna[2]; - - u8 AntennaToggle; - u8 boInTimerHandler; - u8 boTimerActive; /* Wb: reserved */ - u8 boSave; - - u32 BScanEnable; /* Background scan enable. Default is On */ -} SCAN_PARAMETERS, *psSCAN_PARAMETERS; - -/* Encapsulate 'adapter' data structure */ -#define psSCAN (&(adapter->sScanPara)) -#define psSCANREQ (&(adapter->sScanPara.sScanReq)) - -/* - * =========================================================== - * scan.h - * Define the related definitions of scan module - * - * =========================================================== - */ - -/* Define the state of scan module */ -#define SCAN_INACTIVE 0 -#define WAIT_PROBE_DELAY 1 -#define WAIT_RESPONSE_MIN 2 -#define WAIT_RESPONSE_MAX_ACTIVE 3 -#define WAIT_BEACON_MAX_PASSIVE 4 -#define SCAN_COMPLETE 5 -#define BG_SCAN 6 -#define BG_SCANNING 7 - - -/* - * The value will load from EEPROM - * If 0xff is set in EEPOM, the driver will use SCAN_MAX_CHNL_TIME instead. - * The definition is in WbHal.h - */ -#endif diff --git a/drivers/staging/winbond/sme_api.h b/drivers/staging/winbond/sme_api.h index 8f4596c9e9b..652ae7085a5 100644 --- a/drivers/staging/winbond/sme_api.h +++ b/drivers/staging/winbond/sme_api.h @@ -12,7 +12,6 @@ #include "localpara.h" /****************** CONSTANT AND MACRO SECTION ******************************/ -#define _INLINE __inline #define MEDIA_STATE_DISCONNECTED 0 #define MEDIA_STATE_CONNECTED 1 @@ -26,17 +25,17 @@ /* OID_802_11_BSSID */ s8 sme_get_bssid(void *pcore_data, u8 *pbssid); -s8 sme_get_desired_bssid(void *pcore_data, u8 *pbssid); /* Not use */ +s8 sme_get_desired_bssid(void *pcore_data, u8 *pbssid); /* Unused */ s8 sme_set_desired_bssid(void *pcore_data, u8 *pbssid); /* OID_802_11_SSID */ s8 sme_get_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len); -s8 sme_get_desired_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);/* Not use */ +s8 sme_get_desired_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);/* Unused */ s8 sme_set_desired_ssid(void *pcore_data, u8 *pssid, u8 ssid_len); /* OID_802_11_INFRASTRUCTURE_MODE */ s8 sme_get_bss_type(void *pcore_data, u8 *pbss_type); -s8 sme_get_desired_bss_type(void *pcore_data, u8 *pbss_type); /* Not use */ +s8 sme_get_desired_bss_type(void *pcore_data, u8 *pbss_type); /* Unused */ s8 sme_set_desired_bss_type(void *pcore_data, u8 bss_type); /* OID_802_11_FRAGMENTATION_THRESHOLD */ @@ -107,7 +106,7 @@ s8 sme_set_bssid_list_scan(void *pcore_data, void *pscan_para); s8 sme_set_reload_defaults(void *pcore_data, u8 reload_type); -/*------------------------- none-standard ----------------------------------*/ +/*------------------------- non-standard ----------------------------------*/ s8 sme_get_connect_status(void *pcore_data, u8 *pstatus); /*--------------------------------------------------------------------------*/ @@ -138,7 +137,7 @@ s8 sme_set_txrate_policy(void *pcore_data, u8 policy); s8 sme_get_txrate_policy(void *pcore_data, u8 *policy); s8 sme_get_cwmin_value(void *pcore_data, u8 *cwmin); s8 sme_get_cwmax_value(void *pcore_data, u16 *cwmax); -s8 sme_get_ms_radio_mode(void *pcore_data, u8 * pMsRadioOff); +s8 sme_get_ms_radio_mode(void *pcore_data, u8 *pMsRadioOff); s8 sme_set_ms_radio_mode(void *pcore_data, u8 boMsRadioOff); void sme_get_tx_power_level(void *pcore_data, u32 *TxPower); diff --git a/drivers/staging/winbond/sysdef.h b/drivers/staging/winbond/sysdef.h deleted file mode 100644 index 9195adf98e1..00000000000 --- a/drivers/staging/winbond/sysdef.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Winbond WLAN System Configuration defines */ - -#ifndef SYS_DEF_H -#define SYS_DEF_H -#define WB_LINUX -#define WB_LINUX_WPA_PSK - -#define _USE_FALLBACK_RATE_ - -#define _WPA2_ - -#ifndef _WPA_PSK_DEBUG -#undef _WPA_PSK_DEBUG -#endif - -/* debug print options, mark what debug you don't need */ - -#ifdef FULL_DEBUG -#define _PE_STATE_DUMP_ -#define _PE_TX_DUMP_ -#define _PE_RX_DUMP_ -#define _PE_OID_DUMP_ -#define _PE_DTO_DUMP_ -#define _PE_REG_DUMP_ -#define _PE_USB_INI_DUMP_ -#endif - -#endif diff --git a/drivers/staging/winbond/wb35reg.c b/drivers/staging/winbond/wb35reg.c index 770722385ee..bbc5ddcce6f 100644 --- a/drivers/staging/winbond/wb35reg.c +++ b/drivers/staging/winbond/wb35reg.c @@ -1,11 +1,9 @@ -#include "sysdef.h" #include "wb35reg_f.h" +#include "phy_calibration.h" #include <linux/usb.h> #include <linux/slab.h> -extern void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency); - /* * true : read command process successfully * false : register not support @@ -15,7 +13,8 @@ extern void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency); * Flag : AUTO_INCREMENT - RegisterNo will auto increment 4 * NO_INCREMENT - Function will write data into the same register */ -unsigned char Wb35Reg_BurstWrite(struct hw_data *pHwData, u16 RegisterNo, u32 *pRegisterData, u8 NumberOfData, u8 Flag) +unsigned char Wb35Reg_BurstWrite(struct hw_data *pHwData, u16 RegisterNo, + u32 *pRegisterData, u8 NumberOfData, u8 Flag) { struct wb35_reg *reg = &pHwData->reg; struct urb *urb = NULL; @@ -31,88 +30,157 @@ unsigned char Wb35Reg_BurstWrite(struct hw_data *pHwData, u16 RegisterNo, u32 *p /* Trying to use burst write function if use new hardware */ UrbSize = sizeof(struct wb35_reg_queue) + DataSize + sizeof(struct usb_ctrlrequest); reg_queue = kzalloc(UrbSize, GFP_ATOMIC); + if (reg_queue == NULL) + return false; + urb = usb_alloc_urb(0, GFP_ATOMIC); - if (urb && reg_queue) { - reg_queue->DIRECT = 2; /* burst write register */ - reg_queue->INDEX = RegisterNo; - reg_queue->pBuffer = (u32 *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); - memcpy(reg_queue->pBuffer, pRegisterData, DataSize); - /* the function for reversing register data from little endian to big endian */ - for (i = 0; i < NumberOfData ; i++) - reg_queue->pBuffer[i] = cpu_to_le32(reg_queue->pBuffer[i]); - - dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue) + DataSize); - dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; - dr->bRequest = 0x04; /* USB or vendor-defined request code, burst mode */ - dr->wValue = cpu_to_le16(Flag); /* 0: Register number auto-increment, 1: No auto increment */ - dr->wIndex = cpu_to_le16(RegisterNo); - dr->wLength = cpu_to_le16(DataSize); - reg_queue->Next = NULL; - reg_queue->pUsbReq = dr; - reg_queue->urb = urb; + if (urb == NULL) { + kfree(reg_queue); + return false; + } - spin_lock_irq(®->EP0VM_spin_lock); - if (reg->reg_first == NULL) - reg->reg_first = reg_queue; - else - reg->reg_last->Next = reg_queue; - reg->reg_last = reg_queue; + reg_queue->DIRECT = 2; /* burst write register */ + reg_queue->INDEX = RegisterNo; + reg_queue->pBuffer = (u32 *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); + memcpy(reg_queue->pBuffer, pRegisterData, DataSize); + /* the function for reversing register data from little endian to big endian */ + for (i = 0; i < NumberOfData; i++) + reg_queue->pBuffer[i] = cpu_to_le32(reg_queue->pBuffer[i]); + + dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue) + DataSize); + dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; + dr->bRequest = 0x04; /* USB or vendor-defined request code, burst mode */ + dr->wValue = cpu_to_le16(Flag); /* 0: Register number auto-increment, 1: No auto increment */ + dr->wIndex = cpu_to_le16(RegisterNo); + dr->wLength = cpu_to_le16(DataSize); + reg_queue->Next = NULL; + reg_queue->pUsbReq = dr; + reg_queue->urb = urb; - spin_unlock_irq(®->EP0VM_spin_lock); + spin_lock_irq(®->EP0VM_spin_lock); + if (reg->reg_first == NULL) + reg->reg_first = reg_queue; + else + reg->reg_last->Next = reg_queue; + reg->reg_last = reg_queue; - /* Start EP0VM */ - Wb35Reg_EP0VM_start(pHwData); + spin_unlock_irq(®->EP0VM_spin_lock); - return true; - } else { - if (urb) - usb_free_urb(urb); - if (reg_queue) - kfree(reg_queue); - return false; - } - return false; + /* Start EP0VM */ + Wb35Reg_EP0VM_start(pHwData); + + return true; } -void Wb35Reg_Update(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue) +void Wb35Reg_Update(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue) { struct wb35_reg *reg = &pHwData->reg; switch (RegisterNo) { - case 0x3b0: reg->U1B0 = RegisterValue; break; - case 0x3bc: reg->U1BC_LEDConfigure = RegisterValue; break; - case 0x400: reg->D00_DmaControl = RegisterValue; break; - case 0x800: reg->M00_MacControl = RegisterValue; break; - case 0x804: reg->M04_MulticastAddress1 = RegisterValue; break; - case 0x808: reg->M08_MulticastAddress2 = RegisterValue; break; - case 0x824: reg->M24_MacControl = RegisterValue; break; - case 0x828: reg->M28_MacControl = RegisterValue; break; - case 0x82c: reg->M2C_MacControl = RegisterValue; break; - case 0x838: reg->M38_MacControl = RegisterValue; break; - case 0x840: reg->M40_MacControl = RegisterValue; break; - case 0x844: reg->M44_MacControl = RegisterValue; break; - case 0x848: reg->M48_MacControl = RegisterValue; break; - case 0x84c: reg->M4C_MacStatus = RegisterValue; break; - case 0x860: reg->M60_MacControl = RegisterValue; break; - case 0x868: reg->M68_MacControl = RegisterValue; break; - case 0x870: reg->M70_MacControl = RegisterValue; break; - case 0x874: reg->M74_MacControl = RegisterValue; break; - case 0x878: reg->M78_ERPInformation = RegisterValue; break; - case 0x87C: reg->M7C_MacControl = RegisterValue; break; - case 0x880: reg->M80_MacControl = RegisterValue; break; - case 0x884: reg->M84_MacControl = RegisterValue; break; - case 0x888: reg->M88_MacControl = RegisterValue; break; - case 0x898: reg->M98_MacControl = RegisterValue; break; - case 0x100c: reg->BB0C = RegisterValue; break; - case 0x102c: reg->BB2C = RegisterValue; break; - case 0x1030: reg->BB30 = RegisterValue; break; - case 0x103c: reg->BB3C = RegisterValue; break; - case 0x1048: reg->BB48 = RegisterValue; break; - case 0x104c: reg->BB4C = RegisterValue; break; - case 0x1050: reg->BB50 = RegisterValue; break; - case 0x1054: reg->BB54 = RegisterValue; break; - case 0x1058: reg->BB58 = RegisterValue; break; - case 0x105c: reg->BB5C = RegisterValue; break; - case 0x1060: reg->BB60 = RegisterValue; break; + case 0x3b0: + reg->U1B0 = RegisterValue; + break; + case 0x3bc: + reg->U1BC_LEDConfigure = RegisterValue; + break; + case 0x400: + reg->D00_DmaControl = RegisterValue; + break; + case 0x800: + reg->M00_MacControl = RegisterValue; + break; + case 0x804: + reg->M04_MulticastAddress1 = RegisterValue; + break; + case 0x808: + reg->M08_MulticastAddress2 = RegisterValue; + break; + case 0x824: + reg->M24_MacControl = RegisterValue; + break; + case 0x828: + reg->M28_MacControl = RegisterValue; + break; + case 0x82c: + reg->M2C_MacControl = RegisterValue; + break; + case 0x838: + reg->M38_MacControl = RegisterValue; + break; + case 0x840: + reg->M40_MacControl = RegisterValue; + break; + case 0x844: + reg->M44_MacControl = RegisterValue; + break; + case 0x848: + reg->M48_MacControl = RegisterValue; + break; + case 0x84c: + reg->M4C_MacStatus = RegisterValue; + break; + case 0x860: + reg->M60_MacControl = RegisterValue; + break; + case 0x868: + reg->M68_MacControl = RegisterValue; + break; + case 0x870: + reg->M70_MacControl = RegisterValue; + break; + case 0x874: + reg->M74_MacControl = RegisterValue; + break; + case 0x878: + reg->M78_ERPInformation = RegisterValue; + break; + case 0x87C: + reg->M7C_MacControl = RegisterValue; + break; + case 0x880: + reg->M80_MacControl = RegisterValue; + break; + case 0x884: + reg->M84_MacControl = RegisterValue; + break; + case 0x888: + reg->M88_MacControl = RegisterValue; + break; + case 0x898: + reg->M98_MacControl = RegisterValue; + break; + case 0x100c: + reg->BB0C = RegisterValue; + break; + case 0x102c: + reg->BB2C = RegisterValue; + break; + case 0x1030: + reg->BB30 = RegisterValue; + break; + case 0x103c: + reg->BB3C = RegisterValue; + break; + case 0x1048: + reg->BB48 = RegisterValue; + break; + case 0x104c: + reg->BB4C = RegisterValue; + break; + case 0x1050: + reg->BB50 = RegisterValue; + break; + case 0x1054: + reg->BB54 = RegisterValue; + break; + case 0x1058: + reg->BB58 = RegisterValue; + break; + case 0x105c: + reg->BB5C = RegisterValue; + break; + case 0x1060: + reg->BB60 = RegisterValue; + break; } } @@ -120,7 +188,8 @@ void Wb35Reg_Update(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue * true : read command process successfully * false : register not support */ -unsigned char Wb35Reg_WriteSync(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue) +unsigned char Wb35Reg_WriteSync(struct hw_data *pHwData, u16 RegisterNo, + u32 RegisterValue) { struct wb35_reg *reg = &pHwData->reg; int ret = -1; @@ -140,19 +209,18 @@ unsigned char Wb35Reg_WriteSync(struct hw_data *pHwData, u16 RegisterNo, u32 Reg /* Sync IoCallDriver */ reg->EP0vm_state = VM_RUNNING; - ret = usb_control_msg(pHwData->WbUsb.udev, - usb_sndctrlpipe(pHwData->WbUsb.udev, 0), - 0x03, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, - 0x0, RegisterNo, &RegisterValue, 4, HZ * 100); + ret = usb_control_msg(pHwData->udev, + usb_sndctrlpipe(pHwData->udev, 0), + 0x03, + USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, + 0x0, RegisterNo, &RegisterValue, 4, HZ * 100); reg->EP0vm_state = VM_STOP; reg->SyncIoPause = 0; Wb35Reg_EP0VM_start(pHwData); if (ret < 0) { -#ifdef _PE_REG_DUMP_ - printk("EP0 Write register usb message sending error\n"); -#endif + pr_debug("EP0 Write register usb message sending error\n"); pHwData->SurpriseRemove = 1; return false; } @@ -163,7 +231,8 @@ unsigned char Wb35Reg_WriteSync(struct hw_data *pHwData, u16 RegisterNo, u32 Reg * true : read command process successfully * false : register not support */ -unsigned char Wb35Reg_Write(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue) +unsigned char Wb35Reg_Write(struct hw_data *pHwData, u16 RegisterNo, + u32 RegisterValue) { struct wb35_reg *reg = &pHwData->reg; struct usb_ctrlrequest *dr; @@ -178,50 +247,51 @@ unsigned char Wb35Reg_Write(struct hw_data *pHwData, u16 RegisterNo, u32 Registe /* update the register by send urb request */ UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); reg_queue = kzalloc(UrbSize, GFP_ATOMIC); + if (reg_queue == NULL) + return false; + urb = usb_alloc_urb(0, GFP_ATOMIC); - if (urb && reg_queue) { - reg_queue->DIRECT = 1; /* burst write register */ - reg_queue->INDEX = RegisterNo; - reg_queue->VALUE = cpu_to_le32(RegisterValue); - reg_queue->RESERVED_VALID = false; - dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); - dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; - dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */ - dr->wValue = cpu_to_le16(0x0); - dr->wIndex = cpu_to_le16(RegisterNo); - dr->wLength = cpu_to_le16(4); - - /* Enter the sending queue */ - reg_queue->Next = NULL; - reg_queue->pUsbReq = dr; - reg_queue->urb = urb; + if (urb == NULL) { + kfree(reg_queue); + return false; + } - spin_lock_irq(®->EP0VM_spin_lock); - if (reg->reg_first == NULL) - reg->reg_first = reg_queue; - else - reg->reg_last->Next = reg_queue; - reg->reg_last = reg_queue; + reg_queue->DIRECT = 1; /* burst write register */ + reg_queue->INDEX = RegisterNo; + reg_queue->VALUE = cpu_to_le32(RegisterValue); + reg_queue->RESERVED_VALID = false; + dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); + dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; + dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */ + dr->wValue = cpu_to_le16(0x0); + dr->wIndex = cpu_to_le16(RegisterNo); + dr->wLength = cpu_to_le16(4); + + /* Enter the sending queue */ + reg_queue->Next = NULL; + reg_queue->pUsbReq = dr; + reg_queue->urb = urb; - spin_unlock_irq(®->EP0VM_spin_lock); + spin_lock_irq(®->EP0VM_spin_lock); + if (reg->reg_first == NULL) + reg->reg_first = reg_queue; + else + reg->reg_last->Next = reg_queue; + reg->reg_last = reg_queue; - /* Start EP0VM */ - Wb35Reg_EP0VM_start(pHwData); + spin_unlock_irq(®->EP0VM_spin_lock); - return true; - } else { - if (urb) - usb_free_urb(urb); - kfree(reg_queue); - return false; - } + /* Start EP0VM */ + Wb35Reg_EP0VM_start(pHwData); + + return true; } /* * This command will be executed with a user defined value. When it completes, * this value is useful. For example, hal_set_current_channel will use it. * true : read command process successfully - * false : register not support + * false : register not supported */ unsigned char Wb35Reg_WriteWithCallbackValue(struct hw_data *pHwData, u16 RegisterNo, @@ -242,43 +312,45 @@ unsigned char Wb35Reg_WriteWithCallbackValue(struct hw_data *pHwData, /* update the register by send urb request */ UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); reg_queue = kzalloc(UrbSize, GFP_ATOMIC); - urb = usb_alloc_urb(0, GFP_ATOMIC); - if (urb && reg_queue) { - reg_queue->DIRECT = 1; /* burst write register */ - reg_queue->INDEX = RegisterNo; - reg_queue->VALUE = cpu_to_le32(RegisterValue); - /* NOTE : Users must guarantee the size of value will not exceed the buffer size. */ - memcpy(reg_queue->RESERVED, pValue, Len); - reg_queue->RESERVED_VALID = true; - dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); - dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; - dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */ - dr->wValue = cpu_to_le16(0x0); - dr->wIndex = cpu_to_le16(RegisterNo); - dr->wLength = cpu_to_le16(4); - - /* Enter the sending queue */ - reg_queue->Next = NULL; - reg_queue->pUsbReq = dr; - reg_queue->urb = urb; - spin_lock_irq(®->EP0VM_spin_lock); - if (reg->reg_first == NULL) - reg->reg_first = reg_queue; - else - reg->reg_last->Next = reg_queue; - reg->reg_last = reg_queue; - - spin_unlock_irq(®->EP0VM_spin_lock); + if (reg_queue == NULL) + return false; - /* Start EP0VM */ - Wb35Reg_EP0VM_start(pHwData); - return true; - } else { - if (urb) - usb_free_urb(urb); + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (urb == NULL) { kfree(reg_queue); return false; } + + reg_queue->DIRECT = 1; /* burst write register */ + reg_queue->INDEX = RegisterNo; + reg_queue->VALUE = cpu_to_le32(RegisterValue); + /* NOTE : Users must guarantee the size of value will not exceed the buffer size. */ + memcpy(reg_queue->RESERVED, pValue, Len); + reg_queue->RESERVED_VALID = true; + dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); + dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; + dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */ + dr->wValue = cpu_to_le16(0x0); + dr->wIndex = cpu_to_le16(RegisterNo); + dr->wLength = cpu_to_le16(4); + + /* Enter the sending queue */ + reg_queue->Next = NULL; + reg_queue->pUsbReq = dr; + reg_queue->urb = urb; + spin_lock_irq(®->EP0VM_spin_lock); + if (reg->reg_first == NULL) + reg->reg_first = reg_queue; + else + reg->reg_last->Next = reg_queue; + reg->reg_last = reg_queue; + + spin_unlock_irq(®->EP0VM_spin_lock); + + /* Start EP0VM */ + Wb35Reg_EP0VM_start(pHwData); + + return true; } /* @@ -287,7 +359,8 @@ unsigned char Wb35Reg_WriteWithCallbackValue(struct hw_data *pHwData, * pRegisterValue : It must be a resident buffer due to * asynchronous read register. */ -unsigned char Wb35Reg_ReadSync(struct hw_data *pHwData, u16 RegisterNo, u32 *pRegisterValue) +unsigned char Wb35Reg_ReadSync(struct hw_data *pHwData, u16 RegisterNo, + u32 *pRegisterValue) { struct wb35_reg *reg = &pHwData->reg; u32 *pltmp = pRegisterValue; @@ -305,10 +378,11 @@ unsigned char Wb35Reg_ReadSync(struct hw_data *pHwData, u16 RegisterNo, u32 *pRe msleep(10); reg->EP0vm_state = VM_RUNNING; - ret = usb_control_msg(pHwData->WbUsb.udev, - usb_rcvctrlpipe(pHwData->WbUsb.udev, 0), - 0x01, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN, - 0x0, RegisterNo, pltmp, 4, HZ * 100); + ret = usb_control_msg(pHwData->udev, + usb_rcvctrlpipe(pHwData->udev, 0), + 0x01, + USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN, + 0x0, RegisterNo, pltmp, 4, HZ * 100); *pRegisterValue = cpu_to_le32(*pltmp); @@ -320,9 +394,7 @@ unsigned char Wb35Reg_ReadSync(struct hw_data *pHwData, u16 RegisterNo, u32 *pRe Wb35Reg_EP0VM_start(pHwData); if (ret < 0) { -#ifdef _PE_REG_DUMP_ - printk("EP0 Read register usb message sending error\n"); -#endif + pr_debug("EP0 Read register usb message sending error\n"); pHwData->SurpriseRemove = 1; return false; } @@ -335,7 +407,8 @@ unsigned char Wb35Reg_ReadSync(struct hw_data *pHwData, u16 RegisterNo, u32 *pRe * pRegisterValue : It must be a resident buffer due to * asynchronous read register. */ -unsigned char Wb35Reg_Read(struct hw_data *pHwData, u16 RegisterNo, u32 *pRegisterValue) +unsigned char Wb35Reg_Read(struct hw_data *pHwData, u16 RegisterNo, + u32 *pRegisterValue) { struct wb35_reg *reg = &pHwData->reg; struct usb_ctrlrequest *dr; @@ -350,41 +423,41 @@ unsigned char Wb35Reg_Read(struct hw_data *pHwData, u16 RegisterNo, u32 *pRegist /* update the variable by send Urb to read register */ UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); reg_queue = kzalloc(UrbSize, GFP_ATOMIC); - urb = usb_alloc_urb(0, GFP_ATOMIC); - if (urb && reg_queue) { - reg_queue->DIRECT = 0; /* read register */ - reg_queue->INDEX = RegisterNo; - reg_queue->pBuffer = pRegisterValue; - dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); - dr->bRequestType = USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN; - dr->bRequest = 0x01; /* USB or vendor-defined request code, burst mode */ - dr->wValue = cpu_to_le16(0x0); - dr->wIndex = cpu_to_le16(RegisterNo); - dr->wLength = cpu_to_le16(4); - - /* Enter the sending queue */ - reg_queue->Next = NULL; - reg_queue->pUsbReq = dr; - reg_queue->urb = urb; - spin_lock_irq(®->EP0VM_spin_lock); - if (reg->reg_first == NULL) - reg->reg_first = reg_queue; - else - reg->reg_last->Next = reg_queue; - reg->reg_last = reg_queue; - - spin_unlock_irq(®->EP0VM_spin_lock); - - /* Start EP0VM */ - Wb35Reg_EP0VM_start(pHwData); + if (reg_queue == NULL) + return false; - return true; - } else { - if (urb) - usb_free_urb(urb); + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (urb == NULL) { kfree(reg_queue); return false; } + reg_queue->DIRECT = 0; /* read register */ + reg_queue->INDEX = RegisterNo; + reg_queue->pBuffer = pRegisterValue; + dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); + dr->bRequestType = USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN; + dr->bRequest = 0x01; /* USB or vendor-defined request code, burst mode */ + dr->wValue = cpu_to_le16(0x0); + dr->wIndex = cpu_to_le16(RegisterNo); + dr->wLength = cpu_to_le16(4); + + /* Enter the sending queue */ + reg_queue->Next = NULL; + reg_queue->pUsbReq = dr; + reg_queue->urb = urb; + spin_lock_irq(®->EP0VM_spin_lock); + if (reg->reg_first == NULL) + reg->reg_first = reg_queue; + else + reg->reg_last->Next = reg_queue; + reg->reg_last = reg_queue; + + spin_unlock_irq(®->EP0VM_spin_lock); + + /* Start EP0VM */ + Wb35Reg_EP0VM_start(pHwData); + + return true; } @@ -432,8 +505,8 @@ void Wb35Reg_EP0VM(struct hw_data *pHwData) if (reg_queue->DIRECT == 1) /* output */ pBuffer = ®_queue->VALUE; - usb_fill_control_urb(urb, pHwData->WbUsb.udev, - REG_DIRECTION(pHwData->WbUsb.udev, reg_queue), + usb_fill_control_urb(urb, pHwData->udev, + REG_DIRECTION(pHwData->udev, reg_queue), (u8 *)dr, pBuffer, cpu_to_le16(dr->wLength), Wb35Reg_EP0VM_complete, (void *)pHwData); @@ -442,9 +515,7 @@ void Wb35Reg_EP0VM(struct hw_data *pHwData) ret = usb_submit_urb(urb, GFP_ATOMIC); if (ret < 0) { -#ifdef _PE_REG_DUMP_ - printk("EP0 Irp sending error\n"); -#endif + pr_debug("EP0 Irp sending error\n"); goto cleanup; } return; @@ -479,9 +550,7 @@ void Wb35Reg_EP0VM_complete(struct urb *urb) spin_unlock_irq(®->EP0VM_spin_lock); if (reg->EP0VM_status) { -#ifdef _PE_REG_DUMP_ - printk("EP0 IoCompleteRoutine return error\n"); -#endif + pr_debug("EP0 IoCompleteRoutine return error\n"); reg->EP0vm_state = VM_STOP; pHwData->SurpriseRemove = 1; } else { @@ -526,9 +595,7 @@ void Wb35Reg_destroy(struct hw_data *pHwData) usb_free_urb(urb); kfree(reg_queue); } else { -#ifdef _PE_REG_DUMP_ - printk("EP0 queue release error\n"); -#endif + pr_debug("EP0 queue release error\n"); } spin_lock_irq(®->EP0VM_spin_lock); @@ -643,7 +710,7 @@ unsigned char Wb35Reg_initial(struct hw_data *pHwData) * CardComputeCrc -- * * Description: - * Runs the AUTODIN II CRC algorithm on buffer Buffer of length, Length. + * Runs the AUTODIN II CRC algorithm on the buffers Buffer length. * * Arguments: * Buffer - the input buffer diff --git a/drivers/staging/winbond/wb35reg_f.h b/drivers/staging/winbond/wb35reg_f.h index bf23c108419..95dc9809684 100644 --- a/drivers/staging/winbond/wb35reg_f.h +++ b/drivers/staging/winbond/wb35reg_f.h @@ -1,7 +1,7 @@ #ifndef __WINBOND_WB35REG_F_H #define __WINBOND_WB35REG_F_H -#include "wbhal_s.h" +#include "wbhal.h" /* * ==================================== diff --git a/drivers/staging/winbond/wb35reg_s.h b/drivers/staging/winbond/wb35reg_s.h index 4eff009444b..dc79faa4029 100644 --- a/drivers/staging/winbond/wb35reg_s.h +++ b/drivers/staging/winbond/wb35reg_s.h @@ -3,7 +3,9 @@ #include <linux/spinlock.h> #include <linux/types.h> -#include <asm/atomic.h> +#include <linux/atomic.h> + +struct hw_data; /* ========================================================================= * @@ -49,11 +51,7 @@ #define DEFAULT_CWMAX 1023 /* (M2C) CWmax. Its value is in the range 0-1023. */ #define DEFAULT_AID 1 /* (M34) AID. Its value is in the range 1-2007. */ -#ifdef _USE_FALLBACK_RATE_ #define DEFAULT_RATE_RETRY_LIMIT 2 /* (M38) as named */ -#else -#define DEFAULT_RATE_RETRY_LIMIT 7 /* (M38) as named */ -#endif #define DEFAULT_LONG_RETRY_LIMIT 7 /* (M38) LongRetryLimit. Its value is in the range 0-15. */ #define DEFAULT_SHORT_RETRY_LIMIT 7 /* (M38) ShortRetryLimit. Its value is in the range 0-15. */ @@ -168,4 +166,75 @@ struct wb35_reg { u32 SQ3_filter[MAX_SQ3_FILTER_SIZE]; u32 SQ3_index; }; + +/* ===================================================================== + * Function declaration + * ===================================================================== + */ +void hal_remove_mapping_key(struct hw_data *hw_data, u8 *mac_addr); +void hal_remove_default_key(struct hw_data *hw_data, u32 index); +unsigned char hal_set_mapping_key(struct hw_data *adapter, u8 *mac_addr, + u8 null_key, u8 wep_on, u8 *tx_tsc, + u8 *rx_tsc, u8 key_type, u8 key_len, + u8 *key_data); +unsigned char hal_set_default_key(struct hw_data *adapter, u8 index, + u8 null_key, u8 wep_on, u8 *tx_tsc, + u8 *rx_tsc, u8 key_type, u8 key_len, + u8 *key_data); +void hal_clear_all_default_key(struct hw_data *hw_data); +void hal_clear_all_group_key(struct hw_data *hw_data); +void hal_clear_all_mapping_key(struct hw_data *hw_data); +void hal_clear_all_key(struct hw_data *hw_data); +void hal_set_power_save_mode(struct hw_data *hw_data, unsigned char power_save, + unsigned char wakeup, unsigned char dtim); +void hal_get_power_save_mode(struct hw_data *hw_data, u8 *in_pwr_save); +void hal_set_slot_time(struct hw_data *hw_data, u8 type); + +#define hal_set_atim_window(_A, _ATM) + +void hal_start_bss(struct hw_data *hw_data, u8 mac_op_mode); + +/* 0:BSS STA 1:IBSS STA */ +void hal_join_request(struct hw_data *hw_data, u8 bss_type); + +void hal_stop_sync_bss(struct hw_data *hw_data); +void hal_resume_sync_bss(struct hw_data *hw_data); +void hal_set_aid(struct hw_data *hw_data, u16 aid); +void hal_set_bssid(struct hw_data *hw_data, u8 *bssid); +void hal_get_bssid(struct hw_data *hw_data, u8 *bssid); +void hal_set_listen_interval(struct hw_data *hw_data, u16 listen_interval); +void hal_set_cap_info(struct hw_data *hw_data, u16 capability_info); +void hal_set_ssid(struct hw_data *hw_data, u8 *ssid, u8 ssid_len); +void hal_start_tx0(struct hw_data *hw_data); + +#define hal_get_cwmin(_A) ((_A)->cwmin) + +void hal_set_cwmax(struct hw_data *hw_data, u16 cwin_max); + +#define hal_get_cwmax(_A) ((_A)->cwmax) + +void hal_set_rsn_wpa(struct hw_data *hw_data, u32 *rsn_ie_bitmap, + u32 *rsn_oui_type , unsigned char desired_auth_mode); +void hal_set_connect_info(struct hw_data *hw_data, unsigned char bo_connect); +u8 hal_get_est_sq3(struct hw_data *hw_data, u8 count); +void hal_descriptor_indicate(struct hw_data *hw_data, + struct wb35_descriptor *des); +u8 hal_get_antenna_number(struct hw_data *hw_data); +u32 hal_get_bss_pk_cnt(struct hw_data *hw_data); + +#define hal_get_region_from_EEPROM(_A) ((_A)->reg.EEPROMRegion) +#define hal_get_tx_buffer(_A, _B) Wb35Tx_get_tx_buffer(_A, _B) +#define hal_software_set(_A) (_A->SoftwareSet) +#define hal_driver_init_OK(_A) (_A->IsInitOK) +#define hal_rssi_boundary_high(_A) (_A->RSSI_high) +#define hal_rssi_boundary_low(_A) (_A->RSSI_low) +#define hal_scan_interval(_A) (_A->Scan_Interval) + +#define PHY_DEBUG(msg, args...) + +/* return 100ms count */ +#define hal_get_time_count(_P) (_P->time_count / 10) + +#define hal_ibss_disconnect(_A) (hal_stop_sync_bss(_A)) + #endif diff --git a/drivers/staging/winbond/wb35rx.c b/drivers/staging/winbond/wb35rx.c index efe82b141c1..f006b166aeb 100644 --- a/drivers/staging/winbond/wb35rx.c +++ b/drivers/staging/winbond/wb35rx.c @@ -14,10 +14,10 @@ #include <linux/slab.h> #include "core.h" -#include "sysdef.h" #include "wb35rx_f.h" -static void packet_came(struct ieee80211_hw *hw, char *pRxBufferAddress, int PacketSize) +static void packet_came(struct ieee80211_hw *hw, char *pRxBufferAddress, + int PacketSize) { struct wbsoft_priv *priv = hw->priv; struct sk_buff *skb; @@ -65,7 +65,8 @@ static void Wb35Rx_adjust(struct wb35_descriptor *pRxDes) } else if (DecryptionMethod) { /* For TKIP and CCMP */ for (i = 7; i > 1; i--) pRxBufferAddress[i] = pRxBufferAddress[i - 2]; - pRxDes->buffer_address[0] = pRxBufferAddress + 2; /* Update the descriptor, shift 8 byte */ + /* Update the descriptor, shift 8 byte */ + pRxDes->buffer_address[0] = pRxBufferAddress + 2; BufferSize -= 8; /* 8 byte for IV + ICV */ } pRxDes->buffer_size[0] = BufferSize; @@ -96,7 +97,9 @@ static u16 Wb35Rx_indicate(struct ieee80211_hw *hw) /* Parse the bulkin buffer */ while (BufferSize >= 4) { - if ((cpu_to_le32(*(u32 *)pRxBufferAddress) & 0x0fffffff) == RX_END_TAG) /* Is ending? */ + /* Is ending? */ + if ((cpu_to_le32(*(u32 *)pRxBufferAddress) & 0x0fffffff) == + RX_END_TAG) break; /* Get the R00 R01 first */ @@ -109,10 +112,8 @@ static u16 Wb35Rx_indicate(struct ieee80211_hw *hw) /* Basic check for Rx length. Is length valid? */ if (PacketSize > MAX_PACKET_SIZE) { -#ifdef _PE_RX_DUMP_ - printk("Serious ERROR : Rx data size too long, size =%d\n", PacketSize); -#endif - + pr_debug("Serious ERROR : Rx data size too long, size =%d\n", + PacketSize); pWb35Rx->EP3vm_state = VM_STOP; pWb35Rx->Ep3ErrorCount2++; break; @@ -122,7 +123,8 @@ static u16 Wb35Rx_indicate(struct ieee80211_hw *hw) * Wb35Rx_indicate() is called synchronously so it isn't * necessary to set "RxDes.Desctriptor_ID = RxBufferID;" */ - BufferSize -= 8; /* subtract 8 byte for 35's USB header length */ + /* subtract 8 byte for 35's USB header length */ + BufferSize -= 8; pRxBufferAddress += 8; RxDes.buffer_address[0] = pRxBufferAddress; @@ -160,7 +162,7 @@ static void Wb35Rx_Complete(struct urb *urb) u32 SizeCheck; u16 BulkLength; u32 RxBufferId; - R00_DESCRIPTOR R00; + struct R00_descriptor R00; /* Variable setting */ pWb35Rx->EP3vm_state = VM_COMPLETED; @@ -174,7 +176,7 @@ static void Wb35Rx_Complete(struct urb *urb) /* The IRP is completed */ pWb35Rx->EP3vm_state = VM_COMPLETED; - if (pHwData->SurpriseRemove || pHwData->HwStop) /* Must be here, or RxBufferId is invalid */ + if (pHwData->SurpriseRemove) /* Must be here, or RxBufferId is invalid */ goto error; if (pWb35Rx->rx_halt) @@ -186,9 +188,7 @@ static void Wb35Rx_Complete(struct urb *urb) /* The URB is completed, check the result */ if (pWb35Rx->EP3VM_status != 0) { -#ifdef _PE_USB_STATE_DUMP_ - printk("EP3 IoCompleteRoutine return error\n"); -#endif + pr_debug("EP3 IoCompleteRoutine return error\n"); pWb35Rx->EP3vm_state = VM_STOP; goto error; } @@ -239,7 +239,7 @@ static void Wb35Rx(struct ieee80211_hw *hw) u32 RxBufferId; /* Issuing URB */ - if (pHwData->SurpriseRemove || pHwData->HwStop) + if (pHwData->SurpriseRemove) goto error; if (pWb35Rx->rx_halt) @@ -249,9 +249,7 @@ static void Wb35Rx(struct ieee80211_hw *hw) RxBufferId = pWb35Rx->RxBufferId; if (!pWb35Rx->RxOwner[RxBufferId]) { /* It's impossible to run here. */ -#ifdef _PE_RX_DUMP_ - printk("Rx driver fifo unavailable\n"); -#endif + pr_debug("Rx driver fifo unavailable\n"); goto error; } @@ -263,13 +261,13 @@ static void Wb35Rx(struct ieee80211_hw *hw) pWb35Rx->pDRx = kzalloc(MAX_USB_RX_BUFFER, GFP_ATOMIC); if (!pWb35Rx->pDRx) { - printk("w35und: Rx memory alloc failed\n"); + dev_info(&hw->wiphy->dev, "w35und: Rx memory alloc failed\n"); goto error; } pRxBufferAddress = pWb35Rx->pDRx; - usb_fill_bulk_urb(urb, pHwData->WbUsb.udev, - usb_rcvbulkpipe(pHwData->WbUsb.udev, 3), + usb_fill_bulk_urb(urb, pHwData->udev, + usb_rcvbulkpipe(pHwData->udev, 3), pRxBufferAddress, MAX_USB_RX_BUFFER, Wb35Rx_Complete, hw); @@ -278,7 +276,7 @@ static void Wb35Rx(struct ieee80211_hw *hw) retv = usb_submit_urb(urb, GFP_ATOMIC); if (retv != 0) { - printk("Rx URB sending error\n"); + dev_info(&hw->wiphy->dev, "Rx URB sending error\n"); goto error; } return; @@ -314,7 +312,9 @@ static void Wb35Rx_reset_descriptor(struct hw_data *pHwData) pWb35Rx->EP3vm_state = VM_STOP; pWb35Rx->rx_halt = 0; - /* Initial the Queue. The last buffer is reserved for used if the Rx resource is unavailable. */ + /* Initial the Queue. The last buffer is reserved for used + * if the Rx resource is unavailable. + */ for (i = 0; i < MAX_USB_RX_BUFFER_NUMBER; i++) pWb35Rx->RxOwner[i] = 1; } @@ -336,10 +336,9 @@ void Wb35Rx_stop(struct hw_data *pHwData) /* Canceling the Irp if already sends it out. */ if (pWb35Rx->EP3vm_state == VM_RUNNING) { - usb_unlink_urb(pWb35Rx->RxUrb); /* Only use unlink, let Wb35Rx_destroy to free them */ -#ifdef _PE_RX_DUMP_ - printk("EP3 Rx stop\n"); -#endif + /* Only use unlink, let Wb35Rx_destroy to free them */ + usb_unlink_urb(pWb35Rx->RxUrb); + pr_debug("EP3 Rx stop\n"); } } @@ -353,10 +352,7 @@ void Wb35Rx_destroy(struct hw_data *pHwData) } while (pWb35Rx->EP3vm_state != VM_STOP); msleep(10); /* Delay for waiting function exit */ - if (pWb35Rx->RxUrb) - usb_free_urb(pWb35Rx->RxUrb); -#ifdef _PE_RX_DUMP_ - printk("Wb35Rx_destroy OK\n"); -#endif + usb_free_urb(pWb35Rx->RxUrb); + pr_debug("Wb35Rx_destroy OK\n"); } diff --git a/drivers/staging/winbond/wb35rx_f.h b/drivers/staging/winbond/wb35rx_f.h index 98acce517d9..559bdca12e1 100644 --- a/drivers/staging/winbond/wb35rx_f.h +++ b/drivers/staging/winbond/wb35rx_f.h @@ -2,14 +2,14 @@ #define __WINBOND_WB35RX_F_H #include <net/mac80211.h> -#include "wbhal_s.h" +#include "wbhal.h" -//==================================== -// Interface function declare -//==================================== -unsigned char Wb35Rx_initial( struct hw_data * pHwData ); -void Wb35Rx_destroy( struct hw_data * pHwData ); -void Wb35Rx_stop( struct hw_data * pHwData ); +/* + * Interface function declaration + */ +unsigned char Wb35Rx_initial(struct hw_data *pHwData); +void Wb35Rx_destroy(struct hw_data *pHwData); +void Wb35Rx_stop(struct hw_data *pHwData); void Wb35Rx_start(struct ieee80211_hw *hw); #endif diff --git a/drivers/staging/winbond/wb35rx_s.h b/drivers/staging/winbond/wb35rx_s.h index 4b03274a7d2..545bc950072 100644 --- a/drivers/staging/winbond/wb35rx_s.h +++ b/drivers/staging/winbond/wb35rx_s.h @@ -1,44 +1,44 @@ -//============================================================================ -// wb35rx.h -- -//============================================================================ +#ifndef __WINBOND_35RX_S_H +#define __WINBOND_35RX_S_H -// Definition for this module used -#define MAX_USB_RX_BUFFER 4096 // This parameter must be 4096 931130.4.f +/* Definition for this module used */ +#define MAX_USB_RX_BUFFER 4096 /* This parameter must be 4096 931130.4.f */ +#define MAX_USB_RX_BUFFER_NUMBER ETHERNET_RX_DESCRIPTORS /* Maximum 254, 255 is RESERVED ID */ +#define RX_INTERFACE 0 /* Interface 1 */ +#define RX_PIPE 2 /* Pipe 3 */ +#define MAX_PACKET_SIZE 1600 /* 1568 = 8 + 1532 + 4 + 24(IV EIV MIC ICV CRC) for check DMA data 931130.4.g */ +#define RX_END_TAG 0x0badbeef -#define MAX_USB_RX_BUFFER_NUMBER ETHERNET_RX_DESCRIPTORS // Maximum 254, 255 is RESERVED ID -#define RX_INTERFACE 0 // Interface 1 -#define RX_PIPE 2 // Pipe 3 -#define MAX_PACKET_SIZE 1600 //1568 // 8 + 1532 + 4 + 24(IV EIV MIC ICV CRC) for check DMA data 931130.4.g -#define RX_END_TAG 0x0badbeef - -//==================================== -// Internal variable for module -//==================================== +/* + * Internal variable for module + */ struct wb35_rx { - u32 ByteReceived;// For calculating throughput of BulkIn - atomic_t RxFireCounter;// Does Wb35Rx module fire? + u32 ByteReceived; /* For calculating throughput of BulkIn */ + atomic_t RxFireCounter;/* Does Wb35Rx module fire? */ - u8 RxBuffer[ MAX_USB_RX_BUFFER_NUMBER ][ ((MAX_USB_RX_BUFFER+3) & ~0x03 ) ]; - u16 RxBufferSize[ ((MAX_USB_RX_BUFFER_NUMBER+1) & ~0x01) ]; - u8 RxOwner[ ((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03 ) ];//Ownership of buffer 0: SW 1:HW + u8 RxBuffer[MAX_USB_RX_BUFFER_NUMBER][((MAX_USB_RX_BUFFER+3) & ~0x03)]; + u16 RxBufferSize[((MAX_USB_RX_BUFFER_NUMBER+1) & ~0x01)]; + u8 RxOwner[((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03)]; /* Ownership of buffer 0:SW 1:HW */ - u32 RxProcessIndex;//The next index to process - u32 RxBufferId; - u32 EP3vm_state; + u32 RxProcessIndex; /* The next index to process */ + u32 RxBufferId; + u32 EP3vm_state; - u32 rx_halt; // For VM stopping + u32 rx_halt; /* For VM stopping */ - u16 MoreDataSize; - u16 PacketSize; + u16 MoreDataSize; + u16 PacketSize; - u32 CurrentRxBufferId; // For complete routine usage - u32 Rx3UrbCancel; + u32 CurrentRxBufferId; /* For complete routine usage */ + u32 Rx3UrbCancel; - u32 LastR1; // For RSSI reporting - struct urb * RxUrb; - u32 Ep3ErrorCount2; // 20060625.1 Usbd for Rx DMA error count + u32 LastR1; /* For RSSI reporting */ + struct urb *RxUrb; + u32 Ep3ErrorCount2; /* 20060625.1 Usbd for Rx DMA error count */ int EP3VM_status; - u8 * pDRx; + u8 *pDRx; }; + +#endif /* __WINBOND_35RX_S_H */ diff --git a/drivers/staging/winbond/wb35tx.c b/drivers/staging/winbond/wb35tx.c index bda7a913edf..870cff39a22 100644 --- a/drivers/staging/winbond/wb35tx.c +++ b/drivers/staging/winbond/wb35tx.c @@ -1,22 +1,21 @@ -//============================================================================ -// Copyright (c) 1996-2002 Winbond Electronic Corporation -// -// Module Name: -// Wb35Tx.c -// -// Abstract: -// Processing the Tx message and put into down layer -// -//============================================================================ +/* + * Copyright (c) 1996-2002 Winbond Electronic Corporation + * + * Module Name: + * Wb35Tx.c + * + * Abstract: + * Processing the Tx message and put into down layer + * + */ #include <linux/usb.h> #include <linux/gfp.h> #include "wb35tx_f.h" #include "mds_f.h" -#include "sysdef.h" unsigned char -Wb35Tx_get_tx_buffer(struct hw_data * pHwData, u8 **pBuffer) +Wb35Tx_get_tx_buffer(struct hw_data *pHwData, u8 **pBuffer) { struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; @@ -26,30 +25,31 @@ Wb35Tx_get_tx_buffer(struct hw_data * pHwData, u8 **pBuffer) static void Wb35Tx(struct wbsoft_priv *adapter); -static void Wb35Tx_complete(struct urb * pUrb) +static void Wb35Tx_complete(struct urb *pUrb) { struct wbsoft_priv *adapter = pUrb->context; - struct hw_data * pHwData = &adapter->sHwData; + struct hw_data *pHwData = &adapter->sHwData; struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; struct wb35_mds *pMds = &adapter->Mds; printk("wb35: tx complete\n"); - // Variable setting + /* Variable setting */ pWb35Tx->EP4vm_state = VM_COMPLETED; - pWb35Tx->EP4VM_status = pUrb->status; //Store the last result of Irp - pMds->TxOwner[ pWb35Tx->TxSendIndex ] = 0;// Set the owner. Free the owner bit always. + pWb35Tx->EP4VM_status = pUrb->status; /* Store the last result of Irp */ + /* Set the owner. Free the owner bit always. */ + pMds->TxOwner[pWb35Tx->TxSendIndex] = 0; pWb35Tx->TxSendIndex++; pWb35Tx->TxSendIndex %= MAX_USB_TX_BUFFER_NUMBER; - if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove + if (pHwData->SurpriseRemove) /* Let WbWlanHalt handle surprise remove */ goto error; if (pWb35Tx->tx_halt) goto error; - // The URB is completed, check the result + /* The URB is completed, check the result */ if (pWb35Tx->EP4VM_status != 0) { - printk("URB submission failed\n"); + dev_err(&pUrb->dev->dev, "URB submission failed\n"); pWb35Tx->EP4vm_state = VM_STOP; goto error; } @@ -65,43 +65,42 @@ error: static void Wb35Tx(struct wbsoft_priv *adapter) { - struct hw_data * pHwData = &adapter->sHwData; + struct hw_data *pHwData = &adapter->sHwData; struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; u8 *pTxBufferAddress; struct wb35_mds *pMds = &adapter->Mds; - struct urb * pUrb = (struct urb *)pWb35Tx->Tx4Urb; - int retv; + struct urb *pUrb = (struct urb *)pWb35Tx->Tx4Urb; + int retv; u32 SendIndex; - - if (pHwData->SurpriseRemove || pHwData->HwStop) + if (pHwData->SurpriseRemove) goto cleanup; if (pWb35Tx->tx_halt) goto cleanup; - // Ownership checking + /* Ownership checking */ SendIndex = pWb35Tx->TxSendIndex; - if (!pMds->TxOwner[SendIndex]) //No more data need to be sent, return immediately + /* No more data need to be sent, return immediately */ + if (!pMds->TxOwner[SendIndex]) goto cleanup; pTxBufferAddress = pWb35Tx->TxBuffer[SendIndex]; - // - // Issuing URB - // - usb_fill_bulk_urb(pUrb, pHwData->WbUsb.udev, - usb_sndbulkpipe(pHwData->WbUsb.udev, 4), - pTxBufferAddress, pMds->TxBufferSize[ SendIndex ], + + /* Issuing URB */ + usb_fill_bulk_urb(pUrb, pHwData->udev, + usb_sndbulkpipe(pHwData->udev, 4), + pTxBufferAddress, pMds->TxBufferSize[SendIndex], Wb35Tx_complete, adapter); pWb35Tx->EP4vm_state = VM_RUNNING; retv = usb_submit_urb(pUrb, GFP_ATOMIC); - if (retv<0) { - printk("EP4 Tx Irp sending error\n"); + if (retv < 0) { + dev_err(&pUrb->dev->dev, "EP4 Tx Irp sending error\n"); goto cleanup; } - // Check if driver needs issue Irp for EP2 + /* Check if driver needs issue Irp for EP2 */ pWb35Tx->TxFillCount += pMds->TxCountInBuffer[SendIndex]; if (pWb35Tx->TxFillCount > 12) Wb35Tx_EP2VM_start(adapter); @@ -116,10 +115,10 @@ static void Wb35Tx(struct wbsoft_priv *adapter) void Wb35Tx_start(struct wbsoft_priv *adapter) { - struct hw_data * pHwData = &adapter->sHwData; + struct hw_data *pHwData = &adapter->sHwData; struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; - // Allow only one thread to run into function + /* Allow only one thread to run into function */ if (atomic_inc_return(&pWb35Tx->TxFireCounter) == 1) { pWb35Tx->EP4vm_state = VM_RUNNING; Wb35Tx(adapter); @@ -127,7 +126,7 @@ void Wb35Tx_start(struct wbsoft_priv *adapter) atomic_dec(&pWb35Tx->TxFireCounter); } -unsigned char Wb35Tx_initial(struct hw_data * pHwData) +unsigned char Wb35Tx_initial(struct hw_data *pHwData) { struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; @@ -136,62 +135,52 @@ unsigned char Wb35Tx_initial(struct hw_data * pHwData) return false; pWb35Tx->Tx2Urb = usb_alloc_urb(0, GFP_ATOMIC); - if (!pWb35Tx->Tx2Urb) - { - usb_free_urb( pWb35Tx->Tx4Urb ); + if (!pWb35Tx->Tx2Urb) { + usb_free_urb(pWb35Tx->Tx4Urb); return false; } return true; } -//====================================================== -void Wb35Tx_stop(struct hw_data * pHwData) +void Wb35Tx_stop(struct hw_data *pHwData) { struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; - // Trying to canceling the Trp of EP2 + /* Try to cancel the Trp of EP2 */ if (pWb35Tx->EP2vm_state == VM_RUNNING) - usb_unlink_urb( pWb35Tx->Tx2Urb ); // Only use unlink, let Wb35Tx_destrot to free them - #ifdef _PE_TX_DUMP_ - printk("EP2 Tx stop\n"); - #endif + /* Only use unlink, let Wb35Tx_destroy free them */ + usb_unlink_urb(pWb35Tx->Tx2Urb); + pr_debug("EP2 Tx stop\n"); - // Trying to canceling the Irp of EP4 + /* Try to cancel the Irp of EP4 */ if (pWb35Tx->EP4vm_state == VM_RUNNING) - usb_unlink_urb( pWb35Tx->Tx4Urb ); // Only use unlink, let Wb35Tx_destrot to free them - #ifdef _PE_TX_DUMP_ - printk("EP4 Tx stop\n"); - #endif + /* Only use unlink, let Wb35Tx_destroy free them */ + usb_unlink_urb(pWb35Tx->Tx4Urb); + pr_debug("EP4 Tx stop\n"); } -//====================================================== -void Wb35Tx_destroy(struct hw_data * pHwData) +void Wb35Tx_destroy(struct hw_data *pHwData) { struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; - // Wait for VM stop + /* Wait for VM stop */ do { - msleep(10); // Delay for waiting function enter 940623.1.a - } while( (pWb35Tx->EP2vm_state != VM_STOP) && (pWb35Tx->EP4vm_state != VM_STOP) ); - msleep(10); // Delay for waiting function enter 940623.1.b + msleep(10); /* Delay for waiting function enter 940623.1.a */ + } while ((pWb35Tx->EP2vm_state != VM_STOP) && (pWb35Tx->EP4vm_state != VM_STOP)); + msleep(10); /* Delay for waiting function enter 940623.1.b */ - if (pWb35Tx->Tx4Urb) - usb_free_urb( pWb35Tx->Tx4Urb ); + usb_free_urb(pWb35Tx->Tx4Urb); + usb_free_urb(pWb35Tx->Tx2Urb); - if (pWb35Tx->Tx2Urb) - usb_free_urb( pWb35Tx->Tx2Urb ); - - #ifdef _PE_TX_DUMP_ - printk("Wb35Tx_destroy OK\n"); - #endif + pr_debug("Wb35Tx_destroy OK\n"); } void Wb35Tx_CurrentTime(struct wbsoft_priv *adapter, u32 TimeCount) { - struct hw_data * pHwData = &adapter->sHwData; + struct hw_data *pHwData = &adapter->sHwData; struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; - unsigned char Trigger = false; + bool Trigger = false; if (pWb35Tx->TxTimer > TimeCount) Trigger = true; @@ -206,46 +195,45 @@ void Wb35Tx_CurrentTime(struct wbsoft_priv *adapter, u32 TimeCount) static void Wb35Tx_EP2VM(struct wbsoft_priv *adapter); -static void Wb35Tx_EP2VM_complete(struct urb * pUrb) +static void Wb35Tx_EP2VM_complete(struct urb *pUrb) { struct wbsoft_priv *adapter = pUrb->context; - struct hw_data * pHwData = &adapter->sHwData; - T02_DESCRIPTOR T02, TSTATUS; + struct hw_data *pHwData = &adapter->sHwData; + struct T02_descriptor T02, TSTATUS; struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; - u32 * pltmp = (u32 *)pWb35Tx->EP2_buf; + u32 *pltmp = (u32 *)pWb35Tx->EP2_buf; u32 i; u16 InterruptInLength; - - // Variable setting + /* Variable setting */ pWb35Tx->EP2vm_state = VM_COMPLETED; pWb35Tx->EP2VM_status = pUrb->status; - // For Linux 2.4. Interrupt will always trigger - if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove + /* For Linux 2.4. Interrupt will always trigger */ + if (pHwData->SurpriseRemove) /* Let WbWlanHalt handle surprise remove */ goto error; if (pWb35Tx->tx_halt) goto error; - //The Urb is completed, check the result + /* The Urb is completed, check the result */ if (pWb35Tx->EP2VM_status != 0) { - printk("EP2 IoCompleteRoutine return error\n"); - pWb35Tx->EP2vm_state= VM_STOP; + dev_err(&pUrb->dev->dev, "EP2 IoCompleteRoutine return error\n"); + pWb35Tx->EP2vm_state = VM_STOP; goto error; } - // Update the Tx result + /* Update the Tx result */ InterruptInLength = pUrb->actual_length; - // Modify for minimum memory access and DWORD alignment. - T02.value = cpu_to_le32(pltmp[0]) >> 8; // [31:8] -> [24:0] - InterruptInLength -= 1;// 20051221.1.c Modify the follow for more stable - InterruptInLength >>= 2; // InterruptInLength/4 + /* Modify for minimum memory access and DWORD alignment. */ + T02.value = cpu_to_le32(pltmp[0]) >> 8; /* [31:8] -> [24:0] */ + InterruptInLength -= 1; /* 20051221.1.c Modify the follow for more stable */ + InterruptInLength >>= 2; /* InterruptInLength/4 */ for (i = 1; i <= InterruptInLength; i++) { T02.value |= ((cpu_to_le32(pltmp[i]) & 0xff) << 24); - TSTATUS.value = T02.value; //20061009 anson's endian - Mds_SendComplete( adapter, &TSTATUS ); + TSTATUS.value = T02.value; /* 20061009 anson's endian */ + Mds_SendComplete(adapter, &TSTATUS); T02.value = cpu_to_le32(pltmp[i]) >> 8; } @@ -257,31 +245,28 @@ error: static void Wb35Tx_EP2VM(struct wbsoft_priv *adapter) { - struct hw_data * pHwData = &adapter->sHwData; + struct hw_data *pHwData = &adapter->sHwData; struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; - struct urb * pUrb = (struct urb *)pWb35Tx->Tx2Urb; - u32 * pltmp = (u32 *)pWb35Tx->EP2_buf; + struct urb *pUrb = (struct urb *)pWb35Tx->Tx2Urb; + u32 *pltmp = (u32 *)pWb35Tx->EP2_buf; int retv; - if (pHwData->SurpriseRemove || pHwData->HwStop) + if (pHwData->SurpriseRemove) goto error; if (pWb35Tx->tx_halt) goto error; - // - // Issuing URB - // - usb_fill_int_urb( pUrb, pHwData->WbUsb.udev, usb_rcvintpipe(pHwData->WbUsb.udev,2), - pltmp, MAX_INTERRUPT_LENGTH, Wb35Tx_EP2VM_complete, adapter, 32); + /* Issuing URB */ + usb_fill_int_urb(pUrb, pHwData->udev, usb_rcvintpipe(pHwData->udev, 2), + pltmp, MAX_INTERRUPT_LENGTH, Wb35Tx_EP2VM_complete, + adapter, 32); pWb35Tx->EP2vm_state = VM_RUNNING; retv = usb_submit_urb(pUrb, GFP_ATOMIC); if (retv < 0) { - #ifdef _PE_TX_DUMP_ - printk("EP2 Tx Irp sending error\n"); - #endif + pr_debug("EP2 Tx Irp sending error\n"); goto error; } @@ -293,14 +278,13 @@ error: void Wb35Tx_EP2VM_start(struct wbsoft_priv *adapter) { - struct hw_data * pHwData = &adapter->sHwData; + struct hw_data *pHwData = &adapter->sHwData; struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; - // Allow only one thread to run into function + /* Allow only one thread to run into function */ if (atomic_inc_return(&pWb35Tx->TxResultCount) == 1) { pWb35Tx->EP2vm_state = VM_RUNNING; Wb35Tx_EP2VM(adapter); - } - else + } else atomic_dec(&pWb35Tx->TxResultCount); } diff --git a/drivers/staging/winbond/wb35tx_f.h b/drivers/staging/winbond/wb35tx_f.h index 1d3b515f83b..018fd35e815 100644 --- a/drivers/staging/winbond/wb35tx_f.h +++ b/drivers/staging/winbond/wb35tx_f.h @@ -2,7 +2,6 @@ #define __WINBOND_WB35TX_F_H #include "core.h" -#include "wbhal_f.h" /* * ==================================== diff --git a/drivers/staging/winbond/wb35tx_s.h b/drivers/staging/winbond/wb35tx_s.h index f70f4339559..dc120085d52 100644 --- a/drivers/staging/winbond/wb35tx_s.h +++ b/drivers/staging/winbond/wb35tx_s.h @@ -3,45 +3,37 @@ #include "mds_s.h" -//==================================== -// IS89C35 Tx related definition -//==================================== -#define TX_INTERFACE 0 // Interface 1 -#define TX_PIPE 3 // endpoint 4 -#define TX_INTERRUPT 1 // endpoint 2 -#define MAX_INTERRUPT_LENGTH 64 // It must be 64 for EP2 hardware - - - -//==================================== -// Internal variable for module -//==================================== - +/* IS89C35 Tx related definition */ +#define TX_INTERFACE 0 /* Interface 1 */ +#define TX_PIPE 3 /* Endpoint 4 */ +#define TX_INTERRUPT 1 /* Endpoint 2 */ +#define MAX_INTERRUPT_LENGTH 64 /* It must be 64 for EP2 hardware */ +/* Internal variable for module */ struct wb35_tx { - // For Tx buffer - u8 TxBuffer[ MAX_USB_TX_BUFFER_NUMBER ][ MAX_USB_TX_BUFFER ]; + /* For Tx buffer */ + u8 TxBuffer[MAX_USB_TX_BUFFER_NUMBER][MAX_USB_TX_BUFFER]; - // For Interrupt pipe + /* For Interrupt pipe */ u8 EP2_buf[MAX_INTERRUPT_LENGTH]; - atomic_t TxResultCount;// For thread control of EP2 931130.4.m - atomic_t TxFireCounter;// For thread control of EP4 931130.4.n - u32 ByteTransfer; + atomic_t TxResultCount; /* For thread control of EP2 931130.4.m */ + atomic_t TxFireCounter; /* For thread control of EP4 931130.4.n */ + u32 ByteTransfer; - u32 TxSendIndex;// The next index of Mds array to be sent - u32 EP2vm_state; // for EP2vm state - u32 EP4vm_state; // for EP4vm state - u32 tx_halt; // Stopping VM + u32 TxSendIndex; /* The next index of Mds array to be sent */ + u32 EP2vm_state; /* for EP2vm state */ + u32 EP4vm_state; /* for EP4vm state */ + u32 tx_halt; /* Stopping VM */ - struct urb * Tx4Urb; - struct urb * Tx2Urb; + struct urb *Tx4Urb; + struct urb *Tx2Urb; int EP2VM_status; int EP4VM_status; - u32 TxFillCount; // 20060928 - u32 TxTimer; // 20060928 Add if sending packet not great than 13 + u32 TxFillCount; /* 20060928 */ + u32 TxTimer; /* 20060928 Add if sending packet is greater than 13 */ }; #endif diff --git a/drivers/staging/winbond/wbhal_s.h b/drivers/staging/winbond/wbhal.h index 33457c2e39b..289ee549146 100644 --- a/drivers/staging/winbond/wbhal_s.h +++ b/drivers/staging/winbond/wbhal.h @@ -105,7 +105,7 @@ enum { #define FLAG_BAND_RX_MASK 0x10000000 /* Bit 28 */ -typedef struct _R00_DESCRIPTOR { +struct R00_descriptor { union { u32 value; #ifdef _BIG_ENDIAN_ @@ -126,9 +126,9 @@ typedef struct _R00_DESCRIPTOR { }; #endif }; -} R00_DESCRIPTOR, *PR00_DESCRIPTOR; +}; -typedef struct _T00_DESCRIPTOR { +struct T00_descriptor { union { u32 value; #ifdef _BIG_ENDIAN_ @@ -157,9 +157,9 @@ typedef struct _T00_DESCRIPTOR { }; #endif }; -} T00_DESCRIPTOR, *PT00_DESCRIPTOR; +}; -typedef struct _R01_DESCRIPTOR { +struct R01_descriptor { union { u32 value; #ifdef _BIG_ENDIAN_ @@ -208,9 +208,9 @@ typedef struct _R01_DESCRIPTOR { }; #endif }; -} R01_DESCRIPTOR, *PR01_DESCRIPTOR; +}; -typedef struct _T01_DESCRIPTOR { +struct T01_descriptor { union { u32 value; #ifdef _BIG_ENDIAN_ @@ -226,11 +226,11 @@ typedef struct _T01_DESCRIPTOR { u32 T01_add_challenge_text:1; u32 T01_inhibit_crc:1; u32 T01_loop_back_wep_mode:1; - u32 T01_retry_abort_ebable:1; + u32 T01_retry_abort_enable:1; }; #else struct { - u32 T01_retry_abort_ebable:1; + u32 T01_retry_abort_enable:1; u32 T01_loop_back_wep_mode:1; u32 T01_inhibit_crc:1; u32 T01_add_challenge_text:1; @@ -245,9 +245,9 @@ typedef struct _T01_DESCRIPTOR { }; #endif }; -} T01_DESCRIPTOR, *PT01_DESCRIPTOR; +}; -typedef struct _T02_DESCRIPTOR { +struct T02_descriptor { union { u32 value; #ifdef _BIG_ENDIAN_ @@ -290,7 +290,7 @@ typedef struct _T02_DESCRIPTOR { }; #endif }; -} T02_DESCRIPTOR, *PT02_DESCRIPTOR; +}; struct wb35_descriptor { /* Skip length = 8 DWORD */ /* ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition */ @@ -309,20 +309,20 @@ struct wb35_descriptor { /* Skip length = 8 DWORD */ /* For R00 and T00 ------------------------------ */ union { - R00_DESCRIPTOR R00; - T00_DESCRIPTOR T00; + struct R00_descriptor R00; + struct T00_descriptor T00; }; /* For R01 and T01 ------------------------------ */ union { - R01_DESCRIPTOR R01; - T01_DESCRIPTOR T01; + struct R01_descriptor R01; + struct T01_descriptor T01; }; /* For R02 and T02 ------------------------------ */ union { u32 R02; - T02_DESCRIPTOR T02; + struct T02_descriptor T02; }; /* For R03 and T03 ------------------------------ */ @@ -342,17 +342,13 @@ struct wb35_descriptor { /* Skip length = 8 DWORD */ void *buffer_address[MAX_DESCRIPTOR_BUFFER_INDEX]; }; - -#define DEFAULT_NULL_PACKET_COUNT 180000 /* 180 seconds */ - #define MAX_TXVGA_EEPROM 9 /* How many word(u16) of EEPROM will be used for TxVGA */ #define MAX_RF_PARAMETER 32 -typedef struct _TXVGA_FOR_50 { +struct txvga_for_50 { u8 ChanNo; u8 TxVgaValue; -} TXVGA_FOR_50; - +}; /* * ============================================== @@ -360,7 +356,6 @@ typedef struct _TXVGA_FOR_50 { * ============================================== */ -#include "wbusb_s.h" #include "wb35reg_s.h" #include "wb35tx_s.h" #include "wb35rx_s.h" @@ -441,7 +436,7 @@ struct hw_data { * Variable for each module * ================================================== */ - struct wb_usb WbUsb; /* Need WbUsb.h */ + struct usb_device *udev; struct wb35_reg reg; /* Need Wb35Reg.h */ struct wb35_tx Wb35Tx; /* Need Wb35Tx.h */ struct wb35_rx Wb35Rx; /* Need Wb35Rx.h */ @@ -479,7 +474,7 @@ struct hw_data { u8 TxVgaSettingInEEPROM[(((MAX_TXVGA_EEPROM * 2) + 3) & ~0x03)]; /* For EEPROM value */ u8 TxVgaFor24[16]; /* Max is 14, 2 for alignment */ - TXVGA_FOR_50 TxVgaFor50[36]; /* 35 channels in 5G. 35x2 = 70 byte. 2 for alignments */ + struct txvga_for_50 TxVgaFor50[36]; /* 35 channels in 5G. 35x2 = 70 byte. 2 for alignments */ u16 Scan_Interval; u16 RESERVED6; @@ -511,16 +506,8 @@ struct hw_data { u32 RxByteCountLast; u32 TxByteCountLast; - atomic_t SurpriseRemoveCount; - /* For global timer */ u32 time_count; /* TICK_TIME_100ms 1 = 100ms */ - - /* For error recover */ - u32 HwStop; - - /* For avoid AP disconnect */ - u32 NullPacketCount; }; #endif diff --git a/drivers/staging/winbond/wbhal_f.h b/drivers/staging/winbond/wbhal_f.h deleted file mode 100644 index 401c024bead..00000000000 --- a/drivers/staging/winbond/wbhal_f.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * ===================================================================== - * Device related include - * ===================================================================== -*/ -#include "wb35reg_f.h" -#include "wb35tx_f.h" -#include "wb35rx_f.h" - -#include "core.h" - -/* ===================================================================== - * Function declaration - * ===================================================================== - */ -void hal_remove_mapping_key(struct hw_data *hw_data, u8 *mac_addr); -void hal_remove_default_key(struct hw_data *hw_data, u32 index); -unsigned char hal_set_mapping_key(struct hw_data *adapter, u8 *mac_addr, - u8 null_key, u8 wep_on, u8 *tx_tsc, - u8 *rx_tsc, u8 key_type, u8 key_len, - u8 *key_data); -unsigned char hal_set_default_key(struct hw_data *adapter, u8 index, - u8 null_key, u8 wep_on, u8 *tx_tsc, - u8 *rx_tsc, u8 key_type, u8 key_len, - u8 *key_data); -void hal_clear_all_default_key(struct hw_data *hw_data); -void hal_clear_all_group_key(struct hw_data *hw_data); -void hal_clear_all_mapping_key(struct hw_data *hw_data); -void hal_clear_all_key(struct hw_data *hw_data); -void hal_set_power_save_mode(struct hw_data *hw_data, unsigned char power_save, - unsigned char wakeup, unsigned char dtim); -void hal_get_power_save_mode(struct hw_data *hw_data, u8 *in_pwr_save); -void hal_set_slot_time(struct hw_data *hw_data, u8 type); - -#define hal_set_atim_window(_A, _ATM) - -void hal_start_bss(struct hw_data *hw_data, u8 mac_op_mode); - -/* 0:BSS STA 1:IBSS STA */ -void hal_join_request(struct hw_data *hw_data, u8 bss_type); - -void hal_stop_sync_bss(struct hw_data *hw_data); -void hal_resume_sync_bss(struct hw_data *hw_data); -void hal_set_aid(struct hw_data *hw_data, u16 aid); -void hal_set_bssid(struct hw_data *hw_data, u8 *bssid); -void hal_get_bssid(struct hw_data *hw_data, u8 *bssid); -void hal_set_listen_interval(struct hw_data *hw_data, u16 listen_interval); -void hal_set_cap_info(struct hw_data *hw_data, u16 capability_info); -void hal_set_ssid(struct hw_data *hw_data, u8 *ssid, u8 ssid_len); -void hal_start_tx0(struct hw_data *hw_data); - -#define hal_get_cwmin(_A) ((_A)->cwmin) - -void hal_set_cwmax(struct hw_data *hw_data, u16 cwin_max); - -#define hal_get_cwmax(_A) ((_A)->cwmax) - -void hal_set_rsn_wpa(struct hw_data *hw_data, u32 *rsn_ie_bitmap, - u32 *rsn_oui_type , unsigned char desired_auth_mode); -void hal_set_connect_info(struct hw_data *hw_data, unsigned char bo_connect); -u8 hal_get_est_sq3(struct hw_data *hw_data, u8 count); -void hal_descriptor_indicate(struct hw_data *hw_data, - struct wb35_descriptor *des); -u8 hal_get_antenna_number(struct hw_data *hw_data); -u32 hal_get_bss_pk_cnt(struct hw_data *hw_data); - -#define hal_get_region_from_EEPROM(_A) ((_A)->reg.EEPROMRegion) -#define hal_get_tx_buffer(_A, _B) Wb35Tx_get_tx_buffer(_A, _B) -#define hal_software_set(_A) (_A->SoftwareSet) -#define hal_driver_init_OK(_A) (_A->IsInitOK) -#define hal_rssi_boundary_high(_A) (_A->RSSI_high) -#define hal_rssi_boundary_low(_A) (_A->RSSI_low) -#define hal_scan_interval(_A) (_A->Scan_Interval) - -#define PHY_DEBUG(msg, args...) - -/* return 100ms count */ -#define hal_get_time_count(_P) (_P->time_count / 10) -#define hal_detect_error(_P) (_P->WbUsb.DetectCount) - -/* The follow function is unused for IS89C35 */ -#define hal_disable_interrupt(_A) -#define hal_enable_interrupt(_A) -#define hal_get_interrupt_type(_A) -#define hal_get_clear_interrupt(_A) -#define hal_ibss_disconnect(_A) (hal_stop_sync_bss(_A)) -#define hal_join_request_stop(_A) -#define hw_get_cxx_reg(_A, _B, _C) -#define hw_set_cxx_reg(_A, _B, _C) - - diff --git a/drivers/staging/winbond/wblinux_f.h b/drivers/staging/winbond/wblinux_f.h deleted file mode 100644 index 0a9d214f718..00000000000 --- a/drivers/staging/winbond/wblinux_f.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __WBLINUX_F_H -#define __WBLINUX_F_H - -#include "core.h" -#include "mds_s.h" - -/* - * ==================================================================== - * Copyright (c) 1996-2004 Winbond Electronic Corporation - * - * wblinux_f.h - * ==================================================================== - */ -int wb35_start_xmit(struct sk_buff *skb, struct net_device *netdev); -void wb35_set_multicast(struct net_device *netdev); -struct net_device_stats *wb35_netdev_stats(struct net_device *netdev); -#endif diff --git a/drivers/staging/winbond/wbusb.c b/drivers/staging/winbond/wbusb.c index 681419d6856..0d29624416c 100644 --- a/drivers/staging/winbond/wbusb.c +++ b/drivers/staging/winbond/wbusb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Pavel Machek <pavel@suse.cz> + * Copyright 2008 Pavel Machek <pavel@ucw.cz> * * Distribute under GPLv2. * @@ -11,19 +11,21 @@ */ #include <net/mac80211.h> #include <linux/usb.h> +#include <linux/module.h> #include "core.h" #include "mds_f.h" -#include "mlmetxrx_f.h" #include "mto.h" -#include "wbhal_f.h" -#include "wblinux_f.h" +#include "wbhal.h" +#include "wb35reg_f.h" +#include "wb35tx_f.h" +#include "wb35rx_f.h" MODULE_DESCRIPTION("IS89C35 802.11bg WLAN USB Driver"); MODULE_LICENSE("GPL"); MODULE_VERSION("0.1"); -static const struct usb_device_id wb35_table[] __devinitconst = { +static const struct usb_device_id wb35_table[] = { { USB_DEVICE(0x0416, 0x0035) }, { USB_DEVICE(0x18E8, 0x6201) }, { USB_DEVICE(0x18E8, 0x6206) }, @@ -77,18 +79,15 @@ static int wbsoft_add_interface(struct ieee80211_hw *dev, static void wbsoft_remove_interface(struct ieee80211_hw *dev, struct ieee80211_vif *vif) { - printk("wbsoft_remove interface called\n"); } static void wbsoft_stop(struct ieee80211_hw *hw) { - printk(KERN_INFO "%s called\n", __func__); } static int wbsoft_get_stats(struct ieee80211_hw *hw, struct ieee80211_low_level_stats *stats) { - printk(KERN_INFO "%s called\n", __func__); return 0; } @@ -117,13 +116,31 @@ static void wbsoft_configure_filter(struct ieee80211_hw *dev, *total_flags = new_flags; } -static int wbsoft_tx(struct ieee80211_hw *dev, struct sk_buff *skb) +static void wbsoft_tx(struct ieee80211_hw *dev, + struct ieee80211_tx_control *control, + struct sk_buff *skb) { struct wbsoft_priv *priv = dev->priv; - MLMESendFrame(priv, skb->data, skb->len, FRAME_TYPE_802_11_MANAGEMENT); + if (priv->sMlmeFrame.is_in_used != PACKET_FREE_TO_USE) { + priv->sMlmeFrame.wNumTxMMPDUDiscarded++; + kfree_skb(skb); + return; + } + + priv->sMlmeFrame.is_in_used = PACKET_COME_FROM_MLME; + + priv->sMlmeFrame.pMMPDU = skb->data; + priv->sMlmeFrame.data_type = FRAME_TYPE_802_11_MANAGEMENT; + priv->sMlmeFrame.len = skb->len; + priv->sMlmeFrame.wNumTxMMPDU++; + + /* + * H/W will enter power save by set the register. S/W don't send null + * frame with PWRMgt bit enbled to enter power save now. + */ - return NETDEV_TX_OK; + Mds_Tx(priv); } static int wbsoft_start(struct ieee80211_hw *dev) @@ -159,15 +176,9 @@ static void hal_set_current_channel_ex(struct hw_data *pHwData, struct chan_info if (pHwData->SurpriseRemove) return; - printk("Going to channel: %d/%d\n", channel.band, channel.ChanNo); - RFSynthesizer_SwitchingChannel(pHwData, channel); /* Switch channel */ pHwData->Channel = channel.ChanNo; pHwData->band = channel.band; -#ifdef _PE_STATE_DUMP_ - printk("Set channel is %d, band =%d\n", pHwData->Channel, - pHwData->band); -#endif reg->M28_MacControl &= ~0xff; /* Clean channel information field */ reg->M28_MacControl |= channel.ChanNo; Wb35Reg_WriteWithCallbackValue(pHwData, 0x0828, reg->M28_MacControl, @@ -247,8 +258,6 @@ static int wbsoft_config(struct ieee80211_hw *dev, u32 changed) struct wbsoft_priv *priv = dev->priv; struct chan_info ch; - printk("wbsoft_config called\n"); - /* Should use channel_num, or something, as that is already pre-translated */ ch.band = 1; ch.ChanNo = 1; @@ -263,9 +272,8 @@ static int wbsoft_config(struct ieee80211_hw *dev, u32 changed) return 0; } -static u64 wbsoft_get_tsf(struct ieee80211_hw *dev) +static u64 wbsoft_get_tsf(struct ieee80211_hw *dev, struct ieee80211_vif *vif) { - printk("wbsoft_get_tsf called\n"); return 0; } @@ -322,10 +330,8 @@ static void hal_stop(struct hw_data *pHwData) static unsigned char hal_idle(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; - struct wb_usb *pWbUsb = &pHwData->WbUsb; - if (!pHwData->SurpriseRemove - && (pWbUsb->DetectCount || reg->EP0vm_state != VM_STOP)) + if (!pHwData->SurpriseRemove && reg->EP0vm_state != VM_STOP) return false; return true; @@ -591,15 +597,6 @@ static void hal_led_control(unsigned long data) } break; } - - /* Active send null packet to avoid AP disconnect */ - if (pHwData->LED_LinkOn) { - pHwData->NullPacketCount += TimeInterval; - if (pHwData->NullPacketCount >= - DEFAULT_NULL_PACKET_COUNT) { - pHwData->NullPacketCount = 0; - } - } } pHwData->time_count += TimeInterval; @@ -634,13 +631,6 @@ static int hal_init_hardware(struct ieee80211_hw *hw) SoftwareSet = hal_software_set(pHwData); -#ifdef Vendor2 - /* Try to make sure the EEPROM contain */ - SoftwareSet >>= 8; - if (SoftwareSet != 0x82) - return false; -#endif - Wb35Rx_start(hw); Wb35Tx_EP2VM_start(priv); @@ -700,7 +690,7 @@ static int wb35_hw_init(struct ieee80211_hw *hw) Mds_initial(priv); /* - * If no user-defined address in the registry, use the addresss + * If no user-defined address in the registry, use the address * "burned" on the NIC instead. */ pMacAddr = priv->sLocalPara.ThisMacAddress; @@ -717,9 +707,6 @@ static int wb35_hw_init(struct ieee80211_hw *hw) } priv->sLocalPara.bAntennaNo = hal_get_antenna_number(pHwData); -#ifdef _PE_STATE_DUMP_ - printk("Driver init, antenna no = %d\n", psLOCAL->bAntennaNo); -#endif hal_get_hw_radio_off(pHwData); /* Waiting for HAL setting OK */ @@ -752,21 +739,18 @@ static int wb35_probe(struct usb_interface *intf, struct usb_host_interface *interface; struct ieee80211_hw *dev; struct wbsoft_priv *priv; - struct wb_usb *pWbUsb; - int nr, err; + int err; u32 ltmp; usb_get_dev(udev); /* Check the device if it already be opened */ - nr = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + err = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 0x01, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN, 0x0, 0x400, <mp, 4, HZ * 100); - if (nr < 0) { - err = nr; + if (err < 0) goto error; - } /* Is already initialized? */ ltmp = cpu_to_le32(ltmp); @@ -783,19 +767,11 @@ static int wb35_probe(struct usb_interface *intf, priv = dev->priv; - spin_lock_init(&priv->SpinLock); - - pWbUsb = &priv->sHwData.WbUsb; - pWbUsb->udev = udev; + priv->sHwData.udev = udev; interface = intf->cur_altsetting; endpoint = &interface->endpoint[0].desc; - if (endpoint[2].wMaxPacketSize == 512) { - printk("[w35und] Working on USB 2.0\n"); - pWbUsb->IsUsb20 = 1; - } - err = wb35_hw_init(dev); if (err) goto error_free_hw; @@ -812,7 +788,6 @@ static int wb35_probe(struct usb_interface *intf, dev->flags = IEEE80211_HW_SIGNAL_UNSPEC; dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); - dev->channel_change_time = 1000; dev->max_signal = 100; dev->queues = 1; @@ -845,13 +820,8 @@ static void hal_halt(struct hw_data *pHwData) static void wb35_hw_halt(struct wbsoft_priv *adapter) { - Mds_Destroy(adapter); - /* Turn off Rx and Tx hardware ability */ hal_stop(&adapter->sHwData); -#ifdef _PE_USB_INI_DUMP_ - printk("[w35und] Hal_stop O.K.\n"); -#endif /* Waiting Irp completed */ msleep(100); @@ -880,15 +850,4 @@ static struct usb_driver wb35_driver = { .disconnect = wb35_disconnect, }; -static int __init wb35_init(void) -{ - return usb_register(&wb35_driver); -} - -static void __exit wb35_exit(void) -{ - usb_deregister(&wb35_driver); -} - -module_init(wb35_init); -module_exit(wb35_exit); +module_usb_driver(wb35_driver); diff --git a/drivers/staging/winbond/wbusb_s.h b/drivers/staging/winbond/wbusb_s.h deleted file mode 100644 index 8961ae594c4..00000000000 --- a/drivers/staging/winbond/wbusb_s.h +++ /dev/null @@ -1,18 +0,0 @@ -/* ========================================================= - * Copyright (c) 1996-2004 Winbond Electronic Corporation - * - * Module Name: - * wbusb_s.h - * ========================================================= - */ -#ifndef __WINBOND_WBUSB_S_H -#define __WINBOND_WBUSB_S_H - -#include <linux/types.h> - -struct wb_usb { - u32 IsUsb20; - struct usb_device *udev; - u32 DetectCount; -}; -#endif |