diff options
Diffstat (limited to 'drivers/sh/clk')
| -rw-r--r-- | drivers/sh/clk/core.c | 20 | ||||
| -rw-r--r-- | drivers/sh/clk/cpg.c | 38 | 
2 files changed, 43 insertions, 15 deletions
diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c index 74727851820..be56b22ca94 100644 --- a/drivers/sh/clk/core.c +++ b/drivers/sh/clk/core.c @@ -196,17 +196,11 @@ int clk_rate_table_find(struct clk *clk,  			struct cpufreq_frequency_table *freq_table,  			unsigned long rate)  { -	int i; - -	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { -		unsigned long freq = freq_table[i].frequency; +	struct cpufreq_frequency_table *pos; -		if (freq == CPUFREQ_ENTRY_INVALID) -			continue; - -		if (freq == rate) -			return i; -	} +	cpufreq_for_each_valid_entry(pos, freq_table) +		if (pos->frequency == rate) +			return pos - freq_table;  	return -ENOENT;  } @@ -575,11 +569,7 @@ long clk_round_parent(struct clk *clk, unsigned long target,  		return abs(target - *best_freq);  	} -	for (freq = parent->freq_table; freq->frequency != CPUFREQ_TABLE_END; -	     freq++) { -		if (freq->frequency == CPUFREQ_ENTRY_INVALID) -			continue; - +	cpufreq_for_each_valid_entry(freq, parent->freq_table) {  		if (unlikely(freq->frequency / target <= div_min - 1)) {  			unsigned long freq_max; diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 1ebe67cd183..7442bc13005 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c @@ -36,9 +36,47 @@ static void sh_clk_write(int value, struct clk *clk)  		iowrite32(value, clk->mapped_reg);  } +static unsigned int r8(const void __iomem *addr) +{ +	return ioread8(addr); +} + +static unsigned int r16(const void __iomem *addr) +{ +	return ioread16(addr); +} + +static unsigned int r32(const void __iomem *addr) +{ +	return ioread32(addr); +} +  static int sh_clk_mstp_enable(struct clk *clk)  {  	sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); +	if (clk->status_reg) { +		unsigned int (*read)(const void __iomem *addr); +		int i; +		void __iomem *mapped_status = (phys_addr_t)clk->status_reg - +			(phys_addr_t)clk->enable_reg + clk->mapped_reg; + +		if (clk->flags & CLK_ENABLE_REG_8BIT) +			read = r8; +		else if (clk->flags & CLK_ENABLE_REG_16BIT) +			read = r16; +		else +			read = r32; + +		for (i = 1000; +		     (read(mapped_status) & (1 << clk->enable_bit)) && i; +		     i--) +			cpu_relax(); +		if (!i) { +			pr_err("cpg: failed to enable %p[%d]\n", +			       clk->enable_reg, clk->enable_bit); +			return -ETIMEDOUT; +		} +	}  	return 0;  }  | 
