diff options
Diffstat (limited to 'drivers/pwm')
32 files changed, 4897 insertions, 501 deletions
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index e513cd99817..4ad7b89a4cb 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -28,6 +28,10 @@ menuconfig PWM if PWM +config PWM_SYSFS + bool + default y if SYSFS + config PWM_AB8500 tristate "AB8500 PWM support" depends on AB8500_CORE && ARCH_U8500 @@ -37,6 +41,36 @@ config PWM_AB8500 To compile this driver as a module, choose M here: the module will be called pwm-ab8500. +config PWM_ATMEL + tristate "Atmel PWM support" + depends on ARCH_AT91 + help + Generic PWM framework driver for Atmel SoC. + + To compile this driver as a module, choose M here: the module + will be called pwm-atmel. + +config PWM_ATMEL_TCB + tristate "Atmel TC Block PWM support" + depends on ATMEL_TCLIB && OF + help + Generic PWM framework driver for Atmel Timer Counter Block. + + A Timer Counter Block provides 6 PWM devices grouped by 2. + Devices in a given group must have the same period. + + To compile this driver as a module, choose M here: the module + will be called pwm-atmel-tcb. + +config PWM_BCM_KONA + tristate "Kona PWM support" + depends on ARCH_BCM_MOBILE + help + Generic PWM framework driver for Broadcom Kona PWM block. + + To compile this driver as a module, choose M here: the module + will be called pwm-bcm-kona. + config PWM_BFIN tristate "Blackfin PWM support" depends on BFIN_GPTIMERS @@ -46,8 +80,36 @@ config PWM_BFIN To compile this driver as a module, choose M here: the module will be called pwm-bfin. +config PWM_CLPS711X + tristate "CLPS711X PWM support" + depends on ARCH_CLPS711X || COMPILE_TEST + help + Generic PWM framework driver for Cirrus Logic CLPS711X. + + To compile this driver as a module, choose M here: the module + will be called pwm-clps711x. + +config PWM_EP93XX + tristate "Cirrus Logic EP93xx PWM support" + depends on ARCH_EP93XX + help + Generic PWM framework driver for Cirrus Logic EP93xx. + + To compile this driver as a module, choose M here: the module + will be called pwm-ep93xx. + +config PWM_FSL_FTM + tristate "Freescale FlexTimer Module (FTM) PWM support" + depends on OF + help + Generic FTM PWM framework driver for Freescale VF610 and + Layerscape LS-1 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-fsl-ftm. + config PWM_IMX - tristate "i.MX pwm support" + tristate "i.MX PWM support" depends on ARCH_MXC help Generic PWM framework driver for i.MX. @@ -65,6 +127,16 @@ config PWM_JZ4740 To compile this driver as a module, choose M here: the module will be called pwm-jz4740. +config PWM_LP3943 + tristate "TI/National Semiconductor LP3943 PWM support" + depends on MFD_LP3943 + help + Generic PWM framework driver for LP3943 which supports two PWM + channels. + + To compile this driver as a module, choose M here: the module + will be called pwm-lp3943. + config PWM_LPC32XX tristate "LPC32XX PWM support" depends on ARCH_LPC32XX @@ -75,6 +147,16 @@ config PWM_LPC32XX To compile this driver as a module, choose M here: the module will be called pwm-lpc32xx. +config PWM_LPSS + tristate "Intel LPSS PWM support" + depends on ACPI + help + Generic PWM framework driver for Intel Low Power Subsystem PWM + controller. + + To compile this driver as a module, choose M here: the module + will be called pwm-lpss. + config PWM_MXS tristate "Freescale MXS PWM support" depends on ARCH_MXS && OF @@ -85,6 +167,16 @@ config PWM_MXS To compile this driver as a module, choose M here: the module will be called pwm-mxs. +config PWM_PCA9685 + tristate "NXP PCA9685 PWM driver" + depends on OF && I2C + select REGMAP_I2C + help + Generic PWM framework driver for NXP PCA9685 LED controller. + + To compile this driver as a module, choose M here: the module + will be called pwm-pca9685. + config PWM_PUV3 tristate "PKUnity NetBook-0916 PWM support" depends on ARCH_PUV3 @@ -103,8 +195,19 @@ config PWM_PXA To compile this driver as a module, choose M here: the module will be called pwm-pxa. +config PWM_RENESAS_TPU + tristate "Renesas TPU PWM support" + depends on ARCH_SHMOBILE || COMPILE_TEST + depends on HAS_IOMEM + help + This driver exposes the Timer Pulse Unit (TPU) PWM controller found + in Renesas chips through the PWM API. + + To compile this driver as a module, choose M here: the module + will be called pwm-renesas-tpu. + config PWM_SAMSUNG - tristate "Samsung pwm support" + tristate "Samsung PWM support" depends on PLAT_SAMSUNG help Generic PWM framework driver for Samsung. @@ -135,8 +238,7 @@ config PWM_TEGRA config PWM_TIECAP tristate "ECAP PWM support" - depends on SOC_AM33XX - select PWM_TIPWMSS + depends on SOC_AM33XX || ARCH_DAVINCI_DA8XX help PWM driver support for the ECAP APWM controller found on AM33XX TI SOC @@ -146,8 +248,7 @@ config PWM_TIECAP config PWM_TIEHRPWM tristate "EHRPWM PWM support" - depends on SOC_AM33XX - select PWM_TIPWMSS + depends on SOC_AM33XX || ARCH_DAVINCI_DA8XX help PWM driver support for the EHRPWM controller found on AM33XX TI SOC @@ -157,7 +258,7 @@ config PWM_TIEHRPWM config PWM_TIPWMSS bool - depends on SOC_AM33XX && (PWM_TIEHRPWM || PWM_TIECAP) + default y if SOC_AM33XX && (PWM_TIECAP || PWM_TIEHRPWM) help PWM Subsystem driver support for AM33xx SOC. @@ -183,7 +284,7 @@ config PWM_TWL_LED will be called pwm-twl-led. config PWM_VT8500 - tristate "vt8500 pwm support" + tristate "vt8500 PWM support" depends on ARCH_VT8500 help Generic PWM framework driver for vt8500. diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 62a2963cfe5..5c86a19d5d3 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -1,12 +1,23 @@ obj-$(CONFIG_PWM) += core.o +obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o +obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o +obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o +obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o +obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o +obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o +obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o +obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o +obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o obj-$(CONFIG_PWM_MXS) += pwm-mxs.o +obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o +obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 903138b1884..4b66bf09ee5 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -30,10 +30,9 @@ #include <linux/debugfs.h> #include <linux/seq_file.h> -#define MAX_PWMS 1024 +#include <dt-bindings/pwm/pwm.h> -/* flags in the third cell of the DT PWM specifier */ -#define PWM_SPEC_POLARITY (1 << 0) +#define MAX_PWMS 1024 static DEFINE_MUTEX(pwm_lookup_lock); static LIST_HEAD(pwm_lookup_list); @@ -149,7 +148,7 @@ of_pwm_xlate_with_flags(struct pwm_chip *pc, const struct of_phandle_args *args) pwm_set_period(pwm, args->args[1]); - if (args->args[2] & PWM_SPEC_POLARITY) + if (args->args[2] & PWM_POLARITY_INVERTED) pwm_set_polarity(pwm, PWM_POLARITY_INVERSED); else pwm_set_polarity(pwm, PWM_POLARITY_NORMAL); @@ -211,6 +210,7 @@ int pwm_set_chip_data(struct pwm_device *pwm, void *data) return 0; } +EXPORT_SYMBOL_GPL(pwm_set_chip_data); /** * pwm_get_chip_data() - get private chip data for a PWM @@ -220,6 +220,7 @@ void *pwm_get_chip_data(struct pwm_device *pwm) { return pwm ? pwm->chip_data : NULL; } +EXPORT_SYMBOL_GPL(pwm_get_chip_data); /** * pwmchip_add() - register a new PWM chip @@ -272,6 +273,8 @@ int pwmchip_add(struct pwm_chip *chip) if (IS_ENABLED(CONFIG_OF)) of_pwmchip_add(chip); + pwmchip_sysfs_export(chip); + out: mutex_unlock(&pwm_lock); return ret; @@ -308,6 +311,8 @@ int pwmchip_remove(struct pwm_chip *chip) free_pwms(chip); + pwmchip_sysfs_unexport(chip); + out: mutex_unlock(&pwm_lock); return ret; @@ -400,10 +405,19 @@ EXPORT_SYMBOL_GPL(pwm_free); */ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { + int err; + if (!pwm || duty_ns < 0 || period_ns <= 0 || duty_ns > period_ns) return -EINVAL; - return pwm->chip->ops->config(pwm->chip, pwm, duty_ns, period_ns); + err = pwm->chip->ops->config(pwm->chip, pwm, duty_ns, period_ns); + if (err) + return err; + + pwm->duty_cycle = duty_ns; + pwm->period = period_ns; + + return 0; } EXPORT_SYMBOL_GPL(pwm_config); @@ -416,6 +430,8 @@ EXPORT_SYMBOL_GPL(pwm_config); */ int pwm_set_polarity(struct pwm_device *pwm, enum pwm_polarity polarity) { + int err; + if (!pwm || !pwm->chip->ops) return -EINVAL; @@ -425,7 +441,13 @@ int pwm_set_polarity(struct pwm_device *pwm, enum pwm_polarity polarity) if (test_bit(PWMF_ENABLED, &pwm->flags)) return -EBUSY; - return pwm->chip->ops->set_polarity(pwm->chip, pwm, polarity); + err = pwm->chip->ops->set_polarity(pwm->chip, pwm, polarity); + if (err) + return err; + + pwm->polarity = polarity; + + return 0; } EXPORT_SYMBOL_GPL(pwm_set_polarity); @@ -471,7 +493,7 @@ static struct pwm_chip *of_node_to_pwmchip(struct device_node *np) } /** - * of_pwm_request() - request a PWM via the PWM framework + * of_pwm_get() - request a PWM via the PWM framework * @np: device node to get the PWM from * @con_id: consumer name * @@ -486,8 +508,7 @@ static struct pwm_chip *of_node_to_pwmchip(struct device_node *np) * becomes mandatory for devices that look up the PWM device via the con_id * parameter. */ -static struct pwm_device *of_pwm_request(struct device_node *np, - const char *con_id) +struct pwm_device *of_pwm_get(struct device_node *np, const char *con_id) { struct pwm_device *pwm = NULL; struct of_phandle_args args; @@ -545,6 +566,7 @@ put: return pwm; } +EXPORT_SYMBOL_GPL(of_pwm_get); /** * pwm_add_table() - register PWM device consumers @@ -587,7 +609,7 @@ struct pwm_device *pwm_get(struct device *dev, const char *con_id) /* look up via DT first */ if (IS_ENABLED(CONFIG_OF) && dev && dev->of_node) - return of_pwm_request(dev->of_node, con_id); + return of_pwm_get(dev->of_node, con_id); /* * We look up the provider in the static table typically provided by @@ -639,10 +661,16 @@ struct pwm_device *pwm_get(struct device *dev, const char *con_id) } } + mutex_unlock(&pwm_lookup_lock); + if (chip) pwm = pwm_request_from_chip(chip, index, con_id ?: dev_id); + if (IS_ERR(pwm)) + return pwm; + + pwm_set_period(pwm, p->period); + pwm_set_polarity(pwm, p->polarity); - mutex_unlock(&pwm_lookup_lock); return pwm; } @@ -692,7 +720,7 @@ struct pwm_device *devm_pwm_get(struct device *dev, const char *con_id) { struct pwm_device **ptr, *pwm; - ptr = devres_alloc(devm_pwm_release, sizeof(**ptr), GFP_KERNEL); + ptr = devres_alloc(devm_pwm_release, sizeof(*ptr), GFP_KERNEL); if (!ptr) return ERR_PTR(-ENOMEM); @@ -708,6 +736,36 @@ struct pwm_device *devm_pwm_get(struct device *dev, const char *con_id) } EXPORT_SYMBOL_GPL(devm_pwm_get); +/** + * devm_of_pwm_get() - resource managed of_pwm_get() + * @dev: device for PWM consumer + * @np: device node to get the PWM from + * @con_id: consumer name + * + * This function performs like of_pwm_get() but the acquired PWM device will + * automatically be released on driver detach. + */ +struct pwm_device *devm_of_pwm_get(struct device *dev, struct device_node *np, + const char *con_id) +{ + struct pwm_device **ptr, *pwm; + + ptr = devres_alloc(devm_pwm_release, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + pwm = of_pwm_get(np, con_id); + if (!IS_ERR(pwm)) { + *ptr = pwm; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return pwm; +} +EXPORT_SYMBOL_GPL(devm_of_pwm_get); + static int devm_pwm_match(struct device *dev, void *res, void *data) { struct pwm_device **p = res; @@ -733,6 +791,18 @@ void devm_pwm_put(struct device *dev, struct pwm_device *pwm) } EXPORT_SYMBOL_GPL(devm_pwm_put); +/** + * pwm_can_sleep() - report whether PWM access will sleep + * @pwm: PWM device + * + * It returns true if accessing the PWM can sleep, false otherwise. + */ +bool pwm_can_sleep(struct pwm_device *pwm) +{ + return pwm->chip->can_sleep; +} +EXPORT_SYMBOL_GPL(pwm_can_sleep); + #ifdef CONFIG_DEBUG_FS static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s) { @@ -744,12 +814,12 @@ static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s) seq_printf(s, " pwm-%-3d (%-20.20s):", i, pwm->label); if (test_bit(PWMF_REQUESTED, &pwm->flags)) - seq_printf(s, " requested"); + seq_puts(s, " requested"); if (test_bit(PWMF_ENABLED, &pwm->flags)) - seq_printf(s, " enabled"); + seq_puts(s, " enabled"); - seq_printf(s, "\n"); + seq_puts(s, "\n"); } } diff --git a/drivers/pwm/pwm-ab8500.c b/drivers/pwm/pwm-ab8500.c index 4248d041827..4c07a8420b3 100644 --- a/drivers/pwm/pwm-ab8500.c +++ b/drivers/pwm/pwm-ab8500.c @@ -20,10 +20,6 @@ #define AB8500_PWM_OUT_CTRL2_REG 0x61 #define AB8500_PWM_OUT_CTRL7_REG 0x66 -/* backlight driver constants */ -#define ENABLE_PWM 1 -#define DISABLE_PWM 0 - struct ab8500_pwm_chip { struct pwm_chip chip; }; @@ -64,9 +60,9 @@ static int ab8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) ret = abx500_mask_and_set_register_interruptible(chip->dev, AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, - 1 << (chip->base - 1), ENABLE_PWM); + 1 << (chip->base - 1), 1 << (chip->base - 1)); if (ret < 0) - dev_err(chip->dev, "%s: Failed to disable PWM, Error %d\n", + dev_err(chip->dev, "%s: Failed to enable PWM, Error %d\n", pwm->label, ret); return ret; } @@ -77,17 +73,17 @@ static void ab8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ret = abx500_mask_and_set_register_interruptible(chip->dev, AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, - 1 << (chip->base - 1), DISABLE_PWM); + 1 << (chip->base - 1), 0); if (ret < 0) dev_err(chip->dev, "%s: Failed to disable PWM, Error %d\n", pwm->label, ret); - return; } static const struct pwm_ops ab8500_pwm_ops = { .config = ab8500_pwm_config, .enable = ab8500_pwm_enable, .disable = ab8500_pwm_disable, + .owner = THIS_MODULE, }; static int ab8500_pwm_probe(struct platform_device *pdev) @@ -99,11 +95,9 @@ static int ab8500_pwm_probe(struct platform_device *pdev) * Nothing to be done in probe, this is required to get the * device which is required for ab8500 read and write */ - ab8500 = kzalloc(sizeof(*ab8500), GFP_KERNEL); - if (ab8500 == NULL) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL); + if (ab8500 == NULL) return -ENOMEM; - } ab8500->chip.dev = &pdev->dev; ab8500->chip.ops = &ab8500_pwm_ops; @@ -111,10 +105,8 @@ static int ab8500_pwm_probe(struct platform_device *pdev) ab8500->chip.npwm = 1; err = pwmchip_add(&ab8500->chip); - if (err < 0) { - kfree(ab8500); + if (err < 0) return err; - } dev_dbg(&pdev->dev, "pwm probe successful\n"); platform_set_drvdata(pdev, ab8500); @@ -132,7 +124,6 @@ static int ab8500_pwm_remove(struct platform_device *pdev) return err; dev_dbg(&pdev->dev, "pwm driver removed\n"); - kfree(ab8500); return 0; } diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c new file mode 100644 index 00000000000..f3dcd02390f --- /dev/null +++ b/drivers/pwm/pwm-atmel-tcb.c @@ -0,0 +1,449 @@ +/* + * Copyright (C) Overkiz SAS 2012 + * + * Author: Boris BREZILLON <b.brezillon@overkiz.com> + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/irq.h> + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/ioport.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/atmel_tc.h> +#include <linux/pwm.h> +#include <linux/of_device.h> +#include <linux/slab.h> + +#define NPWM 6 + +#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \ + ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG) + +#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \ + ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG) + +struct atmel_tcb_pwm_device { + enum pwm_polarity polarity; /* PWM polarity */ + unsigned div; /* PWM clock divider */ + unsigned duty; /* PWM duty expressed in clk cycles */ + unsigned period; /* PWM period expressed in clk cycles */ +}; + +struct atmel_tcb_pwm_chip { + struct pwm_chip chip; + spinlock_t lock; + struct atmel_tc *tc; + struct atmel_tcb_pwm_device *pwms[NPWM]; +}; + +static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct atmel_tcb_pwm_chip, chip); +} + +static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + + tcbpwm->polarity = polarity; + + return 0; +} + +static int atmel_tcb_pwm_request(struct pwm_chip *chip, + struct pwm_device *pwm) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm; + struct atmel_tc *tc = tcbpwmc->tc; + void __iomem *regs = tc->regs; + unsigned group = pwm->hwpwm / 2; + unsigned index = pwm->hwpwm % 2; + unsigned cmr; + int ret; + + tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL); + if (!tcbpwm) + return -ENOMEM; + + ret = clk_prepare_enable(tc->clk[group]); + if (ret) { + devm_kfree(chip->dev, tcbpwm); + return ret; + } + + pwm_set_chip_data(pwm, tcbpwm); + tcbpwm->polarity = PWM_POLARITY_NORMAL; + tcbpwm->duty = 0; + tcbpwm->period = 0; + tcbpwm->div = 0; + + spin_lock(&tcbpwmc->lock); + cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); + /* + * Get init config from Timer Counter registers if + * Timer Counter is already configured as a PWM generator. + */ + if (cmr & ATMEL_TC_WAVE) { + if (index == 0) + tcbpwm->duty = + __raw_readl(regs + ATMEL_TC_REG(group, RA)); + else + tcbpwm->duty = + __raw_readl(regs + ATMEL_TC_REG(group, RB)); + + tcbpwm->div = cmr & ATMEL_TC_TCCLKS; + tcbpwm->period = __raw_readl(regs + ATMEL_TC_REG(group, RC)); + cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK | + ATMEL_TC_BCMR_MASK); + } else + cmr = 0; + + cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0; + __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR)); + spin_unlock(&tcbpwmc->lock); + + tcbpwmc->pwms[pwm->hwpwm] = tcbpwm; + + return 0; +} + +static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + struct atmel_tc *tc = tcbpwmc->tc; + + clk_disable_unprepare(tc->clk[pwm->hwpwm / 2]); + tcbpwmc->pwms[pwm->hwpwm] = NULL; + devm_kfree(chip->dev, tcbpwm); +} + +static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + struct atmel_tc *tc = tcbpwmc->tc; + void __iomem *regs = tc->regs; + unsigned group = pwm->hwpwm / 2; + unsigned index = pwm->hwpwm % 2; + unsigned cmr; + enum pwm_polarity polarity = tcbpwm->polarity; + + /* + * If duty is 0 the timer will be stopped and we have to + * configure the output correctly on software trigger: + * - set output to high if PWM_POLARITY_INVERSED + * - set output to low if PWM_POLARITY_NORMAL + * + * This is why we're reverting polarity in this case. + */ + if (tcbpwm->duty == 0) + polarity = !polarity; + + spin_lock(&tcbpwmc->lock); + cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); + + /* flush old setting and set the new one */ + if (index == 0) { + cmr &= ~ATMEL_TC_ACMR_MASK; + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_ASWTRG_CLEAR; + else + cmr |= ATMEL_TC_ASWTRG_SET; + } else { + cmr &= ~ATMEL_TC_BCMR_MASK; + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_BSWTRG_CLEAR; + else + cmr |= ATMEL_TC_BSWTRG_SET; + } + + __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR)); + + /* + * Use software trigger to apply the new setting. + * If both PWM devices in this group are disabled we stop the clock. + */ + if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) + __raw_writel(ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS, + regs + ATMEL_TC_REG(group, CCR)); + else + __raw_writel(ATMEL_TC_SWTRG, regs + + ATMEL_TC_REG(group, CCR)); + + spin_unlock(&tcbpwmc->lock); +} + +static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + struct atmel_tc *tc = tcbpwmc->tc; + void __iomem *regs = tc->regs; + unsigned group = pwm->hwpwm / 2; + unsigned index = pwm->hwpwm % 2; + u32 cmr; + enum pwm_polarity polarity = tcbpwm->polarity; + + /* + * If duty is 0 the timer will be stopped and we have to + * configure the output correctly on software trigger: + * - set output to high if PWM_POLARITY_INVERSED + * - set output to low if PWM_POLARITY_NORMAL + * + * This is why we're reverting polarity in this case. + */ + if (tcbpwm->duty == 0) + polarity = !polarity; + + spin_lock(&tcbpwmc->lock); + cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); + + /* flush old setting and set the new one */ + cmr &= ~ATMEL_TC_TCCLKS; + + if (index == 0) { + cmr &= ~ATMEL_TC_ACMR_MASK; + + /* Set CMR flags according to given polarity */ + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_ASWTRG_CLEAR; + else + cmr |= ATMEL_TC_ASWTRG_SET; + } else { + cmr &= ~ATMEL_TC_BCMR_MASK; + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_BSWTRG_CLEAR; + else + cmr |= ATMEL_TC_BSWTRG_SET; + } + + /* + * If duty is 0 or equal to period there's no need to register + * a specific action on RA/RB and RC compare. + * The output will be configured on software trigger and keep + * this config till next config call. + */ + if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) { + if (index == 0) { + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR; + else + cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET; + } else { + if (polarity == PWM_POLARITY_INVERSED) + cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR; + else + cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET; + } + } + + cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS); + + __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR)); + + if (index == 0) + __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RA)); + else + __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RB)); + + __raw_writel(tcbpwm->period, regs + ATMEL_TC_REG(group, RC)); + + /* Use software trigger to apply the new setting */ + __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, + regs + ATMEL_TC_REG(group, CCR)); + spin_unlock(&tcbpwmc->lock); + return 0; +} + +static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); + struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm); + unsigned group = pwm->hwpwm / 2; + unsigned index = pwm->hwpwm % 2; + struct atmel_tcb_pwm_device *atcbpwm = NULL; + struct atmel_tc *tc = tcbpwmc->tc; + int i; + int slowclk = 0; + unsigned period; + unsigned duty; + unsigned rate = clk_get_rate(tc->clk[group]); + unsigned long long min; + unsigned long long max; + + /* + * Find best clk divisor: + * the smallest divisor which can fulfill the period_ns requirements. + */ + for (i = 0; i < 5; ++i) { + if (atmel_tc_divisors[i] == 0) { + slowclk = i; + continue; + } + min = div_u64((u64)NSEC_PER_SEC * atmel_tc_divisors[i], rate); + max = min << tc->tcb_config->counter_width; + if (max >= period_ns) + break; + } + + /* + * If none of the divisor are small enough to represent period_ns + * take slow clock (32KHz). + */ + if (i == 5) { + i = slowclk; + rate = 32768; + min = div_u64(NSEC_PER_SEC, rate); + max = min << tc->tcb_config->counter_width; + + /* If period is too big return ERANGE error */ + if (max < period_ns) + return -ERANGE; + } + + duty = div_u64(duty_ns, min); + period = div_u64(period_ns, min); + + if (index == 0) + atcbpwm = tcbpwmc->pwms[pwm->hwpwm + 1]; + else + atcbpwm = tcbpwmc->pwms[pwm->hwpwm - 1]; + + /* + * PWM devices provided by TCB driver are grouped by 2: + * - group 0: PWM 0 & 1 + * - group 1: PWM 2 & 3 + * - group 2: PWM 4 & 5 + * + * PWM devices in a given group must be configured with the + * same period_ns. + * + * We're checking the period value of the second PWM device + * in this group before applying the new config. + */ + if ((atcbpwm && atcbpwm->duty > 0 && + atcbpwm->duty != atcbpwm->period) && + (atcbpwm->div != i || atcbpwm->period != period)) { + dev_err(chip->dev, + "failed to configure period_ns: PWM group already configured with a different value\n"); + return -EINVAL; + } + + tcbpwm->period = period; + tcbpwm->div = i; + tcbpwm->duty = duty; + + /* If the PWM is enabled, call enable to apply the new conf */ + if (test_bit(PWMF_ENABLED, &pwm->flags)) + atmel_tcb_pwm_enable(chip, pwm); + + return 0; +} + +static const struct pwm_ops atmel_tcb_pwm_ops = { + .request = atmel_tcb_pwm_request, + .free = atmel_tcb_pwm_free, + .config = atmel_tcb_pwm_config, + .set_polarity = atmel_tcb_pwm_set_polarity, + .enable = atmel_tcb_pwm_enable, + .disable = atmel_tcb_pwm_disable, + .owner = THIS_MODULE, +}; + +static int atmel_tcb_pwm_probe(struct platform_device *pdev) +{ + struct atmel_tcb_pwm_chip *tcbpwm; + struct device_node *np = pdev->dev.of_node; + struct atmel_tc *tc; + int err; + int tcblock; + + err = of_property_read_u32(np, "tc-block", &tcblock); + if (err < 0) { + dev_err(&pdev->dev, + "failed to get Timer Counter Block number from device tree (error: %d)\n", + err); + return err; + } + + tc = atmel_tc_alloc(tcblock, "tcb-pwm"); + if (tc == NULL) { + dev_err(&pdev->dev, "failed to allocate Timer Counter Block\n"); + return -ENOMEM; + } + + tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL); + if (tcbpwm == NULL) { + atmel_tc_free(tc); + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + tcbpwm->chip.dev = &pdev->dev; + tcbpwm->chip.ops = &atmel_tcb_pwm_ops; + tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags; + tcbpwm->chip.of_pwm_n_cells = 3; + tcbpwm->chip.base = -1; + tcbpwm->chip.npwm = NPWM; + tcbpwm->tc = tc; + + spin_lock_init(&tcbpwm->lock); + + err = pwmchip_add(&tcbpwm->chip); + if (err < 0) { + atmel_tc_free(tc); + return err; + } + + platform_set_drvdata(pdev, tcbpwm); + + return 0; +} + +static int atmel_tcb_pwm_remove(struct platform_device *pdev) +{ + struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev); + int err; + + err = pwmchip_remove(&tcbpwm->chip); + if (err < 0) + return err; + + atmel_tc_free(tcbpwm->tc); + + return 0; +} + +static const struct of_device_id atmel_tcb_pwm_dt_ids[] = { + { .compatible = "atmel,tcb-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids); + +static struct platform_driver atmel_tcb_pwm_driver = { + .driver = { + .name = "atmel-tcb-pwm", + .owner = THIS_MODULE, + .of_match_table = atmel_tcb_pwm_dt_ids, + }, + .probe = atmel_tcb_pwm_probe, + .remove = atmel_tcb_pwm_remove, +}; +module_platform_driver(atmel_tcb_pwm_driver); + +MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>"); +MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c new file mode 100644 index 00000000000..6e700a541ca --- /dev/null +++ b/drivers/pwm/pwm-atmel.c @@ -0,0 +1,401 @@ +/* + * Driver for Atmel Pulse Width Modulation Controller + * + * Copyright (C) 2013 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * Licensed under GPLv2. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/slab.h> + +/* The following is global registers for PWM controller */ +#define PWM_ENA 0x04 +#define PWM_DIS 0x08 +#define PWM_SR 0x0C +/* Bit field in SR */ +#define PWM_SR_ALL_CH_ON 0x0F + +/* The following register is PWM channel related registers */ +#define PWM_CH_REG_OFFSET 0x200 +#define PWM_CH_REG_SIZE 0x20 + +#define PWM_CMR 0x0 +/* Bit field in CMR */ +#define PWM_CMR_CPOL (1 << 9) +#define PWM_CMR_UPD_CDTY (1 << 10) +#define PWM_CMR_CPRE_MSK 0xF + +/* The following registers for PWM v1 */ +#define PWMV1_CDTY 0x04 +#define PWMV1_CPRD 0x08 +#define PWMV1_CUPD 0x10 + +/* The following registers for PWM v2 */ +#define PWMV2_CDTY 0x04 +#define PWMV2_CDTYUPD 0x08 +#define PWMV2_CPRD 0x0C +#define PWMV2_CPRDUPD 0x10 + +/* + * Max value for duty and period + * + * Although the duty and period register is 32 bit, + * however only the LSB 16 bits are significant. + */ +#define PWM_MAX_DTY 0xFFFF +#define PWM_MAX_PRD 0xFFFF +#define PRD_MAX_PRES 10 + +struct atmel_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; + + void (*config)(struct pwm_chip *chip, struct pwm_device *pwm, + unsigned long dty, unsigned long prd); +}; + +static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct atmel_pwm_chip, chip); +} + +static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip, + unsigned long offset) +{ + return readl_relaxed(chip->base + offset); +} + +static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip, + unsigned long offset, unsigned long val) +{ + writel_relaxed(val, chip->base + offset); +} + +static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip, + unsigned int ch, unsigned long offset) +{ + unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; + + return readl_relaxed(chip->base + base + offset); +} + +static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip, + unsigned int ch, unsigned long offset, + unsigned long val) +{ + unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; + + writel_relaxed(val, chip->base + base + offset); +} + +static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); + unsigned long clk_rate, prd, dty; + unsigned long long div; + unsigned int pres = 0; + u32 val; + int ret; + + if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) { + dev_err(chip->dev, "cannot change PWM period while enabled\n"); + return -EBUSY; + } + + clk_rate = clk_get_rate(atmel_pwm->clk); + div = clk_rate; + + /* Calculate the period cycles */ + while (div > PWM_MAX_PRD) { + div = clk_rate / (1 << pres); + div = div * period_ns; + /* 1/Hz = 100000000 ns */ + do_div(div, 1000000000); + + if (pres++ > PRD_MAX_PRES) { + dev_err(chip->dev, "pres exceeds the maximum value\n"); + return -EINVAL; + } + } + + /* Calculate the duty cycles */ + prd = div; + div *= duty_ns; + do_div(div, period_ns); + dty = prd - div; + + ret = clk_enable(atmel_pwm->clk); + if (ret) { + dev_err(chip->dev, "failed to enable PWM clock\n"); + return ret; + } + + /* It is necessary to preserve CPOL, inside CMR */ + val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); + val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); + atmel_pwm->config(chip, pwm, dty, prd); + + clk_disable(atmel_pwm->clk); + return ret; +} + +static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm, + unsigned long dty, unsigned long prd) +{ + struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); + unsigned int val; + + if (test_bit(PWMF_ENABLED, &pwm->flags)) { + /* + * If the PWM channel is enabled, using the update register, + * it needs to set bit 10 of CMR to 0 + */ + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty); + + val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); + val &= ~PWM_CMR_UPD_CDTY; + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); + } else { + /* + * If the PWM channel is disabled, write value to duty and + * period registers directly. + */ + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty); + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd); + } +} + +static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm, + unsigned long dty, unsigned long prd) +{ + struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); + + if (test_bit(PWMF_ENABLED, &pwm->flags)) { + /* + * If the PWM channel is enabled, using the duty update register + * to update the value. + */ + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTYUPD, dty); + } else { + /* + * If the PWM channel is disabled, write value to duty and + * period registers directly. + */ + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTY, dty); + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CPRD, prd); + } +} + +static int atmel_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); + u32 val; + int ret; + + val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); + + if (polarity == PWM_POLARITY_NORMAL) + val &= ~PWM_CMR_CPOL; + else + val |= PWM_CMR_CPOL; + + ret = clk_enable(atmel_pwm->clk); + if (ret) { + dev_err(chip->dev, "failed to enable PWM clock\n"); + return ret; + } + + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); + + clk_disable(atmel_pwm->clk); + + return 0; +} + +static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); + int ret; + + ret = clk_enable(atmel_pwm->clk); + if (ret) { + dev_err(chip->dev, "failed to enable PWM clock\n"); + return ret; + } + + atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm); + + return 0; +} + +static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); + + atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); + + clk_disable(atmel_pwm->clk); +} + +static const struct pwm_ops atmel_pwm_ops = { + .config = atmel_pwm_config, + .set_polarity = atmel_pwm_set_polarity, + .enable = atmel_pwm_enable, + .disable = atmel_pwm_disable, + .owner = THIS_MODULE, +}; + +struct atmel_pwm_data { + void (*config)(struct pwm_chip *chip, struct pwm_device *pwm, + unsigned long dty, unsigned long prd); +}; + +static const struct atmel_pwm_data atmel_pwm_data_v1 = { + .config = atmel_pwm_config_v1, +}; + +static const struct atmel_pwm_data atmel_pwm_data_v2 = { + .config = atmel_pwm_config_v2, +}; + +static const struct platform_device_id atmel_pwm_devtypes[] = { + { + .name = "at91sam9rl-pwm", + .driver_data = (kernel_ulong_t)&atmel_pwm_data_v1, + }, { + .name = "sama5d3-pwm", + .driver_data = (kernel_ulong_t)&atmel_pwm_data_v2, + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes); + +static const struct of_device_id atmel_pwm_dt_ids[] = { + { + .compatible = "atmel,at91sam9rl-pwm", + .data = &atmel_pwm_data_v1, + }, { + .compatible = "atmel,sama5d3-pwm", + .data = &atmel_pwm_data_v2, + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids); + +static inline const struct atmel_pwm_data * +atmel_pwm_get_driver_data(struct platform_device *pdev) +{ + if (pdev->dev.of_node) { + const struct of_device_id *match; + + match = of_match_device(atmel_pwm_dt_ids, &pdev->dev); + if (!match) + return NULL; + + return match->data; + } else { + const struct platform_device_id *id; + + id = platform_get_device_id(pdev); + + return (struct atmel_pwm_data *)id->driver_data; + } +} + +static int atmel_pwm_probe(struct platform_device *pdev) +{ + const struct atmel_pwm_data *data; + struct atmel_pwm_chip *atmel_pwm; + struct resource *res; + int ret; + + data = atmel_pwm_get_driver_data(pdev); + if (!data) + return -ENODEV; + + atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL); + if (!atmel_pwm) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(atmel_pwm->base)) + return PTR_ERR(atmel_pwm->base); + + atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(atmel_pwm->clk)) + return PTR_ERR(atmel_pwm->clk); + + ret = clk_prepare(atmel_pwm->clk); + if (ret) { + dev_err(&pdev->dev, "failed to prepare PWM clock\n"); + return ret; + } + + atmel_pwm->chip.dev = &pdev->dev; + atmel_pwm->chip.ops = &atmel_pwm_ops; + + if (pdev->dev.of_node) { + atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags; + atmel_pwm->chip.of_pwm_n_cells = 3; + } + + atmel_pwm->chip.base = -1; + atmel_pwm->chip.npwm = 4; + atmel_pwm->chip.can_sleep = true; + atmel_pwm->config = data->config; + + ret = pwmchip_add(&atmel_pwm->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret); + goto unprepare_clk; + } + + platform_set_drvdata(pdev, atmel_pwm); + + return ret; + +unprepare_clk: + clk_unprepare(atmel_pwm->clk); + return ret; +} + +static int atmel_pwm_remove(struct platform_device *pdev) +{ + struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev); + + clk_unprepare(atmel_pwm->clk); + + return pwmchip_remove(&atmel_pwm->chip); +} + +static struct platform_driver atmel_pwm_driver = { + .driver = { + .name = "atmel-pwm", + .of_match_table = of_match_ptr(atmel_pwm_dt_ids), + }, + .id_table = atmel_pwm_devtypes, + .probe = atmel_pwm_probe, + .remove = atmel_pwm_remove, +}; +module_platform_driver(atmel_pwm_driver); + +MODULE_ALIAS("platform:atmel-pwm"); +MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>"); +MODULE_DESCRIPTION("Atmel PWM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c new file mode 100644 index 00000000000..02bc048892a --- /dev/null +++ b/drivers/pwm/pwm-bcm-kona.c @@ -0,0 +1,318 @@ +/* + * Copyright (C) 2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/math64.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/slab.h> +#include <linux/types.h> + +/* + * The Kona PWM has some unusual characteristics. Here are the main points. + * + * 1) There is no disable bit and the hardware docs advise programming a zero + * duty to achieve output equivalent to that of a normal disable operation. + * + * 2) Changes to prescale, duty, period, and polarity do not take effect until + * a subsequent rising edge of the trigger bit. + * + * 3) If the smooth bit and trigger bit are both low, the output is a constant + * high signal. Otherwise, the earlier waveform continues to be output. + * + * 4) If the smooth bit is set on the rising edge of the trigger bit, output + * will transition to the new settings on a period boundary (which could be + * seconds away). If the smooth bit is clear, new settings will be applied + * as soon as possible (the hardware always has a 400ns delay). + * + * 5) When the external clock that feeds the PWM is disabled, output is pegged + * high or low depending on its state at that exact instant. + */ + +#define PWM_CONTROL_OFFSET (0x00000000) +#define PWM_CONTROL_SMOOTH_SHIFT(chan) (24 + (chan)) +#define PWM_CONTROL_TYPE_SHIFT(chan) (16 + (chan)) +#define PWM_CONTROL_POLARITY_SHIFT(chan) (8 + (chan)) +#define PWM_CONTROL_TRIGGER_SHIFT(chan) (chan) + +#define PRESCALE_OFFSET (0x00000004) +#define PRESCALE_SHIFT(chan) ((chan) << 2) +#define PRESCALE_MASK(chan) (0x7 << PRESCALE_SHIFT(chan)) +#define PRESCALE_MIN (0x00000000) +#define PRESCALE_MAX (0x00000007) + +#define PERIOD_COUNT_OFFSET(chan) (0x00000008 + ((chan) << 3)) +#define PERIOD_COUNT_MIN (0x00000002) +#define PERIOD_COUNT_MAX (0x00ffffff) + +#define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + ((chan) << 3)) +#define DUTY_CYCLE_HIGH_MIN (0x00000000) +#define DUTY_CYCLE_HIGH_MAX (0x00ffffff) + +struct kona_pwmc { + struct pwm_chip chip; + void __iomem *base; + struct clk *clk; +}; + +static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip) +{ + return container_of(_chip, struct kona_pwmc, chip); +} + +static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan) +{ + unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); + + /* Clear trigger bit but set smooth bit to maintain old output */ + value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan); + value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan)); + writel(value, kp->base + PWM_CONTROL_OFFSET); + + /* Set trigger bit and clear smooth bit to apply new settings */ + value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan)); + value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan); + writel(value, kp->base + PWM_CONTROL_OFFSET); +} + +static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct kona_pwmc *kp = to_kona_pwmc(chip); + u64 val, div, rate; + unsigned long prescale = PRESCALE_MIN, pc, dc; + unsigned int value, chan = pwm->hwpwm; + + /* + * Find period count, duty count and prescale to suit duty_ns and + * period_ns. This is done according to formulas described below: + * + * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE + * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE + * + * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1)) + * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1)) + */ + + rate = clk_get_rate(kp->clk); + + while (1) { + div = 1000000000; + div *= 1 + prescale; + val = rate * period_ns; + pc = div64_u64(val, div); + val = rate * duty_ns; + dc = div64_u64(val, div); + + /* If duty_ns or period_ns are not achievable then return */ + if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN) + return -EINVAL; + + /* If pc and dc are in bounds, the calculation is done */ + if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX) + break; + + /* Otherwise, increase prescale and recalculate pc and dc */ + if (++prescale > PRESCALE_MAX) + return -EINVAL; + } + + /* If the PWM channel is enabled, write the settings to the HW */ + if (test_bit(PWMF_ENABLED, &pwm->flags)) { + value = readl(kp->base + PRESCALE_OFFSET); + value &= ~PRESCALE_MASK(chan); + value |= prescale << PRESCALE_SHIFT(chan); + writel(value, kp->base + PRESCALE_OFFSET); + + writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan)); + + writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); + + kona_pwmc_apply_settings(kp, chan); + } + + return 0; +} + +static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct kona_pwmc *kp = to_kona_pwmc(chip); + unsigned int chan = pwm->hwpwm; + unsigned int value; + int ret; + + ret = clk_prepare_enable(kp->clk); + if (ret < 0) { + dev_err(chip->dev, "failed to enable clock: %d\n", ret); + return ret; + } + + value = readl(kp->base + PWM_CONTROL_OFFSET); + + if (polarity == PWM_POLARITY_NORMAL) + value |= 1 << PWM_CONTROL_POLARITY_SHIFT(chan); + else + value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan)); + + writel(value, kp->base + PWM_CONTROL_OFFSET); + + kona_pwmc_apply_settings(kp, chan); + + /* Wait for waveform to settle before gating off the clock */ + ndelay(400); + + clk_disable_unprepare(kp->clk); + + return 0; +} + +static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct kona_pwmc *kp = to_kona_pwmc(chip); + int ret; + + ret = clk_prepare_enable(kp->clk); + if (ret < 0) { + dev_err(chip->dev, "failed to enable clock: %d\n", ret); + return ret; + } + + ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period); + if (ret < 0) { + clk_disable_unprepare(kp->clk); + return ret; + } + + return 0; +} + +static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct kona_pwmc *kp = to_kona_pwmc(chip); + unsigned int chan = pwm->hwpwm; + + /* Simulate a disable by configuring for zero duty */ + writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); + kona_pwmc_apply_settings(kp, chan); + + /* Wait for waveform to settle before gating off the clock */ + ndelay(400); + + clk_disable_unprepare(kp->clk); +} + +static const struct pwm_ops kona_pwm_ops = { + .config = kona_pwmc_config, + .set_polarity = kona_pwmc_set_polarity, + .enable = kona_pwmc_enable, + .disable = kona_pwmc_disable, + .owner = THIS_MODULE, +}; + +static int kona_pwmc_probe(struct platform_device *pdev) +{ + struct kona_pwmc *kp; + struct resource *res; + unsigned int chan; + unsigned int value = 0; + int ret = 0; + + kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL); + if (kp == NULL) + return -ENOMEM; + + platform_set_drvdata(pdev, kp); + + kp->chip.dev = &pdev->dev; + kp->chip.ops = &kona_pwm_ops; + kp->chip.base = -1; + kp->chip.npwm = 6; + kp->chip.of_xlate = of_pwm_xlate_with_flags; + kp->chip.of_pwm_n_cells = 3; + kp->chip.can_sleep = true; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + kp->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(kp->base)) + return PTR_ERR(kp->base); + + kp->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(kp->clk)) { + dev_err(&pdev->dev, "failed to get clock: %ld\n", + PTR_ERR(kp->clk)); + return PTR_ERR(kp->clk); + } + + ret = clk_prepare_enable(kp->clk); + if (ret < 0) { + dev_err(&pdev->dev, "failed to enable clock: %d\n", ret); + return ret; + } + + /* Set smooth mode, push/pull, and normal polarity for all channels */ + for (chan = 0; chan < kp->chip.npwm; chan++) { + value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan)); + value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan)); + value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan)); + } + + writel(value, kp->base + PWM_CONTROL_OFFSET); + + clk_disable_unprepare(kp->clk); + + ret = pwmchip_add(&kp->chip); + if (ret < 0) + dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); + + return ret; +} + +static int kona_pwmc_remove(struct platform_device *pdev) +{ + struct kona_pwmc *kp = platform_get_drvdata(pdev); + unsigned int chan; + + for (chan = 0; chan < kp->chip.npwm; chan++) + if (test_bit(PWMF_ENABLED, &kp->chip.pwms[chan].flags)) + clk_disable_unprepare(kp->clk); + + return pwmchip_remove(&kp->chip); +} + +static const struct of_device_id bcm_kona_pwmc_dt[] = { + { .compatible = "brcm,kona-pwm" }, + { }, +}; +MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt); + +static struct platform_driver kona_pwmc_driver = { + .driver = { + .name = "bcm-kona-pwm", + .of_match_table = bcm_kona_pwmc_dt, + }, + .probe = kona_pwmc_probe, + .remove = kona_pwmc_remove, +}; +module_platform_driver(kona_pwmc_driver); + +MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>"); +MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>"); +MODULE_DESCRIPTION("Broadcom Kona PWM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pwm/pwm-bfin.c b/drivers/pwm/pwm-bfin.c index 7631ef194de..9985d830e55 100644 --- a/drivers/pwm/pwm-bfin.c +++ b/drivers/pwm/pwm-bfin.c @@ -149,6 +149,7 @@ static int bfin_pwm_remove(struct platform_device *pdev) static struct platform_driver bfin_pwm_driver = { .driver = { .name = "bfin-pwm", + .owner = THIS_MODULE, }, .probe = bfin_pwm_probe, .remove = bfin_pwm_remove, diff --git a/drivers/pwm/pwm-clps711x.c b/drivers/pwm/pwm-clps711x.c new file mode 100644 index 00000000000..fafb6a0111b --- /dev/null +++ b/drivers/pwm/pwm-clps711x.c @@ -0,0 +1,176 @@ +/* + * Cirrus Logic CLPS711X PWM driver + * + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> + +struct clps711x_chip { + struct pwm_chip chip; + void __iomem *pmpcon; + struct clk *clk; + spinlock_t lock; +}; + +static inline struct clps711x_chip *to_clps711x_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct clps711x_chip, chip); +} + +static void clps711x_pwm_update_val(struct clps711x_chip *priv, u32 n, u32 v) +{ + /* PWM0 - bits 4..7, PWM1 - bits 8..11 */ + u32 shift = (n + 1) * 4; + unsigned long flags; + u32 tmp; + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readl(priv->pmpcon); + tmp &= ~(0xf << shift); + tmp |= v << shift; + writel(tmp, priv->pmpcon); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +static unsigned int clps711x_get_duty(struct pwm_device *pwm, unsigned int v) +{ + /* Duty cycle 0..15 max */ + return DIV_ROUND_CLOSEST(v * 0xf, pwm_get_period(pwm)); +} + +static int clps711x_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct clps711x_chip *priv = to_clps711x_chip(chip); + unsigned int freq = clk_get_rate(priv->clk); + + if (!freq) + return -EINVAL; + + /* Store constant period value */ + pwm_set_period(pwm, DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq)); + + return 0; +} + +static int clps711x_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct clps711x_chip *priv = to_clps711x_chip(chip); + unsigned int duty; + + if (period_ns != pwm_get_period(pwm)) + return -EINVAL; + + duty = clps711x_get_duty(pwm, duty_ns); + clps711x_pwm_update_val(priv, pwm->hwpwm, duty); + + return 0; +} + +static int clps711x_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct clps711x_chip *priv = to_clps711x_chip(chip); + unsigned int duty; + + duty = clps711x_get_duty(pwm, pwm_get_duty_cycle(pwm)); + clps711x_pwm_update_val(priv, pwm->hwpwm, duty); + + return 0; +} + +static void clps711x_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct clps711x_chip *priv = to_clps711x_chip(chip); + + clps711x_pwm_update_val(priv, pwm->hwpwm, 0); +} + +static const struct pwm_ops clps711x_pwm_ops = { + .request = clps711x_pwm_request, + .config = clps711x_pwm_config, + .enable = clps711x_pwm_enable, + .disable = clps711x_pwm_disable, + .owner = THIS_MODULE, +}; + +static struct pwm_device *clps711x_pwm_xlate(struct pwm_chip *chip, + const struct of_phandle_args *args) +{ + if (args->args[0] >= chip->npwm) + return ERR_PTR(-EINVAL); + + return pwm_request_from_chip(chip, args->args[0], NULL); +} + +static int clps711x_pwm_probe(struct platform_device *pdev) +{ + struct clps711x_chip *priv; + struct resource *res; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->pmpcon = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->pmpcon)) + return PTR_ERR(priv->pmpcon); + + priv->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + priv->chip.ops = &clps711x_pwm_ops; + priv->chip.dev = &pdev->dev; + priv->chip.base = -1; + priv->chip.npwm = 2; + priv->chip.of_xlate = clps711x_pwm_xlate; + priv->chip.of_pwm_n_cells = 1; + + spin_lock_init(&priv->lock); + + platform_set_drvdata(pdev, priv); + + return pwmchip_add(&priv->chip); +} + +static int clps711x_pwm_remove(struct platform_device *pdev) +{ + struct clps711x_chip *priv = platform_get_drvdata(pdev); + + return pwmchip_remove(&priv->chip); +} + +static const struct of_device_id __maybe_unused clps711x_pwm_dt_ids[] = { + { .compatible = "cirrus,clps711x-pwm", }, + { } +}; +MODULE_DEVICE_TABLE(of, clps711x_pwm_dt_ids); + +static struct platform_driver clps711x_pwm_driver = { + .driver = { + .name = "clps711x-pwm", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(clps711x_pwm_dt_ids), + }, + .probe = clps711x_pwm_probe, + .remove = clps711x_pwm_remove, +}; +module_platform_driver(clps711x_pwm_driver); + +MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); +MODULE_DESCRIPTION("Cirrus Logic CLPS711X PWM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-ep93xx.c b/drivers/pwm/pwm-ep93xx.c new file mode 100644 index 00000000000..e593e9c45c5 --- /dev/null +++ b/drivers/pwm/pwm-ep93xx.c @@ -0,0 +1,230 @@ +/* + * PWM framework driver for Cirrus Logic EP93xx + * + * Copyright (c) 2009 Matthieu Crapet <mcrapet@gmail.com> + * Copyright (c) 2009, 2013 H Hartley Sweeten <hsweeten@visionengravers.com> + * + * EP9301/02 have only one channel: + * platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14) + * + * EP9307 has only one channel: + * platform device ep93xx-pwm.0 - PWMOUT + * + * EP9312/15 have two channels: + * platform device ep93xx-pwm.0 - PWMOUT + * platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/pwm.h> + +#include <asm/div64.h> + +#include <mach/platform.h> /* for ep93xx_pwm_{acquire,release}_gpio() */ + +#define EP93XX_PWMx_TERM_COUNT 0x00 +#define EP93XX_PWMx_DUTY_CYCLE 0x04 +#define EP93XX_PWMx_ENABLE 0x08 +#define EP93XX_PWMx_INVERT 0x0c + +struct ep93xx_pwm { + void __iomem *base; + struct clk *clk; + struct pwm_chip chip; +}; + +static inline struct ep93xx_pwm *to_ep93xx_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct ep93xx_pwm, chip); +} + +static int ep93xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct platform_device *pdev = to_platform_device(chip->dev); + + return ep93xx_pwm_acquire_gpio(pdev); +} + +static void ep93xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct platform_device *pdev = to_platform_device(chip->dev); + + ep93xx_pwm_release_gpio(pdev); +} + +static int ep93xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip); + void __iomem *base = ep93xx_pwm->base; + unsigned long long c; + unsigned long period_cycles; + unsigned long duty_cycles; + unsigned long term; + int ret = 0; + + /* + * The clock needs to be enabled to access the PWM registers. + * Configuration can be changed at any time. + */ + if (!test_bit(PWMF_ENABLED, &pwm->flags)) { + ret = clk_enable(ep93xx_pwm->clk); + if (ret) + return ret; + } + + c = clk_get_rate(ep93xx_pwm->clk); + c *= period_ns; + do_div(c, 1000000000); + period_cycles = c; + + c = period_cycles; + c *= duty_ns; + do_div(c, period_ns); + duty_cycles = c; + + if (period_cycles < 0x10000 && duty_cycles < 0x10000) { + term = readw(base + EP93XX_PWMx_TERM_COUNT); + + /* Order is important if PWM is running */ + if (period_cycles > term) { + writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT); + writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE); + } else { + writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE); + writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT); + } + } else { + ret = -EINVAL; + } + + if (!test_bit(PWMF_ENABLED, &pwm->flags)) + clk_disable(ep93xx_pwm->clk); + + return ret; +} + +static int ep93xx_pwm_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip); + int ret; + + /* + * The clock needs to be enabled to access the PWM registers. + * Polarity can only be changed when the PWM is disabled. + */ + ret = clk_enable(ep93xx_pwm->clk); + if (ret) + return ret; + + if (polarity == PWM_POLARITY_INVERSED) + writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_INVERT); + else + writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_INVERT); + + clk_disable(ep93xx_pwm->clk); + + return 0; +} + +static int ep93xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip); + int ret; + + ret = clk_enable(ep93xx_pwm->clk); + if (ret) + return ret; + + writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_ENABLE); + + return 0; +} + +static void ep93xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip); + + writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE); + clk_disable(ep93xx_pwm->clk); +} + +static const struct pwm_ops ep93xx_pwm_ops = { + .request = ep93xx_pwm_request, + .free = ep93xx_pwm_free, + .config = ep93xx_pwm_config, + .set_polarity = ep93xx_pwm_polarity, + .enable = ep93xx_pwm_enable, + .disable = ep93xx_pwm_disable, + .owner = THIS_MODULE, +}; + +static int ep93xx_pwm_probe(struct platform_device *pdev) +{ + struct ep93xx_pwm *ep93xx_pwm; + struct resource *res; + int ret; + + ep93xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*ep93xx_pwm), GFP_KERNEL); + if (!ep93xx_pwm) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ep93xx_pwm->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ep93xx_pwm->base)) + return PTR_ERR(ep93xx_pwm->base); + + ep93xx_pwm->clk = devm_clk_get(&pdev->dev, "pwm_clk"); + if (IS_ERR(ep93xx_pwm->clk)) + return PTR_ERR(ep93xx_pwm->clk); + + ep93xx_pwm->chip.dev = &pdev->dev; + ep93xx_pwm->chip.ops = &ep93xx_pwm_ops; + ep93xx_pwm->chip.base = -1; + ep93xx_pwm->chip.npwm = 1; + + ret = pwmchip_add(&ep93xx_pwm->chip); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, ep93xx_pwm); + return 0; +} + +static int ep93xx_pwm_remove(struct platform_device *pdev) +{ + struct ep93xx_pwm *ep93xx_pwm = platform_get_drvdata(pdev); + + return pwmchip_remove(&ep93xx_pwm->chip); +} + +static struct platform_driver ep93xx_pwm_driver = { + .driver = { + .name = "ep93xx-pwm", + }, + .probe = ep93xx_pwm_probe, + .remove = ep93xx_pwm_remove, +}; +module_platform_driver(ep93xx_pwm_driver); + +MODULE_DESCRIPTION("Cirrus Logic EP93xx PWM driver"); +MODULE_AUTHOR("Matthieu Crapet <mcrapet@gmail.com>"); +MODULE_AUTHOR("H Hartley Sweeten <hsweeten@visionengravers.com>"); +MODULE_ALIAS("platform:ep93xx-pwm"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c new file mode 100644 index 00000000000..a18bc8fea38 --- /dev/null +++ b/drivers/pwm/pwm-fsl-ftm.c @@ -0,0 +1,496 @@ +/* + * Freescale FlexTimer Module (FTM) PWM Driver + * + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/slab.h> + +#define FTM_SC 0x00 +#define FTM_SC_CLK_MASK 0x3 +#define FTM_SC_CLK_SHIFT 3 +#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_SHIFT) +#define FTM_SC_PS_MASK 0x7 +#define FTM_SC_PS_SHIFT 0 + +#define FTM_CNT 0x04 +#define FTM_MOD 0x08 + +#define FTM_CSC_BASE 0x0C +#define FTM_CSC_MSB BIT(5) +#define FTM_CSC_MSA BIT(4) +#define FTM_CSC_ELSB BIT(3) +#define FTM_CSC_ELSA BIT(2) +#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8)) + +#define FTM_CV_BASE 0x10 +#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8)) + +#define FTM_CNTIN 0x4C +#define FTM_STATUS 0x50 + +#define FTM_MODE 0x54 +#define FTM_MODE_FTMEN BIT(0) +#define FTM_MODE_INIT BIT(2) +#define FTM_MODE_PWMSYNC BIT(3) + +#define FTM_SYNC 0x58 +#define FTM_OUTINIT 0x5C +#define FTM_OUTMASK 0x60 +#define FTM_COMBINE 0x64 +#define FTM_DEADTIME 0x68 +#define FTM_EXTTRIG 0x6C +#define FTM_POL 0x70 +#define FTM_FMS 0x74 +#define FTM_FILTER 0x78 +#define FTM_FLTCTRL 0x7C +#define FTM_QDCTRL 0x80 +#define FTM_CONF 0x84 +#define FTM_FLTPOL 0x88 +#define FTM_SYNCONF 0x8C +#define FTM_INVCTRL 0x90 +#define FTM_SWOCTRL 0x94 +#define FTM_PWMLOAD 0x98 + +enum fsl_pwm_clk { + FSL_PWM_CLK_SYS, + FSL_PWM_CLK_FIX, + FSL_PWM_CLK_EXT, + FSL_PWM_CLK_CNTEN, + FSL_PWM_CLK_MAX +}; + +struct fsl_pwm_chip { + struct pwm_chip chip; + + struct mutex lock; + + unsigned int use_count; + unsigned int cnt_select; + unsigned int clk_ps; + + void __iomem *base; + + int period_ns; + + struct clk *clk[FSL_PWM_CLK_MAX]; +}; + +static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct fsl_pwm_chip, chip); +} + +static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + + return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); +} + +static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + + clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); +} + +static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc, + enum fsl_pwm_clk index) +{ + unsigned long sys_rate, cnt_rate; + unsigned long long ratio; + + sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]); + if (!sys_rate) + return -EINVAL; + + cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]); + if (!cnt_rate) + return -EINVAL; + + switch (index) { + case FSL_PWM_CLK_SYS: + fpc->clk_ps = 1; + break; + case FSL_PWM_CLK_FIX: + ratio = 2 * cnt_rate - 1; + do_div(ratio, sys_rate); + fpc->clk_ps = ratio; + break; + case FSL_PWM_CLK_EXT: + ratio = 4 * cnt_rate - 1; + do_div(ratio, sys_rate); + fpc->clk_ps = ratio; + break; + default: + return -EINVAL; + } + + return 0; +} + +static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc, + unsigned long period_ns) +{ + unsigned long long c, c0; + + c = clk_get_rate(fpc->clk[fpc->cnt_select]); + c = c * period_ns; + do_div(c, 1000000000UL); + + do { + c0 = c; + do_div(c0, (1 << fpc->clk_ps)); + if (c0 <= 0xFFFF) + return (unsigned long)c0; + } while (++fpc->clk_ps < 8); + + return 0; +} + +static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc, + unsigned long period_ns, + enum fsl_pwm_clk index) +{ + int ret; + + ret = fsl_pwm_calculate_default_ps(fpc, index); + if (ret) { + dev_err(fpc->chip.dev, + "failed to calculate default prescaler: %d\n", + ret); + return 0; + } + + return fsl_pwm_calculate_cycles(fpc, period_ns); +} + +static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, + unsigned long period_ns) +{ + enum fsl_pwm_clk m0, m1; + unsigned long fix_rate, ext_rate, cycles; + + cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, + FSL_PWM_CLK_SYS); + if (cycles) { + fpc->cnt_select = FSL_PWM_CLK_SYS; + return cycles; + } + + fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); + ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); + + if (fix_rate > ext_rate) { + m0 = FSL_PWM_CLK_FIX; + m1 = FSL_PWM_CLK_EXT; + } else { + m0 = FSL_PWM_CLK_EXT; + m1 = FSL_PWM_CLK_FIX; + } + + cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); + if (cycles) { + fpc->cnt_select = m0; + return cycles; + } + + fpc->cnt_select = m1; + + return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1); +} + +static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, + unsigned long period_ns, + unsigned long duty_ns) +{ + unsigned long long val, duty; + + val = readl(fpc->base + FTM_MOD); + duty = duty_ns * (val + 1); + do_div(duty, period_ns); + + return (unsigned long)duty; +} + +static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + u32 val, period, duty; + + mutex_lock(&fpc->lock); + + /* + * The Freescale FTM controller supports only a single period for + * all PWM channels, therefore incompatible changes need to be + * refused. + */ + if (fpc->period_ns && fpc->period_ns != period_ns) { + dev_err(fpc->chip.dev, + "conflicting period requested for PWM %u\n", + pwm->hwpwm); + mutex_unlock(&fpc->lock); + return -EBUSY; + } + + if (!fpc->period_ns && duty_ns) { + period = fsl_pwm_calculate_period(fpc, period_ns); + if (!period) { + dev_err(fpc->chip.dev, "failed to calculate period\n"); + mutex_unlock(&fpc->lock); + return -EINVAL; + } + + val = readl(fpc->base + FTM_SC); + val &= ~(FTM_SC_PS_MASK << FTM_SC_PS_SHIFT); + val |= fpc->clk_ps; + writel(val, fpc->base + FTM_SC); + writel(period - 1, fpc->base + FTM_MOD); + + fpc->period_ns = period_ns; + } + + mutex_unlock(&fpc->lock); + + duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns); + + writel(FTM_CSC_MSB | FTM_CSC_ELSB, fpc->base + FTM_CSC(pwm->hwpwm)); + writel(duty, fpc->base + FTM_CV(pwm->hwpwm)); + + return 0; +} + +static int fsl_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + u32 val; + + val = readl(fpc->base + FTM_POL); + + if (polarity == PWM_POLARITY_INVERSED) + val |= BIT(pwm->hwpwm); + else + val &= ~BIT(pwm->hwpwm); + + writel(val, fpc->base + FTM_POL); + + return 0; +} + +static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) +{ + u32 val; + int ret; + + if (fpc->use_count != 0) + return 0; + + /* select counter clock source */ + val = readl(fpc->base + FTM_SC); + val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT); + val |= FTM_SC_CLK(fpc->cnt_select); + writel(val, fpc->base + FTM_SC); + + ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]); + if (ret) + return ret; + + ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); + if (ret) { + clk_disable_unprepare(fpc->clk[fpc->cnt_select]); + return ret; + } + + fpc->use_count++; + + return 0; +} + +static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + u32 val; + int ret; + + mutex_lock(&fpc->lock); + val = readl(fpc->base + FTM_OUTMASK); + val &= ~BIT(pwm->hwpwm); + writel(val, fpc->base + FTM_OUTMASK); + + ret = fsl_counter_clock_enable(fpc); + mutex_unlock(&fpc->lock); + + return ret; +} + +static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc) +{ + u32 val; + + /* + * already disabled, do nothing + */ + if (fpc->use_count == 0) + return; + + /* there are still users, so can't disable yet */ + if (--fpc->use_count > 0) + return; + + /* no users left, disable PWM counter clock */ + val = readl(fpc->base + FTM_SC); + val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT); + writel(val, fpc->base + FTM_SC); + + clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); + clk_disable_unprepare(fpc->clk[fpc->cnt_select]); +} + +static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + u32 val; + + mutex_lock(&fpc->lock); + val = readl(fpc->base + FTM_OUTMASK); + val |= BIT(pwm->hwpwm); + writel(val, fpc->base + FTM_OUTMASK); + + fsl_counter_clock_disable(fpc); + + val = readl(fpc->base + FTM_OUTMASK); + + if ((val & 0xFF) == 0xFF) + fpc->period_ns = 0; + + mutex_unlock(&fpc->lock); +} + +static const struct pwm_ops fsl_pwm_ops = { + .request = fsl_pwm_request, + .free = fsl_pwm_free, + .config = fsl_pwm_config, + .set_polarity = fsl_pwm_set_polarity, + .enable = fsl_pwm_enable, + .disable = fsl_pwm_disable, + .owner = THIS_MODULE, +}; + +static int fsl_pwm_init(struct fsl_pwm_chip *fpc) +{ + int ret; + + ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); + if (ret) + return ret; + + writel(0x00, fpc->base + FTM_CNTIN); + writel(0x00, fpc->base + FTM_OUTINIT); + writel(0xFF, fpc->base + FTM_OUTMASK); + + clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); + + return 0; +} + +static int fsl_pwm_probe(struct platform_device *pdev) +{ + struct fsl_pwm_chip *fpc; + struct resource *res; + int ret; + + fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); + if (!fpc) + return -ENOMEM; + + mutex_init(&fpc->lock); + + fpc->chip.dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + fpc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(fpc->base)) + return PTR_ERR(fpc->base); + + fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); + if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { + dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n"); + return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); + } + + fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); + if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) + return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); + + fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); + if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) + return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); + + fpc->clk[FSL_PWM_CLK_CNTEN] = + devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); + if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) + return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); + + fpc->chip.ops = &fsl_pwm_ops; + fpc->chip.of_xlate = of_pwm_xlate_with_flags; + fpc->chip.of_pwm_n_cells = 3; + fpc->chip.base = -1; + fpc->chip.npwm = 8; + fpc->chip.can_sleep = true; + + ret = pwmchip_add(&fpc->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, fpc); + + return fsl_pwm_init(fpc); +} + +static int fsl_pwm_remove(struct platform_device *pdev) +{ + struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev); + + return pwmchip_remove(&fpc->chip); +} + +static const struct of_device_id fsl_pwm_dt_ids[] = { + { .compatible = "fsl,vf610-ftm-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); + +static struct platform_driver fsl_pwm_driver = { + .driver = { + .name = "fsl-ftm-pwm", + .of_match_table = fsl_pwm_dt_ids, + }, + .probe = fsl_pwm_probe, + .remove = fsl_pwm_remove, +}; +module_platform_driver(fsl_pwm_driver); + +MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver"); +MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>"); +MODULE_ALIAS("platform:fsl-ftm-pwm"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 65a86bdeabe..d797c7b84c3 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -16,6 +16,7 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/pwm.h> +#include <linux/of.h> #include <linux/of_device.h> /* i.MX1 and i.MX21 share the same PWM function block: */ @@ -43,7 +44,6 @@ struct imx_chip { struct clk *clk_per; struct clk *clk_ipg; - int enabled; void __iomem *mmio_base; struct pwm_chip chip; @@ -135,7 +135,7 @@ static int imx_pwm_config_v2(struct pwm_chip *chip, MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH; - if (imx->enabled) + if (test_bit(PWMF_ENABLED, &pwm->flags)) cr |= MX3_PWMCR_EN; writel(cr, imx->mmio_base + MX3_PWMCR); @@ -186,8 +186,6 @@ static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) imx->set_enable(chip, true); - imx->enabled = 1; - return 0; } @@ -198,7 +196,6 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) imx->set_enable(chip, false); clk_disable_unprepare(imx->clk_per); - imx->enabled = 0; } static struct pwm_ops imx_pwm_ops = { @@ -244,10 +241,8 @@ static int imx_pwm_probe(struct platform_device *pdev) return -ENODEV; imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL); - if (imx == NULL) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + if (imx == NULL) return -ENOMEM; - } imx->clk_per = devm_clk_get(&pdev->dev, "per"); if (IS_ERR(imx->clk_per)) { @@ -269,14 +264,9 @@ static int imx_pwm_probe(struct platform_device *pdev) imx->chip.npwm = 1; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (r == NULL) { - dev_err(&pdev->dev, "no memory resource defined\n"); - return -ENODEV; - } - - imx->mmio_base = devm_request_and_ioremap(&pdev->dev, r); - if (imx->mmio_base == NULL) - return -EADDRNOTAVAIL; + imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(imx->mmio_base)) + return PTR_ERR(imx->mmio_base); data = of_id->data; imx->config = data->config; @@ -304,7 +294,8 @@ static int imx_pwm_remove(struct platform_device *pdev) static struct platform_driver imx_pwm_driver = { .driver = { .name = "imx-pwm", - .of_match_table = of_match_ptr(imx_pwm_dt_ids), + .owner = THIS_MODULE, + .of_match_table = imx_pwm_dt_ids, }, .probe = imx_pwm_probe, .remove = imx_pwm_remove, diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c index 0a2ede3c393..9c46209e1d0 100644 --- a/drivers/pwm/pwm-jz4740.c +++ b/drivers/pwm/pwm-jz4740.c @@ -165,13 +165,12 @@ static const struct pwm_ops jz4740_pwm_ops = { static int jz4740_pwm_probe(struct platform_device *pdev) { struct jz4740_pwm_chip *jz4740; - int ret; jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL); if (!jz4740) return -ENOMEM; - jz4740->clk = clk_get(NULL, "ext"); + jz4740->clk = devm_clk_get(&pdev->dev, "ext"); if (IS_ERR(jz4740->clk)) return PTR_ERR(jz4740->clk); @@ -180,29 +179,16 @@ static int jz4740_pwm_probe(struct platform_device *pdev) jz4740->chip.npwm = NUM_PWM; jz4740->chip.base = -1; - ret = pwmchip_add(&jz4740->chip); - if (ret < 0) { - clk_put(jz4740->clk); - return ret; - } - platform_set_drvdata(pdev, jz4740); - return 0; + return pwmchip_add(&jz4740->chip); } static int jz4740_pwm_remove(struct platform_device *pdev) { struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev); - int ret; - - ret = pwmchip_remove(&jz4740->chip); - if (ret < 0) - return ret; - clk_put(jz4740->clk); - - return 0; + return pwmchip_remove(&jz4740->chip); } static struct platform_driver jz4740_pwm_driver = { diff --git a/drivers/pwm/pwm-lp3943.c b/drivers/pwm/pwm-lp3943.c new file mode 100644 index 00000000000..2c39b0e50fa --- /dev/null +++ b/drivers/pwm/pwm-lp3943.c @@ -0,0 +1,317 @@ +/* + * TI/National Semiconductor LP3943 PWM driver + * + * Copyright 2013 Texas Instruments + * + * Author: Milo Kim <milo.kim@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2. + */ + +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/mfd/lp3943.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/slab.h> + +#define LP3943_MAX_DUTY 255 +#define LP3943_MIN_PERIOD 6250 +#define LP3943_MAX_PERIOD 1600000 + +struct lp3943_pwm { + struct pwm_chip chip; + struct lp3943 *lp3943; + struct lp3943_platform_data *pdata; +}; + +static inline struct lp3943_pwm *to_lp3943_pwm(struct pwm_chip *_chip) +{ + return container_of(_chip, struct lp3943_pwm, chip); +} + +static struct lp3943_pwm_map * +lp3943_pwm_request_map(struct lp3943_pwm *lp3943_pwm, int hwpwm) +{ + struct lp3943_platform_data *pdata = lp3943_pwm->pdata; + struct lp3943 *lp3943 = lp3943_pwm->lp3943; + struct lp3943_pwm_map *pwm_map; + int i, offset; + + pwm_map = kzalloc(sizeof(*pwm_map), GFP_KERNEL); + if (!pwm_map) + return ERR_PTR(-ENOMEM); + + pwm_map->output = pdata->pwms[hwpwm]->output; + pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; + + for (i = 0; i < pwm_map->num_outputs; i++) { + offset = pwm_map->output[i]; + + /* Return an error if the pin is already assigned */ + if (test_and_set_bit(offset, &lp3943->pin_used)) { + kfree(pwm_map); + return ERR_PTR(-EBUSY); + } + } + + return pwm_map; +} + +static int lp3943_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip); + struct lp3943_pwm_map *pwm_map; + + pwm_map = lp3943_pwm_request_map(lp3943_pwm, pwm->hwpwm); + if (IS_ERR(pwm_map)) + return PTR_ERR(pwm_map); + + return pwm_set_chip_data(pwm, pwm_map); +} + +static void lp3943_pwm_free_map(struct lp3943_pwm *lp3943_pwm, + struct lp3943_pwm_map *pwm_map) +{ + struct lp3943 *lp3943 = lp3943_pwm->lp3943; + int i, offset; + + for (i = 0; i < pwm_map->num_outputs; i++) { + offset = pwm_map->output[i]; + clear_bit(offset, &lp3943->pin_used); + } + + kfree(pwm_map); +} + +static void lp3943_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip); + struct lp3943_pwm_map *pwm_map = pwm_get_chip_data(pwm); + + lp3943_pwm_free_map(lp3943_pwm, pwm_map); +} + +static int lp3943_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip); + struct lp3943 *lp3943 = lp3943_pwm->lp3943; + u8 val, reg_duty, reg_prescale; + int err; + + /* + * How to configure the LP3943 PWMs + * + * 1) Period = 6250 ~ 1600000 + * 2) Prescale = period / 6250 -1 + * 3) Duty = input duty + * + * Prescale and duty are register values + */ + + if (pwm->hwpwm == 0) { + reg_prescale = LP3943_REG_PRESCALE0; + reg_duty = LP3943_REG_PWM0; + } else { + reg_prescale = LP3943_REG_PRESCALE1; + reg_duty = LP3943_REG_PWM1; + } + + period_ns = clamp(period_ns, LP3943_MIN_PERIOD, LP3943_MAX_PERIOD); + val = (u8)(period_ns / LP3943_MIN_PERIOD - 1); + + err = lp3943_write_byte(lp3943, reg_prescale, val); + if (err) + return err; + + val = (u8)(duty_ns * LP3943_MAX_DUTY / period_ns); + + return lp3943_write_byte(lp3943, reg_duty, val); +} + +static int lp3943_pwm_set_mode(struct lp3943_pwm *lp3943_pwm, + struct lp3943_pwm_map *pwm_map, + u8 val) +{ + struct lp3943 *lp3943 = lp3943_pwm->lp3943; + const struct lp3943_reg_cfg *mux = lp3943->mux_cfg; + int i, index, err; + + for (i = 0; i < pwm_map->num_outputs; i++) { + index = pwm_map->output[i]; + err = lp3943_update_bits(lp3943, mux[index].reg, + mux[index].mask, + val << mux[index].shift); + if (err) + return err; + } + + return 0; +} + +static int lp3943_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip); + struct lp3943_pwm_map *pwm_map = pwm_get_chip_data(pwm); + u8 val; + + if (pwm->hwpwm == 0) + val = LP3943_DIM_PWM0; + else + val = LP3943_DIM_PWM1; + + /* + * Each PWM generator is set to control any of outputs of LP3943. + * To enable/disable the PWM, these output pins should be configured. + */ + + return lp3943_pwm_set_mode(lp3943_pwm, pwm_map, val); +} + +static void lp3943_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip); + struct lp3943_pwm_map *pwm_map = pwm_get_chip_data(pwm); + + /* + * LP3943 outputs are open-drain, so the pin should be configured + * when the PWM is disabled. + */ + + lp3943_pwm_set_mode(lp3943_pwm, pwm_map, LP3943_GPIO_OUT_HIGH); +} + +static const struct pwm_ops lp3943_pwm_ops = { + .request = lp3943_pwm_request, + .free = lp3943_pwm_free, + .config = lp3943_pwm_config, + .enable = lp3943_pwm_enable, + .disable = lp3943_pwm_disable, + .owner = THIS_MODULE, +}; + +static int lp3943_pwm_parse_dt(struct device *dev, + struct lp3943_pwm *lp3943_pwm) +{ + static const char * const name[] = { "ti,pwm0", "ti,pwm1", }; + struct device_node *node = dev->of_node; + struct lp3943_platform_data *pdata; + struct lp3943_pwm_map *pwm_map; + enum lp3943_pwm_output *output; + int i, err, proplen, count = 0; + u32 num_outputs; + + if (!node) + return -EINVAL; + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + /* + * Read the output map configuration from the device tree. + * Each of the two PWM generators can drive zero or more outputs. + */ + + for (i = 0; i < LP3943_NUM_PWMS; i++) { + if (!of_get_property(node, name[i], &proplen)) + continue; + + num_outputs = proplen / sizeof(u32); + if (num_outputs == 0) + continue; + + output = devm_kzalloc(dev, sizeof(*output) * num_outputs, + GFP_KERNEL); + if (!output) + return -ENOMEM; + + err = of_property_read_u32_array(node, name[i], output, + num_outputs); + if (err) + return err; + + pwm_map = devm_kzalloc(dev, sizeof(*pwm_map), GFP_KERNEL); + if (!pwm_map) + return -ENOMEM; + + pwm_map->output = output; + pwm_map->num_outputs = num_outputs; + pdata->pwms[i] = pwm_map; + + count++; + } + + if (count == 0) + return -ENODATA; + + lp3943_pwm->pdata = pdata; + return 0; +} + +static int lp3943_pwm_probe(struct platform_device *pdev) +{ + struct lp3943 *lp3943 = dev_get_drvdata(pdev->dev.parent); + struct lp3943_pwm *lp3943_pwm; + int ret; + + lp3943_pwm = devm_kzalloc(&pdev->dev, sizeof(*lp3943_pwm), GFP_KERNEL); + if (!lp3943_pwm) + return -ENOMEM; + + lp3943_pwm->pdata = lp3943->pdata; + if (!lp3943_pwm->pdata) { + if (IS_ENABLED(CONFIG_OF)) + ret = lp3943_pwm_parse_dt(&pdev->dev, lp3943_pwm); + else + ret = -ENODEV; + + if (ret) + return ret; + } + + lp3943_pwm->lp3943 = lp3943; + lp3943_pwm->chip.dev = &pdev->dev; + lp3943_pwm->chip.ops = &lp3943_pwm_ops; + lp3943_pwm->chip.npwm = LP3943_NUM_PWMS; + lp3943_pwm->chip.can_sleep = true; + + platform_set_drvdata(pdev, lp3943_pwm); + + return pwmchip_add(&lp3943_pwm->chip); +} + +static int lp3943_pwm_remove(struct platform_device *pdev) +{ + struct lp3943_pwm *lp3943_pwm = platform_get_drvdata(pdev); + + return pwmchip_remove(&lp3943_pwm->chip); +} + +#ifdef CONFIG_OF +static const struct of_device_id lp3943_pwm_of_match[] = { + { .compatible = "ti,lp3943-pwm", }, + { } +}; +MODULE_DEVICE_TABLE(of, lp3943_pwm_of_match); +#endif + +static struct platform_driver lp3943_pwm_driver = { + .probe = lp3943_pwm_probe, + .remove = lp3943_pwm_remove, + .driver = { + .name = "lp3943-pwm", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(lp3943_pwm_of_match), + }, +}; +module_platform_driver(lp3943_pwm_driver); + +MODULE_DESCRIPTION("LP3943 PWM driver"); +MODULE_ALIAS("platform:lp3943-pwm"); +MODULE_AUTHOR("Milo Kim"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index 14106440294..9dc0f9d42bf 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -37,6 +37,7 @@ static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); unsigned long long c; int period_cycles, duty_cycles; + u32 val; c = clk_get_rate(lpc32xx->clk) / 256; c = c * period_ns; @@ -68,8 +69,10 @@ static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, c = 255; duty_cycles = 256 - c; - writel(PWM_ENABLE | PWM_RELOADV(period_cycles) | PWM_DUTY(duty_cycles), - lpc32xx->base + (pwm->hwpwm << 2)); + val = readl(lpc32xx->base + (pwm->hwpwm << 2)); + val &= ~0xFFFF; + val |= PWM_RELOADV(period_cycles) | PWM_DUTY(duty_cycles); + writel(val, lpc32xx->base + (pwm->hwpwm << 2)); return 0; } @@ -77,15 +80,29 @@ static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); + u32 val; + int ret; + + ret = clk_enable(lpc32xx->clk); + if (ret) + return ret; + + val = readl(lpc32xx->base + (pwm->hwpwm << 2)); + val |= PWM_ENABLE; + writel(val, lpc32xx->base + (pwm->hwpwm << 2)); - return clk_enable(lpc32xx->clk); + return 0; } static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); + u32 val; + + val = readl(lpc32xx->base + (pwm->hwpwm << 2)); + val &= ~PWM_ENABLE; + writel(val, lpc32xx->base + (pwm->hwpwm << 2)); - writel(0, lpc32xx->base + (pwm->hwpwm << 2)); clk_disable(lpc32xx->clk); } @@ -107,12 +124,9 @@ static int lpc32xx_pwm_probe(struct platform_device *pdev) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; - - lpc32xx->base = devm_request_and_ioremap(&pdev->dev, res); - if (!lpc32xx->base) - return -EADDRNOTAVAIL; + lpc32xx->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(lpc32xx->base)) + return PTR_ERR(lpc32xx->base); lpc32xx->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(lpc32xx->clk)) @@ -145,7 +159,7 @@ static int lpc32xx_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&lpc32xx->chip); } -static struct of_device_id lpc32xx_pwm_dt_ids[] = { +static const struct of_device_id lpc32xx_pwm_dt_ids[] = { { .compatible = "nxp,lpc3220-pwm", }, { /* sentinel */ } }; @@ -154,7 +168,8 @@ MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids); static struct platform_driver lpc32xx_pwm_driver = { .driver = { .name = "lpc32xx-pwm", - .of_match_table = of_match_ptr(lpc32xx_pwm_dt_ids), + .owner = THIS_MODULE, + .of_match_table = lpc32xx_pwm_dt_ids, }, .probe = lpc32xx_pwm_probe, .remove = lpc32xx_pwm_remove, diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c new file mode 100644 index 00000000000..44ce6c6103a --- /dev/null +++ b/drivers/pwm/pwm-lpss.c @@ -0,0 +1,282 @@ +/* + * Intel Low Power Subsystem PWM controller driver + * + * Copyright (C) 2014, Intel Corporation + * Author: Mika Westerberg <mika.westerberg@linux.intel.com> + * Author: Chew Kean Ho <kean.ho.chew@intel.com> + * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> + * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> + * Author: Alan Cox <alan@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/acpi.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/pwm.h> +#include <linux/platform_device.h> +#include <linux/pci.h> + +static int pci_drv, plat_drv; /* So we know which drivers registered */ + +#define PWM 0x00000000 +#define PWM_ENABLE BIT(31) +#define PWM_SW_UPDATE BIT(30) +#define PWM_BASE_UNIT_SHIFT 8 +#define PWM_BASE_UNIT_MASK 0x00ffff00 +#define PWM_ON_TIME_DIV_MASK 0x000000ff +#define PWM_DIVISION_CORRECTION 0x2 +#define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION) +#define NSECS_PER_SEC 1000000000UL + +struct pwm_lpss_chip { + struct pwm_chip chip; + void __iomem *regs; + struct clk *clk; + unsigned long clk_rate; +}; + +struct pwm_lpss_boardinfo { + unsigned long clk_rate; +}; + +/* BayTrail */ +static const struct pwm_lpss_boardinfo byt_info = { + 25000000 +}; + +static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) +{ + return container_of(chip, struct pwm_lpss_chip, chip); +} + +static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct pwm_lpss_chip *lpwm = to_lpwm(chip); + u8 on_time_div; + unsigned long c; + unsigned long long base_unit, freq = NSECS_PER_SEC; + u32 ctrl; + + do_div(freq, period_ns); + + /* The equation is: base_unit = ((freq / c) * 65536) + correction */ + base_unit = freq * 65536; + + c = lpwm->clk_rate; + if (!c) + return -EINVAL; + + do_div(base_unit, c); + base_unit += PWM_DIVISION_CORRECTION; + if (base_unit > PWM_LIMIT) + return -EINVAL; + + if (duty_ns <= 0) + duty_ns = 1; + on_time_div = 255 - (255 * duty_ns / period_ns); + + ctrl = readl(lpwm->regs + PWM); + ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK); + ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT; + ctrl |= on_time_div; + /* request PWM to update on next cycle */ + ctrl |= PWM_SW_UPDATE; + writel(ctrl, lpwm->regs + PWM); + + return 0; +} + +static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct pwm_lpss_chip *lpwm = to_lpwm(chip); + u32 ctrl; + int ret; + + ret = clk_prepare_enable(lpwm->clk); + if (ret) + return ret; + + ctrl = readl(lpwm->regs + PWM); + writel(ctrl | PWM_ENABLE, lpwm->regs + PWM); + + return 0; +} + +static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct pwm_lpss_chip *lpwm = to_lpwm(chip); + u32 ctrl; + + ctrl = readl(lpwm->regs + PWM); + writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); + + clk_disable_unprepare(lpwm->clk); +} + +static const struct pwm_ops pwm_lpss_ops = { + .config = pwm_lpss_config, + .enable = pwm_lpss_enable, + .disable = pwm_lpss_disable, + .owner = THIS_MODULE, +}; + +static struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, + struct resource *r, + const struct pwm_lpss_boardinfo *info) +{ + struct pwm_lpss_chip *lpwm; + int ret; + + lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); + if (!lpwm) + return ERR_PTR(-ENOMEM); + + lpwm->regs = devm_ioremap_resource(dev, r); + if (IS_ERR(lpwm->regs)) + return ERR_CAST(lpwm->regs); + + if (info) { + lpwm->clk_rate = info->clk_rate; + } else { + lpwm->clk = devm_clk_get(dev, NULL); + if (IS_ERR(lpwm->clk)) { + dev_err(dev, "failed to get PWM clock\n"); + return ERR_CAST(lpwm->clk); + } + lpwm->clk_rate = clk_get_rate(lpwm->clk); + } + + lpwm->chip.dev = dev; + lpwm->chip.ops = &pwm_lpss_ops; + lpwm->chip.base = -1; + lpwm->chip.npwm = 1; + + ret = pwmchip_add(&lpwm->chip); + if (ret) { + dev_err(dev, "failed to add PWM chip: %d\n", ret); + return ERR_PTR(ret); + } + + return lpwm; +} + +static int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) +{ + u32 ctrl; + + ctrl = readl(lpwm->regs + PWM); + writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); + + return pwmchip_remove(&lpwm->chip); +} + +static int pwm_lpss_probe_pci(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + const struct pwm_lpss_boardinfo *info; + struct pwm_lpss_chip *lpwm; + int err; + + err = pci_enable_device(pdev); + if (err < 0) + return err; + + info = (struct pwm_lpss_boardinfo *)id->driver_data; + lpwm = pwm_lpss_probe(&pdev->dev, &pdev->resource[0], info); + if (IS_ERR(lpwm)) + return PTR_ERR(lpwm); + + pci_set_drvdata(pdev, lpwm); + return 0; +} + +static void pwm_lpss_remove_pci(struct pci_dev *pdev) +{ + struct pwm_lpss_chip *lpwm = pci_get_drvdata(pdev); + + pwm_lpss_remove(lpwm); + pci_disable_device(pdev); +} + +static struct pci_device_id pwm_lpss_pci_ids[] = { + { PCI_VDEVICE(INTEL, 0x0f08), (unsigned long)&byt_info}, + { PCI_VDEVICE(INTEL, 0x0f09), (unsigned long)&byt_info}, + { }, +}; +MODULE_DEVICE_TABLE(pci, pwm_lpss_pci_ids); + +static struct pci_driver pwm_lpss_driver_pci = { + .name = "pwm-lpss", + .id_table = pwm_lpss_pci_ids, + .probe = pwm_lpss_probe_pci, + .remove = pwm_lpss_remove_pci, +}; + +static int pwm_lpss_probe_platform(struct platform_device *pdev) +{ + struct pwm_lpss_chip *lpwm; + struct resource *r; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + lpwm = pwm_lpss_probe(&pdev->dev, r, NULL); + if (IS_ERR(lpwm)) + return PTR_ERR(lpwm); + + platform_set_drvdata(pdev, lpwm); + return 0; +} + +static int pwm_lpss_remove_platform(struct platform_device *pdev) +{ + struct pwm_lpss_chip *lpwm = platform_get_drvdata(pdev); + + return pwm_lpss_remove(lpwm); +} + +static const struct acpi_device_id pwm_lpss_acpi_match[] = { + { "80860F09", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match); + +static struct platform_driver pwm_lpss_driver_platform = { + .driver = { + .name = "pwm-lpss", + .acpi_match_table = pwm_lpss_acpi_match, + }, + .probe = pwm_lpss_probe_platform, + .remove = pwm_lpss_remove_platform, +}; + +static int __init pwm_init(void) +{ + pci_drv = pci_register_driver(&pwm_lpss_driver_pci); + plat_drv = platform_driver_register(&pwm_lpss_driver_platform); + if (pci_drv && plat_drv) + return pci_drv; + + return 0; +} +module_init(pwm_init); + +static void __exit pwm_exit(void) +{ + if (!pci_drv) + pci_unregister_driver(&pwm_lpss_driver_pci); + if (!plat_drv) + platform_driver_unregister(&pwm_lpss_driver_platform); +} +module_exit(pwm_exit); + +MODULE_DESCRIPTION("PWM driver for Intel LPSS"); +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:pwm-lpss"); diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c index 7ec345f0183..4f1bb4e0a42 100644 --- a/drivers/pwm/pwm-mxs.c +++ b/drivers/pwm/pwm-mxs.c @@ -16,7 +16,6 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/pwm.h> #include <linux/slab.h> @@ -38,7 +37,6 @@ struct mxs_pwm_chip { struct pwm_chip chip; - struct device *dev; struct clk *clk; void __iomem *base; }; @@ -131,7 +129,6 @@ static int mxs_pwm_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct mxs_pwm_chip *mxs; struct resource *res; - struct pinctrl *pinctrl; int ret; mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL); @@ -139,13 +136,9 @@ static int mxs_pwm_probe(struct platform_device *pdev) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mxs->base = devm_request_and_ioremap(&pdev->dev, res); - if (!mxs->base) - return -EADDRNOTAVAIL; - - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - if (IS_ERR(pinctrl)) - return PTR_ERR(pinctrl); + mxs->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mxs->base)) + return PTR_ERR(mxs->base); mxs->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(mxs->clk)) @@ -154,6 +147,7 @@ static int mxs_pwm_probe(struct platform_device *pdev) mxs->chip.dev = &pdev->dev; mxs->chip.ops = &mxs_pwm_ops; mxs->chip.base = -1; + mxs->chip.can_sleep = true; ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm); if (ret < 0) { dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret); @@ -166,12 +160,17 @@ static int mxs_pwm_probe(struct platform_device *pdev) return ret; } - mxs->dev = &pdev->dev; platform_set_drvdata(pdev, mxs); - stmp_reset_block(mxs->base); + ret = stmp_reset_block(mxs->base); + if (ret) + goto pwm_remove; return 0; + +pwm_remove: + pwmchip_remove(&mxs->chip); + return ret; } static int mxs_pwm_remove(struct platform_device *pdev) @@ -181,7 +180,7 @@ static int mxs_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&mxs->chip); } -static struct of_device_id mxs_pwm_dt_ids[] = { +static const struct of_device_id mxs_pwm_dt_ids[] = { { .compatible = "fsl,imx23-pwm", }, { /* sentinel */ } }; @@ -190,7 +189,8 @@ MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids); static struct platform_driver mxs_pwm_driver = { .driver = { .name = "mxs-pwm", - .of_match_table = of_match_ptr(mxs_pwm_dt_ids), + .owner = THIS_MODULE, + .of_match_table = mxs_pwm_dt_ids, }, .probe = mxs_pwm_probe, .remove = mxs_pwm_remove, diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c new file mode 100644 index 00000000000..3fb775ded0d --- /dev/null +++ b/drivers/pwm/pwm-pca9685.c @@ -0,0 +1,300 @@ +/* + * Driver for PCA9685 16-channel 12-bit PWM LED controller + * + * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * based on the pwm-twl-led.c driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#define PCA9685_MODE1 0x00 +#define PCA9685_MODE2 0x01 +#define PCA9685_SUBADDR1 0x02 +#define PCA9685_SUBADDR2 0x03 +#define PCA9685_SUBADDR3 0x04 +#define PCA9685_ALLCALLADDR 0x05 +#define PCA9685_LEDX_ON_L 0x06 +#define PCA9685_LEDX_ON_H 0x07 +#define PCA9685_LEDX_OFF_L 0x08 +#define PCA9685_LEDX_OFF_H 0x09 + +#define PCA9685_ALL_LED_ON_L 0xFA +#define PCA9685_ALL_LED_ON_H 0xFB +#define PCA9685_ALL_LED_OFF_L 0xFC +#define PCA9685_ALL_LED_OFF_H 0xFD +#define PCA9685_PRESCALE 0xFE + +#define PCA9685_NUMREGS 0xFF +#define PCA9685_MAXCHAN 0x10 + +#define LED_FULL (1 << 4) +#define MODE1_SLEEP (1 << 4) +#define MODE2_INVRT (1 << 4) +#define MODE2_OUTDRV (1 << 2) + +#define LED_N_ON_H(N) (PCA9685_LEDX_ON_H + (4 * (N))) +#define LED_N_ON_L(N) (PCA9685_LEDX_ON_L + (4 * (N))) +#define LED_N_OFF_H(N) (PCA9685_LEDX_OFF_H + (4 * (N))) +#define LED_N_OFF_L(N) (PCA9685_LEDX_OFF_L + (4 * (N))) + +struct pca9685 { + struct pwm_chip chip; + struct regmap *regmap; + int active_cnt; +}; + +static inline struct pca9685 *to_pca(struct pwm_chip *chip) +{ + return container_of(chip, struct pca9685, chip); +} + +static int pca9685_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct pca9685 *pca = to_pca(chip); + unsigned long long duty; + unsigned int reg; + + if (duty_ns < 1) { + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_OFF_H; + else + reg = LED_N_OFF_H(pwm->hwpwm); + + regmap_write(pca->regmap, reg, LED_FULL); + + return 0; + } + + if (duty_ns == period_ns) { + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_ON_H; + else + reg = LED_N_ON_H(pwm->hwpwm); + + regmap_write(pca->regmap, reg, LED_FULL); + + return 0; + } + + duty = 4096 * (unsigned long long)duty_ns; + duty = DIV_ROUND_UP_ULL(duty, period_ns); + + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_OFF_L; + else + reg = LED_N_OFF_L(pwm->hwpwm); + + regmap_write(pca->regmap, reg, (int)duty & 0xff); + + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_OFF_H; + else + reg = LED_N_OFF_H(pwm->hwpwm); + + regmap_write(pca->regmap, reg, ((int)duty >> 8) & 0xf); + + return 0; +} + +static int pca9685_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct pca9685 *pca = to_pca(chip); + unsigned int reg; + + /* + * The PWM subsystem does not support a pre-delay. + * So, set the ON-timeout to 0 + */ + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_ON_L; + else + reg = LED_N_ON_L(pwm->hwpwm); + + regmap_write(pca->regmap, reg, 0); + + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_ON_H; + else + reg = LED_N_ON_H(pwm->hwpwm); + + regmap_write(pca->regmap, reg, 0); + + /* + * Clear the full-off bit. + * It has precedence over the others and must be off. + */ + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_OFF_H; + else + reg = LED_N_OFF_H(pwm->hwpwm); + + regmap_update_bits(pca->regmap, reg, LED_FULL, 0x0); + + return 0; +} + +static void pca9685_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct pca9685 *pca = to_pca(chip); + unsigned int reg; + + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_OFF_H; + else + reg = LED_N_OFF_H(pwm->hwpwm); + + regmap_write(pca->regmap, reg, LED_FULL); + + /* Clear the LED_OFF counter. */ + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_OFF_L; + else + reg = LED_N_OFF_L(pwm->hwpwm); + + regmap_write(pca->regmap, reg, 0x0); +} + +static int pca9685_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct pca9685 *pca = to_pca(chip); + + if (pca->active_cnt++ == 0) + return regmap_update_bits(pca->regmap, PCA9685_MODE1, + MODE1_SLEEP, 0x0); + + return 0; +} + +static void pca9685_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct pca9685 *pca = to_pca(chip); + + if (--pca->active_cnt == 0) + regmap_update_bits(pca->regmap, PCA9685_MODE1, MODE1_SLEEP, + MODE1_SLEEP); +} + +static const struct pwm_ops pca9685_pwm_ops = { + .enable = pca9685_pwm_enable, + .disable = pca9685_pwm_disable, + .config = pca9685_pwm_config, + .request = pca9685_pwm_request, + .free = pca9685_pwm_free, + .owner = THIS_MODULE, +}; + +static struct regmap_config pca9685_regmap_i2c_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = PCA9685_NUMREGS, + .cache_type = REGCACHE_NONE, +}; + +static int pca9685_pwm_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device_node *np = client->dev.of_node; + struct pca9685 *pca; + int ret; + int mode2; + + pca = devm_kzalloc(&client->dev, sizeof(*pca), GFP_KERNEL); + if (!pca) + return -ENOMEM; + + pca->regmap = devm_regmap_init_i2c(client, &pca9685_regmap_i2c_config); + if (IS_ERR(pca->regmap)) { + ret = PTR_ERR(pca->regmap); + dev_err(&client->dev, "Failed to initialize register map: %d\n", + ret); + return ret; + } + + i2c_set_clientdata(client, pca); + + regmap_read(pca->regmap, PCA9685_MODE2, &mode2); + + if (of_property_read_bool(np, "invert")) + mode2 |= MODE2_INVRT; + else + mode2 &= ~MODE2_INVRT; + + if (of_property_read_bool(np, "open-drain")) + mode2 &= ~MODE2_OUTDRV; + else + mode2 |= MODE2_OUTDRV; + + regmap_write(pca->regmap, PCA9685_MODE2, mode2); + + /* clear all "full off" bits */ + regmap_write(pca->regmap, PCA9685_ALL_LED_OFF_L, 0); + regmap_write(pca->regmap, PCA9685_ALL_LED_OFF_H, 0); + + pca->chip.ops = &pca9685_pwm_ops; + /* add an extra channel for ALL_LED */ + pca->chip.npwm = PCA9685_MAXCHAN + 1; + + pca->chip.dev = &client->dev; + pca->chip.base = -1; + pca->chip.can_sleep = true; + + return pwmchip_add(&pca->chip); +} + +static int pca9685_pwm_remove(struct i2c_client *client) +{ + struct pca9685 *pca = i2c_get_clientdata(client); + + regmap_update_bits(pca->regmap, PCA9685_MODE1, MODE1_SLEEP, + MODE1_SLEEP); + + return pwmchip_remove(&pca->chip); +} + +static const struct i2c_device_id pca9685_id[] = { + { "pca9685", 0 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(i2c, pca9685_id); + +static const struct of_device_id pca9685_dt_ids[] = { + { .compatible = "nxp,pca9685-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, pca9685_dt_ids); + +static struct i2c_driver pca9685_i2c_driver = { + .driver = { + .name = "pca9685-pwm", + .owner = THIS_MODULE, + .of_match_table = pca9685_dt_ids, + }, + .probe = pca9685_pwm_probe, + .remove = pca9685_pwm_remove, + .id_table = pca9685_id, +}; + +module_i2c_driver(pca9685_i2c_driver); + +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de>"); +MODULE_DESCRIPTION("PWM driver for PCA9685"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-puv3.c b/drivers/pwm/pwm-puv3.c index b882f6032fe..a9a28083f24 100644 --- a/drivers/pwm/pwm-puv3.c +++ b/drivers/pwm/pwm-puv3.c @@ -27,7 +27,6 @@ struct puv3_pwm_chip { struct pwm_chip chip; void __iomem *base; struct clk *clk; - bool enabled; }; static inline struct puv3_pwm_chip *to_puv3(struct pwm_chip *chip) @@ -118,14 +117,9 @@ static int pwm_probe(struct platform_device *pdev) return PTR_ERR(puv3->clk); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (r == NULL) { - dev_err(&pdev->dev, "no memory resource defined\n"); - return -ENODEV; - } - - puv3->base = devm_request_and_ioremap(&pdev->dev, r); - if (puv3->base == NULL) - return -EADDRNOTAVAIL; + puv3->base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(puv3->base)) + return PTR_ERR(puv3->base); puv3->chip.dev = &pdev->dev; puv3->chip.ops = &puv3_pwm_ops; @@ -152,6 +146,7 @@ static int pwm_remove(struct platform_device *pdev) static struct platform_driver puv3_pwm_driver = { .driver = { .name = "PKUnity-v3-PWM", + .owner = THIS_MODULE, }, .probe = pwm_probe, .remove = pwm_remove, diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c index f32fc4e66e0..0b312ec420b 100644 --- a/drivers/pwm/pwm-pxa.c +++ b/drivers/pwm/pwm-pxa.c @@ -8,7 +8,7 @@ * published by the Free Software Foundation. * * 2008-02-13 initial version - * eric miao <eric.miao@marvell.com> + * eric miao <eric.miao@marvell.com> */ #include <linux/module.h> @@ -19,18 +19,18 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/pwm.h> +#include <linux/of_device.h> #include <asm/div64.h> #define HAS_SECONDARY_PWM 0x10 -#define PWM_ID_BASE(d) ((d) & 0xf) static const struct platform_device_id pwm_id_table[] = { /* PWM has_secondary_pwm? */ { "pxa25x-pwm", 0 }, - { "pxa27x-pwm", 0 | HAS_SECONDARY_PWM }, - { "pxa168-pwm", 1 }, - { "pxa910-pwm", 1 }, + { "pxa27x-pwm", HAS_SECONDARY_PWM }, + { "pxa168-pwm", 0 }, + { "pxa910-pwm", 0 }, { }, }; MODULE_DEVICE_TABLE(platform, pwm_id_table); @@ -48,7 +48,6 @@ struct pxa_pwm_chip { struct device *dev; struct clk *clk; - int clk_enabled; void __iomem *mmio_base; }; @@ -108,24 +107,15 @@ static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, static int pxa_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); - int rc = 0; - if (!pc->clk_enabled) { - rc = clk_prepare_enable(pc->clk); - if (!rc) - pc->clk_enabled++; - } - return rc; + return clk_prepare_enable(pc->clk); } static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); - if (pc->clk_enabled) { - clk_disable_unprepare(pc->clk); - pc->clk_enabled--; - } + clk_disable_unprepare(pc->clk); } static struct pwm_ops pxa_pwm_ops = { @@ -135,6 +125,46 @@ static struct pwm_ops pxa_pwm_ops = { .owner = THIS_MODULE, }; +#ifdef CONFIG_OF +/* + * Device tree users must create one device instance for each PWM channel. + * Hence we dispense with the HAS_SECONDARY_PWM and "tell" the original driver + * code that this is a single channel pxa25x-pwm. Currently all devices are + * supported identically. + */ +static const struct of_device_id pwm_of_match[] = { + { .compatible = "marvell,pxa250-pwm", .data = &pwm_id_table[0]}, + { .compatible = "marvell,pxa270-pwm", .data = &pwm_id_table[0]}, + { .compatible = "marvell,pxa168-pwm", .data = &pwm_id_table[0]}, + { .compatible = "marvell,pxa910-pwm", .data = &pwm_id_table[0]}, + { } +}; +MODULE_DEVICE_TABLE(of, pwm_of_match); +#else +#define pwm_of_match NULL +#endif + +static const struct platform_device_id *pxa_pwm_get_id_dt(struct device *dev) +{ + const struct of_device_id *id = of_match_device(pwm_of_match, dev); + + return id ? id->data : NULL; +} + +static struct pwm_device * +pxa_pwm_of_xlate(struct pwm_chip *pc, const struct of_phandle_args *args) +{ + struct pwm_device *pwm; + + pwm = pwm_request_from_chip(pc, 0, NULL); + if (IS_ERR(pwm)) + return pwm; + + pwm_set_period(pwm, args->args[0]); + + return pwm; +} + static int pwm_probe(struct platform_device *pdev) { const struct platform_device_id *id = platform_get_device_id(pdev); @@ -142,32 +172,34 @@ static int pwm_probe(struct platform_device *pdev) struct resource *r; int ret = 0; + if (IS_ENABLED(CONFIG_OF) && id == NULL) + id = pxa_pwm_get_id_dt(&pdev->dev); + + if (id == NULL) + return -EINVAL; + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); - if (pwm == NULL) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + if (pwm == NULL) return -ENOMEM; - } pwm->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); - pwm->clk_enabled = 0; - pwm->chip.dev = &pdev->dev; pwm->chip.ops = &pxa_pwm_ops; pwm->chip.base = -1; pwm->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1; - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (r == NULL) { - dev_err(&pdev->dev, "no memory resource defined\n"); - return -ENODEV; + if (IS_ENABLED(CONFIG_OF)) { + pwm->chip.of_xlate = pxa_pwm_of_xlate; + pwm->chip.of_pwm_n_cells = 1; } - pwm->mmio_base = devm_request_and_ioremap(&pdev->dev, r); - if (pwm->mmio_base == NULL) - return -EADDRNOTAVAIL; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(pwm->mmio_base)) + return PTR_ERR(pwm->mmio_base); ret = pwmchip_add(&pwm->chip); if (ret < 0) { @@ -194,22 +226,13 @@ static struct platform_driver pwm_driver = { .driver = { .name = "pxa25x-pwm", .owner = THIS_MODULE, + .of_match_table = pwm_of_match, }, .probe = pwm_probe, .remove = pwm_remove, .id_table = pwm_id_table, }; -static int __init pwm_init(void) -{ - return platform_driver_register(&pwm_driver); -} -arch_initcall(pwm_init); - -static void __exit pwm_exit(void) -{ - platform_driver_unregister(&pwm_driver); -} -module_exit(pwm_exit); +module_platform_driver(pwm_driver); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c new file mode 100644 index 00000000000..3b71b42e89d --- /dev/null +++ b/drivers/pwm/pwm-renesas-tpu.c @@ -0,0 +1,481 @@ +/* + * R-Mobile TPU PWM driver + * + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/pwm.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +#define TPU_CHANNEL_MAX 4 + +#define TPU_TSTR 0x00 /* Timer start register (shared) */ + +#define TPU_TCRn 0x00 /* Timer control register */ +#define TPU_TCR_CCLR_NONE (0 << 5) +#define TPU_TCR_CCLR_TGRA (1 << 5) +#define TPU_TCR_CCLR_TGRB (2 << 5) +#define TPU_TCR_CCLR_TGRC (5 << 5) +#define TPU_TCR_CCLR_TGRD (6 << 5) +#define TPU_TCR_CKEG_RISING (0 << 3) +#define TPU_TCR_CKEG_FALLING (1 << 3) +#define TPU_TCR_CKEG_BOTH (2 << 3) +#define TPU_TMDRn 0x04 /* Timer mode register */ +#define TPU_TMDR_BFWT (1 << 6) +#define TPU_TMDR_BFB (1 << 5) +#define TPU_TMDR_BFA (1 << 4) +#define TPU_TMDR_MD_NORMAL (0 << 0) +#define TPU_TMDR_MD_PWM (2 << 0) +#define TPU_TIORn 0x08 /* Timer I/O control register */ +#define TPU_TIOR_IOA_0 (0 << 0) +#define TPU_TIOR_IOA_0_CLR (1 << 0) +#define TPU_TIOR_IOA_0_SET (2 << 0) +#define TPU_TIOR_IOA_0_TOGGLE (3 << 0) +#define TPU_TIOR_IOA_1 (4 << 0) +#define TPU_TIOR_IOA_1_CLR (5 << 0) +#define TPU_TIOR_IOA_1_SET (6 << 0) +#define TPU_TIOR_IOA_1_TOGGLE (7 << 0) +#define TPU_TIERn 0x0c /* Timer interrupt enable register */ +#define TPU_TSRn 0x10 /* Timer status register */ +#define TPU_TCNTn 0x14 /* Timer counter */ +#define TPU_TGRAn 0x18 /* Timer general register A */ +#define TPU_TGRBn 0x1c /* Timer general register B */ +#define TPU_TGRCn 0x20 /* Timer general register C */ +#define TPU_TGRDn 0x24 /* Timer general register D */ + +#define TPU_CHANNEL_OFFSET 0x10 +#define TPU_CHANNEL_SIZE 0x40 + +enum tpu_pin_state { + TPU_PIN_INACTIVE, /* Pin is driven inactive */ + TPU_PIN_PWM, /* Pin is driven by PWM */ + TPU_PIN_ACTIVE, /* Pin is driven active */ +}; + +struct tpu_device; + +struct tpu_pwm_device { + bool timer_on; /* Whether the timer is running */ + + struct tpu_device *tpu; + unsigned int channel; /* Channel number in the TPU */ + + enum pwm_polarity polarity; + unsigned int prescaler; + u16 period; + u16 duty; +}; + +struct tpu_device { + struct platform_device *pdev; + struct pwm_chip chip; + spinlock_t lock; + + void __iomem *base; + struct clk *clk; +}; + +#define to_tpu_device(c) container_of(c, struct tpu_device, chip) + +static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value) +{ + void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET + + pwm->channel * TPU_CHANNEL_SIZE; + + iowrite16(value, base + reg_nr); +} + +static void tpu_pwm_set_pin(struct tpu_pwm_device *pwm, + enum tpu_pin_state state) +{ + static const char * const states[] = { "inactive", "PWM", "active" }; + + dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n", + pwm->channel, states[state]); + + switch (state) { + case TPU_PIN_INACTIVE: + tpu_pwm_write(pwm, TPU_TIORn, + pwm->polarity == PWM_POLARITY_INVERSED ? + TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0); + break; + case TPU_PIN_PWM: + tpu_pwm_write(pwm, TPU_TIORn, + pwm->polarity == PWM_POLARITY_INVERSED ? + TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR); + break; + case TPU_PIN_ACTIVE: + tpu_pwm_write(pwm, TPU_TIORn, + pwm->polarity == PWM_POLARITY_INVERSED ? + TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1); + break; + } +} + +static void tpu_pwm_start_stop(struct tpu_pwm_device *pwm, int start) +{ + unsigned long flags; + u16 value; + + spin_lock_irqsave(&pwm->tpu->lock, flags); + value = ioread16(pwm->tpu->base + TPU_TSTR); + + if (start) + value |= 1 << pwm->channel; + else + value &= ~(1 << pwm->channel); + + iowrite16(value, pwm->tpu->base + TPU_TSTR); + spin_unlock_irqrestore(&pwm->tpu->lock, flags); +} + +static int tpu_pwm_timer_start(struct tpu_pwm_device *pwm) +{ + int ret; + + if (!pwm->timer_on) { + /* Wake up device and enable clock. */ + pm_runtime_get_sync(&pwm->tpu->pdev->dev); + ret = clk_prepare_enable(pwm->tpu->clk); + if (ret) { + dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n"); + return ret; + } + pwm->timer_on = true; + } + + /* + * Make sure the channel is stopped, as we need to reconfigure it + * completely. First drive the pin to the inactive state to avoid + * glitches. + */ + tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE); + tpu_pwm_start_stop(pwm, false); + + /* + * - Clear TCNT on TGRB match + * - Count on rising edge + * - Set prescaler + * - Output 0 until TGRA, output 1 until TGRB (active low polarity) + * - Output 1 until TGRA, output 0 until TGRB (active high polarity + * - PWM mode + */ + tpu_pwm_write(pwm, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING | + pwm->prescaler); + tpu_pwm_write(pwm, TPU_TMDRn, TPU_TMDR_MD_PWM); + tpu_pwm_set_pin(pwm, TPU_PIN_PWM); + tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty); + tpu_pwm_write(pwm, TPU_TGRBn, pwm->period); + + dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n", + pwm->channel, pwm->duty, pwm->period); + + /* Start the channel. */ + tpu_pwm_start_stop(pwm, true); + + return 0; +} + +static void tpu_pwm_timer_stop(struct tpu_pwm_device *pwm) +{ + if (!pwm->timer_on) + return; + + /* Disable channel. */ + tpu_pwm_start_stop(pwm, false); + + /* Stop clock and mark device as idle. */ + clk_disable_unprepare(pwm->tpu->clk); + pm_runtime_put(&pwm->tpu->pdev->dev); + + pwm->timer_on = false; +} + +/* ----------------------------------------------------------------------------- + * PWM API + */ + +static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *_pwm) +{ + struct tpu_device *tpu = to_tpu_device(chip); + struct tpu_pwm_device *pwm; + + if (_pwm->hwpwm >= TPU_CHANNEL_MAX) + return -EINVAL; + + pwm = kzalloc(sizeof(*pwm), GFP_KERNEL); + if (pwm == NULL) + return -ENOMEM; + + pwm->tpu = tpu; + pwm->channel = _pwm->hwpwm; + pwm->polarity = PWM_POLARITY_NORMAL; + pwm->prescaler = 0; + pwm->period = 0; + pwm->duty = 0; + + pwm->timer_on = false; + + pwm_set_chip_data(_pwm, pwm); + + return 0; +} + +static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *_pwm) +{ + struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); + + tpu_pwm_timer_stop(pwm); + kfree(pwm); +} + +static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *_pwm, + int duty_ns, int period_ns) +{ + static const unsigned int prescalers[] = { 1, 4, 16, 64 }; + struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); + struct tpu_device *tpu = to_tpu_device(chip); + unsigned int prescaler; + bool duty_only = false; + u32 clk_rate; + u32 period; + u32 duty; + int ret; + + /* + * Pick a prescaler to avoid overflowing the counter. + * TODO: Pick the highest acceptable prescaler. + */ + clk_rate = clk_get_rate(tpu->clk); + + for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) { + period = clk_rate / prescalers[prescaler] + / (NSEC_PER_SEC / period_ns); + if (period <= 0xffff) + break; + } + + if (prescaler == ARRAY_SIZE(prescalers) || period == 0) { + dev_err(&tpu->pdev->dev, "clock rate mismatch\n"); + return -ENOTSUPP; + } + + if (duty_ns) { + duty = clk_rate / prescalers[prescaler] + / (NSEC_PER_SEC / duty_ns); + if (duty > period) + return -EINVAL; + } else { + duty = 0; + } + + dev_dbg(&tpu->pdev->dev, + "rate %u, prescaler %u, period %u, duty %u\n", + clk_rate, prescalers[prescaler], period, duty); + + if (pwm->prescaler == prescaler && pwm->period == period) + duty_only = true; + + pwm->prescaler = prescaler; + pwm->period = period; + pwm->duty = duty; + + /* If the channel is disabled we're done. */ + if (!test_bit(PWMF_ENABLED, &_pwm->flags)) + return 0; + + if (duty_only && pwm->timer_on) { + /* + * If only the duty cycle changed and the timer is already + * running, there's no need to reconfigure it completely, Just + * modify the duty cycle. + */ + tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty); + dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel, + pwm->duty); + } else { + /* Otherwise perform a full reconfiguration. */ + ret = tpu_pwm_timer_start(pwm); + if (ret < 0) + return ret; + } + + if (duty == 0 || duty == period) { + /* + * To avoid running the timer when not strictly required, handle + * 0% and 100% duty cycles as fixed levels and stop the timer. + */ + tpu_pwm_set_pin(pwm, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); + tpu_pwm_timer_stop(pwm); + } + + return 0; +} + +static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *_pwm, + enum pwm_polarity polarity) +{ + struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); + + pwm->polarity = polarity; + + return 0; +} + +static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *_pwm) +{ + struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); + int ret; + + ret = tpu_pwm_timer_start(pwm); + if (ret < 0) + return ret; + + /* + * To avoid running the timer when not strictly required, handle 0% and + * 100% duty cycles as fixed levels and stop the timer. + */ + if (pwm->duty == 0 || pwm->duty == pwm->period) { + tpu_pwm_set_pin(pwm, pwm->duty ? + TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); + tpu_pwm_timer_stop(pwm); + } + + return 0; +} + +static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *_pwm) +{ + struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm); + + /* The timer must be running to modify the pin output configuration. */ + tpu_pwm_timer_start(pwm); + tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE); + tpu_pwm_timer_stop(pwm); +} + +static const struct pwm_ops tpu_pwm_ops = { + .request = tpu_pwm_request, + .free = tpu_pwm_free, + .config = tpu_pwm_config, + .set_polarity = tpu_pwm_set_polarity, + .enable = tpu_pwm_enable, + .disable = tpu_pwm_disable, + .owner = THIS_MODULE, +}; + +/* ----------------------------------------------------------------------------- + * Probe and remove + */ + +static int tpu_probe(struct platform_device *pdev) +{ + struct tpu_device *tpu; + struct resource *res; + int ret; + + tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL); + if (tpu == NULL) + return -ENOMEM; + + spin_lock_init(&tpu->lock); + tpu->pdev = pdev; + + /* Map memory, get clock and pin control. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + tpu->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tpu->base)) + return PTR_ERR(tpu->base); + + tpu->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(tpu->clk)) { + dev_err(&pdev->dev, "cannot get clock\n"); + return PTR_ERR(tpu->clk); + } + + /* Initialize and register the device. */ + platform_set_drvdata(pdev, tpu); + + tpu->chip.dev = &pdev->dev; + tpu->chip.ops = &tpu_pwm_ops; + tpu->chip.of_xlate = of_pwm_xlate_with_flags; + tpu->chip.of_pwm_n_cells = 3; + tpu->chip.base = -1; + tpu->chip.npwm = TPU_CHANNEL_MAX; + + ret = pwmchip_add(&tpu->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register PWM chip\n"); + return ret; + } + + dev_info(&pdev->dev, "TPU PWM %d registered\n", tpu->pdev->id); + + pm_runtime_enable(&pdev->dev); + + return 0; +} + +static int tpu_remove(struct platform_device *pdev) +{ + struct tpu_device *tpu = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&tpu->chip); + if (ret) + return ret; + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id tpu_of_table[] = { + { .compatible = "renesas,tpu-r8a73a4", }, + { .compatible = "renesas,tpu-r8a7740", }, + { .compatible = "renesas,tpu-r8a7790", }, + { .compatible = "renesas,tpu-sh7372", }, + { .compatible = "renesas,tpu", }, + { }, +}; + +MODULE_DEVICE_TABLE(of, tpu_of_table); +#endif + +static struct platform_driver tpu_driver = { + .probe = tpu_probe, + .remove = tpu_remove, + .driver = { + .name = "renesas-tpu-pwm", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(tpu_of_table), + } +}; + +module_platform_driver(tpu_driver); + +MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); +MODULE_DESCRIPTION("Renesas TPU PWM Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:renesas-tpu-pwm"); diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c index 5207e6cd864..ba6b650cf8d 100644 --- a/drivers/pwm/pwm-samsung.c +++ b/drivers/pwm/pwm-samsung.c @@ -1,355 +1,615 @@ -/* drivers/pwm/pwm-samsung.c - * +/* * Copyright (c) 2007 Ben Dooks * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> + * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> + * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> * - * S3C series PWM device core + * PWM driver for Samsung SoCs * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License. -*/ - -#define pr_fmt(fmt) "pwm-samsung: " fmt + */ +#include <linux/bitops.h> +#include <linux/clk.h> #include <linux/export.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/slab.h> #include <linux/err.h> -#include <linux/clk.h> #include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/pwm.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/time.h> -#include <mach/map.h> +/* For struct samsung_timer_variant and samsung_pwm_lock. */ +#include <clocksource/samsung_pwm.h> -#include <plat/regs-timer.h> +#define REG_TCFG0 0x00 +#define REG_TCFG1 0x04 +#define REG_TCON 0x08 -struct s3c_chip { - struct platform_device *pdev; +#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc)) +#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc)) - struct clk *clk_div; - struct clk *clk; - const char *label; +#define TCFG0_PRESCALER_MASK 0xff +#define TCFG0_PRESCALER1_SHIFT 8 - unsigned int period_ns; - unsigned int duty_ns; +#define TCFG1_MUX_MASK 0xf +#define TCFG1_SHIFT(chan) (4 * (chan)) - unsigned char tcon_base; - unsigned char pwm_id; - struct pwm_chip chip; +/* + * Each channel occupies 4 bits in TCON register, but there is a gap of 4 + * bits (one channel) after channel 0, so channels have different numbering + * when accessing TCON register. See to_tcon_channel() function. + * + * In addition, the location of autoreload bit for channel 4 (TCON channel 5) + * in its set of bits is 2 as opposed to 3 for other channels. + */ +#define TCON_START(chan) BIT(4 * (chan) + 0) +#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1) +#define TCON_INVERT(chan) BIT(4 * (chan) + 2) +#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3) +#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2) +#define TCON_AUTORELOAD(chan) \ + ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan)) + +/** + * struct samsung_pwm_channel - private data of PWM channel + * @period_ns: current period in nanoseconds programmed to the hardware + * @duty_ns: current duty time in nanoseconds programmed to the hardware + * @tin_ns: time of one timer tick in nanoseconds with current timer rate + */ +struct samsung_pwm_channel { + u32 period_ns; + u32 duty_ns; + u32 tin_ns; }; -#define to_s3c_chip(chip) container_of(chip, struct s3c_chip, chip) - -#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) +/** + * struct samsung_pwm_chip - private data of PWM chip + * @chip: generic PWM chip + * @variant: local copy of hardware variant data + * @inverter_mask: inverter status for all channels - one bit per channel + * @base: base address of mapped PWM registers + * @base_clk: base clock used to drive the timers + * @tclk0: external clock 0 (can be ERR_PTR if not present) + * @tclk1: external clock 1 (can be ERR_PTR if not present) + */ +struct samsung_pwm_chip { + struct pwm_chip chip; + struct samsung_pwm_variant variant; + u8 inverter_mask; + + void __iomem *base; + struct clk *base_clk; + struct clk *tclk0; + struct clk *tclk1; +}; -static struct clk *clk_scaler[2]; +#ifndef CONFIG_CLKSRC_SAMSUNG_PWM +/* + * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers + * and some registers need access synchronization. If both drivers are + * compiled in, the spinlock is defined in the clocksource driver, + * otherwise following definition is used. + * + * Currently we do not need any more complex synchronization method + * because all the supported SoCs contain only one instance of the PWM + * IP. Should this change, both drivers will need to be modified to + * properly synchronize accesses to particular instances. + */ +static DEFINE_SPINLOCK(samsung_pwm_lock); +#endif -static inline int pwm_is_tdiv(struct s3c_chip *chip) +static inline +struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip) { - return clk_get_parent(chip->clk) == chip->clk_div; + return container_of(chip, struct samsung_pwm_chip, chip); } -#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0)) -#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2)) -#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3)) -#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1)) +static inline unsigned int to_tcon_channel(unsigned int channel) +{ + /* TCON register has a gap of 4 bits (1 channel) after channel 0 */ + return (channel == 0) ? 0 : (channel + 1); +} -static int s3c_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm, + unsigned int channel, u8 divisor) { - struct s3c_chip *s3c = to_s3c_chip(chip); + u8 shift = TCFG1_SHIFT(channel); unsigned long flags; - unsigned long tcon; + u32 reg; + u8 bits; - local_irq_save(flags); + bits = (fls(divisor) - 1) - pwm->variant.div_base; - tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_start(s3c); - __raw_writel(tcon, S3C2410_TCON); + spin_lock_irqsave(&samsung_pwm_lock, flags); - local_irq_restore(flags); + reg = readl(pwm->base + REG_TCFG1); + reg &= ~(TCFG1_MUX_MASK << shift); + reg |= bits << shift; + writel(reg, pwm->base + REG_TCFG1); - return 0; + spin_unlock_irqrestore(&samsung_pwm_lock, flags); } -static void s3c_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan) { - struct s3c_chip *s3c = to_s3c_chip(chip); - unsigned long flags; - unsigned long tcon; + struct samsung_pwm_variant *variant = &chip->variant; + u32 reg; + + reg = readl(chip->base + REG_TCFG1); + reg >>= TCFG1_SHIFT(chan); + reg &= TCFG1_MUX_MASK; + + return (BIT(reg) & variant->tclk_mask) == 0; +} + +static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip, + unsigned int chan) +{ + unsigned long rate; + u32 reg; - local_irq_save(flags); + rate = clk_get_rate(chip->base_clk); - tcon = __raw_readl(S3C2410_TCON); - tcon &= ~pwm_tcon_start(s3c); - __raw_writel(tcon, S3C2410_TCON); + reg = readl(chip->base + REG_TCFG0); + if (chan >= 2) + reg >>= TCFG0_PRESCALER1_SHIFT; + reg &= TCFG0_PRESCALER_MASK; - local_irq_restore(flags); + return rate / (reg + 1); } -static unsigned long pwm_calc_tin(struct s3c_chip *s3c, unsigned long freq) +static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip, + unsigned int chan, unsigned long freq) { - unsigned long tin_parent_rate; - unsigned int div; + struct samsung_pwm_variant *variant = &chip->variant; + unsigned long rate; + struct clk *clk; + u8 div; + + if (!pwm_samsung_is_tdiv(chip, chan)) { + clk = (chan < 2) ? chip->tclk0 : chip->tclk1; + if (!IS_ERR(clk)) { + rate = clk_get_rate(clk); + if (rate) + return rate; + } + + dev_warn(chip->chip.dev, + "tclk of PWM %d is inoperational, using tdiv\n", chan); + } + + rate = pwm_samsung_get_tin_rate(chip, chan); + dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate); + + /* + * Compare minimum PWM frequency that can be achieved with possible + * divider settings and choose the lowest divisor that can generate + * frequencies lower than requested. + */ + for (div = variant->div_base; div < 4; ++div) + if ((rate >> (variant->bits + div)) < freq) + break; + + pwm_samsung_set_divisor(chip, chan, BIT(div)); + + return rate >> div; +} - tin_parent_rate = clk_get_rate(clk_get_parent(s3c->clk_div)); - pwm_dbg(s3c, "tin parent at %lu\n", tin_parent_rate); +static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + struct samsung_pwm_channel *our_chan; - for (div = 2; div <= 16; div *= 2) { - if ((tin_parent_rate / (div << 16)) < freq) - return tin_parent_rate / div; + if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { + dev_warn(chip->dev, + "tried to request PWM channel %d without output\n", + pwm->hwpwm); + return -EINVAL; } - return tin_parent_rate / 16; + our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL); + if (!our_chan) + return -ENOMEM; + + pwm_set_chip_data(pwm, our_chan); + + return 0; } -#define NS_IN_HZ (1000000000UL) +static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + devm_kfree(chip->dev, pwm_get_chip_data(pwm)); + pwm_set_chip_data(pwm, NULL); +} -static int s3c_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, - int duty_ns, int period_ns) +static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct s3c_chip *s3c = to_s3c_chip(chip); - unsigned long tin_rate; - unsigned long tin_ns; - unsigned long period; + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); unsigned long flags; - unsigned long tcon; - unsigned long tcnt; - long tcmp; + u32 tcon; - /* We currently avoid using 64bit arithmetic by using the - * fact that anything faster than 1Hz is easily representable - * by 32bits. */ + spin_lock_irqsave(&samsung_pwm_lock, flags); + + tcon = readl(our_chip->base + REG_TCON); + + tcon &= ~TCON_START(tcon_chan); + tcon |= TCON_MANUALUPDATE(tcon_chan); + writel(tcon, our_chip->base + REG_TCON); + + tcon &= ~TCON_MANUALUPDATE(tcon_chan); + tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan); + writel(tcon, our_chip->base + REG_TCON); + + spin_unlock_irqrestore(&samsung_pwm_lock, flags); + + return 0; +} - if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) +static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); + unsigned long flags; + u32 tcon; + + spin_lock_irqsave(&samsung_pwm_lock, flags); + + tcon = readl(our_chip->base + REG_TCON); + tcon &= ~TCON_AUTORELOAD(tcon_chan); + writel(tcon, our_chip->base + REG_TCON); + + spin_unlock_irqrestore(&samsung_pwm_lock, flags); +} + +static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); + u32 tin_ns = chan->tin_ns, tcnt, tcmp; + + /* + * We currently avoid using 64bit arithmetic by using the + * fact that anything faster than 1Hz is easily representable + * by 32bits. + */ + if (period_ns > NSEC_PER_SEC) return -ERANGE; - if (period_ns == s3c->period_ns && - duty_ns == s3c->duty_ns) + if (period_ns == chan->period_ns && duty_ns == chan->duty_ns) return 0; - /* The TCMP and TCNT can be read without a lock, they're not - * shared between the timers. */ - - tcmp = __raw_readl(S3C2410_TCMPB(s3c->pwm_id)); - tcnt = __raw_readl(S3C2410_TCNTB(s3c->pwm_id)); + tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); - period = NS_IN_HZ / period_ns; + /* We need tick count for calculation, not last tick. */ + ++tcnt; - pwm_dbg(s3c, "duty_ns=%d, period_ns=%d (%lu)\n", - duty_ns, period_ns, period); + /* Check to see if we are changing the clock rate of the PWM. */ + if (chan->period_ns != period_ns) { + unsigned long tin_rate; + u32 period; - /* Check to see if we are changing the clock rate of the PWM */ + period = NSEC_PER_SEC / period_ns; - if (s3c->period_ns != period_ns) { - if (pwm_is_tdiv(s3c)) { - tin_rate = pwm_calc_tin(s3c, period); - clk_set_rate(s3c->clk_div, tin_rate); - } else - tin_rate = clk_get_rate(s3c->clk); + dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n", + duty_ns, period_ns, period); - s3c->period_ns = period_ns; + tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period); - pwm_dbg(s3c, "tin_rate=%lu\n", tin_rate); + dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate); - tin_ns = NS_IN_HZ / tin_rate; + tin_ns = NSEC_PER_SEC / tin_rate; tcnt = period_ns / tin_ns; - } else - tin_ns = NS_IN_HZ / clk_get_rate(s3c->clk); + } - /* Note, counters count down */ + /* Period is too short. */ + if (tcnt <= 1) + return -ERANGE; + /* Note that counters count down. */ tcmp = duty_ns / tin_ns; + + /* 0% duty is not available */ + if (!tcmp) + ++tcmp; + tcmp = tcnt - tcmp; - /* the pwm hw only checks the compare register after a decrement, - so the pin never toggles if tcmp = tcnt */ - if (tcmp == tcnt) - tcmp--; - pwm_dbg(s3c, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); + /* Decrement to get tick numbers, instead of tick counts. */ + --tcnt; + /* -1UL will give 100% duty. */ + --tcmp; + + dev_dbg(our_chip->chip.dev, + "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt); + + /* Update PWM registers. */ + writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm)); + writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm)); + + chan->period_ns = period_ns; + chan->tin_ns = tin_ns; + chan->duty_ns = duty_ns; + + return 0; +} + +static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip, + unsigned int channel, bool invert) +{ + unsigned int tcon_chan = to_tcon_channel(channel); + unsigned long flags; + u32 tcon; - if (tcmp < 0) - tcmp = 0; + spin_lock_irqsave(&samsung_pwm_lock, flags); - /* Update the PWM register block. */ + tcon = readl(chip->base + REG_TCON); - local_irq_save(flags); + if (invert) { + chip->inverter_mask |= BIT(channel); + tcon |= TCON_INVERT(tcon_chan); + } else { + chip->inverter_mask &= ~BIT(channel); + tcon &= ~TCON_INVERT(tcon_chan); + } - __raw_writel(tcmp, S3C2410_TCMPB(s3c->pwm_id)); - __raw_writel(tcnt, S3C2410_TCNTB(s3c->pwm_id)); + writel(tcon, chip->base + REG_TCON); - tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_manulupdate(s3c); - tcon |= pwm_tcon_autoreload(s3c); - __raw_writel(tcon, S3C2410_TCON); + spin_unlock_irqrestore(&samsung_pwm_lock, flags); +} - tcon &= ~pwm_tcon_manulupdate(s3c); - __raw_writel(tcon, S3C2410_TCON); +static int pwm_samsung_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); + bool invert = (polarity == PWM_POLARITY_NORMAL); - local_irq_restore(flags); + /* Inverted means normal in the hardware. */ + pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert); return 0; } -static struct pwm_ops s3c_pwm_ops = { - .enable = s3c_pwm_enable, - .disable = s3c_pwm_disable, - .config = s3c_pwm_config, - .owner = THIS_MODULE, +static const struct pwm_ops pwm_samsung_ops = { + .request = pwm_samsung_request, + .free = pwm_samsung_free, + .enable = pwm_samsung_enable, + .disable = pwm_samsung_disable, + .config = pwm_samsung_config, + .set_polarity = pwm_samsung_set_polarity, + .owner = THIS_MODULE, +}; + +#ifdef CONFIG_OF +static const struct samsung_pwm_variant s3c24xx_variant = { + .bits = 16, + .div_base = 1, + .has_tint_cstat = false, + .tclk_mask = BIT(4), }; -static int s3c_pwm_probe(struct platform_device *pdev) +static const struct samsung_pwm_variant s3c64xx_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = BIT(7) | BIT(6) | BIT(5), +}; + +static const struct samsung_pwm_variant s5p64x0_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = 0, +}; + +static const struct samsung_pwm_variant s5pc100_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = BIT(5), +}; + +static const struct of_device_id samsung_pwm_matches[] = { + { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant }, + { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant }, + { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant }, + { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant }, + { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant }, + {}, +}; + +static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) +{ + struct device_node *np = chip->chip.dev->of_node; + const struct of_device_id *match; + struct property *prop; + const __be32 *cur; + u32 val; + + match = of_match_node(samsung_pwm_matches, np); + if (!match) + return -ENODEV; + + memcpy(&chip->variant, match->data, sizeof(chip->variant)); + + of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { + if (val >= SAMSUNG_PWM_NUM) { + dev_err(chip->chip.dev, + "%s: invalid channel index in samsung,pwm-outputs property\n", + __func__); + continue; + } + chip->variant.output_mask |= BIT(val); + } + + return 0; +} +#else +static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) +{ + return -ENODEV; +} +#endif + +static int pwm_samsung_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct s3c_chip *s3c; - unsigned long flags; - unsigned long tcon; - unsigned int id = pdev->id; + struct samsung_pwm_chip *chip; + struct resource *res; + unsigned int chan; int ret; - if (id == 4) { - dev_err(dev, "TIMER4 is currently not supported\n"); - return -ENXIO; - } - - s3c = devm_kzalloc(&pdev->dev, sizeof(*s3c), GFP_KERNEL); - if (s3c == NULL) { - dev_err(dev, "failed to allocate pwm_device\n"); + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (chip == NULL) return -ENOMEM; - } - /* calculate base of control bits in TCON */ - s3c->tcon_base = id == 0 ? 0 : (id * 4) + 4; - s3c->pwm_id = id; - s3c->chip.dev = &pdev->dev; - s3c->chip.ops = &s3c_pwm_ops; - s3c->chip.base = -1; - s3c->chip.npwm = 1; - - s3c->clk = devm_clk_get(dev, "pwm-tin"); - if (IS_ERR(s3c->clk)) { - dev_err(dev, "failed to get pwm tin clk\n"); - return PTR_ERR(s3c->clk); + chip->chip.dev = &pdev->dev; + chip->chip.ops = &pwm_samsung_ops; + chip->chip.base = -1; + chip->chip.npwm = SAMSUNG_PWM_NUM; + chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1; + + if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { + ret = pwm_samsung_parse_dt(chip); + if (ret) + return ret; + + chip->chip.of_xlate = of_pwm_xlate_with_flags; + chip->chip.of_pwm_n_cells = 3; + } else { + if (!pdev->dev.platform_data) { + dev_err(&pdev->dev, "no platform data specified\n"); + return -EINVAL; + } + + memcpy(&chip->variant, pdev->dev.platform_data, + sizeof(chip->variant)); } - s3c->clk_div = devm_clk_get(dev, "pwm-tdiv"); - if (IS_ERR(s3c->clk_div)) { - dev_err(dev, "failed to get pwm tdiv clk\n"); - return PTR_ERR(s3c->clk_div); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + chip->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(chip->base)) + return PTR_ERR(chip->base); + + chip->base_clk = devm_clk_get(&pdev->dev, "timers"); + if (IS_ERR(chip->base_clk)) { + dev_err(dev, "failed to get timer base clk\n"); + return PTR_ERR(chip->base_clk); } - clk_enable(s3c->clk); - clk_enable(s3c->clk_div); + ret = clk_prepare_enable(chip->base_clk); + if (ret < 0) { + dev_err(dev, "failed to enable base clock\n"); + return ret; + } - local_irq_save(flags); + for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) + if (chip->variant.output_mask & BIT(chan)) + pwm_samsung_set_invert(chip, chan, true); - tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_invert(s3c); - __raw_writel(tcon, S3C2410_TCON); + /* Following clocks are optional. */ + chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0"); + chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1"); - local_irq_restore(flags); + platform_set_drvdata(pdev, chip); - ret = pwmchip_add(&s3c->chip); + ret = pwmchip_add(&chip->chip); if (ret < 0) { - dev_err(dev, "failed to register pwm\n"); - goto err_clk_tdiv; + dev_err(dev, "failed to register PWM chip\n"); + clk_disable_unprepare(chip->base_clk); + return ret; } - pwm_dbg(s3c, "config bits %02x\n", - (__raw_readl(S3C2410_TCON) >> s3c->tcon_base) & 0x0f); - - dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n", - clk_get_rate(s3c->clk), - clk_get_rate(s3c->clk_div), - pwm_is_tdiv(s3c) ? "div" : "ext", s3c->tcon_base); + dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n", + clk_get_rate(chip->base_clk), + !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0, + !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0); - platform_set_drvdata(pdev, s3c); return 0; - - err_clk_tdiv: - clk_disable(s3c->clk_div); - clk_disable(s3c->clk); - return ret; } -static int s3c_pwm_remove(struct platform_device *pdev) +static int pwm_samsung_remove(struct platform_device *pdev) { - struct s3c_chip *s3c = platform_get_drvdata(pdev); - int err; + struct samsung_pwm_chip *chip = platform_get_drvdata(pdev); + int ret; - err = pwmchip_remove(&s3c->chip); - if (err < 0) - return err; + ret = pwmchip_remove(&chip->chip); + if (ret < 0) + return ret; - clk_disable(s3c->clk_div); - clk_disable(s3c->clk); + clk_disable_unprepare(chip->base_clk); return 0; } -#ifdef CONFIG_PM -static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state) +#ifdef CONFIG_PM_SLEEP +static int pwm_samsung_suspend(struct device *dev) { - struct s3c_chip *s3c = platform_get_drvdata(pdev); + struct samsung_pwm_chip *chip = dev_get_drvdata(dev); + unsigned int i; - /* No one preserve these values during suspend so reset them - * Otherwise driver leaves PWM unconfigured if same values - * passed to pwm_config + /* + * No one preserves these values during suspend so reset them. + * Otherwise driver leaves PWM unconfigured if same values are + * passed to pwm_config() next time. */ - s3c->period_ns = 0; - s3c->duty_ns = 0; + for (i = 0; i < SAMSUNG_PWM_NUM; ++i) { + struct pwm_device *pwm = &chip->chip.pwms[i]; + struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); + + if (!chan) + continue; + + chan->period_ns = 0; + chan->duty_ns = 0; + } return 0; } -static int s3c_pwm_resume(struct platform_device *pdev) +static int pwm_samsung_resume(struct device *dev) { - struct s3c_chip *s3c = platform_get_drvdata(pdev); - unsigned long tcon; + struct samsung_pwm_chip *chip = dev_get_drvdata(dev); + unsigned int chan; - /* Restore invertion */ - tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_invert(s3c); - __raw_writel(tcon, S3C2410_TCON); + /* + * Inverter setting must be preserved across suspend/resume + * as nobody really seems to configure it more than once. + */ + for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) { + if (chip->variant.output_mask & BIT(chan)) + pwm_samsung_set_invert(chip, chan, + chip->inverter_mask & BIT(chan)); + } return 0; } - -#else -#define s3c_pwm_suspend NULL -#define s3c_pwm_resume NULL #endif -static struct platform_driver s3c_pwm_driver = { +static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, pwm_samsung_suspend, + pwm_samsung_resume); + +static struct platform_driver pwm_samsung_driver = { .driver = { - .name = "s3c24xx-pwm", + .name = "samsung-pwm", .owner = THIS_MODULE, + .pm = &pwm_samsung_pm_ops, + .of_match_table = of_match_ptr(samsung_pwm_matches), }, - .probe = s3c_pwm_probe, - .remove = s3c_pwm_remove, - .suspend = s3c_pwm_suspend, - .resume = s3c_pwm_resume, + .probe = pwm_samsung_probe, + .remove = pwm_samsung_remove, }; +module_platform_driver(pwm_samsung_driver); -static int __init pwm_init(void) -{ - int ret; - - clk_scaler[0] = clk_get(NULL, "pwm-scaler0"); - clk_scaler[1] = clk_get(NULL, "pwm-scaler1"); - - if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) { - pr_err("failed to get scaler clocks\n"); - return -EINVAL; - } - - ret = platform_driver_register(&s3c_pwm_driver); - if (ret) - pr_err("failed to add pwm driver\n"); - - return ret; -} - -arch_initcall(pwm_init); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>"); +MODULE_ALIAS("platform:samsung-pwm"); diff --git a/drivers/pwm/pwm-spear.c b/drivers/pwm/pwm-spear.c index 83b21d9d5cf..6fd93e6a412 100644 --- a/drivers/pwm/pwm-spear.c +++ b/drivers/pwm/pwm-spear.c @@ -2,7 +2,7 @@ * ST Microelectronics SPEAr Pulse Width Modulator driver * * Copyright (C) 2012 ST Microelectronics - * Shiraz Hashim <shiraz.hashim@st.com> + * Shiraz Hashim <shiraz.linux.kernel@gmail.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -49,13 +49,11 @@ * @mmio_base: base address of pwm chip * @clk: pointer to clk structure of pwm chip * @chip: linux pwm chip representation - * @dev: pointer to device structure of pwm chip */ struct spear_pwm_chip { void __iomem *mmio_base; struct clk *clk; struct pwm_chip chip; - struct device *dev; }; static inline struct spear_pwm_chip *to_spear_pwm_chip(struct pwm_chip *chip) @@ -143,7 +141,7 @@ static int spear_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) u32 val; rc = clk_enable(pc->clk); - if (!rc) + if (rc) return rc; val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); @@ -180,27 +178,19 @@ static int spear_pwm_probe(struct platform_device *pdev) int ret; u32 val; - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) { - dev_err(&pdev->dev, "no memory resources defined\n"); - return -ENODEV; - } - pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); - if (!pc) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + if (!pc) return -ENOMEM; - } - pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r); - if (!pc->mmio_base) - return -EADDRNOTAVAIL; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(pc->mmio_base)) + return PTR_ERR(pc->mmio_base); pc->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(pc->clk)) return PTR_ERR(pc->clk); - pc->dev = &pdev->dev; platform_set_drvdata(pdev, pc); pc->chip.dev = &pdev->dev; @@ -209,12 +199,12 @@ static int spear_pwm_probe(struct platform_device *pdev) pc->chip.npwm = NUM_PWM; ret = clk_prepare(pc->clk); - if (!ret) + if (ret) return ret; if (of_device_is_compatible(np, "st,spear1340-pwm")) { ret = clk_enable(pc->clk); - if (!ret) { + if (ret) { clk_unprepare(pc->clk); return ret; } @@ -230,7 +220,7 @@ static int spear_pwm_probe(struct platform_device *pdev) } ret = pwmchip_add(&pc->chip); - if (!ret) { + if (ret < 0) { clk_unprepare(pc->clk); dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); } @@ -251,7 +241,7 @@ static int spear_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&pc->chip); } -static struct of_device_id spear_pwm_of_match[] = { +static const struct of_device_id spear_pwm_of_match[] = { { .compatible = "st,spear320-pwm" }, { .compatible = "st,spear1340-pwm" }, { } @@ -262,6 +252,7 @@ MODULE_DEVICE_TABLE(of, spear_pwm_of_match); static struct platform_driver spear_pwm_driver = { .driver = { .name = "spear-pwm", + .owner = THIS_MODULE, .of_match_table = spear_pwm_of_match, }, .probe = spear_pwm_probe, @@ -271,6 +262,6 @@ static struct platform_driver spear_pwm_driver = { module_platform_driver(spear_pwm_driver); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Shiraz Hashim <shiraz.hashim@st.com>"); +MODULE_AUTHOR("Shiraz Hashim <shiraz.linux.kernel@gmail.com>"); MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.com>"); MODULE_ALIAS("platform:spear-pwm"); diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 30c0e2b70ce..61d86b9498c 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -173,22 +173,15 @@ static int tegra_pwm_probe(struct platform_device *pdev) int ret; pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); - if (!pwm) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + if (!pwm) return -ENOMEM; - } pwm->dev = &pdev->dev; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) { - dev_err(&pdev->dev, "no memory resources defined\n"); - return -ENODEV; - } - - pwm->mmio_base = devm_request_and_ioremap(&pdev->dev, r); - if (!pwm->mmio_base) - return -EADDRNOTAVAIL; + pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(pwm->mmio_base)) + return PTR_ERR(pwm->mmio_base); platform_set_drvdata(pdev, pwm); @@ -233,20 +226,19 @@ static int tegra_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&pc->chip); } -#ifdef CONFIG_OF -static struct of_device_id tegra_pwm_of_match[] = { +static const struct of_device_id tegra_pwm_of_match[] = { { .compatible = "nvidia,tegra20-pwm" }, { .compatible = "nvidia,tegra30-pwm" }, { } }; MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); -#endif static struct platform_driver tegra_pwm_driver = { .driver = { .name = "tegra-pwm", - .of_match_table = of_match_ptr(tegra_pwm_of_match), + .owner = THIS_MODULE, + .of_match_table = tegra_pwm_of_match, }, .probe = tegra_pwm_probe, .remove = tegra_pwm_remove, diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c index 5cf016dd982..74efbe7f20c 100644 --- a/drivers/pwm/pwm-tiecap.c +++ b/drivers/pwm/pwm-tiecap.c @@ -26,7 +26,6 @@ #include <linux/pm_runtime.h> #include <linux/pwm.h> #include <linux/of_device.h> -#include <linux/pinctrl/consumer.h> #include "pwm-tipwmss.h" @@ -41,10 +40,17 @@ #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6)) #define ECCTL2_TSCTR_FREERUN BIT(4) +struct ecap_context { + u32 cap3; + u32 cap4; + u16 ecctl2; +}; + struct ecap_pwm_chip { struct pwm_chip chip; unsigned int clk_rate; void __iomem *mmio_base; + struct ecap_context ctx; }; static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip) @@ -201,17 +207,10 @@ static int ecap_pwm_probe(struct platform_device *pdev) struct clk *clk; struct ecap_pwm_chip *pc; u16 status; - struct pinctrl *pinctrl; - - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - if (IS_ERR(pinctrl)) - dev_warn(&pdev->dev, "unable to select pin group\n"); pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); - if (!pc) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + if (!pc) return -ENOMEM; - } clk = devm_clk_get(&pdev->dev, "fck"); if (IS_ERR(clk)) { @@ -233,14 +232,9 @@ static int ecap_pwm_probe(struct platform_device *pdev) pc->chip.npwm = 1; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) { - dev_err(&pdev->dev, "no memory resource defined\n"); - return -ENODEV; - } - - pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r); - if (!pc->mmio_base) - return -EADDRNOTAVAIL; + pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(pc->mmio_base)) + return PTR_ERR(pc->mmio_base); ret = pwmchip_add(&pc->chip); if (ret < 0) { @@ -283,16 +277,63 @@ static int ecap_pwm_remove(struct platform_device *pdev) pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ); pm_runtime_put_sync(&pdev->dev); - pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); return pwmchip_remove(&pc->chip); } +#ifdef CONFIG_PM_SLEEP +static void ecap_pwm_save_context(struct ecap_pwm_chip *pc) +{ + pm_runtime_get_sync(pc->chip.dev); + pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2); + pc->ctx.cap4 = readl(pc->mmio_base + CAP4); + pc->ctx.cap3 = readl(pc->mmio_base + CAP3); + pm_runtime_put_sync(pc->chip.dev); +} + +static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc) +{ + writel(pc->ctx.cap3, pc->mmio_base + CAP3); + writel(pc->ctx.cap4, pc->mmio_base + CAP4); + writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2); +} + +static int ecap_pwm_suspend(struct device *dev) +{ + struct ecap_pwm_chip *pc = dev_get_drvdata(dev); + struct pwm_device *pwm = pc->chip.pwms; + + ecap_pwm_save_context(pc); + + /* Disable explicitly if PWM is running */ + if (test_bit(PWMF_ENABLED, &pwm->flags)) + pm_runtime_put_sync(dev); + + return 0; +} + +static int ecap_pwm_resume(struct device *dev) +{ + struct ecap_pwm_chip *pc = dev_get_drvdata(dev); + struct pwm_device *pwm = pc->chip.pwms; + + /* Enable explicitly if PWM was running */ + if (test_bit(PWMF_ENABLED, &pwm->flags)) + pm_runtime_get_sync(dev); + + ecap_pwm_restore_context(pc); + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume); + static struct platform_driver ecap_pwm_driver = { .driver = { .name = "ecap", .owner = THIS_MODULE, .of_match_table = ecap_of_match, + .pm = &ecap_pwm_pm_ops, }, .probe = ecap_pwm_probe, .remove = ecap_pwm_remove, diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 72a6dd40c9e..cb75133085a 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -26,7 +26,6 @@ #include <linux/clk.h> #include <linux/pm_runtime.h> #include <linux/of_device.h> -#include <linux/pinctrl/consumer.h> #include "pwm-tipwmss.h" @@ -113,6 +112,17 @@ #define NUM_PWM_CHANNEL 2 /* EHRPWM channels */ +struct ehrpwm_context { + u16 tbctl; + u16 tbprd; + u16 cmpa; + u16 cmpb; + u16 aqctla; + u16 aqctlb; + u16 aqsfrc; + u16 aqcsfrc; +}; + struct ehrpwm_pwm_chip { struct pwm_chip chip; unsigned int clk_rate; @@ -120,6 +130,7 @@ struct ehrpwm_pwm_chip { unsigned long period_cycles[NUM_PWM_CHANNEL]; enum pwm_polarity polarity[NUM_PWM_CHANNEL]; struct clk *tbclk; + struct ehrpwm_context ctx; }; static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) @@ -127,12 +138,17 @@ static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) return container_of(chip, struct ehrpwm_pwm_chip, chip); } -static void ehrpwm_write(void *base, int offset, unsigned int val) +static inline u16 ehrpwm_read(void __iomem *base, int offset) +{ + return readw(base + offset); +} + +static inline void ehrpwm_write(void __iomem *base, int offset, unsigned int val) { writew(val & 0xFFFF, base + offset); } -static void ehrpwm_modify(void *base, int offset, +static void ehrpwm_modify(void __iomem *base, int offset, unsigned short mask, unsigned short val) { unsigned short regval; @@ -318,6 +334,7 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); unsigned short aqcsfrc_val, aqcsfrc_mask; + int ret; /* Leave clock enabled on enabling PWM */ pm_runtime_get_sync(chip->dev); @@ -341,7 +358,12 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) configure_polarity(pc, pwm->hwpwm); /* Enable TBCLK before enabling PWM device */ - clk_enable(pc->tbclk); + ret = clk_enable(pc->tbclk); + if (ret) { + dev_err(chip->dev, "Failed to enable TBCLK for %s\n", + dev_name(pc->chip.dev)); + return ret; + } /* Enable time counter for free_run */ ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN); @@ -416,17 +438,10 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev) struct clk *clk; struct ehrpwm_pwm_chip *pc; u16 status; - struct pinctrl *pinctrl; - - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - if (IS_ERR(pinctrl)) - dev_warn(&pdev->dev, "unable to select pin group\n"); pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); - if (!pc) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + if (!pc) return -ENOMEM; - } clk = devm_clk_get(&pdev->dev, "fck"); if (IS_ERR(clk)) { @@ -448,14 +463,9 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev) pc->chip.npwm = NUM_PWM_CHANNEL; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) { - dev_err(&pdev->dev, "no memory resource defined\n"); - return -ENODEV; - } - - pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r); - if (!pc->mmio_base) - return -EADDRNOTAVAIL; + pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(pc->mmio_base)) + return PTR_ERR(pc->mmio_base); /* Acquire tbclk for Time Base EHRPWM submodule */ pc->tbclk = devm_clk_get(&pdev->dev, "tbclk"); @@ -464,6 +474,12 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev) return PTR_ERR(pc->tbclk); } + ret = clk_prepare(pc->tbclk); + if (ret < 0) { + dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret); + return ret; + } + ret = pwmchip_add(&pc->chip); if (ret < 0) { dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); @@ -490,6 +506,7 @@ pwmss_clk_failure: pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); pwmchip_remove(&pc->chip); + clk_unprepare(pc->tbclk); return ret; } @@ -497,6 +514,8 @@ static int ehrpwm_pwm_remove(struct platform_device *pdev) { struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev); + clk_unprepare(pc->tbclk); + pm_runtime_get_sync(&pdev->dev); /* * Due to hardware misbehaviour, acknowledge of the stop_req @@ -510,11 +529,79 @@ static int ehrpwm_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&pc->chip); } +#ifdef CONFIG_PM_SLEEP +static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc) +{ + pm_runtime_get_sync(pc->chip.dev); + pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL); + pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD); + pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA); + pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB); + pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA); + pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB); + pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC); + pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC); + pm_runtime_put_sync(pc->chip.dev); +} + +static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc) +{ + ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd); + ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa); + ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb); + ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla); + ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb); + ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc); + ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc); + ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl); +} + +static int ehrpwm_pwm_suspend(struct device *dev) +{ + struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); + int i; + + ehrpwm_pwm_save_context(pc); + for (i = 0; i < pc->chip.npwm; i++) { + struct pwm_device *pwm = &pc->chip.pwms[i]; + + if (!test_bit(PWMF_ENABLED, &pwm->flags)) + continue; + + /* Disable explicitly if PWM is running */ + pm_runtime_put_sync(dev); + } + return 0; +} + +static int ehrpwm_pwm_resume(struct device *dev) +{ + struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); + int i; + + for (i = 0; i < pc->chip.npwm; i++) { + struct pwm_device *pwm = &pc->chip.pwms[i]; + + if (!test_bit(PWMF_ENABLED, &pwm->flags)) + continue; + + /* Enable explicitly if PWM was running */ + pm_runtime_get_sync(dev); + } + ehrpwm_pwm_restore_context(pc); + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend, + ehrpwm_pwm_resume); + static struct platform_driver ehrpwm_pwm_driver = { .driver = { .name = "ehrpwm", .owner = THIS_MODULE, .of_match_table = ehrpwm_of_match, + .pm = &ehrpwm_pwm_pm_ops, }, .probe = ehrpwm_pwm_probe, .remove = ehrpwm_pwm_remove, diff --git a/drivers/pwm/pwm-tipwmss.c b/drivers/pwm/pwm-tipwmss.c index 3448a1c8859..3b119bc2c3c 100644 --- a/drivers/pwm/pwm-tipwmss.c +++ b/drivers/pwm/pwm-tipwmss.c @@ -70,14 +70,9 @@ static int pwmss_probe(struct platform_device *pdev) mutex_init(&info->pwmss_lock); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) { - dev_err(&pdev->dev, "no memory resource defined\n"); - return -ENODEV; - } - - info->mmio_base = devm_request_and_ioremap(&pdev->dev, r); - if (!info->mmio_base) - return -EADDRNOTAVAIL; + info->mmio_base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(info->mmio_base)) + return PTR_ERR(info->mmio_base); pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); @@ -101,6 +96,7 @@ static int pwmss_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM_SLEEP static int pwmss_suspend(struct device *dev) { struct pwmss_info *info = dev_get_drvdata(dev); @@ -118,6 +114,7 @@ static int pwmss_resume(struct device *dev) writew(info->pwmss_clkconfig, info->mmio_base + PWMSS_CLKCONFIG); return 0; } +#endif static SIMPLE_DEV_PM_OPS(pwmss_pm_ops, pwmss_suspend, pwmss_resume); diff --git a/drivers/pwm/pwm-tipwmss.h b/drivers/pwm/pwm-tipwmss.h index 11f76a1e266..10ad8040408 100644 --- a/drivers/pwm/pwm-tipwmss.h +++ b/drivers/pwm/pwm-tipwmss.h @@ -18,7 +18,6 @@ #ifndef __TIPWMSS_H #define __TIPWMSS_H -#ifdef CONFIG_PWM_TIPWMSS /* PWM substem clock gating */ #define PWMSS_ECAPCLK_EN BIT(0) #define PWMSS_ECAPCLK_STOP_REQ BIT(1) @@ -28,6 +27,7 @@ #define PWMSS_ECAPCLK_EN_ACK BIT(0) #define PWMSS_EPWMCLK_EN_ACK BIT(8) +#ifdef CONFIG_PWM_TIPWMSS extern u16 pwmss_submodule_state_change(struct device *dev, int set); #else static inline u16 pwmss_submodule_state_change(struct device *dev, int set) diff --git a/drivers/pwm/pwm-twl-led.c b/drivers/pwm/pwm-twl-led.c index 9dfa0f3eca3..b964470025c 100644 --- a/drivers/pwm/pwm-twl-led.c +++ b/drivers/pwm/pwm-twl-led.c @@ -21,6 +21,7 @@ */ #include <linux/module.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/pwm.h> #include <linux/i2c/twl.h> @@ -271,6 +272,7 @@ static const struct pwm_ops twl4030_pwmled_ops = { .enable = twl4030_pwmled_enable, .disable = twl4030_pwmled_disable, .config = twl4030_pwmled_config, + .owner = THIS_MODULE, }; static const struct pwm_ops twl6030_pwmled_ops = { @@ -279,6 +281,7 @@ static const struct pwm_ops twl6030_pwmled_ops = { .config = twl6030_pwmled_config, .request = twl6030_pwmled_request, .free = twl6030_pwmled_free, + .owner = THIS_MODULE, }; static int twl_pwmled_probe(struct platform_device *pdev) @@ -300,6 +303,7 @@ static int twl_pwmled_probe(struct platform_device *pdev) twl->chip.dev = &pdev->dev; twl->chip.base = -1; + twl->chip.can_sleep = true; mutex_init(&twl->mutex); @@ -320,7 +324,7 @@ static int twl_pwmled_remove(struct platform_device *pdev) } #ifdef CONFIG_OF -static struct of_device_id twl_pwmled_of_match[] = { +static const struct of_device_id twl_pwmled_of_match[] = { { .compatible = "ti,twl4030-pwmled" }, { .compatible = "ti,twl6030-pwmled" }, { }, diff --git a/drivers/pwm/pwm-twl.c b/drivers/pwm/pwm-twl.c index e65db95d5e5..04f76725d59 100644 --- a/drivers/pwm/pwm-twl.c +++ b/drivers/pwm/pwm-twl.c @@ -18,6 +18,7 @@ */ #include <linux/module.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/pwm.h> #include <linux/i2c/twl.h> @@ -200,8 +201,7 @@ out: static void twl4030_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) { - struct twl_pwm_chip *twl = container_of(chip, struct twl_pwm_chip, - chip); + struct twl_pwm_chip *twl = to_twl(chip); int ret; u8 val, mask; @@ -231,8 +231,7 @@ out: static int twl6030_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct twl_pwm_chip *twl = container_of(chip, struct twl_pwm_chip, - chip); + struct twl_pwm_chip *twl = to_twl(chip); int ret; u8 val; @@ -250,13 +249,12 @@ static int twl6030_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) twl->twl6030_toggle3 = val; out: mutex_unlock(&twl->mutex); - return 0; + return ret; } static void twl6030_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct twl_pwm_chip *twl = container_of(chip, struct twl_pwm_chip, - chip); + struct twl_pwm_chip *twl = to_twl(chip); int ret; u8 val; @@ -267,14 +265,6 @@ static void twl6030_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG); if (ret < 0) { - dev_err(chip->dev, "%s: Failed to read TOGGLE3\n", pwm->label); - goto out; - } - - val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); - - ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG); - if (ret < 0) { dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label); goto out; } @@ -290,12 +280,14 @@ static const struct pwm_ops twl4030_pwm_ops = { .disable = twl4030_pwm_disable, .request = twl4030_pwm_request, .free = twl4030_pwm_free, + .owner = THIS_MODULE, }; static const struct pwm_ops twl6030_pwm_ops = { .config = twl_pwm_config, .enable = twl6030_pwm_enable, .disable = twl6030_pwm_disable, + .owner = THIS_MODULE, }; static int twl_pwm_probe(struct platform_device *pdev) @@ -315,6 +307,7 @@ static int twl_pwm_probe(struct platform_device *pdev) twl->chip.dev = &pdev->dev; twl->chip.base = -1; twl->chip.npwm = 2; + twl->chip.can_sleep = true; mutex_init(&twl->mutex); @@ -335,7 +328,7 @@ static int twl_pwm_remove(struct platform_device *pdev) } #ifdef CONFIG_OF -static struct of_device_id twl_pwm_of_match[] = { +static const struct of_device_id twl_pwm_of_match[] = { { .compatible = "ti,twl4030-pwm" }, { .compatible = "ti,twl6030-pwm" }, { }, diff --git a/drivers/pwm/pwm-vt8500.c b/drivers/pwm/pwm-vt8500.c index b0ba2d40343..652e6b5b859 100644 --- a/drivers/pwm/pwm-vt8500.c +++ b/drivers/pwm/pwm-vt8500.c @@ -36,6 +36,25 @@ */ #define VT8500_NR_PWMS 2 +#define REG_CTRL(pwm) (((pwm) << 4) + 0x00) +#define REG_SCALAR(pwm) (((pwm) << 4) + 0x04) +#define REG_PERIOD(pwm) (((pwm) << 4) + 0x08) +#define REG_DUTY(pwm) (((pwm) << 4) + 0x0C) +#define REG_STATUS 0x40 + +#define CTRL_ENABLE BIT(0) +#define CTRL_INVERT BIT(1) +#define CTRL_AUTOLOAD BIT(2) +#define CTRL_STOP_IMM BIT(3) +#define CTRL_LOAD_PRESCALE BIT(4) +#define CTRL_LOAD_PERIOD BIT(5) + +#define STATUS_CTRL_UPDATE BIT(0) +#define STATUS_SCALAR_UPDATE BIT(1) +#define STATUS_PERIOD_UPDATE BIT(2) +#define STATUS_DUTY_UPDATE BIT(3) +#define STATUS_ALL_UPDATE 0x0F + struct vt8500_chip { struct pwm_chip chip; void __iomem *base; @@ -45,15 +64,17 @@ struct vt8500_chip { #define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip) #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) -static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask) +static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask) { int loops = msecs_to_loops(10); - while ((readb(reg) & bitmask) && --loops) + u32 mask = bitmask << (nr << 8); + + while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) cpu_relax(); if (unlikely(!loops)) - pr_warn("Waiting for status bits 0x%x to clear timed out\n", - bitmask); + dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n", + mask); } static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -63,6 +84,7 @@ static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, unsigned long long c; unsigned long period_cycles, prescale, pv, dc; int err; + u32 val; err = clk_enable(vt8500->clk); if (err < 0) { @@ -91,14 +113,19 @@ static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, do_div(c, period_ns); dc = c; - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 1)); - writel(prescale, vt8500->base + 0x4 + (pwm->hwpwm << 4)); + writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE); + + writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE); - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 2)); - writel(pv, vt8500->base + 0x8 + (pwm->hwpwm << 4)); + writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE); - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 3)); - writel(dc, vt8500->base + 0xc + (pwm->hwpwm << 4)); + val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); + val |= CTRL_AUTOLOAD; + writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); clk_disable(vt8500->clk); return 0; @@ -106,8 +133,9 @@ static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - int err; struct vt8500_chip *vt8500 = to_vt8500_chip(chip); + int err; + u32 val; err = clk_enable(vt8500->clk); if (err < 0) { @@ -115,25 +143,52 @@ static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) return err; } - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 0)); - writel(5, vt8500->base + (pwm->hwpwm << 4)); + val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); + val |= CTRL_ENABLE; + writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); + return 0; } static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct vt8500_chip *vt8500 = to_vt8500_chip(chip); + u32 val; - pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 0)); - writel(0, vt8500->base + (pwm->hwpwm << 4)); + val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); + val &= ~CTRL_ENABLE; + writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); clk_disable(vt8500->clk); } +static int vt8500_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct vt8500_chip *vt8500 = to_vt8500_chip(chip); + u32 val; + + val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); + + if (polarity == PWM_POLARITY_INVERSED) + val |= CTRL_INVERT; + else + val &= ~CTRL_INVERT; + + writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); + pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); + + return 0; +} + static struct pwm_ops vt8500_pwm_ops = { .enable = vt8500_pwm_enable, .disable = vt8500_pwm_disable, .config = vt8500_pwm_config, + .set_polarity = vt8500_pwm_set_polarity, .owner = THIS_MODULE, }; @@ -156,13 +211,13 @@ static int vt8500_pwm_probe(struct platform_device *pdev) } chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); - if (chip == NULL) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + if (chip == NULL) return -ENOMEM; - } chip->chip.dev = &pdev->dev; chip->chip.ops = &vt8500_pwm_ops; + chip->chip.of_xlate = of_pwm_xlate_with_flags; + chip->chip.of_pwm_n_cells = 3; chip->chip.base = -1; chip->chip.npwm = VT8500_NR_PWMS; @@ -173,14 +228,9 @@ static int vt8500_pwm_probe(struct platform_device *pdev) } r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (r == NULL) { - dev_err(&pdev->dev, "no memory resource defined\n"); - return -ENODEV; - } - - chip->base = devm_request_and_ioremap(&pdev->dev, r); - if (!chip->base) - return -EADDRNOTAVAIL; + chip->base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(chip->base)) + return PTR_ERR(chip->base); ret = clk_prepare(chip->clk); if (ret < 0) { diff --git a/drivers/pwm/sysfs.c b/drivers/pwm/sysfs.c new file mode 100644 index 00000000000..4bd0c639e16 --- /dev/null +++ b/drivers/pwm/sysfs.c @@ -0,0 +1,347 @@ +/* + * A simple sysfs interface for the generic PWM framework + * + * Copyright (C) 2013 H Hartley Sweeten <hsweeten@visionengravers.com> + * + * Based on previous work by Lars Poeschel <poeschel@lemonage.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/kdev_t.h> +#include <linux/pwm.h> + +struct pwm_export { + struct device child; + struct pwm_device *pwm; +}; + +static struct pwm_export *child_to_pwm_export(struct device *child) +{ + return container_of(child, struct pwm_export, child); +} + +static struct pwm_device *child_to_pwm_device(struct device *child) +{ + struct pwm_export *export = child_to_pwm_export(child); + + return export->pwm; +} + +static ssize_t pwm_period_show(struct device *child, + struct device_attribute *attr, + char *buf) +{ + const struct pwm_device *pwm = child_to_pwm_device(child); + + return sprintf(buf, "%u\n", pwm->period); +} + +static ssize_t pwm_period_store(struct device *child, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct pwm_device *pwm = child_to_pwm_device(child); + unsigned int val; + int ret; + + ret = kstrtouint(buf, 0, &val); + if (ret) + return ret; + + ret = pwm_config(pwm, pwm->duty_cycle, val); + + return ret ? : size; +} + +static ssize_t pwm_duty_cycle_show(struct device *child, + struct device_attribute *attr, + char *buf) +{ + const struct pwm_device *pwm = child_to_pwm_device(child); + + return sprintf(buf, "%u\n", pwm->duty_cycle); +} + +static ssize_t pwm_duty_cycle_store(struct device *child, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct pwm_device *pwm = child_to_pwm_device(child); + unsigned int val; + int ret; + + ret = kstrtouint(buf, 0, &val); + if (ret) + return ret; + + ret = pwm_config(pwm, val, pwm->period); + + return ret ? : size; +} + +static ssize_t pwm_enable_show(struct device *child, + struct device_attribute *attr, + char *buf) +{ + const struct pwm_device *pwm = child_to_pwm_device(child); + int enabled = test_bit(PWMF_ENABLED, &pwm->flags); + + return sprintf(buf, "%d\n", enabled); +} + +static ssize_t pwm_enable_store(struct device *child, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct pwm_device *pwm = child_to_pwm_device(child); + int val, ret; + + ret = kstrtoint(buf, 0, &val); + if (ret) + return ret; + + switch (val) { + case 0: + pwm_disable(pwm); + break; + case 1: + ret = pwm_enable(pwm); + break; + default: + ret = -EINVAL; + break; + } + + return ret ? : size; +} + +static ssize_t pwm_polarity_show(struct device *child, + struct device_attribute *attr, + char *buf) +{ + const struct pwm_device *pwm = child_to_pwm_device(child); + + return sprintf(buf, "%s\n", pwm->polarity ? "inversed" : "normal"); +} + +static ssize_t pwm_polarity_store(struct device *child, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct pwm_device *pwm = child_to_pwm_device(child); + enum pwm_polarity polarity; + int ret; + + if (sysfs_streq(buf, "normal")) + polarity = PWM_POLARITY_NORMAL; + else if (sysfs_streq(buf, "inversed")) + polarity = PWM_POLARITY_INVERSED; + else + return -EINVAL; + + ret = pwm_set_polarity(pwm, polarity); + + return ret ? : size; +} + +static DEVICE_ATTR(period, 0644, pwm_period_show, pwm_period_store); +static DEVICE_ATTR(duty_cycle, 0644, pwm_duty_cycle_show, pwm_duty_cycle_store); +static DEVICE_ATTR(enable, 0644, pwm_enable_show, pwm_enable_store); +static DEVICE_ATTR(polarity, 0644, pwm_polarity_show, pwm_polarity_store); + +static struct attribute *pwm_attrs[] = { + &dev_attr_period.attr, + &dev_attr_duty_cycle.attr, + &dev_attr_enable.attr, + &dev_attr_polarity.attr, + NULL +}; +ATTRIBUTE_GROUPS(pwm); + +static void pwm_export_release(struct device *child) +{ + struct pwm_export *export = child_to_pwm_export(child); + + kfree(export); +} + +static int pwm_export_child(struct device *parent, struct pwm_device *pwm) +{ + struct pwm_export *export; + int ret; + + if (test_and_set_bit(PWMF_EXPORTED, &pwm->flags)) + return -EBUSY; + + export = kzalloc(sizeof(*export), GFP_KERNEL); + if (!export) { + clear_bit(PWMF_EXPORTED, &pwm->flags); + return -ENOMEM; + } + + export->pwm = pwm; + + export->child.release = pwm_export_release; + export->child.parent = parent; + export->child.devt = MKDEV(0, 0); + export->child.groups = pwm_groups; + dev_set_name(&export->child, "pwm%u", pwm->hwpwm); + + ret = device_register(&export->child); + if (ret) { + clear_bit(PWMF_EXPORTED, &pwm->flags); + kfree(export); + return ret; + } + + return 0; +} + +static int pwm_unexport_match(struct device *child, void *data) +{ + return child_to_pwm_device(child) == data; +} + +static int pwm_unexport_child(struct device *parent, struct pwm_device *pwm) +{ + struct device *child; + + if (!test_and_clear_bit(PWMF_EXPORTED, &pwm->flags)) + return -ENODEV; + + child = device_find_child(parent, pwm, pwm_unexport_match); + if (!child) + return -ENODEV; + + /* for device_find_child() */ + put_device(child); + device_unregister(child); + pwm_put(pwm); + + return 0; +} + +static ssize_t pwm_export_store(struct device *parent, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct pwm_chip *chip = dev_get_drvdata(parent); + struct pwm_device *pwm; + unsigned int hwpwm; + int ret; + + ret = kstrtouint(buf, 0, &hwpwm); + if (ret < 0) + return ret; + + if (hwpwm >= chip->npwm) + return -ENODEV; + + pwm = pwm_request_from_chip(chip, hwpwm, "sysfs"); + if (IS_ERR(pwm)) + return PTR_ERR(pwm); + + ret = pwm_export_child(parent, pwm); + if (ret < 0) + pwm_put(pwm); + + return ret ? : len; +} +static DEVICE_ATTR(export, 0200, NULL, pwm_export_store); + +static ssize_t pwm_unexport_store(struct device *parent, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct pwm_chip *chip = dev_get_drvdata(parent); + unsigned int hwpwm; + int ret; + + ret = kstrtouint(buf, 0, &hwpwm); + if (ret < 0) + return ret; + + if (hwpwm >= chip->npwm) + return -ENODEV; + + ret = pwm_unexport_child(parent, &chip->pwms[hwpwm]); + + return ret ? : len; +} +static DEVICE_ATTR(unexport, 0200, NULL, pwm_unexport_store); + +static ssize_t npwm_show(struct device *parent, struct device_attribute *attr, + char *buf) +{ + const struct pwm_chip *chip = dev_get_drvdata(parent); + + return sprintf(buf, "%u\n", chip->npwm); +} +static DEVICE_ATTR_RO(npwm); + +static struct attribute *pwm_chip_attrs[] = { + &dev_attr_export.attr, + &dev_attr_unexport.attr, + &dev_attr_npwm.attr, + NULL, +}; +ATTRIBUTE_GROUPS(pwm_chip); + +static struct class pwm_class = { + .name = "pwm", + .owner = THIS_MODULE, + .dev_groups = pwm_chip_groups, +}; + +static int pwmchip_sysfs_match(struct device *parent, const void *data) +{ + return dev_get_drvdata(parent) == data; +} + +void pwmchip_sysfs_export(struct pwm_chip *chip) +{ + struct device *parent; + + /* + * If device_create() fails the pwm_chip is still usable by + * the kernel its just not exported. + */ + parent = device_create(&pwm_class, chip->dev, MKDEV(0, 0), chip, + "pwmchip%d", chip->base); + if (IS_ERR(parent)) { + dev_warn(chip->dev, + "device_create failed for pwm_chip sysfs export\n"); + } +} + +void pwmchip_sysfs_unexport(struct pwm_chip *chip) +{ + struct device *parent; + + parent = class_find_device(&pwm_class, NULL, chip, + pwmchip_sysfs_match); + if (parent) { + /* for class_find_device() */ + put_device(parent); + device_unregister(parent); + } +} + +static int __init pwm_sysfs_init(void) +{ + return class_register(&pwm_class); +} +subsys_initcall(pwm_sysfs_init); |