diff options
Diffstat (limited to 'drivers/pinctrl')
144 files changed, 75405 insertions, 24908 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f910962baaa..0042ccb46b9 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -49,36 +49,119 @@ config PINCTRL_AB8505 bool "AB8505 pin controller driver" depends on PINCTRL_ABX500 && ARCH_U8500 +config PINCTRL_ADI2 + bool "ADI pin controller driver" + depends on BLACKFIN + select PINMUX + select IRQ_DOMAIN + help + This is the pin controller and gpio driver for ADI BF54x, BF60x and + future processors. This option is selected automatically when specific + machine and arch are selected to build. + +config PINCTRL_AS3722 + bool "Pinctrl and GPIO driver for ams AS3722 PMIC" + depends on MFD_AS3722 && GPIOLIB + select PINMUX + select GENERIC_PINCONF + help + AS3722 device supports the configuration of GPIO pins for different + functionality. This driver supports the pinmux, push-pull and + open drain configuration for the GPIO pins of AS3722 devices. It also + supports the GPIO functionality through gpiolib. + +config PINCTRL_BF54x + def_bool y if BF54x + select PINCTRL_ADI2 + +config PINCTRL_BF60x + def_bool y if BF60x + select PINCTRL_ADI2 + config PINCTRL_AT91 bool "AT91 pinctrl driver" depends on OF depends on ARCH_AT91 select PINMUX select PINCONF + select GPIOLIB + select OF_GPIO + select GPIOLIB_IRQCHIP help Say Y here to enable the at91 pinctrl driver +config PINCTRL_BAYTRAIL + bool "Intel Baytrail GPIO pin control" + depends on GPIOLIB && ACPI && X86 + select IRQ_DOMAIN + help + driver for memory mapped GPIO functionality on Intel Baytrail + platforms. Supports 3 banks with 102, 28 and 44 gpios. + Most pins are usually muxed to some other functionality by firmware, + so only a small amount is available for gpio use. + + Requires ACPI device enumeration code to set up a platform device. + config PINCTRL_BCM2835 bool select PINMUX select PINCONF +config PINCTRL_BCM281XX + bool "Broadcom BCM281xx pinctrl driver" + depends on OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select REGMAP_MMIO + help + Say Y here to support Broadcom BCM281xx pinctrl driver, which is used + for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, + BCM28145, and BCM28155 SoCs. This driver requires the pinctrl + framework. GPIO is provided by a separate GPIO driver. + config PINCTRL_IMX bool select PINMUX select PINCONF +config PINCTRL_IMX1_CORE + bool + select PINMUX + select PINCONF + +config PINCTRL_IMX27 + bool "IMX27 pinctrl driver" + depends on SOC_IMX27 + select PINCTRL_IMX1_CORE + help + Say Y here to enable the imx27 pinctrl driver + + +config PINCTRL_IMX25 + bool "IMX25 pinctrl driver" + depends on OF + depends on SOC_IMX25 + select PINCTRL_IMX + help + Say Y here to enable the imx25 pinctrl driver + config PINCTRL_IMX35 bool "IMX35 pinctrl driver" - depends on OF depends on SOC_IMX35 select PINCTRL_IMX help Say Y here to enable the imx35 pinctrl driver +config PINCTRL_IMX50 + bool "IMX50 pinctrl driver" + depends on SOC_IMX50 + select PINCTRL_IMX + help + Say Y here to enable the imx50 pinctrl driver + config PINCTRL_IMX51 bool "IMX51 pinctrl driver" - depends on OF depends on SOC_IMX51 select PINCTRL_IMX help @@ -86,19 +169,38 @@ config PINCTRL_IMX51 config PINCTRL_IMX53 bool "IMX53 pinctrl driver" - depends on OF depends on SOC_IMX53 select PINCTRL_IMX help Say Y here to enable the imx53 pinctrl driver config PINCTRL_IMX6Q - bool "IMX6Q pinctrl driver" - depends on OF + bool "IMX6Q/DL pinctrl driver" depends on SOC_IMX6Q select PINCTRL_IMX help - Say Y here to enable the imx6q pinctrl driver + Say Y here to enable the imx6q/dl pinctrl driver + +config PINCTRL_IMX6SL + bool "IMX6SL pinctrl driver" + depends on SOC_IMX6SL + select PINCTRL_IMX + help + Say Y here to enable the imx6sl pinctrl driver + +config PINCTRL_IMX6SX + bool "IMX6SX pinctrl driver" + depends on SOC_IMX6SX + select PINCTRL_IMX + help + Say Y here to enable the imx6sx pinctrl driver + +config PINCTRL_VF610 + bool "Freescale Vybrid VF610 pinctrl driver" + depends on SOC_VF610 + select PINCTRL_IMX + help + Say Y here to enable the Freescale Vybrid VF610 pinctrl driver config PINCTRL_LANTIQ bool @@ -124,11 +226,45 @@ config PINCTRL_IMX28 bool select PINCTRL_MXS +config PINCTRL_MSM + bool + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB_IRQCHIP + +config PINCTRL_APQ8064 + tristate "Qualcomm APQ8064 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm APQ8064 platform. + +config PINCTRL_IPQ8064 + tristate "Qualcomm IPQ8064 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. + +config PINCTRL_MSM8X74 + tristate "Qualcomm 8x74 pin controller driver" + depends on GPIOLIB && OF && (ARCH_QCOM || COMPILE_TEST) + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8974 platform. + config PINCTRL_NOMADIK bool "Nomadik pin controller driver" depends on ARCH_U8500 || ARCH_NOMADIK select PINMUX select PINCONF + select GPIOLIB + select OF_GPIO + select GPIOLIB_IRQCHIP config PINCTRL_STN8815 bool "STN8815 pin controller driver" @@ -142,6 +278,13 @@ config PINCTRL_DB8540 bool "DB8540 pin controller driver" depends on PINCTRL_NOMADIK && ARCH_U8500 +config PINCTRL_ROCKCHIP + bool + select PINMUX + select GENERIC_PINCONF + select GENERIC_IRQ_CHIP + select MFD_SYSCON + config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" depends on OF @@ -155,11 +298,14 @@ config PINCTRL_SIRF bool "CSR SiRFprimaII/SiRFmarco pin controller driver" depends on ARCH_SIRF select PINMUX + select GPIOLIB_IRQCHIP -config PINCTRL_SUNXI +config PINCTRL_ST bool + depends on OF select PINMUX - select GENERIC_PINCONF + select PINCONF + select GPIOLIB_IRQCHIP config PINCTRL_TEGRA bool @@ -178,6 +324,22 @@ config PINCTRL_TEGRA114 bool select PINCTRL_TEGRA +config PINCTRL_TEGRA124 + bool + select PINCTRL_TEGRA + +config PINCTRL_TZ1090 + bool "Toumaz Xenif TZ1090 pin control driver" + depends on SOC_TZ1090 + select PINMUX + select GENERIC_PINCONF + +config PINCTRL_TZ1090_PDC + bool "Toumaz Xenif TZ1090 PDC pin control driver" + depends on SOC_TZ1090 + select PINMUX + select PINCONF + config PINCTRL_U300 bool "U300 pin controller driver" depends on ARCH_U300 @@ -187,6 +349,7 @@ config PINCTRL_U300 config PINCTRL_COH901 bool "ST-Ericsson U300 COH 901 335/571 GPIO" depends on GPIOLIB && ARCH_U300 && PINCTRL_U300 + select GPIOLIB_IRQCHIP help Say yes here to support GPIO interface on ST-Ericsson U300. The names of the two IP block variants supported are @@ -199,29 +362,53 @@ config PINCTRL_SAMSUNG select PINCONF config PINCTRL_EXYNOS - bool "Pinctrl driver data for Samsung EXYNOS SoCs" - depends on OF && GPIOLIB + bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440" + depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210) select PINCTRL_SAMSUNG config PINCTRL_EXYNOS5440 bool "Samsung EXYNOS5440 SoC pinctrl driver" + depends on SOC_EXYNOS5440 select PINMUX select PINCONF +config PINCTRL_PALMAS + bool "Pinctrl driver for the PALMAS Series MFD devices" + depends on OF && MFD_PALMAS + select PINMUX + select GENERIC_PINCONF + help + Palmas device supports the configuration of pins for different + functionality. This driver supports the pinmux, push-pull and + open drain configuration for the Palmas series devices like + TPS65913, TPS80036 etc. + +config PINCTRL_S3C24XX + bool "Samsung S3C24XX SoC pinctrl driver" + depends on ARCH_S3C24XX + select PINCTRL_SAMSUNG + config PINCTRL_S3C64XX bool "Samsung S3C64XX SoC pinctrl driver" depends on ARCH_S3C64XX select PINCTRL_SAMSUNG +source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" +source "drivers/pinctrl/sunxi/Kconfig" +source "drivers/pinctrl/vt8500/Kconfig" config PINCTRL_XWAY bool depends on SOC_TYPE_XWAY depends on PINCTRL_LANTIQ +config PINCTRL_TB10X + bool + depends on ARC_PLAT_TB10X + endmenu endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 988279ae23c..c4b5d405b8f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -2,7 +2,7 @@ ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG -obj-$(CONFIG_PINCTRL) += core.o +obj-$(CONFIG_PINCTRL) += core.o pinctrl-utils.o obj-$(CONFIG_PINMUX) += pinmux.o obj-$(CONFIG_PINCONF) += pinconf.o ifeq ($(CONFIG_OF),y) @@ -14,38 +14,66 @@ obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o +obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o +obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o +obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o +obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o +obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o +obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o +obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o +obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o +obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o +obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o +obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o +obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o +obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o +obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o +obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o +obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o +obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o +obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o -obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o -obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o +obj-$(CONFIG_PINCTRL_SIRF) += sirf/ obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o +obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o +obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o +obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o +obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o +obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o +obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o +obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o +obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_PLAT_ORION) += mvebu/ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ obj-$(CONFIG_SUPERH) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ +obj-$(CONFIG_ARCH_VT8500) += vt8500/ +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig new file mode 100644 index 00000000000..b18322bc7bf --- /dev/null +++ b/drivers/pinctrl/berlin/Kconfig @@ -0,0 +1,20 @@ +if ARCH_BERLIN + +config PINCTRL_BERLIN + bool + select PINMUX + select REGMAP_MMIO + +config PINCTRL_BERLIN_BG2 + bool + select PINCTRL_BERLIN + +config PINCTRL_BERLIN_BG2CD + bool + select PINCTRL_BERLIN + +config PINCTRL_BERLIN_BG2Q + bool + select PINCTRL_BERLIN + +endif diff --git a/drivers/pinctrl/berlin/Makefile b/drivers/pinctrl/berlin/Makefile new file mode 100644 index 00000000000..deb0c6baf31 --- /dev/null +++ b/drivers/pinctrl/berlin/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_PINCTRL_BERLIN) += berlin.o +obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o +obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o +obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o diff --git a/drivers/pinctrl/berlin/berlin-bg2.c b/drivers/pinctrl/berlin/berlin-bg2.c new file mode 100644 index 00000000000..dcd4f6a4fc5 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin-bg2.c @@ -0,0 +1,274 @@ +/* + * Marvell Berlin BG2 pinctrl driver. + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "berlin.h" + +static const struct berlin_desc_group berlin2_soc_pinctrl_groups[] = { + /* G */ + BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "usb1")), + BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s0")), + BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "soc"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s1")), + BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "pwm")), + BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + /* + * Mode 0x3 mux i2s2 mclk *and* i2s3 mclk: + * add two functions so it can be used with other groups + * within the same subnode in the device tree + */ + BERLIN_PINCTRL_FUNCTION(0x3, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s3")), + BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x2, "et")), + BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + BERLIN_PINCTRL_FUNCTION(0x3, "vdac")), + BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "sata_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "sata_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16, + BERLIN_PINCTRL_FUNCTION(0x0, "soc"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi0"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "ptp")), + BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "soc"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "eddc")), + BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a, + BERLIN_PINCTRL_FUNCTION(0x0, "sts2"), + BERLIN_PINCTRL_FUNCTION(0x1, "sata"), + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), + BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sata"), + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), + BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + BERLIN_PINCTRL_FUNCTION(0x3, "osco")), + BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp")), + BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp")), + BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "pll"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s0")), + BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d, + BERLIN_PINCTRL_FUNCTION(0x0, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), + BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION(0x0, "spdif"), + BERLIN_PINCTRL_FUNCTION(0x1, "arc")), + BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "adac_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "pdm_a"), /* gpio17..19,pdm */ + BERLIN_PINCTRL_FUNCTION(0x7, "pdm_b")), /* gpio12..14,pdm */ + BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "twsi0"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), + BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "vclki"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x7, "pdm")), + BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1")), + BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "nand"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s2")), + BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), + BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "nand")), + BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e, + BERLIN_PINCTRL_FUNCTION(0x0, "dvo"), + BERLIN_PINCTRL_FUNCTION(0x2, "sp")), +}; + +static const struct berlin_desc_group berlin2_sysmgr_pinctrl_groups[] = { + /* GSM */ + BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), + BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), + BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "twsi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), + BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */ + BERLIN_PINCTRL_FUNCTION(0x2, "uart2"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x3, "twsi2")), + BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x1, "irda0")), + BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x2, "irda1"), + BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")), + BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "clki")), + BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x10, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), + BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x11, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), + BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), +}; + +static const struct berlin_pinctrl_desc berlin2_soc_pinctrl_data = { + .groups = berlin2_soc_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2_soc_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin2_sysmgr_pinctrl_data = { + .groups = berlin2_sysmgr_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2_sysmgr_pinctrl_groups), +}; + +static const struct of_device_id berlin2_pinctrl_match[] = { + { + .compatible = "marvell,berlin2-chip-ctrl", + .data = &berlin2_soc_pinctrl_data + }, + { + .compatible = "marvell,berlin2-system-ctrl", + .data = &berlin2_sysmgr_pinctrl_data + }, + {} +}; +MODULE_DEVICE_TABLE(of, berlin2_pinctrl_match); + +static int berlin2_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match = + of_match_device(berlin2_pinctrl_match, &pdev->dev); + struct regmap_config *rmconfig; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); + if (!rmconfig) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rmconfig->reg_bits = 32, + rmconfig->val_bits = 32, + rmconfig->reg_stride = 4, + rmconfig->max_register = resource_size(res); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe(pdev, match->data); +} + +static struct platform_driver berlin2_pinctrl_driver = { + .probe = berlin2_pinctrl_probe, + .driver = { + .name = "berlin-bg2-pinctrl", + .owner = THIS_MODULE, + .of_match_table = berlin2_pinctrl_match, + }, +}; +module_platform_driver(berlin2_pinctrl_driver); + +MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Berlin BG2 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c new file mode 100644 index 00000000000..89d585ef7da --- /dev/null +++ b/drivers/pinctrl/berlin/berlin-bg2cd.c @@ -0,0 +1,217 @@ +/* + * Marvell Berlin BG2CD pinctrl driver. + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "berlin.h" + +static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { + /* G */ + BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "led"), + BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), + BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fe"), + BERLIN_PINCTRL_FUNCTION(0x3, "pll"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "twsi2"), + BERLIN_PINCTRL_FUNCTION(0x3, "pll"), + BERLIN_PINCTRL_FUNCTION(0x4, "fe"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), + BERLIN_PINCTRL_FUNCTION(0x3, "pll"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), + BERLIN_PINCTRL_FUNCTION(0x3, "arc"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d, + BERLIN_PINCTRL_FUNCTION(0x0, "eddc"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10, + BERLIN_PINCTRL_FUNCTION(0x0, "ss0"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "twsi0")), + BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a, + BERLIN_PINCTRL_FUNCTION(0x0, "usb1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x1, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x2, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), +}; + +static const struct berlin_desc_group berlin2cd_sysmgr_pinctrl_groups[] = { + /* GSM */ + BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0f, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x10, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x11, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x12, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), +}; + +static const struct berlin_pinctrl_desc berlin2cd_soc_pinctrl_data = { + .groups = berlin2cd_soc_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2cd_soc_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin2cd_sysmgr_pinctrl_data = { + .groups = berlin2cd_sysmgr_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2cd_sysmgr_pinctrl_groups), +}; + +static const struct of_device_id berlin2cd_pinctrl_match[] = { + { + .compatible = "marvell,berlin2cd-chip-ctrl", + .data = &berlin2cd_soc_pinctrl_data + }, + { + .compatible = "marvell,berlin2cd-system-ctrl", + .data = &berlin2cd_sysmgr_pinctrl_data + }, + {} +}; +MODULE_DEVICE_TABLE(of, berlin2cd_pinctrl_match); + +static int berlin2cd_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match = + of_match_device(berlin2cd_pinctrl_match, &pdev->dev); + struct regmap_config *rmconfig; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); + if (!rmconfig) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rmconfig->reg_bits = 32, + rmconfig->val_bits = 32, + rmconfig->reg_stride = 4, + rmconfig->max_register = resource_size(res); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe(pdev, match->data); +} + +static struct platform_driver berlin2cd_pinctrl_driver = { + .probe = berlin2cd_pinctrl_probe, + .driver = { + .name = "berlin-bg2cd-pinctrl", + .owner = THIS_MODULE, + .of_match_table = berlin2cd_pinctrl_match, + }, +}; +module_platform_driver(berlin2cd_pinctrl_driver); + +MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Berlin BG2CD pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin-bg2q.c b/drivers/pinctrl/berlin/berlin-bg2q.c new file mode 100644 index 00000000000..9fcf9836045 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin-bg2q.c @@ -0,0 +1,436 @@ +/* + * Marvell Berlin BG2Q pinctrl driver + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "berlin.h" + +static const struct berlin_desc_group berlin2q_soc_pinctrl_groups[] = { + /* G */ + BERLIN_PINCTRL_GROUP("G0", 0x18, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x1, "mmc"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G1", 0x18, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G2", 0x18, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "arc"), + BERLIN_PINCTRL_FUNCTION(0x3, "lvds")), + BERLIN_PINCTRL_GROUP("G3", 0x18, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x3, "lvds")), + BERLIN_PINCTRL_GROUP("G4", 0x18, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "pll"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata_dbg"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G5", 0x18, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata_dbg"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G6", 0x18, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi0"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G7", 0x18, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "eddc")), + BERLIN_PINCTRL_GROUP("G8", 0x18, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G9", 0x18, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata")), + BERLIN_PINCTRL_GROUP("G10", 0x1c, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata")), + BERLIN_PINCTRL_GROUP("G11", 0x1c, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata")), + BERLIN_PINCTRL_GROUP("G12", 0x1c, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "agc"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G13", 0x1c, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G14", 0x1c, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G15", 0x1c, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x5, "vdac"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G16", 0x1c, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x5, "osco"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G17", 0x1c, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x3, "spdif"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G18", 0x1c, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1")), + BERLIN_PINCTRL_GROUP("G19", 0x1c, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x5, "osco")), + BERLIN_PINCTRL_GROUP("G20", 0x20, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "demod"), + /* + * Mode 0x4 mux usb2_dbg *and* usb3_dbg: + * add two functions so it can be used with other groups + * within the same subnode in the device tree + */ + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb3_dbg")), + BERLIN_PINCTRL_GROUP("G21", 0x20, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts2"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "demod")), + BERLIN_PINCTRL_GROUP("G22", 0x20, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G23", 0x20, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "avif"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")), + BERLIN_PINCTRL_GROUP("G24", 0x20, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "demod"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")), + BERLIN_PINCTRL_GROUP("G25", 0x20, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "vga"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "avif"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")), + BERLIN_PINCTRL_GROUP("G26", 0x20, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "lvds"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G27", 0x20, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "agc"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G28", 0x20, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "avif"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")), + BERLIN_PINCTRL_GROUP("G29", 0x20, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G30", 0x24, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "scrd1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G31", 0x24, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G32", 0x24, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + /* GAV */ + BERLIN_PINCTRL_GROUP("GAV0", 0x24, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "lvds")), + BERLIN_PINCTRL_GROUP("GAV1", 0x24, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "vga")), + BERLIN_PINCTRL_GROUP("GAV2", 0x24, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x4, "pdm"), + BERLIN_PINCTRL_FUNCTION(0x6, "adac")), + BERLIN_PINCTRL_GROUP("GAV3", 0x24, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x6, "adac")), + BERLIN_PINCTRL_GROUP("GAV4", 0x24, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x6, "adac")), + BERLIN_PINCTRL_GROUP("GAV5", 0x24, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "spdif")), + BERLIN_PINCTRL_GROUP("GAV6", 0x24, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s2")), + BERLIN_PINCTRL_GROUP("GAV7", 0x28, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s3")), + BERLIN_PINCTRL_GROUP("GAV8", 0x28, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), + BERLIN_PINCTRL_GROUP("GAV9", 0x28, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), + BERLIN_PINCTRL_GROUP("GAV10", 0x28, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "agc")), + BERLIN_PINCTRL_GROUP("GAV11", 0x28, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x5, "vclki")), + BERLIN_PINCTRL_GROUP("GAV12", 0x28, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")), + BERLIN_PINCTRL_GROUP("GAV13", 0x28, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2")), + BERLIN_PINCTRL_GROUP("GAV14", 0x28, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")), + BERLIN_PINCTRL_GROUP("GAV15", 0x28, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")), + BERLIN_PINCTRL_GROUP("GAV16", 0x28, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), + BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")), + BERLIN_PINCTRL_GROUP("GAV17", 0x2c, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x3, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), + BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")), + BERLIN_PINCTRL_GROUP("GAV18", 0x2c, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spdif"), + BERLIN_PINCTRL_FUNCTION(0x2, "arc")), + BERLIN_PINCTRL_GROUP("GAV19", 0x2c, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spdif"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x5, "pdm")), +}; + +static const struct berlin_desc_group berlin2q_sysmgr_pinctrl_groups[] = { + /* GSM */ + BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), + BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), + BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eddc")), + BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eddc")), + BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x1, 0x08, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x1, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x1, 0x0a, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x0d, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), + BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), + BERLIN_PINCTRL_GROUP("GSM12", 0x40, 0x2, 0x10, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x1, "irda0"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("GSM13", 0x40, 0x2, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */ + BERLIN_PINCTRL_FUNCTION(0x2, "uart1"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x3, "twsi2")), + BERLIN_PINCTRL_GROUP("GSM14", 0x40, 0x2, 0x14, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x2, "irda1"), + BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")), + BERLIN_PINCTRL_GROUP("GSM15", 0x40, 0x2, 0x16, + BERLIN_PINCTRL_FUNCTION(0x0, "pwr"), + BERLIN_PINCTRL_FUNCTION(0x1, "led"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("GSM16", 0x40, 0x1, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "eddc")), + BERLIN_PINCTRL_GROUP("GSM17", 0x40, 0x1, 0x19, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "eddc")), + BERLIN_PINCTRL_GROUP("GSM18", 0x40, 0x1, 0x1a, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "eddc")), +}; + +static const struct berlin_pinctrl_desc berlin2q_soc_pinctrl_data = { + .groups = berlin2q_soc_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2q_soc_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin2q_sysmgr_pinctrl_data = { + .groups = berlin2q_sysmgr_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2q_sysmgr_pinctrl_groups), +}; + +static const struct of_device_id berlin2q_pinctrl_match[] = { + { + .compatible = "marvell,berlin2q-chip-ctrl", + .data = &berlin2q_soc_pinctrl_data, + }, + { + .compatible = "marvell,berlin2q-system-ctrl", + .data = &berlin2q_sysmgr_pinctrl_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, berlin2q_pinctrl_match); + +static int berlin2q_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match = + of_match_device(berlin2q_pinctrl_match, &pdev->dev); + struct regmap_config *rmconfig; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); + if (!rmconfig) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rmconfig->reg_bits = 32, + rmconfig->val_bits = 32, + rmconfig->reg_stride = 4, + rmconfig->max_register = resource_size(res); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe(pdev, match->data); +} + +static struct platform_driver berlin2q_pinctrl_driver = { + .probe = berlin2q_pinctrl_probe, + .driver = { + .name = "berlin-bg2q-pinctrl", + .owner = THIS_MODULE, + .of_match_table = berlin2q_pinctrl_match, + }, +}; +module_platform_driver(berlin2q_pinctrl_driver); + +MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Berlin BG2Q pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c new file mode 100644 index 00000000000..86db2235ab0 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin.c @@ -0,0 +1,348 @@ +/* + * Marvell Berlin SoC pinctrl core driver + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "berlin.h" + +struct berlin_pinctrl { + struct regmap *regmap; + struct device *dev; + const struct berlin_pinctrl_desc *desc; + struct berlin_pinctrl_function *functions; + unsigned nfunctions; + struct pinctrl_dev *pctrl_dev; +}; + +static int berlin_pinctrl_get_group_count(struct pinctrl_dev *pctrl_dev) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pctrl->desc->ngroups; +} + +static const char *berlin_pinctrl_get_group_name(struct pinctrl_dev *pctrl_dev, + unsigned group) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pctrl->desc->groups[group].name; +} + +static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + struct property *prop; + const char *function_name, *group_name; + unsigned reserved_maps = 0; + int ret, ngroups; + + *map = NULL; + *num_maps = 0; + + ret = of_property_read_string(node, "function", &function_name); + if (ret) { + dev_err(pctrl->dev, + "missing function property in node %s\n", + node->name); + return -EINVAL; + } + + ngroups = of_property_count_strings(node, "groups"); + if (ngroups < 0) { + dev_err(pctrl->dev, + "missing groups property in node %s\n", + node->name); + return -EINVAL; + } + + ret = pinctrl_utils_reserve_map(pctrl_dev, map, &reserved_maps, + num_maps, ngroups); + if (ret) { + dev_err(pctrl->dev, "can't reserve map: %d\n", ret); + return ret; + } + + of_property_for_each_string(node, "groups", prop, group_name) { + ret = pinctrl_utils_add_map_mux(pctrl_dev, map, &reserved_maps, + num_maps, group_name, + function_name); + if (ret) { + dev_err(pctrl->dev, "can't add map: %d\n", ret); + return ret; + } + } + + return 0; +} + +static void berlin_pinctrl_dt_free_map(struct pinctrl_dev *pctrl_dev, + struct pinctrl_map *map, + unsigned nmaps) +{ + int i; + + for (i = 0; i < nmaps; i++) { + if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) { + kfree(map[i].data.mux.group); + + /* a function can be applied to multiple groups */ + if (i == 0) + kfree(map[i].data.mux.function); + } + } + + kfree(map); +} + +static const struct pinctrl_ops berlin_pinctrl_ops = { + .get_groups_count = &berlin_pinctrl_get_group_count, + .get_group_name = &berlin_pinctrl_get_group_name, + .dt_node_to_map = &berlin_pinctrl_dt_node_to_map, + .dt_free_map = &berlin_pinctrl_dt_free_map, +}; + +static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pctrl->nfunctions; +} + +static const char *berlin_pinmux_get_function_name(struct pinctrl_dev *pctrl_dev, + unsigned function) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pctrl->functions[function].name; +} + +static int berlin_pinmux_get_function_groups(struct pinctrl_dev *pctrl_dev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + *groups = pctrl->functions[function].groups; + *num_groups = pctrl->functions[function].ngroups; + + return 0; +} + +static struct berlin_desc_function * +berlin_pinctrl_find_function_by_name(struct berlin_pinctrl *pctrl, + const struct berlin_desc_group *group, + const char *fname) +{ + struct berlin_desc_function *function = group->functions; + + while (function->name) { + if (!strcmp(function->name, fname)) + return function; + + function++; + } + + return NULL; +} + +static int berlin_pinmux_enable(struct pinctrl_dev *pctrl_dev, + unsigned function, + unsigned group) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + const struct berlin_desc_group *group_desc = pctrl->desc->groups + group; + struct berlin_pinctrl_function *func = pctrl->functions + function; + struct berlin_desc_function *function_desc = + berlin_pinctrl_find_function_by_name(pctrl, group_desc, + func->name); + u32 mask, val; + + if (!function_desc) + return -EINVAL; + + mask = GENMASK(group_desc->lsb + group_desc->bit_width - 1, + group_desc->lsb); + val = function_desc->muxval << group_desc->lsb; + regmap_update_bits(pctrl->regmap, group_desc->offset, mask, val); + + return 0; +} + +static const struct pinmux_ops berlin_pinmux_ops = { + .get_functions_count = &berlin_pinmux_get_functions_count, + .get_function_name = &berlin_pinmux_get_function_name, + .get_function_groups = &berlin_pinmux_get_function_groups, + .enable = &berlin_pinmux_enable, +}; + +static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl, + const char *name) +{ + struct berlin_pinctrl_function *function = pctrl->functions; + + while (function->name) { + if (!strcmp(function->name, name)) { + function->ngroups++; + return -EEXIST; + } + function++; + } + + function->name = name; + function->ngroups = 1; + + pctrl->nfunctions++; + + return 0; +} + +static int berlin_pinctrl_build_state(struct platform_device *pdev) +{ + struct berlin_pinctrl *pctrl = platform_get_drvdata(pdev); + struct berlin_desc_group const *desc_group; + struct berlin_desc_function const *desc_function; + int i, max_functions = 0; + + pctrl->nfunctions = 0; + + for (i = 0; i < pctrl->desc->ngroups; i++) { + desc_group = pctrl->desc->groups + i; + /* compute the maxiumum number of functions a group can have */ + max_functions += 1 << (desc_group->bit_width + 1); + } + + /* we will reallocate later */ + pctrl->functions = devm_kzalloc(&pdev->dev, + max_functions * sizeof(*pctrl->functions), + GFP_KERNEL); + if (!pctrl->functions) + return -ENOMEM; + + /* register all functions */ + for (i = 0; i < pctrl->desc->ngroups; i++) { + desc_group = pctrl->desc->groups + i; + desc_function = desc_group->functions; + + while (desc_function->name) { + berlin_pinctrl_add_function(pctrl, desc_function->name); + desc_function++; + } + } + + pctrl->functions = krealloc(pctrl->functions, + pctrl->nfunctions * sizeof(*pctrl->functions), + GFP_KERNEL); + + /* map functions to theirs groups */ + for (i = 0; i < pctrl->desc->ngroups; i++) { + desc_group = pctrl->desc->groups + i; + desc_function = desc_group->functions; + + while (desc_function->name) { + struct berlin_pinctrl_function + *function = pctrl->functions; + const char **groups; + bool found = false; + + while (function->name) { + if (!strcmp(desc_function->name, function->name)) { + found = true; + break; + } + function++; + } + + if (!found) + return -EINVAL; + + if (!function->groups) { + function->groups = + devm_kzalloc(&pdev->dev, + function->ngroups * sizeof(char *), + GFP_KERNEL); + + if (!function->groups) + return -ENOMEM; + } + + groups = function->groups; + while (*groups) + groups++; + + *groups = desc_group->name; + + desc_function++; + } + } + + return 0; +} + +static struct pinctrl_desc berlin_pctrl_desc = { + .name = "berlin-pinctrl", + .pctlops = &berlin_pinctrl_ops, + .pmxops = &berlin_pinmux_ops, + .owner = THIS_MODULE, +}; + +int berlin_pinctrl_probe(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc) +{ + struct device *dev = &pdev->dev; + struct berlin_pinctrl *pctrl; + struct regmap *regmap; + int ret; + + regmap = dev_get_regmap(&pdev->dev, NULL); + if (!regmap) + return -ENODEV; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctrl); + + pctrl->regmap = regmap; + pctrl->dev = &pdev->dev; + pctrl->desc = desc; + + ret = berlin_pinctrl_build_state(pdev); + if (ret) { + dev_err(dev, "cannot build driver state: %d\n", ret); + return ret; + } + + pctrl->pctrl_dev = pinctrl_register(&berlin_pctrl_desc, dev, pctrl); + if (!pctrl->pctrl_dev) { + dev_err(dev, "failed to register pinctrl driver\n"); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h new file mode 100644 index 00000000000..e1aa8414519 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin.h @@ -0,0 +1,61 @@ +/* + * Marvell Berlin SoC pinctrl driver. + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PINCTRL_BERLIN_H +#define __PINCTRL_BERLIN_H + +struct berlin_desc_function { + const char *name; + u8 muxval; +}; + +struct berlin_desc_group { + const char *name; + u8 offset; + u8 bit_width; + u8 lsb; + struct berlin_desc_function *functions; +}; + +struct berlin_pinctrl_desc { + const struct berlin_desc_group *groups; + unsigned ngroups; +}; + +struct berlin_pinctrl_function { + const char *name; + const char **groups; + unsigned ngroups; +}; + +#define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ + { \ + .name = _name, \ + .offset = _offset, \ + .bit_width = _width, \ + .lsb = _lsb, \ + .functions = (struct berlin_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define BERLIN_PINCTRL_FUNCTION(_muxval, _name) \ + { \ + .name = _name, \ + .muxval = _muxval, \ + } + +#define BERLIN_PINCTRL_FUNCTION_UNKNOWN {} + +int berlin_pinctrl_probe(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc); + +#endif /* __PINCTRL_BERLIN_H */ diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index c3d222ed39a..e09474ecde2 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -41,13 +41,13 @@ static bool pinctrl_dummy_state; /* Mutex taken to protect pinctrl_list */ -DEFINE_MUTEX(pinctrl_list_mutex); +static DEFINE_MUTEX(pinctrl_list_mutex); /* Mutex taken to protect pinctrl_maps */ DEFINE_MUTEX(pinctrl_maps_mutex); /* Mutex taken to protect pinctrldev_list */ -DEFINE_MUTEX(pinctrldev_list_mutex); +static DEFINE_MUTEX(pinctrldev_list_mutex); /* Global list of pin control devices (struct pinctrl_dev) */ static LIST_HEAD(pinctrldev_list); @@ -101,20 +101,23 @@ EXPORT_SYMBOL_GPL(pinctrl_dev_get_drvdata); struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *devname) { struct pinctrl_dev *pctldev = NULL; - bool found = false; if (!devname) return NULL; + mutex_lock(&pinctrldev_list_mutex); + list_for_each_entry(pctldev, &pinctrldev_list, node) { if (!strcmp(dev_name(pctldev->dev), devname)) { /* Matched on device name */ - found = true; - break; + mutex_unlock(&pinctrldev_list_mutex); + return pctldev; } } - return found ? pctldev : NULL; + mutex_unlock(&pinctrldev_list_mutex); + + return NULL; } struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np) @@ -129,7 +132,7 @@ struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np) return pctldev; } - mutex_lock(&pinctrldev_list_mutex); + mutex_unlock(&pinctrldev_list_mutex); return NULL; } @@ -150,9 +153,7 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name) pin = pctldev->desc->pins[i].number; desc = pin_desc_get(pctldev, pin); /* Pin space may be sparse */ - if (desc == NULL) - continue; - if (desc->name && !strcmp(name, desc->name)) + if (desc && !strcmp(name, desc->name)) return pin; } @@ -280,6 +281,29 @@ static int pinctrl_register_pins(struct pinctrl_dev *pctldev, } /** + * gpio_to_pin() - GPIO range GPIO number to pin number translation + * @range: GPIO range used for the translation + * @gpio: gpio pin to translate to a pin number + * + * Finds the pin number for a given GPIO using the specified GPIO range + * as a base for translation. The distinction between linear GPIO ranges + * and pin list based GPIO ranges is managed correctly by this function. + * + * This function assumes the gpio is part of the specified GPIO range, use + * only after making sure this is the case (e.g. by calling it on the + * result of successful pinctrl_get_device_gpio_range calls)! + */ +static inline int gpio_to_pin(struct pinctrl_gpio_range *range, + unsigned int gpio) +{ + unsigned int offset = gpio - range->base; + if (range->pins) + return range->pins[offset]; + else + return range->pin_base + offset; +} + +/** * pinctrl_match_gpio_range() - check if a certain GPIO pin is in range * @pctldev: pin controller device to check * @gpio: gpio pin to check taken from the global GPIO pin space @@ -326,17 +350,26 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio) struct pinctrl_gpio_range *range = NULL; struct gpio_chip *chip = gpio_to_chip(gpio); + mutex_lock(&pinctrldev_list_mutex); + /* Loop over the pin controllers */ list_for_each_entry(pctldev, &pinctrldev_list, node) { /* Loop over the ranges */ + mutex_lock(&pctldev->mutex); list_for_each_entry(range, &pctldev->gpio_ranges, node) { /* Check if any gpio range overlapped with gpio chip */ if (range->base + range->npins - 1 < chip->base || range->base > chip->base + chip->ngpio - 1) continue; + mutex_unlock(&pctldev->mutex); + mutex_unlock(&pinctrldev_list_mutex); return true; } + mutex_unlock(&pctldev->mutex); } + + mutex_unlock(&pinctrldev_list_mutex); + return false; } #else @@ -360,6 +393,8 @@ static int pinctrl_get_device_gpio_range(unsigned gpio, { struct pinctrl_dev *pctldev = NULL; + mutex_lock(&pinctrldev_list_mutex); + /* Loop over the pin controllers */ list_for_each_entry(pctldev, &pinctrldev_list, node) { struct pinctrl_gpio_range *range; @@ -368,10 +403,13 @@ static int pinctrl_get_device_gpio_range(unsigned gpio, if (range != NULL) { *outdev = pctldev; *outrange = range; + mutex_unlock(&pinctrldev_list_mutex); return 0; } } + mutex_unlock(&pinctrldev_list_mutex); + return -EPROBE_DEFER; } @@ -408,8 +446,6 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname, { struct pinctrl_dev *pctldev; - mutex_lock(&pinctrldev_list_mutex); - pctldev = get_pinctrl_dev_from_devname(devname); /* @@ -418,17 +454,31 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname, * range need to defer probing. */ if (!pctldev) { - mutex_unlock(&pinctrldev_list_mutex); return ERR_PTR(-EPROBE_DEFER); } pinctrl_add_gpio_range(pctldev, range); - mutex_unlock(&pinctrldev_list_mutex); - return pctldev; } EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range); +int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, const char *pin_group, + const unsigned **pins, unsigned *num_pins) +{ + const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; + int gs; + + if (!pctlops->get_group_pins) + return -EINVAL; + + gs = pinctrl_get_group_selector(pctldev, pin_group); + if (gs < 0) + return gs; + + return pctlops->get_group_pins(pctldev, gs, pins, num_pins); +} +EXPORT_SYMBOL_GPL(pinctrl_get_group_pins); + /** * pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin * @pctldev: the pin controller device to look in @@ -438,21 +488,26 @@ struct pinctrl_gpio_range * pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev, unsigned int pin) { - struct pinctrl_gpio_range *range = NULL; + struct pinctrl_gpio_range *range; mutex_lock(&pctldev->mutex); /* Loop over the ranges */ list_for_each_entry(range, &pctldev->gpio_ranges, node) { /* Check if we're in the valid range */ - if (pin >= range->pin_base && - pin < range->pin_base + range->npins) { - mutex_unlock(&pctldev->mutex); - return range; - } + if (range->pins) { + int a; + for (a = 0; a < range->npins; a++) { + if (range->pins[a] == pin) + goto out; + } + } else if (pin >= range->pin_base && + pin < range->pin_base + range->npins) + goto out; } + range = NULL; +out: mutex_unlock(&pctldev->mutex); - - return NULL; + return range; } EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin); @@ -517,22 +572,22 @@ int pinctrl_request_gpio(unsigned gpio) int ret; int pin; - mutex_lock(&pinctrldev_list_mutex); - ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { if (pinctrl_ready_for_gpio_range(gpio)) ret = 0; - mutex_unlock(&pinctrldev_list_mutex); return ret; } + mutex_lock(&pctldev->mutex); + /* Convert to the pin controllers number space */ - pin = gpio - range->base + range->pin_base; + pin = gpio_to_pin(range, gpio); ret = pinmux_request_gpio(pctldev, range, pin, gpio); - mutex_unlock(&pinctrldev_list_mutex); + mutex_unlock(&pctldev->mutex); + return ret; } EXPORT_SYMBOL_GPL(pinctrl_request_gpio); @@ -552,22 +607,18 @@ void pinctrl_free_gpio(unsigned gpio) int ret; int pin; - mutex_lock(&pinctrldev_list_mutex); - ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { - mutex_unlock(&pinctrldev_list_mutex); return; } mutex_lock(&pctldev->mutex); /* Convert to the pin controllers number space */ - pin = gpio - range->base + range->pin_base; + pin = gpio_to_pin(range, gpio); pinmux_free_gpio(pctldev, pin, range); mutex_unlock(&pctldev->mutex); - mutex_unlock(&pinctrldev_list_mutex); } EXPORT_SYMBOL_GPL(pinctrl_free_gpio); @@ -578,22 +629,18 @@ static int pinctrl_gpio_direction(unsigned gpio, bool input) int ret; int pin; - mutex_lock(&pinctrldev_list_mutex); - ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { - mutex_unlock(&pinctrldev_list_mutex); return ret; } mutex_lock(&pctldev->mutex); /* Convert to the pin controllers number space */ - pin = gpio - range->base + range->pin_base; + pin = gpio_to_pin(range, gpio); ret = pinmux_gpio_direction(pctldev, range, pin, input); mutex_unlock(&pctldev->mutex); - mutex_unlock(&pinctrldev_list_mutex); return ret; } @@ -807,7 +854,9 @@ static struct pinctrl *create_pinctrl(struct device *dev) kref_init(&p->users); /* Add the pinctrl handle to the global list */ + mutex_lock(&pinctrl_list_mutex); list_add_tail(&p->node, &pinctrl_list); + mutex_unlock(&pinctrl_list_mutex); return p; } @@ -1173,6 +1222,7 @@ void pinctrl_unregister_map(struct pinctrl_map const *map) list_for_each_entry(maps_node, &pinctrl_maps, node) { if (maps_node->maps == map) { list_del(&maps_node->node); + kfree(maps_node); mutex_unlock(&pinctrl_maps_mutex); return; } @@ -1204,6 +1254,68 @@ int pinctrl_force_default(struct pinctrl_dev *pctldev) } EXPORT_SYMBOL_GPL(pinctrl_force_default); +#ifdef CONFIG_PM + +/** + * pinctrl_pm_select_state() - select pinctrl state for PM + * @dev: device to select default state for + * @state: state to set + */ +static int pinctrl_pm_select_state(struct device *dev, + struct pinctrl_state *state) +{ + struct dev_pin_info *pins = dev->pins; + int ret; + + if (IS_ERR(state)) + return 0; /* No such state */ + ret = pinctrl_select_state(pins->p, state); + if (ret) + dev_err(dev, "failed to activate pinctrl state %s\n", + state->name); + return ret; +} + +/** + * pinctrl_pm_select_default_state() - select default pinctrl state for PM + * @dev: device to select default state for + */ +int pinctrl_pm_select_default_state(struct device *dev) +{ + if (!dev->pins) + return 0; + + return pinctrl_pm_select_state(dev, dev->pins->default_state); +} +EXPORT_SYMBOL_GPL(pinctrl_pm_select_default_state); + +/** + * pinctrl_pm_select_sleep_state() - select sleep pinctrl state for PM + * @dev: device to select sleep state for + */ +int pinctrl_pm_select_sleep_state(struct device *dev) +{ + if (!dev->pins) + return 0; + + return pinctrl_pm_select_state(dev, dev->pins->sleep_state); +} +EXPORT_SYMBOL_GPL(pinctrl_pm_select_sleep_state); + +/** + * pinctrl_pm_select_idle_state() - select idle pinctrl state for PM + * @dev: device to select idle state for + */ +int pinctrl_pm_select_idle_state(struct device *dev) +{ + if (!dev->pins) + return 0; + + return pinctrl_pm_select_state(dev, dev->pins->idle_state); +} +EXPORT_SYMBOL_GPL(pinctrl_pm_select_idle_state); +#endif + #ifdef CONFIG_DEBUG_FS static int pinctrl_pins_show(struct seq_file *s, void *what) @@ -1253,15 +1365,16 @@ static int pinctrl_groups_show(struct seq_file *s, void *what) seq_puts(s, "registered pin groups:\n"); while (selector < ngroups) { - const unsigned *pins; - unsigned num_pins; + const unsigned *pins = NULL; + unsigned num_pins = 0; const char *gname = ops->get_group_name(pctldev, selector); const char *pname; - int ret; + int ret = 0; int i; - ret = ops->get_group_pins(pctldev, selector, - &pins, &num_pins); + if (ops->get_group_pins) + ret = ops->get_group_pins(pctldev, selector, + &pins, &num_pins); if (ret) seq_printf(s, "%s [ERROR GETTING PINS]\n", gname); @@ -1296,11 +1409,21 @@ static int pinctrl_gpioranges_show(struct seq_file *s, void *what) /* Loop over the ranges */ list_for_each_entry(range, &pctldev->gpio_ranges, node) { - seq_printf(s, "%u: %s GPIOS [%u - %u] PINS [%u - %u]\n", - range->id, range->name, - range->base, (range->base + range->npins - 1), - range->pin_base, - (range->pin_base + range->npins - 1)); + if (range->pins) { + int a; + seq_printf(s, "%u: %s GPIOS [%u - %u] PINS {", + range->id, range->name, + range->base, (range->base + range->npins - 1)); + for (a = 0; a < range->npins - 1; a++) + seq_printf(s, "%u, ", range->pins[a]); + seq_printf(s, "%u}\n", range->pins[a]); + } + else + seq_printf(s, "%u: %s GPIOS [%u - %u] PINS [%u - %u]\n", + range->id, range->name, + range->base, (range->base + range->npins - 1), + range->pin_base, + (range->pin_base + range->npins - 1)); } mutex_unlock(&pctldev->mutex); @@ -1525,8 +1648,10 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev) device_root, pctldev, &pinctrl_groups_ops); debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO, device_root, pctldev, &pinctrl_gpioranges_ops); - pinmux_init_device_debugfs(device_root, pctldev); - pinconf_init_device_debugfs(device_root, pctldev); + if (pctldev->desc->pmxops) + pinmux_init_device_debugfs(device_root, pctldev); + if (pctldev->desc->confops) + pinconf_init_device_debugfs(device_root, pctldev); } static void pinctrl_remove_device_debugfs(struct pinctrl_dev *pctldev) @@ -1573,8 +1698,7 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev) if (!ops || !ops->get_groups_count || - !ops->get_group_name || - !ops->get_group_pins) + !ops->get_group_name) return -EINVAL; if (ops->dt_node_to_map && !ops->dt_free_map) diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 340fb4e6c60..eda13de2e7c 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -186,7 +186,9 @@ int pinctrl_dt_to_map(struct pinctrl *p) /* CONFIG_OF enabled, p->dev not instantiated from DT */ if (!np) { - dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n"); + if (of_have_populated_dt()) + dev_dbg(p->dev, + "no of_node; not parsing pinctrl DT\n"); return 0; } diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig index 366fa541ee9..d6dd8358a6f 100644 --- a/drivers/pinctrl/mvebu/Kconfig +++ b/drivers/pinctrl/mvebu/Kconfig @@ -8,6 +8,7 @@ config PINCTRL_MVEBU config PINCTRL_DOVE bool select PINCTRL_MVEBU + select MFD_SYSCON config PINCTRL_KIRKWOOD bool @@ -17,8 +18,20 @@ config PINCTRL_ARMADA_370 bool select PINCTRL_MVEBU +config PINCTRL_ARMADA_375 + bool + select PINCTRL_MVEBU + +config PINCTRL_ARMADA_38X + bool + select PINCTRL_MVEBU + config PINCTRL_ARMADA_XP bool select PINCTRL_MVEBU +config PINCTRL_ORION + bool + select PINCTRL_MVEBU + endif diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile index 37c253297af..a0818e96374 100644 --- a/drivers/pinctrl/mvebu/Makefile +++ b/drivers/pinctrl/mvebu/Makefile @@ -2,4 +2,7 @@ obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o +obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o +obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o +obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 48e21a22948..670e5b01c67 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -23,6 +23,18 @@ #include "pinctrl-mvebu.h" +static void __iomem *mpp_base; + +static int armada_370_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + return default_mpp_ctrl_get(mpp_base, pid, config); +} + +static int armada_370_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + return default_mpp_ctrl_set(mpp_base, pid, config); +} + static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_MODE(0, MPP_FUNCTION(0x0, "gpio", NULL), @@ -373,7 +385,7 @@ static struct of_device_id armada_370_pinctrl_of_match[] = { }; static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = { - MPP_REG_CTRL(0, 65), + MPP_FUNC_CTRL(0, 65, NULL, armada_370_mpp_ctrl), }; static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = { @@ -385,6 +397,12 @@ static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = { static int armada_370_pinctrl_probe(struct platform_device *pdev) { struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mpp_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mpp_base)) + return PTR_ERR(mpp_base); soc->variant = 0; /* no variants for Armada 370 */ soc->controls = mv88f6710_mpp_controls; @@ -408,7 +426,7 @@ static struct platform_driver armada_370_pinctrl_driver = { .driver = { .name = "armada-370-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(armada_370_pinctrl_of_match), + .of_match_table = armada_370_pinctrl_of_match, }, .probe = armada_370_pinctrl_probe, .remove = armada_370_pinctrl_remove, diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c new file mode 100644 index 00000000000..db078fe7ace --- /dev/null +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -0,0 +1,459 @@ +/* + * Marvell Armada 375 pinctrl driver based on mvebu pinctrl core + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-mvebu.h" + +static void __iomem *mpp_base; + +static int armada_375_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + return default_mpp_ctrl_get(mpp_base, pid, config); +} + +static int armada_375_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + return default_mpp_ctrl_set(mpp_base, pid, config); +} + +static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { + MPP_MODE(0, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "ad2"), + MPP_FUNCTION(0x2, "spi0", "cs1"), + MPP_FUNCTION(0x3, "spi1", "cs1"), + MPP_FUNCTION(0x5, "nand", "io2")), + MPP_MODE(1, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "ad3"), + MPP_FUNCTION(0x2, "spi0", "mosi"), + MPP_FUNCTION(0x3, "spi1", "mosi"), + MPP_FUNCTION(0x5, "nand", "io3")), + MPP_MODE(2, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "ad4"), + MPP_FUNCTION(0x2, "ptp", "eventreq"), + MPP_FUNCTION(0x3, "led", "c0"), + MPP_FUNCTION(0x4, "audio", "sdi"), + MPP_FUNCTION(0x5, "nand", "io4"), + MPP_FUNCTION(0x6, "spi1", "mosi")), + MPP_MODE(3, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "ad5"), + MPP_FUNCTION(0x2, "ptp", "triggen"), + MPP_FUNCTION(0x3, "led", "p3"), + MPP_FUNCTION(0x4, "audio", "mclk"), + MPP_FUNCTION(0x5, "nand", "io5"), + MPP_FUNCTION(0x6, "spi1", "miso")), + MPP_MODE(4, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "ad6"), + MPP_FUNCTION(0x2, "spi0", "miso"), + MPP_FUNCTION(0x3, "spi1", "miso"), + MPP_FUNCTION(0x5, "nand", "io6")), + MPP_MODE(5, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "ad7"), + MPP_FUNCTION(0x2, "spi0", "cs2"), + MPP_FUNCTION(0x3, "spi1", "cs2"), + MPP_FUNCTION(0x5, "nand", "io7"), + MPP_FUNCTION(0x6, "spi1", "miso")), + MPP_MODE(6, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "ad0"), + MPP_FUNCTION(0x3, "led", "p1"), + MPP_FUNCTION(0x4, "audio", "rclk"), + MPP_FUNCTION(0x5, "nand", "io0")), + MPP_MODE(7, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "ad1"), + MPP_FUNCTION(0x2, "ptp", "clk"), + MPP_FUNCTION(0x3, "led", "p2"), + MPP_FUNCTION(0x4, "audio", "extclk"), + MPP_FUNCTION(0x5, "nand", "io1")), + MPP_MODE(8, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev ", "bootcs"), + MPP_FUNCTION(0x2, "spi0", "cs0"), + MPP_FUNCTION(0x3, "spi1", "cs0"), + MPP_FUNCTION(0x5, "nand", "ce")), + MPP_MODE(9, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "nf", "wen"), + MPP_FUNCTION(0x2, "spi0", "sck"), + MPP_FUNCTION(0x3, "spi1", "sck"), + MPP_FUNCTION(0x5, "nand", "we")), + MPP_MODE(10, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "nf", "ren"), + MPP_FUNCTION(0x2, "dram", "vttctrl"), + MPP_FUNCTION(0x3, "led", "c1"), + MPP_FUNCTION(0x5, "nand", "re"), + MPP_FUNCTION(0x6, "spi1", "sck")), + MPP_MODE(11, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "a0"), + MPP_FUNCTION(0x3, "led", "c2"), + MPP_FUNCTION(0x4, "audio", "sdo"), + MPP_FUNCTION(0x5, "nand", "cle")), + MPP_MODE(12, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "a1"), + MPP_FUNCTION(0x4, "audio", "bclk"), + MPP_FUNCTION(0x5, "nand", "ale")), + MPP_MODE(13, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "dev", "readyn"), + MPP_FUNCTION(0x2, "pcie0", "rstoutn"), + MPP_FUNCTION(0x3, "pcie1", "rstoutn"), + MPP_FUNCTION(0x5, "nand", "rb"), + MPP_FUNCTION(0x6, "spi1", "mosi")), + MPP_MODE(14, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "i2c0", "sda"), + MPP_FUNCTION(0x3, "uart1", "txd")), + MPP_MODE(15, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "i2c0", "sck"), + MPP_FUNCTION(0x3, "uart1", "rxd")), + MPP_MODE(16, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "uart0", "txd")), + MPP_MODE(17, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "uart0", "rxd")), + MPP_MODE(18, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "tdm", "intn")), + MPP_MODE(19, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "tdm", "rstn")), + MPP_MODE(20, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "tdm", "pclk")), + MPP_MODE(21, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "tdm", "fsync")), + MPP_MODE(22, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "tdm", "drx")), + MPP_MODE(23, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "tdm", "dtx")), + MPP_MODE(24, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "p0"), + MPP_FUNCTION(0x2, "ge1", "rxd0"), + MPP_FUNCTION(0x3, "sd", "cmd"), + MPP_FUNCTION(0x4, "uart0", "rts"), + MPP_FUNCTION(0x5, "spi0", "cs0"), + MPP_FUNCTION(0x6, "dev", "cs1")), + MPP_MODE(25, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "p2"), + MPP_FUNCTION(0x2, "ge1", "rxd1"), + MPP_FUNCTION(0x3, "sd", "d0"), + MPP_FUNCTION(0x4, "uart0", "cts"), + MPP_FUNCTION(0x5, "spi0", "mosi"), + MPP_FUNCTION(0x6, "dev", "cs2")), + MPP_MODE(26, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "pcie0", "clkreq"), + MPP_FUNCTION(0x2, "ge1", "rxd2"), + MPP_FUNCTION(0x3, "sd", "d2"), + MPP_FUNCTION(0x4, "uart1", "rts"), + MPP_FUNCTION(0x5, "spi0", "cs1"), + MPP_FUNCTION(0x6, "led", "c1")), + MPP_MODE(27, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "pcie1", "clkreq"), + MPP_FUNCTION(0x2, "ge1", "rxd3"), + MPP_FUNCTION(0x3, "sd", "d1"), + MPP_FUNCTION(0x4, "uart1", "cts"), + MPP_FUNCTION(0x5, "spi0", "miso"), + MPP_FUNCTION(0x6, "led", "c2")), + MPP_MODE(28, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "p3"), + MPP_FUNCTION(0x2, "ge1", "txctl"), + MPP_FUNCTION(0x3, "sd", "clk"), + MPP_FUNCTION(0x5, "dram", "vttctrl")), + MPP_MODE(29, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "pcie1", "clkreq"), + MPP_FUNCTION(0x2, "ge1", "rxclk"), + MPP_FUNCTION(0x3, "sd", "d3"), + MPP_FUNCTION(0x5, "spi0", "sck"), + MPP_FUNCTION(0x6, "pcie0", "rstoutn")), + MPP_MODE(30, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ge1", "txd0"), + MPP_FUNCTION(0x3, "spi1", "cs0"), + MPP_FUNCTION(0x5, "led", "p3"), + MPP_FUNCTION(0x6, "ptp", "eventreq")), + MPP_MODE(31, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ge1", "txd1"), + MPP_FUNCTION(0x3, "spi1", "mosi"), + MPP_FUNCTION(0x5, "led", "p0")), + MPP_MODE(32, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ge1", "txd2"), + MPP_FUNCTION(0x3, "spi1", "sck"), + MPP_FUNCTION(0x4, "ptp", "triggen"), + MPP_FUNCTION(0x5, "led", "c0")), + MPP_MODE(33, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ge1", "txd3"), + MPP_FUNCTION(0x3, "spi1", "miso"), + MPP_FUNCTION(0x5, "led", "p2")), + MPP_MODE(34, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ge1", "txclkout"), + MPP_FUNCTION(0x3, "spi1", "sck"), + MPP_FUNCTION(0x5, "led", "c1")), + MPP_MODE(35, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ge1", "rxctl"), + MPP_FUNCTION(0x3, "spi1", "cs1"), + MPP_FUNCTION(0x4, "spi0", "cs2"), + MPP_FUNCTION(0x5, "led", "p1")), + MPP_MODE(36, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "pcie0", "clkreq"), + MPP_FUNCTION(0x5, "led", "c2")), + MPP_MODE(37, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "pcie0", "clkreq"), + MPP_FUNCTION(0x2, "tdm", "intn"), + MPP_FUNCTION(0x4, "ge", "mdc")), + MPP_MODE(38, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "pcie1", "clkreq"), + MPP_FUNCTION(0x4, "ge", "mdio")), + MPP_MODE(39, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x4, "ref", "clkout"), + MPP_FUNCTION(0x5, "led", "p3")), + MPP_MODE(40, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x4, "uart1", "txd"), + MPP_FUNCTION(0x5, "led", "p0")), + MPP_MODE(41, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x4, "uart1", "rxd"), + MPP_FUNCTION(0x5, "led", "p1")), + MPP_MODE(42, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x3, "spi1", "cs2"), + MPP_FUNCTION(0x4, "led", "c0"), + MPP_FUNCTION(0x6, "ptp", "clk")), + MPP_MODE(43, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "sata0", "prsnt"), + MPP_FUNCTION(0x4, "dram", "vttctrl"), + MPP_FUNCTION(0x5, "led", "c1")), + MPP_MODE(44, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x4, "sata0", "prsnt")), + MPP_MODE(45, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "spi0", "cs2"), + MPP_FUNCTION(0x4, "pcie0", "rstoutn"), + MPP_FUNCTION(0x5, "led", "c2"), + MPP_FUNCTION(0x6, "spi1", "cs2")), + MPP_MODE(46, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "p0"), + MPP_FUNCTION(0x2, "ge0", "txd0"), + MPP_FUNCTION(0x3, "ge1", "txd0"), + MPP_FUNCTION(0x6, "dev", "wen1")), + MPP_MODE(47, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "p1"), + MPP_FUNCTION(0x2, "ge0", "txd1"), + MPP_FUNCTION(0x3, "ge1", "txd1"), + MPP_FUNCTION(0x5, "ptp", "triggen"), + MPP_FUNCTION(0x6, "dev", "ale0")), + MPP_MODE(48, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "p2"), + MPP_FUNCTION(0x2, "ge0", "txd2"), + MPP_FUNCTION(0x3, "ge1", "txd2"), + MPP_FUNCTION(0x6, "dev", "ale1")), + MPP_MODE(49, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "p3"), + MPP_FUNCTION(0x2, "ge0", "txd3"), + MPP_FUNCTION(0x3, "ge1", "txd3"), + MPP_FUNCTION(0x6, "dev", "a2")), + MPP_MODE(50, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "c0"), + MPP_FUNCTION(0x2, "ge0", "rxd0"), + MPP_FUNCTION(0x3, "ge1", "rxd0"), + MPP_FUNCTION(0x5, "ptp", "eventreq"), + MPP_FUNCTION(0x6, "dev", "ad12")), + MPP_MODE(51, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "c1"), + MPP_FUNCTION(0x2, "ge0", "rxd1"), + MPP_FUNCTION(0x3, "ge1", "rxd1"), + MPP_FUNCTION(0x6, "dev", "ad8")), + MPP_MODE(52, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "led", "c2"), + MPP_FUNCTION(0x2, "ge0", "rxd2"), + MPP_FUNCTION(0x3, "ge1", "rxd2"), + MPP_FUNCTION(0x5, "i2c0", "sda"), + MPP_FUNCTION(0x6, "dev", "ad9")), + MPP_MODE(53, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "pcie1", "rstoutn"), + MPP_FUNCTION(0x2, "ge0", "rxd3"), + MPP_FUNCTION(0x3, "ge1", "rxd3"), + MPP_FUNCTION(0x5, "i2c0", "sck"), + MPP_FUNCTION(0x6, "dev", "ad10")), + MPP_MODE(54, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "pcie0", "rstoutn"), + MPP_FUNCTION(0x2, "ge0", "rxctl"), + MPP_FUNCTION(0x3, "ge1", "rxctl"), + MPP_FUNCTION(0x6, "dev", "ad11")), + MPP_MODE(55, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ge0", "rxclk"), + MPP_FUNCTION(0x3, "ge1", "rxclk"), + MPP_FUNCTION(0x6, "dev", "cs0")), + MPP_MODE(56, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ge0", "txclkout"), + MPP_FUNCTION(0x3, "ge1", "txclkout"), + MPP_FUNCTION(0x6, "dev", "oe")), + MPP_MODE(57, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ge0", "txctl"), + MPP_FUNCTION(0x3, "ge1", "txctl"), + MPP_FUNCTION(0x6, "dev", "wen0")), + MPP_MODE(58, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x4, "led", "c0")), + MPP_MODE(59, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x4, "led", "c1")), + MPP_MODE(60, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "uart1", "txd"), + MPP_FUNCTION(0x4, "led", "c2"), + MPP_FUNCTION(0x6, "dev", "ad13")), + MPP_MODE(61, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "i2c1", "sda"), + MPP_FUNCTION(0x2, "uart1", "rxd"), + MPP_FUNCTION(0x3, "spi1", "cs2"), + MPP_FUNCTION(0x4, "led", "p0"), + MPP_FUNCTION(0x6, "dev", "ad14")), + MPP_MODE(62, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "i2c1", "sck"), + MPP_FUNCTION(0x4, "led", "p1"), + MPP_FUNCTION(0x6, "dev", "ad15")), + MPP_MODE(63, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ptp", "triggen"), + MPP_FUNCTION(0x4, "led", "p2"), + MPP_FUNCTION(0x6, "dev", "burst")), + MPP_MODE(64, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "dram", "vttctrl"), + MPP_FUNCTION(0x4, "led", "p3")), + MPP_MODE(65, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "sata1", "prsnt")), + MPP_MODE(66, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x2, "ptp", "eventreq"), + MPP_FUNCTION(0x4, "spi1", "cs3"), + MPP_FUNCTION(0x5, "pcie0", "rstoutn"), + MPP_FUNCTION(0x6, "dev", "cs3")), +}; + +static struct mvebu_pinctrl_soc_info armada_375_pinctrl_info; + +static struct of_device_id armada_375_pinctrl_of_match[] = { + { .compatible = "marvell,mv88f6720-pinctrl" }, + { }, +}; + +static struct mvebu_mpp_ctrl mv88f6720_mpp_controls[] = { + MPP_FUNC_CTRL(0, 69, NULL, armada_375_mpp_ctrl), +}; + +static struct pinctrl_gpio_range mv88f6720_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 32), + MPP_GPIO_RANGE(1, 32, 32, 32), + MPP_GPIO_RANGE(2, 64, 64, 3), +}; + +static int armada_375_pinctrl_probe(struct platform_device *pdev) +{ + struct mvebu_pinctrl_soc_info *soc = &armada_375_pinctrl_info; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mpp_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mpp_base)) + return PTR_ERR(mpp_base); + + soc->variant = 0; /* no variants for Armada 375 */ + soc->controls = mv88f6720_mpp_controls; + soc->ncontrols = ARRAY_SIZE(mv88f6720_mpp_controls); + soc->modes = mv88f6720_mpp_modes; + soc->nmodes = ARRAY_SIZE(mv88f6720_mpp_modes); + soc->gpioranges = mv88f6720_mpp_gpio_ranges; + soc->ngpioranges = ARRAY_SIZE(mv88f6720_mpp_gpio_ranges); + + pdev->dev.platform_data = soc; + + return mvebu_pinctrl_probe(pdev); +} + +static int armada_375_pinctrl_remove(struct platform_device *pdev) +{ + return mvebu_pinctrl_remove(pdev); +} + +static struct platform_driver armada_375_pinctrl_driver = { + .driver = { + .name = "armada-375-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(armada_375_pinctrl_of_match), + }, + .probe = armada_375_pinctrl_probe, + .remove = armada_375_pinctrl_remove, +}; + +module_platform_driver(armada_375_pinctrl_driver); + +MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Armada 375 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c new file mode 100644 index 00000000000..1049f82fb62 --- /dev/null +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -0,0 +1,462 @@ +/* + * Marvell Armada 380/385 pinctrl driver based on mvebu pinctrl core + * + * Copyright (C) 2013 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-mvebu.h" + +static void __iomem *mpp_base; + +static int armada_38x_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + return default_mpp_ctrl_get(mpp_base, pid, config); +} + +static int armada_38x_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + return default_mpp_ctrl_set(mpp_base, pid, config); +} + +enum { + V_88F6810 = BIT(0), + V_88F6820 = BIT(1), + V_88F6828 = BIT(2), + V_88F6810_PLUS = (V_88F6810 | V_88F6820 | V_88F6828), + V_88F6820_PLUS = (V_88F6820 | V_88F6828), +}; + +static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { + MPP_MODE(0, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ua0", "rxd", V_88F6810_PLUS)), + MPP_MODE(1, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ua0", "txd", V_88F6810_PLUS)), + MPP_MODE(2, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "i2c0", "sck", V_88F6810_PLUS)), + MPP_MODE(3, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "i2c0", "sda", V_88F6810_PLUS)), + MPP_MODE(4, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge", "mdc", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ua1", "txd", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS)), + MPP_MODE(5, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge", "mdio", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ua1", "rxd", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS)), + MPP_MODE(6, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txclkout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge0", "crs", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "cs3", V_88F6810_PLUS)), + MPP_MODE(7, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txd0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad9", V_88F6810_PLUS)), + MPP_MODE(8, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txd1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad10", V_88F6810_PLUS)), + MPP_MODE(9, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txd2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad11", V_88F6810_PLUS)), + MPP_MODE(10, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txd3", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6810_PLUS)), + MPP_MODE(11, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txctl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6810_PLUS)), + MPP_MODE(12, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxd0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "cs1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS)), + MPP_MODE(13, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxd1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "pcie0", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "cs2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS)), + MPP_MODE(14, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS)), + MPP_MODE(15, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxd3", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge", "mdc slave", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)), + MPP_MODE(16, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS)), + MPP_MODE(17, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS)), + MPP_MODE(18, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "trig_gen", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)), + MPP_MODE(19, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)), + MPP_MODE(20, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)), + MPP_MODE(21, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "rxd0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS)), + MPP_MODE(22, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad0", V_88F6810_PLUS)), + MPP_MODE(23, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "sck", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad2", V_88F6810_PLUS)), + MPP_MODE(24, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6810_PLUS)), + MPP_MODE(25, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d5", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6810_PLUS)), + MPP_MODE(26, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d6", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6810_PLUS)), + MPP_MODE(27, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "txclkout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d7", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6810_PLUS)), + MPP_MODE(28, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "txd0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6810_PLUS)), + MPP_MODE(29, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "txd1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ale0", V_88F6810_PLUS)), + MPP_MODE(30, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "txd2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6810_PLUS)), + MPP_MODE(31, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "txd3", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ale1", V_88F6810_PLUS)), + MPP_MODE(32, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "txctl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6810_PLUS)), + MPP_MODE(33, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6810_PLUS)), + MPP_MODE(34, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6810_PLUS)), + MPP_MODE(35, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6810_PLUS)), + MPP_MODE(36, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ptp", "trig_gen", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6810_PLUS)), + MPP_MODE(37, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ptp", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "rxclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d3", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6810_PLUS)), + MPP_MODE(38, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "rxd1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6810_PLUS)), + MPP_MODE(39, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "rxd2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6810_PLUS)), + MPP_MODE(40, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "rxd3", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6810_PLUS)), + MPP_MODE(41, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge1", "rxctl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS)), + MPP_MODE(42, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "ad7", V_88F6810_PLUS)), + MPP_MODE(43, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)), + MPP_MODE(44, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828), + MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828), + MPP_VAR_FUNCTION(5, "pcie0", "rstout", V_88F6810_PLUS)), + MPP_MODE(45, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)), + MPP_MODE(46, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)), + MPP_MODE(47, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828), + MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6828)), + MPP_MODE(48, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS)), + MPP_MODE(49, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828), + MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828), + MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS)), + MPP_MODE(50, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(3, "tdm2c", "drx", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)), + MPP_MODE(51, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm2c", "dtx", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "m", "decc_err", V_88F6810_PLUS)), + MPP_MODE(52, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(3, "tdm2c", "intn", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)), + MPP_MODE(53, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm2c", "rstn", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS)), + MPP_MODE(54, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6810_PLUS)), + MPP_MODE(55, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge", "mdio", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS)), + MPP_MODE(56, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS)), + MPP_MODE(57, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS)), + MPP_MODE(58, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "pcie1", "clkreq", V_88F6820_PLUS), + MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS)), + MPP_MODE(59, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6810_PLUS)), +}; + +static struct mvebu_pinctrl_soc_info armada_38x_pinctrl_info; + +static struct of_device_id armada_38x_pinctrl_of_match[] = { + { + .compatible = "marvell,mv88f6810-pinctrl", + .data = (void *) V_88F6810, + }, + { + .compatible = "marvell,mv88f6820-pinctrl", + .data = (void *) V_88F6820, + }, + { + .compatible = "marvell,mv88f6828-pinctrl", + .data = (void *) V_88F6828, + }, + { }, +}; + +static struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = { + MPP_FUNC_CTRL(0, 59, NULL, armada_38x_mpp_ctrl), +}; + +static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 32), + MPP_GPIO_RANGE(1, 32, 32, 27), +}; + +static int armada_38x_pinctrl_probe(struct platform_device *pdev) +{ + struct mvebu_pinctrl_soc_info *soc = &armada_38x_pinctrl_info; + const struct of_device_id *match = + of_match_device(armada_38x_pinctrl_of_match, &pdev->dev); + struct resource *res; + + if (!match) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mpp_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mpp_base)) + return PTR_ERR(mpp_base); + + soc->variant = (unsigned) match->data & 0xff; + soc->controls = armada_38x_mpp_controls; + soc->ncontrols = ARRAY_SIZE(armada_38x_mpp_controls); + soc->gpioranges = armada_38x_mpp_gpio_ranges; + soc->ngpioranges = ARRAY_SIZE(armada_38x_mpp_gpio_ranges); + soc->modes = armada_38x_mpp_modes; + soc->nmodes = armada_38x_mpp_controls[0].npins; + + pdev->dev.platform_data = soc; + + return mvebu_pinctrl_probe(pdev); +} + +static int armada_38x_pinctrl_remove(struct platform_device *pdev) +{ + return mvebu_pinctrl_remove(pdev); +} + +static struct platform_driver armada_38x_pinctrl_driver = { + .driver = { + .name = "armada-38x-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(armada_38x_pinctrl_of_match), + }, + .probe = armada_38x_pinctrl_probe, + .remove = armada_38x_pinctrl_remove, +}; + +module_platform_driver(armada_38x_pinctrl_driver); + +MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Armada 38x pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index ab5dc04b3e8..de311129f7a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -33,6 +33,18 @@ #include "pinctrl-mvebu.h" +static void __iomem *mpp_base; + +static int armada_xp_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + return default_mpp_ctrl_get(mpp_base, pid, config); +} + +static int armada_xp_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + return default_mpp_ctrl_set(mpp_base, pid, config); +} + enum armada_xp_variant { V_MV78230 = BIT(0), V_MV78260 = BIT(1), @@ -366,7 +378,7 @@ static struct of_device_id armada_xp_pinctrl_of_match[] = { }; static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = { - MPP_REG_CTRL(0, 48), + MPP_FUNC_CTRL(0, 48, NULL, armada_xp_mpp_ctrl), }; static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = { @@ -375,7 +387,7 @@ static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = { }; static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = { - MPP_REG_CTRL(0, 66), + MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl), }; static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = { @@ -385,7 +397,7 @@ static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = { }; static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = { - MPP_REG_CTRL(0, 66), + MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl), }; static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { @@ -399,10 +411,16 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev) struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info; const struct of_device_id *match = of_match_device(armada_xp_pinctrl_of_match, &pdev->dev); + struct resource *res; if (!match) return -ENODEV; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mpp_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mpp_base)) + return PTR_ERR(mpp_base); + soc->variant = (unsigned) match->data & 0xff; switch (soc->variant) { @@ -455,7 +473,7 @@ static struct platform_driver armada_xp_pinctrl_driver = { .driver = { .name = "armada-xp-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(armada_xp_pinctrl_of_match), + .of_match_table = armada_xp_pinctrl_of_match, }, .probe = armada_xp_pinctrl_probe, .remove = armada_xp_pinctrl_remove, diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index 428ea96a94d..3b022178a56 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c @@ -18,95 +18,122 @@ #include <linux/clk.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/mfd/syscon.h> #include <linux/pinctrl/pinctrl.h> +#include <linux/regmap.h> #include "pinctrl-mvebu.h" -#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) -#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) -#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) -#define DOVE_AU0_AC97_SEL BIT(16) -#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) -#define DOVE_TWSI_ENABLE_OPTION1 BIT(7) -#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) -#define DOVE_TWSI_ENABLE_OPTION2 BIT(20) -#define DOVE_TWSI_ENABLE_OPTION3 BIT(21) -#define DOVE_TWSI_OPTION3_GPIO BIT(22) -#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) -#define DOVE_SSP_ON_AU1 BIT(0) -#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) -#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) -#define DOVE_NAND_GPIO_EN BIT(0) -#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) -#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) -#define DOVE_SPI_GPIO_SEL BIT(5) -#define DOVE_UART1_GPIO_SEL BIT(4) -#define DOVE_AU1_GPIO_SEL BIT(3) -#define DOVE_CAM_GPIO_SEL BIT(2) -#define DOVE_SD1_GPIO_SEL BIT(1) -#define DOVE_SD0_GPIO_SEL BIT(0) - -#define MPPS_PER_REG 8 -#define MPP_BITS 4 -#define MPP_MASK 0xf +/* Internal registers can be configured at any 1 MiB aligned address */ +#define INT_REGS_MASK ~(SZ_1M - 1) +#define MPP4_REGS_OFFS 0xd0440 +#define PMU_REGS_OFFS 0xd802c +#define GC_REGS_OFFS 0xe802c + +/* MPP Base registers */ +#define PMU_MPP_GENERAL_CTRL 0x10 +#define AU0_AC97_SEL BIT(16) + +/* MPP Control 4 register */ +#define SPI_GPIO_SEL BIT(5) +#define UART1_GPIO_SEL BIT(4) +#define AU1_GPIO_SEL BIT(3) +#define CAM_GPIO_SEL BIT(2) +#define SD1_GPIO_SEL BIT(1) +#define SD0_GPIO_SEL BIT(0) + +/* PMU Signal Select registers */ +#define PMU_SIGNAL_SELECT_0 0x00 +#define PMU_SIGNAL_SELECT_1 0x04 + +/* Global Config regmap registers */ +#define GLOBAL_CONFIG_1 0x00 +#define TWSI_ENABLE_OPTION1 BIT(7) +#define GLOBAL_CONFIG_2 0x04 +#define TWSI_ENABLE_OPTION2 BIT(20) +#define TWSI_ENABLE_OPTION3 BIT(21) +#define TWSI_OPTION3_GPIO BIT(22) +#define SSP_CTRL_STATUS_1 0x08 +#define SSP_ON_AU1 BIT(0) +#define MPP_GENERAL_CONFIG 0x10 +#define AU1_SPDIFO_GPIO_EN BIT(1) +#define NAND_GPIO_EN BIT(0) #define CONFIG_PMU BIT(4) -static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl, - unsigned long *config) +static void __iomem *mpp_base; +static void __iomem *mpp4_base; +static void __iomem *pmu_base; +static struct regmap *gconfmap; + +static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + return default_mpp_ctrl_get(mpp_base, pid, config); +} + +static int dove_mpp_ctrl_set(unsigned pid, unsigned long config) { - unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; - unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; - unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); - unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off); - - if (pmu & (1 << ctrl->pid)) - *config = CONFIG_PMU; - else - *config = (mpp >> shift) & MPP_MASK; + return default_mpp_ctrl_set(mpp_base, pid, config); +} + +static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + unsigned long func; + + if ((pmu & BIT(pid)) == 0) + return default_mpp_ctrl_get(mpp_base, pid, config); + + func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); + *config = (func >> shift) & MVEBU_MPP_MASK; + *config |= CONFIG_PMU; + return 0; } -static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl, - unsigned long config) +static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) { - unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; - unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; - unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); - unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off); - - if (config == CONFIG_PMU) - writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); - else { - writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); - mpp &= ~(MPP_MASK << shift); - mpp |= config << shift; - writel(mpp, DOVE_MPP_VIRT_BASE + off); + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + unsigned long func; + + if ((config & CONFIG_PMU) == 0) { + writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); + return default_mpp_ctrl_set(mpp_base, pid, config); } + + writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); + func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); + func &= ~(MVEBU_MPP_MASK << shift); + func |= (config & MVEBU_MPP_MASK) << shift; + writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off); + return 0; } -static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl, - unsigned long *config) +static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) { - unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); + unsigned long mpp4 = readl(mpp4_base); unsigned long mask; - switch (ctrl->pid) { + switch (pid) { case 24: /* mpp_camera */ - mask = DOVE_CAM_GPIO_SEL; + mask = CAM_GPIO_SEL; break; case 40: /* mpp_sdio0 */ - mask = DOVE_SD0_GPIO_SEL; + mask = SD0_GPIO_SEL; break; case 46: /* mpp_sdio1 */ - mask = DOVE_SD1_GPIO_SEL; + mask = SD1_GPIO_SEL; break; case 58: /* mpp_spi0 */ - mask = DOVE_SPI_GPIO_SEL; + mask = SPI_GPIO_SEL; break; case 62: /* mpp_uart1 */ - mask = DOVE_UART1_GPIO_SEL; + mask = UART1_GPIO_SEL; break; default: return -EINVAL; @@ -117,27 +144,26 @@ static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl, return 0; } -static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl, - unsigned long config) +static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) { - unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); + unsigned long mpp4 = readl(mpp4_base); unsigned long mask; - switch (ctrl->pid) { + switch (pid) { case 24: /* mpp_camera */ - mask = DOVE_CAM_GPIO_SEL; + mask = CAM_GPIO_SEL; break; case 40: /* mpp_sdio0 */ - mask = DOVE_SD0_GPIO_SEL; + mask = SD0_GPIO_SEL; break; case 46: /* mpp_sdio1 */ - mask = DOVE_SD1_GPIO_SEL; + mask = SD1_GPIO_SEL; break; case 58: /* mpp_spi0 */ - mask = DOVE_SPI_GPIO_SEL; + mask = SPI_GPIO_SEL; break; case 62: /* mpp_uart1 */ - mask = DOVE_UART1_GPIO_SEL; + mask = UART1_GPIO_SEL; break; default: return -EINVAL; @@ -147,74 +173,69 @@ static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl, if (config) mpp4 |= mask; - writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); + writel(mpp4, mpp4_base); return 0; } -static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl, - unsigned long *config) +static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) { - unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); + unsigned int gmpp; - *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); + regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp); + *config = ((gmpp & NAND_GPIO_EN) != 0); return 0; } -static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl, - unsigned long config) +static int dove_nand_ctrl_set(unsigned pid, unsigned long config) { - unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); - - gmpp &= ~DOVE_NAND_GPIO_EN; - if (config) - gmpp |= DOVE_NAND_GPIO_EN; - - writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); - + regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG, + NAND_GPIO_EN, + (config) ? NAND_GPIO_EN : 0); return 0; } -static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl, - unsigned long *config) +static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config) { - unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); + unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); - *config = ((pmu & DOVE_AU0_AC97_SEL) != 0); + *config = ((pmu & AU0_AC97_SEL) != 0); return 0; } -static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl, - unsigned long config) +static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) { - unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); + unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); - pmu &= ~DOVE_AU0_AC97_SEL; + pmu &= ~AU0_AC97_SEL; if (config) - pmu |= DOVE_AU0_AC97_SEL; - writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL); + pmu |= AU0_AC97_SEL; + writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL); return 0; } -static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl, - unsigned long *config) +static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) { - unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); - unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); - unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); - unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); + unsigned int mpp4 = readl(mpp4_base); + unsigned int sspc1; + unsigned int gmpp; + unsigned int gcfg2; + + regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1); + regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp); + regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2); *config = 0; - if (mpp4 & DOVE_AU1_GPIO_SEL) + if (mpp4 & AU1_GPIO_SEL) *config |= BIT(3); - if (sspc1 & DOVE_SSP_ON_AU1) + if (sspc1 & SSP_ON_AU1) *config |= BIT(2); - if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) + if (gmpp & AU1_SPDIFO_GPIO_EN) *config |= BIT(1); - if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) + if (gcfg2 & TWSI_OPTION3_GPIO) *config |= BIT(0); /* SSP/TWSI only if I2S1 not set*/ @@ -226,35 +247,24 @@ static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl, return 0; } -static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl, - unsigned long config) +static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) { - unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); - unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); - unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); - unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); + unsigned int mpp4 = readl(mpp4_base); - /* - * clear all audio1 related bits before configure - */ - gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; - gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; - sspc1 &= ~DOVE_SSP_ON_AU1; - mpp4 &= ~DOVE_AU1_GPIO_SEL; - - if (config & BIT(0)) - gcfg2 |= DOVE_TWSI_OPTION3_GPIO; - if (config & BIT(1)) - gmpp |= DOVE_AU1_SPDIFO_GPIO_EN; - if (config & BIT(2)) - sspc1 |= DOVE_SSP_ON_AU1; + mpp4 &= ~AU1_GPIO_SEL; if (config & BIT(3)) - mpp4 |= DOVE_AU1_GPIO_SEL; - - writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); - writel(sspc1, DOVE_SSP_CTRL_STATUS_1); - writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); - writel(gcfg2, DOVE_GLOBAL_CONFIG_2); + mpp4 |= AU1_GPIO_SEL; + writel(mpp4, mpp4_base); + + regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1, + SSP_ON_AU1, + (config & BIT(2)) ? SSP_ON_AU1 : 0); + regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG, + AU1_SPDIFO_GPIO_EN, + (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0); + regmap_update_bits(gconfmap, GLOBAL_CONFIG_2, + TWSI_OPTION3_GPIO, + (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0); return 0; } @@ -264,11 +274,11 @@ static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl, * break other functions. If you require all mpps as gpio * enforce gpio setting by pinctrl mapping. */ -static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid) +static int dove_audio1_ctrl_gpio_req(unsigned pid) { unsigned long config; - dove_audio1_ctrl_get(ctrl, &config); + dove_audio1_ctrl_get(pid, &config); switch (config) { case 0x02: /* i2s1 : gpio[56:57] */ @@ -291,76 +301,62 @@ static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid) } /* mpp[52:57] has gpio pins capable of in and out */ -static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid, - bool input) +static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input) { if (pid < 52 || pid > 57) return -ENOTSUPP; return 0; } -static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl, - unsigned long *config) +static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) { - unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); - unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); + unsigned int gcfg1; + unsigned int gcfg2; + + regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1); + regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2); *config = 0; - if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) + if (gcfg1 & TWSI_ENABLE_OPTION1) *config = 1; - else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) + else if (gcfg2 & TWSI_ENABLE_OPTION2) *config = 2; - else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) + else if (gcfg2 & TWSI_ENABLE_OPTION3) *config = 3; return 0; } -static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl, - unsigned long config) +static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) { - unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); - unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); - - gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; - gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2); + unsigned int gcfg1 = 0; + unsigned int gcfg2 = 0; switch (config) { case 1: - gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; + gcfg1 = TWSI_ENABLE_OPTION1; break; case 2: - gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; + gcfg2 = TWSI_ENABLE_OPTION2; break; case 3: - gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; + gcfg2 = TWSI_ENABLE_OPTION3; break; } - writel(gcfg1, DOVE_GLOBAL_CONFIG_1); - writel(gcfg2, DOVE_GLOBAL_CONFIG_2); + regmap_update_bits(gconfmap, GLOBAL_CONFIG_1, + TWSI_ENABLE_OPTION1, + gcfg1); + regmap_update_bits(gconfmap, GLOBAL_CONFIG_2, + TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3, + gcfg2); return 0; } static struct mvebu_mpp_ctrl dove_mpp_controls[] = { - MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl), - MPP_REG_CTRL(16, 23), + MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl), + MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl), MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), @@ -378,20 +374,53 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = { MPP_FUNCTION(0x02, "uart2", "rts"), MPP_FUNCTION(0x03, "sdio0", "cd"), MPP_FUNCTION(0x0f, "lcd0", "pwm"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(1, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart2", "cts"), MPP_FUNCTION(0x03, "sdio0", "wp"), MPP_FUNCTION(0x0f, "lcd1", "pwm"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(2, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "sata", "prsnt"), MPP_FUNCTION(0x02, "uart2", "txd"), MPP_FUNCTION(0x03, "sdio0", "buspwr"), MPP_FUNCTION(0x04, "uart1", "rts"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(3, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "sata", "act"), @@ -399,43 +428,131 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = { MPP_FUNCTION(0x03, "sdio0", "ledctrl"), MPP_FUNCTION(0x04, "uart1", "cts"), MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(4, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "rts"), MPP_FUNCTION(0x03, "sdio1", "cd"), MPP_FUNCTION(0x04, "spi1", "miso"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(5, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "cts"), MPP_FUNCTION(0x03, "sdio1", "wp"), MPP_FUNCTION(0x04, "spi1", "cs"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(6, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "txd"), MPP_FUNCTION(0x03, "sdio1", "buspwr"), MPP_FUNCTION(0x04, "spi1", "mosi"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(7, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "rxd"), MPP_FUNCTION(0x03, "sdio1", "ledctrl"), MPP_FUNCTION(0x04, "spi1", "sck"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(8, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "watchdog", "rstout"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(9, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x05, "pex1", "clkreq"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(10, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x05, "ssp", "sclk"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(11, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "sata", "prsnt"), @@ -443,33 +560,88 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = { MPP_FUNCTION(0x03, "sdio0", "ledctrl"), MPP_FUNCTION(0x04, "sdio1", "ledctrl"), MPP_FUNCTION(0x05, "pex0", "clkreq"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(12, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x01, "sata", "act"), MPP_FUNCTION(0x02, "uart2", "rts"), MPP_FUNCTION(0x03, "audio0", "extclk"), MPP_FUNCTION(0x04, "sdio1", "cd"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(13, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart2", "cts"), MPP_FUNCTION(0x03, "audio1", "extclk"), MPP_FUNCTION(0x04, "sdio1", "wp"), MPP_FUNCTION(0x05, "ssp", "extclk"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(14, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart2", "txd"), MPP_FUNCTION(0x04, "sdio1", "buspwr"), MPP_FUNCTION(0x05, "ssp", "rxd"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(15, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart2", "rxd"), MPP_FUNCTION(0x04, "sdio1", "ledctrl"), MPP_FUNCTION(0x05, "ssp", "sfrm"), - MPP_FUNCTION(0x10, "pmu", NULL)), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), MPP_MODE(16, MPP_FUNCTION(0x00, "gpio", NULL), MPP_FUNCTION(0x02, "uart3", "rts"), @@ -584,8 +756,17 @@ static struct of_device_id dove_pinctrl_of_match[] = { { } }; +static struct regmap_config gc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 5, +}; + static int dove_pinctrl_probe(struct platform_device *pdev) { + struct resource *res, *mpp_res; + struct resource fb_res; const struct of_device_id *match = of_match_device(dove_pinctrl_of_match, &pdev->dev); pdev->dev.platform_data = (void *)match->data; @@ -597,10 +778,63 @@ static int dove_pinctrl_probe(struct platform_device *pdev) clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(clk)) { dev_err(&pdev->dev, "Unable to get pdma clock"); - return PTR_RET(clk); + return PTR_ERR(clk); } clk_prepare_enable(clk); + mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res); + if (IS_ERR(mpp_base)) + return PTR_ERR(mpp_base); + + /* prepare fallback resource */ + memcpy(&fb_res, mpp_res, sizeof(struct resource)); + fb_res.start = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n"); + adjust_resource(&fb_res, + (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4); + res = &fb_res; + } + + mpp4_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mpp4_base)) + return PTR_ERR(mpp4_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) { + dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n"); + adjust_resource(&fb_res, + (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8); + res = &fb_res; + } + + pmu_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmu_base)) + return PTR_ERR(pmu_base); + + gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config"); + if (IS_ERR(gconfmap)) { + void __iomem *gc_base; + + dev_warn(&pdev->dev, "falling back to hardcoded global registers\n"); + adjust_resource(&fb_res, + (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14); + gc_base = devm_ioremap_resource(&pdev->dev, &fb_res); + if (IS_ERR(gc_base)) + return PTR_ERR(gc_base); + gconfmap = devm_regmap_init_mmio(&pdev->dev, + gc_base, &gc_regmap_config); + if (IS_ERR(gconfmap)) + return PTR_ERR(gconfmap); + } + + /* Warn on any missing DT resource */ + if (fb_res.start) + dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n"); + return mvebu_pinctrl_probe(pdev); } @@ -618,7 +852,7 @@ static struct platform_driver dove_pinctrl_driver = { .driver = { .name = "dove-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(dove_pinctrl_of_match), + .of_match_table = dove_pinctrl_of_match, }, .probe = dove_pinctrl_probe, .remove = dove_pinctrl_remove, diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c index cdd483df673..0d0211a1a0b 100644 --- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c +++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c @@ -21,6 +21,18 @@ #include "pinctrl-mvebu.h" +static void __iomem *mpp_base; + +static int kirkwood_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + return default_mpp_ctrl_get(mpp_base, pid, config); +} + +static int kirkwood_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + return default_mpp_ctrl_set(mpp_base, pid, config); +} + #define V(f6180, f6190, f6192, f6281, f6282, dx4122) \ ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \ (f6281 << 3) | (f6282 << 4) | (dx4122 << 5)) @@ -359,7 +371,7 @@ static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = { }; static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = { - MPP_REG_CTRL(0, 29), + MPP_FUNC_CTRL(0, 29, NULL, kirkwood_mpp_ctrl), }; static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = { @@ -367,7 +379,7 @@ static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = { }; static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = { - MPP_REG_CTRL(0, 35), + MPP_FUNC_CTRL(0, 35, NULL, kirkwood_mpp_ctrl), }; static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = { @@ -376,7 +388,7 @@ static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = { }; static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = { - MPP_REG_CTRL(0, 49), + MPP_FUNC_CTRL(0, 49, NULL, kirkwood_mpp_ctrl), }; static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = { @@ -456,9 +468,16 @@ static struct of_device_id kirkwood_pinctrl_of_match[] = { static int kirkwood_pinctrl_probe(struct platform_device *pdev) { + struct resource *res; const struct of_device_id *match = of_match_device(kirkwood_pinctrl_of_match, &pdev->dev); pdev->dev.platform_data = (void *)match->data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mpp_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mpp_base)) + return PTR_ERR(mpp_base); + return mvebu_pinctrl_probe(pdev); } @@ -471,7 +490,7 @@ static struct platform_driver kirkwood_pinctrl_driver = { .driver = { .name = "kirkwood-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(kirkwood_pinctrl_of_match), + .of_match_table = kirkwood_pinctrl_of_match, }, .probe = kirkwood_pinctrl_probe, .remove = kirkwood_pinctrl_remove, diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index bb7ddb1bc89..9908374f8f9 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -50,7 +50,6 @@ struct mvebu_pinctrl { struct device *dev; struct pinctrl_dev *pctldev; struct pinctrl_desc desc; - void __iomem *base; struct mvebu_pinctrl_group *groups; unsigned num_groups; struct mvebu_pinctrl_function *functions; @@ -138,43 +137,6 @@ static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name( return NULL; } -/* - * Common mpp pin configuration registers on MVEBU are - * registers of eight 4-bit values for each mpp setting. - * Register offset and bit mask are calculated accordingly below. - */ -static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl, - struct mvebu_pinctrl_group *grp, - unsigned long *config) -{ - unsigned pin = grp->gid; - unsigned off = (pin / MPPS_PER_REG) * MPP_BITS; - unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS; - - *config = readl(pctl->base + off); - *config >>= shift; - *config &= MPP_MASK; - - return 0; -} - -static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl, - struct mvebu_pinctrl_group *grp, - unsigned long config) -{ - unsigned pin = grp->gid; - unsigned off = (pin / MPPS_PER_REG) * MPP_BITS; - unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS; - unsigned long reg; - - reg = readl(pctl->base + off); - reg &= ~(MPP_MASK << shift); - reg |= (config << shift); - writel(reg, pctl->base + off); - - return 0; -} - static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned gid, unsigned long *config) { @@ -184,25 +146,27 @@ static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev, if (!grp->ctrl) return -EINVAL; - if (grp->ctrl->mpp_get) - return grp->ctrl->mpp_get(grp->ctrl, config); - - return mvebu_common_mpp_get(pctl, grp, config); + return grp->ctrl->mpp_get(grp->pins[0], config); } static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned gid, unsigned long config) + unsigned gid, unsigned long *configs, + unsigned num_configs) { struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct mvebu_pinctrl_group *grp = &pctl->groups[gid]; + int i, ret; if (!grp->ctrl) return -EINVAL; - if (grp->ctrl->mpp_set) - return grp->ctrl->mpp_set(grp->ctrl, config); + for (i = 0; i < num_configs; i++) { + ret = grp->ctrl->mpp_set(grp->pins[0], configs[i]); + if (ret) + return ret; + } /* for each config */ - return mvebu_common_mpp_set(pctl, grp, config); + return 0; } static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, @@ -303,6 +267,7 @@ static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid, struct mvebu_pinctrl_group *grp = &pctl->groups[gid]; struct mvebu_mpp_ctrl_setting *setting; int ret; + unsigned long config; setting = mvebu_pinctrl_find_setting_by_name(pctl, grp, func->name); @@ -313,7 +278,8 @@ static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid, return -EINVAL; } - ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val); + config = setting->val; + ret = mvebu_pinconf_group_set(pctldev, grp->gid, &config, 1); if (ret) { dev_err(pctl->dev, "cannot set group %s to %s\n", func->groups[gid], func->name); @@ -329,19 +295,22 @@ static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct mvebu_pinctrl_group *grp; struct mvebu_mpp_ctrl_setting *setting; + unsigned long config; grp = mvebu_pinctrl_find_group_by_pid(pctl, offset); if (!grp) return -EINVAL; if (grp->ctrl->mpp_gpio_req) - return grp->ctrl->mpp_gpio_req(grp->ctrl, offset); + return grp->ctrl->mpp_gpio_req(offset); setting = mvebu_pinctrl_find_gpio_setting(pctl, grp); if (!setting) return -ENOTSUPP; - return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val); + config = setting->val; + + return mvebu_pinconf_group_set(pctldev, grp->gid, &config, 1); } static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, @@ -356,7 +325,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, return -EINVAL; if (grp->ctrl->mpp_gpio_dir) - return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input); + return grp->ctrl->mpp_gpio_dir(offset, input); setting = mvebu_pinctrl_find_gpio_setting(pctl, grp); if (!setting) @@ -430,7 +399,7 @@ static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, } *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); - if (map == NULL) { + if (*map == NULL) { dev_err(pctl->dev, "cannot allocate pinctrl_map memory for %s\n", np->name); @@ -579,11 +548,12 @@ static int mvebu_pinctrl_build_functions(struct platform_device *pdev, int mvebu_pinctrl_probe(struct platform_device *pdev) { struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev); - struct device_node *np = pdev->dev.of_node; struct mvebu_pinctrl *pctl; - void __iomem *base; struct pinctrl_pin_desc *pdesc; unsigned gid, n, k; + unsigned size, noname = 0; + char *noname_buf; + void *p; int ret; if (!soc || !soc->controls || !soc->modes) { @@ -591,12 +561,6 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) return -EINVAL; } - base = of_iomap(np, 0); - if (!base) { - dev_err(&pdev->dev, "unable to get base address\n"); - return -ENODEV; - } - pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl), GFP_KERNEL); if (!pctl) { @@ -610,7 +574,6 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) pctl->desc.pmxops = &mvebu_pinmux_ops; pctl->desc.confops = &mvebu_pinconf_ops; pctl->variant = soc->variant; - pctl->base = base; pctl->dev = &pdev->dev; platform_set_drvdata(pdev, pctl); @@ -620,33 +583,23 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) pctl->desc.npins = 0; for (n = 0; n < soc->ncontrols; n++) { struct mvebu_mpp_ctrl *ctrl = &soc->controls[n]; - char *names; pctl->desc.npins += ctrl->npins; - /* initial control pins */ + /* initialize control's pins[] array */ for (k = 0; k < ctrl->npins; k++) ctrl->pins[k] = ctrl->pid + k; - /* special soc specific control */ - if (ctrl->mpp_get || ctrl->mpp_set) { - if (!ctrl->name || !ctrl->mpp_get || !ctrl->mpp_set) { - dev_err(&pdev->dev, "wrong soc control info\n"); - return -EINVAL; - } + /* + * We allow to pass controls with NULL name that we treat + * as a range of one-pin groups with generic mvebu register + * controls. + */ + if (!ctrl->name) { + pctl->num_groups += ctrl->npins; + noname += ctrl->npins; + } else { pctl->num_groups += 1; - continue; } - - /* generic mvebu register control */ - names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL); - if (!names) { - dev_err(&pdev->dev, "failed to alloc mpp names\n"); - return -ENOMEM; - } - for (k = 0; k < ctrl->npins; k++) - sprintf(names + 8*k, "mpp%d", ctrl->pid+k); - ctrl->name = names; - pctl->num_groups += ctrl->npins; } pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins * @@ -660,12 +613,17 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) pdesc[n].number = n; pctl->desc.pins = pdesc; - pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups * - sizeof(struct mvebu_pinctrl_group), GFP_KERNEL); - if (!pctl->groups) { - dev_err(&pdev->dev, "failed to alloc pinctrl groups\n"); + /* + * allocate groups and name buffers for unnamed groups. + */ + size = pctl->num_groups * sizeof(*pctl->groups) + noname * 8; + p = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); + if (!p) { + dev_err(&pdev->dev, "failed to alloc group data\n"); return -ENOMEM; } + pctl->groups = p; + noname_buf = p + pctl->num_groups * sizeof(*pctl->groups); /* assign mpp controls to groups */ gid = 0; @@ -677,17 +635,26 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) pctl->groups[gid].pins = ctrl->pins; pctl->groups[gid].npins = ctrl->npins; - /* generic mvebu register control maps to a number of groups */ - if (!ctrl->mpp_get && !ctrl->mpp_set) { + /* + * We treat unnamed controls as a range of one-pin groups + * with generic mvebu register controls. Use one group for + * each in this range and assign a default group name. + */ + if (!ctrl->name) { + pctl->groups[gid].name = noname_buf; pctl->groups[gid].npins = 1; + sprintf(noname_buf, "mpp%d", ctrl->pid+0); + noname_buf += 8; for (k = 1; k < ctrl->npins; k++) { gid++; pctl->groups[gid].gid = gid; pctl->groups[gid].ctrl = ctrl; - pctl->groups[gid].name = &ctrl->name[8*k]; + pctl->groups[gid].name = noname_buf; pctl->groups[gid].pins = &ctrl->pins[k]; pctl->groups[gid].npins = 1; + sprintf(noname_buf, "mpp%d", ctrl->pid+k); + noname_buf += 8; } } gid++; diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h b/drivers/pinctrl/mvebu/pinctrl-mvebu.h index 90bd3beee86..65a98e6f726 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.h +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h @@ -28,20 +28,19 @@ * between two or more different settings, e.g. assign mpp pin 13 to * uart1 or sata. * - * If optional mpp_get/_set functions are set these are used to get/set - * a specific mode. Otherwise it is assumed that the mpp control is based - * on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir - * functions can be used to allow pin settings with varying gpio pins. + * The mpp_get/_set functions are mandatory and are used to get/set a + * specific mode. The optional mpp_gpio_req/_dir functions can be used + * to allow pin settings with varying gpio pins. */ struct mvebu_mpp_ctrl { const char *name; u8 pid; u8 npins; unsigned *pins; - int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config); - int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config); - int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid); - int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input); + int (*mpp_get)(unsigned pid, unsigned long *config); + int (*mpp_set)(unsigned pid, unsigned long config); + int (*mpp_gpio_req)(unsigned pid); + int (*mpp_gpio_dir)(unsigned pid, bool input); }; /** @@ -114,18 +113,6 @@ struct mvebu_pinctrl_soc_info { int ngpioranges; }; -#define MPP_REG_CTRL(_idl, _idh) \ - { \ - .name = NULL, \ - .pid = _idl, \ - .npins = _idh - _idl + 1, \ - .pins = (unsigned[_idh - _idl + 1]) { }, \ - .mpp_get = NULL, \ - .mpp_set = NULL, \ - .mpp_gpio_req = NULL, \ - .mpp_gpio_dir = NULL, \ - } - #define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \ { \ .name = _name, \ @@ -186,6 +173,34 @@ struct mvebu_pinctrl_soc_info { .npins = _npins, \ } +#define MVEBU_MPPS_PER_REG 8 +#define MVEBU_MPP_BITS 4 +#define MVEBU_MPP_MASK 0xf + +static inline int default_mpp_ctrl_get(void __iomem *base, unsigned int pid, + unsigned long *config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + + *config = (readl(base + off) >> shift) & MVEBU_MPP_MASK; + + return 0; +} + +static inline int default_mpp_ctrl_set(void __iomem *base, unsigned int pid, + unsigned long config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned long reg; + + reg = readl(base + off) & ~(MVEBU_MPP_MASK << shift); + writel(reg | (config << shift), base + off); + + return 0; +} + int mvebu_pinctrl_probe(struct platform_device *pdev); int mvebu_pinctrl_remove(struct platform_device *pdev); diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c new file mode 100644 index 00000000000..dda1e7254e1 --- /dev/null +++ b/drivers/pinctrl/mvebu/pinctrl-orion.c @@ -0,0 +1,261 @@ +/* + * Marvell Orion pinctrl driver based on mvebu pinctrl core + * + * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The first 16 MPP pins on Orion are easy to handle: they are + * configured through 2 consecutive registers, located at the base + * address of the MPP device. + * + * However the last 4 MPP pins are handled by a register at offset + * 0x50 from the base address, so it is not consecutive with the first + * two registers. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-mvebu.h" + +static void __iomem *mpp_base; +static void __iomem *high_mpp_base; + +static int orion_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + + if (pid < 16) { + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + *config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK; + } + else { + *config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK; + } + + return 0; +} + +static int orion_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + + if (pid < 16) { + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift); + writel(reg | (config << shift), mpp_base + off); + } + else { + u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift); + writel(reg | (config << shift), high_mpp_base); + } + + return 0; +} + +#define V(f5181l, f5182, f5281) \ + ((f5181l << 0) | (f5182 << 1) | (f5281 << 2)) + +enum orion_variant { + V_5181L = V(1, 0, 0), + V_5182 = V(0, 1, 0), + V_5281 = V(0, 0, 1), + V_ALL = V(1, 1, 1), +}; + +static struct mvebu_mpp_mode orion_mpp_modes[] = { + MPP_MODE(0, + MPP_VAR_FUNCTION(0x0, "pcie", "rstout", V_ALL), + MPP_VAR_FUNCTION(0x2, "pci", "req2", V_ALL), + MPP_VAR_FUNCTION(0x3, "gpio", NULL, V_ALL)), + MPP_MODE(1, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x2, "pci", "gnt2", V_ALL)), + MPP_MODE(2, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x2, "pci", "req3", V_ALL), + MPP_VAR_FUNCTION(0x3, "pci-1", "pme", V_ALL)), + MPP_MODE(3, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x2, "pci", "gnt3", V_ALL)), + MPP_MODE(4, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x2, "pci", "req4", V_ALL), + MPP_VAR_FUNCTION(0x4, "bootnand", "re", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V_5182)), + MPP_MODE(5, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x2, "pci", "gnt4", V_ALL), + MPP_VAR_FUNCTION(0x4, "bootnand", "we", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V_5182)), + MPP_MODE(6, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL), + MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L), + MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)), + MPP_MODE(7, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL), + MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L), + MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)), + MPP_MODE(8, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x1, "ge", "col", V_ALL)), + MPP_MODE(9, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x1, "ge", "rxerr", V_ALL)), + MPP_MODE(10, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x1, "ge", "crs", V_ALL)), + MPP_MODE(11, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x1, "ge", "txerr", V_ALL)), + MPP_MODE(12, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x1, "ge", "txd4", V_ALL), + MPP_VAR_FUNCTION(0x4, "nand", "re1", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)), + MPP_MODE(13, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x1, "ge", "txd5", V_ALL), + MPP_VAR_FUNCTION(0x4, "nand", "we1", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)), + MPP_MODE(14, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x1, "ge", "txd6", V_ALL), + MPP_VAR_FUNCTION(0x4, "nand", "re2", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x5, "sata0", "ledact", V_5182)), + MPP_MODE(15, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), + MPP_VAR_FUNCTION(0x1, "ge", "txd7", V_ALL), + MPP_VAR_FUNCTION(0x4, "nand", "we2", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x5, "sata1", "ledact", V_5182)), + MPP_MODE(16, + MPP_VAR_FUNCTION(0x0, "uart1", "rxd", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x1, "ge", "rxd4", V_ALL), + MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)), + MPP_MODE(17, + MPP_VAR_FUNCTION(0x0, "uart1", "txd", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x1, "ge", "rxd5", V_ALL), + MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)), + MPP_MODE(18, + MPP_VAR_FUNCTION(0x0, "uart1", "cts", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x1, "ge", "rxd6", V_ALL), + MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)), + MPP_MODE(19, + MPP_VAR_FUNCTION(0x0, "uart1", "rts", V_5182 | V_5281), + MPP_VAR_FUNCTION(0x1, "ge", "rxd7", V_ALL), + MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)), +}; + +static struct mvebu_mpp_ctrl orion_mpp_controls[] = { + MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl), +}; + +static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 16), +}; + +static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 19), +}; + +static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 16), +}; + +static struct mvebu_pinctrl_soc_info mv88f5181l_info = { + .variant = V_5181L, + .controls = orion_mpp_controls, + .ncontrols = ARRAY_SIZE(orion_mpp_controls), + .modes = orion_mpp_modes, + .nmodes = ARRAY_SIZE(orion_mpp_modes), + .gpioranges = mv88f5181l_gpio_ranges, + .ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges), +}; + +static struct mvebu_pinctrl_soc_info mv88f5182_info = { + .variant = V_5182, + .controls = orion_mpp_controls, + .ncontrols = ARRAY_SIZE(orion_mpp_controls), + .modes = orion_mpp_modes, + .nmodes = ARRAY_SIZE(orion_mpp_modes), + .gpioranges = mv88f5182_gpio_ranges, + .ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges), +}; + +static struct mvebu_pinctrl_soc_info mv88f5281_info = { + .variant = V_5281, + .controls = orion_mpp_controls, + .ncontrols = ARRAY_SIZE(orion_mpp_controls), + .modes = orion_mpp_modes, + .nmodes = ARRAY_SIZE(orion_mpp_modes), + .gpioranges = mv88f5281_gpio_ranges, + .ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges), +}; + +/* + * There are multiple variants of the Orion SoCs, but in terms of pin + * muxing, they are identical. + */ +static struct of_device_id orion_pinctrl_of_match[] = { + { .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info }, + { .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info }, + { .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info }, + { } +}; + +static int orion_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match = + of_match_device(orion_pinctrl_of_match, &pdev->dev); + struct resource *res; + + pdev->dev.platform_data = (void*)match->data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mpp_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mpp_base)) + return PTR_ERR(mpp_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + high_mpp_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(high_mpp_base)) + return PTR_ERR(high_mpp_base); + + return mvebu_pinctrl_probe(pdev); +} + +static int orion_pinctrl_remove(struct platform_device *pdev) +{ + return mvebu_pinctrl_remove(pdev); +} + +static struct platform_driver orion_pinctrl_driver = { + .driver = { + .name = "orion-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(orion_pinctrl_of_match), + }, + .probe = orion_pinctrl_probe, + .remove = orion_pinctrl_remove, +}; + +module_platform_driver(orion_pinctrl_driver); + +MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Orion pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 2ad5a8d337b..29ff77f90fc 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -21,8 +21,10 @@ #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/of.h> #include "core.h" #include "pinconf.h" +#include "pinctrl-utils.h" #ifdef CONFIG_DEBUG_FS @@ -37,14 +39,19 @@ struct pin_config_item { static struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL), PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL), + PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL), PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL), PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, + "input bias pull to pin specific state", NULL), PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL), + PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA"), + PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL), - PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "time units"), + PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec"), PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"), PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL), PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"), @@ -135,3 +142,198 @@ void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, } EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); #endif + +#ifdef CONFIG_OF +struct pinconf_generic_dt_params { + const char * const property; + enum pin_config_param param; + u32 default_value; +}; + +static struct pinconf_generic_dt_params dt_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, + { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0}, +}; + +/** + * pinconf_generic_parse_dt_config() + * parse the config properties into generic pinconfig values. + * @np: node containing the pinconfig properties + * @configs: array with nconfigs entries containing the generic pinconf values + * @nconfigs: umber of configurations + */ +int pinconf_generic_parse_dt_config(struct device_node *np, + unsigned long **configs, + unsigned int *nconfigs) +{ + unsigned long *cfg; + unsigned int ncfg = 0; + int ret; + int i; + u32 val; + + if (!np) + return -EINVAL; + + /* allocate a temporary array big enough to hold one of each option */ + cfg = kzalloc(sizeof(*cfg) * ARRAY_SIZE(dt_params), GFP_KERNEL); + if (!cfg) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(dt_params); i++) { + struct pinconf_generic_dt_params *par = &dt_params[i]; + ret = of_property_read_u32(np, par->property, &val); + + /* property not found */ + if (ret == -EINVAL) + continue; + + /* use default value, when no value is specified */ + if (ret) + val = par->default_value; + + pr_debug("found %s with value %u\n", par->property, val); + cfg[ncfg] = pinconf_to_config_packed(par->param, val); + ncfg++; + } + + ret = 0; + + /* no configs found at all */ + if (ncfg == 0) { + *configs = NULL; + *nconfigs = 0; + goto out; + } + + /* + * Now limit the number of configs to the real number of + * found properties. + */ + *configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL); + if (!*configs) { + ret = -ENOMEM; + goto out; + } + + *nconfigs = ncfg; + +out: + kfree(cfg); + return ret; +} + +int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, struct pinctrl_map **map, + unsigned *reserved_maps, unsigned *num_maps, + enum pinctrl_map_type type) +{ + int ret; + const char *function; + struct device *dev = pctldev->dev; + unsigned long *configs = NULL; + unsigned num_configs = 0; + unsigned reserve; + struct property *prop; + const char *group; + + ret = of_property_read_string(np, "function", &function); + if (ret < 0) { + /* EINVAL=missing, which is fine since it's optional */ + if (ret != -EINVAL) + dev_err(dev, "could not parse property function\n"); + function = NULL; + } + + ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + if (ret < 0) { + dev_err(dev, "could not parse node property\n"); + return ret; + } + + reserve = 0; + if (function != NULL) + reserve++; + if (num_configs) + reserve++; + ret = of_property_count_strings(np, "pins"); + if (ret < 0) { + dev_err(dev, "could not parse property pins\n"); + goto exit; + } + reserve *= ret; + + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, + num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "pins", prop, group) { + if (function) { + ret = pinctrl_utils_add_map_mux(pctldev, map, + reserved_maps, num_maps, group, + function); + if (ret < 0) + goto exit; + } + + if (num_configs) { + ret = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, group, configs, + num_configs, type); + if (ret < 0) + goto exit; + } + } + ret = 0; + +exit: + kfree(configs); + return ret; +} +EXPORT_SYMBOL_GPL(pinconf_generic_dt_subnode_to_map); + +int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, struct pinctrl_map **map, + unsigned *num_maps, enum pinctrl_map_type type) +{ + unsigned reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps, type); + if (ret < 0) { + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map); + +#endif diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index c67c37e23dd..8bfa0643e5d 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -28,12 +28,6 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev) { const struct pinconf_ops *ops = pctldev->desc->confops; - /* We must be able to read out pin status */ - if (!ops->pin_config_get && !ops->pin_config_group_get) { - dev_err(pctldev->dev, - "pinconf must be able to read out pin status\n"); - return -EINVAL; - } /* We have to be able to config the pins in SOME way */ if (!ops->pin_config_set && !ops->pin_config_group_set) { dev_err(pctldev->dev, @@ -67,106 +61,14 @@ int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin, const struct pinconf_ops *ops = pctldev->desc->confops; if (!ops || !ops->pin_config_get) { - dev_err(pctldev->dev, "cannot get pin configuration, missing " + dev_dbg(pctldev->dev, "cannot get pin configuration, missing " "pin_config_get() function in driver\n"); - return -EINVAL; + return -ENOTSUPP; } return ops->pin_config_get(pctldev, pin, config); } -/** - * pin_config_get() - get the configuration of a single pin parameter - * @dev_name: name of the pin controller device for this pin - * @name: name of the pin to get the config for - * @config: the config pointed to by this argument will be filled in with the - * current pin state, it can be used directly by drivers as a numeral, or - * it can be dereferenced to any struct. - */ -int pin_config_get(const char *dev_name, const char *name, - unsigned long *config) -{ - struct pinctrl_dev *pctldev; - int pin; - - pctldev = get_pinctrl_dev_from_devname(dev_name); - if (!pctldev) { - pin = -EINVAL; - return pin; - } - - mutex_lock(&pctldev->mutex); - - pin = pin_get_from_name(pctldev, name); - if (pin < 0) - goto unlock; - - pin = pin_config_get_for_pin(pctldev, pin, config); - -unlock: - mutex_unlock(&pctldev->mutex); - return pin; -} -EXPORT_SYMBOL(pin_config_get); - -static int pin_config_set_for_pin(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) -{ - const struct pinconf_ops *ops = pctldev->desc->confops; - int ret; - - if (!ops || !ops->pin_config_set) { - dev_err(pctldev->dev, "cannot configure pin, missing " - "config function in driver\n"); - return -EINVAL; - } - - ret = ops->pin_config_set(pctldev, pin, config); - if (ret) { - dev_err(pctldev->dev, - "unable to set pin configuration on pin %d\n", pin); - return ret; - } - - return 0; -} - -/** - * pin_config_set() - set the configuration of a single pin parameter - * @dev_name: name of pin controller device for this pin - * @name: name of the pin to set the config for - * @config: the config in this argument will contain the desired pin state, it - * can be used directly by drivers as a numeral, or it can be dereferenced - * to any struct. - */ -int pin_config_set(const char *dev_name, const char *name, - unsigned long config) -{ - struct pinctrl_dev *pctldev; - int pin, ret; - - pctldev = get_pinctrl_dev_from_devname(dev_name); - if (!pctldev) { - ret = -EINVAL; - return ret; - } - - mutex_lock(&pctldev->mutex); - - pin = pin_get_from_name(pctldev, name); - if (pin < 0) { - ret = pin; - goto unlock; - } - - ret = pin_config_set_for_pin(pctldev, pin, config); - -unlock: - mutex_unlock(&pctldev->mutex); - return ret; -} -EXPORT_SYMBOL(pin_config_set); - int pin_config_group_get(const char *dev_name, const char *pin_group, unsigned long *config) { @@ -185,10 +87,10 @@ int pin_config_group_get(const char *dev_name, const char *pin_group, ops = pctldev->desc->confops; if (!ops || !ops->pin_config_group_get) { - dev_err(pctldev->dev, "cannot get configuration for pin " + dev_dbg(pctldev->dev, "cannot get configuration for pin " "group, missing group config get function in " "driver\n"); - ret = -EINVAL; + ret = -ENOTSUPP; goto unlock; } @@ -204,88 +106,6 @@ unlock: mutex_unlock(&pctldev->mutex); return ret; } -EXPORT_SYMBOL(pin_config_group_get); - -int pin_config_group_set(const char *dev_name, const char *pin_group, - unsigned long config) -{ - struct pinctrl_dev *pctldev; - const struct pinconf_ops *ops; - const struct pinctrl_ops *pctlops; - int selector; - const unsigned *pins; - unsigned num_pins; - int ret; - int i; - - pctldev = get_pinctrl_dev_from_devname(dev_name); - if (!pctldev) { - ret = -EINVAL; - return ret; - } - - mutex_lock(&pctldev->mutex); - - ops = pctldev->desc->confops; - pctlops = pctldev->desc->pctlops; - - if (!ops || (!ops->pin_config_group_set && !ops->pin_config_set)) { - dev_err(pctldev->dev, "cannot configure pin group, missing " - "config function in driver\n"); - ret = -EINVAL; - goto unlock; - } - - selector = pinctrl_get_group_selector(pctldev, pin_group); - if (selector < 0) { - ret = selector; - goto unlock; - } - - ret = pctlops->get_group_pins(pctldev, selector, &pins, &num_pins); - if (ret) { - dev_err(pctldev->dev, "cannot configure pin group, error " - "getting pins\n"); - goto unlock; - } - - /* - * If the pin controller supports handling entire groups we use that - * capability. - */ - if (ops->pin_config_group_set) { - ret = ops->pin_config_group_set(pctldev, selector, config); - /* - * If the pin controller prefer that a certain group be handled - * pin-by-pin as well, it returns -EAGAIN. - */ - if (ret != -EAGAIN) - goto unlock; - } - - /* - * If the controller cannot handle entire groups, we configure each pin - * individually. - */ - if (!ops->pin_config_set) { - ret = 0; - goto unlock; - } - - for (i = 0; i < num_pins; i++) { - ret = ops->pin_config_set(pctldev, pins[i], config); - if (ret < 0) - goto unlock; - } - - ret = 0; - -unlock: - mutex_unlock(&pctldev->mutex); - - return ret; -} -EXPORT_SYMBOL(pin_config_group_set); int pinconf_map_to_setting(struct pinctrl_map const *map, struct pinctrl_setting *setting) @@ -332,7 +152,7 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinconf_ops *ops = pctldev->desc->confops; - int i, ret; + int ret; if (!ops) { dev_err(pctldev->dev, "missing confops\n"); @@ -345,17 +165,15 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) dev_err(pctldev->dev, "missing pin_config_set op\n"); return -EINVAL; } - for (i = 0; i < setting->data.configs.num_configs; i++) { - ret = ops->pin_config_set(pctldev, - setting->data.configs.group_or_pin, - setting->data.configs.configs[i]); - if (ret < 0) { - dev_err(pctldev->dev, - "pin_config_set op failed for pin %d config %08lx\n", - setting->data.configs.group_or_pin, - setting->data.configs.configs[i]); - return ret; - } + ret = ops->pin_config_set(pctldev, + setting->data.configs.group_or_pin, + setting->data.configs.configs, + setting->data.configs.num_configs); + if (ret < 0) { + dev_err(pctldev->dev, + "pin_config_set op failed for pin %d\n", + setting->data.configs.group_or_pin); + return ret; } break; case PIN_MAP_TYPE_CONFIGS_GROUP: @@ -364,17 +182,15 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) "missing pin_config_group_set op\n"); return -EINVAL; } - for (i = 0; i < setting->data.configs.num_configs; i++) { - ret = ops->pin_config_group_set(pctldev, - setting->data.configs.group_or_pin, - setting->data.configs.configs[i]); - if (ret < 0) { - dev_err(pctldev->dev, - "pin_config_group_set op failed for group %d config %08lx\n", - setting->data.configs.group_or_pin, - setting->data.configs.configs[i]); - return ret; - } + ret = ops->pin_config_group_set(pctldev, + setting->data.configs.group_or_pin, + setting->data.configs.configs, + setting->data.configs.num_configs); + if (ret < 0) { + dev_err(pctldev->dev, + "pin_config_group_set op failed for group %d\n", + setting->data.configs.group_or_pin); + return ret; } break; default: @@ -480,12 +296,8 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev, static int pinconf_pins_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; - const struct pinconf_ops *ops = pctldev->desc->confops; unsigned i, pin; - if (!ops || !ops->pin_config_get) - return 0; - seq_puts(s, "Pin config settings per pin\n"); seq_puts(s, "Format: pin (name): configs\n"); @@ -530,13 +342,9 @@ static int pinconf_groups_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; - const struct pinconf_ops *ops = pctldev->desc->confops; unsigned ngroups = pctlops->get_groups_count(pctldev); unsigned selector = 0; - if (!ops || !ops->pin_config_group_get) - return 0; - seq_puts(s, "Pin config settings per pin group\n"); seq_puts(s, "Format: group (name): configs\n"); @@ -602,15 +410,14 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) { struct pinctrl_maps *maps_node; const struct pinctrl_map *map; - struct pinctrl_dev *pctldev = NULL; + const struct pinctrl_map *found = NULL; + struct pinctrl_dev *pctldev; const struct pinconf_ops *confops = NULL; - const struct pinctrl_map_configs *configs; struct dbg_cfg *dbg = &pinconf_dbg_conf; int i, j; - bool found = false; unsigned long config; - mutex_lock(&pctldev->mutex); + mutex_lock(&pinctrl_maps_mutex); /* Parse the pinctrl map and look for the elected pin/state */ for_each_maps(maps_node, i, map) { @@ -624,14 +431,8 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) for (j = 0; j < map->data.configs.num_configs; j++) { if (!strcmp(map->data.configs.group_or_pin, dbg->pin_name)) { - /* - * We found the right pin / state, read the - * config and he pctldev for later use - */ - configs = &map->data.configs; - pctldev = get_pinctrl_dev_from_devname - (map->ctrl_dev_name); - found = true; + /* We found the right pin / state */ + found = map; break; } } @@ -647,7 +448,8 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) goto exit; } - config = *(configs->configs); + pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name); + config = *found->data.configs.configs; seq_printf(s, "Dev %s has config of %s in state %s: 0x%08lX\n", dbg->dev_name, dbg->pin_name, dbg->state_name, config); @@ -659,7 +461,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) confops->pin_config_config_dbg_show(pctldev, s, config); exit: - mutex_unlock(&pctldev->mutex); + mutex_unlock(&pinctrl_maps_mutex); return 0; } @@ -674,17 +476,17 @@ exit: * <devicename> <state> <pinname> are values that should match the pinctrl-maps * <newvalue> reflects the new config and is driver dependant */ -static int pinconf_dbg_config_write(struct file *file, +static ssize_t pinconf_dbg_config_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) { struct pinctrl_maps *maps_node; const struct pinctrl_map *map; - struct pinctrl_dev *pctldev = NULL; + const struct pinctrl_map *found = NULL; + struct pinctrl_dev *pctldev; const struct pinconf_ops *confops = NULL; struct dbg_cfg *dbg = &pinconf_dbg_conf; const struct pinctrl_map_configs *configs; char config[MAX_NAME_LEN+1]; - bool found = false; char buf[128]; char *b = &buf[0]; int buf_size; @@ -692,7 +494,7 @@ static int pinconf_dbg_config_write(struct file *file, int i; /* Get userspace string and assure termination */ - buf_size = min(count, (sizeof(buf)-1)); + buf_size = min(count, sizeof(buf) - 1); if (copy_from_user(buf, user_buf, buf_size)) return -EFAULT; buf[buf_size] = 0; @@ -762,10 +564,7 @@ static int pinconf_dbg_config_write(struct file *file, /* we found the right pin / state, so overwrite config */ if (!strcmp(map->data.configs.group_or_pin, dbg->pin_name)) { - found = true; - pctldev = get_pinctrl_dev_from_devname( - map->ctrl_dev_name); - configs = &map->data.configs; + found = map; break; } } @@ -775,10 +574,12 @@ static int pinconf_dbg_config_write(struct file *file, goto exit; } + pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name); if (pctldev) confops = pctldev->desc->confops; if (confops && confops->pin_config_dbg_parse_modify) { + configs = &found->data.configs; for (i = 0; i < configs->num_configs; i++) { confops->pin_config_dbg_parse_modify(pctldev, config, diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index 92c7267244d..a4a5417e141 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -123,3 +123,9 @@ static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, return; } #endif + +#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF) +int pinconf_generic_parse_dt_config(struct device_node *np, + unsigned long **configs, + unsigned int *nconfigs); +#endif diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index aa17f7580f6..163da9c3ea0 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -24,14 +24,16 @@ #include <linux/bitops.h> #include <linux/mfd/abx500.h> #include <linux/mfd/abx500/ab8500.h> -#include <linux/mfd/abx500/ab8500-gpio.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/machine.h> #include "pinctrl-abx500.h" +#include "core.h" +#include "pinconf.h" /* * The AB9540 and AB8540 GPIO support are extended versions @@ -93,13 +95,15 @@ #define AB8540_GPIOX_VBAT_START 51 #define AB8540_GPIOX_VBAT_END 54 +#define ABX500_GPIO_INPUT 0 +#define ABX500_GPIO_OUTPUT 1 + struct abx500_pinctrl { struct device *dev; struct pinctrl_dev *pctldev; struct abx500_pinctrl_soc_data *soc; struct gpio_chip chip; struct ab8500 *parent; - struct mutex lock; struct abx500_gpio_irq_cluster *irq_cluster; int irq_cluster_size; }; @@ -129,8 +133,8 @@ static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, if (ret < 0) dev_err(pct->dev, - "%s read reg =%x, offset=%x failed\n", - __func__, reg, offset); + "%s read reg =%x, offset=%x failed (%d)\n", + __func__, reg, offset, ret); return ret; } @@ -146,7 +150,8 @@ static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, ret = abx500_mask_and_set_register_interruptible(pct->dev, AB8500_MISC, reg, BIT(pos), val << pos); if (ret < 0) - dev_err(pct->dev, "%s write failed\n", __func__); + dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n", + __func__, reg, offset, ret); return ret; } @@ -160,12 +165,24 @@ static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) { struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); bool bit; + bool is_out; + u8 gpio_offset = offset - 1; int ret; - ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, - offset, &bit); + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, + gpio_offset, &is_out); + if (ret < 0) + goto out; + + if (is_out) + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG, + gpio_offset, &bit); + else + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, + gpio_offset, &bit); +out: if (ret < 0) { - dev_err(pct->dev, "%s failed\n", __func__); + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); return ret; } @@ -179,13 +196,14 @@ static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); if (ret < 0) - dev_err(pct->dev, "%s write failed\n", __func__); + dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret); } -static int abx500_config_pull_updown(struct abx500_pinctrl *pct, - int offset, enum abx500_gpio_pull_updown val) +static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset, + enum abx500_gpio_pull_updown *pull_updown) { u8 pos; + u8 val; int ret; struct pullud *pullud; @@ -204,7 +222,41 @@ static int abx500_config_pull_updown(struct abx500_pinctrl *pct, goto out; } - pos = offset << 1; + ret = abx500_get_register_interruptible(pct->dev, + AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val); + + pos = (offset - pullud->first_pin) << 1; + *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK; + +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + + return ret; +} + +static int abx500_set_pull_updown(struct abx500_pinctrl *pct, + int offset, enum abx500_gpio_pull_updown val) +{ + u8 pos; + int ret; + struct pullud *pullud; + + if (!pct->soc->pullud) { + dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", + __func__); + ret = -EPERM; + goto out; + } + + pullud = pct->soc->pullud; + + if ((offset < pullud->first_pin) + || (offset > pullud->last_pin)) { + ret = -EINVAL; + goto out; + } + pos = (offset - pullud->first_pin) << 1; ret = abx500_mask_and_set_register_interruptible(pct->dev, AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, @@ -217,33 +269,51 @@ out: return ret; } +static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio) +{ + struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + struct pullud *pullud = pct->soc->pullud; + + return (pullud && + gpio >= pullud->first_pin && + gpio <= pullud->last_pin); +} + static int abx500_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) { struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); - struct pullud *pullud = pct->soc->pullud; unsigned gpio; int ret; /* set direction as output */ - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1); + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_DIR1_REG, + offset, + ABX500_GPIO_OUTPUT); if (ret < 0) - return ret; + goto out; /* disable pull down */ - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1); + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_PUD1_REG, + offset, + ABX500_GPIO_PULL_NONE); if (ret < 0) - return ret; + goto out; /* if supported, disable both pull down and pull up */ gpio = offset + 1; - if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) { - ret = abx500_config_pull_updown(pct, + if (abx500_pullud_supported(chip, gpio)) { + ret = abx500_set_pull_updown(pct, gpio, ABX500_GPIO_PULL_NONE); - if (ret < 0) - return ret; + } +out: + if (ret < 0) { + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + return ret; } /* set the output as 1 or 0 */ @@ -253,7 +323,10 @@ static int abx500_gpio_direction_output(struct gpio_chip *chip, static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { /* set the register as input */ - return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0); + return abx500_gpio_set_bits(chip, + AB8500_GPIO_DIR1_REG, + offset, + ABX500_GPIO_INPUT); } static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) @@ -338,15 +411,21 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, if (af.alt_bit1 != UNUSED) { ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, offset, 0); + if (ret < 0) + goto out; + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit1, - !!(af.alta_val && BIT(0))); + !!(af.alta_val & BIT(0))); + if (ret < 0) + goto out; + if (af.alt_bit2 != UNUSED) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, - !!(af.alta_val && BIT(1))); + !!(af.alta_val & BIT(1))); } else ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, offset, 1); @@ -355,22 +434,34 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, case ABX500_ALT_B: ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, offset, 0); + if (ret < 0) + goto out; + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, - af.alt_bit1, !!(af.altb_val && BIT(0))); + af.alt_bit1, !!(af.altb_val & BIT(0))); + if (ret < 0) + goto out; + if (af.alt_bit2 != UNUSED) ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, - !!(af.altb_val && BIT(1))); + !!(af.altb_val & BIT(1))); break; case ABX500_ALT_C: ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, offset, 0); + if (ret < 0) + goto out; + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, - af.alt_bit2, !!(af.altc_val && BIT(0))); + af.alt_bit2, !!(af.altc_val & BIT(0))); + if (ret < 0) + goto out; + ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, - af.alt_bit2, !!(af.altc_val && BIT(1))); + af.alt_bit2, !!(af.altc_val & BIT(1))); break; default: @@ -378,11 +469,14 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, return -EINVAL; } +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); return ret; } -static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, +static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, unsigned gpio) { u8 mode; @@ -393,6 +487,7 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, struct alternate_functions af = pct->soc->alternate_functions[gpio]; /* on ABx5xx, there is no GPIO0, so adjust the offset */ unsigned offset = gpio - 1; + int ret; /* * if gpiosel_bit is set to unused, @@ -402,8 +497,11 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, return ABX500_DEFAULT; /* read GpioSelx register */ - abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), af.gpiosel_bit, &bit_mode); + if (ret < 0) + goto out; + mode = bit_mode; /* sanity check */ @@ -435,14 +533,19 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, * pin use the AlternatFunction register * read alt_bit1 value */ - abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit1, &alt_bit1); + if (ret < 0) + goto out; - if (af.alt_bit2 != UNUSED) + if (af.alt_bit2 != UNUSED) { /* read alt_bit2 value */ - abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, + af.alt_bit2, &alt_bit2); - else + if (ret < 0) + goto out; + } else alt_bit2 = 0; mode = (alt_bit2 << 1) + alt_bit1; @@ -452,6 +555,10 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, return ABX500_ALT_B; else return ABX500_ALT_C; + +out: + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + return ret; } #ifdef CONFIG_DEBUG_FS @@ -463,11 +570,14 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip, unsigned offset, unsigned gpio) { + struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); const char *label = gpiochip_is_requested(chip, offset - 1); u8 gpio_offset = offset - 1; int mode = -1; bool is_out; - bool pull; + bool pd; + enum abx500_gpio_pull_updown pud = 0; + int ret; const char *modes[] = { [ABX500_DEFAULT] = "default", @@ -476,21 +586,48 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s, [ABX500_ALT_C] = "altC", }; - abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out); - abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull); + const char *pull_up_down[] = { + [ABX500_GPIO_PULL_DOWN] = "pull down", + [ABX500_GPIO_PULL_NONE] = "pull none", + [ABX500_GPIO_PULL_NONE + 1] = "pull none", + [ABX500_GPIO_PULL_UP] = "pull up", + }; + + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, + gpio_offset, &is_out); + if (ret < 0) + goto out; + + seq_printf(s, " gpio-%-3d (%-20.20s) %-3s", + gpio, label ?: "(none)", + is_out ? "out" : "in "); + + if (!is_out) { + if (abx500_pullud_supported(chip, offset)) { + ret = abx500_get_pull_updown(pct, offset, &pud); + if (ret < 0) + goto out; + + seq_printf(s, " %-9s", pull_up_down[pud]); + } else { + ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, + gpio_offset, &pd); + if (ret < 0) + goto out; + + seq_printf(s, " %-9s", pull_up_down[pd]); + } + } else + seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); if (pctldev) mode = abx500_get_mode(pctldev, chip, offset); - seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s", - gpio, label ?: "(none)", - is_out ? "out" : "in ", - is_out ? - (chip->get - ? (chip->get(chip, offset) ? "hi" : "lo") - : "? ") - : (pull ? "pull up" : "pull down"), - (mode < 0) ? "unknown" : modes[mode]); + seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); + +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); } static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) @@ -594,6 +731,9 @@ static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); } + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); + return ret; } @@ -642,10 +782,8 @@ static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, ret = abx500_set_mode(pct->pctldev, &pct->chip, offset, p->altfunc); - if (ret < 0) { + if (ret < 0) dev_err(pct->dev, "%s setting altfunc failed\n", __func__); - return ret; - } return ret; } @@ -704,11 +842,193 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, chip->base + offset - 1); } +static void abx500_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + kfree(map); +} + +static int abx500_dt_reserve_map(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, + unsigned reserve) +{ + unsigned old_num = *reserved_maps; + unsigned new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int abx500_dt_add_map_mux(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, const char *group, + const char *function) +{ + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +static int abx500_dt_add_map_configs(struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps, const char *group, + unsigned long *configs, unsigned num_configs) +{ + unsigned long *dup_configs; + + if (*num_maps == *reserved_maps) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) + return -ENOMEM; + + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; + + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev, + const char *pin_name) +{ + int i, pin_number; + struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) + for (i = 0; i < npct->soc->npins; i++) + if (npct->soc->pins[i].number == pin_number) + return npct->soc->pins[i].name; + return NULL; +} + +static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + int ret; + const char *function = NULL; + unsigned long *configs; + unsigned int nconfigs = 0; + bool has_config = 0; + unsigned reserve = 0; + struct property *prop; + const char *group, *gpio_name; + struct device_node *np_config; + + ret = of_property_read_string(np, "ste,function", &function); + if (ret >= 0) + reserve = 1; + + ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); + if (nconfigs) + has_config = 1; + + np_config = of_parse_phandle(np, "ste,config", 0); + if (np_config) { + ret = pinconf_generic_parse_dt_config(np_config, &configs, + &nconfigs); + if (ret) + goto exit; + has_config |= nconfigs; + } + + ret = of_property_count_strings(np, "ste,pins"); + if (ret < 0) + goto exit; + + if (has_config) + reserve++; + + reserve *= ret; + + ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "ste,pins", prop, group) { + if (function) { + ret = abx500_dt_add_map_mux(map, reserved_maps, + num_maps, group, function); + if (ret < 0) + goto exit; + } + if (has_config) { + gpio_name = abx500_find_pin_name(pctldev, group); + + ret = abx500_dt_add_map_configs(map, reserved_maps, + num_maps, gpio_name, configs, 1); + if (ret < 0) + goto exit; + } + + } +exit: + return ret; +} + +static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + unsigned reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = abx500_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + abx500_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + static const struct pinctrl_ops abx500_pinctrl_ops = { .get_groups_count = abx500_get_groups_cnt, .get_group_name = abx500_get_group_name, .get_group_pins = abx500_get_group_pins, .pin_dbg_show = abx500_pin_dbg_show, + .dt_node_to_map = abx500_dt_node_to_map, + .dt_free_map = abx500_dt_free_map, }; static int abx500_pin_config_get(struct pinctrl_dev *pctldev, @@ -720,60 +1040,118 @@ static int abx500_pin_config_get(struct pinctrl_dev *pctldev, static int abx500_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); - struct pullud *pullud = pct->soc->pullud; struct gpio_chip *chip = &pct->chip; unsigned offset; - int ret; - enum pin_config_param param = pinconf_to_config_param(config); - enum pin_config_param argument = pinconf_to_config_argument(config); - - dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", - pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input", - (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") : - (argument ? "pull up" : "pull down")); - - /* on ABx500, there is no GPIO0, so adjust the offset */ - offset = pin - 1; - - switch (param) { - case PIN_CONFIG_BIAS_PULL_DOWN: - /* - * if argument = 1 set the pull down - * else clear the pull down - */ - ret = abx500_gpio_direction_input(chip, offset); - /* - * Some chips only support pull down, while some actually - * support both pull up and pull down. Such chips have - * a "pullud" range specified for the pins that support - * both features. If the pin is not within that range, we - * fall back to the old bit set that only support pull down. - */ - if (pullud && - pin >= pullud->first_pin && - pin <= pullud->last_pin) - ret = abx500_config_pull_updown(pct, - pin, - argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); - else - /* Chip only supports pull down */ - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, - offset, argument ? 0 : 1); - break; - - case PIN_CONFIG_OUTPUT: - ret = abx500_gpio_direction_output(chip, offset, argument); - - break; - - default: - dev_err(chip->dev, "illegal configuration requested\n"); - - return -EINVAL; - } + int ret = -EINVAL; + int i; + enum pin_config_param param; + enum pin_config_param argument; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + argument = pinconf_to_config_argument(configs[i]); + + dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", + pin, configs[i], + (param == PIN_CONFIG_OUTPUT) ? "output " : "input", + (param == PIN_CONFIG_OUTPUT) ? + (argument ? "high" : "low") : + (argument ? "pull up" : "pull down")); + + /* on ABx500, there is no GPIO0, so adjust the offset */ + offset = pin - 1; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * Some chips only support pull down, while some + * actually support both pull up and pull down. Such + * chips have a "pullud" range specified for the pins + * that support both features. If the pin is not + * within that range, we fall back to the old bit set + * that only support pull down. + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + ABX500_GPIO_PULL_NONE); + else + /* Chip only supports pull down */ + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_PUD1_REG, offset, + ABX500_GPIO_PULL_NONE); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * if argument = 1 set the pull down + * else clear the pull down + * Some chips only support pull down, while some + * actually support both pull up and pull down. Such + * chips have a "pullud" range specified for the pins + * that support both features. If the pin is not + * within that range, we fall back to the old bit set + * that only support pull down. + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + argument ? ABX500_GPIO_PULL_DOWN : + ABX500_GPIO_PULL_NONE); + else + /* Chip only supports pull down */ + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_PUD1_REG, + offset, + argument ? ABX500_GPIO_PULL_DOWN : + ABX500_GPIO_PULL_NONE); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * if argument = 1 set the pull up + * else clear the pull up + */ + ret = abx500_gpio_direction_input(chip, offset); + /* + * Some chips only support pull down, while some + * actually support both pull up and pull down. Such + * chips have a "pullud" range specified for the pins + * that support both features. If the pin is not + * within that range, do nothing + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + argument ? ABX500_GPIO_PULL_UP : + ABX500_GPIO_PULL_NONE); + break; + + case PIN_CONFIG_OUTPUT: + ret = abx500_gpio_direction_output(chip, offset, + argument); + break; + + default: + dev_err(chip->dev, "illegal configuration requested\n"); + } + } /* for each config */ +out: + if (ret < 0) + dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); return ret; } @@ -839,35 +1217,18 @@ static const struct of_device_id abx500_gpio_match[] = { static int abx500_gpio_probe(struct platform_device *pdev) { - struct ab8500_platform_data *abx500_pdata = - dev_get_platdata(pdev->dev.parent); - struct abx500_gpio_platform_data *pdata = NULL; struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; struct abx500_pinctrl *pct; - const struct platform_device_id *platid = platform_get_device_id(pdev); unsigned int id = -1; int ret, err; int i; - if (abx500_pdata) - pdata = abx500_pdata->gpio; - if (!pdata) { - if (np) { - const struct of_device_id *match; - - match = of_match_device(abx500_gpio_match, &pdev->dev); - if (!match) - return -ENODEV; - id = (unsigned long)match->data; - } else { - dev_err(&pdev->dev, "gpio dt and platform data missing\n"); - return -ENODEV; - } + if (!np) { + dev_err(&pdev->dev, "gpio dt node missing\n"); + return -ENODEV; } - if (platid) - id = platid->driver_data; - pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), GFP_KERNEL); if (pct == NULL) { @@ -880,10 +1241,14 @@ static int abx500_gpio_probe(struct platform_device *pdev) pct->parent = dev_get_drvdata(pdev->dev.parent); pct->chip = abx500gpio_chip; pct->chip.dev = &pdev->dev; - pct->chip.base = (np) ? -1 : pdata->gpio_base; + pct->chip.base = -1; /* Dynamic allocation */ - /* initialize the lock */ - mutex_init(&pct->lock); + match = of_match_device(abx500_gpio_match, &pdev->dev); + if (!match) { + dev_err(&pdev->dev, "gpio dt not matching\n"); + return -ENODEV; + } + id = (unsigned long)match->data; /* Poke in other ASIC variants here */ switch (id) { @@ -900,15 +1265,12 @@ static int abx500_gpio_probe(struct platform_device *pdev) abx500_pinctrl_ab8505_init(&pct->soc); break; default: - dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", - (int) platid->driver_data); - mutex_destroy(&pct->lock); + dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); return -EINVAL; } if (!pct->soc) { dev_err(&pdev->dev, "Invalid SOC data\n"); - mutex_destroy(&pct->lock); return -EINVAL; } @@ -919,7 +1281,6 @@ static int abx500_gpio_probe(struct platform_device *pdev) ret = gpiochip_add(&pct->chip); if (ret) { dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); - mutex_destroy(&pct->lock); return ret; } dev_info(&pdev->dev, "added gpiochip\n"); @@ -956,7 +1317,6 @@ out_rem_chip: if (err) dev_info(&pdev->dev, "failed to remove gpiochip\n"); - mutex_destroy(&pct->lock); return ret; } @@ -976,19 +1336,9 @@ static int abx500_gpio_remove(struct platform_device *pdev) return ret; } - mutex_destroy(&pct->lock); - return 0; } -static const struct platform_device_id abx500_pinctrl_id[] = { - { "pinctrl-ab8500", PINCTRL_AB8500 }, - { "pinctrl-ab8540", PINCTRL_AB8540 }, - { "pinctrl-ab9540", PINCTRL_AB9540 }, - { "pinctrl-ab8505", PINCTRL_AB8505 }, - { }, -}; - static struct platform_driver abx500_gpio_driver = { .driver = { .name = "abx500-gpio", @@ -997,7 +1347,6 @@ static struct platform_driver abx500_gpio_driver = { }, .probe = abx500_gpio_probe, .remove = abx500_gpio_remove, - .id_table = abx500_pinctrl_id, }; static int __init abx500_gpio_init(void) diff --git a/drivers/pinctrl/pinctrl-abx500.h b/drivers/pinctrl/pinctrl-abx500.h index eeca8f97399..2beef3bfe9c 100644 --- a/drivers/pinctrl/pinctrl-abx500.h +++ b/drivers/pinctrl/pinctrl-abx500.h @@ -1,4 +1,4 @@ -#ifndef PINCTRL_PINCTRL_ABx5O0_H +#ifndef PINCTRL_PINCTRL_ABx500_H #define PINCTRL_PINCTRL_ABx500_H /* Package definitions */ @@ -15,6 +15,18 @@ enum abx500_pin_func { ABX500_ALT_C, }; +enum abx500_gpio_pull_updown { + ABX500_GPIO_PULL_DOWN = 0x0, + ABX500_GPIO_PULL_NONE = 0x1, + ABX500_GPIO_PULL_UP = 0x3, +}; + +enum abx500_gpio_vinsel { + ABX500_GPIO_VINSEL_VBAT = 0x0, + ABX500_GPIO_VINSEL_VIN_1V8 = 0x1, + ABX500_GPIO_VINSEL_VDD_BIF = 0x2, +}; + /** * struct abx500_function - ABx500 pinctrl mux function * @name: The name of the function, exported to pinctrl core. diff --git a/drivers/pinctrl/pinctrl-adi2-bf54x.c b/drivers/pinctrl/pinctrl-adi2-bf54x.c new file mode 100644 index 00000000000..008a29e92e5 --- /dev/null +++ b/drivers/pinctrl/pinctrl-adi2-bf54x.c @@ -0,0 +1,588 @@ +/* + * Pinctrl Driver for ADI GPIO2 controller + * + * Copyright 2007-2013 Analog Devices Inc. + * + * Licensed under the GPLv2 or later + */ + +#include <asm/portmux.h> +#include "pinctrl-adi2.h" + +static const struct pinctrl_pin_desc adi_pads[] = { + PINCTRL_PIN(0, "PA0"), + PINCTRL_PIN(1, "PA1"), + PINCTRL_PIN(2, "PA2"), + PINCTRL_PIN(3, "PG3"), + PINCTRL_PIN(4, "PA4"), + PINCTRL_PIN(5, "PA5"), + PINCTRL_PIN(6, "PA6"), + PINCTRL_PIN(7, "PA7"), + PINCTRL_PIN(8, "PA8"), + PINCTRL_PIN(9, "PA9"), + PINCTRL_PIN(10, "PA10"), + PINCTRL_PIN(11, "PA11"), + PINCTRL_PIN(12, "PA12"), + PINCTRL_PIN(13, "PA13"), + PINCTRL_PIN(14, "PA14"), + PINCTRL_PIN(15, "PA15"), + PINCTRL_PIN(16, "PB0"), + PINCTRL_PIN(17, "PB1"), + PINCTRL_PIN(18, "PB2"), + PINCTRL_PIN(19, "PB3"), + PINCTRL_PIN(20, "PB4"), + PINCTRL_PIN(21, "PB5"), + PINCTRL_PIN(22, "PB6"), + PINCTRL_PIN(23, "PB7"), + PINCTRL_PIN(24, "PB8"), + PINCTRL_PIN(25, "PB9"), + PINCTRL_PIN(26, "PB10"), + PINCTRL_PIN(27, "PB11"), + PINCTRL_PIN(28, "PB12"), + PINCTRL_PIN(29, "PB13"), + PINCTRL_PIN(30, "PB14"), + PINCTRL_PIN(32, "PC0"), + PINCTRL_PIN(33, "PC1"), + PINCTRL_PIN(34, "PC2"), + PINCTRL_PIN(35, "PC3"), + PINCTRL_PIN(36, "PC4"), + PINCTRL_PIN(37, "PC5"), + PINCTRL_PIN(38, "PC6"), + PINCTRL_PIN(39, "PC7"), + PINCTRL_PIN(40, "PC8"), + PINCTRL_PIN(41, "PC9"), + PINCTRL_PIN(42, "PC10"), + PINCTRL_PIN(43, "PC11"), + PINCTRL_PIN(44, "PC12"), + PINCTRL_PIN(45, "PC13"), + PINCTRL_PIN(48, "PD0"), + PINCTRL_PIN(49, "PD1"), + PINCTRL_PIN(50, "PD2"), + PINCTRL_PIN(51, "PD3"), + PINCTRL_PIN(52, "PD4"), + PINCTRL_PIN(53, "PD5"), + PINCTRL_PIN(54, "PD6"), + PINCTRL_PIN(55, "PD7"), + PINCTRL_PIN(56, "PD8"), + PINCTRL_PIN(57, "PD9"), + PINCTRL_PIN(58, "PD10"), + PINCTRL_PIN(59, "PD11"), + PINCTRL_PIN(60, "PD12"), + PINCTRL_PIN(61, "PD13"), + PINCTRL_PIN(62, "PD14"), + PINCTRL_PIN(63, "PD15"), + PINCTRL_PIN(64, "PE0"), + PINCTRL_PIN(65, "PE1"), + PINCTRL_PIN(66, "PE2"), + PINCTRL_PIN(67, "PE3"), + PINCTRL_PIN(68, "PE4"), + PINCTRL_PIN(69, "PE5"), + PINCTRL_PIN(70, "PE6"), + PINCTRL_PIN(71, "PE7"), + PINCTRL_PIN(72, "PE8"), + PINCTRL_PIN(73, "PE9"), + PINCTRL_PIN(74, "PE10"), + PINCTRL_PIN(75, "PE11"), + PINCTRL_PIN(76, "PE12"), + PINCTRL_PIN(77, "PE13"), + PINCTRL_PIN(78, "PE14"), + PINCTRL_PIN(79, "PE15"), + PINCTRL_PIN(80, "PF0"), + PINCTRL_PIN(81, "PF1"), + PINCTRL_PIN(82, "PF2"), + PINCTRL_PIN(83, "PF3"), + PINCTRL_PIN(84, "PF4"), + PINCTRL_PIN(85, "PF5"), + PINCTRL_PIN(86, "PF6"), + PINCTRL_PIN(87, "PF7"), + PINCTRL_PIN(88, "PF8"), + PINCTRL_PIN(89, "PF9"), + PINCTRL_PIN(90, "PF10"), + PINCTRL_PIN(91, "PF11"), + PINCTRL_PIN(92, "PF12"), + PINCTRL_PIN(93, "PF13"), + PINCTRL_PIN(94, "PF14"), + PINCTRL_PIN(95, "PF15"), + PINCTRL_PIN(96, "PG0"), + PINCTRL_PIN(97, "PG1"), + PINCTRL_PIN(98, "PG2"), + PINCTRL_PIN(99, "PG3"), + PINCTRL_PIN(100, "PG4"), + PINCTRL_PIN(101, "PG5"), + PINCTRL_PIN(102, "PG6"), + PINCTRL_PIN(103, "PG7"), + PINCTRL_PIN(104, "PG8"), + PINCTRL_PIN(105, "PG9"), + PINCTRL_PIN(106, "PG10"), + PINCTRL_PIN(107, "PG11"), + PINCTRL_PIN(108, "PG12"), + PINCTRL_PIN(109, "PG13"), + PINCTRL_PIN(110, "PG14"), + PINCTRL_PIN(111, "PG15"), + PINCTRL_PIN(112, "PH0"), + PINCTRL_PIN(113, "PH1"), + PINCTRL_PIN(114, "PH2"), + PINCTRL_PIN(115, "PH3"), + PINCTRL_PIN(116, "PH4"), + PINCTRL_PIN(117, "PH5"), + PINCTRL_PIN(118, "PH6"), + PINCTRL_PIN(119, "PH7"), + PINCTRL_PIN(120, "PH8"), + PINCTRL_PIN(121, "PH9"), + PINCTRL_PIN(122, "PH10"), + PINCTRL_PIN(123, "PH11"), + PINCTRL_PIN(124, "PH12"), + PINCTRL_PIN(125, "PH13"), + PINCTRL_PIN(128, "PI0"), + PINCTRL_PIN(129, "PI1"), + PINCTRL_PIN(130, "PI2"), + PINCTRL_PIN(131, "PI3"), + PINCTRL_PIN(132, "PI4"), + PINCTRL_PIN(133, "PI5"), + PINCTRL_PIN(134, "PI6"), + PINCTRL_PIN(135, "PI7"), + PINCTRL_PIN(136, "PI8"), + PINCTRL_PIN(137, "PI9"), + PINCTRL_PIN(138, "PI10"), + PINCTRL_PIN(139, "PI11"), + PINCTRL_PIN(140, "PI12"), + PINCTRL_PIN(141, "PI13"), + PINCTRL_PIN(142, "PI14"), + PINCTRL_PIN(143, "PI15"), + PINCTRL_PIN(144, "PJ0"), + PINCTRL_PIN(145, "PJ1"), + PINCTRL_PIN(146, "PJ2"), + PINCTRL_PIN(147, "PJ3"), + PINCTRL_PIN(148, "PJ4"), + PINCTRL_PIN(149, "PJ5"), + PINCTRL_PIN(150, "PJ6"), + PINCTRL_PIN(151, "PJ7"), + PINCTRL_PIN(152, "PJ8"), + PINCTRL_PIN(153, "PJ9"), + PINCTRL_PIN(154, "PJ10"), + PINCTRL_PIN(155, "PJ11"), + PINCTRL_PIN(156, "PJ12"), + PINCTRL_PIN(157, "PJ13"), +}; + +static const unsigned uart0_pins[] = { + GPIO_PE7, GPIO_PE8, +}; + +static const unsigned uart1_pins[] = { + GPIO_PH0, GPIO_PH1, +}; + +static const unsigned uart1_ctsrts_pins[] = { + GPIO_PE9, GPIO_PE10, +}; + +static const unsigned uart2_pins[] = { + GPIO_PB4, GPIO_PB5, +}; + +static const unsigned uart3_pins[] = { + GPIO_PB6, GPIO_PB7, +}; + +static const unsigned uart3_ctsrts_pins[] = { + GPIO_PB2, GPIO_PB3, +}; + +static const unsigned rsi0_pins[] = { + GPIO_PC8, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, GPIO_PC13, +}; + +static const unsigned spi0_pins[] = { + GPIO_PE0, GPIO_PE1, GPIO_PE2, +}; + +static const unsigned spi1_pins[] = { + GPIO_PG8, GPIO_PG9, GPIO_PG10, +}; + +static const unsigned twi0_pins[] = { + GPIO_PE14, GPIO_PE15, +}; + +static const unsigned twi1_pins[] = { + GPIO_PB0, GPIO_PB1, +}; + +static const unsigned rotary_pins[] = { + GPIO_PH4, GPIO_PH3, GPIO_PH5, +}; + +static const unsigned can0_pins[] = { + GPIO_PG13, GPIO_PG12, +}; + +static const unsigned can1_pins[] = { + GPIO_PG14, GPIO_PG15, +}; + +static const unsigned smc0_pins[] = { + GPIO_PH8, GPIO_PH9, GPIO_PH10, GPIO_PH11, GPIO_PH12, GPIO_PH13, + GPIO_PI0, GPIO_PI1, GPIO_PI2, GPIO_PI3, GPIO_PI4, GPIO_PI5, GPIO_PI6, + GPIO_PI7, GPIO_PI8, GPIO_PI9, GPIO_PI10, GPIO_PI11, + GPIO_PI12, GPIO_PI13, GPIO_PI14, GPIO_PI15, +}; + +static const unsigned sport0_pins[] = { + GPIO_PC0, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC6, GPIO_PC7, +}; + +static const unsigned sport1_pins[] = { + GPIO_PD0, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD6, GPIO_PD7, +}; + +static const unsigned sport2_pins[] = { + GPIO_PA0, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA6, GPIO_PA7, +}; + +static const unsigned sport3_pins[] = { + GPIO_PA8, GPIO_PA10, GPIO_PA11, GPIO_PA12, GPIO_PA14, GPIO_PA15, +}; + +static const unsigned ppi0_8b_pins[] = { + GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, + GPIO_PF7, GPIO_PF13, GPIO_PG0, GPIO_PG1, GPIO_PG2, +}; + +static const unsigned ppi0_16b_pins[] = { + GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, + GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, + GPIO_PF13, GPIO_PF14, GPIO_PF15, + GPIO_PG0, GPIO_PG1, GPIO_PG2, +}; + +static const unsigned ppi0_24b_pins[] = { + GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, + GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, + GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PD0, GPIO_PD1, GPIO_PD2, + GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PG3, GPIO_PG4, + GPIO_PG0, GPIO_PG1, GPIO_PG2, +}; + +static const unsigned ppi1_8b_pins[] = { + GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6, + GPIO_PD7, GPIO_PE11, GPIO_PE12, GPIO_PE13, +}; + +static const unsigned ppi1_16b_pins[] = { + GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6, + GPIO_PD7, GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12, + GPIO_PD13, GPIO_PD14, GPIO_PD15, + GPIO_PE11, GPIO_PE12, GPIO_PE13, +}; + +static const unsigned ppi2_8b_pins[] = { + GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12, + GPIO_PD13, GPIO_PD14, GPIO_PD15, + GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3, +}; + +static const unsigned atapi_pins[] = { + GPIO_PH2, GPIO_PJ3, GPIO_PJ4, GPIO_PJ5, GPIO_PJ6, + GPIO_PJ7, GPIO_PJ8, GPIO_PJ9, GPIO_PJ10, +}; + +static const unsigned atapi_alter_pins[] = { + GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, + GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, + GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PG2, GPIO_PG3, GPIO_PG4, +}; + +static const unsigned nfc0_pins[] = { + GPIO_PJ1, GPIO_PJ2, +}; + +static const unsigned keys_4x4_pins[] = { + GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, + GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15, +}; + +static const unsigned keys_8x8_pins[] = { + GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, + GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15, + GPIO_PE0, GPIO_PE1, GPIO_PE2, GPIO_PE3, + GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, +}; + +static const unsigned short uart0_mux[] = { + P_UART0_TX, P_UART0_RX, + 0 +}; + +static const unsigned short uart1_mux[] = { + P_UART1_TX, P_UART1_RX, + 0 +}; + +static const unsigned short uart1_ctsrts_mux[] = { + P_UART1_RTS, P_UART1_CTS, + 0 +}; + +static const unsigned short uart2_mux[] = { + P_UART2_TX, P_UART2_RX, + 0 +}; + +static const unsigned short uart3_mux[] = { + P_UART3_TX, P_UART3_RX, + 0 +}; + +static const unsigned short uart3_ctsrts_mux[] = { + P_UART3_RTS, P_UART3_CTS, + 0 +}; + +static const unsigned short rsi0_mux[] = { + P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, + 0 +}; + +static const unsigned short spi0_mux[] = { + P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0 +}; + +static const unsigned short spi1_mux[] = { + P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0 +}; + +static const unsigned short twi0_mux[] = { + P_TWI0_SCL, P_TWI0_SDA, 0 +}; + +static const unsigned short twi1_mux[] = { + P_TWI1_SCL, P_TWI1_SDA, 0 +}; + +static const unsigned short rotary_mux[] = { + P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0 +}; + +static const unsigned short sport0_mux[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 +}; + +static const unsigned short sport1_mux[] = { + P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 +}; + +static const unsigned short sport2_mux[] = { + P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, + P_SPORT2_DRPRI, P_SPORT2_RSCLK, 0 +}; + +static const unsigned short sport3_mux[] = { + P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, + P_SPORT3_DRPRI, P_SPORT3_RSCLK, 0 +}; + +static const unsigned short can0_mux[] = { + P_CAN0_RX, P_CAN0_TX, 0 +}; + +static const unsigned short can1_mux[] = { + P_CAN1_RX, P_CAN1_TX, 0 +}; + +static const unsigned short smc0_mux[] = { + P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, + P_A22, P_A23, P_A24, P_A25, P_NOR_CLK, 0, +}; + +static const unsigned short ppi0_8b_mux[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, + P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, + 0, +}; + +static const unsigned short ppi0_16b_mux[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, + P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, + P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, + P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, + 0, +}; + +static const unsigned short ppi0_24b_mux[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, + P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, + P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, + P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, + P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19, + P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, + 0, +}; + +static const unsigned short ppi1_8b_mux[] = { + P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, + P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, + P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, + 0, +}; + +static const unsigned short ppi1_16b_mux[] = { + P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, + P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, + P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11, + P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15, + P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, + 0, +}; + +static const unsigned short ppi2_8b_mux[] = { + P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3, + P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7, + P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2, + 0, +}; + +static const unsigned short atapi_mux[] = { + P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, P_ATAPI_CS1, + P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, P_ATAPI_IORDY, +}; + +static const unsigned short atapi_alter_mux[] = { + P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, P_ATAPI_D3A, P_ATAPI_D4A, + P_ATAPI_D5A, P_ATAPI_D6A, P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, + P_ATAPI_D10A, P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A, + P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, + 0 +}; + +static const unsigned short nfc0_mux[] = { + P_NAND_CE, P_NAND_RB, + 0 +}; + +static const unsigned short keys_4x4_mux[] = { + P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0, + P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0, + 0 +}; + +static const unsigned short keys_8x8_mux[] = { + P_KEY_ROW7, P_KEY_ROW6, P_KEY_ROW5, P_KEY_ROW4, + P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0, + P_KEY_COL7, P_KEY_COL6, P_KEY_COL5, P_KEY_COL4, + P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0, + 0 +}; + +static const struct adi_pin_group adi_pin_groups[] = { + ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux), + ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux), + ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux), + ADI_PIN_GROUP("uart2grp", uart2_pins, uart2_mux), + ADI_PIN_GROUP("uart3grp", uart3_pins, uart3_mux), + ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins, uart3_ctsrts_mux), + ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux), + ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux), + ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux), + ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux), + ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux), + ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux), + ADI_PIN_GROUP("can0grp", can0_pins, can0_mux), + ADI_PIN_GROUP("can1grp", can1_pins, can1_mux), + ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux), + ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux), + ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux), + ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux), + ADI_PIN_GROUP("sport3grp", sport3_pins, sport3_mux), + ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux), + ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux), + ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux), + ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux), + ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux), + ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux), + ADI_PIN_GROUP("atapigrp", atapi_pins, atapi_mux), + ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins, atapi_alter_mux), + ADI_PIN_GROUP("nfc0grp", nfc0_pins, nfc0_mux), + ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins, keys_4x4_mux), + ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins, keys_8x8_mux), +}; + +static const char * const uart0grp[] = { "uart0grp" }; +static const char * const uart1grp[] = { "uart1grp" }; +static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" }; +static const char * const uart2grp[] = { "uart2grp" }; +static const char * const uart3grp[] = { "uart3grp" }; +static const char * const uart3ctsrtsgrp[] = { "uart3ctsrtsgrp" }; +static const char * const rsi0grp[] = { "rsi0grp" }; +static const char * const spi0grp[] = { "spi0grp" }; +static const char * const spi1grp[] = { "spi1grp" }; +static const char * const twi0grp[] = { "twi0grp" }; +static const char * const twi1grp[] = { "twi1grp" }; +static const char * const rotarygrp[] = { "rotarygrp" }; +static const char * const can0grp[] = { "can0grp" }; +static const char * const can1grp[] = { "can1grp" }; +static const char * const smc0grp[] = { "smc0grp" }; +static const char * const sport0grp[] = { "sport0grp" }; +static const char * const sport1grp[] = { "sport1grp" }; +static const char * const sport2grp[] = { "sport2grp" }; +static const char * const sport3grp[] = { "sport3grp" }; +static const char * const ppi0grp[] = { "ppi0_8bgrp", + "ppi0_16bgrp", + "ppi0_24bgrp" }; +static const char * const ppi1grp[] = { "ppi1_8bgrp", + "ppi1_16bgrp" }; +static const char * const ppi2grp[] = { "ppi2_8bgrp" }; +static const char * const atapigrp[] = { "atapigrp" }; +static const char * const atapialtergrp[] = { "atapialtergrp" }; +static const char * const nfc0grp[] = { "nfc0grp" }; +static const char * const keysgrp[] = { "keys_4x4grp", + "keys_8x8grp" }; + +static const struct adi_pmx_func adi_pmx_functions[] = { + ADI_PMX_FUNCTION("uart0", uart0grp), + ADI_PMX_FUNCTION("uart1", uart1grp), + ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp), + ADI_PMX_FUNCTION("uart2", uart2grp), + ADI_PMX_FUNCTION("uart3", uart3grp), + ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp), + ADI_PMX_FUNCTION("rsi0", rsi0grp), + ADI_PMX_FUNCTION("spi0", spi0grp), + ADI_PMX_FUNCTION("spi1", spi1grp), + ADI_PMX_FUNCTION("twi0", twi0grp), + ADI_PMX_FUNCTION("twi1", twi1grp), + ADI_PMX_FUNCTION("rotary", rotarygrp), + ADI_PMX_FUNCTION("can0", can0grp), + ADI_PMX_FUNCTION("can1", can1grp), + ADI_PMX_FUNCTION("smc0", smc0grp), + ADI_PMX_FUNCTION("sport0", sport0grp), + ADI_PMX_FUNCTION("sport1", sport1grp), + ADI_PMX_FUNCTION("sport2", sport2grp), + ADI_PMX_FUNCTION("sport3", sport3grp), + ADI_PMX_FUNCTION("ppi0", ppi0grp), + ADI_PMX_FUNCTION("ppi1", ppi1grp), + ADI_PMX_FUNCTION("ppi2", ppi2grp), + ADI_PMX_FUNCTION("atapi", atapigrp), + ADI_PMX_FUNCTION("atapi_alter", atapialtergrp), + ADI_PMX_FUNCTION("nfc0", nfc0grp), + ADI_PMX_FUNCTION("keys", keysgrp), +}; + +static const struct adi_pinctrl_soc_data adi_bf54x_soc = { + .functions = adi_pmx_functions, + .nfunctions = ARRAY_SIZE(adi_pmx_functions), + .groups = adi_pin_groups, + .ngroups = ARRAY_SIZE(adi_pin_groups), + .pins = adi_pads, + .npins = ARRAY_SIZE(adi_pads), +}; + +void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc) +{ + *soc = &adi_bf54x_soc; +} diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c new file mode 100644 index 00000000000..4cb59fe9be7 --- /dev/null +++ b/drivers/pinctrl/pinctrl-adi2-bf60x.c @@ -0,0 +1,517 @@ +/* + * Pinctrl Driver for ADI GPIO2 controller + * + * Copyright 2007-2013 Analog Devices Inc. + * + * Licensed under the GPLv2 or later + */ + +#include <asm/portmux.h> +#include "pinctrl-adi2.h" + +static const struct pinctrl_pin_desc adi_pads[] = { + PINCTRL_PIN(0, "PA0"), + PINCTRL_PIN(1, "PA1"), + PINCTRL_PIN(2, "PA2"), + PINCTRL_PIN(3, "PG3"), + PINCTRL_PIN(4, "PA4"), + PINCTRL_PIN(5, "PA5"), + PINCTRL_PIN(6, "PA6"), + PINCTRL_PIN(7, "PA7"), + PINCTRL_PIN(8, "PA8"), + PINCTRL_PIN(9, "PA9"), + PINCTRL_PIN(10, "PA10"), + PINCTRL_PIN(11, "PA11"), + PINCTRL_PIN(12, "PA12"), + PINCTRL_PIN(13, "PA13"), + PINCTRL_PIN(14, "PA14"), + PINCTRL_PIN(15, "PA15"), + PINCTRL_PIN(16, "PB0"), + PINCTRL_PIN(17, "PB1"), + PINCTRL_PIN(18, "PB2"), + PINCTRL_PIN(19, "PB3"), + PINCTRL_PIN(20, "PB4"), + PINCTRL_PIN(21, "PB5"), + PINCTRL_PIN(22, "PB6"), + PINCTRL_PIN(23, "PB7"), + PINCTRL_PIN(24, "PB8"), + PINCTRL_PIN(25, "PB9"), + PINCTRL_PIN(26, "PB10"), + PINCTRL_PIN(27, "PB11"), + PINCTRL_PIN(28, "PB12"), + PINCTRL_PIN(29, "PB13"), + PINCTRL_PIN(30, "PB14"), + PINCTRL_PIN(31, "PB15"), + PINCTRL_PIN(32, "PC0"), + PINCTRL_PIN(33, "PC1"), + PINCTRL_PIN(34, "PC2"), + PINCTRL_PIN(35, "PC3"), + PINCTRL_PIN(36, "PC4"), + PINCTRL_PIN(37, "PC5"), + PINCTRL_PIN(38, "PC6"), + PINCTRL_PIN(39, "PC7"), + PINCTRL_PIN(40, "PC8"), + PINCTRL_PIN(41, "PC9"), + PINCTRL_PIN(42, "PC10"), + PINCTRL_PIN(43, "PC11"), + PINCTRL_PIN(44, "PC12"), + PINCTRL_PIN(45, "PC13"), + PINCTRL_PIN(46, "PC14"), + PINCTRL_PIN(47, "PC15"), + PINCTRL_PIN(48, "PD0"), + PINCTRL_PIN(49, "PD1"), + PINCTRL_PIN(50, "PD2"), + PINCTRL_PIN(51, "PD3"), + PINCTRL_PIN(52, "PD4"), + PINCTRL_PIN(53, "PD5"), + PINCTRL_PIN(54, "PD6"), + PINCTRL_PIN(55, "PD7"), + PINCTRL_PIN(56, "PD8"), + PINCTRL_PIN(57, "PD9"), + PINCTRL_PIN(58, "PD10"), + PINCTRL_PIN(59, "PD11"), + PINCTRL_PIN(60, "PD12"), + PINCTRL_PIN(61, "PD13"), + PINCTRL_PIN(62, "PD14"), + PINCTRL_PIN(63, "PD15"), + PINCTRL_PIN(64, "PE0"), + PINCTRL_PIN(65, "PE1"), + PINCTRL_PIN(66, "PE2"), + PINCTRL_PIN(67, "PE3"), + PINCTRL_PIN(68, "PE4"), + PINCTRL_PIN(69, "PE5"), + PINCTRL_PIN(70, "PE6"), + PINCTRL_PIN(71, "PE7"), + PINCTRL_PIN(72, "PE8"), + PINCTRL_PIN(73, "PE9"), + PINCTRL_PIN(74, "PE10"), + PINCTRL_PIN(75, "PE11"), + PINCTRL_PIN(76, "PE12"), + PINCTRL_PIN(77, "PE13"), + PINCTRL_PIN(78, "PE14"), + PINCTRL_PIN(79, "PE15"), + PINCTRL_PIN(80, "PF0"), + PINCTRL_PIN(81, "PF1"), + PINCTRL_PIN(82, "PF2"), + PINCTRL_PIN(83, "PF3"), + PINCTRL_PIN(84, "PF4"), + PINCTRL_PIN(85, "PF5"), + PINCTRL_PIN(86, "PF6"), + PINCTRL_PIN(87, "PF7"), + PINCTRL_PIN(88, "PF8"), + PINCTRL_PIN(89, "PF9"), + PINCTRL_PIN(90, "PF10"), + PINCTRL_PIN(91, "PF11"), + PINCTRL_PIN(92, "PF12"), + PINCTRL_PIN(93, "PF13"), + PINCTRL_PIN(94, "PF14"), + PINCTRL_PIN(95, "PF15"), + PINCTRL_PIN(96, "PG0"), + PINCTRL_PIN(97, "PG1"), + PINCTRL_PIN(98, "PG2"), + PINCTRL_PIN(99, "PG3"), + PINCTRL_PIN(100, "PG4"), + PINCTRL_PIN(101, "PG5"), + PINCTRL_PIN(102, "PG6"), + PINCTRL_PIN(103, "PG7"), + PINCTRL_PIN(104, "PG8"), + PINCTRL_PIN(105, "PG9"), + PINCTRL_PIN(106, "PG10"), + PINCTRL_PIN(107, "PG11"), + PINCTRL_PIN(108, "PG12"), + PINCTRL_PIN(109, "PG13"), + PINCTRL_PIN(110, "PG14"), + PINCTRL_PIN(111, "PG15"), +}; + +static const unsigned uart0_pins[] = { + GPIO_PD7, GPIO_PD8, +}; + +static const unsigned uart0_ctsrts_pins[] = { + GPIO_PD9, GPIO_PD10, +}; + +static const unsigned uart1_pins[] = { + GPIO_PG15, GPIO_PG14, +}; + +static const unsigned uart1_ctsrts_pins[] = { + GPIO_PG10, GPIO_PG13, +}; + +static const unsigned rsi0_pins[] = { + GPIO_PG3, GPIO_PG2, GPIO_PG0, GPIO_PE15, GPIO_PG5, GPIO_PG6, +}; + +static const unsigned eth0_pins[] = { + GPIO_PC6, GPIO_PC7, GPIO_PC2, GPIO_PC0, GPIO_PC3, GPIO_PC1, + GPIO_PB13, GPIO_PD6, GPIO_PC5, GPIO_PC4, GPIO_PB14, GPIO_PB15, +}; + +static const unsigned eth1_pins[] = { + GPIO_PE10, GPIO_PE11, GPIO_PG3, GPIO_PG0, GPIO_PG2, GPIO_PE15, + GPIO_PG5, GPIO_PE12, GPIO_PE13, GPIO_PE14, GPIO_PG6, GPIO_PC9, +}; + +static const unsigned spi0_pins[] = { + GPIO_PD4, GPIO_PD2, GPIO_PD3, +}; + +static const unsigned spi1_pins[] = { + GPIO_PD5, GPIO_PD14, GPIO_PD13, +}; + +static const unsigned twi0_pins[] = { +}; + +static const unsigned twi1_pins[] = { +}; + +static const unsigned rotary_pins[] = { + GPIO_PG7, GPIO_PG11, GPIO_PG12, +}; + +static const unsigned can0_pins[] = { + GPIO_PG1, GPIO_PG4, +}; + +static const unsigned smc0_pins[] = { + GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6, + GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PB2, GPIO_PA10, GPIO_PA11, + GPIO_PB3, GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB6, + GPIO_PB7, GPIO_PB8, GPIO_PB10, GPIO_PB11, GPIO_PB0, +}; + +static const unsigned sport0_pins[] = { + GPIO_PB5, GPIO_PB4, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB11, +}; + +static const unsigned sport1_pins[] = { + GPIO_PE2, GPIO_PE5, GPIO_PD15, GPIO_PE4, GPIO_PE3, GPIO_PE1, +}; + +static const unsigned sport2_pins[] = { + GPIO_PG4, GPIO_PG1, GPIO_PG9, GPIO_PG10, GPIO_PG7, GPIO_PB12, +}; + +static const unsigned ppi0_8b_pins[] = { + GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, + GPIO_PF7, GPIO_PF13, GPIO_PF14, GPIO_PF15, + GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9, +}; + +static const unsigned ppi0_16b_pins[] = { + GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, + GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, + GPIO_PF13, GPIO_PF14, GPIO_PF15, + GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9, +}; + +static const unsigned ppi0_24b_pins[] = { + GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, + GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, + GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PE0, GPIO_PE1, GPIO_PE2, + GPIO_PE3, GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, GPIO_PE8, + GPIO_PE9, GPIO_PD12, GPIO_PD15, +}; + +static const unsigned ppi1_8b_pins[] = { + GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6, + GPIO_PC7, GPIO_PC8, GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6, +}; + +static const unsigned ppi1_16b_pins[] = { + GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6, + GPIO_PC7, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, + GPIO_PC13, GPIO_PC14, GPIO_PC15, + GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6, +}; + +static const unsigned ppi2_8b_pins[] = { + GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6, + GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3, +}; + +static const unsigned ppi2_16b_pins[] = { + GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6, + GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, GPIO_PA12, + GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB0, GPIO_PB1, GPIO_PB2, +}; + +static const unsigned lp0_pins[] = { + GPIO_PB0, GPIO_PB1, GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, + GPIO_PA4, GPIO_PA5, GPIO_PA6, GPIO_PA7, +}; + +static const unsigned lp1_pins[] = { + GPIO_PB3, GPIO_PB2, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, + GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, +}; + +static const unsigned lp2_pins[] = { + GPIO_PE6, GPIO_PE7, GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, + GPIO_PF4, GPIO_PF5, GPIO_PF6, GPIO_PF7, +}; + +static const unsigned lp3_pins[] = { + GPIO_PE9, GPIO_PE8, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, + GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15, +}; + +static const unsigned short uart0_mux[] = { + P_UART0_TX, P_UART0_RX, + 0 +}; + +static const unsigned short uart0_ctsrts_mux[] = { + P_UART0_RTS, P_UART0_CTS, + 0 +}; + +static const unsigned short uart1_mux[] = { + P_UART1_TX, P_UART1_RX, + 0 +}; + +static const unsigned short uart1_ctsrts_mux[] = { + P_UART1_RTS, P_UART1_CTS, + 0 +}; + +static const unsigned short rsi0_mux[] = { + P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, + P_RSI_CMD, P_RSI_CLK, 0 +}; + +static const unsigned short eth0_mux[] = P_RMII0; +static const unsigned short eth1_mux[] = P_RMII1; + +static const unsigned short spi0_mux[] = { + P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0 +}; + +static const unsigned short spi1_mux[] = { + P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0 +}; + +static const unsigned short twi0_mux[] = { + P_TWI0_SCL, P_TWI0_SDA, 0 +}; + +static const unsigned short twi1_mux[] = { + P_TWI1_SCL, P_TWI1_SDA, 0 +}; + +static const unsigned short rotary_mux[] = { + P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0 +}; + +static const unsigned short sport0_mux[] = { + P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK, + P_SPORT0_BFS, P_SPORT0_BD0, 0, +}; + +static const unsigned short sport1_mux[] = { + P_SPORT1_ACLK, P_SPORT1_AFS, P_SPORT1_AD0, P_SPORT1_BCLK, + P_SPORT1_BFS, P_SPORT1_BD0, 0, +}; + +static const unsigned short sport2_mux[] = { + P_SPORT2_ACLK, P_SPORT2_AFS, P_SPORT2_AD0, P_SPORT2_BCLK, + P_SPORT2_BFS, P_SPORT2_BD0, 0, +}; + +static const unsigned short can0_mux[] = { + P_CAN0_RX, P_CAN0_TX, 0 +}; + +static const unsigned short smc0_mux[] = { + P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, + P_A22, P_A23, P_A24, P_A25, P_NORCK, 0, +}; + +static const unsigned short ppi0_8b_mux[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, + P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, + 0, +}; + +static const unsigned short ppi0_16b_mux[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, + P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, + P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, + P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, + 0, +}; + +static const unsigned short ppi0_24b_mux[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, + P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, + P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, + P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, + P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19, + P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, + 0, +}; + +static const unsigned short ppi1_8b_mux[] = { + P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, + P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, + P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, + 0, +}; + +static const unsigned short ppi1_16b_mux[] = { + P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, + P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, + P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11, + P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15, + P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, + 0, +}; + +static const unsigned short ppi2_8b_mux[] = { + P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3, + P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7, + P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2, + 0, +}; + +static const unsigned short ppi2_16b_mux[] = { + P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3, + P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7, + P_PPI2_D8, P_PPI2_D9, P_PPI2_D10, P_PPI2_D11, + P_PPI2_D12, P_PPI2_D13, P_PPI2_D14, P_PPI2_D15, + P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2, + 0, +}; + +static const unsigned short lp0_mux[] = { + P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2, + P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7, + 0 +}; + +static const unsigned short lp1_mux[] = { + P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2, + P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7, + 0 +}; + +static const unsigned short lp2_mux[] = { + P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2, + P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7, + 0 +}; + +static const unsigned short lp3_mux[] = { + P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2, + P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7, + 0 +}; + +static const struct adi_pin_group adi_pin_groups[] = { + ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux), + ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins, uart0_ctsrts_mux), + ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux), + ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux), + ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux), + ADI_PIN_GROUP("eth0grp", eth0_pins, eth0_mux), + ADI_PIN_GROUP("eth1grp", eth1_pins, eth1_mux), + ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux), + ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux), + ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux), + ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux), + ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux), + ADI_PIN_GROUP("can0grp", can0_pins, can0_mux), + ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux), + ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux), + ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux), + ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux), + ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux), + ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux), + ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux), + ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux), + ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux), + ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux), + ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins, ppi2_16b_mux), + ADI_PIN_GROUP("lp0grp", lp0_pins, lp0_mux), + ADI_PIN_GROUP("lp1grp", lp1_pins, lp1_mux), + ADI_PIN_GROUP("lp2grp", lp2_pins, lp2_mux), + ADI_PIN_GROUP("lp3grp", lp3_pins, lp3_mux), +}; + +static const char * const uart0grp[] = { "uart0grp" }; +static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" }; +static const char * const uart1grp[] = { "uart1grp" }; +static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" }; +static const char * const rsi0grp[] = { "rsi0grp" }; +static const char * const eth0grp[] = { "eth0grp" }; +static const char * const eth1grp[] = { "eth1grp" }; +static const char * const spi0grp[] = { "spi0grp" }; +static const char * const spi1grp[] = { "spi1grp" }; +static const char * const twi0grp[] = { "twi0grp" }; +static const char * const twi1grp[] = { "twi1grp" }; +static const char * const rotarygrp[] = { "rotarygrp" }; +static const char * const can0grp[] = { "can0grp" }; +static const char * const smc0grp[] = { "smc0grp" }; +static const char * const sport0grp[] = { "sport0grp" }; +static const char * const sport1grp[] = { "sport1grp" }; +static const char * const sport2grp[] = { "sport2grp" }; +static const char * const ppi0grp[] = { "ppi0_8bgrp", + "ppi0_16bgrp", + "ppi0_24bgrp" }; +static const char * const ppi1grp[] = { "ppi1_8bgrp", + "ppi1_16bgrp" }; +static const char * const ppi2grp[] = { "ppi2_8bgrp", + "ppi2_16bgrp" }; +static const char * const lp0grp[] = { "lp0grp" }; +static const char * const lp1grp[] = { "lp1grp" }; +static const char * const lp2grp[] = { "lp2grp" }; +static const char * const lp3grp[] = { "lp3grp" }; + +static const struct adi_pmx_func adi_pmx_functions[] = { + ADI_PMX_FUNCTION("uart0", uart0grp), + ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp), + ADI_PMX_FUNCTION("uart1", uart1grp), + ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp), + ADI_PMX_FUNCTION("rsi0", rsi0grp), + ADI_PMX_FUNCTION("eth0", eth0grp), + ADI_PMX_FUNCTION("eth1", eth1grp), + ADI_PMX_FUNCTION("spi0", spi0grp), + ADI_PMX_FUNCTION("spi1", spi1grp), + ADI_PMX_FUNCTION("twi0", twi0grp), + ADI_PMX_FUNCTION("twi1", twi1grp), + ADI_PMX_FUNCTION("rotary", rotarygrp), + ADI_PMX_FUNCTION("can0", can0grp), + ADI_PMX_FUNCTION("smc0", smc0grp), + ADI_PMX_FUNCTION("sport0", sport0grp), + ADI_PMX_FUNCTION("sport1", sport1grp), + ADI_PMX_FUNCTION("sport2", sport2grp), + ADI_PMX_FUNCTION("ppi0", ppi0grp), + ADI_PMX_FUNCTION("ppi1", ppi1grp), + ADI_PMX_FUNCTION("ppi2", ppi2grp), + ADI_PMX_FUNCTION("lp0", lp0grp), + ADI_PMX_FUNCTION("lp1", lp1grp), + ADI_PMX_FUNCTION("lp2", lp2grp), + ADI_PMX_FUNCTION("lp3", lp3grp), +}; + +static const struct adi_pinctrl_soc_data adi_bf60x_soc = { + .functions = adi_pmx_functions, + .nfunctions = ARRAY_SIZE(adi_pmx_functions), + .groups = adi_pin_groups, + .ngroups = ARRAY_SIZE(adi_pin_groups), + .pins = adi_pads, + .npins = ARRAY_SIZE(adi_pads), +}; + +void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc) +{ + *soc = &adi_bf60x_soc; +} diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c new file mode 100644 index 00000000000..5c44feb54eb --- /dev/null +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -0,0 +1,1178 @@ +/* + * Pinctrl Driver for ADI GPIO2 controller + * + * Copyright 2007-2013 Analog Devices Inc. + * + * Licensed under the GPLv2 or later + */ + +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/module.h> +#include <linux/err.h> +#include <linux/debugfs.h> +#include <linux/seq_file.h> +#include <linux/irq.h> +#include <linux/platform_data/pinctrl-adi2.h> +#include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/syscore_ops.h> +#include <linux/gpio.h> +#include <asm/portmux.h> +#include "pinctrl-adi2.h" +#include "core.h" + +/* +According to the BF54x HRM, pint means "pin interrupt". +http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf + +ADSP-BF54x processor Blackfin processors have four SIC interrupt chan- +nels dedicated to pin interrupt purposes. These channels are managed by +four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx +block can sense to up to 32 pins. While PINT0 and PINT1 can sense the +pins of port A and port B, PINT2 and PINT3 manage all the pins from port +C to port J as shown in Figure 9-2. + +n BF54x HRM: +The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and +upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi- +plexers shown in Figure 9-3. Lower half units of eight pins can be +forwarded to either byte 0 or byte 2 of either associated PINTx block. +Upper half units can be forwarded to either byte 1 or byte 3 of the pin +interrupt blocks, without further restrictions. + +All MMR registers in the pin interrupt module are 32 bits wide. To simply the +mapping logic, this driver only maps a 16-bit gpio port to the upper or lower +16 bits of a PINTx block. You can find the Figure 9-3 on page 583. + +Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map +to one PINT device. Two in "struct gpio_pint" are used to ease the PINT +interrupt handler. + +The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ +domain pointer in domain[0]. The IRQ domain pointer of the other bank is set +to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out +the current domain pointer according to whether the interrupt request mask +is in lower 16 bits (domain[0]) or upper 16bits (domain[1]). + +A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO +port devices can be mapped to the same PINT device. + +*/ + +static LIST_HEAD(adi_pint_list); +static LIST_HEAD(adi_gpio_port_list); + +#define DRIVER_NAME "pinctrl-adi2" + +#define PINT_HI_OFFSET 16 + +/** + * struct gpio_port_saved - GPIO port registers that should be saved between + * power suspend and resume operations. + * + * @fer: PORTx_FER register + * @data: PORTx_DATA register + * @dir: PORTx_DIR register + * @inen: PORTx_INEN register + * @mux: PORTx_MUX register + */ +struct gpio_port_saved { + u16 fer; + u16 data; + u16 dir; + u16 inen; + u32 mux; +}; + +/* + * struct gpio_pint_saved - PINT registers saved in PM operations + * + * @assign: ASSIGN register + * @edge_set: EDGE_SET register + * @invert_set: INVERT_SET register + */ +struct gpio_pint_saved { + u32 assign; + u32 edge_set; + u32 invert_set; +}; + +/** + * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO + * banks can be mapped into one Pin interrupt controller. + * + * @node: All gpio_pint instances are added to a global list. + * @base: PINT device register base address + * @irq: IRQ of the PINT device, it is the parent IRQ of all + * GPIO IRQs mapping to this device. + * @domain: [0] irq domain of the gpio port, whose hardware interrupts are + * mapping to the low 16-bit of the pint registers. + * [1] irq domain of the gpio port, whose hardware interrupts are + * mapping to the high 16-bit of the pint registers. + * @regs: address pointer to the PINT device + * @map_count: No more than 2 GPIO banks can be mapped to this PINT device. + * @lock: This lock make sure the irq_chip operations to one PINT device + * for different GPIO interrrupts are atomic. + * @pint_map_port: Set up the mapping between one PINT device and + * multiple GPIO banks. + */ +struct gpio_pint { + struct list_head node; + void __iomem *base; + int irq; + struct irq_domain *domain[2]; + struct gpio_pint_regs *regs; + struct gpio_pint_saved saved_data; + int map_count; + spinlock_t lock; + + int (*pint_map_port)(struct gpio_pint *pint, bool assign, + u8 map, struct irq_domain *domain); +}; + +/** + * ADI pin controller + * + * @dev: a pointer back to containing device + * @pctl: the pinctrl device + * @soc: SoC data for this specific chip + */ +struct adi_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + const struct adi_pinctrl_soc_data *soc; +}; + +/** + * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped + * into one pin interrupt controller. + * + * @node: All gpio_port instances are added to a list. + * @base: GPIO bank device register base address + * @irq_base: base IRQ of the GPIO bank device + * @width: PIN number of the GPIO bank device + * @regs: address pointer to the GPIO bank device + * @saved_data: registers that should be saved between PM operations. + * @dev: device structure of this GPIO bank + * @pint: GPIO PINT device that this GPIO bank mapped to + * @pint_map: GIOP bank mapping code in PINT device + * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A + * GPIO bank can be mapped into either low 16 bits[0] or high 16 + * bits[1] of each PINT register. + * @lock: This lock make sure the irq_chip operations to one PINT device + * for different GPIO interrrupts are atomic. + * @chip: abstract a GPIO controller + * @domain: The irq domain owned by the GPIO port. + * @rsvmap: Reservation map array for each pin in the GPIO bank + */ +struct gpio_port { + struct list_head node; + void __iomem *base; + int irq_base; + unsigned int width; + struct gpio_port_t *regs; + struct gpio_port_saved saved_data; + struct device *dev; + + struct gpio_pint *pint; + u8 pint_map; + bool pint_assign; + + spinlock_t lock; + struct gpio_chip chip; + struct irq_domain *domain; +}; + +static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin) +{ + return pin - range->pin_base; +} + +static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq) +{ + return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq); +} + +static struct gpio_pint *find_gpio_pint(unsigned id) +{ + struct gpio_pint *pint; + int i = 0; + + list_for_each_entry(pint, &adi_pint_list, node) { + if (id == i) + return pint; + i++; + } + + return NULL; +} + +static inline void port_setup(struct gpio_port *port, unsigned offset, + bool use_for_gpio) +{ + struct gpio_port_t *regs = port->regs; + + if (use_for_gpio) + writew(readw(®s->port_fer) & ~BIT(offset), + ®s->port_fer); + else + writew(readw(®s->port_fer) | BIT(offset), ®s->port_fer); +} + +static inline void portmux_setup(struct gpio_port *port, unsigned offset, + unsigned short function) +{ + struct gpio_port_t *regs = port->regs; + u32 pmux; + + pmux = readl(®s->port_mux); + + /* The function field of each pin has 2 consecutive bits in + * the mux register. + */ + pmux &= ~(0x3 << (2 * offset)); + pmux |= (function & 0x3) << (2 * offset); + + writel(pmux, ®s->port_mux); +} + +static inline u16 get_portmux(struct gpio_port *port, unsigned offset) +{ + struct gpio_port_t *regs = port->regs; + u32 pmux = readl(®s->port_mux); + + /* The function field of each pin has 2 consecutive bits in + * the mux register. + */ + return pmux >> (2 * offset) & 0x3; +} + +static void adi_gpio_ack_irq(struct irq_data *d) +{ + unsigned long flags; + struct gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_pint_regs *regs = port->pint->regs; + unsigned pintbit = hwirq_to_pintbit(port, d->hwirq); + + spin_lock_irqsave(&port->lock, flags); + spin_lock(&port->pint->lock); + + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { + if (readl(®s->invert_set) & pintbit) + writel(pintbit, ®s->invert_clear); + else + writel(pintbit, ®s->invert_set); + } + + writel(pintbit, ®s->request); + + spin_unlock(&port->pint->lock); + spin_unlock_irqrestore(&port->lock, flags); +} + +static void adi_gpio_mask_ack_irq(struct irq_data *d) +{ + unsigned long flags; + struct gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_pint_regs *regs = port->pint->regs; + unsigned pintbit = hwirq_to_pintbit(port, d->hwirq); + + spin_lock_irqsave(&port->lock, flags); + spin_lock(&port->pint->lock); + + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { + if (readl(®s->invert_set) & pintbit) + writel(pintbit, ®s->invert_clear); + else + writel(pintbit, ®s->invert_set); + } + + writel(pintbit, ®s->request); + writel(pintbit, ®s->mask_clear); + + spin_unlock(&port->pint->lock); + spin_unlock_irqrestore(&port->lock, flags); +} + +static void adi_gpio_mask_irq(struct irq_data *d) +{ + unsigned long flags; + struct gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_pint_regs *regs = port->pint->regs; + + spin_lock_irqsave(&port->lock, flags); + spin_lock(&port->pint->lock); + + writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear); + + spin_unlock(&port->pint->lock); + spin_unlock_irqrestore(&port->lock, flags); +} + +static void adi_gpio_unmask_irq(struct irq_data *d) +{ + unsigned long flags; + struct gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_pint_regs *regs = port->pint->regs; + + spin_lock_irqsave(&port->lock, flags); + spin_lock(&port->pint->lock); + + writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set); + + spin_unlock(&port->pint->lock); + spin_unlock_irqrestore(&port->lock, flags); +} + +static unsigned int adi_gpio_irq_startup(struct irq_data *d) +{ + unsigned long flags; + struct gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_pint_regs *regs; + + if (!port) { + pr_err("GPIO IRQ %d :Not exist\n", d->irq); + /* FIXME: negative return code will be ignored */ + return -ENODEV; + } + + regs = port->pint->regs; + + spin_lock_irqsave(&port->lock, flags); + spin_lock(&port->pint->lock); + + port_setup(port, d->hwirq, true); + writew(BIT(d->hwirq), &port->regs->dir_clear); + writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen); + + writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set); + + spin_unlock(&port->pint->lock); + spin_unlock_irqrestore(&port->lock, flags); + + return 0; +} + +static void adi_gpio_irq_shutdown(struct irq_data *d) +{ + unsigned long flags; + struct gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_pint_regs *regs = port->pint->regs; + + spin_lock_irqsave(&port->lock, flags); + spin_lock(&port->pint->lock); + + writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear); + + spin_unlock(&port->pint->lock); + spin_unlock_irqrestore(&port->lock, flags); +} + +static int adi_gpio_irq_type(struct irq_data *d, unsigned int type) +{ + unsigned long flags; + struct gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_pint_regs *pint_regs; + unsigned pintmask; + unsigned int irq = d->irq; + int ret = 0; + char buf[16]; + + if (!port) { + pr_err("GPIO IRQ %d :Not exist\n", d->irq); + return -ENODEV; + } + + pint_regs = port->pint->regs; + + pintmask = hwirq_to_pintbit(port, d->hwirq); + + spin_lock_irqsave(&port->lock, flags); + spin_lock(&port->pint->lock); + + /* In case of interrupt autodetect, set irq type to edge sensitive. */ + if (type == IRQ_TYPE_PROBE) + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | + IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + snprintf(buf, 16, "gpio-irq%d", irq); + port_setup(port, d->hwirq, true); + } else + goto out; + + /* The GPIO interrupt is triggered only when its input value + * transfer from 0 to 1. So, invert the input value if the + * irq type is low or falling + */ + if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) + writel(pintmask, &pint_regs->invert_set); + else + writel(pintmask, &pint_regs->invert_clear); + + /* In edge sensitive case, if the input value of the requested irq + * is already 1, invert it. + */ + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { + if (gpio_get_value(port->chip.base + d->hwirq)) + writel(pintmask, &pint_regs->invert_set); + else + writel(pintmask, &pint_regs->invert_clear); + } + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { + writel(pintmask, &pint_regs->edge_set); + __irq_set_handler_locked(irq, handle_edge_irq); + } else { + writel(pintmask, &pint_regs->edge_clear); + __irq_set_handler_locked(irq, handle_level_irq); + } + +out: + spin_unlock(&port->pint->lock); + spin_unlock_irqrestore(&port->lock, flags); + + return ret; +} + +#ifdef CONFIG_PM +static int adi_gpio_set_wake(struct irq_data *d, unsigned int state) +{ + struct gpio_port *port = irq_data_get_irq_chip_data(d); + + if (!port || !port->pint || port->pint->irq != d->irq) + return -EINVAL; + +#ifndef SEC_GCTL + adi_internal_set_wake(port->pint->irq, state); +#endif + + return 0; +} + +static int adi_pint_suspend(void) +{ + struct gpio_pint *pint; + + list_for_each_entry(pint, &adi_pint_list, node) { + writel(0xffffffff, &pint->regs->mask_clear); + pint->saved_data.assign = readl(&pint->regs->assign); + pint->saved_data.edge_set = readl(&pint->regs->edge_set); + pint->saved_data.invert_set = readl(&pint->regs->invert_set); + } + + return 0; +} + +static void adi_pint_resume(void) +{ + struct gpio_pint *pint; + + list_for_each_entry(pint, &adi_pint_list, node) { + writel(pint->saved_data.assign, &pint->regs->assign); + writel(pint->saved_data.edge_set, &pint->regs->edge_set); + writel(pint->saved_data.invert_set, &pint->regs->invert_set); + } +} + +static int adi_gpio_suspend(void) +{ + struct gpio_port *port; + + list_for_each_entry(port, &adi_gpio_port_list, node) { + port->saved_data.fer = readw(&port->regs->port_fer); + port->saved_data.mux = readl(&port->regs->port_mux); + port->saved_data.data = readw(&port->regs->data); + port->saved_data.inen = readw(&port->regs->inen); + port->saved_data.dir = readw(&port->regs->dir_set); + } + + return adi_pint_suspend(); +} + +static void adi_gpio_resume(void) +{ + struct gpio_port *port; + + adi_pint_resume(); + + list_for_each_entry(port, &adi_gpio_port_list, node) { + writel(port->saved_data.mux, &port->regs->port_mux); + writew(port->saved_data.fer, &port->regs->port_fer); + writew(port->saved_data.inen, &port->regs->inen); + writew(port->saved_data.data & port->saved_data.dir, + &port->regs->data_set); + writew(port->saved_data.dir, &port->regs->dir_set); + } + +} + +static struct syscore_ops gpio_pm_syscore_ops = { + .suspend = adi_gpio_suspend, + .resume = adi_gpio_resume, +}; +#else /* CONFIG_PM */ +#define adi_gpio_set_wake NULL +#endif /* CONFIG_PM */ + +#ifdef CONFIG_IRQ_PREFLOW_FASTEOI +static inline void preflow_handler(struct irq_desc *desc) +{ + if (desc->preflow_handler) + desc->preflow_handler(&desc->irq_data); +} +#else +static inline void preflow_handler(struct irq_desc *desc) { } +#endif + +static void adi_gpio_handle_pint_irq(unsigned int inta_irq, + struct irq_desc *desc) +{ + u32 request; + u32 level_mask, hwirq; + bool umask = false; + struct gpio_pint *pint = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct gpio_pint_regs *regs = pint->regs; + struct irq_domain *domain; + + preflow_handler(desc); + chained_irq_enter(chip, desc); + + request = readl(®s->request); + level_mask = readl(®s->edge_set) & request; + + hwirq = 0; + domain = pint->domain[0]; + while (request) { + /* domain pointer need to be changed only once at IRQ 16 when + * we go through IRQ requests from bit 0 to bit 31. + */ + if (hwirq == PINT_HI_OFFSET) + domain = pint->domain[1]; + + if (request & 1) { + if (level_mask & BIT(hwirq)) { + umask = true; + chained_irq_exit(chip, desc); + } + generic_handle_irq(irq_find_mapping(domain, + hwirq % PINT_HI_OFFSET)); + } + + hwirq++; + request >>= 1; + } + + if (!umask) + chained_irq_exit(chip, desc); +} + +static struct irq_chip adi_gpio_irqchip = { + .name = "GPIO", + .irq_ack = adi_gpio_ack_irq, + .irq_mask = adi_gpio_mask_irq, + .irq_mask_ack = adi_gpio_mask_ack_irq, + .irq_unmask = adi_gpio_unmask_irq, + .irq_disable = adi_gpio_mask_irq, + .irq_enable = adi_gpio_unmask_irq, + .irq_set_type = adi_gpio_irq_type, + .irq_startup = adi_gpio_irq_startup, + .irq_shutdown = adi_gpio_irq_shutdown, + .irq_set_wake = adi_gpio_set_wake, +}; + +static int adi_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl->soc->ngroups; +} + +static const char *adi_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl->soc->groups[selector].name; +} + +static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pinctrl->soc->groups[selector].pins; + *num_pins = pinctrl->soc->groups[selector].num; + return 0; +} + +static struct pinctrl_ops adi_pctrl_ops = { + .get_groups_count = adi_get_groups_count, + .get_group_name = adi_get_group_name, + .get_group_pins = adi_get_group_pins, +}; + +static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id, + unsigned group_id) +{ + struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_port *port; + struct pinctrl_gpio_range *range; + unsigned long flags; + unsigned short *mux, pin; + + mux = (unsigned short *)pinctrl->soc->groups[group_id].mux; + + while (*mux) { + pin = P_IDENT(*mux); + + range = pinctrl_find_gpio_range_from_pin(pctldev, pin); + if (range == NULL) /* should not happen */ + return -ENODEV; + + port = container_of(range->gc, struct gpio_port, chip); + + spin_lock_irqsave(&port->lock, flags); + + portmux_setup(port, pin_to_offset(range, pin), + P_FUNCT2MUX(*mux)); + port_setup(port, pin_to_offset(range, pin), false); + mux++; + + spin_unlock_irqrestore(&port->lock, flags); + } + + return 0; +} + +static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned func_id, + unsigned group_id) +{ + struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_port *port; + struct pinctrl_gpio_range *range; + unsigned long flags; + unsigned short *mux, pin; + + mux = (unsigned short *)pinctrl->soc->groups[group_id].mux; + + while (*mux) { + pin = P_IDENT(*mux); + + range = pinctrl_find_gpio_range_from_pin(pctldev, pin); + if (range == NULL) /* should not happen */ + return; + + port = container_of(range->gc, struct gpio_port, chip); + + spin_lock_irqsave(&port->lock, flags); + + port_setup(port, pin_to_offset(range, pin), true); + mux++; + + spin_unlock_irqrestore(&port->lock, flags); + } +} + +static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl->soc->nfunctions; +} + +static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl->soc->functions[selector].name; +} + +static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pinctrl->soc->functions[selector].groups; + *num_groups = pinctrl->soc->functions[selector].num_groups; + return 0; +} + +static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned pin) +{ + struct gpio_port *port; + unsigned long flags; + u8 offset; + + port = container_of(range->gc, struct gpio_port, chip); + offset = pin_to_offset(range, pin); + + spin_lock_irqsave(&port->lock, flags); + + port_setup(port, offset, true); + + spin_unlock_irqrestore(&port->lock, flags); + + return 0; +} + +static struct pinmux_ops adi_pinmux_ops = { + .enable = adi_pinmux_enable, + .disable = adi_pinmux_disable, + .get_functions_count = adi_pinmux_get_funcs_count, + .get_function_name = adi_pinmux_get_func_name, + .get_function_groups = adi_pinmux_get_groups, + .gpio_request_enable = adi_pinmux_request_gpio, +}; + + +static struct pinctrl_desc adi_pinmux_desc = { + .name = DRIVER_NAME, + .pctlops = &adi_pctrl_ops, + .pmxops = &adi_pinmux_ops, + .owner = THIS_MODULE, +}; + +static int adi_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void adi_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct gpio_port *port; + unsigned long flags; + + port = container_of(chip, struct gpio_port, chip); + + spin_lock_irqsave(&port->lock, flags); + + writew(BIT(offset), &port->regs->dir_clear); + writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen); + + spin_unlock_irqrestore(&port->lock, flags); + + return 0; +} + +static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct gpio_port *port = container_of(chip, struct gpio_port, chip); + struct gpio_port_t *regs = port->regs; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + + if (value) + writew(BIT(offset), ®s->data_set); + else + writew(BIT(offset), ®s->data_clear); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct gpio_port *port = container_of(chip, struct gpio_port, chip); + struct gpio_port_t *regs = port->regs; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + + writew(readw(®s->inen) & ~BIT(offset), ®s->inen); + if (value) + writew(BIT(offset), ®s->data_set); + else + writew(BIT(offset), ®s->data_clear); + writew(BIT(offset), ®s->dir_set); + + spin_unlock_irqrestore(&port->lock, flags); + + return 0; +} + +static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + struct gpio_port *port = container_of(chip, struct gpio_port, chip); + struct gpio_port_t *regs = port->regs; + unsigned long flags; + int ret; + + spin_lock_irqsave(&port->lock, flags); + + ret = !!(readw(®s->data) & BIT(offset)); + + spin_unlock_irqrestore(&port->lock, flags); + + return ret; +} + +static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct gpio_port *port = container_of(chip, struct gpio_port, chip); + + if (port->irq_base >= 0) + return irq_find_mapping(port->domain, offset); + else + return irq_create_mapping(port->domain, offset); +} + +static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map, + struct irq_domain *domain) +{ + struct gpio_pint_regs *regs = pint->regs; + u32 map_mask; + + if (pint->map_count > 1) + return -EINVAL; + + pint->map_count++; + + /* The map_mask of each gpio port is a 16-bit duplicate + * of the 8-bit map. It can be set to either high 16 bits or low + * 16 bits of the pint assignment register. + */ + map_mask = (map << 8) | map; + if (assign) { + map_mask <<= PINT_HI_OFFSET; + writel((readl(®s->assign) & 0xFFFF) | map_mask, + ®s->assign); + } else + writel((readl(®s->assign) & 0xFFFF0000) | map_mask, + ®s->assign); + + pint->domain[assign] = domain; + + return 0; +} + +static int adi_gpio_pint_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct gpio_pint *pint; + + pint = devm_kzalloc(dev, sizeof(struct gpio_pint), GFP_KERNEL); + if (!pint) { + dev_err(dev, "Memory alloc failed\n"); + return -ENOMEM; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pint->base = devm_ioremap_resource(dev, res); + if (IS_ERR(pint->base)) + return PTR_ERR(pint->base); + + pint->regs = (struct gpio_pint_regs *)pint->base; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(dev, "Invalid IRQ resource\n"); + return -ENODEV; + } + + spin_lock_init(&pint->lock); + + pint->irq = res->start; + pint->pint_map_port = adi_pint_map_port; + platform_set_drvdata(pdev, pint); + + irq_set_chained_handler(pint->irq, adi_gpio_handle_pint_irq); + irq_set_handler_data(pint->irq, pint); + + list_add_tail(&pint->node, &adi_pint_list); + + return 0; +} + +static int adi_gpio_pint_remove(struct platform_device *pdev) +{ + struct gpio_pint *pint = platform_get_drvdata(pdev); + + list_del(&pint->node); + irq_set_handler(pint->irq, handle_simple_irq); + + return 0; +} + +static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct gpio_port *port = d->host_data; + + if (!port) + return -EINVAL; + + irq_set_chip_data(irq, port); + irq_set_chip_and_handler(irq, &adi_gpio_irqchip, + handle_level_irq); + + return 0; +} + +static const struct irq_domain_ops adi_gpio_irq_domain_ops = { + .map = adi_gpio_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int adi_gpio_init_int(struct gpio_port *port) +{ + struct device_node *node = port->dev->of_node; + struct gpio_pint *pint = port->pint; + int ret; + + port->domain = irq_domain_add_linear(node, port->width, + &adi_gpio_irq_domain_ops, port); + if (!port->domain) { + dev_err(port->dev, "Failed to create irqdomain\n"); + return -ENOSYS; + } + + /* According to BF54x and BF60x HRM, pin interrupt devices are not + * part of the GPIO port device. in GPIO interrupt mode, the GPIO + * pins of multiple port devices can be routed into one pin interrupt + * device. The mapping can be configured by setting pint assignment + * register with the mapping value of different GPIO port. This is + * done via function pint_map_port(). + */ + ret = pint->pint_map_port(port->pint, port->pint_assign, + port->pint_map, port->domain); + if (ret) + return ret; + + if (port->irq_base >= 0) { + ret = irq_create_strict_mappings(port->domain, port->irq_base, + 0, port->width); + if (ret) { + dev_err(port->dev, "Couldn't associate to domain\n"); + return ret; + } + } + + return 0; +} + +#define DEVNAME_SIZE 16 + +static int adi_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct adi_pinctrl_gpio_platform_data *pdata; + struct resource *res; + struct gpio_port *port; + char pinctrl_devname[DEVNAME_SIZE]; + static int gpio; + int ret = 0, ret1; + + pdata = dev->platform_data; + if (!pdata) + return -EINVAL; + + port = devm_kzalloc(dev, sizeof(struct gpio_port), GFP_KERNEL); + if (!port) { + dev_err(dev, "Memory alloc failed\n"); + return -ENOMEM; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + port->base = devm_ioremap_resource(dev, res); + if (IS_ERR(port->base)) + return PTR_ERR(port->base); + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) + port->irq_base = -1; + else + port->irq_base = res->start; + + port->width = pdata->port_width; + port->dev = dev; + port->regs = (struct gpio_port_t *)port->base; + port->pint_assign = pdata->pint_assign; + port->pint_map = pdata->pint_map; + + port->pint = find_gpio_pint(pdata->pint_id); + if (port->pint) { + ret = adi_gpio_init_int(port); + if (ret) + return ret; + } + + spin_lock_init(&port->lock); + + platform_set_drvdata(pdev, port); + + port->chip.label = "adi-gpio"; + port->chip.direction_input = adi_gpio_direction_input; + port->chip.get = adi_gpio_get_value; + port->chip.direction_output = adi_gpio_direction_output; + port->chip.set = adi_gpio_set_value; + port->chip.request = adi_gpio_request; + port->chip.free = adi_gpio_free; + port->chip.to_irq = adi_gpio_to_irq; + if (pdata->port_gpio_base > 0) + port->chip.base = pdata->port_gpio_base; + else + port->chip.base = gpio; + port->chip.ngpio = port->width; + gpio = port->chip.base + port->width; + + ret = gpiochip_add(&port->chip); + if (ret) { + dev_err(&pdev->dev, "Fail to add GPIO chip.\n"); + goto out_remove_domain; + } + + /* Add gpio pin range */ + snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d", + pdata->pinctrl_id); + pinctrl_devname[DEVNAME_SIZE - 1] = 0; + ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname, + 0, pdata->port_pin_base, port->width); + if (ret) { + dev_err(&pdev->dev, "Fail to add pin range to %s.\n", + pinctrl_devname); + goto out_remove_gpiochip; + } + + list_add_tail(&port->node, &adi_gpio_port_list); + + return 0; + +out_remove_gpiochip: + ret1 = gpiochip_remove(&port->chip); +out_remove_domain: + if (port->pint) + irq_domain_remove(port->domain); + + return ret; +} + +static int adi_gpio_remove(struct platform_device *pdev) +{ + struct gpio_port *port = platform_get_drvdata(pdev); + int ret; + u8 offset; + + list_del(&port->node); + gpiochip_remove_pin_ranges(&port->chip); + ret = gpiochip_remove(&port->chip); + if (port->pint) { + for (offset = 0; offset < port->width; offset++) + irq_dispose_mapping(irq_find_mapping(port->domain, + offset)); + irq_domain_remove(port->domain); + } + + return ret; +} + +static int adi_pinctrl_probe(struct platform_device *pdev) +{ + struct adi_pinctrl *pinctrl; + + pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); + if (!pinctrl) + return -ENOMEM; + + pinctrl->dev = &pdev->dev; + + adi_pinctrl_soc_init(&pinctrl->soc); + + adi_pinmux_desc.pins = pinctrl->soc->pins; + adi_pinmux_desc.npins = pinctrl->soc->npins; + + /* Now register the pin controller and all pins it handles */ + pinctrl->pctl = pinctrl_register(&adi_pinmux_desc, &pdev->dev, pinctrl); + if (!pinctrl->pctl) { + dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n"); + return -EINVAL; + } + + platform_set_drvdata(pdev, pinctrl); + + return 0; +} + +static int adi_pinctrl_remove(struct platform_device *pdev) +{ + struct adi_pinctrl *pinctrl = platform_get_drvdata(pdev); + + pinctrl_unregister(pinctrl->pctl); + + return 0; +} + +static struct platform_driver adi_pinctrl_driver = { + .probe = adi_pinctrl_probe, + .remove = adi_pinctrl_remove, + .driver = { + .name = DRIVER_NAME, + }, +}; + +static struct platform_driver adi_gpio_pint_driver = { + .probe = adi_gpio_pint_probe, + .remove = adi_gpio_pint_remove, + .driver = { + .name = "adi-gpio-pint", + }, +}; + +static struct platform_driver adi_gpio_driver = { + .probe = adi_gpio_probe, + .remove = adi_gpio_remove, + .driver = { + .name = "adi-gpio", + }, +}; + +static int __init adi_pinctrl_setup(void) +{ + int ret; + + ret = platform_driver_register(&adi_pinctrl_driver); + if (ret) + return ret; + + ret = platform_driver_register(&adi_gpio_pint_driver); + if (ret) + goto pint_error; + + ret = platform_driver_register(&adi_gpio_driver); + if (ret) + goto gpio_error; + +#ifdef CONFIG_PM + register_syscore_ops(&gpio_pm_syscore_ops); +#endif + return ret; +gpio_error: + platform_driver_unregister(&adi_gpio_pint_driver); +pint_error: + platform_driver_unregister(&adi_pinctrl_driver); + + return ret; +} +arch_initcall(adi_pinctrl_setup); + +MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>"); +MODULE_DESCRIPTION("ADI gpio2 pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-adi2.h b/drivers/pinctrl/pinctrl-adi2.h new file mode 100644 index 00000000000..3ca29738213 --- /dev/null +++ b/drivers/pinctrl/pinctrl-adi2.h @@ -0,0 +1,75 @@ +/* + * Pinctrl Driver for ADI GPIO2 controller + * + * Copyright 2007-2013 Analog Devices Inc. + * + * Licensed under the GPLv2 or later + */ + +#ifndef PINCTRL_PINCTRL_ADI2_H +#define PINCTRL_PINCTRL_ADI2_H + +#include <linux/pinctrl/pinctrl.h> + + /** + * struct adi_pin_group - describes a pin group + * @name: the name of this pin group + * @pins: an array of pins + * @num: the number of pins in this array + */ +struct adi_pin_group { + const char *name; + const unsigned *pins; + const unsigned num; + const unsigned short *mux; +}; + +#define ADI_PIN_GROUP(n, p, m) \ + { \ + .name = n, \ + .pins = p, \ + .num = ARRAY_SIZE(p), \ + .mux = m, \ + } + + /** + * struct adi_pmx_func - describes function mux setting of pin groups + * @name: the name of this function mux setting + * @groups: an array of pin groups + * @num_groups: the number of pin groups in this array + * @mux: the function mux setting array, end by zero + */ +struct adi_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; +}; + +#define ADI_PMX_FUNCTION(n, g) \ + { \ + .name = n, \ + .groups = g, \ + .num_groups = ARRAY_SIZE(g), \ + } + +/** + * struct adi_pinctrl_soc_data - ADI pin controller per-SoC configuration + * @functions: The functions supported on this SoC. + * @nfunction: The number of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The number of entries in @groups. + * @pins: An array describing all pins the pin controller affects. + * @npins: The number of entries in @pins. + */ +struct adi_pinctrl_soc_data { + const struct adi_pmx_func *functions; + int nfunctions; + const struct adi_pin_group *groups; + int ngroups; + const struct pinctrl_pin_desc *pins; + int npins; +}; + +void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc); + +#endif /* PINCTRL_PINCTRL_ADI2_H */ diff --git a/drivers/pinctrl/pinctrl-apq8064.c b/drivers/pinctrl/pinctrl-apq8064.c new file mode 100644 index 00000000000..519f7886b0f --- /dev/null +++ b/drivers/pinctrl/pinctrl-apq8064.c @@ -0,0 +1,613 @@ +/* + * Copyright (c) 2014, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc apq8064_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + + PINCTRL_PIN(90, "SDC1_CLK"), + PINCTRL_PIN(91, "SDC1_CMD"), + PINCTRL_PIN(92, "SDC1_DATA"), + PINCTRL_PIN(93, "SDC3_CLK"), + PINCTRL_PIN(94, "SDC3_CMD"), + PINCTRL_PIN(95, "SDC3_DATA"), +}; + +#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_APQ_GPIO_PINS(0); +DECLARE_APQ_GPIO_PINS(1); +DECLARE_APQ_GPIO_PINS(2); +DECLARE_APQ_GPIO_PINS(3); +DECLARE_APQ_GPIO_PINS(4); +DECLARE_APQ_GPIO_PINS(5); +DECLARE_APQ_GPIO_PINS(6); +DECLARE_APQ_GPIO_PINS(7); +DECLARE_APQ_GPIO_PINS(8); +DECLARE_APQ_GPIO_PINS(9); +DECLARE_APQ_GPIO_PINS(10); +DECLARE_APQ_GPIO_PINS(11); +DECLARE_APQ_GPIO_PINS(12); +DECLARE_APQ_GPIO_PINS(13); +DECLARE_APQ_GPIO_PINS(14); +DECLARE_APQ_GPIO_PINS(15); +DECLARE_APQ_GPIO_PINS(16); +DECLARE_APQ_GPIO_PINS(17); +DECLARE_APQ_GPIO_PINS(18); +DECLARE_APQ_GPIO_PINS(19); +DECLARE_APQ_GPIO_PINS(20); +DECLARE_APQ_GPIO_PINS(21); +DECLARE_APQ_GPIO_PINS(22); +DECLARE_APQ_GPIO_PINS(23); +DECLARE_APQ_GPIO_PINS(24); +DECLARE_APQ_GPIO_PINS(25); +DECLARE_APQ_GPIO_PINS(26); +DECLARE_APQ_GPIO_PINS(27); +DECLARE_APQ_GPIO_PINS(28); +DECLARE_APQ_GPIO_PINS(29); +DECLARE_APQ_GPIO_PINS(30); +DECLARE_APQ_GPIO_PINS(31); +DECLARE_APQ_GPIO_PINS(32); +DECLARE_APQ_GPIO_PINS(33); +DECLARE_APQ_GPIO_PINS(34); +DECLARE_APQ_GPIO_PINS(35); +DECLARE_APQ_GPIO_PINS(36); +DECLARE_APQ_GPIO_PINS(37); +DECLARE_APQ_GPIO_PINS(38); +DECLARE_APQ_GPIO_PINS(39); +DECLARE_APQ_GPIO_PINS(40); +DECLARE_APQ_GPIO_PINS(41); +DECLARE_APQ_GPIO_PINS(42); +DECLARE_APQ_GPIO_PINS(43); +DECLARE_APQ_GPIO_PINS(44); +DECLARE_APQ_GPIO_PINS(45); +DECLARE_APQ_GPIO_PINS(46); +DECLARE_APQ_GPIO_PINS(47); +DECLARE_APQ_GPIO_PINS(48); +DECLARE_APQ_GPIO_PINS(49); +DECLARE_APQ_GPIO_PINS(50); +DECLARE_APQ_GPIO_PINS(51); +DECLARE_APQ_GPIO_PINS(52); +DECLARE_APQ_GPIO_PINS(53); +DECLARE_APQ_GPIO_PINS(54); +DECLARE_APQ_GPIO_PINS(55); +DECLARE_APQ_GPIO_PINS(56); +DECLARE_APQ_GPIO_PINS(57); +DECLARE_APQ_GPIO_PINS(58); +DECLARE_APQ_GPIO_PINS(59); +DECLARE_APQ_GPIO_PINS(60); +DECLARE_APQ_GPIO_PINS(61); +DECLARE_APQ_GPIO_PINS(62); +DECLARE_APQ_GPIO_PINS(63); +DECLARE_APQ_GPIO_PINS(64); +DECLARE_APQ_GPIO_PINS(65); +DECLARE_APQ_GPIO_PINS(66); +DECLARE_APQ_GPIO_PINS(67); +DECLARE_APQ_GPIO_PINS(68); +DECLARE_APQ_GPIO_PINS(69); +DECLARE_APQ_GPIO_PINS(70); +DECLARE_APQ_GPIO_PINS(71); +DECLARE_APQ_GPIO_PINS(72); +DECLARE_APQ_GPIO_PINS(73); +DECLARE_APQ_GPIO_PINS(74); +DECLARE_APQ_GPIO_PINS(75); +DECLARE_APQ_GPIO_PINS(76); +DECLARE_APQ_GPIO_PINS(77); +DECLARE_APQ_GPIO_PINS(78); +DECLARE_APQ_GPIO_PINS(79); +DECLARE_APQ_GPIO_PINS(80); +DECLARE_APQ_GPIO_PINS(81); +DECLARE_APQ_GPIO_PINS(82); +DECLARE_APQ_GPIO_PINS(83); +DECLARE_APQ_GPIO_PINS(84); +DECLARE_APQ_GPIO_PINS(85); +DECLARE_APQ_GPIO_PINS(86); +DECLARE_APQ_GPIO_PINS(87); +DECLARE_APQ_GPIO_PINS(88); +DECLARE_APQ_GPIO_PINS(89); + +static const unsigned int sdc1_clk_pins[] = { 90 }; +static const unsigned int sdc1_cmd_pins[] = { 91 }; +static const unsigned int sdc1_data_pins[] = { 92 }; +static const unsigned int sdc3_clk_pins[] = { 93 }; +static const unsigned int sdc3_cmd_pins[] = { 94 }; +static const unsigned int sdc3_data_pins[] = { 95 }; + +#define FUNCTION(fname) \ + [APQ_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + APQ_MUX_NA, /* gpio mode */ \ + APQ_MUX_##f1, \ + APQ_MUX_##f2, \ + APQ_MUX_##f3, \ + APQ_MUX_##f4, \ + APQ_MUX_##f5, \ + APQ_MUX_##f6, \ + APQ_MUX_##f7, \ + APQ_MUX_##f8, \ + APQ_MUX_##f9, \ + APQ_MUX_##f10, \ + }, \ + .nfuncs = 11, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum apq8064_functions { + APQ_MUX_cam_mclk, + APQ_MUX_codec_mic_i2s, + APQ_MUX_codec_spkr_i2s, + APQ_MUX_gsbi1, + APQ_MUX_gsbi2, + APQ_MUX_gsbi3, + APQ_MUX_gsbi4, + APQ_MUX_gsbi4_cam_i2c, + APQ_MUX_gsbi5, + APQ_MUX_gsbi5_spi_cs1, + APQ_MUX_gsbi5_spi_cs2, + APQ_MUX_gsbi5_spi_cs3, + APQ_MUX_gsbi6, + APQ_MUX_gsbi6_spi_cs1, + APQ_MUX_gsbi6_spi_cs2, + APQ_MUX_gsbi6_spi_cs3, + APQ_MUX_gsbi7, + APQ_MUX_gsbi7_spi_cs1, + APQ_MUX_gsbi7_spi_cs2, + APQ_MUX_gsbi7_spi_cs3, + APQ_MUX_gsbi_cam_i2c, + APQ_MUX_hdmi, + APQ_MUX_mi2s, + APQ_MUX_riva_bt, + APQ_MUX_riva_fm, + APQ_MUX_riva_wlan, + APQ_MUX_sdc2, + APQ_MUX_sdc4, + APQ_MUX_slimbus, + APQ_MUX_spkr_i2s, + APQ_MUX_tsif1, + APQ_MUX_tsif2, + APQ_MUX_usb2_hsic, + APQ_MUX_NA, +}; + +static const char * const cam_mclk_groups[] = { + "gpio4" "gpio5" +}; +static const char * const codec_mic_i2s_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38" +}; +static const char * const codec_spkr_i2s_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42" +}; +static const char * const gsbi1_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21" +}; +static const char * const gsbi2_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char * const gsbi3_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9" +}; +static const char * const gsbi4_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const gsbi4_cam_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const gsbi5_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54" +}; +static const char * const gsbi5_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi5_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi5_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi6_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17" +}; +static const char * const gsbi6_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi6_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi6_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi7_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85" +}; +static const char * const gsbi7_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi7_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi7_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi_cam_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const hdmi_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; +static const char * const mi2s_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33" +}; +static const char * const riva_bt_groups[] = { + "gpio16", "gpio17" +}; +static const char * const riva_fm_groups[] = { + "gpio14", "gpio15" +}; +static const char * const riva_wlan_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const sdc2_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62" +}; +static const char * const sdc4_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const slimbus_groups[] = { + "gpio40", "gpio41" +}; +static const char * const spkr_i2s_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50" +}; +static const char * const tsif1_groups[] = { + "gpio55", "gpio56", "gpio57" +}; +static const char * const tsif2_groups[] = { + "gpio58", "gpio59", "gpio60" +}; +static const char * const usb2_hsic_groups[] = { + "gpio88", "gpio89" +}; + +static const struct msm_function apq8064_functions[] = { + FUNCTION(cam_mclk), + FUNCTION(codec_mic_i2s), + FUNCTION(codec_spkr_i2s), + FUNCTION(gsbi1), + FUNCTION(gsbi2), + FUNCTION(gsbi3), + FUNCTION(gsbi4), + FUNCTION(gsbi4_cam_i2c), + FUNCTION(gsbi5), + FUNCTION(gsbi5_spi_cs1), + FUNCTION(gsbi5_spi_cs2), + FUNCTION(gsbi5_spi_cs3), + FUNCTION(gsbi6), + FUNCTION(gsbi6_spi_cs1), + FUNCTION(gsbi6_spi_cs2), + FUNCTION(gsbi6_spi_cs3), + FUNCTION(gsbi7), + FUNCTION(gsbi7_spi_cs1), + FUNCTION(gsbi7_spi_cs2), + FUNCTION(gsbi7_spi_cs3), + FUNCTION(gsbi_cam_i2c), + FUNCTION(hdmi), + FUNCTION(mi2s), + FUNCTION(riva_bt), + FUNCTION(riva_fm), + FUNCTION(riva_wlan), + FUNCTION(sdc2), + FUNCTION(sdc4), + FUNCTION(slimbus), + FUNCTION(spkr_i2s), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(usb2_hsic), +}; + +static const struct msm_pingroup apq8064_groups[] = { + PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, NA, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi4, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c, NA), + PINGROUP(11, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c), + PINGROUP(12, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), + PINGROUP(13, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), + PINGROUP(14, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA), + PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA), + PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA), + PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, tsif1, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, NA, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 90 + +static const struct msm_pinctrl_soc_data apq8064_pinctrl = { + .pins = apq8064_pins, + .npins = ARRAY_SIZE(apq8064_pins), + .functions = apq8064_functions, + .nfunctions = ARRAY_SIZE(apq8064_functions), + .groups = apq8064_groups, + .ngroups = ARRAY_SIZE(apq8064_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int apq8064_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &apq8064_pinctrl); +} + +static const struct of_device_id apq8064_pinctrl_of_match[] = { + { .compatible = "qcom,apq8064-pinctrl", }, + { }, +}; + +static struct platform_driver apq8064_pinctrl_driver = { + .driver = { + .name = "apq8064-pinctrl", + .owner = THIS_MODULE, + .of_match_table = apq8064_pinctrl_of_match, + }, + .probe = apq8064_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init apq8064_pinctrl_init(void) +{ + return platform_driver_register(&apq8064_pinctrl_driver); +} +arch_initcall(apq8064_pinctrl_init); + +static void __exit apq8064_pinctrl_exit(void) +{ + platform_driver_unregister(&apq8064_pinctrl_driver); +} +module_exit(apq8064_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); +MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c new file mode 100644 index 00000000000..c862f9c0e9c --- /dev/null +++ b/drivers/pinctrl/pinctrl-as3722.c @@ -0,0 +1,655 @@ +/* + * ams AS3722 pin control and GPIO driver. + * + * Copyright (c) 2013, NVIDIA Corporation. + * + * Author: Laxman Dewangan <ldewangan@nvidia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/mfd/as3722.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pm.h> +#include <linux/slab.h> + +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + +#define AS3722_PIN_GPIO0 0 +#define AS3722_PIN_GPIO1 1 +#define AS3722_PIN_GPIO2 2 +#define AS3722_PIN_GPIO3 3 +#define AS3722_PIN_GPIO4 4 +#define AS3722_PIN_GPIO5 5 +#define AS3722_PIN_GPIO6 6 +#define AS3722_PIN_GPIO7 7 +#define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1) + +#define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP) +#define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN) +#define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE) +#define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN) + +struct as3722_pin_function { + const char *name; + const char * const *groups; + unsigned ngroups; + int mux_option; +}; + +struct as3722_gpio_pin_control { + unsigned mode_prop; + int io_function; +}; + +struct as3722_pingroup { + const char *name; + const unsigned pins[1]; + unsigned npins; +}; + +struct as3722_pctrl_info { + struct device *dev; + struct pinctrl_dev *pctl; + struct as3722 *as3722; + struct gpio_chip gpio_chip; + int pins_current_opt[AS3722_PIN_NUM]; + const struct as3722_pin_function *functions; + unsigned num_functions; + const struct as3722_pingroup *pin_groups; + int num_pin_groups; + const struct pinctrl_pin_desc *pins; + unsigned num_pins; + struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM]; +}; + +static const struct pinctrl_pin_desc as3722_pins_desc[] = { + PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"), + PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"), + PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"), + PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"), + PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"), + PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"), + PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"), + PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"), +}; + +static const char * const gpio_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", +}; + +enum as3722_pinmux_option { + AS3722_PINMUX_GPIO = 0, + AS3722_PINMUX_INTERRUPT_OUT = 1, + AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2, + AS3722_PINMUX_GPIO_INTERRUPT = 3, + AS3722_PINMUX_PWM_INPUT = 4, + AS3722_PINMUX_VOLTAGE_IN_STBY = 5, + AS3722_PINMUX_OC_PG_SD0 = 6, + AS3722_PINMUX_PG_OUT = 7, + AS3722_PINMUX_CLK32K_OUT = 8, + AS3722_PINMUX_WATCHDOG_INPUT = 9, + AS3722_PINMUX_SOFT_RESET_IN = 11, + AS3722_PINMUX_PWM_OUTPUT = 12, + AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13, + AS3722_PINMUX_OC_PG_SD6 = 14, +}; + +#define FUNCTION_GROUP(fname, mux) \ + { \ + .name = #fname, \ + .groups = gpio_groups, \ + .ngroups = ARRAY_SIZE(gpio_groups), \ + .mux_option = AS3722_PINMUX_##mux, \ + } + +static const struct as3722_pin_function as3722_pin_function[] = { + FUNCTION_GROUP(gpio, GPIO), + FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT), + FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT), + FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT), + FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT), + FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY), + FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0), + FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6), + FUNCTION_GROUP(powergood-out, PG_OUT), + FUNCTION_GROUP(pwm-in, PWM_INPUT), + FUNCTION_GROUP(pwm-out, PWM_OUTPUT), + FUNCTION_GROUP(clk32k-out, CLK32K_OUT), + FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT), + FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN), +}; + +#define AS3722_PINGROUP(pg_name, pin_id) \ + { \ + .name = #pg_name, \ + .pins = {AS3722_PIN_##pin_id}, \ + .npins = 1, \ + } + +static const struct as3722_pingroup as3722_pingroups[] = { + AS3722_PINGROUP(gpio0, GPIO0), + AS3722_PINGROUP(gpio1, GPIO1), + AS3722_PINGROUP(gpio2, GPIO2), + AS3722_PINGROUP(gpio3, GPIO3), + AS3722_PINGROUP(gpio4, GPIO4), + AS3722_PINGROUP(gpio5, GPIO5), + AS3722_PINGROUP(gpio6, GPIO6), + AS3722_PINGROUP(gpio7, GPIO7), +}; + +static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + + return as_pci->num_pin_groups; +} + +static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + + return as_pci->pin_groups[group].name; +} + +static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, unsigned *num_pins) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + + *pins = as_pci->pin_groups[group].pins; + *num_pins = as_pci->pin_groups[group].npins; + return 0; +} + +static const struct pinctrl_ops as3722_pinctrl_ops = { + .get_groups_count = as3722_pinctrl_get_groups_count, + .get_group_name = as3722_pinctrl_get_group_name, + .get_group_pins = as3722_pinctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + + return as_pci->num_functions; +} + +static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + + return as_pci->functions[function].name; +} + +static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, const char * const **groups, + unsigned * const num_groups) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + + *groups = as_pci->functions[function].groups; + *num_groups = as_pci->functions[function].ngroups; + return 0; +} + +static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group); + u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option); + int ret; + + dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n", + __func__, group, function, val); + + ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg, + AS3722_GPIO_IOSF_MASK, val); + if (ret < 0) { + dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n", + group, ret); + return ret; + } + as_pci->gpio_control[group].io_function = function; + + switch (val) { + case AS3722_GPIO_IOSF_SD0_OUT: + case AS3722_GPIO_IOSF_PWR_GOOD_OUT: + case AS3722_GPIO_IOSF_Q32K_OUT: + case AS3722_GPIO_IOSF_PWM_OUT: + case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW: + ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg, + AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH); + if (ret < 0) { + dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n", + group, ret); + return ret; + } + as_pci->gpio_control[group].mode_prop = + AS3722_GPIO_MODE_OUTPUT_VDDH; + break; + default: + break; + } + return ret; +} + +static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input) +{ + if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED) + return -EINVAL; + + if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) { + if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP) + return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP; + return AS3722_GPIO_MODE_IO_OPEN_DRAIN; + } + if (input) { + if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP) + return AS3722_GPIO_MODE_INPUT_PULL_UP; + else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN) + return AS3722_GPIO_MODE_INPUT_PULL_DOWN; + return AS3722_GPIO_MODE_INPUT; + } + if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN) + return AS3722_GPIO_MODE_OUTPUT_VDDL; + return AS3722_GPIO_MODE_OUTPUT_VDDH; +} + +static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned offset) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + + if (as_pci->gpio_control[offset].io_function) + return -EBUSY; + return 0; +} + +static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned offset, bool input) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + struct as3722 *as3722 = as_pci->as3722; + int mode; + + mode = as3722_pinctrl_gpio_get_mode( + as_pci->gpio_control[offset].mode_prop, input); + if (mode < 0) { + dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n", + (input) ? "Input" : "Output", offset); + return mode; + } + + return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset), + AS3722_GPIO_MODE_MASK, mode); +} + +static const struct pinmux_ops as3722_pinmux_ops = { + .get_functions_count = as3722_pinctrl_get_funcs_count, + .get_function_name = as3722_pinctrl_get_func_name, + .get_function_groups = as3722_pinctrl_get_func_groups, + .enable = as3722_pinctrl_enable, + .gpio_request_enable = as3722_pinctrl_gpio_request_enable, + .gpio_set_direction = as3722_pinctrl_gpio_set_direction, +}; + +static int as3722_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *config) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + int arg = 0; + u16 prop; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + prop = AS3722_GPIO_MODE_PULL_UP | + AS3722_GPIO_MODE_PULL_DOWN; + if (!(as_pci->gpio_control[pin].mode_prop & prop)) + arg = 1; + prop = 0; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + prop = AS3722_GPIO_MODE_PULL_UP; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + prop = AS3722_GPIO_MODE_PULL_DOWN; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + prop = AS3722_GPIO_MODE_OPEN_DRAIN; + break; + + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + prop = AS3722_GPIO_MODE_HIGH_IMPED; + break; + + default: + dev_err(as_pci->dev, "Properties not supported\n"); + return -ENOTSUPP; + } + + if (as_pci->gpio_control[pin].mode_prop & prop) + arg = 1; + + *config = pinconf_to_config_packed(param, (u16)arg); + return 0; +} + +static int as3722_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *configs, + unsigned num_configs) +{ + struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + int mode_prop; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + mode_prop = as_pci->gpio_control[pin].mode_prop; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + break; + + case PIN_CONFIG_BIAS_DISABLE: + mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP | + AS3722_GPIO_MODE_PULL_DOWN); + break; + case PIN_CONFIG_BIAS_PULL_UP: + mode_prop |= AS3722_GPIO_MODE_PULL_UP; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + mode_prop |= AS3722_GPIO_MODE_PULL_DOWN; + break; + + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN; + break; + + default: + dev_err(as_pci->dev, "Properties not supported\n"); + return -ENOTSUPP; + } + + as_pci->gpio_control[pin].mode_prop = mode_prop; + } + return 0; +} + +static const struct pinconf_ops as3722_pinconf_ops = { + .pin_config_get = as3722_pinconf_get, + .pin_config_set = as3722_pinconf_set, +}; + +static struct pinctrl_desc as3722_pinctrl_desc = { + .pctlops = &as3722_pinctrl_ops, + .pmxops = &as3722_pinmux_ops, + .confops = &as3722_pinconf_ops, + .owner = THIS_MODULE, +}; + +static inline struct as3722_pctrl_info *to_as_pci(struct gpio_chip *chip) +{ + return container_of(chip, struct as3722_pctrl_info, gpio_chip); +} + +static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct as3722_pctrl_info *as_pci = to_as_pci(chip); + struct as3722 *as3722 = as_pci->as3722; + int ret; + u32 reg; + u32 control; + u32 val; + int mode; + int invert_enable; + + ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control); + if (ret < 0) { + dev_err(as_pci->dev, + "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret); + return ret; + } + + invert_enable = !!(control & AS3722_GPIO_INV); + mode = control & AS3722_GPIO_MODE_MASK; + switch (mode) { + case AS3722_GPIO_MODE_INPUT: + case AS3722_GPIO_MODE_INPUT_PULL_UP: + case AS3722_GPIO_MODE_INPUT_PULL_DOWN: + case AS3722_GPIO_MODE_IO_OPEN_DRAIN: + case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP: + reg = AS3722_GPIO_SIGNAL_IN_REG; + break; + case AS3722_GPIO_MODE_OUTPUT_VDDH: + case AS3722_GPIO_MODE_OUTPUT_VDDL: + reg = AS3722_GPIO_SIGNAL_OUT_REG; + break; + default: + return -EINVAL; + } + + ret = as3722_read(as3722, reg, &val); + if (ret < 0) { + dev_err(as_pci->dev, + "GPIO_SIGNAL_IN_REG read failed: %d\n", ret); + return ret; + } + + val = !!(val & AS3722_GPIOn_SIGNAL(offset)); + return (invert_enable) ? !val : val; +} + +static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct as3722_pctrl_info *as_pci = to_as_pci(chip); + struct as3722 *as3722 = as_pci->as3722; + int en_invert; + u32 val; + int ret; + + ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val); + if (ret < 0) { + dev_err(as_pci->dev, + "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret); + return; + } + en_invert = !!(val & AS3722_GPIO_INV); + + if (value) + val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset); + else + val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0; + + ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG, + AS3722_GPIOn_SIGNAL(offset), val); + if (ret < 0) + dev_err(as_pci->dev, + "GPIO_SIGNAL_OUT_REG update failed: %d\n", ret); +} + +static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int as3722_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + as3722_gpio_set(chip, offset, value); + return pinctrl_gpio_direction_output(chip->base + offset); +} + +static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct as3722_pctrl_info *as_pci = to_as_pci(chip); + + return as3722_irq_get_virq(as_pci->as3722, offset); +} + +static int as3722_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void as3722_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static const struct gpio_chip as3722_gpio_chip = { + .label = "as3722-gpio", + .owner = THIS_MODULE, + .request = as3722_gpio_request, + .free = as3722_gpio_free, + .get = as3722_gpio_get, + .set = as3722_gpio_set, + .direction_input = as3722_gpio_direction_input, + .direction_output = as3722_gpio_direction_output, + .to_irq = as3722_gpio_to_irq, + .can_sleep = true, + .ngpio = AS3722_PIN_NUM, + .base = -1, +}; + +static int as3722_pinctrl_probe(struct platform_device *pdev) +{ + struct as3722_pctrl_info *as_pci; + int ret; + int tret; + + as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL); + if (!as_pci) + return -ENOMEM; + + as_pci->dev = &pdev->dev; + as_pci->dev->of_node = pdev->dev.parent->of_node; + as_pci->as3722 = dev_get_drvdata(pdev->dev.parent); + platform_set_drvdata(pdev, as_pci); + + as_pci->pins = as3722_pins_desc; + as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc); + as_pci->functions = as3722_pin_function; + as_pci->num_functions = ARRAY_SIZE(as3722_pin_function); + as_pci->pin_groups = as3722_pingroups; + as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups); + as3722_pinctrl_desc.name = dev_name(&pdev->dev); + as3722_pinctrl_desc.pins = as3722_pins_desc; + as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc); + as_pci->pctl = pinctrl_register(&as3722_pinctrl_desc, + &pdev->dev, as_pci); + if (!as_pci->pctl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -EINVAL; + } + + as_pci->gpio_chip = as3722_gpio_chip; + as_pci->gpio_chip.dev = &pdev->dev; + as_pci->gpio_chip.of_node = pdev->dev.parent->of_node; + ret = gpiochip_add(&as_pci->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret); + goto fail_chip_add; + } + + ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev), + 0, 0, AS3722_PIN_NUM); + if (ret < 0) { + dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret); + goto fail_range_add; + } + + return 0; + +fail_range_add: + tret = gpiochip_remove(&as_pci->gpio_chip); + if (tret < 0) + dev_warn(&pdev->dev, "Couldn't remove gpio chip, %d\n", tret); + +fail_chip_add: + pinctrl_unregister(as_pci->pctl); + return ret; +} + +static int as3722_pinctrl_remove(struct platform_device *pdev) +{ + struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&as_pci->gpio_chip); + if (ret < 0) + return ret; + pinctrl_unregister(as_pci->pctl); + return 0; +} + +static struct of_device_id as3722_pinctrl_of_match[] = { + { .compatible = "ams,as3722-pinctrl", }, + { }, +}; +MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match); + +static struct platform_driver as3722_pinctrl_driver = { + .driver = { + .name = "as3722-pinctrl", + .owner = THIS_MODULE, + .of_match_table = as3722_pinctrl_of_match, + }, + .probe = as3722_pinctrl_probe, + .remove = as3722_pinctrl_remove, +}; +module_platform_driver(as3722_pinctrl_driver); + +MODULE_ALIAS("platform:as3722-pinctrl"); +MODULE_DESCRIPTION("AS3722 pin control and GPIO driver"); +MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 4d7f531e945..421493cb490 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -16,8 +16,6 @@ #include <linux/of_irq.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> #include <linux/io.h> #include <linux/gpio.h> #include <linux/pinctrl/machine.h> @@ -27,13 +25,12 @@ /* Since we request GPIOs from ourself */ #include <linux/pinctrl/consumer.h> -#include <asm/mach/irq.h> - #include <mach/hardware.h> #include <mach/at91_pio.h> #include "core.h" +#define MAX_GPIO_BANKS 5 #define MAX_NB_GPIO_PER_BANK 32 struct at91_pinctrl_mux_ops; @@ -47,7 +44,6 @@ struct at91_gpio_chip { int pioc_idx; /* PIO bank index */ void __iomem *regbase; /* PIO bank virtual address */ struct clk *clock; /* associated clock */ - struct irq_domain *domain; /* associated irq domain */ struct at91_pinctrl_mux_ops *ops; /* ops */ }; @@ -118,7 +114,7 @@ struct at91_pin_group { }; /** - * struct at91_pinctrl_mux_ops - describes an At91 mux ops group + * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group * on new IP with support for periph C and D the way to mux in * periph A and B has changed * So provide the right call back @@ -145,11 +141,11 @@ struct at91_pinctrl_mux_ops { void (*mux_C_periph)(void __iomem *pio, unsigned mask); void (*mux_D_periph)(void __iomem *pio, unsigned mask); bool (*get_deglitch)(void __iomem *pio, unsigned pin); - void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on); + void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); - void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div); + void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); bool (*get_pulldown)(void __iomem *pio, unsigned pin); - void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on); + void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); /* irq */ @@ -244,7 +240,7 @@ static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, int i; /* - * first find the group of this node and check if we need create + * first find the group of this node and check if we need to create * config maps for pins */ grp = at91_pinctrl_find_group_by_name(info, np->name); @@ -326,7 +322,7 @@ static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) { - return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1; + return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); } static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) @@ -418,6 +414,14 @@ static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); } +static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) +{ + if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) + return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); + + return false; +} + static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) { if (is_on) @@ -429,7 +433,8 @@ static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div { *div = __raw_readl(pio + PIO_SCDR); - return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1; + return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) && + ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); } static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, @@ -439,14 +444,13 @@ static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, __raw_writel(mask, pio + PIO_IFSCER); __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); __raw_writel(mask, pio + PIO_IFER); - } else { - __raw_writel(mask, pio + PIO_IFDR); - } + } else + __raw_writel(mask, pio + PIO_IFSCDR); } static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) { - return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1; + return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1); } static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) @@ -479,7 +483,7 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = { .mux_B_periph = at91_mux_pio3_set_B_periph, .mux_C_periph = at91_mux_pio3_set_C_periph, .mux_D_periph = at91_mux_pio3_set_D_periph, - .get_deglitch = at91_mux_get_deglitch, + .get_deglitch = at91_mux_pio3_get_deglitch, .set_deglitch = at91_mux_pio3_set_deglitch, .get_debounce = at91_mux_pio3_get_debounce, .set_debounce = at91_mux_pio3_set_debounce, @@ -565,7 +569,7 @@ static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, info->functions[selector].name, info->groups[group].name); /* first check that all the pins of the group are valid with a valid - * paramter */ + * parameter */ for (i = 0; i < npins; i++) { pin = &pins_conf[i]; ret = pin_check_config(info, info->groups[group].name, i, pin); @@ -714,7 +718,8 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin; int div; - dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); + *config = 0; + dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); pio = pin_to_controller(info, pin_to_bank(pin_id)); pin = pin_id % MAX_NB_GPIO_PER_BANK; @@ -737,38 +742,73 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev, } static int at91_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long config) + unsigned pin_id, unsigned long *configs, + unsigned num_configs) { struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); unsigned mask; void __iomem *pio; - - dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config); - pio = pin_to_controller(info, pin_to_bank(pin_id)); - mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); - - if (config & PULL_UP && config & PULL_DOWN) - return -EINVAL; - - at91_mux_set_pullup(pio, mask, config & PULL_UP); - at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); - if (info->ops->set_deglitch) - info->ops->set_deglitch(pio, mask, config & DEGLITCH); - if (info->ops->set_debounce) - info->ops->set_debounce(pio, mask, config & DEBOUNCE, + int i; + unsigned long config; + + for (i = 0; i < num_configs; i++) { + config = configs[i]; + + dev_dbg(info->dev, + "%s:%d, pin_id=%d, config=0x%lx", + __func__, __LINE__, pin_id, config); + pio = pin_to_controller(info, pin_to_bank(pin_id)); + mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); + + if (config & PULL_UP && config & PULL_DOWN) + return -EINVAL; + + at91_mux_set_pullup(pio, mask, config & PULL_UP); + at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); + if (info->ops->set_deglitch) + info->ops->set_deglitch(pio, mask, config & DEGLITCH); + if (info->ops->set_debounce) + info->ops->set_debounce(pio, mask, config & DEBOUNCE, (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); - if (info->ops->set_pulldown) - info->ops->set_pulldown(pio, mask, config & PULL_DOWN); - if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) - info->ops->disable_schmitt_trig(pio, mask); + if (info->ops->set_pulldown) + info->ops->set_pulldown(pio, mask, config & PULL_DOWN); + if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) + info->ops->disable_schmitt_trig(pio, mask); + + } /* for each config */ return 0; } +#define DBG_SHOW_FLAG(flag) do { \ + if (config & flag) { \ + if (num_conf) \ + seq_puts(s, "|"); \ + seq_puts(s, #flag); \ + num_conf++; \ + } \ +} while (0) + static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin_id) { + unsigned long config; + int ret, val, num_conf = 0; + + ret = at91_pinconf_get(pctldev, pin_id, &config); + DBG_SHOW_FLAG(MULTI_DRIVE); + DBG_SHOW_FLAG(PULL_UP); + DBG_SHOW_FLAG(PULL_DOWN); + DBG_SHOW_FLAG(DIS_SCHMIT); + DBG_SHOW_FLAG(DEGLITCH); + DBG_SHOW_FLAG(DEBOUNCE); + if (config & DEBOUNCE) { + val = config >> DEBOUNCE_VAL_SHIFT; + seq_printf(s, "(%d)", val); + } + + return; } static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, @@ -949,7 +989,7 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev, at91_pinctrl_child_count(info, np); if (info->nbanks < 1) { - dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); + dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); return -EINVAL; } @@ -1093,6 +1133,17 @@ static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) pinctrl_free_gpio(gpio); } +static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + unsigned mask = 1 << offset; + u32 osr; + + osr = readl_relaxed(pio + PIO_OSR); + return !(osr & mask); +} + static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); @@ -1137,21 +1188,6 @@ static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, return 0; } -static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); - int virq; - - if (offset < chip->ngpio) - virq = irq_create_mapping(at91_gpio->domain, offset); - else - virq = -ENXIO; - - dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", - chip->label, offset + chip->base, virq); - return virq; -} - #ifdef CONFIG_DEBUG_FS static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { @@ -1161,8 +1197,7 @@ static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) void __iomem *pio = at91_gpio->regbase; for (i = 0; i < chip->ngpio; i++) { - unsigned pin = chip->base + i; - unsigned mask = pin_to_mask(pin); + unsigned mask = pin_to_mask(i); const char *gpio_label; u32 pdsr; @@ -1242,18 +1277,22 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type) switch (type) { case IRQ_TYPE_EDGE_RISING: + __irq_set_handler_locked(d->irq, handle_simple_irq); writel_relaxed(mask, pio + PIO_ESR); writel_relaxed(mask, pio + PIO_REHLSR); break; case IRQ_TYPE_EDGE_FALLING: + __irq_set_handler_locked(d->irq, handle_simple_irq); writel_relaxed(mask, pio + PIO_ESR); writel_relaxed(mask, pio + PIO_FELLSR); break; case IRQ_TYPE_LEVEL_LOW: + __irq_set_handler_locked(d->irq, handle_level_irq); writel_relaxed(mask, pio + PIO_LSR); writel_relaxed(mask, pio + PIO_FELLSR); break; case IRQ_TYPE_LEVEL_HIGH: + __irq_set_handler_locked(d->irq, handle_level_irq); writel_relaxed(mask, pio + PIO_LSR); writel_relaxed(mask, pio + PIO_REHLSR); break; @@ -1262,6 +1301,7 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type) * disable additional interrupt modes: * fall back to default behavior */ + __irq_set_handler_locked(d->irq, handle_simple_irq); writel_relaxed(mask, pio + PIO_AIMDR); return 0; case IRQ_TYPE_NONE: @@ -1276,6 +1316,36 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type) return 0; } +static void gpio_irq_ack(struct irq_data *d) +{ + /* the interrupt is already cleared before by reading ISR */ +} + +static unsigned int gpio_irq_startup(struct irq_data *d) +{ + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); + unsigned pin = d->hwirq; + int ret; + + ret = gpio_lock_as_irq(&at91_gpio->chip, pin); + if (ret) { + dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n", + d->hwirq); + return ret; + } + gpio_irq_unmask(d); + return 0; +} + +static void gpio_irq_shutdown(struct irq_data *d) +{ + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); + unsigned pin = d->hwirq; + + gpio_irq_mask(d); + gpio_unlock_as_irq(&at91_gpio->chip, pin); +} + #ifdef CONFIG_PM static u32 wakeups[MAX_GPIO_BANKS]; @@ -1316,13 +1386,11 @@ void at91_pinctrl_gpio_suspend(void) __raw_writel(backups[i], pio + PIO_IDR); __raw_writel(wakeups[i], pio + PIO_IER); - if (!wakeups[i]) { - clk_unprepare(gpio_chips[i]->clock); - clk_disable(gpio_chips[i]->clock); - } else { + if (!wakeups[i]) + clk_disable_unprepare(gpio_chips[i]->clock); + else printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); - } } } @@ -1338,10 +1406,8 @@ void at91_pinctrl_gpio_resume(void) pio = gpio_chips[i]->regbase; - if (!wakeups[i]) { - if (clk_prepare(gpio_chips[i]->clock) == 0) - clk_enable(gpio_chips[i]->clock); - } + if (!wakeups[i]) + clk_prepare_enable(gpio_chips[i]->clock); __raw_writel(wakeups[i], pio + PIO_IDR); __raw_writel(backups[i], pio + PIO_IER); @@ -1354,6 +1420,9 @@ void at91_pinctrl_gpio_resume(void) static struct irq_chip gpio_irqchip = { .name = "GPIO", + .irq_ack = gpio_irq_ack, + .irq_startup = gpio_irq_startup, + .irq_shutdown = gpio_irq_shutdown, .irq_disable = gpio_irq_mask, .irq_mask = gpio_irq_mask, .irq_unmask = gpio_irq_unmask, @@ -1363,9 +1432,11 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct irq_chip *chip = irq_desc_get_chip(desc); - struct irq_data *idata = irq_desc_get_irq_data(desc); - struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); + struct irq_chip *chip = irq_get_chip(irq); + struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); + struct at91_gpio_chip *at91_gpio = container_of(gpio_chip, + struct at91_gpio_chip, chip); + void __iomem *pio = at91_gpio->regbase; unsigned long isr; int n; @@ -1373,7 +1444,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) chained_irq_enter(chip, desc); for (;;) { /* Reading ISR acks pending (edge triggered) GPIO interrupts. - * When there none are pending, we're finished unless we need + * When there are none pending, we're finished unless we need * to process multiple banks (like ID_PIOCDE on sam9263). */ isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); @@ -1382,78 +1453,25 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) break; at91_gpio = at91_gpio->next; pio = at91_gpio->regbase; + gpio_chip = &at91_gpio->chip; continue; } for_each_set_bit(n, &isr, BITS_PER_LONG) { - generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); + generic_handle_irq(irq_find_mapping( + gpio_chip->irqdomain, n)); } } chained_irq_exit(chip, desc); /* now it may re-trigger */ } -/* - * This lock class tells lockdep that GPIO irqs are in a different - * category than their parents, so it won't report false recursion. - */ -static struct lock_class_key gpio_lock_class; - -static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct at91_gpio_chip *at91_gpio = h->host_data; - - irq_set_lockdep_class(virq, &gpio_lock_class); - - /* - * Can use the "simple" and not "edge" handler since it's - * shorter, and the AIC handles interrupts sanely. - */ - irq_set_chip_and_handler(virq, &gpio_irqchip, - handle_simple_irq); - set_irq_flags(virq, IRQF_VALID); - irq_set_chip_data(virq, at91_gpio); - - return 0; -} - -static int at91_gpio_irq_domain_xlate(struct irq_domain *d, - struct device_node *ctrlr, - const u32 *intspec, unsigned int intsize, - irq_hw_number_t *out_hwirq, - unsigned int *out_type) -{ - struct at91_gpio_chip *at91_gpio = d->host_data; - int ret; - int pin = at91_gpio->chip.base + intspec[0]; - - if (WARN_ON(intsize < 2)) - return -EINVAL; - *out_hwirq = intspec[0]; - *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; - - ret = gpio_request(pin, ctrlr->full_name); - if (ret) - return ret; - - ret = gpio_direction_input(pin); - if (ret) - return ret; - - return 0; -} - -static struct irq_domain_ops at91_gpio_ops = { - .map = at91_gpio_irq_map, - .xlate = at91_gpio_irq_domain_xlate, -}; - static int at91_gpio_of_irq_setup(struct device_node *node, struct at91_gpio_chip *at91_gpio) { - struct at91_gpio_chip *prev = NULL; + struct at91_gpio_chip *prev = NULL; struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); + int ret; at91_gpio->pioc_hwirq = irqd_to_hwirq(d); @@ -1463,10 +1481,17 @@ static int at91_gpio_of_irq_setup(struct device_node *node, /* Disable irqs of this PIO controller */ writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); - /* Setup irq domain */ - at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, - &at91_gpio_ops, at91_gpio); - if (!at91_gpio->domain) + /* + * Let the generic code handle this edge IRQ, the the chained + * handler will perform the actual work of handling the parent + * interrupt. + */ + ret = gpiochip_irqchip_add(&at91_gpio->chip, + &gpio_irqchip, + 0, + handle_edge_irq, + IRQ_TYPE_EDGE_BOTH); + if (ret) panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", at91_gpio->pioc_idx); @@ -1474,15 +1499,18 @@ static int at91_gpio_of_irq_setup(struct device_node *node, if (at91_gpio->pioc_idx) prev = gpio_chips[at91_gpio->pioc_idx - 1]; - /* The toplevel handler handles one bank of GPIOs, except - * on some SoC it can handles up to three... + /* The top level handler handles one bank of GPIOs, except + * on some SoC it can handle up to three... * We only set up the handler for the first of the list. */ if (prev && prev->next == at91_gpio) return 0; - irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); - irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); + /* Then register the chain on the parent IRQ */ + gpiochip_set_chained_irqchip(&at91_gpio->chip, + &gpio_irqchip, + at91_gpio->pioc_virq, + gpio_irq_handler); return 0; } @@ -1491,13 +1519,13 @@ static int at91_gpio_of_irq_setup(struct device_node *node, static struct gpio_chip at91_gpio_template = { .request = at91_gpio_request, .free = at91_gpio_free, + .get_direction = at91_gpio_get_direction, .direction_input = at91_gpio_direction_input, .get = at91_gpio_get, .direction_output = at91_gpio_direction_output, .set = at91_gpio_set, - .to_irq = at91_gpio_to_irq, .dbg_show = at91_gpio_dbg_show, - .can_sleep = 0, + .can_sleep = false, .ngpio = MAX_NB_GPIO_PER_BANK, }; @@ -1544,12 +1572,6 @@ static int at91_gpio_probe(struct platform_device *pdev) goto err; } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - ret = -ENOENT; - goto err; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { ret = irq; @@ -1562,6 +1584,7 @@ static int at91_gpio_probe(struct platform_device *pdev) goto err; } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(at91_chip->regbase)) { ret = PTR_ERR(at91_chip->regbase); @@ -1655,7 +1678,7 @@ static struct platform_driver at91_gpio_driver = { .driver = { .name = "gpio-at91", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(at91_gpio_of_match), + .of_match_table = at91_gpio_of_match, }, .probe = at91_gpio_probe, }; @@ -1664,7 +1687,7 @@ static struct platform_driver at91_pinctrl_driver = { .driver = { .name = "pinctrl-at91", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(at91_pinctrl_of_match), + .of_match_table = at91_pinctrl_of_match, }, .probe = at91_pinctrl_probe, .remove = at91_pinctrl_remove, diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c new file mode 100644 index 00000000000..975572e2f26 --- /dev/null +++ b/drivers/pinctrl/pinctrl-baytrail.c @@ -0,0 +1,656 @@ +/* + * Pinctrl GPIO driver for Intel Baytrail + * Copyright (c) 2012-2013, Intel Corporation. + * + * Author: Mathias Nyman <mathias.nyman@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/bitops.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/irqdomain.h> +#include <linux/acpi.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/io.h> +#include <linux/pm_runtime.h> +#include <linux/pinctrl/pinctrl.h> + +/* memory mapped register offsets */ +#define BYT_CONF0_REG 0x000 +#define BYT_CONF1_REG 0x004 +#define BYT_VAL_REG 0x008 +#define BYT_DFT_REG 0x00c +#define BYT_INT_STAT_REG 0x800 + +/* BYT_CONF0_REG register bits */ +#define BYT_IODEN BIT(31) +#define BYT_TRIG_NEG BIT(26) +#define BYT_TRIG_POS BIT(25) +#define BYT_TRIG_LVL BIT(24) +#define BYT_PULL_STR_SHIFT 9 +#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_ASSIGN_SHIFT 7 +#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT) +#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) +#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) +#define BYT_PIN_MUX 0x07 + +/* BYT_VAL_REG register bits */ +#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ +#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ +#define BYT_LEVEL BIT(0) + +#define BYT_DIR_MASK (BIT(1) | BIT(2)) +#define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24)) + +#define BYT_NGPIO_SCORE 102 +#define BYT_NGPIO_NCORE 28 +#define BYT_NGPIO_SUS 44 + +#define BYT_SCORE_ACPI_UID "1" +#define BYT_NCORE_ACPI_UID "2" +#define BYT_SUS_ACPI_UID "3" + +/* + * Baytrail gpio controller consist of three separate sub-controllers called + * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID. + * + * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does + * _not_ correspond to the first gpio register at controller's gpio base. + * There is no logic or pattern in mapping gpio numbers to registers (pads) so + * each sub-controller needs to have its own mapping table + */ + +/* score_pins[gpio_nr] = pad_nr */ + +static unsigned const score_pins[BYT_NGPIO_SCORE] = { + 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, + 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, + 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, + 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, + 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, + 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, + 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, + 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, + 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, + 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, + 97, 100, +}; + +static unsigned const ncore_pins[BYT_NGPIO_NCORE] = { + 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, + 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, + 3, 6, 10, 13, 2, 5, 9, 7, +}; + +static unsigned const sus_pins[BYT_NGPIO_SUS] = { + 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, + 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, + 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, + 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, + 52, 53, 59, 40, +}; + +static struct pinctrl_gpio_range byt_ranges[] = { + { + .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */ + .npins = BYT_NGPIO_SCORE, + .pins = score_pins, + }, + { + .name = BYT_NCORE_ACPI_UID, + .npins = BYT_NGPIO_NCORE, + .pins = ncore_pins, + }, + { + .name = BYT_SUS_ACPI_UID, + .npins = BYT_NGPIO_SUS, + .pins = sus_pins, + }, + { + }, +}; + +struct byt_gpio { + struct gpio_chip chip; + struct irq_domain *domain; + struct platform_device *pdev; + spinlock_t lock; + void __iomem *reg_base; + struct pinctrl_gpio_range *range; +}; + +#define to_byt_gpio(c) container_of(c, struct byt_gpio, chip) + +static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset, + int reg) +{ + struct byt_gpio *vg = to_byt_gpio(chip); + u32 reg_offset; + + if (reg == BYT_INT_STAT_REG) + reg_offset = (offset / 32) * 4; + else + reg_offset = vg->range->pins[offset] * 16; + + return vg->reg_base + reg_offset + reg; +} + +static bool is_special_pin(struct byt_gpio *vg, unsigned offset) +{ + /* SCORE pin 92-93 */ + if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) && + offset >= 92 && offset <= 93) + return true; + + /* SUS pin 11-21 */ + if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) && + offset >= 11 && offset <= 21) + return true; + + return false; +} + +static int byt_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct byt_gpio *vg = to_byt_gpio(chip); + void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG); + u32 value; + bool special; + + /* + * In most cases, func pin mux 000 means GPIO function. + * But, some pins may have func pin mux 001 represents + * GPIO function. Only allow user to export pin with + * func pin mux preset as GPIO function by BIOS/FW. + */ + value = readl(reg) & BYT_PIN_MUX; + special = is_special_pin(vg, offset); + if ((special && value != 1) || (!special && value)) { + dev_err(&vg->pdev->dev, + "pin %u cannot be used as GPIO.\n", offset); + return -EINVAL; + } + + pm_runtime_get(&vg->pdev->dev); + + return 0; +} + +static void byt_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct byt_gpio *vg = to_byt_gpio(chip); + void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); + u32 value; + + /* clear interrupt triggering */ + value = readl(reg); + value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + writel(value, reg); + + pm_runtime_put(&vg->pdev->dev); +} + +static int byt_irq_type(struct irq_data *d, unsigned type) +{ + struct byt_gpio *vg = irq_data_get_irq_chip_data(d); + u32 offset = irqd_to_hwirq(d); + u32 value; + unsigned long flags; + void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); + + if (offset >= vg->chip.ngpio) + return -EINVAL; + + spin_lock_irqsave(&vg->lock, flags); + value = readl(reg); + + /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits + * are used to indicate high and low level triggering + */ + value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + value |= BYT_TRIG_LVL; + case IRQ_TYPE_EDGE_RISING: + value |= BYT_TRIG_POS; + break; + case IRQ_TYPE_LEVEL_LOW: + value |= BYT_TRIG_LVL; + case IRQ_TYPE_EDGE_FALLING: + value |= BYT_TRIG_NEG; + break; + case IRQ_TYPE_EDGE_BOTH: + value |= (BYT_TRIG_NEG | BYT_TRIG_POS); + break; + } + writel(value, reg); + + spin_unlock_irqrestore(&vg->lock, flags); + + return 0; +} + +static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); + return readl(reg) & BYT_LEVEL; +} + +static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct byt_gpio *vg = to_byt_gpio(chip); + void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); + unsigned long flags; + u32 old_val; + + spin_lock_irqsave(&vg->lock, flags); + + old_val = readl(reg); + + if (value) + writel(old_val | BYT_LEVEL, reg); + else + writel(old_val & ~BYT_LEVEL, reg); + + spin_unlock_irqrestore(&vg->lock, flags); +} + +static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct byt_gpio *vg = to_byt_gpio(chip); + void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); + unsigned long flags; + u32 value; + + spin_lock_irqsave(&vg->lock, flags); + + value = readl(reg) | BYT_DIR_MASK; + value &= ~BYT_INPUT_EN; /* active low */ + writel(value, reg); + + spin_unlock_irqrestore(&vg->lock, flags); + + return 0; +} + +static int byt_gpio_direction_output(struct gpio_chip *chip, + unsigned gpio, int value) +{ + struct byt_gpio *vg = to_byt_gpio(chip); + void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG); + unsigned long flags; + u32 reg_val; + + spin_lock_irqsave(&vg->lock, flags); + + reg_val = readl(reg) | BYT_DIR_MASK; + reg_val &= ~BYT_OUTPUT_EN; + + if (value) + writel(reg_val | BYT_LEVEL, reg); + else + writel(reg_val & ~BYT_LEVEL, reg); + + spin_unlock_irqrestore(&vg->lock, flags); + + return 0; +} + +static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + struct byt_gpio *vg = to_byt_gpio(chip); + int i; + unsigned long flags; + u32 conf0, val, offs; + + spin_lock_irqsave(&vg->lock, flags); + + for (i = 0; i < vg->chip.ngpio; i++) { + const char *pull_str = NULL; + const char *pull = NULL; + const char *label; + offs = vg->range->pins[i] * 16; + conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); + val = readl(vg->reg_base + offs + BYT_VAL_REG); + + label = gpiochip_is_requested(chip, i); + if (!label) + label = "Unrequested"; + + switch (conf0 & BYT_PULL_ASSIGN_MASK) { + case BYT_PULL_ASSIGN_UP: + pull = "up"; + break; + case BYT_PULL_ASSIGN_DOWN: + pull = "down"; + break; + } + + switch (conf0 & BYT_PULL_STR_MASK) { + case BYT_PULL_STR_2K: + pull_str = "2k"; + break; + case BYT_PULL_STR_10K: + pull_str = "10k"; + break; + case BYT_PULL_STR_20K: + pull_str = "20k"; + break; + case BYT_PULL_STR_40K: + pull_str = "40k"; + break; + } + + seq_printf(s, + " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", + i, + label, + val & BYT_INPUT_EN ? " " : "in", + val & BYT_OUTPUT_EN ? " " : "out", + val & BYT_LEVEL ? "hi" : "lo", + vg->range->pins[i], offs, + conf0 & 0x7, + conf0 & BYT_TRIG_NEG ? " fall" : " ", + conf0 & BYT_TRIG_POS ? " rise" : " ", + conf0 & BYT_TRIG_LVL ? " level" : " "); + + if (pull && pull_str) + seq_printf(s, " %-4s %-3s", pull, pull_str); + else + seq_puts(s, " "); + + if (conf0 & BYT_IODEN) + seq_puts(s, " open-drain"); + + seq_puts(s, "\n"); + } + spin_unlock_irqrestore(&vg->lock, flags); +} + +static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct byt_gpio *vg = to_byt_gpio(chip); + return irq_create_mapping(vg->domain, offset); +} + +static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +{ + struct irq_data *data = irq_desc_get_irq_data(desc); + struct byt_gpio *vg = irq_data_get_irq_handler_data(data); + struct irq_chip *chip = irq_data_get_irq_chip(data); + u32 base, pin, mask; + void __iomem *reg; + u32 pending; + unsigned virq; + int looplimit = 0; + + /* check from GPIO controller which pin triggered the interrupt */ + for (base = 0; base < vg->chip.ngpio; base += 32) { + + reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); + + while ((pending = readl(reg))) { + pin = __ffs(pending); + mask = BIT(pin); + /* Clear before handling so we can't lose an edge */ + writel(mask, reg); + + virq = irq_find_mapping(vg->domain, base + pin); + generic_handle_irq(virq); + + /* In case bios or user sets triggering incorretly a pin + * might remain in "interrupt triggered" state. + */ + if (looplimit++ > 32) { + dev_err(&vg->pdev->dev, + "Gpio %d interrupt flood, disabling\n", + base + pin); + + reg = byt_gpio_reg(&vg->chip, base + pin, + BYT_CONF0_REG); + mask = readl(reg); + mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS | + BYT_TRIG_LVL); + writel(mask, reg); + mask = readl(reg); /* flush */ + break; + } + } + } + chip->irq_eoi(data); +} + +static void byt_irq_unmask(struct irq_data *d) +{ +} + +static void byt_irq_mask(struct irq_data *d) +{ +} + +static int byt_irq_reqres(struct irq_data *d) +{ + struct byt_gpio *vg = irq_data_get_irq_chip_data(d); + + if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) { + dev_err(vg->chip.dev, + "unable to lock HW IRQ %lu for IRQ\n", + irqd_to_hwirq(d)); + return -EINVAL; + } + return 0; +} + +static void byt_irq_relres(struct irq_data *d) +{ + struct byt_gpio *vg = irq_data_get_irq_chip_data(d); + + gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d)); +} + +static struct irq_chip byt_irqchip = { + .name = "BYT-GPIO", + .irq_mask = byt_irq_mask, + .irq_unmask = byt_irq_unmask, + .irq_set_type = byt_irq_type, + .irq_request_resources = byt_irq_reqres, + .irq_release_resources = byt_irq_relres, +}; + +static void byt_gpio_irq_init_hw(struct byt_gpio *vg) +{ + void __iomem *reg; + u32 base, value; + + /* clear interrupt status trigger registers */ + for (base = 0; base < vg->chip.ngpio; base += 32) { + reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); + writel(0xffffffff, reg); + /* make sure trigger bits are cleared, if not then a pin + might be misconfigured in bios */ + value = readl(reg); + if (value) + dev_err(&vg->pdev->dev, + "GPIO interrupt error, pins misconfigured\n"); + } +} + +static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + struct byt_gpio *vg = d->host_data; + + irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq, + "demux"); + irq_set_chip_data(virq, vg); + irq_set_irq_type(virq, IRQ_TYPE_NONE); + + return 0; +} + +static const struct irq_domain_ops byt_gpio_irq_ops = { + .map = byt_gpio_irq_map, +}; + +static int byt_gpio_probe(struct platform_device *pdev) +{ + struct byt_gpio *vg; + struct gpio_chip *gc; + struct resource *mem_rc, *irq_rc; + struct device *dev = &pdev->dev; + struct acpi_device *acpi_dev; + struct pinctrl_gpio_range *range; + acpi_handle handle = ACPI_HANDLE(dev); + unsigned hwirq; + int ret; + + if (acpi_bus_get_device(handle, &acpi_dev)) + return -ENODEV; + + vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL); + if (!vg) { + dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n"); + return -ENOMEM; + } + + for (range = byt_ranges; range->name; range++) { + if (!strcmp(acpi_dev->pnp.unique_id, range->name)) { + vg->chip.ngpio = range->npins; + vg->range = range; + break; + } + } + + if (!vg->chip.ngpio || !vg->range) + return -ENODEV; + + vg->pdev = pdev; + platform_set_drvdata(pdev, vg); + + mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); + vg->reg_base = devm_ioremap_resource(dev, mem_rc); + if (IS_ERR(vg->reg_base)) + return PTR_ERR(vg->reg_base); + + spin_lock_init(&vg->lock); + + gc = &vg->chip; + gc->label = dev_name(&pdev->dev); + gc->owner = THIS_MODULE; + gc->request = byt_gpio_request; + gc->free = byt_gpio_free; + gc->direction_input = byt_gpio_direction_input; + gc->direction_output = byt_gpio_direction_output; + gc->get = byt_gpio_get; + gc->set = byt_gpio_set; + gc->dbg_show = byt_gpio_dbg_show; + gc->base = -1; + gc->can_sleep = false; + gc->dev = dev; + + /* set up interrupts */ + irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (irq_rc && irq_rc->start) { + hwirq = irq_rc->start; + gc->to_irq = byt_gpio_to_irq; + + vg->domain = irq_domain_add_linear(NULL, gc->ngpio, + &byt_gpio_irq_ops, vg); + if (!vg->domain) + return -ENXIO; + + byt_gpio_irq_init_hw(vg); + + irq_set_handler_data(hwirq, vg); + irq_set_chained_handler(hwirq, byt_gpio_irq_handler); + } + + ret = gpiochip_add(gc); + if (ret) { + dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); + return ret; + } + + pm_runtime_enable(dev); + + return 0; +} + +static int byt_gpio_runtime_suspend(struct device *dev) +{ + return 0; +} + +static int byt_gpio_runtime_resume(struct device *dev) +{ + return 0; +} + +static const struct dev_pm_ops byt_gpio_pm_ops = { + .runtime_suspend = byt_gpio_runtime_suspend, + .runtime_resume = byt_gpio_runtime_resume, +}; + +static const struct acpi_device_id byt_gpio_acpi_match[] = { + { "INT33B2", 0 }, + { "INT33FC", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); + +static int byt_gpio_remove(struct platform_device *pdev) +{ + struct byt_gpio *vg = platform_get_drvdata(pdev); + int err; + + pm_runtime_disable(&pdev->dev); + err = gpiochip_remove(&vg->chip); + if (err) + dev_warn(&pdev->dev, "failed to remove gpio_chip.\n"); + + return 0; +} + +static struct platform_driver byt_gpio_driver = { + .probe = byt_gpio_probe, + .remove = byt_gpio_remove, + .driver = { + .name = "byt_gpio", + .owner = THIS_MODULE, + .pm = &byt_gpio_pm_ops, + .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), + }, +}; + +static int __init byt_gpio_init(void) +{ + return platform_driver_register(&byt_gpio_driver); +} + +subsys_initcall(byt_gpio_init); diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/pinctrl-bcm281xx.c new file mode 100644 index 00000000000..3bed792b2c0 --- /dev/null +++ b/drivers/pinctrl/pinctrl-bcm281xx.c @@ -0,0 +1,1461 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include "core.h" +#include "pinctrl-utils.h" + +/* BCM281XX Pin Control Registers Definitions */ + +/* Function Select bits are the same for all pin control registers */ +#define BCM281XX_PIN_REG_F_SEL_MASK 0x0700 +#define BCM281XX_PIN_REG_F_SEL_SHIFT 8 + +/* Standard pin register */ +#define BCM281XX_STD_PIN_REG_DRV_STR_MASK 0x0007 +#define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT 0 +#define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008 +#define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT 3 +#define BCM281XX_STD_PIN_REG_SLEW_MASK 0x0010 +#define BCM281XX_STD_PIN_REG_SLEW_SHIFT 4 +#define BCM281XX_STD_PIN_REG_PULL_UP_MASK 0x0020 +#define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT 5 +#define BCM281XX_STD_PIN_REG_PULL_DN_MASK 0x0040 +#define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT 6 +#define BCM281XX_STD_PIN_REG_HYST_MASK 0x0080 +#define BCM281XX_STD_PIN_REG_HYST_SHIFT 7 + +/* I2C pin register */ +#define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004 +#define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT 2 +#define BCM281XX_I2C_PIN_REG_SLEW_MASK 0x0008 +#define BCM281XX_I2C_PIN_REG_SLEW_SHIFT 3 +#define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070 +#define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT 4 + +/* HDMI pin register */ +#define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008 +#define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT 3 +#define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010 +#define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4 + +/** + * bcm281xx_pin_type - types of pin register + */ +enum bcm281xx_pin_type { + BCM281XX_PIN_TYPE_UNKNOWN = 0, + BCM281XX_PIN_TYPE_STD, + BCM281XX_PIN_TYPE_I2C, + BCM281XX_PIN_TYPE_HDMI, +}; + +static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD; +static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C; +static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI; + +/** + * bcm281xx_pin_function- define pin function + */ +struct bcm281xx_pin_function { + const char *name; + const char * const *groups; + const unsigned ngroups; +}; + +/** + * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data + * @reg_base - base of pinctrl registers + */ +struct bcm281xx_pinctrl_data { + void __iomem *reg_base; + + /* List of all pins */ + const struct pinctrl_pin_desc *pins; + const unsigned npins; + + const struct bcm281xx_pin_function *functions; + const unsigned nfunctions; + + struct regmap *regmap; +}; + +/* + * Pin number definition. The order here must be the same as defined in the + * PADCTRLREG block in the RDB. + */ +#define BCM281XX_PIN_ADCSYNC 0 +#define BCM281XX_PIN_BAT_RM 1 +#define BCM281XX_PIN_BSC1_SCL 2 +#define BCM281XX_PIN_BSC1_SDA 3 +#define BCM281XX_PIN_BSC2_SCL 4 +#define BCM281XX_PIN_BSC2_SDA 5 +#define BCM281XX_PIN_CLASSGPWR 6 +#define BCM281XX_PIN_CLK_CX8 7 +#define BCM281XX_PIN_CLKOUT_0 8 +#define BCM281XX_PIN_CLKOUT_1 9 +#define BCM281XX_PIN_CLKOUT_2 10 +#define BCM281XX_PIN_CLKOUT_3 11 +#define BCM281XX_PIN_CLKREQ_IN_0 12 +#define BCM281XX_PIN_CLKREQ_IN_1 13 +#define BCM281XX_PIN_CWS_SYS_REQ1 14 +#define BCM281XX_PIN_CWS_SYS_REQ2 15 +#define BCM281XX_PIN_CWS_SYS_REQ3 16 +#define BCM281XX_PIN_DIGMIC1_CLK 17 +#define BCM281XX_PIN_DIGMIC1_DQ 18 +#define BCM281XX_PIN_DIGMIC2_CLK 19 +#define BCM281XX_PIN_DIGMIC2_DQ 20 +#define BCM281XX_PIN_GPEN13 21 +#define BCM281XX_PIN_GPEN14 22 +#define BCM281XX_PIN_GPEN15 23 +#define BCM281XX_PIN_GPIO00 24 +#define BCM281XX_PIN_GPIO01 25 +#define BCM281XX_PIN_GPIO02 26 +#define BCM281XX_PIN_GPIO03 27 +#define BCM281XX_PIN_GPIO04 28 +#define BCM281XX_PIN_GPIO05 29 +#define BCM281XX_PIN_GPIO06 30 +#define BCM281XX_PIN_GPIO07 31 +#define BCM281XX_PIN_GPIO08 32 +#define BCM281XX_PIN_GPIO09 33 +#define BCM281XX_PIN_GPIO10 34 +#define BCM281XX_PIN_GPIO11 35 +#define BCM281XX_PIN_GPIO12 36 +#define BCM281XX_PIN_GPIO13 37 +#define BCM281XX_PIN_GPIO14 38 +#define BCM281XX_PIN_GPS_PABLANK 39 +#define BCM281XX_PIN_GPS_TMARK 40 +#define BCM281XX_PIN_HDMI_SCL 41 +#define BCM281XX_PIN_HDMI_SDA 42 +#define BCM281XX_PIN_IC_DM 43 +#define BCM281XX_PIN_IC_DP 44 +#define BCM281XX_PIN_KP_COL_IP_0 45 +#define BCM281XX_PIN_KP_COL_IP_1 46 +#define BCM281XX_PIN_KP_COL_IP_2 47 +#define BCM281XX_PIN_KP_COL_IP_3 48 +#define BCM281XX_PIN_KP_ROW_OP_0 49 +#define BCM281XX_PIN_KP_ROW_OP_1 50 +#define BCM281XX_PIN_KP_ROW_OP_2 51 +#define BCM281XX_PIN_KP_ROW_OP_3 52 +#define BCM281XX_PIN_LCD_B_0 53 +#define BCM281XX_PIN_LCD_B_1 54 +#define BCM281XX_PIN_LCD_B_2 55 +#define BCM281XX_PIN_LCD_B_3 56 +#define BCM281XX_PIN_LCD_B_4 57 +#define BCM281XX_PIN_LCD_B_5 58 +#define BCM281XX_PIN_LCD_B_6 59 +#define BCM281XX_PIN_LCD_B_7 60 +#define BCM281XX_PIN_LCD_G_0 61 +#define BCM281XX_PIN_LCD_G_1 62 +#define BCM281XX_PIN_LCD_G_2 63 +#define BCM281XX_PIN_LCD_G_3 64 +#define BCM281XX_PIN_LCD_G_4 65 +#define BCM281XX_PIN_LCD_G_5 66 +#define BCM281XX_PIN_LCD_G_6 67 +#define BCM281XX_PIN_LCD_G_7 68 +#define BCM281XX_PIN_LCD_HSYNC 69 +#define BCM281XX_PIN_LCD_OE 70 +#define BCM281XX_PIN_LCD_PCLK 71 +#define BCM281XX_PIN_LCD_R_0 72 +#define BCM281XX_PIN_LCD_R_1 73 +#define BCM281XX_PIN_LCD_R_2 74 +#define BCM281XX_PIN_LCD_R_3 75 +#define BCM281XX_PIN_LCD_R_4 76 +#define BCM281XX_PIN_LCD_R_5 77 +#define BCM281XX_PIN_LCD_R_6 78 +#define BCM281XX_PIN_LCD_R_7 79 +#define BCM281XX_PIN_LCD_VSYNC 80 +#define BCM281XX_PIN_MDMGPIO0 81 +#define BCM281XX_PIN_MDMGPIO1 82 +#define BCM281XX_PIN_MDMGPIO2 83 +#define BCM281XX_PIN_MDMGPIO3 84 +#define BCM281XX_PIN_MDMGPIO4 85 +#define BCM281XX_PIN_MDMGPIO5 86 +#define BCM281XX_PIN_MDMGPIO6 87 +#define BCM281XX_PIN_MDMGPIO7 88 +#define BCM281XX_PIN_MDMGPIO8 89 +#define BCM281XX_PIN_MPHI_DATA_0 90 +#define BCM281XX_PIN_MPHI_DATA_1 91 +#define BCM281XX_PIN_MPHI_DATA_2 92 +#define BCM281XX_PIN_MPHI_DATA_3 93 +#define BCM281XX_PIN_MPHI_DATA_4 94 +#define BCM281XX_PIN_MPHI_DATA_5 95 +#define BCM281XX_PIN_MPHI_DATA_6 96 +#define BCM281XX_PIN_MPHI_DATA_7 97 +#define BCM281XX_PIN_MPHI_DATA_8 98 +#define BCM281XX_PIN_MPHI_DATA_9 99 +#define BCM281XX_PIN_MPHI_DATA_10 100 +#define BCM281XX_PIN_MPHI_DATA_11 101 +#define BCM281XX_PIN_MPHI_DATA_12 102 +#define BCM281XX_PIN_MPHI_DATA_13 103 +#define BCM281XX_PIN_MPHI_DATA_14 104 +#define BCM281XX_PIN_MPHI_DATA_15 105 +#define BCM281XX_PIN_MPHI_HA0 106 +#define BCM281XX_PIN_MPHI_HAT0 107 +#define BCM281XX_PIN_MPHI_HAT1 108 +#define BCM281XX_PIN_MPHI_HCE0_N 109 +#define BCM281XX_PIN_MPHI_HCE1_N 110 +#define BCM281XX_PIN_MPHI_HRD_N 111 +#define BCM281XX_PIN_MPHI_HWR_N 112 +#define BCM281XX_PIN_MPHI_RUN0 113 +#define BCM281XX_PIN_MPHI_RUN1 114 +#define BCM281XX_PIN_MTX_SCAN_CLK 115 +#define BCM281XX_PIN_MTX_SCAN_DATA 116 +#define BCM281XX_PIN_NAND_AD_0 117 +#define BCM281XX_PIN_NAND_AD_1 118 +#define BCM281XX_PIN_NAND_AD_2 119 +#define BCM281XX_PIN_NAND_AD_3 120 +#define BCM281XX_PIN_NAND_AD_4 121 +#define BCM281XX_PIN_NAND_AD_5 122 +#define BCM281XX_PIN_NAND_AD_6 123 +#define BCM281XX_PIN_NAND_AD_7 124 +#define BCM281XX_PIN_NAND_ALE 125 +#define BCM281XX_PIN_NAND_CEN_0 126 +#define BCM281XX_PIN_NAND_CEN_1 127 +#define BCM281XX_PIN_NAND_CLE 128 +#define BCM281XX_PIN_NAND_OEN 129 +#define BCM281XX_PIN_NAND_RDY_0 130 +#define BCM281XX_PIN_NAND_RDY_1 131 +#define BCM281XX_PIN_NAND_WEN 132 +#define BCM281XX_PIN_NAND_WP 133 +#define BCM281XX_PIN_PC1 134 +#define BCM281XX_PIN_PC2 135 +#define BCM281XX_PIN_PMU_INT 136 +#define BCM281XX_PIN_PMU_SCL 137 +#define BCM281XX_PIN_PMU_SDA 138 +#define BCM281XX_PIN_RFST2G_MTSLOTEN3G 139 +#define BCM281XX_PIN_RGMII_0_RX_CTL 140 +#define BCM281XX_PIN_RGMII_0_RXC 141 +#define BCM281XX_PIN_RGMII_0_RXD_0 142 +#define BCM281XX_PIN_RGMII_0_RXD_1 143 +#define BCM281XX_PIN_RGMII_0_RXD_2 144 +#define BCM281XX_PIN_RGMII_0_RXD_3 145 +#define BCM281XX_PIN_RGMII_0_TX_CTL 146 +#define BCM281XX_PIN_RGMII_0_TXC 147 +#define BCM281XX_PIN_RGMII_0_TXD_0 148 +#define BCM281XX_PIN_RGMII_0_TXD_1 149 +#define BCM281XX_PIN_RGMII_0_TXD_2 150 +#define BCM281XX_PIN_RGMII_0_TXD_3 151 +#define BCM281XX_PIN_RGMII_1_RX_CTL 152 +#define BCM281XX_PIN_RGMII_1_RXC 153 +#define BCM281XX_PIN_RGMII_1_RXD_0 154 +#define BCM281XX_PIN_RGMII_1_RXD_1 155 +#define BCM281XX_PIN_RGMII_1_RXD_2 156 +#define BCM281XX_PIN_RGMII_1_RXD_3 157 +#define BCM281XX_PIN_RGMII_1_TX_CTL 158 +#define BCM281XX_PIN_RGMII_1_TXC 159 +#define BCM281XX_PIN_RGMII_1_TXD_0 160 +#define BCM281XX_PIN_RGMII_1_TXD_1 161 +#define BCM281XX_PIN_RGMII_1_TXD_2 162 +#define BCM281XX_PIN_RGMII_1_TXD_3 163 +#define BCM281XX_PIN_RGMII_GPIO_0 164 +#define BCM281XX_PIN_RGMII_GPIO_1 165 +#define BCM281XX_PIN_RGMII_GPIO_2 166 +#define BCM281XX_PIN_RGMII_GPIO_3 167 +#define BCM281XX_PIN_RTXDATA2G_TXDATA3G1 168 +#define BCM281XX_PIN_RTXEN2G_TXDATA3G2 169 +#define BCM281XX_PIN_RXDATA3G0 170 +#define BCM281XX_PIN_RXDATA3G1 171 +#define BCM281XX_PIN_RXDATA3G2 172 +#define BCM281XX_PIN_SDIO1_CLK 173 +#define BCM281XX_PIN_SDIO1_CMD 174 +#define BCM281XX_PIN_SDIO1_DATA_0 175 +#define BCM281XX_PIN_SDIO1_DATA_1 176 +#define BCM281XX_PIN_SDIO1_DATA_2 177 +#define BCM281XX_PIN_SDIO1_DATA_3 178 +#define BCM281XX_PIN_SDIO4_CLK 179 +#define BCM281XX_PIN_SDIO4_CMD 180 +#define BCM281XX_PIN_SDIO4_DATA_0 181 +#define BCM281XX_PIN_SDIO4_DATA_1 182 +#define BCM281XX_PIN_SDIO4_DATA_2 183 +#define BCM281XX_PIN_SDIO4_DATA_3 184 +#define BCM281XX_PIN_SIM_CLK 185 +#define BCM281XX_PIN_SIM_DATA 186 +#define BCM281XX_PIN_SIM_DET 187 +#define BCM281XX_PIN_SIM_RESETN 188 +#define BCM281XX_PIN_SIM2_CLK 189 +#define BCM281XX_PIN_SIM2_DATA 190 +#define BCM281XX_PIN_SIM2_DET 191 +#define BCM281XX_PIN_SIM2_RESETN 192 +#define BCM281XX_PIN_SRI_C 193 +#define BCM281XX_PIN_SRI_D 194 +#define BCM281XX_PIN_SRI_E 195 +#define BCM281XX_PIN_SSP_EXTCLK 196 +#define BCM281XX_PIN_SSP0_CLK 197 +#define BCM281XX_PIN_SSP0_FS 198 +#define BCM281XX_PIN_SSP0_RXD 199 +#define BCM281XX_PIN_SSP0_TXD 200 +#define BCM281XX_PIN_SSP2_CLK 201 +#define BCM281XX_PIN_SSP2_FS_0 202 +#define BCM281XX_PIN_SSP2_FS_1 203 +#define BCM281XX_PIN_SSP2_FS_2 204 +#define BCM281XX_PIN_SSP2_FS_3 205 +#define BCM281XX_PIN_SSP2_RXD_0 206 +#define BCM281XX_PIN_SSP2_RXD_1 207 +#define BCM281XX_PIN_SSP2_TXD_0 208 +#define BCM281XX_PIN_SSP2_TXD_1 209 +#define BCM281XX_PIN_SSP3_CLK 210 +#define BCM281XX_PIN_SSP3_FS 211 +#define BCM281XX_PIN_SSP3_RXD 212 +#define BCM281XX_PIN_SSP3_TXD 213 +#define BCM281XX_PIN_SSP4_CLK 214 +#define BCM281XX_PIN_SSP4_FS 215 +#define BCM281XX_PIN_SSP4_RXD 216 +#define BCM281XX_PIN_SSP4_TXD 217 +#define BCM281XX_PIN_SSP5_CLK 218 +#define BCM281XX_PIN_SSP5_FS 219 +#define BCM281XX_PIN_SSP5_RXD 220 +#define BCM281XX_PIN_SSP5_TXD 221 +#define BCM281XX_PIN_SSP6_CLK 222 +#define BCM281XX_PIN_SSP6_FS 223 +#define BCM281XX_PIN_SSP6_RXD 224 +#define BCM281XX_PIN_SSP6_TXD 225 +#define BCM281XX_PIN_STAT_1 226 +#define BCM281XX_PIN_STAT_2 227 +#define BCM281XX_PIN_SYSCLKEN 228 +#define BCM281XX_PIN_TRACECLK 229 +#define BCM281XX_PIN_TRACEDT00 230 +#define BCM281XX_PIN_TRACEDT01 231 +#define BCM281XX_PIN_TRACEDT02 232 +#define BCM281XX_PIN_TRACEDT03 233 +#define BCM281XX_PIN_TRACEDT04 234 +#define BCM281XX_PIN_TRACEDT05 235 +#define BCM281XX_PIN_TRACEDT06 236 +#define BCM281XX_PIN_TRACEDT07 237 +#define BCM281XX_PIN_TRACEDT08 238 +#define BCM281XX_PIN_TRACEDT09 239 +#define BCM281XX_PIN_TRACEDT10 240 +#define BCM281XX_PIN_TRACEDT11 241 +#define BCM281XX_PIN_TRACEDT12 242 +#define BCM281XX_PIN_TRACEDT13 243 +#define BCM281XX_PIN_TRACEDT14 244 +#define BCM281XX_PIN_TRACEDT15 245 +#define BCM281XX_PIN_TXDATA3G0 246 +#define BCM281XX_PIN_TXPWRIND 247 +#define BCM281XX_PIN_UARTB1_UCTS 248 +#define BCM281XX_PIN_UARTB1_URTS 249 +#define BCM281XX_PIN_UARTB1_URXD 250 +#define BCM281XX_PIN_UARTB1_UTXD 251 +#define BCM281XX_PIN_UARTB2_URXD 252 +#define BCM281XX_PIN_UARTB2_UTXD 253 +#define BCM281XX_PIN_UARTB3_UCTS 254 +#define BCM281XX_PIN_UARTB3_URTS 255 +#define BCM281XX_PIN_UARTB3_URXD 256 +#define BCM281XX_PIN_UARTB3_UTXD 257 +#define BCM281XX_PIN_UARTB4_UCTS 258 +#define BCM281XX_PIN_UARTB4_URTS 259 +#define BCM281XX_PIN_UARTB4_URXD 260 +#define BCM281XX_PIN_UARTB4_UTXD 261 +#define BCM281XX_PIN_VC_CAM1_SCL 262 +#define BCM281XX_PIN_VC_CAM1_SDA 263 +#define BCM281XX_PIN_VC_CAM2_SCL 264 +#define BCM281XX_PIN_VC_CAM2_SDA 265 +#define BCM281XX_PIN_VC_CAM3_SCL 266 +#define BCM281XX_PIN_VC_CAM3_SDA 267 + +#define BCM281XX_PIN_DESC(a, b, c) \ + { .number = a, .name = b, .drv_data = &c##_pin } + +/* + * Pin description definition. The order here must be the same as defined in + * the PADCTRLREG block in the RDB, since the pin number is used as an index + * into this array. + */ +static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = { + BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi), + BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi), + BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", + std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1, + "rtxdata2g_txdata3g1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", + std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std), + BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c), + BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c), +}; + +static const char * const bcm281xx_alt_groups[] = { + "adcsync", + "bat_rm", + "bsc1_scl", + "bsc1_sda", + "bsc2_scl", + "bsc2_sda", + "classgpwr", + "clk_cx8", + "clkout_0", + "clkout_1", + "clkout_2", + "clkout_3", + "clkreq_in_0", + "clkreq_in_1", + "cws_sys_req1", + "cws_sys_req2", + "cws_sys_req3", + "digmic1_clk", + "digmic1_dq", + "digmic2_clk", + "digmic2_dq", + "gpen13", + "gpen14", + "gpen15", + "gpio00", + "gpio01", + "gpio02", + "gpio03", + "gpio04", + "gpio05", + "gpio06", + "gpio07", + "gpio08", + "gpio09", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gps_pablank", + "gps_tmark", + "hdmi_scl", + "hdmi_sda", + "ic_dm", + "ic_dp", + "kp_col_ip_0", + "kp_col_ip_1", + "kp_col_ip_2", + "kp_col_ip_3", + "kp_row_op_0", + "kp_row_op_1", + "kp_row_op_2", + "kp_row_op_3", + "lcd_b_0", + "lcd_b_1", + "lcd_b_2", + "lcd_b_3", + "lcd_b_4", + "lcd_b_5", + "lcd_b_6", + "lcd_b_7", + "lcd_g_0", + "lcd_g_1", + "lcd_g_2", + "lcd_g_3", + "lcd_g_4", + "lcd_g_5", + "lcd_g_6", + "lcd_g_7", + "lcd_hsync", + "lcd_oe", + "lcd_pclk", + "lcd_r_0", + "lcd_r_1", + "lcd_r_2", + "lcd_r_3", + "lcd_r_4", + "lcd_r_5", + "lcd_r_6", + "lcd_r_7", + "lcd_vsync", + "mdmgpio0", + "mdmgpio1", + "mdmgpio2", + "mdmgpio3", + "mdmgpio4", + "mdmgpio5", + "mdmgpio6", + "mdmgpio7", + "mdmgpio8", + "mphi_data_0", + "mphi_data_1", + "mphi_data_2", + "mphi_data_3", + "mphi_data_4", + "mphi_data_5", + "mphi_data_6", + "mphi_data_7", + "mphi_data_8", + "mphi_data_9", + "mphi_data_10", + "mphi_data_11", + "mphi_data_12", + "mphi_data_13", + "mphi_data_14", + "mphi_data_15", + "mphi_ha0", + "mphi_hat0", + "mphi_hat1", + "mphi_hce0_n", + "mphi_hce1_n", + "mphi_hrd_n", + "mphi_hwr_n", + "mphi_run0", + "mphi_run1", + "mtx_scan_clk", + "mtx_scan_data", + "nand_ad_0", + "nand_ad_1", + "nand_ad_2", + "nand_ad_3", + "nand_ad_4", + "nand_ad_5", + "nand_ad_6", + "nand_ad_7", + "nand_ale", + "nand_cen_0", + "nand_cen_1", + "nand_cle", + "nand_oen", + "nand_rdy_0", + "nand_rdy_1", + "nand_wen", + "nand_wp", + "pc1", + "pc2", + "pmu_int", + "pmu_scl", + "pmu_sda", + "rfst2g_mtsloten3g", + "rgmii_0_rx_ctl", + "rgmii_0_rxc", + "rgmii_0_rxd_0", + "rgmii_0_rxd_1", + "rgmii_0_rxd_2", + "rgmii_0_rxd_3", + "rgmii_0_tx_ctl", + "rgmii_0_txc", + "rgmii_0_txd_0", + "rgmii_0_txd_1", + "rgmii_0_txd_2", + "rgmii_0_txd_3", + "rgmii_1_rx_ctl", + "rgmii_1_rxc", + "rgmii_1_rxd_0", + "rgmii_1_rxd_1", + "rgmii_1_rxd_2", + "rgmii_1_rxd_3", + "rgmii_1_tx_ctl", + "rgmii_1_txc", + "rgmii_1_txd_0", + "rgmii_1_txd_1", + "rgmii_1_txd_2", + "rgmii_1_txd_3", + "rgmii_gpio_0", + "rgmii_gpio_1", + "rgmii_gpio_2", + "rgmii_gpio_3", + "rtxdata2g_txdata3g1", + "rtxen2g_txdata3g2", + "rxdata3g0", + "rxdata3g1", + "rxdata3g2", + "sdio1_clk", + "sdio1_cmd", + "sdio1_data_0", + "sdio1_data_1", + "sdio1_data_2", + "sdio1_data_3", + "sdio4_clk", + "sdio4_cmd", + "sdio4_data_0", + "sdio4_data_1", + "sdio4_data_2", + "sdio4_data_3", + "sim_clk", + "sim_data", + "sim_det", + "sim_resetn", + "sim2_clk", + "sim2_data", + "sim2_det", + "sim2_resetn", + "sri_c", + "sri_d", + "sri_e", + "ssp_extclk", + "ssp0_clk", + "ssp0_fs", + "ssp0_rxd", + "ssp0_txd", + "ssp2_clk", + "ssp2_fs_0", + "ssp2_fs_1", + "ssp2_fs_2", + "ssp2_fs_3", + "ssp2_rxd_0", + "ssp2_rxd_1", + "ssp2_txd_0", + "ssp2_txd_1", + "ssp3_clk", + "ssp3_fs", + "ssp3_rxd", + "ssp3_txd", + "ssp4_clk", + "ssp4_fs", + "ssp4_rxd", + "ssp4_txd", + "ssp5_clk", + "ssp5_fs", + "ssp5_rxd", + "ssp5_txd", + "ssp6_clk", + "ssp6_fs", + "ssp6_rxd", + "ssp6_txd", + "stat_1", + "stat_2", + "sysclken", + "traceclk", + "tracedt00", + "tracedt01", + "tracedt02", + "tracedt03", + "tracedt04", + "tracedt05", + "tracedt06", + "tracedt07", + "tracedt08", + "tracedt09", + "tracedt10", + "tracedt11", + "tracedt12", + "tracedt13", + "tracedt14", + "tracedt15", + "txdata3g0", + "txpwrind", + "uartb1_ucts", + "uartb1_urts", + "uartb1_urxd", + "uartb1_utxd", + "uartb2_urxd", + "uartb2_utxd", + "uartb3_ucts", + "uartb3_urts", + "uartb3_urxd", + "uartb3_utxd", + "uartb4_ucts", + "uartb4_urts", + "uartb4_urxd", + "uartb4_utxd", + "vc_cam1_scl", + "vc_cam1_sda", + "vc_cam2_scl", + "vc_cam2_sda", + "vc_cam3_scl", + "vc_cam3_sda", +}; + +/* Every pin can implement all ALT1-ALT4 functions */ +#define BCM281XX_PIN_FUNCTION(fcn_name) \ +{ \ + .name = #fcn_name, \ + .groups = bcm281xx_alt_groups, \ + .ngroups = ARRAY_SIZE(bcm281xx_alt_groups), \ +} + +static const struct bcm281xx_pin_function bcm281xx_functions[] = { + BCM281XX_PIN_FUNCTION(alt1), + BCM281XX_PIN_FUNCTION(alt2), + BCM281XX_PIN_FUNCTION(alt3), + BCM281XX_PIN_FUNCTION(alt4), +}; + +static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = { + .pins = bcm281xx_pinctrl_pins, + .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins), + .functions = bcm281xx_functions, + .nfunctions = ARRAY_SIZE(bcm281xx_functions), +}; + +static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev, + unsigned pin) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + if (pin >= pdata->npins) + return BCM281XX_PIN_TYPE_UNKNOWN; + + return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data); +} + +#define BCM281XX_PIN_SHIFT(type, param) \ + (BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT) + +#define BCM281XX_PIN_MASK(type, param) \ + (BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK) + +/* + * This helper function is used to build up the value and mask used to write to + * a pin register, but does not actually write to the register. + */ +static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask, + u32 param_val, u32 param_shift, + u32 param_mask) +{ + *reg_val &= ~param_mask; + *reg_val |= (param_val << param_shift) & param_mask; + *reg_mask |= param_mask; +} + +static struct regmap_config bcm281xx_pinctrl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = BCM281XX_PIN_VC_CAM3_SDA, +}; + +static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->npins; +} + +static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->pins[group].name; +} + +static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pdata->pins[group].number; + *num_pins = 1; + + return 0; +} + +static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +static struct pinctrl_ops bcm281xx_pinctrl_ops = { + .get_groups_count = bcm281xx_pinctrl_get_groups_count, + .get_group_name = bcm281xx_pinctrl_get_group_name, + .get_group_pins = bcm281xx_pinctrl_get_group_pins, + .pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->nfunctions; +} + +static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->functions[function].name; +} + +static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *groups = pdata->functions[function].groups; + *num_groups = pdata->functions[function].ngroups; + + return 0; +} + +static int bcm281xx_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + const struct bcm281xx_pin_function *f = &pdata->functions[function]; + u32 offset = 4 * pdata->pins[group].number; + int rc = 0; + + dev_dbg(pctldev->dev, + "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n", + __func__, f->name, function, pdata->pins[group].name, + pdata->pins[group].number, offset); + + rc = regmap_update_bits(pdata->regmap, offset, + BCM281XX_PIN_REG_F_SEL_MASK, + function << BCM281XX_PIN_REG_F_SEL_SHIFT); + if (rc) + dev_err(pctldev->dev, + "Error updating register for pin %s (%d).\n", + pdata->pins[group].name, pdata->pins[group].number); + + return rc; +} + +static struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = { + .get_functions_count = bcm281xx_pinctrl_get_fcns_count, + .get_function_name = bcm281xx_pinctrl_get_fcn_name, + .get_function_groups = bcm281xx_pinctrl_get_fcn_groups, + .enable = bcm281xx_pinmux_enable, +}; + +static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + return -ENOTSUPP; +} + + +/* Goes through the configs and update register val/mask */ +static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs, + u32 *val, + u32 *mask) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i; + enum pin_config_param param; + u16 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg = (arg >= 1 ? 1 : 0); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(STD, HYST), + BCM281XX_PIN_MASK(STD, HYST)); + break; + /* + * The pin bias can only be one of pull-up, pull-down, or + * disable. The user does not need to specify a value for the + * property, and the default value from pinconf-generic is + * ignored. + */ + case PIN_CONFIG_BIAS_DISABLE: + bcm281xx_pin_update(val, mask, 0, + BCM281XX_PIN_SHIFT(STD, PULL_UP), + BCM281XX_PIN_MASK(STD, PULL_UP)); + bcm281xx_pin_update(val, mask, 0, + BCM281XX_PIN_SHIFT(STD, PULL_DN), + BCM281XX_PIN_MASK(STD, PULL_DN)); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + bcm281xx_pin_update(val, mask, 1, + BCM281XX_PIN_SHIFT(STD, PULL_UP), + BCM281XX_PIN_MASK(STD, PULL_UP)); + bcm281xx_pin_update(val, mask, 0, + BCM281XX_PIN_SHIFT(STD, PULL_DN), + BCM281XX_PIN_MASK(STD, PULL_DN)); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + bcm281xx_pin_update(val, mask, 0, + BCM281XX_PIN_SHIFT(STD, PULL_UP), + BCM281XX_PIN_MASK(STD, PULL_UP)); + bcm281xx_pin_update(val, mask, 1, + BCM281XX_PIN_SHIFT(STD, PULL_DN), + BCM281XX_PIN_MASK(STD, PULL_DN)); + break; + + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(STD, SLEW), + BCM281XX_PIN_MASK(STD, SLEW)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(STD, INPUT_DIS), + BCM281XX_PIN_MASK(STD, INPUT_DIS)); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + /* Valid range is 2-16 mA, even numbers only */ + if ((arg < 2) || (arg > 16) || (arg % 2)) { + dev_err(pctldev->dev, + "Invalid Drive Strength value (%d) for " + "pin %s (%d). Valid values are " + "(2..16) mA, even numbers only.\n", + arg, pdata->pins[pin].name, pin); + return -EINVAL; + } + bcm281xx_pin_update(val, mask, (arg/2)-1, + BCM281XX_PIN_SHIFT(STD, DRV_STR), + BCM281XX_PIN_MASK(STD, DRV_STR)); + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +/* + * The pull-up strength for an I2C pin is represented by bits 4-6 in the + * register with the following mapping: + * 0b000: No pull-up + * 0b001: 1200 Ohm + * 0b010: 1800 Ohm + * 0b011: 720 Ohm + * 0b100: 2700 Ohm + * 0b101: 831 Ohm + * 0b110: 1080 Ohm + * 0b111: 568 Ohm + * This array maps pull-up strength in Ohms to register values (1+index). + */ +static const u16 bcm281xx_pullup_map[] = { + 1200, 1800, 720, 2700, 831, 1080, 568 +}; + +/* Goes through the configs and update register val/mask */ +static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs, + u32 *val, + u32 *mask) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i, j; + enum pin_config_param param; + u16 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++) + if (bcm281xx_pullup_map[j] == arg) + break; + + if (j == ARRAY_SIZE(bcm281xx_pullup_map)) { + dev_err(pctldev->dev, + "Invalid pull-up value (%d) for pin %s " + "(%d). Valid values are 568, 720, 831, " + "1080, 1200, 1800, 2700 Ohms.\n", + arg, pdata->pins[pin].name, pin); + return -EINVAL; + } + + bcm281xx_pin_update(val, mask, j+1, + BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR), + BCM281XX_PIN_MASK(I2C, PULL_UP_STR)); + break; + + case PIN_CONFIG_BIAS_DISABLE: + bcm281xx_pin_update(val, mask, 0, + BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR), + BCM281XX_PIN_MASK(I2C, PULL_UP_STR)); + break; + + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(I2C, SLEW), + BCM281XX_PIN_MASK(I2C, SLEW)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(I2C, INPUT_DIS), + BCM281XX_PIN_MASK(I2C, INPUT_DIS)); + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +/* Goes through the configs and update register val/mask */ +static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs, + u32 *val, + u32 *mask) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i; + enum pin_config_param param; + u16 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(HDMI, MODE), + BCM281XX_PIN_MASK(HDMI, MODE)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS), + BCM281XX_PIN_MASK(HDMI, INPUT_DIS)); + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + enum bcm281xx_pin_type pin_type; + u32 offset = 4 * pin; + u32 cfg_val, cfg_mask; + int rc; + + cfg_val = 0; + cfg_mask = 0; + pin_type = pin_type_get(pctldev, pin); + + /* Different pins have different configuration options */ + switch (pin_type) { + case BCM281XX_PIN_TYPE_STD: + rc = bcm281xx_std_pin_update(pctldev, pin, configs, + num_configs, &cfg_val, &cfg_mask); + break; + + case BCM281XX_PIN_TYPE_I2C: + rc = bcm281xx_i2c_pin_update(pctldev, pin, configs, + num_configs, &cfg_val, &cfg_mask); + break; + + case BCM281XX_PIN_TYPE_HDMI: + rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs, + num_configs, &cfg_val, &cfg_mask); + break; + + default: + dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n", + pdata->pins[pin].name, pin); + return -EINVAL; + + } /* switch pin type */ + + if (rc) + return rc; + + dev_dbg(pctldev->dev, + "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", + __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); + + rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); + if (rc) { + dev_err(pctldev->dev, + "Error updating register for pin %s (%d).\n", + pdata->pins[pin].name, pin); + return rc; + } + + return 0; +} + +static struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = { + .pin_config_get = bcm281xx_pinctrl_pin_config_get, + .pin_config_set = bcm281xx_pinctrl_pin_config_set, +}; + +static struct pinctrl_desc bcm281xx_pinctrl_desc = { + /* name, pins, npins members initialized in probe function */ + .pctlops = &bcm281xx_pinctrl_ops, + .pmxops = &bcm281xx_pinctrl_pinmux_ops, + .confops = &bcm281xx_pinctrl_pinconf_ops, + .owner = THIS_MODULE, +}; + +int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) +{ + struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl; + struct resource *res; + struct pinctrl_dev *pctl; + + /* So far We can assume there is only 1 bank of registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Missing MEM resource\n"); + return -ENODEV; + } + + pdata->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pdata->reg_base)) { + dev_err(&pdev->dev, "Failed to ioremap MEM resource\n"); + return -ENODEV; + } + + /* Initialize the dynamic part of pinctrl_desc */ + pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base, + &bcm281xx_pinctrl_regmap_config); + if (IS_ERR(pdata->regmap)) { + dev_err(&pdev->dev, "Regmap MMIO init failed.\n"); + return -ENODEV; + } + + bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev); + bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins; + bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins; + + pctl = pinctrl_register(&bcm281xx_pinctrl_desc, + &pdev->dev, + pdata); + if (!pctl) { + dev_err(&pdev->dev, "Failed to register pinctrl\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, pdata); + + return 0; +} + +static struct of_device_id bcm281xx_pinctrl_of_match[] = { + { .compatible = "brcm,bcm11351-pinctrl", }, + { }, +}; + +static struct platform_driver bcm281xx_pinctrl_driver = { + .driver = { + .name = "bcm281xx-pinctrl", + .owner = THIS_MODULE, + .of_match_table = bcm281xx_pinctrl_of_match, + }, +}; + +module_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe); + +MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>"); +MODULE_AUTHOR("Sherman Yin <syin@broadcom.com>"); +MODULE_DESCRIPTION("Broadcom BCM281xx pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c index f28d4b08771..3d907de9bc9 100644 --- a/drivers/pinctrl/pinctrl-bcm2835.c +++ b/drivers/pinctrl/pinctrl-bcm2835.c @@ -113,7 +113,7 @@ static struct lock_class_key gpio_lock_class; /* pins are just named GPIO0..GPIO53 */ #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) -struct pinctrl_pin_desc bcm2835_gpio_pins[] = { +static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { BCM2835_GPIO_PIN(0), BCM2835_GPIO_PIN(1), BCM2835_GPIO_PIN(2), @@ -384,7 +384,7 @@ static struct gpio_chip bcm2835_gpio_chip = { .to_irq = bcm2835_gpio_to_irq, .base = -1, .ngpio = BCM2835_NUM_GPIOS, - .can_sleep = 0, + .can_sleep = false, }; static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) @@ -699,11 +699,6 @@ static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, return 0; } -static inline u32 prop_u32(struct property *p, int i) -{ - return be32_to_cpup(((__be32 *)p->value) + i); -} - static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) @@ -761,7 +756,9 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, return -ENOMEM; for (i = 0; i < num_pins; i++) { - pin = prop_u32(pins, i); + err = of_property_read_u32_index(np, "brcm,pins", i, &pin); + if (err) + goto out; if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) { dev_err(pc->dev, "%s: invalid brcm,pins value %d\n", of_node_full_name(np), pin); @@ -770,14 +767,20 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, } if (num_funcs) { - func = prop_u32(funcs, (num_funcs > 1) ? i : 0); + err = of_property_read_u32_index(np, "brcm,function", + (num_funcs > 1) ? i : 0, &func); + if (err) + goto out; err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, func, &cur_map); if (err) goto out; } if (num_pulls) { - pull = prop_u32(pulls, (num_pulls > 1) ? i : 0); + err = of_property_read_u32_index(np, "brcm,pull", + (num_funcs > 1) ? i : 0, &pull); + if (err) + goto out; err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, pull, &cur_map); if (err) @@ -890,28 +893,35 @@ static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, } static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); - enum bcm2835_pinconf_param param = BCM2835_PINCONF_UNPACK_PARAM(config); - u16 arg = BCM2835_PINCONF_UNPACK_ARG(config); + enum bcm2835_pinconf_param param; + u16 arg; u32 off, bit; + int i; - if (param != BCM2835_PINCONF_PARAM_PULL) - return -EINVAL; - - off = GPIO_REG_OFFSET(pin); - bit = GPIO_REG_SHIFT(pin); - - bcm2835_gpio_wr(pc, GPPUD, arg & 3); - /* - * Docs say to wait 150 cycles, but not of what. We assume a - * 1 MHz clock here, which is pretty slow... - */ - udelay(150); - bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); - udelay(150); - bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); + for (i = 0; i < num_configs; i++) { + param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]); + arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]); + + if (param != BCM2835_PINCONF_PARAM_PULL) + return -EINVAL; + + off = GPIO_REG_OFFSET(pin); + bit = GPIO_REG_SHIFT(pin); + + bcm2835_gpio_wr(pc, GPPUD, arg & 3); + /* + * Docs say to wait 150 cycles, but not of what. We assume a + * 1 MHz clock here, which is pretty slow... + */ + udelay(150); + bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); + udelay(150); + bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index edde3acc418..d182fdd2e71 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -8,21 +8,17 @@ * Author: Jonas Aaberg <jonas.aberg@stericsson.com> */ #include <linux/module.h> -#include <linux/irq.h> #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/errno.h> #include <linux/io.h> -#include <linux/irqdomain.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/platform_device.h> #include <linux/gpio.h> -#include <linux/list.h> #include <linux/slab.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> -#include <linux/platform_data/pinctrl-coh901.h> #include "pinctrl-coh901.h" #define U300_GPIO_PORT_STRIDE (0x30) @@ -58,12 +54,21 @@ #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) /* 8 bits per port, no version has more than 7 ports */ +#define U300_GPIO_NUM_PORTS 7 #define U300_GPIO_PINS_PER_PORT 8 -#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7) +#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) + +struct u300_gpio_port { + struct u300_gpio *gpio; + char name[8]; + int irq; + int number; + u8 toggle_edge_mode; +}; struct u300_gpio { struct gpio_chip chip; - struct list_head port_list; + struct u300_gpio_port ports[U300_GPIO_NUM_PORTS]; struct clk *clk; void __iomem *base; struct device *dev; @@ -78,16 +83,6 @@ struct u300_gpio { u32 iev; }; -struct u300_gpio_port { - struct list_head node; - struct u300_gpio *gpio; - char name[8]; - struct irq_domain *domain; - int irq; - int number; - u8 toggle_edge_mode; -}; - /* * Macro to expand to read a specific register found in the "gpio" * struct. It requires the struct u300_gpio *gpio variable to exist in @@ -111,9 +106,6 @@ struct u300_gpio_confdata { int outval; }; -/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */ -#define BS335_GPIO_NUM_PORTS 7 - #define U300_FLOATING_INPUT { \ .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ .output = false, \ @@ -136,7 +128,7 @@ struct u300_gpio_confdata { /* Initial configuration */ static const struct __initconst u300_gpio_confdata -bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { +bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { /* Port 0, pins 0-7 */ { U300_FLOATING_INPUT, @@ -311,39 +303,6 @@ static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, return 0; } -static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct u300_gpio *gpio = to_u300_gpio(chip); - int portno = offset >> 3; - struct u300_gpio_port *port = NULL; - struct list_head *p; - int retirq; - bool found = false; - - list_for_each(p, &gpio->port_list) { - port = list_entry(p, struct u300_gpio_port, node); - if (port->number == portno) { - found = true; - break; - } - } - if (!found) { - dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n", - offset); - return -EINVAL; - } - - /* - * The local hwirqs on the port are the lower three bits, there - * are exactly 8 IRQs per port since they are 8-bit - */ - retirq = irq_find_mapping(port->domain, (offset & 0x7)); - - dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n", - offset, retirq, port->number); - return retirq; -} - /* Returning -EINVAL means "supported but not available" */ int u300_gpio_config_get(struct gpio_chip *chip, unsigned offset, @@ -464,7 +423,6 @@ static struct gpio_chip u300_gpio_chip = { .set = u300_gpio_set, .direction_input = u300_gpio_direction_input, .direction_output = u300_gpio_direction_output, - .to_irq = u300_gpio_to_irq, }; static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) @@ -488,9 +446,10 @@ static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) { - struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); - struct u300_gpio *gpio = port->gpio; - int offset = (port->number << 3) + d->hwirq; + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct u300_gpio *gpio = to_u300_gpio(chip); + struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; + int offset = d->hwirq; u32 val; if ((trigger & IRQF_TRIGGER_RISING) && @@ -524,9 +483,10 @@ static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) static void u300_gpio_irq_enable(struct irq_data *d) { - struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); - struct u300_gpio *gpio = port->gpio; - int offset = (port->number << 3) + d->hwirq; + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct u300_gpio *gpio = to_u300_gpio(chip); + struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; + int offset = d->hwirq; u32 val; unsigned long flags; @@ -540,9 +500,9 @@ static void u300_gpio_irq_enable(struct irq_data *d) static void u300_gpio_irq_disable(struct irq_data *d) { - struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); - struct u300_gpio *gpio = port->gpio; - int offset = (port->number << 3) + d->hwirq; + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct u300_gpio *gpio = to_u300_gpio(chip); + int offset = d->hwirq; u32 val; unsigned long flags; @@ -557,17 +517,19 @@ static struct irq_chip u300_gpio_irqchip = { .irq_enable = u300_gpio_irq_enable, .irq_disable = u300_gpio_irq_disable, .irq_set_type = u300_gpio_irq_type, - }; static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct u300_gpio_port *port = irq_get_handler_data(irq); - struct u300_gpio *gpio = port->gpio; + struct irq_chip *parent_chip = irq_get_chip(irq); + struct gpio_chip *chip = irq_get_handler_data(irq); + struct u300_gpio *gpio = to_u300_gpio(chip); + struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; int pinoffset = port->number << 3; /* get the right stride */ unsigned long val; - desc->irq_data.chip->irq_ack(&desc->irq_data); + chained_irq_enter(parent_chip, desc); + /* Read event register */ val = readl(U300_PIN_REG(pinoffset, iev)); /* Mask relevant bits */ @@ -580,8 +542,8 @@ static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) int irqoffset; for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { - int pin_irq = irq_find_mapping(port->domain, irqoffset); int offset = pinoffset + irqoffset; + int pin_irq = irq_find_mapping(chip->irqdomain, offset); dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", pin_irq, offset); @@ -595,7 +557,7 @@ static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) } } - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chained_irq_exit(parent_chip, desc); } static void __init u300_gpio_init_pin(struct u300_gpio *gpio, @@ -630,13 +592,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio, } } -static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, - struct u300_gpio_platform *plat) +static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) { int i, j; /* Write default config and values to all pins */ - for (i = 0; i < plat->ports; i++) { + for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { for (j = 0; j < 8; j++) { const struct u300_gpio_confdata *conf; int offset = (i*8) + j; @@ -647,20 +608,6 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, } } -static inline void u300_gpio_free_ports(struct u300_gpio *gpio) -{ - struct u300_gpio_port *port; - struct list_head *p, *n; - - list_for_each_safe(p, n, &gpio->port_list) { - port = list_entry(p, struct u300_gpio_port, node); - list_del(&port->node); - if (port->domain) - irq_domain_remove(port->domain); - kfree(port); - } -} - /* * Here we map a GPIO in the local gpio_chip pin space to a pin in * the local pinctrl pin space. The pin controller used is @@ -693,7 +640,6 @@ static struct coh901_pinpair coh901_pintable[] = { static int __init u300_gpio_probe(struct platform_device *pdev) { - struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); struct u300_gpio *gpio; struct resource *memres; int err = 0; @@ -707,17 +653,12 @@ static int __init u300_gpio_probe(struct platform_device *pdev) return -ENOMEM; gpio->chip = u300_gpio_chip; - gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT; + gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT; gpio->chip.dev = &pdev->dev; - gpio->chip.base = plat->gpio_base; + gpio->chip.base = 0; gpio->dev = &pdev->dev; memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!memres) { - dev_err(gpio->dev, "could not get GPIO memory resource\n"); - return -ENODEV; - } - gpio->base = devm_ioremap_resource(&pdev->dev, memres); if (IS_ERR(gpio->base)) return PTR_ERR(gpio->base); @@ -755,68 +696,47 @@ static int __init u300_gpio_probe(struct platform_device *pdev) ((val & 0x0000FE00) >> 9) * 8); writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, gpio->base + U300_GPIO_CR); - u300_gpio_init_coh901571(gpio, plat); + u300_gpio_init_coh901571(gpio); + +#ifdef CONFIG_OF_GPIO + gpio->chip.of_node = pdev->dev.of_node; +#endif + err = gpiochip_add(&gpio->chip); + if (err) { + dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); + goto err_no_chip; + } + + err = gpiochip_irqchip_add(&gpio->chip, + &u300_gpio_irqchip, + 0, + handle_simple_irq, + IRQ_TYPE_EDGE_FALLING); + if (err) { + dev_err(gpio->dev, "no GPIO irqchip\n"); + goto err_no_irqchip; + } /* Add each port with its IRQ separately */ - INIT_LIST_HEAD(&gpio->port_list); - for (portno = 0 ; portno < plat->ports; portno++) { - struct u300_gpio_port *port = - kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); - - if (!port) { - dev_err(gpio->dev, "out of memory\n"); - err = -ENOMEM; - goto err_no_port; - } + for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { + struct u300_gpio_port *port = &gpio->ports[portno]; snprintf(port->name, 8, "gpio%d", portno); port->number = portno; port->gpio = gpio; - port->irq = platform_get_irq_byname(pdev, - port->name); - - dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, - port->name); - - port->domain = irq_domain_add_linear(pdev->dev.of_node, - U300_GPIO_PINS_PER_PORT, - &irq_domain_simple_ops, - port); - if (!port->domain) { - err = -ENOMEM; - goto err_no_domain; - } - - irq_set_chained_handler(port->irq, u300_gpio_irq_handler); - irq_set_handler_data(port->irq, port); + port->irq = platform_get_irq(pdev, portno); - /* For each GPIO pin set the unique IRQ handler */ - for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) { - int irqno = irq_create_mapping(port->domain, i); - - dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n", - gpio->chip.base + (port->number << 3) + i, - port->name, irqno); - irq_set_chip_and_handler(irqno, &u300_gpio_irqchip, - handle_simple_irq); - set_irq_flags(irqno, IRQF_VALID); - irq_set_chip_data(irqno, port); - } + gpiochip_set_chained_irqchip(&gpio->chip, + &u300_gpio_irqchip, + port->irq, + u300_gpio_irq_handler); /* Turns off irq force (test register) for this port */ writel(0x0, gpio->base + portno * gpio->stride + ifr); - - list_add_tail(&port->node, &gpio->port_list); } dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); - err = gpiochip_add(&gpio->chip); - if (err) { - dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); - goto err_no_chip; - } - /* * Add pinctrl pin ranges, the pin controller must be registered * at this point @@ -835,11 +755,10 @@ static int __init u300_gpio_probe(struct platform_device *pdev) return 0; err_no_range: - err = gpiochip_remove(&gpio->chip); +err_no_irqchip: + if (gpiochip_remove(&gpio->chip)) + dev_err(&pdev->dev, "failed to remove gpio chip\n"); err_no_chip: -err_no_domain: -err_no_port: - u300_gpio_free_ports(gpio); clk_disable_unprepare(gpio->clk); dev_err(&pdev->dev, "module ERROR:%d\n", err); return err; @@ -858,15 +777,19 @@ static int __exit u300_gpio_remove(struct platform_device *pdev) dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err); return err; } - u300_gpio_free_ports(gpio); clk_disable_unprepare(gpio->clk); - platform_set_drvdata(pdev, NULL); return 0; } +static const struct of_device_id u300_gpio_match[] = { + { .compatible = "stericsson,gpio-coh901" }, + {}, +}; + static struct platform_driver u300_gpio_driver = { .driver = { .name = "u300-gpio", + .of_match_table = u300_gpio_match, }, .remove = __exit_p(u300_gpio_remove), }; diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c index 8b10b1ac907..9609c23834c 100644 --- a/drivers/pinctrl/pinctrl-exynos.c +++ b/drivers/pinctrl/pinctrl-exynos.c @@ -23,14 +23,13 @@ #include <linux/interrupt.h> #include <linux/irqdomain.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/of_irq.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/err.h> -#include <asm/mach/irq.h> - #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" @@ -51,37 +50,58 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { { } }; -static void exynos_gpio_irq_unmask(struct irq_data *irqd) +static void exynos_gpio_irq_mask(struct irq_data *irqd) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; unsigned long mask; + unsigned long flags; + + spin_lock_irqsave(&bank->slock, flags); mask = readl(d->virt_base + reg_mask); - mask &= ~(1 << irqd->hwirq); + mask |= 1 << irqd->hwirq; writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&bank->slock, flags); } -static void exynos_gpio_irq_mask(struct irq_data *irqd) +static void exynos_gpio_irq_ack(struct irq_data *irqd) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; - unsigned long mask; + unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; - mask = readl(d->virt_base + reg_mask); - mask |= 1 << irqd->hwirq; - writel(mask, d->virt_base + reg_mask); + writel(1 << irqd->hwirq, d->virt_base + reg_pend); } -static void exynos_gpio_irq_ack(struct irq_data *irqd) +static void exynos_gpio_irq_unmask(struct irq_data *irqd) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; + unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; + unsigned long mask; + unsigned long flags; - writel(1 << irqd->hwirq, d->virt_base + reg_pend); + /* + * Ack level interrupts right before unmask + * + * If we don't do this we'll get a double-interrupt. Level triggered + * interrupts must not fire an interrupt if the level is not + * _currently_ active, even if it was active while the interrupt was + * masked. + */ + if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) + exynos_gpio_irq_ack(irqd); + + spin_lock_irqsave(&bank->slock, flags); + + mask = readl(d->virt_base + reg_mask); + mask &= ~(1 << irqd->hwirq); + writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&bank->slock, flags); } static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) @@ -197,6 +217,12 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) return IRQ_HANDLED; } +struct exynos_eint_gpio_save { + u32 eint_con; + u32 eint_fltcon0; + u32 eint_fltcon1; +}; + /* * exynos_eint_gpio_init() - setup handling of external gpio interrupts. * @d: driver data of samsung pinctrl driver. @@ -205,8 +231,8 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) { struct samsung_pin_bank *bank; struct device *dev = d->dev; - unsigned int ret; - unsigned int i; + int ret; + int i; if (!d->irq) { dev_err(dev, "irq number not available\n"); @@ -228,23 +254,29 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) bank->nr_pins, &exynos_gpio_irqd_ops, bank); if (!bank->irq_domain) { dev_err(dev, "gpio irq domain add failed\n"); - return -ENXIO; + ret = -ENXIO; + goto err_domains; + } + + bank->soc_priv = devm_kzalloc(d->dev, + sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); + if (!bank->soc_priv) { + irq_domain_remove(bank->irq_domain); + ret = -ENOMEM; + goto err_domains; } } return 0; -} -static void exynos_wkup_irq_unmask(struct irq_data *irqd) -{ - struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); - struct samsung_pinctrl_drv_data *d = b->drvdata; - unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; - unsigned long mask; +err_domains: + for (--i, --bank; i >= 0; --i, --bank) { + if (bank->eint_type != EINT_TYPE_GPIO) + continue; + irq_domain_remove(bank->irq_domain); + } - mask = readl(d->virt_base + reg_mask); - mask &= ~(1 << irqd->hwirq); - writel(mask, d->virt_base + reg_mask); + return ret; } static void exynos_wkup_irq_mask(struct irq_data *irqd) @@ -253,10 +285,15 @@ static void exynos_wkup_irq_mask(struct irq_data *irqd) struct samsung_pinctrl_drv_data *d = b->drvdata; unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; unsigned long mask; + unsigned long flags; + + spin_lock_irqsave(&b->slock, flags); mask = readl(d->virt_base + reg_mask); mask |= 1 << irqd->hwirq; writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&b->slock, flags); } static void exynos_wkup_irq_ack(struct irq_data *irqd) @@ -268,6 +305,34 @@ static void exynos_wkup_irq_ack(struct irq_data *irqd) writel(1 << irqd->hwirq, d->virt_base + pend); } +static void exynos_wkup_irq_unmask(struct irq_data *irqd) +{ + struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = b->drvdata; + unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; + unsigned long mask; + unsigned long flags; + + /* + * Ack level interrupts right before unmask + * + * If we don't do this we'll get a double-interrupt. Level triggered + * interrupts must not fire an interrupt if the level is not + * _currently_ active, even if it was active while the interrupt was + * masked. + */ + if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) + exynos_wkup_irq_ack(irqd); + + spin_lock_irqsave(&b->slock, flags); + + mask = readl(d->virt_base + reg_mask); + mask &= ~(1 << irqd->hwirq); + writel(mask, d->virt_base + reg_mask); + + spin_unlock_irqrestore(&b->slock, flags); +} + static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); @@ -327,6 +392,28 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) return 0; } +static u32 exynos_eint_wake_mask = 0xffffffff; + +u32 exynos_get_eint_wake_mask(void) +{ + return exynos_eint_wake_mask; +} + +static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); + + pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); + + if (!on) + exynos_eint_wake_mask |= bit; + else + exynos_eint_wake_mask &= ~bit; + + return 0; +} + /* * irq_chip for wakeup interrupts */ @@ -336,6 +423,7 @@ static struct irq_chip exynos_wkup_irq_chip = { .irq_mask = exynos_wkup_irq_mask, .irq_ack = exynos_wkup_irq_ack, .irq_set_type = exynos_wkup_irq_set_type, + .irq_set_wake = exynos_wkup_irq_set_wake, }; /* interrupt handler for wakeup interrupts 0..15 */ @@ -506,6 +594,197 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) return 0; } +static void exynos_pinctrl_suspend_bank( + struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = drvdata->virt_base; + + save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + + pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); + pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); +} + +static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + struct samsung_pin_bank *bank = ctrl->pin_banks; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) + if (bank->eint_type == EINT_TYPE_GPIO) + exynos_pinctrl_suspend_bank(drvdata, bank); +} + +static void exynos_pinctrl_resume_bank( + struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = drvdata->virt_base; + + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); + pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset), save->eint_fltcon0); + pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4), save->eint_fltcon1); + + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); +} + +static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + struct samsung_pin_bank *bank = ctrl->pin_banks; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) + if (bank->eint_type == EINT_TYPE_GPIO) + exynos_pinctrl_resume_bank(drvdata, bank); +} + +/* pin banks of s5pv210 pin-controller */ +static struct samsung_pin_bank s5pv210_pin_bank[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), + EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), + EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), + EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), + EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), + EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), + EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), + EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), + EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), + EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), + EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), + EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), + EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), + EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), + EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), +}; + +struct samsung_pin_ctrl s5pv210_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = s5pv210_pin_bank, + .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "s5pv210-gpio-ctrl0", + }, +}; + +/* pin banks of exynos3250 pin-controller 0 */ +static struct samsung_pin_bank exynos3250_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), +}; + +/* pin banks of exynos3250 pin-controller 1 */ +static struct samsung_pin_bank exynos3250_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), + EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), + EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* + * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes + * two gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos3250_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos3250_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos3250-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos3250_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos3250-gpio-ctrl1", + }, +}; + /* pin banks of exynos4210 pin-controller 0 */ static struct samsung_pin_bank exynos4210_pin_banks0[] = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), @@ -569,6 +848,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, .label = "exynos4210-gpio-ctrl0", }, { /* pin-controller instance 1 data */ @@ -583,6 +864,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, .label = "exynos4210-gpio-ctrl1", }, { /* pin-controller instance 2 data */ @@ -664,6 +947,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, .label = "exynos4x12-gpio-ctrl0", }, { /* pin-controller instance 1 data */ @@ -678,6 +963,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, .label = "exynos4x12-gpio-ctrl1", }, { /* pin-controller instance 2 data */ @@ -688,6 +975,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, .label = "exynos4x12-gpio-ctrl2", }, { /* pin-controller instance 3 data */ @@ -698,6 +987,324 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, .svc = EXYNOS_SVC_OFFSET, .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, .label = "exynos4x12-gpio-ctrl3", }, }; + +/* pin banks of exynos5250 pin-controller 0 */ +static struct samsung_pin_bank exynos5250_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), + EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), + EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), + EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5250 pin-controller 1 */ +static struct samsung_pin_bank exynos5250_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), +}; + +/* pin banks of exynos5250 pin-controller 2 */ +static struct samsung_pin_bank exynos5250_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5250 pin-controller 3 */ +static struct samsung_pin_bank exynos5250_pin_banks3[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5250_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5250-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5250_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5250-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5250_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5250-gpio-ctrl2", + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5250_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .label = "exynos5250-gpio-ctrl3", + }, +}; + +/* pin banks of exynos5260 pin-controller 0 */ +static struct samsung_pin_bank exynos5260_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5260 pin-controller 1 */ +static struct samsung_pin_bank exynos5260_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), +}; + +/* pin banks of exynos5260 pin-controller 2 */ +static struct samsung_pin_bank exynos5260_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5260_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .label = "exynos5260-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5260_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5260_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5260-gpio-ctrl2", + }, +}; + +/* pin banks of exynos5420 pin-controller 0 */ +static struct samsung_pin_bank exynos5420_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5420 pin-controller 1 */ +static struct samsung_pin_bank exynos5420_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), + EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), +}; + +/* pin banks of exynos5420 pin-controller 2 */ +static struct samsung_pin_bank exynos5420_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), + EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), +}; + +/* pin banks of exynos5420 pin-controller 3 */ +static struct samsung_pin_bank exynos5420_pin_banks3[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), +}; + +/* pin banks of exynos5420 pin-controller 4 */ +static struct samsung_pin_bank exynos5420_pin_banks4[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +struct samsung_pin_ctrl exynos5420_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5420_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .weint_con = EXYNOS_WKUP_ECON_OFFSET, + .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .label = "exynos5420-gpio-ctrl0", + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5420_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl1", + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5420_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl2", + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5420_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl3", + }, { + /* pin-controller instance 4 data */ + .pin_banks = exynos5420_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), + .geint_con = EXYNOS_GPIO_ECON_OFFSET, + .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, + .svc = EXYNOS_SVC_OFFSET, + .eint_gpio_init = exynos_eint_gpio_init, + .label = "exynos5420-gpio-ctrl4", + }, +}; diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h index 9b1f77a5bf0..3c91c357792 100644 --- a/drivers/pinctrl/pinctrl-exynos.h +++ b/drivers/pinctrl/pinctrl-exynos.h @@ -19,6 +19,7 @@ /* External GPIO and wakeup interrupt related definitions */ #define EXYNOS_GPIO_ECON_OFFSET 0x700 +#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 #define EXYNOS_GPIO_EMASK_OFFSET 0x900 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00 #define EXYNOS_WKUP_ECON_OFFSET 0xE00 diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c index 6038503ed92..8fe2ab0a769 100644 --- a/drivers/pinctrl/pinctrl-exynos5440.c +++ b/drivers/pinctrl/pinctrl-exynos5440.c @@ -220,7 +220,7 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, dev_err(dev, "failed to alloc memory for group name\n"); goto free_map; } - sprintf(gname, "%s%s", np->name, GROUP_SUFFIX); + snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX); /* * don't have config options? then skip over to creating function @@ -259,7 +259,8 @@ skip_cfgs: dev_err(dev, "failed to alloc memory for func name\n"); goto free_cfg; } - sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX); + snprintf(fname, strlen(np->name) + 4, "%s%s", np->name, + FUNCTION_SUFFIX); map[*nmaps].data.mux.group = gname; map[*nmaps].data.mux.function = fname; @@ -400,64 +401,71 @@ static const struct pinmux_ops exynos5440_pinmux_ops = { /* set the pin config settings for a specified pin */ static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct exynos5440_pinctrl_priv_data *priv; void __iomem *base; - enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config); - u32 cfg_value = PINCFG_UNPACK_VALUE(config); + enum pincfg_type cfg_type; + u32 cfg_value; u32 data; + int i; priv = pinctrl_dev_get_drvdata(pctldev); base = priv->reg_base; - switch (cfg_type) { - case PINCFG_TYPE_PUD: - /* first set pull enable/disable bit */ - data = readl(base + GPIO_PE); - data &= ~(1 << pin); - if (cfg_value) - data |= (1 << pin); - writel(data, base + GPIO_PE); - - /* then set pull up/down bit */ - data = readl(base + GPIO_PS); - data &= ~(1 << pin); - if (cfg_value == 2) - data |= (1 << pin); - writel(data, base + GPIO_PS); - break; - - case PINCFG_TYPE_DRV: - /* set the first bit of the drive strength */ - data = readl(base + GPIO_DS0); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_DS0); - cfg_value >>= 1; - - /* set the second bit of the driver strength */ - data = readl(base + GPIO_DS1); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_DS1); - break; - case PINCFG_TYPE_SKEW_RATE: - data = readl(base + GPIO_SR); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_SR); - break; - case PINCFG_TYPE_INPUT_TYPE: - data = readl(base + GPIO_TYPE); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_TYPE); - break; - default: - WARN_ON(1); - return -EINVAL; - } + for (i = 0; i < num_configs; i++) { + cfg_type = PINCFG_UNPACK_TYPE(configs[i]); + cfg_value = PINCFG_UNPACK_VALUE(configs[i]); + + switch (cfg_type) { + case PINCFG_TYPE_PUD: + /* first set pull enable/disable bit */ + data = readl(base + GPIO_PE); + data &= ~(1 << pin); + if (cfg_value) + data |= (1 << pin); + writel(data, base + GPIO_PE); + + /* then set pull up/down bit */ + data = readl(base + GPIO_PS); + data &= ~(1 << pin); + if (cfg_value == 2) + data |= (1 << pin); + writel(data, base + GPIO_PS); + break; + + case PINCFG_TYPE_DRV: + /* set the first bit of the drive strength */ + data = readl(base + GPIO_DS0); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_DS0); + cfg_value >>= 1; + + /* set the second bit of the driver strength */ + data = readl(base + GPIO_DS1); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_DS1); + break; + case PINCFG_TYPE_SKEW_RATE: + data = readl(base + GPIO_SR); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_SR); + break; + case PINCFG_TYPE_INPUT_TYPE: + data = readl(base + GPIO_TYPE); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_TYPE); + break; + default: + WARN_ON(1); + return -EINVAL; + } + } /* for each config */ return 0; } @@ -509,7 +517,8 @@ static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, /* set the pin config settings for a specified pin group */ static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { struct exynos5440_pinctrl_priv_data *priv; const unsigned int *pins; @@ -519,7 +528,8 @@ static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev, pins = priv->pin_groups[group].pins; for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++) - exynos5440_pinconf_set(pctldev, pins[cnt], config); + exynos5440_pinconf_set(pctldev, pins[cnt], configs, + num_configs); return 0; } @@ -713,7 +723,8 @@ static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, dev_err(dev, "failed to alloc memory for group name\n"); return -ENOMEM; } - sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX); + snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, + GROUP_SUFFIX); grp->name = gname; grp->pins = pin_list; @@ -733,7 +744,8 @@ skip_to_pin_function: dev_err(dev, "failed to alloc memory for func name\n"); return -ENOMEM; } - sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX); + snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, + FUNCTION_SUFFIX); func->name = fname; func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); @@ -806,7 +818,7 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev, /* for each pin, set the name of the pin */ for (pin = 0; pin < ctrldesc->npins; pin++) { - sprintf(pin_names, "gpio%02d", pin); + snprintf(pin_names, 6, "gpio%02d", pin); pdesc = pindesc + pin; pdesc->name = pin_names; pin_names += PIN_NAME_LENGTH; @@ -1000,11 +1012,6 @@ static int exynos5440_pinctrl_probe(struct platform_device *pdev) } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "cannot find IO resource\n"); - return -ENOENT; - } - priv->reg_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(priv->reg_base)) return PTR_ERR(priv->reg_base); @@ -1041,7 +1048,7 @@ static struct platform_driver exynos5440_pinctrl_driver = { .driver = { .name = "exynos5440-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match), + .of_match_table = exynos5440_pinctrl_dt_match, }, }; diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c index f9b2a1d4854..2e62689b5e9 100644 --- a/drivers/pinctrl/pinctrl-falcon.c +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -75,6 +75,7 @@ enum falcon_mux { FALCON_MUX_GPIO = 0, FALCON_MUX_RST, FALCON_MUX_NTR, + FALCON_MUX_PPS, FALCON_MUX_MDIO, FALCON_MUX_LED, FALCON_MUX_SPI, @@ -114,7 +115,7 @@ static struct ltq_mfp_pin falcon_mfp[] = { MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE), MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE), MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE), - MFP_FALCON(GPIO5, NTR, GPIO, NONE, NONE), + MFP_FALCON(GPIO5, NTR, GPIO, PPS, NONE), MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE), MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE), MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE), @@ -168,6 +169,7 @@ static struct ltq_mfp_pin falcon_mfp[] = { static const unsigned pins_por[] = {GPIO0}; static const unsigned pins_ntr[] = {GPIO4}; static const unsigned pins_ntr8k[] = {GPIO5}; +static const unsigned pins_pps[] = {GPIO5}; static const unsigned pins_hrst[] = {GPIO6}; static const unsigned pins_mdio[] = {GPIO7, GPIO8}; static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11, @@ -186,6 +188,7 @@ static struct ltq_pin_group falcon_grps[] = { GRP_MUX("por", RST, pins_por), GRP_MUX("ntr", NTR, pins_ntr), GRP_MUX("ntr8k", NTR, pins_ntr8k), + GRP_MUX("pps", PPS, pins_pps), GRP_MUX("hrst", RST, pins_hrst), GRP_MUX("mdio", MDIO, pins_mdio), GRP_MUX("bootled", LED, pins_bled), @@ -201,7 +204,7 @@ static struct ltq_pin_group falcon_grps[] = { }; static const char * const ltq_rst_grps[] = {"por", "hrst"}; -static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k"}; +static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"}; static const char * const ltq_mdio_grps[] = {"mdio"}; static const char * const ltq_bled_grps[] = {"bootled"}; static const char * const ltq_asc_grps[] = {"asc0", "asc1"}; @@ -235,7 +238,8 @@ static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev, } static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { return -ENOTSUPP; } @@ -276,39 +280,47 @@ static int falcon_pinconf_get(struct pinctrl_dev *pctrldev, } static int falcon_pinconf_set(struct pinctrl_dev *pctrldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { - enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); - int arg = LTQ_PINCONF_UNPACK_ARG(config); + enum ltq_pinconf_param param; + int arg; struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); void __iomem *mem = info->membase[PORT(pin)]; u32 reg; + int i; - switch (param) { - case LTQ_PINCONF_PARAM_DRIVE_CURRENT: - reg = LTQ_PADC_DCC; - break; - - case LTQ_PINCONF_PARAM_SLEW_RATE: - reg = LTQ_PADC_SRC; - break; - - case LTQ_PINCONF_PARAM_PULL: - if (arg == 1) - reg = LTQ_PADC_PDEN; - else - reg = LTQ_PADC_PUEN; - break; + for (i = 0; i < num_configs; i++) { + param = LTQ_PINCONF_UNPACK_PARAM(configs[i]); + arg = LTQ_PINCONF_UNPACK_ARG(configs[i]); + + switch (param) { + case LTQ_PINCONF_PARAM_DRIVE_CURRENT: + reg = LTQ_PADC_DCC; + break; + + case LTQ_PINCONF_PARAM_SLEW_RATE: + reg = LTQ_PADC_SRC; + break; + + case LTQ_PINCONF_PARAM_PULL: + if (arg == 1) + reg = LTQ_PADC_PDEN; + else + reg = LTQ_PADC_PUEN; + break; + + default: + pr_err("%s: Invalid config param %04x\n", + pinctrl_dev_get_name(pctrldev), param); + return -ENOTSUPP; + } - default: - pr_err("%s: Invalid config param %04x\n", - pinctrl_dev_get_name(pctrldev), param); - return -ENOTSUPP; - } + pad_w32(mem, BIT(PORT_PIN(pin)), reg); + if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) + return -ENOTSUPP; + } /* for each config */ - pad_w32(mem, BIT(PORT_PIN(pin)), reg); - if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) - return -ENOTSUPP; return 0; } diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c index 0ef190449ea..a24448e5d39 100644 --- a/drivers/pinctrl/pinctrl-imx.c +++ b/drivers/pinctrl/pinctrl-imx.c @@ -27,18 +27,6 @@ #include "core.h" #include "pinctrl-imx.h" -#define IMX_PMX_DUMP(info, p, m, c, n) \ -{ \ - int i, j; \ - printk(KERN_DEBUG "Format: Pin Mux Config\n"); \ - for (i = 0; i < n; i++) { \ - j = p[i]; \ - printk(KERN_DEBUG "%s %d 0x%lx\n", \ - info->pins[j].name, \ - m[i], c[i]); \ - } \ -} - /* The bits in CONFIG cell defined in binding doc*/ #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ #define IMX_PAD_SION 0x40000000 /* set SION */ @@ -54,32 +42,6 @@ struct imx_pinctrl { const struct imx_pinctrl_soc_info *info; }; -static const struct imx_pin_reg *imx_find_pin_reg( - const struct imx_pinctrl_soc_info *info, - unsigned pin, bool is_mux, unsigned mux) -{ - const struct imx_pin_reg *pin_reg = NULL; - int i; - - for (i = 0; i < info->npin_regs; i++) { - pin_reg = &info->pin_regs[i]; - if (pin_reg->pid != pin) - continue; - if (!is_mux) - break; - else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK)) - break; - } - - if (i == info->npin_regs) { - dev_err(info->dev, "Pin(%s): unable to find pin reg map\n", - info->pins[pin].name); - return NULL; - } - - return pin_reg; -} - static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( const struct imx_pinctrl_soc_info *info, const char *name) @@ -124,7 +86,7 @@ static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, if (selector >= info->ngroups) return -EINVAL; - *pins = info->groups[selector].pins; + *pins = info->groups[selector].pin_ids; *npins = info->groups[selector].npins; return 0; @@ -160,7 +122,7 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, } for (i = 0; i < grp->npins; i++) { - if (!(grp->configs[i] & IMX_NO_PAD_CTL)) + if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) map_num++; } @@ -185,11 +147,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, /* create config map */ new_map++; for (i = j = 0; i < grp->npins; i++) { - if (!(grp->configs[i] & IMX_NO_PAD_CTL)) { + if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) { new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; new_map[j].data.configs.group_or_pin = - pin_get_name(pctldev, grp->pins[i]); - new_map[j].data.configs.configs = &grp->configs[i]; + pin_get_name(pctldev, grp->pins[i].pin); + new_map[j].data.configs.configs = &grp->pins[i].config; new_map[j].data.configs.num_configs = 1; j++; } @@ -223,46 +185,79 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg; - const unsigned *pins, *mux; unsigned int npins, pin_id; int i; + struct imx_pin_group *grp; /* * Configure the mux mode for each pin in the group for a specific * function. */ - pins = info->groups[group].pins; - npins = info->groups[group].npins; - mux = info->groups[group].mux_mode; - - WARN_ON(!pins || !npins || !mux); + grp = &info->groups[group]; + npins = grp->npins; dev_dbg(ipctl->dev, "enable function %s group %s\n", - info->functions[selector].name, info->groups[group].name); + info->functions[selector].name, grp->name); for (i = 0; i < npins; i++) { - pin_id = pins[i]; - - pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]); - if (!pin_reg) - return -EINVAL; + struct imx_pin *pin = &grp->pins[i]; + pin_id = pin->pin; + pin_reg = &info->pin_regs[pin_id]; - if (!pin_reg->mux_reg) { + if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) { dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", info->pins[pin_id].name); return -EINVAL; } - writel(mux[i], ipctl->base + pin_reg->mux_reg); + if (info->flags & SHARE_MUX_CONF_REG) { + u32 reg; + reg = readl(ipctl->base + pin_reg->mux_reg); + reg &= ~(0x7 << 20); + reg |= (pin->mux_mode << 20); + writel(reg, ipctl->base + pin_reg->mux_reg); + } else { + writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); + } dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, mux[i]); - - /* some pins also need select input setting, set it if found */ - if (pin_reg->input_reg) { - writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg); + pin_reg->mux_reg, pin->mux_mode); + + /* + * If the select input value begins with 0xff, it's a quirky + * select input and the value should be interpreted as below. + * 31 23 15 7 0 + * | 0xff | shift | width | select | + * It's used to work around the problem that the select + * input for some pin is not implemented in the select + * input register but in some general purpose register. + * We encode the select input value, width and shift of + * the bit field into input_val cell of pin function ID + * in device tree, and then decode them here for setting + * up the select input bits in general purpose register. + */ + if (pin->input_val >> 24 == 0xff) { + u32 val = pin->input_val; + u8 select = val & 0xff; + u8 width = (val >> 8) & 0xff; + u8 shift = (val >> 16) & 0xff; + u32 mask = ((1 << width) - 1) << shift; + /* + * The input_reg[i] here is actually some IOMUXC general + * purpose register, not regular select input register. + */ + val = readl(ipctl->base + pin->input_reg); + val &= ~mask; + val |= select << shift; + writel(val, ipctl->base + pin->input_reg); + } else if (pin->input_reg) { + /* + * Regular select input register can never be at offset + * 0, and we only print register value for regular case. + */ + writel(pin->input_val, ipctl->base + pin->input_reg); dev_dbg(ipctl->dev, "==>select_input: offset 0x%x val 0x%x\n", - pin_reg->input_reg, pin_reg->input_val); + pin->input_reg, pin->input_val); } } @@ -311,13 +306,9 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg) - return -EINVAL; + const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; - if (!pin_reg->conf_reg) { + if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { dev_err(info->dev, "Pin(%s) does not support config function\n", info->pins[pin_id].name); return -EINVAL; @@ -325,21 +316,22 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, *config = readl(ipctl->base + pin_reg->conf_reg); + if (info->flags & SHARE_MUX_CONF_REG) + *config &= 0xffff; + return 0; } static int imx_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long config) + unsigned pin_id, unsigned long *configs, + unsigned num_configs) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg) - return -EINVAL; + const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; + int i; - if (!pin_reg->conf_reg) { + if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { dev_err(info->dev, "Pin(%s) does not support config function\n", info->pins[pin_id].name); return -EINVAL; @@ -348,9 +340,19 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, dev_dbg(ipctl->dev, "pinconf set pin %s\n", info->pins[pin_id].name); - writel(config, ipctl->base + pin_reg->conf_reg); - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", - pin_reg->conf_reg, config); + for (i = 0; i < num_configs; i++) { + if (info->flags & SHARE_MUX_CONF_REG) { + u32 reg; + reg = readl(ipctl->base + pin_reg->conf_reg); + reg &= ~0xffff; + reg |= configs[i]; + writel(reg, ipctl->base + pin_reg->conf_reg); + } else { + writel(configs[i], ipctl->base + pin_reg->conf_reg); + } + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", + pin_reg->conf_reg, configs[i]); + } /* for each config */ return 0; } @@ -360,10 +362,9 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; + const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; unsigned long config; - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); if (!pin_reg || !pin_reg->conf_reg) { seq_printf(s, "N/A"); return; @@ -389,8 +390,9 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "\n"); grp = &info->groups[group]; for (i = 0; i < grp->npins; i++) { - name = pin_get_name(pctldev, grp->pins[i]); - ret = imx_pinconf_get(pctldev, grp->pins[i], &config); + struct imx_pin *pin = &grp->pins[i]; + name = pin_get_name(pctldev, pin->pin); + ret = imx_pinconf_get(pctldev, pin->pin, &config); if (ret) return; seq_printf(s, "%s: 0x%lx", name, config); @@ -411,33 +413,29 @@ static struct pinctrl_desc imx_pinctrl_desc = { .owner = THIS_MODULE, }; -/* decode pin id and mux from pin function id got from device tree*/ -static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info, - unsigned int pin_func_id, unsigned int *pin_id, - unsigned int *mux) -{ - if (pin_func_id > info->npin_regs) - return -EINVAL; - - *pin_id = info->pin_regs[pin_func_id].pid; - *mux = info->pin_regs[pin_func_id].mux_mode; - - return 0; -} +/* + * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and + * 1 u32 CONFIG, so 24 types in total for each pin. + */ +#define FSL_PIN_SIZE 24 +#define SHARE_FSL_PIN_SIZE 20 static int imx_pinctrl_parse_groups(struct device_node *np, struct imx_pin_group *grp, struct imx_pinctrl_soc_info *info, u32 index) { - unsigned int pin_func_id; - int ret, size; + int size, pin_size; const __be32 *list; - int i, j; + int i; u32 config; dev_dbg(info->dev, "group(%d): %s\n", index, np->name); + if (info->flags & SHARE_MUX_CONF_REG) + pin_size = SHARE_FSL_PIN_SIZE; + else + pin_size = FSL_PIN_SIZE; /* Initialise group */ grp->name = np->name; @@ -446,38 +444,56 @@ static int imx_pinctrl_parse_groups(struct device_node *np, * do sanity check and calculate pins number */ list = of_get_property(np, "fsl,pins", &size); + if (!list) { + dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); + return -EINVAL; + } + /* we do not check return since it's safe node passed down */ - size /= sizeof(*list); - if (!size || size % 2) { - dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n"); + if (!size || size % pin_size) { + dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); return -EINVAL; } - grp->npins = size / 2; - grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), + grp->npins = size / pin_size; + grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin), GFP_KERNEL); - grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), + grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), GFP_KERNEL); - grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long), - GFP_KERNEL); - for (i = 0, j = 0; i < size; i += 2, j++) { - pin_func_id = be32_to_cpu(*list++); - ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id, - &grp->pins[j], &grp->mux_mode[j]); - if (ret) { - dev_err(info->dev, "get invalid pin function id\n"); - return -EINVAL; - } + if (!grp->pins || ! grp->pin_ids) + return -ENOMEM; + + for (i = 0; i < grp->npins; i++) { + u32 mux_reg = be32_to_cpu(*list++); + u32 conf_reg; + unsigned int pin_id; + struct imx_pin_reg *pin_reg; + struct imx_pin *pin = &grp->pins[i]; + + if (info->flags & SHARE_MUX_CONF_REG) + conf_reg = mux_reg; + else + conf_reg = be32_to_cpu(*list++); + + pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; + pin_reg = &info->pin_regs[pin_id]; + pin->pin = pin_id; + grp->pin_ids[i] = pin_id; + pin_reg->mux_reg = mux_reg; + pin_reg->conf_reg = conf_reg; + pin->input_reg = be32_to_cpu(*list++); + pin->mux_mode = be32_to_cpu(*list++); + pin->input_val = be32_to_cpu(*list++); + /* SION bit is in mux register */ config = be32_to_cpu(*list++); if (config & IMX_PAD_SION) - grp->mux_mode[j] |= IOMUXC_CONFIG_SION; - grp->configs[j] = config & ~IMX_PAD_SION; - } + pin->mux_mode |= IOMUXC_CONFIG_SION; + pin->config = config & ~IMX_PAD_SION; -#ifdef DEBUG - IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins); -#endif + dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, + pin->mux_mode, pin->config); + } return 0; } @@ -489,7 +505,6 @@ static int imx_pinctrl_parse_functions(struct device_node *np, struct device_node *child; struct imx_pmx_func *func; struct imx_pin_group *grp; - int ret; static u32 grp_index; u32 i = 0; @@ -501,7 +516,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, func->name = np->name; func->num_groups = of_get_child_count(np); if (func->num_groups <= 0) { - dev_err(info->dev, "no groups defined\n"); + dev_err(info->dev, "no groups defined in %s\n", np->full_name); return -EINVAL; } func->groups = devm_kzalloc(info->dev, @@ -510,9 +525,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, for_each_child_of_node(np, child) { func->groups[i] = child->name; grp = &info->groups[grp_index++]; - ret = imx_pinctrl_parse_groups(child, grp, info, i++); - if (ret) - return ret; + imx_pinctrl_parse_groups(child, grp, info, i++); } return 0; @@ -523,7 +536,6 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, { struct device_node *np = pdev->dev.of_node; struct device_node *child; - int ret; u32 nfuncs = 0; u32 i = 0; @@ -550,13 +562,8 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, if (!info->groups) return -ENOMEM; - for_each_child_of_node(np, child) { - ret = imx_pinctrl_parse_functions(child, info, i++); - if (ret) { - dev_err(&pdev->dev, "failed to parse function\n"); - return ret; - } - } + for_each_child_of_node(np, child) + imx_pinctrl_parse_functions(child, info, i++); return 0; } @@ -568,8 +575,7 @@ int imx_pinctrl_probe(struct platform_device *pdev, struct resource *res; int ret; - if (!info || !info->pins || !info->npins - || !info->pin_regs || !info->npin_regs) { + if (!info || !info->pins || !info->npins) { dev_err(&pdev->dev, "wrong pinctrl info\n"); return -EINVAL; } @@ -580,10 +586,12 @@ int imx_pinctrl_probe(struct platform_device *pdev, if (!ipctl) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENOENT; + info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) * + info->npins, GFP_KERNEL); + if (!info->pin_regs) + return -ENOMEM; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ipctl->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(ipctl->base)) return PTR_ERR(ipctl->base); diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h index 9b65e7828f1..db408b05700 100644 --- a/drivers/pinctrl/pinctrl-imx.h +++ b/drivers/pinctrl/pinctrl-imx.h @@ -18,23 +18,35 @@ struct platform_device; /** + * struct imx_pin_group - describes a single i.MX pin + * @pin: the pin_id of this pin + * @mux_mode: the mux mode for this pin. + * @input_reg: the select input register offset for this pin if any + * 0 if no select input setting needed. + * @input_val: the select input value for this pin. + * @configs: the config for this pin. + */ +struct imx_pin { + unsigned int pin; + unsigned int mux_mode; + u16 input_reg; + unsigned int input_val; + unsigned long config; +}; + +/** * struct imx_pin_group - describes an IMX pin group * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space * @npins: the number of pins in this group array, i.e. the number of * elements in .pins so we can iterate over that array - * @mux_mode: the mux mode for each pin in this group. The size of this - * array is the same as pins. - * @configs: the config for each pin in this group. The size of this - * array is the same as pins. + * @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array + * @pins: array of pins */ struct imx_pin_group { const char *name; - unsigned int *pins; unsigned npins; - unsigned int *mux_mode; - unsigned long *configs; + unsigned int *pin_ids; + struct imx_pin *pins; }; /** @@ -51,49 +63,32 @@ struct imx_pmx_func { /** * struct imx_pin_reg - describe a pin reg map - * The last 3 members are used for select input setting - * @pid: pin id * @mux_reg: mux register offset * @conf_reg: config register offset - * @mux_mode: mux mode - * @input_reg: select input register offset for this mux if any - * 0 if no select input setting needed. - * @input_val: the value set to select input register */ struct imx_pin_reg { - u16 pid; u16 mux_reg; u16 conf_reg; - u8 mux_mode; - u16 input_reg; - u8 input_val; }; struct imx_pinctrl_soc_info { struct device *dev; const struct pinctrl_pin_desc *pins; unsigned int npins; - const struct imx_pin_reg *pin_regs; - unsigned int npin_regs; + struct imx_pin_reg *pin_regs; struct imx_pin_group *groups; unsigned int ngroups; struct imx_pmx_func *functions; unsigned int nfunctions; + unsigned int flags; }; +#define ZERO_OFFSET_VALID 0x1 +#define SHARE_MUX_CONF_REG 0x2 + #define NO_MUX 0x0 #define NO_PAD 0x0 -#define IMX_PIN_REG(id, conf, mux, mode, input, val) \ - { \ - .pid = id, \ - .conf_reg = conf, \ - .mux_reg = mux, \ - .mux_mode = mode, \ - .input_reg = input, \ - .input_val = val, \ - } - #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) #define PAD_CTL_MASK(len) ((1 << len) - 1) diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c new file mode 100644 index 00000000000..815384b377b --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx1-core.c @@ -0,0 +1,660 @@ +/* + * Core driver for the imx pin controller in imx1/21/27 + * + * Copyright (C) 2013 Pengutronix + * Author: Markus Pargmann <mpa@pengutronix.de> + * + * Based on pinctrl-imx.c: + * Author: Dong Aisheng <dong.aisheng@linaro.org> + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/slab.h> + +#include "core.h" +#include "pinctrl-imx1.h" + +struct imx1_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *base; + const struct imx1_pinctrl_soc_info *info; +}; + +/* + * MX1 register offsets + */ + +#define MX1_DDIR 0x00 +#define MX1_OCR 0x04 +#define MX1_ICONFA 0x0c +#define MX1_ICONFB 0x14 +#define MX1_GIUS 0x20 +#define MX1_GPR 0x38 +#define MX1_PUEN 0x40 + +#define MX1_PORT_STRIDE 0x100 + + +/* + * MUX_ID format defines + */ +#define MX1_MUX_FUNCTION(val) (BIT(0) & val) +#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1) +#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2) +#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4) +#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8) +#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10) + + +/* + * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX + * control register are seperated into function, output configuration, input + * configuration A, input configuration B, GPIO in use and data direction. + * + * Those controls that are represented by 1 bit have a direct mapping between + * bit position and pin id. If they are represented by 2 bit, the lower 16 pins + * are in the first register and the upper 16 pins in the second (next) + * register. pin_id is stored in bit (pin_id%16)*2 and the bit above. + */ + +/* + * Calculates the register offset from a pin_id + */ +static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id) +{ + unsigned int port = pin_id / 32; + return ipctl->base + port * MX1_PORT_STRIDE; +} + +/* + * Write to a register with 2 bits per pin. The function will automatically + * use the next register if the pin is managed in the second register. + */ +static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, + u32 value, u32 reg_offset) +{ + void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; + int offset = (pin_id % 16) * 2; /* offset, regardless of register used */ + int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */ + u32 old_val; + u32 new_val; + + /* Use the next register if the pin's port pin number is >=16 */ + if (pin_id % 32 >= 16) + reg += 0x04; + + dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", + reg, offset, value); + + /* Get current state of pins */ + old_val = readl(reg); + old_val &= mask; + + new_val = value & 0x3; /* Make sure value is really 2 bit */ + new_val <<= offset; + new_val |= old_val;/* Set new state for pin_id */ + + writel(new_val, reg); +} + +static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, + u32 value, u32 reg_offset) +{ + void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; + int offset = pin_id % 32; + int mask = ~BIT_MASK(offset); + u32 old_val; + u32 new_val; + + /* Get current state of pins */ + old_val = readl(reg); + old_val &= mask; + + new_val = value & 0x1; /* Make sure value is really 1 bit */ + new_val <<= offset; + new_val |= old_val;/* Set new state for pin_id */ + + writel(new_val, reg); +} + +static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, + u32 reg_offset) +{ + void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; + int offset = (pin_id % 16) * 2; + + /* Use the next register if the pin's port pin number is >=16 */ + if (pin_id % 32 >= 16) + reg += 0x04; + + return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset; +} + +static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, + u32 reg_offset) +{ + void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; + int offset = pin_id % 32; + + return !!(readl(reg) & BIT(offset)); +} + +static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name( + const struct imx1_pinctrl_soc_info *info, + const char *name) +{ + const struct imx1_pin_group *grp = NULL; + int i; + + for (i = 0; i < info->ngroups; i++) { + if (!strcmp(info->groups[i].name, name)) { + grp = &info->groups[i]; + break; + } + } + + return grp; +} + +static int imx1_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + return info->ngroups; +} + +static const char *imx1_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + return info->groups[selector].name; +} + +static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + const unsigned int **pins, + unsigned *npins) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pin_ids; + *npins = info->groups[selector].npins; + + return 0; +} + +static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned offset) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + + seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d", + imx1_read_bit(ipctl, offset, MX1_GIUS), + imx1_read_bit(ipctl, offset, MX1_GPR), + imx1_read_bit(ipctl, offset, MX1_DDIR), + imx1_read_2bit(ipctl, offset, MX1_OCR), + imx1_read_2bit(ipctl, offset, MX1_ICONFA), + imx1_read_2bit(ipctl, offset, MX1_ICONFB)); +} + +static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + const struct imx1_pin_group *grp; + struct pinctrl_map *new_map; + struct device_node *parent; + int map_num = 1; + int i, j; + + /* + * first find the group of this node and check if we need create + * config maps for pins + */ + grp = imx1_pinctrl_find_group_by_name(info, np->name); + if (!grp) { + dev_err(info->dev, "unable to find group for node %s\n", + np->name); + return -EINVAL; + } + + for (i = 0; i < grp->npins; i++) + map_num++; + + new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + *map = new_map; + *num_maps = map_num; + + /* create mux map */ + parent = of_get_parent(np); + if (!parent) { + kfree(new_map); + return -EINVAL; + } + new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; + new_map[0].data.mux.function = parent->name; + new_map[0].data.mux.group = np->name; + of_node_put(parent); + + /* create config map */ + new_map++; + for (i = j = 0; i < grp->npins; i++) { + new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[j].data.configs.group_or_pin = + pin_get_name(pctldev, grp->pins[i].pin_id); + new_map[j].data.configs.configs = &grp->pins[i].config; + new_map[j].data.configs.num_configs = 1; + j++; + } + + dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", + (*map)->data.mux.function, (*map)->data.mux.group, map_num); + + return 0; +} + +static void imx1_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops imx1_pctrl_ops = { + .get_groups_count = imx1_get_groups_count, + .get_group_name = imx1_get_group_name, + .get_group_pins = imx1_get_group_pins, + .pin_dbg_show = imx1_pin_dbg_show, + .dt_node_to_map = imx1_dt_node_to_map, + .dt_free_map = imx1_dt_free_map, + +}; + +static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + const struct imx1_pin *pins; + unsigned int npins; + int i; + + /* + * Configure the mux mode for each pin in the group for a specific + * function. + */ + pins = info->groups[group].pins; + npins = info->groups[group].npins; + + WARN_ON(!pins || !npins); + + dev_dbg(ipctl->dev, "enable function %s group %s\n", + info->functions[selector].name, info->groups[group].name); + + for (i = 0; i < npins; i++) { + unsigned int mux = pins[i].mux_id; + unsigned int pin_id = pins[i].pin_id; + unsigned int afunction = MX1_MUX_FUNCTION(mux); + unsigned int gpio_in_use = MX1_MUX_GPIO(mux); + unsigned int direction = MX1_MUX_DIR(mux); + unsigned int gpio_oconf = MX1_MUX_OCONF(mux); + unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux); + unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux); + + dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n", + __func__, pin_id, afunction, gpio_in_use, + direction, gpio_oconf, gpio_iconfa, + gpio_iconfb); + + imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS); + imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR); + + if (gpio_in_use) { + imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR); + imx1_write_2bit(ipctl, pin_id, gpio_iconfa, + MX1_ICONFA); + imx1_write_2bit(ipctl, pin_id, gpio_iconfb, + MX1_ICONFB); + } else { + imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR); + } + } + + return 0; +} + +static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + return info->nfunctions; +} + +static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + return info->functions[selector].name; +} + +static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + + *groups = info->functions[selector].groups; + *num_groups = info->functions[selector].num_groups; + + return 0; +} + +static const struct pinmux_ops imx1_pmx_ops = { + .get_functions_count = imx1_pmx_get_funcs_count, + .get_function_name = imx1_pmx_get_func_name, + .get_function_groups = imx1_pmx_get_groups, + .enable = imx1_pmx_enable, +}; + +static int imx1_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *config) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + + *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN); + + return 0; +} + +static int imx1_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *configs, + unsigned num_configs) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + int i; + + for (i = 0; i != num_configs; ++i) { + imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN); + + dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n", + info->pins[pin_id].name); + } + + return 0; +} + +static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin_id) +{ + unsigned long config; + + imx1_pinconf_get(pctldev, pin_id, &config); + seq_printf(s, "0x%lx", config); +} + +static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned group) +{ + struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx1_pinctrl_soc_info *info = ipctl->info; + struct imx1_pin_group *grp; + unsigned long config; + const char *name; + int i, ret; + + if (group > info->ngroups) + return; + + seq_puts(s, "\n"); + grp = &info->groups[group]; + for (i = 0; i < grp->npins; i++) { + name = pin_get_name(pctldev, grp->pins[i].pin_id); + ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config); + if (ret) + return; + seq_printf(s, "%s: 0x%lx", name, config); + } +} + +static const struct pinconf_ops imx1_pinconf_ops = { + .pin_config_get = imx1_pinconf_get, + .pin_config_set = imx1_pinconf_set, + .pin_config_dbg_show = imx1_pinconf_dbg_show, + .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show, +}; + +static struct pinctrl_desc imx1_pinctrl_desc = { + .pctlops = &imx1_pctrl_ops, + .pmxops = &imx1_pmx_ops, + .confops = &imx1_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int imx1_pinctrl_parse_groups(struct device_node *np, + struct imx1_pin_group *grp, + struct imx1_pinctrl_soc_info *info, + u32 index) +{ + int size; + const __be32 *list; + int i; + + dev_dbg(info->dev, "group(%d): %s\n", index, np->name); + + /* Initialise group */ + grp->name = np->name; + + /* + * the binding format is fsl,pins = <PIN MUX_ID CONFIG> + */ + list = of_get_property(np, "fsl,pins", &size); + /* we do not check return since it's safe node passed down */ + if (!size || size % 12) { + dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n", + np->name); + return -EINVAL; + } + + grp->npins = size / 12; + grp->pins = devm_kzalloc(info->dev, + grp->npins * sizeof(struct imx1_pin), GFP_KERNEL); + grp->pin_ids = devm_kzalloc(info->dev, + grp->npins * sizeof(unsigned int), GFP_KERNEL); + + if (!grp->pins || !grp->pin_ids) + return -ENOMEM; + + for (i = 0; i < grp->npins; i++) { + grp->pins[i].pin_id = be32_to_cpu(*list++); + grp->pins[i].mux_id = be32_to_cpu(*list++); + grp->pins[i].config = be32_to_cpu(*list++); + + grp->pin_ids[i] = grp->pins[i].pin_id; + } + + return 0; +} + +static int imx1_pinctrl_parse_functions(struct device_node *np, + struct imx1_pinctrl_soc_info *info, + u32 index) +{ + struct device_node *child; + struct imx1_pmx_func *func; + struct imx1_pin_group *grp; + int ret; + static u32 grp_index; + u32 i = 0; + + dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); + + func = &info->functions[index]; + + /* Initialise function */ + func->name = np->name; + func->num_groups = of_get_child_count(np); + if (func->num_groups <= 0) + return -EINVAL; + + func->groups = devm_kzalloc(info->dev, + func->num_groups * sizeof(char *), GFP_KERNEL); + + if (!func->groups) + return -ENOMEM; + + for_each_child_of_node(np, child) { + func->groups[i] = child->name; + grp = &info->groups[grp_index++]; + ret = imx1_pinctrl_parse_groups(child, grp, info, i++); + if (ret == -ENOMEM) + return ret; + } + + return 0; +} + +static int imx1_pinctrl_parse_dt(struct platform_device *pdev, + struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info) +{ + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + int ret; + u32 nfuncs = 0; + u32 ngroups = 0; + u32 ifunc = 0; + + if (!np) + return -ENODEV; + + for_each_child_of_node(np, child) { + ++nfuncs; + ngroups += of_get_child_count(child); + } + + if (!nfuncs) { + dev_err(&pdev->dev, "No pin functions defined\n"); + return -EINVAL; + } + + info->nfunctions = nfuncs; + info->functions = devm_kzalloc(&pdev->dev, + nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL); + + info->ngroups = ngroups; + info->groups = devm_kzalloc(&pdev->dev, + ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL); + + + if (!info->functions || !info->groups) + return -ENOMEM; + + for_each_child_of_node(np, child) { + ret = imx1_pinctrl_parse_functions(child, info, ifunc++); + if (ret == -ENOMEM) + return -ENOMEM; + } + + return 0; +} + +int imx1_pinctrl_core_probe(struct platform_device *pdev, + struct imx1_pinctrl_soc_info *info) +{ + struct imx1_pinctrl *ipctl; + struct resource *res; + struct pinctrl_desc *pctl_desc; + int ret; + + if (!info || !info->pins || !info->npins) { + dev_err(&pdev->dev, "wrong pinctrl info\n"); + return -EINVAL; + } + info->dev = &pdev->dev; + + /* Create state holders etc for this driver */ + ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); + if (!ipctl) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOENT; + + ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ipctl->base) + return -ENOMEM; + + pctl_desc = &imx1_pinctrl_desc; + pctl_desc->name = dev_name(&pdev->dev); + pctl_desc->pins = info->pins; + pctl_desc->npins = info->npins; + + ret = imx1_pinctrl_parse_dt(pdev, ipctl, info); + if (ret) { + dev_err(&pdev->dev, "fail to probe dt properties\n"); + return ret; + } + + ipctl->info = info; + ipctl->dev = info->dev; + platform_set_drvdata(pdev, ipctl); + ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl); + if (!ipctl->pctl) { + dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); + return -EINVAL; + } + + ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (ret) { + pinctrl_unregister(ipctl->pctl); + dev_err(&pdev->dev, "Failed to populate subdevices\n"); + return ret; + } + + dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); + + return 0; +} + +int imx1_pinctrl_core_remove(struct platform_device *pdev) +{ + struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev); + + pinctrl_unregister(ipctl->pctl); + + return 0; +} diff --git a/drivers/pinctrl/pinctrl-imx1.h b/drivers/pinctrl/pinctrl-imx1.h new file mode 100644 index 00000000000..692a54c15cd --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx1.h @@ -0,0 +1,73 @@ +/* + * IMX pinmux core definitions + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro Ltd. + * + * Author: Dong Aisheng <dong.aisheng@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DRIVERS_PINCTRL_IMX1_H +#define __DRIVERS_PINCTRL_IMX1_H + +struct platform_device; + +/** + * struct imx1_pin - describes an IMX1/21/27 pin. + * @pin_id: ID of the described pin. + * @mux_id: ID of the mux setup. + * @config: Configuration of the pin (currently only pullup-enable). + */ +struct imx1_pin { + unsigned int pin_id; + unsigned int mux_id; + unsigned long config; +}; + +/** + * struct imx1_pin_group - describes an IMX pin group + * @name: the name of this specific pin group + * @pins: an array of imx1_pin structs used in this group + * @npins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + */ +struct imx1_pin_group { + const char *name; + unsigned int *pin_ids; + struct imx1_pin *pins; + unsigned npins; +}; + +/** + * struct imx1_pmx_func - describes IMX pinmux functions + * @name: the name of this specific function + * @groups: corresponding pin groups + * @num_groups: the number of groups + */ +struct imx1_pmx_func { + const char *name; + const char **groups; + unsigned num_groups; +}; + +struct imx1_pinctrl_soc_info { + struct device *dev; + const struct pinctrl_pin_desc *pins; + unsigned int npins; + struct imx1_pin_group *groups; + unsigned int ngroups; + struct imx1_pmx_func *functions; + unsigned int nfunctions; +}; + +#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) + +int imx1_pinctrl_core_probe(struct platform_device *pdev, + struct imx1_pinctrl_soc_info *info); +int imx1_pinctrl_core_remove(struct platform_device *pdev); +#endif /* __DRIVERS_PINCTRL_IMX1_H */ diff --git a/drivers/pinctrl/pinctrl-imx25.c b/drivers/pinctrl/pinctrl-imx25.c new file mode 100644 index 00000000000..1aae1b61c4d --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx25.c @@ -0,0 +1,351 @@ +/* + * imx25 pinctrl driver. + * + * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> + * + * This driver was mostly copied from the imx51 pinctrl driver which has: + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro, Inc. + * + * Author: Denis Carikli <denis@eukrea.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum imx25_pads { + MX25_PAD_RESERVE0 = 1, + MX25_PAD_RESERVE1 = 2, + MX25_PAD_A10 = 3, + MX25_PAD_A13 = 4, + MX25_PAD_A14 = 5, + MX25_PAD_A15 = 6, + MX25_PAD_A16 = 7, + MX25_PAD_A17 = 8, + MX25_PAD_A18 = 9, + MX25_PAD_A19 = 10, + MX25_PAD_A20 = 11, + MX25_PAD_A21 = 12, + MX25_PAD_A22 = 13, + MX25_PAD_A23 = 14, + MX25_PAD_A24 = 15, + MX25_PAD_A25 = 16, + MX25_PAD_EB0 = 17, + MX25_PAD_EB1 = 18, + MX25_PAD_OE = 19, + MX25_PAD_CS0 = 20, + MX25_PAD_CS1 = 21, + MX25_PAD_CS4 = 22, + MX25_PAD_CS5 = 23, + MX25_PAD_NF_CE0 = 24, + MX25_PAD_ECB = 25, + MX25_PAD_LBA = 26, + MX25_PAD_BCLK = 27, + MX25_PAD_RW = 28, + MX25_PAD_NFWE_B = 29, + MX25_PAD_NFRE_B = 30, + MX25_PAD_NFALE = 31, + MX25_PAD_NFCLE = 32, + MX25_PAD_NFWP_B = 33, + MX25_PAD_NFRB = 34, + MX25_PAD_D15 = 35, + MX25_PAD_D14 = 36, + MX25_PAD_D13 = 37, + MX25_PAD_D12 = 38, + MX25_PAD_D11 = 39, + MX25_PAD_D10 = 40, + MX25_PAD_D9 = 41, + MX25_PAD_D8 = 42, + MX25_PAD_D7 = 43, + MX25_PAD_D6 = 44, + MX25_PAD_D5 = 45, + MX25_PAD_D4 = 46, + MX25_PAD_D3 = 47, + MX25_PAD_D2 = 48, + MX25_PAD_D1 = 49, + MX25_PAD_D0 = 50, + MX25_PAD_LD0 = 51, + MX25_PAD_LD1 = 52, + MX25_PAD_LD2 = 53, + MX25_PAD_LD3 = 54, + MX25_PAD_LD4 = 55, + MX25_PAD_LD5 = 56, + MX25_PAD_LD6 = 57, + MX25_PAD_LD7 = 58, + MX25_PAD_LD8 = 59, + MX25_PAD_LD9 = 60, + MX25_PAD_LD10 = 61, + MX25_PAD_LD11 = 62, + MX25_PAD_LD12 = 63, + MX25_PAD_LD13 = 64, + MX25_PAD_LD14 = 65, + MX25_PAD_LD15 = 66, + MX25_PAD_HSYNC = 67, + MX25_PAD_VSYNC = 68, + MX25_PAD_LSCLK = 69, + MX25_PAD_OE_ACD = 70, + MX25_PAD_CONTRAST = 71, + MX25_PAD_PWM = 72, + MX25_PAD_CSI_D2 = 73, + MX25_PAD_CSI_D3 = 74, + MX25_PAD_CSI_D4 = 75, + MX25_PAD_CSI_D5 = 76, + MX25_PAD_CSI_D6 = 77, + MX25_PAD_CSI_D7 = 78, + MX25_PAD_CSI_D8 = 79, + MX25_PAD_CSI_D9 = 80, + MX25_PAD_CSI_MCLK = 81, + MX25_PAD_CSI_VSYNC = 82, + MX25_PAD_CSI_HSYNC = 83, + MX25_PAD_CSI_PIXCLK = 84, + MX25_PAD_I2C1_CLK = 85, + MX25_PAD_I2C1_DAT = 86, + MX25_PAD_CSPI1_MOSI = 87, + MX25_PAD_CSPI1_MISO = 88, + MX25_PAD_CSPI1_SS0 = 89, + MX25_PAD_CSPI1_SS1 = 90, + MX25_PAD_CSPI1_SCLK = 91, + MX25_PAD_CSPI1_RDY = 92, + MX25_PAD_UART1_RXD = 93, + MX25_PAD_UART1_TXD = 94, + MX25_PAD_UART1_RTS = 95, + MX25_PAD_UART1_CTS = 96, + MX25_PAD_UART2_RXD = 97, + MX25_PAD_UART2_TXD = 98, + MX25_PAD_UART2_RTS = 99, + MX25_PAD_UART2_CTS = 100, + MX25_PAD_SD1_CMD = 101, + MX25_PAD_SD1_CLK = 102, + MX25_PAD_SD1_DATA0 = 103, + MX25_PAD_SD1_DATA1 = 104, + MX25_PAD_SD1_DATA2 = 105, + MX25_PAD_SD1_DATA3 = 106, + MX25_PAD_KPP_ROW0 = 107, + MX25_PAD_KPP_ROW1 = 108, + MX25_PAD_KPP_ROW2 = 109, + MX25_PAD_KPP_ROW3 = 110, + MX25_PAD_KPP_COL0 = 111, + MX25_PAD_KPP_COL1 = 112, + MX25_PAD_KPP_COL2 = 113, + MX25_PAD_KPP_COL3 = 114, + MX25_PAD_FEC_MDC = 115, + MX25_PAD_FEC_MDIO = 116, + MX25_PAD_FEC_TDATA0 = 117, + MX25_PAD_FEC_TDATA1 = 118, + MX25_PAD_FEC_TX_EN = 119, + MX25_PAD_FEC_RDATA0 = 120, + MX25_PAD_FEC_RDATA1 = 121, + MX25_PAD_FEC_RX_DV = 122, + MX25_PAD_FEC_TX_CLK = 123, + MX25_PAD_RTCK = 124, + MX25_PAD_DE_B = 125, + MX25_PAD_GPIO_A = 126, + MX25_PAD_GPIO_B = 127, + MX25_PAD_GPIO_C = 128, + MX25_PAD_GPIO_D = 129, + MX25_PAD_GPIO_E = 130, + MX25_PAD_GPIO_F = 131, + MX25_PAD_EXT_ARMCLK = 132, + MX25_PAD_UPLL_BYPCLK = 133, + MX25_PAD_VSTBY_REQ = 134, + MX25_PAD_VSTBY_ACK = 135, + MX25_PAD_POWER_FAIL = 136, + MX25_PAD_CLKO = 137, + MX25_PAD_BOOT_MODE0 = 138, + MX25_PAD_BOOT_MODE1 = 139, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX25_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX25_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX25_PAD_A10), + IMX_PINCTRL_PIN(MX25_PAD_A13), + IMX_PINCTRL_PIN(MX25_PAD_A14), + IMX_PINCTRL_PIN(MX25_PAD_A15), + IMX_PINCTRL_PIN(MX25_PAD_A16), + IMX_PINCTRL_PIN(MX25_PAD_A17), + IMX_PINCTRL_PIN(MX25_PAD_A18), + IMX_PINCTRL_PIN(MX25_PAD_A19), + IMX_PINCTRL_PIN(MX25_PAD_A20), + IMX_PINCTRL_PIN(MX25_PAD_A21), + IMX_PINCTRL_PIN(MX25_PAD_A22), + IMX_PINCTRL_PIN(MX25_PAD_A23), + IMX_PINCTRL_PIN(MX25_PAD_A24), + IMX_PINCTRL_PIN(MX25_PAD_A25), + IMX_PINCTRL_PIN(MX25_PAD_EB0), + IMX_PINCTRL_PIN(MX25_PAD_EB1), + IMX_PINCTRL_PIN(MX25_PAD_OE), + IMX_PINCTRL_PIN(MX25_PAD_CS0), + IMX_PINCTRL_PIN(MX25_PAD_CS1), + IMX_PINCTRL_PIN(MX25_PAD_CS4), + IMX_PINCTRL_PIN(MX25_PAD_CS5), + IMX_PINCTRL_PIN(MX25_PAD_NF_CE0), + IMX_PINCTRL_PIN(MX25_PAD_ECB), + IMX_PINCTRL_PIN(MX25_PAD_LBA), + IMX_PINCTRL_PIN(MX25_PAD_BCLK), + IMX_PINCTRL_PIN(MX25_PAD_RW), + IMX_PINCTRL_PIN(MX25_PAD_NFWE_B), + IMX_PINCTRL_PIN(MX25_PAD_NFRE_B), + IMX_PINCTRL_PIN(MX25_PAD_NFALE), + IMX_PINCTRL_PIN(MX25_PAD_NFCLE), + IMX_PINCTRL_PIN(MX25_PAD_NFWP_B), + IMX_PINCTRL_PIN(MX25_PAD_NFRB), + IMX_PINCTRL_PIN(MX25_PAD_D15), + IMX_PINCTRL_PIN(MX25_PAD_D14), + IMX_PINCTRL_PIN(MX25_PAD_D13), + IMX_PINCTRL_PIN(MX25_PAD_D12), + IMX_PINCTRL_PIN(MX25_PAD_D11), + IMX_PINCTRL_PIN(MX25_PAD_D10), + IMX_PINCTRL_PIN(MX25_PAD_D9), + IMX_PINCTRL_PIN(MX25_PAD_D8), + IMX_PINCTRL_PIN(MX25_PAD_D7), + IMX_PINCTRL_PIN(MX25_PAD_D6), + IMX_PINCTRL_PIN(MX25_PAD_D5), + IMX_PINCTRL_PIN(MX25_PAD_D4), + IMX_PINCTRL_PIN(MX25_PAD_D3), + IMX_PINCTRL_PIN(MX25_PAD_D2), + IMX_PINCTRL_PIN(MX25_PAD_D1), + IMX_PINCTRL_PIN(MX25_PAD_D0), + IMX_PINCTRL_PIN(MX25_PAD_LD0), + IMX_PINCTRL_PIN(MX25_PAD_LD1), + IMX_PINCTRL_PIN(MX25_PAD_LD2), + IMX_PINCTRL_PIN(MX25_PAD_LD3), + IMX_PINCTRL_PIN(MX25_PAD_LD4), + IMX_PINCTRL_PIN(MX25_PAD_LD5), + IMX_PINCTRL_PIN(MX25_PAD_LD6), + IMX_PINCTRL_PIN(MX25_PAD_LD7), + IMX_PINCTRL_PIN(MX25_PAD_LD8), + IMX_PINCTRL_PIN(MX25_PAD_LD9), + IMX_PINCTRL_PIN(MX25_PAD_LD10), + IMX_PINCTRL_PIN(MX25_PAD_LD11), + IMX_PINCTRL_PIN(MX25_PAD_LD12), + IMX_PINCTRL_PIN(MX25_PAD_LD13), + IMX_PINCTRL_PIN(MX25_PAD_LD14), + IMX_PINCTRL_PIN(MX25_PAD_LD15), + IMX_PINCTRL_PIN(MX25_PAD_HSYNC), + IMX_PINCTRL_PIN(MX25_PAD_VSYNC), + IMX_PINCTRL_PIN(MX25_PAD_LSCLK), + IMX_PINCTRL_PIN(MX25_PAD_OE_ACD), + IMX_PINCTRL_PIN(MX25_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX25_PAD_PWM), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D2), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D3), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D4), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D5), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D6), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D7), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D8), + IMX_PINCTRL_PIN(MX25_PAD_CSI_D9), + IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK), + IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK), + IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY), + IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0), + IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1), + IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2), + IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3), + IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0), + IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1), + IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2), + IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3), + IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC), + IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO), + IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0), + IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1), + IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN), + IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0), + IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1), + IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV), + IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK), + IMX_PINCTRL_PIN(MX25_PAD_RTCK), + IMX_PINCTRL_PIN(MX25_PAD_DE_B), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_A), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_B), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_C), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_D), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_E), + IMX_PINCTRL_PIN(MX25_PAD_GPIO_F), + IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK), + IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK), + IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ), + IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK), + IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL), + IMX_PINCTRL_PIN(MX25_PAD_CLKO), + IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0), + IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1), +}; + +static struct imx_pinctrl_soc_info imx25_pinctrl_info = { + .pins = imx25_pinctrl_pads, + .npins = ARRAY_SIZE(imx25_pinctrl_pads), +}; + +static struct of_device_id imx25_pinctrl_of_match[] = { + { .compatible = "fsl,imx25-iomuxc", }, + { /* sentinel */ } +}; + +static int imx25_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx25_pinctrl_info); +} + +static struct platform_driver imx25_pinctrl_driver = { + .driver = { + .name = "imx25-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx25_pinctrl_of_match), + }, + .probe = imx25_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx25_pinctrl_init(void) +{ + return platform_driver_register(&imx25_pinctrl_driver); +} +arch_initcall(imx25_pinctrl_init); + +static void __exit imx25_pinctrl_exit(void) +{ + platform_driver_unregister(&imx25_pinctrl_driver); +} +module_exit(imx25_pinctrl_exit); +MODULE_AUTHOR("Denis Carikli <denis@eukrea.com>"); +MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c new file mode 100644 index 00000000000..417c99205bc --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx27.c @@ -0,0 +1,477 @@ +/* + * imx27 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2013 Pengutronix + * + * Author: Markus Pargmann <mpa@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx1.h" + +#define PAD_ID(port, pin) (port*32 + pin) +#define PA 0 +#define PB 1 +#define PC 2 +#define PD 3 +#define PE 4 +#define PF 5 + +enum imx27_pads { + MX27_PAD_USBH2_CLK = PAD_ID(PA, 0), + MX27_PAD_USBH2_DIR = PAD_ID(PA, 1), + MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2), + MX27_PAD_USBH2_NXT = PAD_ID(PA, 3), + MX27_PAD_USBH2_STP = PAD_ID(PA, 4), + MX27_PAD_LSCLK = PAD_ID(PA, 5), + MX27_PAD_LD0 = PAD_ID(PA, 6), + MX27_PAD_LD1 = PAD_ID(PA, 7), + MX27_PAD_LD2 = PAD_ID(PA, 8), + MX27_PAD_LD3 = PAD_ID(PA, 9), + MX27_PAD_LD4 = PAD_ID(PA, 10), + MX27_PAD_LD5 = PAD_ID(PA, 11), + MX27_PAD_LD6 = PAD_ID(PA, 12), + MX27_PAD_LD7 = PAD_ID(PA, 13), + MX27_PAD_LD8 = PAD_ID(PA, 14), + MX27_PAD_LD9 = PAD_ID(PA, 15), + MX27_PAD_LD10 = PAD_ID(PA, 16), + MX27_PAD_LD11 = PAD_ID(PA, 17), + MX27_PAD_LD12 = PAD_ID(PA, 18), + MX27_PAD_LD13 = PAD_ID(PA, 19), + MX27_PAD_LD14 = PAD_ID(PA, 20), + MX27_PAD_LD15 = PAD_ID(PA, 21), + MX27_PAD_LD16 = PAD_ID(PA, 22), + MX27_PAD_LD17 = PAD_ID(PA, 23), + MX27_PAD_REV = PAD_ID(PA, 24), + MX27_PAD_CLS = PAD_ID(PA, 25), + MX27_PAD_PS = PAD_ID(PA, 26), + MX27_PAD_SPL_SPR = PAD_ID(PA, 27), + MX27_PAD_HSYNC = PAD_ID(PA, 28), + MX27_PAD_VSYNC = PAD_ID(PA, 29), + MX27_PAD_CONTRAST = PAD_ID(PA, 30), + MX27_PAD_OE_ACD = PAD_ID(PA, 31), + + MX27_PAD_UNUSED0 = PAD_ID(PB, 0), + MX27_PAD_UNUSED1 = PAD_ID(PB, 1), + MX27_PAD_UNUSED2 = PAD_ID(PB, 2), + MX27_PAD_UNUSED3 = PAD_ID(PB, 3), + MX27_PAD_SD2_D0 = PAD_ID(PB, 4), + MX27_PAD_SD2_D1 = PAD_ID(PB, 5), + MX27_PAD_SD2_D2 = PAD_ID(PB, 6), + MX27_PAD_SD2_D3 = PAD_ID(PB, 7), + MX27_PAD_SD2_CMD = PAD_ID(PB, 8), + MX27_PAD_SD2_CLK = PAD_ID(PB, 9), + MX27_PAD_CSI_D0 = PAD_ID(PB, 10), + MX27_PAD_CSI_D1 = PAD_ID(PB, 11), + MX27_PAD_CSI_D2 = PAD_ID(PB, 12), + MX27_PAD_CSI_D3 = PAD_ID(PB, 13), + MX27_PAD_CSI_D4 = PAD_ID(PB, 14), + MX27_PAD_CSI_MCLK = PAD_ID(PB, 15), + MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16), + MX27_PAD_CSI_D5 = PAD_ID(PB, 17), + MX27_PAD_CSI_D6 = PAD_ID(PB, 18), + MX27_PAD_CSI_D7 = PAD_ID(PB, 19), + MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20), + MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21), + MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22), + MX27_PAD_USB_PWR = PAD_ID(PB, 23), + MX27_PAD_USB_OC_B = PAD_ID(PB, 24), + MX27_PAD_USBH1_RCV = PAD_ID(PB, 25), + MX27_PAD_USBH1_FS = PAD_ID(PB, 26), + MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27), + MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28), + MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29), + MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30), + MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31), + + MX27_PAD_UNUSED4 = PAD_ID(PC, 0), + MX27_PAD_UNUSED5 = PAD_ID(PC, 1), + MX27_PAD_UNUSED6 = PAD_ID(PC, 2), + MX27_PAD_UNUSED7 = PAD_ID(PC, 3), + MX27_PAD_UNUSED8 = PAD_ID(PC, 4), + MX27_PAD_I2C2_SDA = PAD_ID(PC, 5), + MX27_PAD_I2C2_SCL = PAD_ID(PC, 6), + MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7), + MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8), + MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9), + MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10), + MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11), + MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12), + MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13), + MX27_PAD_TOUT = PAD_ID(PC, 14), + MX27_PAD_TIN = PAD_ID(PC, 15), + MX27_PAD_SSI4_FS = PAD_ID(PC, 16), + MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17), + MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18), + MX27_PAD_SSI4_CLK = PAD_ID(PC, 19), + MX27_PAD_SSI1_FS = PAD_ID(PC, 20), + MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21), + MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22), + MX27_PAD_SSI1_CLK = PAD_ID(PC, 23), + MX27_PAD_SSI2_FS = PAD_ID(PC, 24), + MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25), + MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26), + MX27_PAD_SSI2_CLK = PAD_ID(PC, 27), + MX27_PAD_SSI3_FS = PAD_ID(PC, 28), + MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29), + MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30), + MX27_PAD_SSI3_CLK = PAD_ID(PC, 31), + + MX27_PAD_SD3_CMD = PAD_ID(PD, 0), + MX27_PAD_SD3_CLK = PAD_ID(PD, 1), + MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2), + MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3), + MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4), + MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5), + MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6), + MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7), + MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8), + MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9), + MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10), + MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11), + MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12), + MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13), + MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14), + MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15), + MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16), + MX27_PAD_I2C_DATA = PAD_ID(PD, 17), + MX27_PAD_I2C_CLK = PAD_ID(PD, 18), + MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19), + MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20), + MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21), + MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22), + MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23), + MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24), + MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25), + MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26), + MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27), + MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28), + MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29), + MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30), + MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31), + + MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0), + MX27_PAD_USBOTG_STP = PAD_ID(PE, 1), + MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2), + MX27_PAD_UART2_CTS = PAD_ID(PE, 3), + MX27_PAD_UART2_RTS = PAD_ID(PE, 4), + MX27_PAD_PWMO = PAD_ID(PE, 5), + MX27_PAD_UART2_TXD = PAD_ID(PE, 6), + MX27_PAD_UART2_RXD = PAD_ID(PE, 7), + MX27_PAD_UART3_TXD = PAD_ID(PE, 8), + MX27_PAD_UART3_RXD = PAD_ID(PE, 9), + MX27_PAD_UART3_CTS = PAD_ID(PE, 10), + MX27_PAD_UART3_RTS = PAD_ID(PE, 11), + MX27_PAD_UART1_TXD = PAD_ID(PE, 12), + MX27_PAD_UART1_RXD = PAD_ID(PE, 13), + MX27_PAD_UART1_CTS = PAD_ID(PE, 14), + MX27_PAD_UART1_RTS = PAD_ID(PE, 15), + MX27_PAD_RTCK = PAD_ID(PE, 16), + MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17), + MX27_PAD_SD1_D0 = PAD_ID(PE, 18), + MX27_PAD_SD1_D1 = PAD_ID(PE, 19), + MX27_PAD_SD1_D2 = PAD_ID(PE, 20), + MX27_PAD_SD1_D3 = PAD_ID(PE, 21), + MX27_PAD_SD1_CMD = PAD_ID(PE, 22), + MX27_PAD_SD1_CLK = PAD_ID(PE, 23), + MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24), + MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25), + MX27_PAD_UNUSED9 = PAD_ID(PE, 26), + MX27_PAD_UNUSED10 = PAD_ID(PE, 27), + MX27_PAD_UNUSED11 = PAD_ID(PE, 28), + MX27_PAD_UNUSED12 = PAD_ID(PE, 29), + MX27_PAD_UNUSED13 = PAD_ID(PE, 30), + MX27_PAD_UNUSED14 = PAD_ID(PE, 31), + + MX27_PAD_NFRB = PAD_ID(PF, 0), + MX27_PAD_NFCLE = PAD_ID(PF, 1), + MX27_PAD_NFWP_B = PAD_ID(PF, 2), + MX27_PAD_NFCE_B = PAD_ID(PF, 3), + MX27_PAD_NFALE = PAD_ID(PF, 4), + MX27_PAD_NFRE_B = PAD_ID(PF, 5), + MX27_PAD_NFWE_B = PAD_ID(PF, 6), + MX27_PAD_PC_POE = PAD_ID(PF, 7), + MX27_PAD_PC_RW_B = PAD_ID(PF, 8), + MX27_PAD_IOIS16 = PAD_ID(PF, 9), + MX27_PAD_PC_RST = PAD_ID(PF, 10), + MX27_PAD_PC_BVD2 = PAD_ID(PF, 11), + MX27_PAD_PC_BVD1 = PAD_ID(PF, 12), + MX27_PAD_PC_VS2 = PAD_ID(PF, 13), + MX27_PAD_PC_VS1 = PAD_ID(PF, 14), + MX27_PAD_CLKO = PAD_ID(PF, 15), + MX27_PAD_PC_PWRON = PAD_ID(PF, 16), + MX27_PAD_PC_READY = PAD_ID(PF, 17), + MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18), + MX27_PAD_PC_CD2_B = PAD_ID(PF, 19), + MX27_PAD_PC_CD1_B = PAD_ID(PF, 20), + MX27_PAD_CS4_B = PAD_ID(PF, 21), + MX27_PAD_CS5_B = PAD_ID(PF, 22), + MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23), + MX27_PAD_UNUSED15 = PAD_ID(PF, 24), + MX27_PAD_UNUSED16 = PAD_ID(PF, 25), + MX27_PAD_UNUSED17 = PAD_ID(PF, 26), + MX27_PAD_UNUSED18 = PAD_ID(PF, 27), + MX27_PAD_UNUSED19 = PAD_ID(PF, 28), + MX27_PAD_UNUSED20 = PAD_ID(PF, 29), + MX27_PAD_UNUSED21 = PAD_ID(PF, 30), + MX27_PAD_UNUSED22 = PAD_ID(PF, 31), +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP), + IMX_PINCTRL_PIN(MX27_PAD_LSCLK), + IMX_PINCTRL_PIN(MX27_PAD_LD0), + IMX_PINCTRL_PIN(MX27_PAD_LD1), + IMX_PINCTRL_PIN(MX27_PAD_LD2), + IMX_PINCTRL_PIN(MX27_PAD_LD3), + IMX_PINCTRL_PIN(MX27_PAD_LD4), + IMX_PINCTRL_PIN(MX27_PAD_LD5), + IMX_PINCTRL_PIN(MX27_PAD_LD6), + IMX_PINCTRL_PIN(MX27_PAD_LD7), + IMX_PINCTRL_PIN(MX27_PAD_LD8), + IMX_PINCTRL_PIN(MX27_PAD_LD9), + IMX_PINCTRL_PIN(MX27_PAD_LD10), + IMX_PINCTRL_PIN(MX27_PAD_LD11), + IMX_PINCTRL_PIN(MX27_PAD_LD12), + IMX_PINCTRL_PIN(MX27_PAD_LD13), + IMX_PINCTRL_PIN(MX27_PAD_LD14), + IMX_PINCTRL_PIN(MX27_PAD_LD15), + IMX_PINCTRL_PIN(MX27_PAD_LD16), + IMX_PINCTRL_PIN(MX27_PAD_LD17), + IMX_PINCTRL_PIN(MX27_PAD_REV), + IMX_PINCTRL_PIN(MX27_PAD_CLS), + IMX_PINCTRL_PIN(MX27_PAD_PS), + IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR), + IMX_PINCTRL_PIN(MX27_PAD_HSYNC), + IMX_PINCTRL_PIN(MX27_PAD_VSYNC), + IMX_PINCTRL_PIN(MX27_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX27_PAD_OE_ACD), + + IMX_PINCTRL_PIN(MX27_PAD_UNUSED0), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED1), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED2), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED3), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D0), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D1), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D2), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D3), + IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D0), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D1), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D2), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D3), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D4), + IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D5), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D6), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D7), + IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP), + IMX_PINCTRL_PIN(MX27_PAD_USB_PWR), + IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP), + + IMX_PINCTRL_PIN(MX27_PAD_UNUSED4), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED5), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED6), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED7), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED8), + IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA), + IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3), + IMX_PINCTRL_PIN(MX27_PAD_TOUT), + IMX_PINCTRL_PIN(MX27_PAD_TIN), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK), + + IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14), + IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA), + IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI), + + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR), + IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX27_PAD_PWMO), + IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD), + IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD), + IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS), + IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS), + IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX27_PAD_RTCK), + IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D0), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D1), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D2), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D3), + IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED9), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED10), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED11), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED12), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED13), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED14), + + IMX_PINCTRL_PIN(MX27_PAD_NFRB), + IMX_PINCTRL_PIN(MX27_PAD_NFCLE), + IMX_PINCTRL_PIN(MX27_PAD_NFWP_B), + IMX_PINCTRL_PIN(MX27_PAD_NFCE_B), + IMX_PINCTRL_PIN(MX27_PAD_NFALE), + IMX_PINCTRL_PIN(MX27_PAD_NFRE_B), + IMX_PINCTRL_PIN(MX27_PAD_NFWE_B), + IMX_PINCTRL_PIN(MX27_PAD_PC_POE), + IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B), + IMX_PINCTRL_PIN(MX27_PAD_IOIS16), + IMX_PINCTRL_PIN(MX27_PAD_PC_RST), + IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2), + IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1), + IMX_PINCTRL_PIN(MX27_PAD_PC_VS2), + IMX_PINCTRL_PIN(MX27_PAD_PC_VS1), + IMX_PINCTRL_PIN(MX27_PAD_CLKO), + IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON), + IMX_PINCTRL_PIN(MX27_PAD_PC_READY), + IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B), + IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B), + IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B), + IMX_PINCTRL_PIN(MX27_PAD_CS4_B), + IMX_PINCTRL_PIN(MX27_PAD_CS5_B), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED15), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED16), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED17), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED18), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED19), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED20), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED21), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED22), +}; + +static struct imx1_pinctrl_soc_info imx27_pinctrl_info = { + .pins = imx27_pinctrl_pads, + .npins = ARRAY_SIZE(imx27_pinctrl_pads), +}; + +static struct of_device_id imx27_pinctrl_of_match[] = { + { .compatible = "fsl,imx27-iomuxc", }, + { /* sentinel */ } +}; + +struct imx27_pinctrl_private { + int num_gpio_childs; + struct platform_device **gpio_dev; + struct mxc_gpio_platform_data *gpio_pdata; +}; + +static int imx27_pinctrl_probe(struct platform_device *pdev) +{ + return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info); +} + +static struct platform_driver imx27_pinctrl_driver = { + .driver = { + .name = "imx27-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx27_pinctrl_of_match), + }, + .probe = imx27_pinctrl_probe, + .remove = imx1_pinctrl_core_remove, +}; + +static int __init imx27_pinctrl_init(void) +{ + return platform_driver_register(&imx27_pinctrl_driver); +} +arch_initcall(imx27_pinctrl_init); + +static void __exit imx27_pinctrl_exit(void) +{ + platform_driver_unregister(&imx27_pinctrl_driver); +} +module_exit(imx27_pinctrl_exit); +MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>"); +MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c index 6e214110e3d..278a04ae894 100644 --- a/drivers/pinctrl/pinctrl-imx35.c +++ b/drivers/pinctrl/pinctrl-imx35.c @@ -24,1249 +24,496 @@ #include "pinctrl-imx.h" enum imx35_pads { - MX35_PAD_CAPTURE = 0, - MX35_PAD_COMPARE = 1, - MX35_PAD_WDOG_RST = 2, - MX35_PAD_GPIO1_0 = 3, - MX35_PAD_GPIO1_1 = 4, - MX35_PAD_GPIO2_0 = 5, - MX35_PAD_GPIO3_0 = 6, - MX35_PAD_RESET_IN_B = 7, - MX35_PAD_POR_B = 8, - MX35_PAD_CLKO = 9, - MX35_PAD_BOOT_MODE0 = 10, - MX35_PAD_BOOT_MODE1 = 11, - MX35_PAD_CLK_MODE0 = 12, - MX35_PAD_CLK_MODE1 = 13, - MX35_PAD_POWER_FAIL = 14, - MX35_PAD_VSTBY = 15, - MX35_PAD_A0 = 16, - MX35_PAD_A1 = 17, - MX35_PAD_A2 = 18, - MX35_PAD_A3 = 19, - MX35_PAD_A4 = 20, - MX35_PAD_A5 = 21, - MX35_PAD_A6 = 22, - MX35_PAD_A7 = 23, - MX35_PAD_A8 = 24, - MX35_PAD_A9 = 25, - MX35_PAD_A10 = 26, - MX35_PAD_MA10 = 27, - MX35_PAD_A11 = 28, - MX35_PAD_A12 = 29, - MX35_PAD_A13 = 30, - MX35_PAD_A14 = 31, - MX35_PAD_A15 = 32, - MX35_PAD_A16 = 33, - MX35_PAD_A17 = 34, - MX35_PAD_A18 = 35, - MX35_PAD_A19 = 36, - MX35_PAD_A20 = 37, - MX35_PAD_A21 = 38, - MX35_PAD_A22 = 39, - MX35_PAD_A23 = 40, - MX35_PAD_A24 = 41, - MX35_PAD_A25 = 42, - MX35_PAD_SDBA1 = 43, - MX35_PAD_SDBA0 = 44, - MX35_PAD_SD0 = 45, - MX35_PAD_SD1 = 46, - MX35_PAD_SD2 = 47, - MX35_PAD_SD3 = 48, - MX35_PAD_SD4 = 49, - MX35_PAD_SD5 = 50, - MX35_PAD_SD6 = 51, - MX35_PAD_SD7 = 52, - MX35_PAD_SD8 = 53, - MX35_PAD_SD9 = 54, - MX35_PAD_SD10 = 55, - MX35_PAD_SD11 = 56, - MX35_PAD_SD12 = 57, - MX35_PAD_SD13 = 58, - MX35_PAD_SD14 = 59, - MX35_PAD_SD15 = 60, - MX35_PAD_SD16 = 61, - MX35_PAD_SD17 = 62, - MX35_PAD_SD18 = 63, - MX35_PAD_SD19 = 64, - MX35_PAD_SD20 = 65, - MX35_PAD_SD21 = 66, - MX35_PAD_SD22 = 67, - MX35_PAD_SD23 = 68, - MX35_PAD_SD24 = 69, - MX35_PAD_SD25 = 70, - MX35_PAD_SD26 = 71, - MX35_PAD_SD27 = 72, - MX35_PAD_SD28 = 73, - MX35_PAD_SD29 = 74, - MX35_PAD_SD30 = 75, - MX35_PAD_SD31 = 76, - MX35_PAD_DQM0 = 77, - MX35_PAD_DQM1 = 78, - MX35_PAD_DQM2 = 79, - MX35_PAD_DQM3 = 80, - MX35_PAD_EB0 = 81, - MX35_PAD_EB1 = 82, - MX35_PAD_OE = 83, - MX35_PAD_CS0 = 84, - MX35_PAD_CS1 = 85, - MX35_PAD_CS2 = 86, - MX35_PAD_CS3 = 87, - MX35_PAD_CS4 = 88, - MX35_PAD_CS5 = 89, - MX35_PAD_NF_CE0 = 90, - MX35_PAD_ECB = 91, - MX35_PAD_LBA = 92, - MX35_PAD_BCLK = 93, - MX35_PAD_RW = 94, - MX35_PAD_RAS = 95, - MX35_PAD_CAS = 96, - MX35_PAD_SDWE = 97, - MX35_PAD_SDCKE0 = 98, - MX35_PAD_SDCKE1 = 99, - MX35_PAD_SDCLK = 100, - MX35_PAD_SDQS0 = 101, - MX35_PAD_SDQS1 = 102, - MX35_PAD_SDQS2 = 103, - MX35_PAD_SDQS3 = 104, - MX35_PAD_NFWE_B = 105, - MX35_PAD_NFRE_B = 106, - MX35_PAD_NFALE = 107, - MX35_PAD_NFCLE = 108, - MX35_PAD_NFWP_B = 109, - MX35_PAD_NFRB = 110, - MX35_PAD_D15 = 111, - MX35_PAD_D14 = 112, - MX35_PAD_D13 = 113, - MX35_PAD_D12 = 114, - MX35_PAD_D11 = 115, - MX35_PAD_D10 = 116, - MX35_PAD_D9 = 117, - MX35_PAD_D8 = 118, - MX35_PAD_D7 = 119, - MX35_PAD_D6 = 120, - MX35_PAD_D5 = 121, - MX35_PAD_D4 = 122, - MX35_PAD_D3 = 123, - MX35_PAD_D2 = 124, - MX35_PAD_D1 = 125, - MX35_PAD_D0 = 126, - MX35_PAD_CSI_D8 = 127, - MX35_PAD_CSI_D9 = 128, - MX35_PAD_CSI_D10 = 129, - MX35_PAD_CSI_D11 = 130, - MX35_PAD_CSI_D12 = 131, - MX35_PAD_CSI_D13 = 132, - MX35_PAD_CSI_D14 = 133, - MX35_PAD_CSI_D15 = 134, - MX35_PAD_CSI_MCLK = 135, - MX35_PAD_CSI_VSYNC = 136, - MX35_PAD_CSI_HSYNC = 137, - MX35_PAD_CSI_PIXCLK = 138, - MX35_PAD_I2C1_CLK = 139, - MX35_PAD_I2C1_DAT = 140, - MX35_PAD_I2C2_CLK = 141, - MX35_PAD_I2C2_DAT = 142, - MX35_PAD_STXD4 = 143, - MX35_PAD_SRXD4 = 144, - MX35_PAD_SCK4 = 145, - MX35_PAD_STXFS4 = 146, - MX35_PAD_STXD5 = 147, - MX35_PAD_SRXD5 = 148, - MX35_PAD_SCK5 = 149, - MX35_PAD_STXFS5 = 150, - MX35_PAD_SCKR = 151, - MX35_PAD_FSR = 152, - MX35_PAD_HCKR = 153, - MX35_PAD_SCKT = 154, - MX35_PAD_FST = 155, - MX35_PAD_HCKT = 156, - MX35_PAD_TX5_RX0 = 157, - MX35_PAD_TX4_RX1 = 158, - MX35_PAD_TX3_RX2 = 159, - MX35_PAD_TX2_RX3 = 160, - MX35_PAD_TX1 = 161, - MX35_PAD_TX0 = 162, - MX35_PAD_CSPI1_MOSI = 163, - MX35_PAD_CSPI1_MISO = 164, - MX35_PAD_CSPI1_SS0 = 165, - MX35_PAD_CSPI1_SS1 = 166, - MX35_PAD_CSPI1_SCLK = 167, - MX35_PAD_CSPI1_SPI_RDY = 168, - MX35_PAD_RXD1 = 169, - MX35_PAD_TXD1 = 170, - MX35_PAD_RTS1 = 171, - MX35_PAD_CTS1 = 172, - MX35_PAD_RXD2 = 173, - MX35_PAD_TXD2 = 174, - MX35_PAD_RTS2 = 175, - MX35_PAD_CTS2 = 176, - MX35_PAD_RTCK = 177, - MX35_PAD_TCK = 178, - MX35_PAD_TMS = 179, - MX35_PAD_TDI = 180, - MX35_PAD_TDO = 181, - MX35_PAD_TRSTB = 182, - MX35_PAD_DE_B = 183, - MX35_PAD_SJC_MOD = 184, - MX35_PAD_USBOTG_PWR = 185, - MX35_PAD_USBOTG_OC = 186, - MX35_PAD_LD0 = 187, - MX35_PAD_LD1 = 188, - MX35_PAD_LD2 = 189, - MX35_PAD_LD3 = 190, - MX35_PAD_LD4 = 191, - MX35_PAD_LD5 = 192, - MX35_PAD_LD6 = 193, - MX35_PAD_LD7 = 194, - MX35_PAD_LD8 = 195, - MX35_PAD_LD9 = 196, - MX35_PAD_LD10 = 197, - MX35_PAD_LD11 = 198, - MX35_PAD_LD12 = 199, - MX35_PAD_LD13 = 200, - MX35_PAD_LD14 = 201, - MX35_PAD_LD15 = 202, - MX35_PAD_LD16 = 203, - MX35_PAD_LD17 = 204, - MX35_PAD_LD18 = 205, - MX35_PAD_LD19 = 206, - MX35_PAD_LD20 = 207, - MX35_PAD_LD21 = 208, - MX35_PAD_LD22 = 209, - MX35_PAD_LD23 = 210, - MX35_PAD_D3_HSYNC = 211, - MX35_PAD_D3_FPSHIFT = 212, - MX35_PAD_D3_DRDY = 213, - MX35_PAD_CONTRAST = 214, - MX35_PAD_D3_VSYNC = 215, - MX35_PAD_D3_REV = 216, - MX35_PAD_D3_CLS = 217, - MX35_PAD_D3_SPL = 218, - MX35_PAD_SD1_CMD = 219, - MX35_PAD_SD1_CLK = 220, - MX35_PAD_SD1_DATA0 = 221, - MX35_PAD_SD1_DATA1 = 222, - MX35_PAD_SD1_DATA2 = 223, - MX35_PAD_SD1_DATA3 = 224, - MX35_PAD_SD2_CMD = 225, - MX35_PAD_SD2_CLK = 226, - MX35_PAD_SD2_DATA0 = 227, - MX35_PAD_SD2_DATA1 = 228, - MX35_PAD_SD2_DATA2 = 229, - MX35_PAD_SD2_DATA3 = 230, - MX35_PAD_ATA_CS0 = 231, - MX35_PAD_ATA_CS1 = 232, - MX35_PAD_ATA_DIOR = 233, - MX35_PAD_ATA_DIOW = 234, - MX35_PAD_ATA_DMACK = 235, - MX35_PAD_ATA_RESET_B = 236, - MX35_PAD_ATA_IORDY = 237, - MX35_PAD_ATA_DATA0 = 238, - MX35_PAD_ATA_DATA1 = 239, - MX35_PAD_ATA_DATA2 = 240, - MX35_PAD_ATA_DATA3 = 241, - MX35_PAD_ATA_DATA4 = 242, - MX35_PAD_ATA_DATA5 = 243, - MX35_PAD_ATA_DATA6 = 244, - MX35_PAD_ATA_DATA7 = 245, - MX35_PAD_ATA_DATA8 = 246, - MX35_PAD_ATA_DATA9 = 247, - MX35_PAD_ATA_DATA10 = 248, - MX35_PAD_ATA_DATA11 = 249, - MX35_PAD_ATA_DATA12 = 250, - MX35_PAD_ATA_DATA13 = 251, - MX35_PAD_ATA_DATA14 = 252, - MX35_PAD_ATA_DATA15 = 253, - MX35_PAD_ATA_INTRQ = 254, - MX35_PAD_ATA_BUFF_EN = 255, - MX35_PAD_ATA_DMARQ = 256, - MX35_PAD_ATA_DA0 = 257, - MX35_PAD_ATA_DA1 = 258, - MX35_PAD_ATA_DA2 = 259, - MX35_PAD_MLB_CLK = 260, - MX35_PAD_MLB_DAT = 261, - MX35_PAD_MLB_SIG = 262, - MX35_PAD_FEC_TX_CLK = 263, - MX35_PAD_FEC_RX_CLK = 264, - MX35_PAD_FEC_RX_DV = 265, - MX35_PAD_FEC_COL = 266, - MX35_PAD_FEC_RDATA0 = 267, - MX35_PAD_FEC_TDATA0 = 268, - MX35_PAD_FEC_TX_EN = 269, - MX35_PAD_FEC_MDC = 270, - MX35_PAD_FEC_MDIO = 271, - MX35_PAD_FEC_TX_ERR = 272, - MX35_PAD_FEC_RX_ERR = 273, - MX35_PAD_FEC_CRS = 274, - MX35_PAD_FEC_RDATA1 = 275, - MX35_PAD_FEC_TDATA1 = 276, - MX35_PAD_FEC_RDATA2 = 277, - MX35_PAD_FEC_TDATA2 = 278, - MX35_PAD_FEC_RDATA3 = 279, - MX35_PAD_FEC_TDATA3 = 280, - MX35_PAD_EXT_ARMCLK = 281, - MX35_PAD_TEST_MODE = 282, -}; - -/* imx35 register maps */ -static struct imx_pin_reg imx35_pin_regs[] = { - [0] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 0, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CAPIN1 */ - [1] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 1, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CMPOUT2 */ - [2] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 2, 0x7f4, 0), /* MX35_PAD_CAPTURE__CSPI2_SS1 */ - [3] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 3, 0x0, 0), /* MX35_PAD_CAPTURE__EPIT1_EPITO */ - [4] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 4, 0x7d0, 0), /* MX35_PAD_CAPTURE__CCM_CLK32K */ - [5] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 5, 0x850, 0), /* MX35_PAD_CAPTURE__GPIO1_4 */ - [6] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 0, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT1 */ - [7] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 1, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CAPIN2 */ - [8] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 2, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT3 */ - [9] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 3, 0x0, 0), /* MX35_PAD_COMPARE__EPIT2_EPITO */ - [10] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 5, 0x854, 0), /* MX35_PAD_COMPARE__GPIO1_5 */ - [11] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 7, 0x0, 0), /* MX35_PAD_COMPARE__SDMA_EXTDMA_2 */ - [12] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 0, 0x0, 0), /* MX35_PAD_WDOG_RST__WDOG_WDOG_B */ - [13] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 3, 0x0, 0), /* MX35_PAD_WDOG_RST__IPU_FLASH_STROBE */ - [14] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 5, 0x858, 0), /* MX35_PAD_WDOG_RST__GPIO1_6 */ - [15] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 0, 0x82c, 0), /* MX35_PAD_GPIO1_0__GPIO1_0 */ - [16] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 1, 0x7d4, 0), /* MX35_PAD_GPIO1_0__CCM_PMIC_RDY */ - [17] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 2, 0x990, 0), /* MX35_PAD_GPIO1_0__OWIRE_LINE */ - [18] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 7, 0x0, 0), /* MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 */ - [19] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 0, 0x838, 0), /* MX35_PAD_GPIO1_1__GPIO1_1 */ - [20] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 2, 0x0, 0), /* MX35_PAD_GPIO1_1__PWM_PWMO */ - [21] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 3, 0x7d8, 0), /* MX35_PAD_GPIO1_1__CSPI1_SS2 */ - [22] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 6, 0x0, 0), /* MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT */ - [23] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 7, 0x0, 0), /* MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 */ - [24] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 0, 0x868, 0), /* MX35_PAD_GPIO2_0__GPIO2_0 */ - [25] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 1, 0x0, 0), /* MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK */ - [26] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 0, 0x8e8, 0), /* MX35_PAD_GPIO3_0__GPIO3_0 */ - [27] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 1, 0x0, 0), /* MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK */ - [28] = IMX_PIN_REG(MX35_PAD_RESET_IN_B, 0x344, 0x0, 0, 0x0, 0), /* MX35_PAD_RESET_IN_B__CCM_RESET_IN_B */ - [29] = IMX_PIN_REG(MX35_PAD_POR_B, 0x348, 0x0, 0, 0x0, 0), /* MX35_PAD_POR_B__CCM_POR_B */ - [30] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 0, 0x0, 0), /* MX35_PAD_CLKO__CCM_CLKO */ - [31] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 5, 0x860, 0), /* MX35_PAD_CLKO__GPIO1_8 */ - [32] = IMX_PIN_REG(MX35_PAD_BOOT_MODE0, 0x350, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 */ - [33] = IMX_PIN_REG(MX35_PAD_BOOT_MODE1, 0x354, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 */ - [34] = IMX_PIN_REG(MX35_PAD_CLK_MODE0, 0x358, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 */ - [35] = IMX_PIN_REG(MX35_PAD_CLK_MODE1, 0x35c, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 */ - [36] = IMX_PIN_REG(MX35_PAD_POWER_FAIL, 0x360, 0x0, 0, 0x0, 0), /* MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 */ - [37] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 0, 0x0, 0), /* MX35_PAD_VSTBY__CCM_VSTBY */ - [38] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 5, 0x85c, 0), /* MX35_PAD_VSTBY__GPIO1_7 */ - [39] = IMX_PIN_REG(MX35_PAD_A0, 0x368, 0x028, 0, 0x0, 0), /* MX35_PAD_A0__EMI_EIM_DA_L_0 */ - [40] = IMX_PIN_REG(MX35_PAD_A1, 0x36c, 0x02c, 0, 0x0, 0), /* MX35_PAD_A1__EMI_EIM_DA_L_1 */ - [41] = IMX_PIN_REG(MX35_PAD_A2, 0x370, 0x030, 0, 0x0, 0), /* MX35_PAD_A2__EMI_EIM_DA_L_2 */ - [42] = IMX_PIN_REG(MX35_PAD_A3, 0x374, 0x034, 0, 0x0, 0), /* MX35_PAD_A3__EMI_EIM_DA_L_3 */ - [43] = IMX_PIN_REG(MX35_PAD_A4, 0x378, 0x038, 0, 0x0, 0), /* MX35_PAD_A4__EMI_EIM_DA_L_4 */ - [44] = IMX_PIN_REG(MX35_PAD_A5, 0x37c, 0x03c, 0, 0x0, 0), /* MX35_PAD_A5__EMI_EIM_DA_L_5 */ - [45] = IMX_PIN_REG(MX35_PAD_A6, 0x380, 0x040, 0, 0x0, 0), /* MX35_PAD_A6__EMI_EIM_DA_L_6 */ - [46] = IMX_PIN_REG(MX35_PAD_A7, 0x384, 0x044, 0, 0x0, 0), /* MX35_PAD_A7__EMI_EIM_DA_L_7 */ - [47] = IMX_PIN_REG(MX35_PAD_A8, 0x388, 0x048, 0, 0x0, 0), /* MX35_PAD_A8__EMI_EIM_DA_H_8 */ - [48] = IMX_PIN_REG(MX35_PAD_A9, 0x38c, 0x04c, 0, 0x0, 0), /* MX35_PAD_A9__EMI_EIM_DA_H_9 */ - [49] = IMX_PIN_REG(MX35_PAD_A10, 0x390, 0x050, 0, 0x0, 0), /* MX35_PAD_A10__EMI_EIM_DA_H_10 */ - [50] = IMX_PIN_REG(MX35_PAD_MA10, 0x394, 0x054, 0, 0x0, 0), /* MX35_PAD_MA10__EMI_MA10 */ - [51] = IMX_PIN_REG(MX35_PAD_A11, 0x398, 0x058, 0, 0x0, 0), /* MX35_PAD_A11__EMI_EIM_DA_H_11 */ - [52] = IMX_PIN_REG(MX35_PAD_A12, 0x39c, 0x05c, 0, 0x0, 0), /* MX35_PAD_A12__EMI_EIM_DA_H_12 */ - [53] = IMX_PIN_REG(MX35_PAD_A13, 0x3a0, 0x060, 0, 0x0, 0), /* MX35_PAD_A13__EMI_EIM_DA_H_13 */ - [54] = IMX_PIN_REG(MX35_PAD_A14, 0x3a4, 0x064, 0, 0x0, 0), /* MX35_PAD_A14__EMI_EIM_DA_H2_14 */ - [55] = IMX_PIN_REG(MX35_PAD_A15, 0x3a8, 0x068, 0, 0x0, 0), /* MX35_PAD_A15__EMI_EIM_DA_H2_15 */ - [56] = IMX_PIN_REG(MX35_PAD_A16, 0x3ac, 0x06c, 0, 0x0, 0), /* MX35_PAD_A16__EMI_EIM_A_16 */ - [57] = IMX_PIN_REG(MX35_PAD_A17, 0x3b0, 0x070, 0, 0x0, 0), /* MX35_PAD_A17__EMI_EIM_A_17 */ - [58] = IMX_PIN_REG(MX35_PAD_A18, 0x3b4, 0x074, 0, 0x0, 0), /* MX35_PAD_A18__EMI_EIM_A_18 */ - [59] = IMX_PIN_REG(MX35_PAD_A19, 0x3b8, 0x078, 0, 0x0, 0), /* MX35_PAD_A19__EMI_EIM_A_19 */ - [60] = IMX_PIN_REG(MX35_PAD_A20, 0x3bc, 0x07c, 0, 0x0, 0), /* MX35_PAD_A20__EMI_EIM_A_20 */ - [61] = IMX_PIN_REG(MX35_PAD_A21, 0x3c0, 0x080, 0, 0x0, 0), /* MX35_PAD_A21__EMI_EIM_A_21 */ - [62] = IMX_PIN_REG(MX35_PAD_A22, 0x3c4, 0x084, 0, 0x0, 0), /* MX35_PAD_A22__EMI_EIM_A_22 */ - [63] = IMX_PIN_REG(MX35_PAD_A23, 0x3c8, 0x088, 0, 0x0, 0), /* MX35_PAD_A23__EMI_EIM_A_23 */ - [64] = IMX_PIN_REG(MX35_PAD_A24, 0x3cc, 0x08c, 0, 0x0, 0), /* MX35_PAD_A24__EMI_EIM_A_24 */ - [65] = IMX_PIN_REG(MX35_PAD_A25, 0x3d0, 0x090, 0, 0x0, 0), /* MX35_PAD_A25__EMI_EIM_A_25 */ - [66] = IMX_PIN_REG(MX35_PAD_SDBA1, 0x3d4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA1__EMI_EIM_SDBA1 */ - [67] = IMX_PIN_REG(MX35_PAD_SDBA0, 0x3d8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA0__EMI_EIM_SDBA0 */ - [68] = IMX_PIN_REG(MX35_PAD_SD0, 0x3dc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD0__EMI_DRAM_D_0 */ - [69] = IMX_PIN_REG(MX35_PAD_SD1, 0x3e0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD1__EMI_DRAM_D_1 */ - [70] = IMX_PIN_REG(MX35_PAD_SD2, 0x3e4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD2__EMI_DRAM_D_2 */ - [71] = IMX_PIN_REG(MX35_PAD_SD3, 0x3e8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD3__EMI_DRAM_D_3 */ - [72] = IMX_PIN_REG(MX35_PAD_SD4, 0x3ec, 0x0, 0, 0x0, 0), /* MX35_PAD_SD4__EMI_DRAM_D_4 */ - [73] = IMX_PIN_REG(MX35_PAD_SD5, 0x3f0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD5__EMI_DRAM_D_5 */ - [74] = IMX_PIN_REG(MX35_PAD_SD6, 0x3f4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD6__EMI_DRAM_D_6 */ - [75] = IMX_PIN_REG(MX35_PAD_SD7, 0x3f8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD7__EMI_DRAM_D_7 */ - [76] = IMX_PIN_REG(MX35_PAD_SD8, 0x3fc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD8__EMI_DRAM_D_8 */ - [77] = IMX_PIN_REG(MX35_PAD_SD9, 0x400, 0x0, 0, 0x0, 0), /* MX35_PAD_SD9__EMI_DRAM_D_9 */ - [78] = IMX_PIN_REG(MX35_PAD_SD10, 0x404, 0x0, 0, 0x0, 0), /* MX35_PAD_SD10__EMI_DRAM_D_10 */ - [79] = IMX_PIN_REG(MX35_PAD_SD11, 0x408, 0x0, 0, 0x0, 0), /* MX35_PAD_SD11__EMI_DRAM_D_11 */ - [80] = IMX_PIN_REG(MX35_PAD_SD12, 0x40c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD12__EMI_DRAM_D_12 */ - [81] = IMX_PIN_REG(MX35_PAD_SD13, 0x410, 0x0, 0, 0x0, 0), /* MX35_PAD_SD13__EMI_DRAM_D_13 */ - [82] = IMX_PIN_REG(MX35_PAD_SD14, 0x414, 0x0, 0, 0x0, 0), /* MX35_PAD_SD14__EMI_DRAM_D_14 */ - [83] = IMX_PIN_REG(MX35_PAD_SD15, 0x418, 0x0, 0, 0x0, 0), /* MX35_PAD_SD15__EMI_DRAM_D_15 */ - [84] = IMX_PIN_REG(MX35_PAD_SD16, 0x41c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD16__EMI_DRAM_D_16 */ - [85] = IMX_PIN_REG(MX35_PAD_SD17, 0x420, 0x0, 0, 0x0, 0), /* MX35_PAD_SD17__EMI_DRAM_D_17 */ - [86] = IMX_PIN_REG(MX35_PAD_SD18, 0x424, 0x0, 0, 0x0, 0), /* MX35_PAD_SD18__EMI_DRAM_D_18 */ - [87] = IMX_PIN_REG(MX35_PAD_SD19, 0x428, 0x0, 0, 0x0, 0), /* MX35_PAD_SD19__EMI_DRAM_D_19 */ - [88] = IMX_PIN_REG(MX35_PAD_SD20, 0x42c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD20__EMI_DRAM_D_20 */ - [89] = IMX_PIN_REG(MX35_PAD_SD21, 0x430, 0x0, 0, 0x0, 0), /* MX35_PAD_SD21__EMI_DRAM_D_21 */ - [90] = IMX_PIN_REG(MX35_PAD_SD22, 0x434, 0x0, 0, 0x0, 0), /* MX35_PAD_SD22__EMI_DRAM_D_22 */ - [91] = IMX_PIN_REG(MX35_PAD_SD23, 0x438, 0x0, 0, 0x0, 0), /* MX35_PAD_SD23__EMI_DRAM_D_23 */ - [92] = IMX_PIN_REG(MX35_PAD_SD24, 0x43c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD24__EMI_DRAM_D_24 */ - [93] = IMX_PIN_REG(MX35_PAD_SD25, 0x440, 0x0, 0, 0x0, 0), /* MX35_PAD_SD25__EMI_DRAM_D_25 */ - [94] = IMX_PIN_REG(MX35_PAD_SD26, 0x444, 0x0, 0, 0x0, 0), /* MX35_PAD_SD26__EMI_DRAM_D_26 */ - [95] = IMX_PIN_REG(MX35_PAD_SD27, 0x448, 0x0, 0, 0x0, 0), /* MX35_PAD_SD27__EMI_DRAM_D_27 */ - [96] = IMX_PIN_REG(MX35_PAD_SD28, 0x44c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD28__EMI_DRAM_D_28 */ - [97] = IMX_PIN_REG(MX35_PAD_SD29, 0x450, 0x0, 0, 0x0, 0), /* MX35_PAD_SD29__EMI_DRAM_D_29 */ - [98] = IMX_PIN_REG(MX35_PAD_SD30, 0x454, 0x0, 0, 0x0, 0), /* MX35_PAD_SD30__EMI_DRAM_D_30 */ - [99] = IMX_PIN_REG(MX35_PAD_SD31, 0x458, 0x0, 0, 0x0, 0), /* MX35_PAD_SD31__EMI_DRAM_D_31 */ - [100] = IMX_PIN_REG(MX35_PAD_DQM0, 0x45c, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM0__EMI_DRAM_DQM_0 */ - [101] = IMX_PIN_REG(MX35_PAD_DQM1, 0x460, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM1__EMI_DRAM_DQM_1 */ - [102] = IMX_PIN_REG(MX35_PAD_DQM2, 0x464, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM2__EMI_DRAM_DQM_2 */ - [103] = IMX_PIN_REG(MX35_PAD_DQM3, 0x468, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM3__EMI_DRAM_DQM_3 */ - [104] = IMX_PIN_REG(MX35_PAD_EB0, 0x46c, 0x094, 0, 0x0, 0), /* MX35_PAD_EB0__EMI_EIM_EB0_B */ - [105] = IMX_PIN_REG(MX35_PAD_EB1, 0x470, 0x098, 0, 0x0, 0), /* MX35_PAD_EB1__EMI_EIM_EB1_B */ - [106] = IMX_PIN_REG(MX35_PAD_OE, 0x474, 0x09c, 0, 0x0, 0), /* MX35_PAD_OE__EMI_EIM_OE */ - [107] = IMX_PIN_REG(MX35_PAD_CS0, 0x478, 0x0a0, 0, 0x0, 0), /* MX35_PAD_CS0__EMI_EIM_CS0 */ - [108] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 0, 0x0, 0), /* MX35_PAD_CS1__EMI_EIM_CS1 */ - [109] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 3, 0x0, 0), /* MX35_PAD_CS1__EMI_NANDF_CE3 */ - [110] = IMX_PIN_REG(MX35_PAD_CS2, 0x480, 0x0a8, 0, 0x0, 0), /* MX35_PAD_CS2__EMI_EIM_CS2 */ - [111] = IMX_PIN_REG(MX35_PAD_CS3, 0x484, 0x0ac, 0, 0x0, 0), /* MX35_PAD_CS3__EMI_EIM_CS3 */ - [112] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 0, 0x0, 0), /* MX35_PAD_CS4__EMI_EIM_CS4 */ - [113] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 1, 0x800, 0), /* MX35_PAD_CS4__EMI_DTACK_B */ - [114] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 3, 0x0, 0), /* MX35_PAD_CS4__EMI_NANDF_CE1 */ - [115] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 5, 0x83c, 0), /* MX35_PAD_CS4__GPIO1_20 */ - [116] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 0, 0x0, 0), /* MX35_PAD_CS5__EMI_EIM_CS5 */ - [117] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 1, 0x7f8, 0), /* MX35_PAD_CS5__CSPI2_SS2 */ - [118] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 2, 0x7d8, 1), /* MX35_PAD_CS5__CSPI1_SS2 */ - [119] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 3, 0x0, 0), /* MX35_PAD_CS5__EMI_NANDF_CE2 */ - [120] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 5, 0x840, 0), /* MX35_PAD_CS5__GPIO1_21 */ - [121] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 0, 0x0, 0), /* MX35_PAD_NF_CE0__EMI_NANDF_CE0 */ - [122] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 5, 0x844, 0), /* MX35_PAD_NF_CE0__GPIO1_22 */ - [123] = IMX_PIN_REG(MX35_PAD_ECB, 0x494, 0x0, 0, 0x0, 0), /* MX35_PAD_ECB__EMI_EIM_ECB */ - [124] = IMX_PIN_REG(MX35_PAD_LBA, 0x498, 0x0bc, 0, 0x0, 0), /* MX35_PAD_LBA__EMI_EIM_LBA */ - [125] = IMX_PIN_REG(MX35_PAD_BCLK, 0x49c, 0x0c0, 0, 0x0, 0), /* MX35_PAD_BCLK__EMI_EIM_BCLK */ - [126] = IMX_PIN_REG(MX35_PAD_RW, 0x4a0, 0x0c4, 0, 0x0, 0), /* MX35_PAD_RW__EMI_EIM_RW */ - [127] = IMX_PIN_REG(MX35_PAD_RAS, 0x4a4, 0x0, 0, 0x0, 0), /* MX35_PAD_RAS__EMI_DRAM_RAS */ - [128] = IMX_PIN_REG(MX35_PAD_CAS, 0x4a8, 0x0, 0, 0x0, 0), /* MX35_PAD_CAS__EMI_DRAM_CAS */ - [129] = IMX_PIN_REG(MX35_PAD_SDWE, 0x4ac, 0x0, 0, 0x0, 0), /* MX35_PAD_SDWE__EMI_DRAM_SDWE */ - [130] = IMX_PIN_REG(MX35_PAD_SDCKE0, 0x4b0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 */ - [131] = IMX_PIN_REG(MX35_PAD_SDCKE1, 0x4b4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 */ - [132] = IMX_PIN_REG(MX35_PAD_SDCLK, 0x4b8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCLK__EMI_DRAM_SDCLK */ - [133] = IMX_PIN_REG(MX35_PAD_SDQS0, 0x4bc, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 */ - [134] = IMX_PIN_REG(MX35_PAD_SDQS1, 0x4c0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 */ - [135] = IMX_PIN_REG(MX35_PAD_SDQS2, 0x4c4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 */ - [136] = IMX_PIN_REG(MX35_PAD_SDQS3, 0x4c8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 */ - [137] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 0, 0x0, 0), /* MX35_PAD_NFWE_B__EMI_NANDF_WE_B */ - [138] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 1, 0x9d8, 0), /* MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 */ - [139] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 2, 0x924, 0), /* MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC */ - [140] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 5, 0x88c, 0), /* MX35_PAD_NFWE_B__GPIO2_18 */ - [141] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 7, 0x0, 0), /* MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 */ - [142] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 0, 0x0, 0), /* MX35_PAD_NFRE_B__EMI_NANDF_RE_B */ - [143] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 1, 0x9ec, 0), /* MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR */ - [144] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 2, 0x0, 0), /* MX35_PAD_NFRE_B__IPU_DISPB_BCLK */ - [145] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 5, 0x890, 0), /* MX35_PAD_NFRE_B__GPIO2_19 */ - [146] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 7, 0x0, 0), /* MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 */ - [147] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 0, 0x0, 0), /* MX35_PAD_NFALE__EMI_NANDF_ALE */ - [148] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 1, 0x0, 0), /* MX35_PAD_NFALE__USB_TOP_USBH2_STP */ - [149] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 2, 0x0, 0), /* MX35_PAD_NFALE__IPU_DISPB_CS0 */ - [150] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 5, 0x898, 0), /* MX35_PAD_NFALE__GPIO2_20 */ - [151] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 7, 0x0, 0), /* MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 */ - [152] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 0, 0x0, 0), /* MX35_PAD_NFCLE__EMI_NANDF_CLE */ - [153] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 1, 0x9f0, 0), /* MX35_PAD_NFCLE__USB_TOP_USBH2_NXT */ - [154] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 2, 0x0, 0), /* MX35_PAD_NFCLE__IPU_DISPB_PAR_RS */ - [155] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 5, 0x89c, 0), /* MX35_PAD_NFCLE__GPIO2_21 */ - [156] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 7, 0x0, 0), /* MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 */ - [157] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 0, 0x0, 0), /* MX35_PAD_NFWP_B__EMI_NANDF_WP_B */ - [158] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 1, 0x9e8, 0), /* MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 */ - [159] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 2, 0x0, 0), /* MX35_PAD_NFWP_B__IPU_DISPB_WR */ - [160] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 5, 0x8a0, 0), /* MX35_PAD_NFWP_B__GPIO2_22 */ - [161] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 7, 0x0, 0), /* MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL */ - [162] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 0, 0x0, 0), /* MX35_PAD_NFRB__EMI_NANDF_RB */ - [163] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 2, 0x0, 0), /* MX35_PAD_NFRB__IPU_DISPB_RD */ - [164] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 5, 0x8a4, 0), /* MX35_PAD_NFRB__GPIO2_23 */ - [165] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 7, 0x0, 0), /* MX35_PAD_NFRB__ARM11P_TOP_TRCLK */ - [166] = IMX_PIN_REG(MX35_PAD_D15, 0x4e4, 0x0, 0, 0x0, 0), /* MX35_PAD_D15__EMI_EIM_D_15 */ - [167] = IMX_PIN_REG(MX35_PAD_D14, 0x4e8, 0x0, 0, 0x0, 0), /* MX35_PAD_D14__EMI_EIM_D_14 */ - [168] = IMX_PIN_REG(MX35_PAD_D13, 0x4ec, 0x0, 0, 0x0, 0), /* MX35_PAD_D13__EMI_EIM_D_13 */ - [169] = IMX_PIN_REG(MX35_PAD_D12, 0x4f0, 0x0, 0, 0x0, 0), /* MX35_PAD_D12__EMI_EIM_D_12 */ - [170] = IMX_PIN_REG(MX35_PAD_D11, 0x4f4, 0x0, 0, 0x0, 0), /* MX35_PAD_D11__EMI_EIM_D_11 */ - [171] = IMX_PIN_REG(MX35_PAD_D10, 0x4f8, 0x0, 0, 0x0, 0), /* MX35_PAD_D10__EMI_EIM_D_10 */ - [172] = IMX_PIN_REG(MX35_PAD_D9, 0x4fc, 0x0, 0, 0x0, 0), /* MX35_PAD_D9__EMI_EIM_D_9 */ - [173] = IMX_PIN_REG(MX35_PAD_D8, 0x500, 0x0, 0, 0x0, 0), /* MX35_PAD_D8__EMI_EIM_D_8 */ - [174] = IMX_PIN_REG(MX35_PAD_D7, 0x504, 0x0, 0, 0x0, 0), /* MX35_PAD_D7__EMI_EIM_D_7 */ - [175] = IMX_PIN_REG(MX35_PAD_D6, 0x508, 0x0, 0, 0x0, 0), /* MX35_PAD_D6__EMI_EIM_D_6 */ - [176] = IMX_PIN_REG(MX35_PAD_D5, 0x50c, 0x0, 0, 0x0, 0), /* MX35_PAD_D5__EMI_EIM_D_5 */ - [177] = IMX_PIN_REG(MX35_PAD_D4, 0x510, 0x0, 0, 0x0, 0), /* MX35_PAD_D4__EMI_EIM_D_4 */ - [178] = IMX_PIN_REG(MX35_PAD_D3, 0x514, 0x0, 0, 0x0, 0), /* MX35_PAD_D3__EMI_EIM_D_3 */ - [179] = IMX_PIN_REG(MX35_PAD_D2, 0x518, 0x0, 0, 0x0, 0), /* MX35_PAD_D2__EMI_EIM_D_2 */ - [180] = IMX_PIN_REG(MX35_PAD_D1, 0x51c, 0x0, 0, 0x0, 0), /* MX35_PAD_D1__EMI_EIM_D_1 */ - [181] = IMX_PIN_REG(MX35_PAD_D0, 0x520, 0x0, 0, 0x0, 0), /* MX35_PAD_D0__EMI_EIM_D_0 */ - [182] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 0, 0x0, 0), /* MX35_PAD_CSI_D8__IPU_CSI_D_8 */ - [183] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 1, 0x950, 0), /* MX35_PAD_CSI_D8__KPP_COL_0 */ - [184] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 5, 0x83c, 1), /* MX35_PAD_CSI_D8__GPIO1_20 */ - [185] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 7, 0x0, 0), /* MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 */ - [186] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 0, 0x0, 0), /* MX35_PAD_CSI_D9__IPU_CSI_D_9 */ - [187] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 1, 0x954, 0), /* MX35_PAD_CSI_D9__KPP_COL_1 */ - [188] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 5, 0x840, 1), /* MX35_PAD_CSI_D9__GPIO1_21 */ - [189] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 7, 0x0, 0), /* MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 */ - [190] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 0, 0x0, 0), /* MX35_PAD_CSI_D10__IPU_CSI_D_10 */ - [191] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 1, 0x958, 0), /* MX35_PAD_CSI_D10__KPP_COL_2 */ - [192] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 5, 0x844, 1), /* MX35_PAD_CSI_D10__GPIO1_22 */ - [193] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 7, 0x0, 0), /* MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 */ - [194] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 0, 0x0, 0), /* MX35_PAD_CSI_D11__IPU_CSI_D_11 */ - [195] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 1, 0x95c, 0), /* MX35_PAD_CSI_D11__KPP_COL_3 */ - [196] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 5, 0x0, 0), /* MX35_PAD_CSI_D11__GPIO1_23 */ - [197] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 0, 0x0, 0), /* MX35_PAD_CSI_D12__IPU_CSI_D_12 */ - [198] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 1, 0x970, 0), /* MX35_PAD_CSI_D12__KPP_ROW_0 */ - [199] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 5, 0x0, 0), /* MX35_PAD_CSI_D12__GPIO1_24 */ - [200] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 0, 0x0, 0), /* MX35_PAD_CSI_D13__IPU_CSI_D_13 */ - [201] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 1, 0x974, 0), /* MX35_PAD_CSI_D13__KPP_ROW_1 */ - [202] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 5, 0x0, 0), /* MX35_PAD_CSI_D13__GPIO1_25 */ - [203] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 0, 0x0, 0), /* MX35_PAD_CSI_D14__IPU_CSI_D_14 */ - [204] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 1, 0x978, 0), /* MX35_PAD_CSI_D14__KPP_ROW_2 */ - [205] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 5, 0x0, 0), /* MX35_PAD_CSI_D14__GPIO1_26 */ - [206] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 0, 0x97c, 0), /* MX35_PAD_CSI_D15__IPU_CSI_D_15 */ - [207] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 1, 0x0, 0), /* MX35_PAD_CSI_D15__KPP_ROW_3 */ - [208] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 5, 0x0, 0), /* MX35_PAD_CSI_D15__GPIO1_27 */ - [209] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 0, 0x0, 0), /* MX35_PAD_CSI_MCLK__IPU_CSI_MCLK */ - [210] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 5, 0x0, 0), /* MX35_PAD_CSI_MCLK__GPIO1_28 */ - [211] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 0, 0x0, 0), /* MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC */ - [212] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 5, 0x0, 0), /* MX35_PAD_CSI_VSYNC__GPIO1_29 */ - [213] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 0, 0x0, 0), /* MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC */ - [214] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 5, 0x0, 0), /* MX35_PAD_CSI_HSYNC__GPIO1_30 */ - [215] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 0, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK */ - [216] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 5, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__GPIO1_31 */ - [217] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 0, 0x0, 0), /* MX35_PAD_I2C1_CLK__I2C1_SCL */ - [218] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 5, 0x8a8, 0), /* MX35_PAD_I2C1_CLK__GPIO2_24 */ - [219] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 6, 0x0, 0), /* MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK */ - [220] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 0, 0x0, 0), /* MX35_PAD_I2C1_DAT__I2C1_SDA */ - [221] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 5, 0x8ac, 0), /* MX35_PAD_I2C1_DAT__GPIO2_25 */ - [222] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 0, 0x0, 0), /* MX35_PAD_I2C2_CLK__I2C2_SCL */ - [223] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 1, 0x0, 0), /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */ - [224] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 2, 0x0, 0), /* MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR */ - [225] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 5, 0x8b0, 0), /* MX35_PAD_I2C2_CLK__GPIO2_26 */ - [226] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 6, 0x0, 0), /* MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 */ - [227] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 0, 0x0, 0), /* MX35_PAD_I2C2_DAT__I2C2_SDA */ - [228] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 1, 0x7c8, 0), /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */ - [229] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 2, 0x9f4, 0), /* MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC */ - [230] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 5, 0x8b4, 0), /* MX35_PAD_I2C2_DAT__GPIO2_27 */ - [231] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 6, 0x0, 0), /* MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 */ - [232] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 0, 0x0, 0), /* MX35_PAD_STXD4__AUDMUX_AUD4_TXD */ - [233] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 5, 0x8b8, 0), /* MX35_PAD_STXD4__GPIO2_28 */ - [234] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 7, 0x0, 0), /* MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 */ - [235] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 0, 0x0, 0), /* MX35_PAD_SRXD4__AUDMUX_AUD4_RXD */ - [236] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 5, 0x8bc, 0), /* MX35_PAD_SRXD4__GPIO2_29 */ - [237] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 7, 0x0, 0), /* MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 */ - [238] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 0, 0x0, 0), /* MX35_PAD_SCK4__AUDMUX_AUD4_TXC */ - [239] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 5, 0x8c4, 0), /* MX35_PAD_SCK4__GPIO2_30 */ - [240] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 7, 0x0, 0), /* MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 */ - [241] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 0, 0x0, 0), /* MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS */ - [242] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 5, 0x8c8, 0), /* MX35_PAD_STXFS4__GPIO2_31 */ - [243] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 7, 0x0, 0), /* MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 */ - [244] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 0, 0x0, 0), /* MX35_PAD_STXD5__AUDMUX_AUD5_TXD */ - [245] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 1, 0x0, 0), /* MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 */ - [246] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 2, 0x7ec, 0), /* MX35_PAD_STXD5__CSPI2_MOSI */ - [247] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 5, 0x82c, 1), /* MX35_PAD_STXD5__GPIO1_0 */ - [248] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 7, 0x0, 0), /* MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 */ - [249] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 0, 0x0, 0), /* MX35_PAD_SRXD5__AUDMUX_AUD5_RXD */ - [250] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 1, 0x998, 0), /* MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 */ - [251] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 2, 0x7e8, 0), /* MX35_PAD_SRXD5__CSPI2_MISO */ - [252] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 5, 0x838, 1), /* MX35_PAD_SRXD5__GPIO1_1 */ - [253] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 7, 0x0, 0), /* MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 */ - [254] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 0, 0x0, 0), /* MX35_PAD_SCK5__AUDMUX_AUD5_TXC */ - [255] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 1, 0x994, 0), /* MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK */ - [256] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 2, 0x7e0, 0), /* MX35_PAD_SCK5__CSPI2_SCLK */ - [257] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 5, 0x848, 0), /* MX35_PAD_SCK5__GPIO1_2 */ - [258] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 7, 0x0, 0), /* MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 */ - [259] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 0, 0x0, 0), /* MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS */ - [260] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 2, 0x7e4, 0), /* MX35_PAD_STXFS5__CSPI2_RDY */ - [261] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 5, 0x84c, 0), /* MX35_PAD_STXFS5__GPIO1_3 */ - [262] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 7, 0x0, 0), /* MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 */ - [263] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 0, 0x0, 0), /* MX35_PAD_SCKR__ESAI_SCKR */ - [264] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 5, 0x850, 1), /* MX35_PAD_SCKR__GPIO1_4 */ - [265] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 7, 0x0, 0), /* MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 */ - [266] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 0, 0x0, 0), /* MX35_PAD_FSR__ESAI_FSR */ - [267] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 5, 0x854, 1), /* MX35_PAD_FSR__GPIO1_5 */ - [268] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 7, 0x0, 0), /* MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 */ - [269] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 0, 0x0, 0), /* MX35_PAD_HCKR__ESAI_HCKR */ - [270] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 1, 0x0, 0), /* MX35_PAD_HCKR__AUDMUX_AUD5_RXFS */ - [271] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 2, 0x7f0, 0), /* MX35_PAD_HCKR__CSPI2_SS0 */ - [272] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 3, 0x0, 0), /* MX35_PAD_HCKR__IPU_FLASH_STROBE */ - [273] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 5, 0x858, 1), /* MX35_PAD_HCKR__GPIO1_6 */ - [274] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 7, 0x0, 0), /* MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 */ - [275] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 0, 0x0, 0), /* MX35_PAD_SCKT__ESAI_SCKT */ - [276] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 5, 0x85c, 1), /* MX35_PAD_SCKT__GPIO1_7 */ - [277] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 6, 0x930, 0), /* MX35_PAD_SCKT__IPU_CSI_D_0 */ - [278] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 7, 0x978, 1), /* MX35_PAD_SCKT__KPP_ROW_2 */ - [279] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 0, 0x0, 0), /* MX35_PAD_FST__ESAI_FST */ - [280] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 5, 0x860, 1), /* MX35_PAD_FST__GPIO1_8 */ - [281] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 6, 0x934, 0), /* MX35_PAD_FST__IPU_CSI_D_1 */ - [282] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 7, 0x97c, 1), /* MX35_PAD_FST__KPP_ROW_3 */ - [283] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 0, 0x0, 0), /* MX35_PAD_HCKT__ESAI_HCKT */ - [284] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 1, 0x7a8, 0), /* MX35_PAD_HCKT__AUDMUX_AUD5_RXC */ - [285] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 5, 0x864, 0), /* MX35_PAD_HCKT__GPIO1_9 */ - [286] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 6, 0x938, 0), /* MX35_PAD_HCKT__IPU_CSI_D_2 */ - [287] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 7, 0x95c, 1), /* MX35_PAD_HCKT__KPP_COL_3 */ - [288] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 0, 0x0, 0), /* MX35_PAD_TX5_RX0__ESAI_TX5_RX0 */ - [289] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 1, 0x0, 0), /* MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC */ - [290] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 2, 0x7f8, 1), /* MX35_PAD_TX5_RX0__CSPI2_SS2 */ - [291] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 3, 0x0, 0), /* MX35_PAD_TX5_RX0__CAN2_TXCAN */ - [292] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 4, 0x0, 0), /* MX35_PAD_TX5_RX0__UART2_DTR */ - [293] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 5, 0x830, 0), /* MX35_PAD_TX5_RX0__GPIO1_10 */ - [294] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 7, 0x0, 0), /* MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 */ - [295] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 0, 0x0, 0), /* MX35_PAD_TX4_RX1__ESAI_TX4_RX1 */ - [296] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 1, 0x0, 0), /* MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS */ - [297] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 2, 0x7fc, 0), /* MX35_PAD_TX4_RX1__CSPI2_SS3 */ - [298] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 3, 0x7cc, 0), /* MX35_PAD_TX4_RX1__CAN2_RXCAN */ - [299] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 4, 0x0, 0), /* MX35_PAD_TX4_RX1__UART2_DSR */ - [300] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 5, 0x834, 0), /* MX35_PAD_TX4_RX1__GPIO1_11 */ - [301] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 6, 0x93c, 0), /* MX35_PAD_TX4_RX1__IPU_CSI_D_3 */ - [302] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 7, 0x970, 1), /* MX35_PAD_TX4_RX1__KPP_ROW_0 */ - [303] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 0, 0x0, 0), /* MX35_PAD_TX3_RX2__ESAI_TX3_RX2 */ - [304] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 1, 0x91c, 0), /* MX35_PAD_TX3_RX2__I2C3_SCL */ - [305] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 3, 0x0, 0), /* MX35_PAD_TX3_RX2__EMI_NANDF_CE1 */ - [306] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 5, 0x0, 0), /* MX35_PAD_TX3_RX2__GPIO1_12 */ - [307] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 6, 0x940, 0), /* MX35_PAD_TX3_RX2__IPU_CSI_D_4 */ - [308] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 7, 0x974, 1), /* MX35_PAD_TX3_RX2__KPP_ROW_1 */ - [309] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 0, 0x0, 0), /* MX35_PAD_TX2_RX3__ESAI_TX2_RX3 */ - [310] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 1, 0x920, 0), /* MX35_PAD_TX2_RX3__I2C3_SDA */ - [311] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 3, 0x0, 0), /* MX35_PAD_TX2_RX3__EMI_NANDF_CE2 */ - [312] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 5, 0x0, 0), /* MX35_PAD_TX2_RX3__GPIO1_13 */ - [313] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 6, 0x944, 0), /* MX35_PAD_TX2_RX3__IPU_CSI_D_5 */ - [314] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 7, 0x950, 1), /* MX35_PAD_TX2_RX3__KPP_COL_0 */ - [315] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 0, 0x0, 0), /* MX35_PAD_TX1__ESAI_TX1 */ - [316] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 1, 0x7d4, 1), /* MX35_PAD_TX1__CCM_PMIC_RDY */ - [317] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 2, 0x7d8, 2), /* MX35_PAD_TX1__CSPI1_SS2 */ - [318] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 3, 0x0, 0), /* MX35_PAD_TX1__EMI_NANDF_CE3 */ - [319] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 4, 0x0, 0), /* MX35_PAD_TX1__UART2_RI */ - [320] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 5, 0x0, 0), /* MX35_PAD_TX1__GPIO1_14 */ - [321] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 6, 0x948, 0), /* MX35_PAD_TX1__IPU_CSI_D_6 */ - [322] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 7, 0x954, 1), /* MX35_PAD_TX1__KPP_COL_1 */ - [323] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 0, 0x0, 0), /* MX35_PAD_TX0__ESAI_TX0 */ - [324] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 1, 0x994, 1), /* MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK */ - [325] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 2, 0x7dc, 0), /* MX35_PAD_TX0__CSPI1_SS3 */ - [326] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 3, 0x800, 1), /* MX35_PAD_TX0__EMI_DTACK_B */ - [327] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 4, 0x0, 0), /* MX35_PAD_TX0__UART2_DCD */ - [328] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 5, 0x0, 0), /* MX35_PAD_TX0__GPIO1_15 */ - [329] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 6, 0x94c, 0), /* MX35_PAD_TX0__IPU_CSI_D_7 */ - [330] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 7, 0x958, 1), /* MX35_PAD_TX0__KPP_COL_2 */ - [331] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 0, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__CSPI1_MOSI */ - [332] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 5, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__GPIO1_16 */ - [333] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 7, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 */ - [334] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 0, 0x0, 0), /* MX35_PAD_CSPI1_MISO__CSPI1_MISO */ - [335] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 5, 0x0, 0), /* MX35_PAD_CSPI1_MISO__GPIO1_17 */ - [336] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 7, 0x0, 0), /* MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 */ - [337] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS0__CSPI1_SS0 */ - [338] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 1, 0x990, 1), /* MX35_PAD_CSPI1_SS0__OWIRE_LINE */ - [339] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 2, 0x7fc, 1), /* MX35_PAD_CSPI1_SS0__CSPI2_SS3 */ - [340] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS0__GPIO1_18 */ - [341] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 */ - [342] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS1__CSPI1_SS1 */ - [343] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 1, 0x0, 0), /* MX35_PAD_CSPI1_SS1__PWM_PWMO */ - [344] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 2, 0x7d0, 1), /* MX35_PAD_CSPI1_SS1__CCM_CLK32K */ - [345] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS1__GPIO1_19 */ - [346] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 6, 0x0, 0), /* MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 */ - [347] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 */ - [348] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 0, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__CSPI1_SCLK */ - [349] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 5, 0x904, 0), /* MX35_PAD_CSPI1_SCLK__GPIO3_4 */ - [350] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 6, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 */ - [351] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 7, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 */ - [352] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 0, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY */ - [353] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 5, 0x908, 0), /* MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 */ - [354] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 6, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 */ - [355] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 7, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 */ - [356] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 0, 0x0, 0), /* MX35_PAD_RXD1__UART1_RXD_MUX */ - [357] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 1, 0x7ec, 1), /* MX35_PAD_RXD1__CSPI2_MOSI */ - [358] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 4, 0x960, 0), /* MX35_PAD_RXD1__KPP_COL_4 */ - [359] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 5, 0x90c, 0), /* MX35_PAD_RXD1__GPIO3_6 */ - [360] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 7, 0x0, 0), /* MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 */ - [361] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 0, 0x0, 0), /* MX35_PAD_TXD1__UART1_TXD_MUX */ - [362] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 1, 0x7e8, 1), /* MX35_PAD_TXD1__CSPI2_MISO */ - [363] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 4, 0x964, 0), /* MX35_PAD_TXD1__KPP_COL_5 */ - [364] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 5, 0x910, 0), /* MX35_PAD_TXD1__GPIO3_7 */ - [365] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 7, 0x0, 0), /* MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 */ - [366] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 0, 0x0, 0), /* MX35_PAD_RTS1__UART1_RTS */ - [367] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 1, 0x7e0, 1), /* MX35_PAD_RTS1__CSPI2_SCLK */ - [368] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 2, 0x91c, 1), /* MX35_PAD_RTS1__I2C3_SCL */ - [369] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 3, 0x930, 1), /* MX35_PAD_RTS1__IPU_CSI_D_0 */ - [370] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 4, 0x968, 0), /* MX35_PAD_RTS1__KPP_COL_6 */ - [371] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 5, 0x914, 0), /* MX35_PAD_RTS1__GPIO3_8 */ - [372] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 6, 0x0, 0), /* MX35_PAD_RTS1__EMI_NANDF_CE1 */ - [373] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 7, 0x0, 0), /* MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 */ - [374] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 0, 0x0, 0), /* MX35_PAD_CTS1__UART1_CTS */ - [375] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 1, 0x7e4, 1), /* MX35_PAD_CTS1__CSPI2_RDY */ - [376] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 2, 0x920, 1), /* MX35_PAD_CTS1__I2C3_SDA */ - [377] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 3, 0x934, 1), /* MX35_PAD_CTS1__IPU_CSI_D_1 */ - [378] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 4, 0x96c, 0), /* MX35_PAD_CTS1__KPP_COL_7 */ - [379] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 5, 0x918, 0), /* MX35_PAD_CTS1__GPIO3_9 */ - [380] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 6, 0x0, 0), /* MX35_PAD_CTS1__EMI_NANDF_CE2 */ - [381] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 7, 0x0, 0), /* MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 */ - [382] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 0, 0x0, 0), /* MX35_PAD_RXD2__UART2_RXD_MUX */ - [383] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 4, 0x980, 0), /* MX35_PAD_RXD2__KPP_ROW_4 */ - [384] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 5, 0x8ec, 0), /* MX35_PAD_RXD2__GPIO3_10 */ - [385] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 0, 0x0, 0), /* MX35_PAD_TXD2__UART2_TXD_MUX */ - [386] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 1, 0x994, 2), /* MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK */ - [387] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 4, 0x984, 0), /* MX35_PAD_TXD2__KPP_ROW_5 */ - [388] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 5, 0x8f0, 0), /* MX35_PAD_TXD2__GPIO3_11 */ - [389] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 0, 0x0, 0), /* MX35_PAD_RTS2__UART2_RTS */ - [390] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 1, 0x998, 1), /* MX35_PAD_RTS2__SPDIF_SPDIF_IN1 */ - [391] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 2, 0x7cc, 1), /* MX35_PAD_RTS2__CAN2_RXCAN */ - [392] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 3, 0x938, 1), /* MX35_PAD_RTS2__IPU_CSI_D_2 */ - [393] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 4, 0x988, 0), /* MX35_PAD_RTS2__KPP_ROW_6 */ - [394] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 5, 0x8f4, 0), /* MX35_PAD_RTS2__GPIO3_12 */ - [395] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 6, 0x0, 0), /* MX35_PAD_RTS2__AUDMUX_AUD5_RXC */ - [396] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 7, 0x9a0, 0), /* MX35_PAD_RTS2__UART3_RXD_MUX */ - [397] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 0, 0x0, 0), /* MX35_PAD_CTS2__UART2_CTS */ - [398] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 1, 0x0, 0), /* MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 */ - [399] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 2, 0x0, 0), /* MX35_PAD_CTS2__CAN2_TXCAN */ - [400] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 3, 0x93c, 1), /* MX35_PAD_CTS2__IPU_CSI_D_3 */ - [401] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 4, 0x98c, 0), /* MX35_PAD_CTS2__KPP_ROW_7 */ - [402] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 5, 0x8f8, 0), /* MX35_PAD_CTS2__GPIO3_13 */ - [403] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 6, 0x0, 0), /* MX35_PAD_CTS2__AUDMUX_AUD5_RXFS */ - [404] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 7, 0x0, 0), /* MX35_PAD_CTS2__UART3_TXD_MUX */ - [405] = IMX_PIN_REG(MX35_PAD_RTCK, 0x5ec, 0x0, 0, 0x0, 0), /* MX35_PAD_RTCK__ARM11P_TOP_RTCK */ - [406] = IMX_PIN_REG(MX35_PAD_TCK, 0x5f0, 0x0, 0, 0x0, 0), /* MX35_PAD_TCK__SJC_TCK */ - [407] = IMX_PIN_REG(MX35_PAD_TMS, 0x5f4, 0x0, 0, 0x0, 0), /* MX35_PAD_TMS__SJC_TMS */ - [408] = IMX_PIN_REG(MX35_PAD_TDI, 0x5f8, 0x0, 0, 0x0, 0), /* MX35_PAD_TDI__SJC_TDI */ - [409] = IMX_PIN_REG(MX35_PAD_TDO, 0x5fc, 0x0, 0, 0x0, 0), /* MX35_PAD_TDO__SJC_TDO */ - [410] = IMX_PIN_REG(MX35_PAD_TRSTB, 0x600, 0x0, 0, 0x0, 0), /* MX35_PAD_TRSTB__SJC_TRSTB */ - [411] = IMX_PIN_REG(MX35_PAD_DE_B, 0x604, 0x0, 0, 0x0, 0), /* MX35_PAD_DE_B__SJC_DE_B */ - [412] = IMX_PIN_REG(MX35_PAD_SJC_MOD, 0x608, 0x0, 0, 0x0, 0), /* MX35_PAD_SJC_MOD__SJC_MOD */ - [413] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 0, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR */ - [414] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 1, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR */ - [415] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 5, 0x8fc, 0), /* MX35_PAD_USBOTG_PWR__GPIO3_14 */ - [416] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 0, 0x0, 0), /* MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC */ - [417] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 1, 0x9f4, 1), /* MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC */ - [418] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 5, 0x900, 0), /* MX35_PAD_USBOTG_OC__GPIO3_15 */ - [419] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 0, 0x0, 0), /* MX35_PAD_LD0__IPU_DISPB_DAT_0 */ - [420] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 5, 0x868, 1), /* MX35_PAD_LD0__GPIO2_0 */ - [421] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 6, 0x0, 0), /* MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 */ - [422] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 0, 0x0, 0), /* MX35_PAD_LD1__IPU_DISPB_DAT_1 */ - [423] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 5, 0x894, 0), /* MX35_PAD_LD1__GPIO2_1 */ - [424] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 6, 0x0, 0), /* MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 */ - [425] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 0, 0x0, 0), /* MX35_PAD_LD2__IPU_DISPB_DAT_2 */ - [426] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 5, 0x8c0, 0), /* MX35_PAD_LD2__GPIO2_2 */ - [427] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 6, 0x0, 0), /* MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 */ - [428] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 0, 0x0, 0), /* MX35_PAD_LD3__IPU_DISPB_DAT_3 */ - [429] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 5, 0x8cc, 0), /* MX35_PAD_LD3__GPIO2_3 */ - [430] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 6, 0x0, 0), /* MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 */ - [431] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 0, 0x0, 0), /* MX35_PAD_LD4__IPU_DISPB_DAT_4 */ - [432] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 5, 0x8d0, 0), /* MX35_PAD_LD4__GPIO2_4 */ - [433] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 6, 0x0, 0), /* MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 */ - [434] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 0, 0x0, 0), /* MX35_PAD_LD5__IPU_DISPB_DAT_5 */ - [435] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 5, 0x8d4, 0), /* MX35_PAD_LD5__GPIO2_5 */ - [436] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 6, 0x0, 0), /* MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 */ - [437] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 0, 0x0, 0), /* MX35_PAD_LD6__IPU_DISPB_DAT_6 */ - [438] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 5, 0x8d8, 0), /* MX35_PAD_LD6__GPIO2_6 */ - [439] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 6, 0x0, 0), /* MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 */ - [440] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 0, 0x0, 0), /* MX35_PAD_LD7__IPU_DISPB_DAT_7 */ - [441] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 5, 0x8dc, 0), /* MX35_PAD_LD7__GPIO2_7 */ - [442] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 6, 0x0, 0), /* MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 */ - [443] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 0, 0x0, 0), /* MX35_PAD_LD8__IPU_DISPB_DAT_8 */ - [444] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 5, 0x8e0, 0), /* MX35_PAD_LD8__GPIO2_8 */ - [445] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 6, 0x0, 0), /* MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 */ - [446] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 0, 0x0, 0), /* MX35_PAD_LD9__IPU_DISPB_DAT_9 */ - [447] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 5, 0x8e4, 0), /* MX35_PAD_LD9__GPIO2_9 */ - [448] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 6, 0x0, 0), /* MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 */ - [449] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 0, 0x0, 0), /* MX35_PAD_LD10__IPU_DISPB_DAT_10 */ - [450] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 5, 0x86c, 0), /* MX35_PAD_LD10__GPIO2_10 */ - [451] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 6, 0x0, 0), /* MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 */ - [452] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 0, 0x0, 0), /* MX35_PAD_LD11__IPU_DISPB_DAT_11 */ - [453] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 5, 0x870, 0), /* MX35_PAD_LD11__GPIO2_11 */ - [454] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 6, 0x0, 0), /* MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 */ - [455] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 7, 0x0, 0), /* MX35_PAD_LD11__ARM11P_TOP_TRACE_4 */ - [456] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 0, 0x0, 0), /* MX35_PAD_LD12__IPU_DISPB_DAT_12 */ - [457] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 5, 0x874, 0), /* MX35_PAD_LD12__GPIO2_12 */ - [458] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 6, 0x0, 0), /* MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 */ - [459] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 7, 0x0, 0), /* MX35_PAD_LD12__ARM11P_TOP_TRACE_5 */ - [460] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 0, 0x0, 0), /* MX35_PAD_LD13__IPU_DISPB_DAT_13 */ - [461] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 5, 0x878, 0), /* MX35_PAD_LD13__GPIO2_13 */ - [462] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 6, 0x0, 0), /* MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 */ - [463] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 7, 0x0, 0), /* MX35_PAD_LD13__ARM11P_TOP_TRACE_6 */ - [464] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 0, 0x0, 0), /* MX35_PAD_LD14__IPU_DISPB_DAT_14 */ - [465] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 5, 0x87c, 0), /* MX35_PAD_LD14__GPIO2_14 */ - [466] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 6, 0x0, 0), /* MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 */ - [467] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 7, 0x0, 0), /* MX35_PAD_LD14__ARM11P_TOP_TRACE_7 */ - [468] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 0, 0x0, 0), /* MX35_PAD_LD15__IPU_DISPB_DAT_15 */ - [469] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 5, 0x880, 0), /* MX35_PAD_LD15__GPIO2_15 */ - [470] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 6, 0x0, 0), /* MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 */ - [471] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 7, 0x0, 0), /* MX35_PAD_LD15__ARM11P_TOP_TRACE_8 */ - [472] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 0, 0x0, 0), /* MX35_PAD_LD16__IPU_DISPB_DAT_16 */ - [473] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 2, 0x928, 0), /* MX35_PAD_LD16__IPU_DISPB_D12_VSYNC */ - [474] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 5, 0x884, 0), /* MX35_PAD_LD16__GPIO2_16 */ - [475] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 6, 0x0, 0), /* MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 */ - [476] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 7, 0x0, 0), /* MX35_PAD_LD16__ARM11P_TOP_TRACE_9 */ - [477] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 0, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_DAT_17 */ - [478] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 2, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_CS2 */ - [479] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 5, 0x888, 0), /* MX35_PAD_LD17__GPIO2_17 */ - [480] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 6, 0x0, 0), /* MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 */ - [481] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 7, 0x0, 0), /* MX35_PAD_LD17__ARM11P_TOP_TRACE_10 */ - [482] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 0, 0x0, 0), /* MX35_PAD_LD18__IPU_DISPB_DAT_18 */ - [483] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 1, 0x924, 1), /* MX35_PAD_LD18__IPU_DISPB_D0_VSYNC */ - [484] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 2, 0x928, 1), /* MX35_PAD_LD18__IPU_DISPB_D12_VSYNC */ - [485] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 3, 0x818, 0), /* MX35_PAD_LD18__ESDHC3_CMD */ - [486] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 4, 0x9b0, 0), /* MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 */ - [487] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 5, 0x0, 0), /* MX35_PAD_LD18__GPIO3_24 */ - [488] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 6, 0x0, 0), /* MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 */ - [489] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 7, 0x0, 0), /* MX35_PAD_LD18__ARM11P_TOP_TRACE_11 */ - [490] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 0, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_DAT_19 */ - [491] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 1, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_BCLK */ - [492] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 2, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_CS1 */ - [493] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 3, 0x814, 0), /* MX35_PAD_LD19__ESDHC3_CLK */ - [494] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 4, 0x9c4, 0), /* MX35_PAD_LD19__USB_TOP_USBOTG_DIR */ - [495] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 5, 0x0, 0), /* MX35_PAD_LD19__GPIO3_25 */ - [496] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 6, 0x0, 0), /* MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 */ - [497] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 7, 0x0, 0), /* MX35_PAD_LD19__ARM11P_TOP_TRACE_12 */ - [498] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 0, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_DAT_20 */ - [499] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 1, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_CS0 */ - [500] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 2, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_SD_CLK */ - [501] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 3, 0x81c, 0), /* MX35_PAD_LD20__ESDHC3_DAT0 */ - [502] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 5, 0x0, 0), /* MX35_PAD_LD20__GPIO3_26 */ - [503] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 6, 0x0, 0), /* MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 */ - [504] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 7, 0x0, 0), /* MX35_PAD_LD20__ARM11P_TOP_TRACE_13 */ - [505] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 0, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_DAT_21 */ - [506] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 1, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_PAR_RS */ - [507] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 2, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_SER_RS */ - [508] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 3, 0x820, 0), /* MX35_PAD_LD21__ESDHC3_DAT1 */ - [509] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 4, 0x0, 0), /* MX35_PAD_LD21__USB_TOP_USBOTG_STP */ - [510] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 5, 0x0, 0), /* MX35_PAD_LD21__GPIO3_27 */ - [511] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 6, 0x0, 0), /* MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL */ - [512] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 7, 0x0, 0), /* MX35_PAD_LD21__ARM11P_TOP_TRACE_14 */ - [513] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 0, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_DAT_22 */ - [514] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 1, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_WR */ - [515] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 2, 0x92c, 0), /* MX35_PAD_LD22__IPU_DISPB_SD_D_I */ - [516] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 3, 0x824, 0), /* MX35_PAD_LD22__ESDHC3_DAT2 */ - [517] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 4, 0x9c8, 0), /* MX35_PAD_LD22__USB_TOP_USBOTG_NXT */ - [518] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 5, 0x0, 0), /* MX35_PAD_LD22__GPIO3_28 */ - [519] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 6, 0x0, 0), /* MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR */ - [520] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 7, 0x0, 0), /* MX35_PAD_LD22__ARM11P_TOP_TRCTL */ - [521] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 0, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_DAT_23 */ - [522] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 1, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_RD */ - [523] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 2, 0x92c, 1), /* MX35_PAD_LD23__IPU_DISPB_SD_D_IO */ - [524] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 3, 0x828, 0), /* MX35_PAD_LD23__ESDHC3_DAT3 */ - [525] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 4, 0x9c0, 0), /* MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 */ - [526] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 5, 0x0, 0), /* MX35_PAD_LD23__GPIO3_29 */ - [527] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 6, 0x0, 0), /* MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS */ - [528] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 7, 0x0, 0), /* MX35_PAD_LD23__ARM11P_TOP_TRCLK */ - [529] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 0, 0x0, 0), /* MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC */ - [530] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 2, 0x92c, 2), /* MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO */ - [531] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 5, 0x0, 0), /* MX35_PAD_D3_HSYNC__GPIO3_30 */ - [532] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 6, 0x0, 0), /* MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE */ - [533] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 7, 0x0, 0), /* MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 */ - [534] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 0, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK */ - [535] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 2, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK */ - [536] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 5, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__GPIO3_31 */ - [537] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 6, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 */ - [538] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 7, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 */ - [539] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 0, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY */ - [540] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 2, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O */ - [541] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 5, 0x82c, 2), /* MX35_PAD_D3_DRDY__GPIO1_0 */ - [542] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 6, 0x0, 0), /* MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 */ - [543] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 7, 0x0, 0), /* MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 */ - [544] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 0, 0x0, 0), /* MX35_PAD_CONTRAST__IPU_DISPB_CONTR */ - [545] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 5, 0x838, 2), /* MX35_PAD_CONTRAST__GPIO1_1 */ - [546] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 6, 0x0, 0), /* MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 */ - [547] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 7, 0x0, 0), /* MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 */ - [548] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 0, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC */ - [549] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 2, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 */ - [550] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 5, 0x848, 1), /* MX35_PAD_D3_VSYNC__GPIO1_2 */ - [551] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 6, 0x0, 0), /* MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD */ - [552] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 7, 0x0, 0), /* MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 */ - [553] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 0, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_D3_REV */ - [554] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 2, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_SER_RS */ - [555] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 5, 0x84c, 1), /* MX35_PAD_D3_REV__GPIO1_3 */ - [556] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 6, 0x0, 0), /* MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB */ - [557] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 7, 0x0, 0), /* MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 */ - [558] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 0, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS */ - [559] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 2, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_CS2 */ - [560] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 5, 0x850, 2), /* MX35_PAD_D3_CLS__GPIO1_4 */ - [561] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 6, 0x0, 0), /* MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 */ - [562] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 7, 0x0, 0), /* MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 */ - [563] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 0, 0x0, 0), /* MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL */ - [564] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 2, 0x928, 2), /* MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC */ - [565] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 5, 0x854, 2), /* MX35_PAD_D3_SPL__GPIO1_5 */ - [566] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 6, 0x0, 0), /* MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 */ - [567] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 7, 0x0, 0), /* MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 */ - [568] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 0, 0x0, 0), /* MX35_PAD_SD1_CMD__ESDHC1_CMD */ - [569] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 1, 0x0, 0), /* MX35_PAD_SD1_CMD__MSHC_SCLK */ - [570] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 3, 0x924, 2), /* MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC */ - [571] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 4, 0x9b4, 0), /* MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 */ - [572] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 5, 0x858, 2), /* MX35_PAD_SD1_CMD__GPIO1_6 */ - [573] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 7, 0x0, 0), /* MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL */ - [574] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 0, 0x0, 0), /* MX35_PAD_SD1_CLK__ESDHC1_CLK */ - [575] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 1, 0x0, 0), /* MX35_PAD_SD1_CLK__MSHC_BS */ - [576] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 3, 0x0, 0), /* MX35_PAD_SD1_CLK__IPU_DISPB_BCLK */ - [577] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 4, 0x9b8, 0), /* MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 */ - [578] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 5, 0x85c, 2), /* MX35_PAD_SD1_CLK__GPIO1_7 */ - [579] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 7, 0x0, 0), /* MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK */ - [580] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 0, 0x0, 0), /* MX35_PAD_SD1_DATA0__ESDHC1_DAT0 */ - [581] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 1, 0x0, 0), /* MX35_PAD_SD1_DATA0__MSHC_DATA_0 */ - [582] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 3, 0x0, 0), /* MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 */ - [583] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 4, 0x9bc, 0), /* MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 */ - [584] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 5, 0x860, 2), /* MX35_PAD_SD1_DATA0__GPIO1_8 */ - [585] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 7, 0x0, 0), /* MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 */ - [586] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 0, 0x0, 0), /* MX35_PAD_SD1_DATA1__ESDHC1_DAT1 */ - [587] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 1, 0x0, 0), /* MX35_PAD_SD1_DATA1__MSHC_DATA_1 */ - [588] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 3, 0x0, 0), /* MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS */ - [589] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 4, 0x9a4, 0), /* MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 */ - [590] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 5, 0x864, 1), /* MX35_PAD_SD1_DATA1__GPIO1_9 */ - [591] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 7, 0x0, 0), /* MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 */ - [592] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 0, 0x0, 0), /* MX35_PAD_SD1_DATA2__ESDHC1_DAT2 */ - [593] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 1, 0x0, 0), /* MX35_PAD_SD1_DATA2__MSHC_DATA_2 */ - [594] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 3, 0x0, 0), /* MX35_PAD_SD1_DATA2__IPU_DISPB_WR */ - [595] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 4, 0x9a8, 0), /* MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 */ - [596] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 5, 0x830, 1), /* MX35_PAD_SD1_DATA2__GPIO1_10 */ - [597] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 7, 0x0, 0), /* MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 */ - [598] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 0, 0x0, 0), /* MX35_PAD_SD1_DATA3__ESDHC1_DAT3 */ - [599] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 1, 0x0, 0), /* MX35_PAD_SD1_DATA3__MSHC_DATA_3 */ - [600] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 3, 0x0, 0), /* MX35_PAD_SD1_DATA3__IPU_DISPB_RD */ - [601] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 4, 0x9ac, 0), /* MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 */ - [602] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 5, 0x834, 1), /* MX35_PAD_SD1_DATA3__GPIO1_11 */ - [603] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 7, 0x0, 0), /* MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 */ - [604] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 0, 0x0, 0), /* MX35_PAD_SD2_CMD__ESDHC2_CMD */ - [605] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 1, 0x91c, 2), /* MX35_PAD_SD2_CMD__I2C3_SCL */ - [606] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 2, 0x804, 0), /* MX35_PAD_SD2_CMD__ESDHC1_DAT4 */ - [607] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 3, 0x938, 2), /* MX35_PAD_SD2_CMD__IPU_CSI_D_2 */ - [608] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 4, 0x9dc, 0), /* MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 */ - [609] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 5, 0x868, 2), /* MX35_PAD_SD2_CMD__GPIO2_0 */ - [610] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 6, 0x0, 0), /* MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 */ - [611] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 7, 0x928, 3), /* MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC */ - [612] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 0, 0x0, 0), /* MX35_PAD_SD2_CLK__ESDHC2_CLK */ - [613] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 1, 0x920, 2), /* MX35_PAD_SD2_CLK__I2C3_SDA */ - [614] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 2, 0x808, 0), /* MX35_PAD_SD2_CLK__ESDHC1_DAT5 */ - [615] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 3, 0x93c, 2), /* MX35_PAD_SD2_CLK__IPU_CSI_D_3 */ - [616] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 4, 0x9e0, 0), /* MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 */ - [617] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 5, 0x894, 1), /* MX35_PAD_SD2_CLK__GPIO2_1 */ - [618] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 6, 0x998, 2), /* MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 */ - [619] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 7, 0x0, 0), /* MX35_PAD_SD2_CLK__IPU_DISPB_CS2 */ - [620] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 0, 0x0, 0), /* MX35_PAD_SD2_DATA0__ESDHC2_DAT0 */ - [621] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 1, 0x9a0, 1), /* MX35_PAD_SD2_DATA0__UART3_RXD_MUX */ - [622] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 2, 0x80c, 0), /* MX35_PAD_SD2_DATA0__ESDHC1_DAT6 */ - [623] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 3, 0x940, 1), /* MX35_PAD_SD2_DATA0__IPU_CSI_D_4 */ - [624] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 4, 0x9e4, 0), /* MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 */ - [625] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 5, 0x8c0, 1), /* MX35_PAD_SD2_DATA0__GPIO2_2 */ - [626] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 6, 0x994, 3), /* MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK */ - [627] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 0, 0x0, 0), /* MX35_PAD_SD2_DATA1__ESDHC2_DAT1 */ - [628] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 1, 0x0, 0), /* MX35_PAD_SD2_DATA1__UART3_TXD_MUX */ - [629] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 2, 0x810, 0), /* MX35_PAD_SD2_DATA1__ESDHC1_DAT7 */ - [630] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 3, 0x944, 1), /* MX35_PAD_SD2_DATA1__IPU_CSI_D_5 */ - [631] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 4, 0x9cc, 0), /* MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 */ - [632] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 5, 0x8cc, 1), /* MX35_PAD_SD2_DATA1__GPIO2_3 */ - [633] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 0, 0x0, 0), /* MX35_PAD_SD2_DATA2__ESDHC2_DAT2 */ - [634] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 1, 0x99c, 0), /* MX35_PAD_SD2_DATA2__UART3_RTS */ - [635] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 2, 0x7c8, 1), /* MX35_PAD_SD2_DATA2__CAN1_RXCAN */ - [636] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 3, 0x948, 1), /* MX35_PAD_SD2_DATA2__IPU_CSI_D_6 */ - [637] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 4, 0x9d0, 0), /* MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 */ - [638] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 5, 0x8d0, 1), /* MX35_PAD_SD2_DATA2__GPIO2_4 */ - [639] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 0, 0x0, 0), /* MX35_PAD_SD2_DATA3__ESDHC2_DAT3 */ - [640] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 1, 0x0, 0), /* MX35_PAD_SD2_DATA3__UART3_CTS */ - [641] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 2, 0x0, 0), /* MX35_PAD_SD2_DATA3__CAN1_TXCAN */ - [642] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 3, 0x94c, 1), /* MX35_PAD_SD2_DATA3__IPU_CSI_D_7 */ - [643] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 4, 0x9d4, 0), /* MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 */ - [644] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 5, 0x8d4, 1), /* MX35_PAD_SD2_DATA3__GPIO2_5 */ - [645] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 0, 0x0, 0), /* MX35_PAD_ATA_CS0__ATA_CS0 */ - [646] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 1, 0x7dc, 1), /* MX35_PAD_ATA_CS0__CSPI1_SS3 */ - [647] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 3, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DISPB_CS1 */ - [648] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 5, 0x8d8, 1), /* MX35_PAD_ATA_CS0__GPIO2_6 */ - [649] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 6, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DIAGB_0 */ - [650] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 7, 0x0, 0), /* MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 */ - [651] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 0, 0x0, 0), /* MX35_PAD_ATA_CS1__ATA_CS1 */ - [652] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 3, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DISPB_CS2 */ - [653] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 4, 0x7f0, 1), /* MX35_PAD_ATA_CS1__CSPI2_SS0 */ - [654] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 5, 0x8dc, 1), /* MX35_PAD_ATA_CS1__GPIO2_7 */ - [655] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 6, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DIAGB_1 */ - [656] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 7, 0x0, 0), /* MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 */ - [657] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 0, 0x0, 0), /* MX35_PAD_ATA_DIOR__ATA_DIOR */ - [658] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 1, 0x81c, 1), /* MX35_PAD_ATA_DIOR__ESDHC3_DAT0 */ - [659] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 2, 0x9c4, 1), /* MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR */ - [660] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 3, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 */ - [661] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 4, 0x7f4, 1), /* MX35_PAD_ATA_DIOR__CSPI2_SS1 */ - [662] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 5, 0x8e0, 1), /* MX35_PAD_ATA_DIOR__GPIO2_8 */ - [663] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 6, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DIAGB_2 */ - [664] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 7, 0x0, 0), /* MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 */ - [665] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 0, 0x0, 0), /* MX35_PAD_ATA_DIOW__ATA_DIOW */ - [666] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 1, 0x820, 1), /* MX35_PAD_ATA_DIOW__ESDHC3_DAT1 */ - [667] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 2, 0x0, 0), /* MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP */ - [668] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 3, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 */ - [669] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 4, 0x7ec, 2), /* MX35_PAD_ATA_DIOW__CSPI2_MOSI */ - [670] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 5, 0x8e4, 1), /* MX35_PAD_ATA_DIOW__GPIO2_9 */ - [671] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 6, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DIAGB_3 */ - [672] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 7, 0x0, 0), /* MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 */ - [673] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 0, 0x0, 0), /* MX35_PAD_ATA_DMACK__ATA_DMACK */ - [674] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 1, 0x824, 1), /* MX35_PAD_ATA_DMACK__ESDHC3_DAT2 */ - [675] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 2, 0x9c8, 1), /* MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT */ - [676] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 4, 0x7e8, 2), /* MX35_PAD_ATA_DMACK__CSPI2_MISO */ - [677] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 5, 0x86c, 1), /* MX35_PAD_ATA_DMACK__GPIO2_10 */ - [678] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 6, 0x0, 0), /* MX35_PAD_ATA_DMACK__IPU_DIAGB_4 */ - [679] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 7, 0x0, 0), /* MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 */ - [680] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 0, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ATA_RESET_B */ - [681] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 1, 0x828, 1), /* MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 */ - [682] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 2, 0x9a4, 1), /* MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 */ - [683] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 3, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O */ - [684] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 4, 0x7e4, 2), /* MX35_PAD_ATA_RESET_B__CSPI2_RDY */ - [685] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 5, 0x870, 1), /* MX35_PAD_ATA_RESET_B__GPIO2_11 */ - [686] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 6, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 */ - [687] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 7, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 */ - [688] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 0, 0x0, 0), /* MX35_PAD_ATA_IORDY__ATA_IORDY */ - [689] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 1, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC3_DAT4 */ - [690] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 2, 0x9a8, 1), /* MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 */ - [691] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 3, 0x92c, 3), /* MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO */ - [692] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 4, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC2_DAT4 */ - [693] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 5, 0x874, 1), /* MX35_PAD_ATA_IORDY__GPIO2_12 */ - [694] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 6, 0x0, 0), /* MX35_PAD_ATA_IORDY__IPU_DIAGB_6 */ - [695] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 7, 0x0, 0), /* MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 */ - [696] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA0__ATA_DATA_0 */ - [697] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 1, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC3_DAT5 */ - [698] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 2, 0x9ac, 1), /* MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 */ - [699] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 3, 0x928, 4), /* MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC */ - [700] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 4, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC2_DAT5 */ - [701] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 5, 0x878, 1), /* MX35_PAD_ATA_DATA0__GPIO2_13 */ - [702] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA0__IPU_DIAGB_7 */ - [703] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 */ - [704] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 0, 0x0, 0), /* MX35_PAD_ATA_DATA1__ATA_DATA_1 */ - [705] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 1, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC3_DAT6 */ - [706] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 2, 0x9b0, 1), /* MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 */ - [707] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 3, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK */ - [708] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 4, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC2_DAT6 */ - [709] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 5, 0x87c, 1), /* MX35_PAD_ATA_DATA1__GPIO2_14 */ - [710] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 6, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DIAGB_8 */ - [711] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 7, 0x0, 0), /* MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 */ - [712] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 0, 0x0, 0), /* MX35_PAD_ATA_DATA2__ATA_DATA_2 */ - [713] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 1, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC3_DAT7 */ - [714] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 2, 0x9b4, 1), /* MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 */ - [715] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 3, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS */ - [716] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 4, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC2_DAT7 */ - [717] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 5, 0x880, 1), /* MX35_PAD_ATA_DATA2__GPIO2_15 */ - [718] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 6, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DIAGB_9 */ - [719] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 7, 0x0, 0), /* MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 */ - [720] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 0, 0x0, 0), /* MX35_PAD_ATA_DATA3__ATA_DATA_3 */ - [721] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 1, 0x814, 1), /* MX35_PAD_ATA_DATA3__ESDHC3_CLK */ - [722] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 2, 0x9b8, 1), /* MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 */ - [723] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 4, 0x7e0, 2), /* MX35_PAD_ATA_DATA3__CSPI2_SCLK */ - [724] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 5, 0x884, 1), /* MX35_PAD_ATA_DATA3__GPIO2_16 */ - [725] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 6, 0x0, 0), /* MX35_PAD_ATA_DATA3__IPU_DIAGB_10 */ - [726] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 7, 0x0, 0), /* MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 */ - [727] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA4__ATA_DATA_4 */ - [728] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 1, 0x818, 1), /* MX35_PAD_ATA_DATA4__ESDHC3_CMD */ - [729] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 2, 0x9bc, 1), /* MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 */ - [730] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 5, 0x888, 1), /* MX35_PAD_ATA_DATA4__GPIO2_17 */ - [731] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA4__IPU_DIAGB_11 */ - [732] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 */ - [733] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 0, 0x0, 0), /* MX35_PAD_ATA_DATA5__ATA_DATA_5 */ - [734] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 2, 0x9c0, 1), /* MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 */ - [735] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 5, 0x88c, 1), /* MX35_PAD_ATA_DATA5__GPIO2_18 */ - [736] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 6, 0x0, 0), /* MX35_PAD_ATA_DATA5__IPU_DIAGB_12 */ - [737] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 7, 0x0, 0), /* MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 */ - [738] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 0, 0x0, 0), /* MX35_PAD_ATA_DATA6__ATA_DATA_6 */ - [739] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 1, 0x0, 0), /* MX35_PAD_ATA_DATA6__CAN1_TXCAN */ - [740] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 2, 0x0, 0), /* MX35_PAD_ATA_DATA6__UART1_DTR */ - [741] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 3, 0x7b4, 0), /* MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD */ - [742] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 5, 0x890, 1), /* MX35_PAD_ATA_DATA6__GPIO2_19 */ - [743] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 6, 0x0, 0), /* MX35_PAD_ATA_DATA6__IPU_DIAGB_13 */ - [744] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 0, 0x0, 0), /* MX35_PAD_ATA_DATA7__ATA_DATA_7 */ - [745] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 1, 0x7c8, 2), /* MX35_PAD_ATA_DATA7__CAN1_RXCAN */ - [746] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 2, 0x0, 0), /* MX35_PAD_ATA_DATA7__UART1_DSR */ - [747] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 3, 0x7b0, 0), /* MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD */ - [748] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 5, 0x898, 1), /* MX35_PAD_ATA_DATA7__GPIO2_20 */ - [749] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 6, 0x0, 0), /* MX35_PAD_ATA_DATA7__IPU_DIAGB_14 */ - [750] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA8__ATA_DATA_8 */ - [751] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 1, 0x99c, 1), /* MX35_PAD_ATA_DATA8__UART3_RTS */ - [752] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 2, 0x0, 0), /* MX35_PAD_ATA_DATA8__UART1_RI */ - [753] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 3, 0x7c0, 0), /* MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC */ - [754] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 5, 0x89c, 1), /* MX35_PAD_ATA_DATA8__GPIO2_21 */ - [755] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA8__IPU_DIAGB_15 */ - [756] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA9__ATA_DATA_9 */ - [757] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 1, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART3_CTS */ - [758] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 2, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART1_DCD */ - [759] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 3, 0x7c4, 0), /* MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS */ - [760] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 5, 0x8a0, 1), /* MX35_PAD_ATA_DATA9__GPIO2_22 */ - [761] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA9__IPU_DIAGB_16 */ - [762] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA10__ATA_DATA_10 */ - [763] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 1, 0x9a0, 2), /* MX35_PAD_ATA_DATA10__UART3_RXD_MUX */ - [764] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 3, 0x7b8, 0), /* MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC */ - [765] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 5, 0x8a4, 1), /* MX35_PAD_ATA_DATA10__GPIO2_23 */ - [766] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA10__IPU_DIAGB_17 */ - [767] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA11__ATA_DATA_11 */ - [768] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 1, 0x0, 0), /* MX35_PAD_ATA_DATA11__UART3_TXD_MUX */ - [769] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 3, 0x7bc, 0), /* MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS */ - [770] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 5, 0x8a8, 1), /* MX35_PAD_ATA_DATA11__GPIO2_24 */ - [771] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA11__IPU_DIAGB_18 */ - [772] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 0, 0x0, 0), /* MX35_PAD_ATA_DATA12__ATA_DATA_12 */ - [773] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 1, 0x91c, 3), /* MX35_PAD_ATA_DATA12__I2C3_SCL */ - [774] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 5, 0x8ac, 1), /* MX35_PAD_ATA_DATA12__GPIO2_25 */ - [775] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 6, 0x0, 0), /* MX35_PAD_ATA_DATA12__IPU_DIAGB_19 */ - [776] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA13__ATA_DATA_13 */ - [777] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 1, 0x920, 3), /* MX35_PAD_ATA_DATA13__I2C3_SDA */ - [778] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 5, 0x8b0, 1), /* MX35_PAD_ATA_DATA13__GPIO2_26 */ - [779] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA13__IPU_DIAGB_20 */ - [780] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA14__ATA_DATA_14 */ - [781] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 1, 0x930, 2), /* MX35_PAD_ATA_DATA14__IPU_CSI_D_0 */ - [782] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 3, 0x970, 2), /* MX35_PAD_ATA_DATA14__KPP_ROW_0 */ - [783] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 5, 0x8b4, 1), /* MX35_PAD_ATA_DATA14__GPIO2_27 */ - [784] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA14__IPU_DIAGB_21 */ - [785] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA15__ATA_DATA_15 */ - [786] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 1, 0x934, 2), /* MX35_PAD_ATA_DATA15__IPU_CSI_D_1 */ - [787] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 3, 0x974, 2), /* MX35_PAD_ATA_DATA15__KPP_ROW_1 */ - [788] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 5, 0x8b8, 1), /* MX35_PAD_ATA_DATA15__GPIO2_28 */ - [789] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA15__IPU_DIAGB_22 */ - [790] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 0, 0x0, 0), /* MX35_PAD_ATA_INTRQ__ATA_INTRQ */ - [791] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 1, 0x938, 3), /* MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 */ - [792] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 3, 0x978, 2), /* MX35_PAD_ATA_INTRQ__KPP_ROW_2 */ - [793] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 5, 0x8bc, 1), /* MX35_PAD_ATA_INTRQ__GPIO2_29 */ - [794] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 6, 0x0, 0), /* MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 */ - [795] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 0, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN */ - [796] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 1, 0x93c, 3), /* MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 */ - [797] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 3, 0x97c, 2), /* MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 */ - [798] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 5, 0x8c4, 1), /* MX35_PAD_ATA_BUFF_EN__GPIO2_30 */ - [799] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 6, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 */ - [800] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 0, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ATA_DMARQ */ - [801] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 1, 0x940, 2), /* MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 */ - [802] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 3, 0x950, 2), /* MX35_PAD_ATA_DMARQ__KPP_COL_0 */ - [803] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 5, 0x8c8, 1), /* MX35_PAD_ATA_DMARQ__GPIO2_31 */ - [804] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 6, 0x0, 0), /* MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 */ - [805] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 7, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 */ - [806] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 0, 0x0, 0), /* MX35_PAD_ATA_DA0__ATA_DA_0 */ - [807] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 1, 0x944, 2), /* MX35_PAD_ATA_DA0__IPU_CSI_D_5 */ - [808] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 3, 0x954, 2), /* MX35_PAD_ATA_DA0__KPP_COL_1 */ - [809] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 5, 0x8e8, 1), /* MX35_PAD_ATA_DA0__GPIO3_0 */ - [810] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 6, 0x0, 0), /* MX35_PAD_ATA_DA0__IPU_DIAGB_26 */ - [811] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 7, 0x0, 0), /* MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 */ - [812] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 0, 0x0, 0), /* MX35_PAD_ATA_DA1__ATA_DA_1 */ - [813] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 1, 0x948, 2), /* MX35_PAD_ATA_DA1__IPU_CSI_D_6 */ - [814] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 3, 0x958, 2), /* MX35_PAD_ATA_DA1__KPP_COL_2 */ - [815] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 5, 0x0, 0), /* MX35_PAD_ATA_DA1__GPIO3_1 */ - [816] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 6, 0x0, 0), /* MX35_PAD_ATA_DA1__IPU_DIAGB_27 */ - [817] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 7, 0x0, 0), /* MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 */ - [818] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 0, 0x0, 0), /* MX35_PAD_ATA_DA2__ATA_DA_2 */ - [819] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 1, 0x94c, 2), /* MX35_PAD_ATA_DA2__IPU_CSI_D_7 */ - [820] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 3, 0x95c, 2), /* MX35_PAD_ATA_DA2__KPP_COL_3 */ - [821] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 5, 0x0, 0), /* MX35_PAD_ATA_DA2__GPIO3_2 */ - [822] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 6, 0x0, 0), /* MX35_PAD_ATA_DA2__IPU_DIAGB_28 */ - [823] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 7, 0x0, 0), /* MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 */ - [824] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 0, 0x0, 0), /* MX35_PAD_MLB_CLK__MLB_MLBCLK */ - [825] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 5, 0x0, 0), /* MX35_PAD_MLB_CLK__GPIO3_3 */ - [826] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 0, 0x0, 0), /* MX35_PAD_MLB_DAT__MLB_MLBDAT */ - [827] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 5, 0x904, 1), /* MX35_PAD_MLB_DAT__GPIO3_4 */ - [828] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 0, 0x0, 0), /* MX35_PAD_MLB_SIG__MLB_MLBSIG */ - [829] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 5, 0x908, 1), /* MX35_PAD_MLB_SIG__GPIO3_5 */ - [830] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 0, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__FEC_TX_CLK */ - [831] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 1, 0x804, 1), /* MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 */ - [832] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 2, 0x9a0, 3), /* MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX */ - [833] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 3, 0x9ec, 1), /* MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR */ - [834] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 4, 0x7ec, 3), /* MX35_PAD_FEC_TX_CLK__CSPI2_MOSI */ - [835] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 5, 0x90c, 1), /* MX35_PAD_FEC_TX_CLK__GPIO3_6 */ - [836] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 6, 0x928, 5), /* MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC */ - [837] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 7, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 */ - [838] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 0, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__FEC_RX_CLK */ - [839] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 1, 0x808, 1), /* MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 */ - [840] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 2, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX */ - [841] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 3, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP */ - [842] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 4, 0x7e8, 3), /* MX35_PAD_FEC_RX_CLK__CSPI2_MISO */ - [843] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 5, 0x910, 1), /* MX35_PAD_FEC_RX_CLK__GPIO3_7 */ - [844] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 6, 0x92c, 4), /* MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I */ - [845] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 7, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 */ - [846] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 0, 0x0, 0), /* MX35_PAD_FEC_RX_DV__FEC_RX_DV */ - [847] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 1, 0x80c, 1), /* MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 */ - [848] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 2, 0x99c, 2), /* MX35_PAD_FEC_RX_DV__UART3_RTS */ - [849] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 3, 0x9f0, 1), /* MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT */ - [850] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 4, 0x7e0, 3), /* MX35_PAD_FEC_RX_DV__CSPI2_SCLK */ - [851] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 5, 0x914, 1), /* MX35_PAD_FEC_RX_DV__GPIO3_8 */ - [852] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 6, 0x0, 0), /* MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK */ - [853] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 7, 0x0, 0), /* MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 */ - [854] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 0, 0x0, 0), /* MX35_PAD_FEC_COL__FEC_COL */ - [855] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 1, 0x810, 1), /* MX35_PAD_FEC_COL__ESDHC1_DAT7 */ - [856] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 2, 0x0, 0), /* MX35_PAD_FEC_COL__UART3_CTS */ - [857] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 3, 0x9cc, 1), /* MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 */ - [858] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 4, 0x7e4, 3), /* MX35_PAD_FEC_COL__CSPI2_RDY */ - [859] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 5, 0x918, 1), /* MX35_PAD_FEC_COL__GPIO3_9 */ - [860] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 6, 0x0, 0), /* MX35_PAD_FEC_COL__IPU_DISPB_SER_RS */ - [861] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 7, 0x0, 0), /* MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 */ - [862] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA0__FEC_RDATA_0 */ - [863] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 1, 0x0, 0), /* MX35_PAD_FEC_RDATA0__PWM_PWMO */ - [864] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA0__UART3_DTR */ - [865] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 3, 0x9d0, 1), /* MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 */ - [866] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 4, 0x7f0, 2), /* MX35_PAD_FEC_RDATA0__CSPI2_SS0 */ - [867] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 5, 0x8ec, 1), /* MX35_PAD_FEC_RDATA0__GPIO3_10 */ - [868] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 */ - [869] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 7, 0x0, 0), /* MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 */ - [870] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA0__FEC_TDATA_0 */ - [871] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 1, 0x0, 0), /* MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 */ - [872] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 2, 0x0, 0), /* MX35_PAD_FEC_TDATA0__UART3_DSR */ - [873] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 3, 0x9d4, 1), /* MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 */ - [874] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 4, 0x7f4, 2), /* MX35_PAD_FEC_TDATA0__CSPI2_SS1 */ - [875] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 5, 0x8f0, 1), /* MX35_PAD_FEC_TDATA0__GPIO3_11 */ - [876] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 */ - [877] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 7, 0x0, 0), /* MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 */ - [878] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 0, 0x0, 0), /* MX35_PAD_FEC_TX_EN__FEC_TX_EN */ - [879] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 1, 0x998, 3), /* MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 */ - [880] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 2, 0x0, 0), /* MX35_PAD_FEC_TX_EN__UART3_RI */ - [881] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 3, 0x9d8, 1), /* MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 */ - [882] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 5, 0x8f4, 1), /* MX35_PAD_FEC_TX_EN__GPIO3_12 */ - [883] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 6, 0x0, 0), /* MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS */ - [884] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 7, 0x0, 0), /* MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 */ - [885] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 0, 0x0, 0), /* MX35_PAD_FEC_MDC__FEC_MDC */ - [886] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 1, 0x0, 0), /* MX35_PAD_FEC_MDC__CAN2_TXCAN */ - [887] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 2, 0x0, 0), /* MX35_PAD_FEC_MDC__UART3_DCD */ - [888] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 3, 0x9dc, 1), /* MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 */ - [889] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 5, 0x8f8, 1), /* MX35_PAD_FEC_MDC__GPIO3_13 */ - [890] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 6, 0x0, 0), /* MX35_PAD_FEC_MDC__IPU_DISPB_WR */ - [891] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 7, 0x0, 0), /* MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 */ - [892] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 0, 0x0, 0), /* MX35_PAD_FEC_MDIO__FEC_MDIO */ - [893] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 1, 0x7cc, 2), /* MX35_PAD_FEC_MDIO__CAN2_RXCAN */ - [894] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 3, 0x9e0, 1), /* MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 */ - [895] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 5, 0x8fc, 1), /* MX35_PAD_FEC_MDIO__GPIO3_14 */ - [896] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 6, 0x0, 0), /* MX35_PAD_FEC_MDIO__IPU_DISPB_RD */ - [897] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 7, 0x0, 0), /* MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 */ - [898] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 0, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__FEC_TX_ERR */ - [899] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 1, 0x990, 2), /* MX35_PAD_FEC_TX_ERR__OWIRE_LINE */ - [900] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 2, 0x994, 4), /* MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK */ - [901] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 3, 0x9e4, 1), /* MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 */ - [902] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 5, 0x900, 1), /* MX35_PAD_FEC_TX_ERR__GPIO3_15 */ - [903] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 6, 0x924, 3), /* MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC */ - [904] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 7, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 */ - [905] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 0, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__FEC_RX_ERR */ - [906] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 1, 0x930, 3), /* MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 */ - [907] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 3, 0x9e8, 1), /* MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 */ - [908] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 4, 0x960, 1), /* MX35_PAD_FEC_RX_ERR__KPP_COL_4 */ - [909] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 5, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__GPIO3_16 */ - [910] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 6, 0x92c, 5), /* MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO */ - [911] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 0, 0x0, 0), /* MX35_PAD_FEC_CRS__FEC_CRS */ - [912] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 1, 0x934, 3), /* MX35_PAD_FEC_CRS__IPU_CSI_D_1 */ - [913] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 3, 0x0, 0), /* MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR */ - [914] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 4, 0x964, 1), /* MX35_PAD_FEC_CRS__KPP_COL_5 */ - [915] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 5, 0x0, 0), /* MX35_PAD_FEC_CRS__GPIO3_17 */ - [916] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 6, 0x0, 0), /* MX35_PAD_FEC_CRS__IPU_FLASH_STROBE */ - [917] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA1__FEC_RDATA_1 */ - [918] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 1, 0x938, 4), /* MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 */ - [919] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC */ - [920] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 3, 0x9f4, 2), /* MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC */ - [921] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 4, 0x968, 1), /* MX35_PAD_FEC_RDATA1__KPP_COL_6 */ - [922] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA1__GPIO3_18 */ - [923] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 */ - [924] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA1__FEC_TDATA_1 */ - [925] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 1, 0x93c, 4), /* MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 */ - [926] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 2, 0x7bc, 1), /* MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS */ - [927] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 4, 0x96c, 1), /* MX35_PAD_FEC_TDATA1__KPP_COL_7 */ - [928] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA1__GPIO3_19 */ - [929] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 */ - [930] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA2__FEC_RDATA_2 */ - [931] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 1, 0x940, 3), /* MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 */ - [932] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 2, 0x7b4, 1), /* MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD */ - [933] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 4, 0x980, 1), /* MX35_PAD_FEC_RDATA2__KPP_ROW_4 */ - [934] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA2__GPIO3_20 */ - [935] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA2__FEC_TDATA_2 */ - [936] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 1, 0x944, 3), /* MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 */ - [937] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 2, 0x7b0, 1), /* MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD */ - [938] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 4, 0x984, 1), /* MX35_PAD_FEC_TDATA2__KPP_ROW_5 */ - [939] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA2__GPIO3_21 */ - [940] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA3__FEC_RDATA_3 */ - [941] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 1, 0x948, 3), /* MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 */ - [942] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 2, 0x7c0, 1), /* MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC */ - [943] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 4, 0x988, 1), /* MX35_PAD_FEC_RDATA3__KPP_ROW_6 */ - [944] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA3__GPIO3_22 */ - [945] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA3__FEC_TDATA_3 */ - [946] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 1, 0x94c, 3), /* MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 */ - [947] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 2, 0x7c4, 1), /* MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS */ - [948] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 4, 0x98c, 1), /* MX35_PAD_FEC_TDATA3__KPP_ROW_7 */ - [949] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA3__GPIO3_23 */ - [950] = IMX_PIN_REG(MX35_PAD_EXT_ARMCLK, 0x78c, 0x0, 0, 0x0, 0), /* MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK */ - [951] = IMX_PIN_REG(MX35_PAD_TEST_MODE, 0x790, 0x0, 0, 0x0, 0), /* MX35_PAD_TEST_MODE__TCU_TEST_MODE */ + MX35_PAD_RESERVE0 = 0, + MX35_PAD_CAPTURE = 1, + MX35_PAD_COMPARE = 2, + MX35_PAD_WDOG_RST = 3, + MX35_PAD_GPIO1_0 = 4, + MX35_PAD_GPIO1_1 = 5, + MX35_PAD_GPIO2_0 = 6, + MX35_PAD_GPIO3_0 = 7, + MX35_PAD_CLKO = 8, + MX35_PAD_VSTBY = 9, + MX35_PAD_A0 = 10, + MX35_PAD_A1 = 11, + MX35_PAD_A2 = 12, + MX35_PAD_A3 = 13, + MX35_PAD_A4 = 14, + MX35_PAD_A5 = 15, + MX35_PAD_A6 = 16, + MX35_PAD_A7 = 17, + MX35_PAD_A8 = 18, + MX35_PAD_A9 = 19, + MX35_PAD_A10 = 20, + MX35_PAD_MA10 = 21, + MX35_PAD_A11 = 22, + MX35_PAD_A12 = 23, + MX35_PAD_A13 = 24, + MX35_PAD_A14 = 25, + MX35_PAD_A15 = 26, + MX35_PAD_A16 = 27, + MX35_PAD_A17 = 28, + MX35_PAD_A18 = 29, + MX35_PAD_A19 = 30, + MX35_PAD_A20 = 31, + MX35_PAD_A21 = 32, + MX35_PAD_A22 = 33, + MX35_PAD_A23 = 34, + MX35_PAD_A24 = 35, + MX35_PAD_A25 = 36, + MX35_PAD_EB0 = 37, + MX35_PAD_EB1 = 38, + MX35_PAD_OE = 39, + MX35_PAD_CS0 = 40, + MX35_PAD_CS1 = 41, + MX35_PAD_CS2 = 42, + MX35_PAD_CS3 = 43, + MX35_PAD_CS4 = 44, + MX35_PAD_CS5 = 45, + MX35_PAD_NF_CE0 = 46, + MX35_PAD_LBA = 47, + MX35_PAD_BCLK = 48, + MX35_PAD_RW = 49, + MX35_PAD_NFWE_B = 50, + MX35_PAD_NFRE_B = 51, + MX35_PAD_NFALE = 52, + MX35_PAD_NFCLE = 53, + MX35_PAD_NFWP_B = 54, + MX35_PAD_NFRB = 55, + MX35_PAD_CSI_D8 = 56, + MX35_PAD_CSI_D9 = 57, + MX35_PAD_CSI_D10 = 58, + MX35_PAD_CSI_D11 = 59, + MX35_PAD_CSI_D12 = 60, + MX35_PAD_CSI_D13 = 61, + MX35_PAD_CSI_D14 = 62, + MX35_PAD_CSI_D15 = 63, + MX35_PAD_CSI_MCLK = 64, + MX35_PAD_CSI_VSYNC = 65, + MX35_PAD_CSI_HSYNC = 66, + MX35_PAD_CSI_PIXCLK = 67, + MX35_PAD_I2C1_CLK = 68, + MX35_PAD_I2C1_DAT = 69, + MX35_PAD_I2C2_CLK = 70, + MX35_PAD_I2C2_DAT = 71, + MX35_PAD_STXD4 = 72, + MX35_PAD_SRXD4 = 73, + MX35_PAD_SCK4 = 74, + MX35_PAD_STXFS4 = 75, + MX35_PAD_STXD5 = 76, + MX35_PAD_SRXD5 = 77, + MX35_PAD_SCK5 = 78, + MX35_PAD_STXFS5 = 79, + MX35_PAD_SCKR = 80, + MX35_PAD_FSR = 81, + MX35_PAD_HCKR = 82, + MX35_PAD_SCKT = 83, + MX35_PAD_FST = 84, + MX35_PAD_HCKT = 85, + MX35_PAD_TX5_RX0 = 86, + MX35_PAD_TX4_RX1 = 87, + MX35_PAD_TX3_RX2 = 88, + MX35_PAD_TX2_RX3 = 89, + MX35_PAD_TX1 = 90, + MX35_PAD_TX0 = 91, + MX35_PAD_CSPI1_MOSI = 92, + MX35_PAD_CSPI1_MISO = 93, + MX35_PAD_CSPI1_SS0 = 94, + MX35_PAD_CSPI1_SS1 = 95, + MX35_PAD_CSPI1_SCLK = 96, + MX35_PAD_CSPI1_SPI_RDY = 97, + MX35_PAD_RXD1 = 98, + MX35_PAD_TXD1 = 99, + MX35_PAD_RTS1 = 100, + MX35_PAD_CTS1 = 101, + MX35_PAD_RXD2 = 102, + MX35_PAD_TXD2 = 103, + MX35_PAD_RTS2 = 104, + MX35_PAD_CTS2 = 105, + MX35_PAD_USBOTG_PWR = 106, + MX35_PAD_USBOTG_OC = 107, + MX35_PAD_LD0 = 108, + MX35_PAD_LD1 = 109, + MX35_PAD_LD2 = 110, + MX35_PAD_LD3 = 111, + MX35_PAD_LD4 = 112, + MX35_PAD_LD5 = 113, + MX35_PAD_LD6 = 114, + MX35_PAD_LD7 = 115, + MX35_PAD_LD8 = 116, + MX35_PAD_LD9 = 117, + MX35_PAD_LD10 = 118, + MX35_PAD_LD11 = 119, + MX35_PAD_LD12 = 120, + MX35_PAD_LD13 = 121, + MX35_PAD_LD14 = 122, + MX35_PAD_LD15 = 123, + MX35_PAD_LD16 = 124, + MX35_PAD_LD17 = 125, + MX35_PAD_LD18 = 126, + MX35_PAD_LD19 = 127, + MX35_PAD_LD20 = 128, + MX35_PAD_LD21 = 129, + MX35_PAD_LD22 = 130, + MX35_PAD_LD23 = 131, + MX35_PAD_D3_HSYNC = 132, + MX35_PAD_D3_FPSHIFT = 133, + MX35_PAD_D3_DRDY = 134, + MX35_PAD_CONTRAST = 135, + MX35_PAD_D3_VSYNC = 136, + MX35_PAD_D3_REV = 137, + MX35_PAD_D3_CLS = 138, + MX35_PAD_D3_SPL = 139, + MX35_PAD_SD1_CMD = 140, + MX35_PAD_SD1_CLK = 141, + MX35_PAD_SD1_DATA0 = 142, + MX35_PAD_SD1_DATA1 = 143, + MX35_PAD_SD1_DATA2 = 144, + MX35_PAD_SD1_DATA3 = 145, + MX35_PAD_SD2_CMD = 146, + MX35_PAD_SD2_CLK = 147, + MX35_PAD_SD2_DATA0 = 148, + MX35_PAD_SD2_DATA1 = 149, + MX35_PAD_SD2_DATA2 = 150, + MX35_PAD_SD2_DATA3 = 151, + MX35_PAD_ATA_CS0 = 152, + MX35_PAD_ATA_CS1 = 153, + MX35_PAD_ATA_DIOR = 154, + MX35_PAD_ATA_DIOW = 155, + MX35_PAD_ATA_DMACK = 156, + MX35_PAD_ATA_RESET_B = 157, + MX35_PAD_ATA_IORDY = 158, + MX35_PAD_ATA_DATA0 = 159, + MX35_PAD_ATA_DATA1 = 160, + MX35_PAD_ATA_DATA2 = 161, + MX35_PAD_ATA_DATA3 = 162, + MX35_PAD_ATA_DATA4 = 163, + MX35_PAD_ATA_DATA5 = 164, + MX35_PAD_ATA_DATA6 = 165, + MX35_PAD_ATA_DATA7 = 166, + MX35_PAD_ATA_DATA8 = 167, + MX35_PAD_ATA_DATA9 = 168, + MX35_PAD_ATA_DATA10 = 169, + MX35_PAD_ATA_DATA11 = 170, + MX35_PAD_ATA_DATA12 = 171, + MX35_PAD_ATA_DATA13 = 172, + MX35_PAD_ATA_DATA14 = 173, + MX35_PAD_ATA_DATA15 = 174, + MX35_PAD_ATA_INTRQ = 175, + MX35_PAD_ATA_BUFF_EN = 176, + MX35_PAD_ATA_DMARQ = 177, + MX35_PAD_ATA_DA0 = 178, + MX35_PAD_ATA_DA1 = 179, + MX35_PAD_ATA_DA2 = 180, + MX35_PAD_MLB_CLK = 181, + MX35_PAD_MLB_DAT = 182, + MX35_PAD_MLB_SIG = 183, + MX35_PAD_FEC_TX_CLK = 184, + MX35_PAD_FEC_RX_CLK = 185, + MX35_PAD_FEC_RX_DV = 186, + MX35_PAD_FEC_COL = 187, + MX35_PAD_FEC_RDATA0 = 188, + MX35_PAD_FEC_TDATA0 = 189, + MX35_PAD_FEC_TX_EN = 190, + MX35_PAD_FEC_MDC = 191, + MX35_PAD_FEC_MDIO = 192, + MX35_PAD_FEC_TX_ERR = 193, + MX35_PAD_FEC_RX_ERR = 194, + MX35_PAD_FEC_CRS = 195, + MX35_PAD_FEC_RDATA1 = 196, + MX35_PAD_FEC_TDATA1 = 197, + MX35_PAD_FEC_RDATA2 = 198, + MX35_PAD_FEC_TDATA2 = 199, + MX35_PAD_FEC_RDATA3 = 200, + MX35_PAD_FEC_TDATA3 = 201, + MX35_PAD_RESERVE1 = 202, + MX35_PAD_RESERVE2 = 203, + MX35_PAD_RESERVE3 = 204, + MX35_PAD_RESERVE4 = 205, + MX35_PAD_RESERVE5 = 206, + MX35_PAD_RESERVE6 = 207, + MX35_PAD_RESERVE7 = 208, + MX35_PAD_RESET_IN_B = 209, + MX35_PAD_POR_B = 210, + MX35_PAD_RESERVE8 = 211, + MX35_PAD_BOOT_MODE0 = 212, + MX35_PAD_BOOT_MODE1 = 213, + MX35_PAD_CLK_MODE0 = 214, + MX35_PAD_CLK_MODE1 = 215, + MX35_PAD_POWER_FAIL = 216, + MX35_PAD_RESERVE9 = 217, + MX35_PAD_RESERVE10 = 218, + MX35_PAD_RESERVE11 = 219, + MX35_PAD_RESERVE12 = 220, + MX35_PAD_RESERVE13 = 221, + MX35_PAD_RESERVE14 = 222, + MX35_PAD_RESERVE15 = 223, + MX35_PAD_RESERVE16 = 224, + MX35_PAD_RESERVE17 = 225, + MX35_PAD_RESERVE18 = 226, + MX35_PAD_RESERVE19 = 227, + MX35_PAD_RESERVE20 = 228, + MX35_PAD_RESERVE21 = 229, + MX35_PAD_RESERVE22 = 230, + MX35_PAD_RESERVE23 = 231, + MX35_PAD_RESERVE24 = 232, + MX35_PAD_RESERVE25 = 233, + MX35_PAD_RESERVE26 = 234, + MX35_PAD_RESERVE27 = 235, + MX35_PAD_RESERVE28 = 236, + MX35_PAD_RESERVE29 = 237, + MX35_PAD_RESERVE30 = 238, + MX35_PAD_RESERVE31 = 239, + MX35_PAD_RESERVE32 = 240, + MX35_PAD_RESERVE33 = 241, + MX35_PAD_RESERVE34 = 242, + MX35_PAD_RESERVE35 = 243, + MX35_PAD_RESERVE36 = 244, + MX35_PAD_SDBA1 = 245, + MX35_PAD_SDBA0 = 246, + MX35_PAD_SD0 = 247, + MX35_PAD_SD1 = 248, + MX35_PAD_SD2 = 249, + MX35_PAD_SD3 = 250, + MX35_PAD_SD4 = 251, + MX35_PAD_SD5 = 252, + MX35_PAD_SD6 = 253, + MX35_PAD_SD7 = 254, + MX35_PAD_SD8 = 255, + MX35_PAD_SD9 = 256, + MX35_PAD_SD10 = 257, + MX35_PAD_SD11 = 258, + MX35_PAD_SD12 = 259, + MX35_PAD_SD13 = 260, + MX35_PAD_SD14 = 261, + MX35_PAD_SD15 = 262, + MX35_PAD_SD16 = 263, + MX35_PAD_SD17 = 264, + MX35_PAD_SD18 = 265, + MX35_PAD_SD19 = 266, + MX35_PAD_SD20 = 267, + MX35_PAD_SD21 = 268, + MX35_PAD_SD22 = 269, + MX35_PAD_SD23 = 270, + MX35_PAD_SD24 = 271, + MX35_PAD_SD25 = 272, + MX35_PAD_SD26 = 273, + MX35_PAD_SD27 = 274, + MX35_PAD_SD28 = 275, + MX35_PAD_SD29 = 276, + MX35_PAD_SD30 = 277, + MX35_PAD_SD31 = 278, + MX35_PAD_DQM0 = 279, + MX35_PAD_DQM1 = 280, + MX35_PAD_DQM2 = 281, + MX35_PAD_DQM3 = 282, + MX35_PAD_RESERVE37 = 283, + MX35_PAD_RESERVE38 = 284, + MX35_PAD_RESERVE39 = 285, + MX35_PAD_RESERVE40 = 286, + MX35_PAD_RESERVE41 = 287, + MX35_PAD_RESERVE42 = 288, + MX35_PAD_RESERVE43 = 289, + MX35_PAD_RESERVE44 = 290, + MX35_PAD_RESERVE45 = 291, + MX35_PAD_RESERVE46 = 292, + MX35_PAD_ECB = 293, + MX35_PAD_RESERVE47 = 294, + MX35_PAD_RESERVE48 = 295, + MX35_PAD_RESERVE49 = 296, + MX35_PAD_RAS = 297, + MX35_PAD_CAS = 298, + MX35_PAD_SDWE = 299, + MX35_PAD_SDCKE0 = 300, + MX35_PAD_SDCKE1 = 301, + MX35_PAD_SDCLK = 302, + MX35_PAD_SDQS0 = 303, + MX35_PAD_SDQS1 = 304, + MX35_PAD_SDQS2 = 305, + MX35_PAD_SDQS3 = 306, + MX35_PAD_RESERVE50 = 307, + MX35_PAD_RESERVE51 = 308, + MX35_PAD_RESERVE52 = 309, + MX35_PAD_RESERVE53 = 310, + MX35_PAD_RESERVE54 = 311, + MX35_PAD_RESERVE55 = 312, + MX35_PAD_D15 = 313, + MX35_PAD_D14 = 314, + MX35_PAD_D13 = 315, + MX35_PAD_D12 = 316, + MX35_PAD_D11 = 317, + MX35_PAD_D10 = 318, + MX35_PAD_D9 = 319, + MX35_PAD_D8 = 320, + MX35_PAD_D7 = 321, + MX35_PAD_D6 = 322, + MX35_PAD_D5 = 323, + MX35_PAD_D4 = 324, + MX35_PAD_D3 = 325, + MX35_PAD_D2 = 326, + MX35_PAD_D1 = 327, + MX35_PAD_D0 = 328, + MX35_PAD_RESERVE56 = 329, + MX35_PAD_RESERVE57 = 330, + MX35_PAD_RESERVE58 = 331, + MX35_PAD_RESERVE59 = 332, + MX35_PAD_RESERVE60 = 333, + MX35_PAD_RESERVE61 = 334, + MX35_PAD_RESERVE62 = 335, + MX35_PAD_RESERVE63 = 336, + MX35_PAD_RESERVE64 = 337, + MX35_PAD_RESERVE65 = 338, + MX35_PAD_RESERVE66 = 339, + MX35_PAD_RESERVE67 = 340, + MX35_PAD_RESERVE68 = 341, + MX35_PAD_RESERVE69 = 342, + MX35_PAD_RESERVE70 = 343, + MX35_PAD_RESERVE71 = 344, + MX35_PAD_RESERVE72 = 345, + MX35_PAD_RESERVE73 = 346, + MX35_PAD_RESERVE74 = 347, + MX35_PAD_RESERVE75 = 348, + MX35_PAD_RESERVE76 = 349, + MX35_PAD_RESERVE77 = 350, + MX35_PAD_RESERVE78 = 351, + MX35_PAD_RESERVE79 = 352, + MX35_PAD_RESERVE80 = 353, + MX35_PAD_RESERVE81 = 354, + MX35_PAD_RESERVE82 = 355, + MX35_PAD_RESERVE83 = 356, + MX35_PAD_RESERVE84 = 357, + MX35_PAD_RESERVE85 = 358, + MX35_PAD_RESERVE86 = 359, + MX35_PAD_RESERVE87 = 360, + MX35_PAD_RESERVE88 = 361, + MX35_PAD_RESERVE89 = 362, + MX35_PAD_RESERVE90 = 363, + MX35_PAD_RESERVE91 = 364, + MX35_PAD_RESERVE92 = 365, + MX35_PAD_RESERVE93 = 366, + MX35_PAD_RESERVE94 = 367, + MX35_PAD_RESERVE95 = 368, + MX35_PAD_RESERVE96 = 369, + MX35_PAD_RESERVE97 = 370, + MX35_PAD_RESERVE98 = 371, + MX35_PAD_RESERVE99 = 372, + MX35_PAD_RESERVE100 = 373, + MX35_PAD_RESERVE101 = 374, + MX35_PAD_RESERVE102 = 375, + MX35_PAD_RESERVE103 = 376, + MX35_PAD_RESERVE104 = 377, + MX35_PAD_RESERVE105 = 378, + MX35_PAD_RTCK = 379, + MX35_PAD_TCK = 380, + MX35_PAD_TMS = 381, + MX35_PAD_TDI = 382, + MX35_PAD_TDO = 383, + MX35_PAD_TRSTB = 384, + MX35_PAD_DE_B = 385, + MX35_PAD_SJC_MOD = 386, + MX35_PAD_RESERVE106 = 387, + MX35_PAD_RESERVE107 = 388, + MX35_PAD_RESERVE108 = 389, + MX35_PAD_RESERVE109 = 390, + MX35_PAD_RESERVE110 = 391, + MX35_PAD_RESERVE111 = 392, + MX35_PAD_RESERVE112 = 393, + MX35_PAD_RESERVE113 = 394, + MX35_PAD_RESERVE114 = 395, + MX35_PAD_RESERVE115 = 396, + MX35_PAD_RESERVE116 = 397, + MX35_PAD_RESERVE117 = 398, + MX35_PAD_RESERVE118 = 399, + MX35_PAD_RESERVE119 = 400, + MX35_PAD_RESERVE120 = 401, + MX35_PAD_RESERVE121 = 402, + MX35_PAD_RESERVE122 = 403, + MX35_PAD_RESERVE123 = 404, + MX35_PAD_RESERVE124 = 405, + MX35_PAD_RESERVE125 = 406, + MX35_PAD_RESERVE126 = 407, + MX35_PAD_RESERVE127 = 408, + MX35_PAD_RESERVE128 = 409, + MX35_PAD_RESERVE129 = 410, + MX35_PAD_RESERVE130 = 411, + MX35_PAD_RESERVE131 = 412, + MX35_PAD_RESERVE132 = 413, + MX35_PAD_RESERVE133 = 414, + MX35_PAD_RESERVE134 = 415, + MX35_PAD_RESERVE135 = 416, + MX35_PAD_RESERVE136 = 417, + MX35_PAD_RESERVE137 = 418, + MX35_PAD_RESERVE138 = 419, + MX35_PAD_RESERVE139 = 420, + MX35_PAD_RESERVE140 = 421, + MX35_PAD_RESERVE141 = 422, + MX35_PAD_RESERVE142 = 423, + MX35_PAD_RESERVE143 = 424, + MX35_PAD_RESERVE144 = 425, + MX35_PAD_RESERVE145 = 426, + MX35_PAD_RESERVE146 = 427, + MX35_PAD_RESERVE147 = 428, + MX35_PAD_RESERVE148 = 429, + MX35_PAD_RESERVE149 = 430, + MX35_PAD_RESERVE150 = 431, + MX35_PAD_RESERVE151 = 432, + MX35_PAD_RESERVE152 = 433, + MX35_PAD_RESERVE153 = 434, + MX35_PAD_RESERVE154 = 435, + MX35_PAD_RESERVE155 = 436, + MX35_PAD_RESERVE156 = 437, + MX35_PAD_RESERVE157 = 438, + MX35_PAD_RESERVE158 = 439, + MX35_PAD_RESERVE159 = 440, + MX35_PAD_RESERVE160 = 441, + MX35_PAD_RESERVE161 = 442, + MX35_PAD_RESERVE162 = 443, + MX35_PAD_RESERVE163 = 444, + MX35_PAD_RESERVE164 = 445, + MX35_PAD_RESERVE165 = 446, + MX35_PAD_RESERVE166 = 447, + MX35_PAD_RESERVE167 = 448, + MX35_PAD_RESERVE168 = 449, + MX35_PAD_RESERVE169 = 450, + MX35_PAD_RESERVE170 = 451, + MX35_PAD_RESERVE171 = 452, + MX35_PAD_RESERVE172 = 453, + MX35_PAD_RESERVE173 = 454, + MX35_PAD_RESERVE174 = 455, + MX35_PAD_RESERVE175 = 456, + MX35_PAD_RESERVE176 = 457, + MX35_PAD_RESERVE177 = 458, + MX35_PAD_RESERVE178 = 459, + MX35_PAD_RESERVE179 = 460, + MX35_PAD_RESERVE180 = 461, + MX35_PAD_RESERVE181 = 462, + MX35_PAD_RESERVE182 = 463, + MX35_PAD_RESERVE183 = 464, + MX35_PAD_RESERVE184 = 465, + MX35_PAD_RESERVE185 = 466, + MX35_PAD_RESERVE186 = 467, + MX35_PAD_RESERVE187 = 468, + MX35_PAD_RESERVE188 = 469, + MX35_PAD_RESERVE189 = 470, + MX35_PAD_RESERVE190 = 471, + MX35_PAD_RESERVE191 = 472, + MX35_PAD_RESERVE192 = 473, + MX35_PAD_RESERVE193 = 474, + MX35_PAD_RESERVE194 = 475, + MX35_PAD_RESERVE195 = 476, + MX35_PAD_RESERVE196 = 477, + MX35_PAD_RESERVE197 = 478, + MX35_PAD_RESERVE198 = 479, + MX35_PAD_RESERVE199 = 480, + MX35_PAD_RESERVE200 = 481, + MX35_PAD_RESERVE201 = 482, + MX35_PAD_EXT_ARMCLK = 483, + MX35_PAD_TEST_MODE = 484, }; /* Pad names for the pinmux subsystem */ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX35_PAD_RESERVE0), IMX_PINCTRL_PIN(MX35_PAD_CAPTURE), IMX_PINCTRL_PIN(MX35_PAD_COMPARE), IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST), @@ -1274,14 +521,7 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1), IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0), IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0), - IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B), - IMX_PINCTRL_PIN(MX35_PAD_POR_B), IMX_PINCTRL_PIN(MX35_PAD_CLKO), - IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0), - IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1), - IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0), - IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1), - IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL), IMX_PINCTRL_PIN(MX35_PAD_VSTBY), IMX_PINCTRL_PIN(MX35_PAD_A0), IMX_PINCTRL_PIN(MX35_PAD_A1), @@ -1310,44 +550,6 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX35_PAD_A23), IMX_PINCTRL_PIN(MX35_PAD_A24), IMX_PINCTRL_PIN(MX35_PAD_A25), - IMX_PINCTRL_PIN(MX35_PAD_SDBA1), - IMX_PINCTRL_PIN(MX35_PAD_SDBA0), - IMX_PINCTRL_PIN(MX35_PAD_SD0), - IMX_PINCTRL_PIN(MX35_PAD_SD1), - IMX_PINCTRL_PIN(MX35_PAD_SD2), - IMX_PINCTRL_PIN(MX35_PAD_SD3), - IMX_PINCTRL_PIN(MX35_PAD_SD4), - IMX_PINCTRL_PIN(MX35_PAD_SD5), - IMX_PINCTRL_PIN(MX35_PAD_SD6), - IMX_PINCTRL_PIN(MX35_PAD_SD7), - IMX_PINCTRL_PIN(MX35_PAD_SD8), - IMX_PINCTRL_PIN(MX35_PAD_SD9), - IMX_PINCTRL_PIN(MX35_PAD_SD10), - IMX_PINCTRL_PIN(MX35_PAD_SD11), - IMX_PINCTRL_PIN(MX35_PAD_SD12), - IMX_PINCTRL_PIN(MX35_PAD_SD13), - IMX_PINCTRL_PIN(MX35_PAD_SD14), - IMX_PINCTRL_PIN(MX35_PAD_SD15), - IMX_PINCTRL_PIN(MX35_PAD_SD16), - IMX_PINCTRL_PIN(MX35_PAD_SD17), - IMX_PINCTRL_PIN(MX35_PAD_SD18), - IMX_PINCTRL_PIN(MX35_PAD_SD19), - IMX_PINCTRL_PIN(MX35_PAD_SD20), - IMX_PINCTRL_PIN(MX35_PAD_SD21), - IMX_PINCTRL_PIN(MX35_PAD_SD22), - IMX_PINCTRL_PIN(MX35_PAD_SD23), - IMX_PINCTRL_PIN(MX35_PAD_SD24), - IMX_PINCTRL_PIN(MX35_PAD_SD25), - IMX_PINCTRL_PIN(MX35_PAD_SD26), - IMX_PINCTRL_PIN(MX35_PAD_SD27), - IMX_PINCTRL_PIN(MX35_PAD_SD28), - IMX_PINCTRL_PIN(MX35_PAD_SD29), - IMX_PINCTRL_PIN(MX35_PAD_SD30), - IMX_PINCTRL_PIN(MX35_PAD_SD31), - IMX_PINCTRL_PIN(MX35_PAD_DQM0), - IMX_PINCTRL_PIN(MX35_PAD_DQM1), - IMX_PINCTRL_PIN(MX35_PAD_DQM2), - IMX_PINCTRL_PIN(MX35_PAD_DQM3), IMX_PINCTRL_PIN(MX35_PAD_EB0), IMX_PINCTRL_PIN(MX35_PAD_EB1), IMX_PINCTRL_PIN(MX35_PAD_OE), @@ -1358,42 +560,15 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX35_PAD_CS4), IMX_PINCTRL_PIN(MX35_PAD_CS5), IMX_PINCTRL_PIN(MX35_PAD_NF_CE0), - IMX_PINCTRL_PIN(MX35_PAD_ECB), IMX_PINCTRL_PIN(MX35_PAD_LBA), IMX_PINCTRL_PIN(MX35_PAD_BCLK), IMX_PINCTRL_PIN(MX35_PAD_RW), - IMX_PINCTRL_PIN(MX35_PAD_RAS), - IMX_PINCTRL_PIN(MX35_PAD_CAS), - IMX_PINCTRL_PIN(MX35_PAD_SDWE), - IMX_PINCTRL_PIN(MX35_PAD_SDCKE0), - IMX_PINCTRL_PIN(MX35_PAD_SDCKE1), - IMX_PINCTRL_PIN(MX35_PAD_SDCLK), - IMX_PINCTRL_PIN(MX35_PAD_SDQS0), - IMX_PINCTRL_PIN(MX35_PAD_SDQS1), - IMX_PINCTRL_PIN(MX35_PAD_SDQS2), - IMX_PINCTRL_PIN(MX35_PAD_SDQS3), IMX_PINCTRL_PIN(MX35_PAD_NFWE_B), IMX_PINCTRL_PIN(MX35_PAD_NFRE_B), IMX_PINCTRL_PIN(MX35_PAD_NFALE), IMX_PINCTRL_PIN(MX35_PAD_NFCLE), IMX_PINCTRL_PIN(MX35_PAD_NFWP_B), IMX_PINCTRL_PIN(MX35_PAD_NFRB), - IMX_PINCTRL_PIN(MX35_PAD_D15), - IMX_PINCTRL_PIN(MX35_PAD_D14), - IMX_PINCTRL_PIN(MX35_PAD_D13), - IMX_PINCTRL_PIN(MX35_PAD_D12), - IMX_PINCTRL_PIN(MX35_PAD_D11), - IMX_PINCTRL_PIN(MX35_PAD_D10), - IMX_PINCTRL_PIN(MX35_PAD_D9), - IMX_PINCTRL_PIN(MX35_PAD_D8), - IMX_PINCTRL_PIN(MX35_PAD_D7), - IMX_PINCTRL_PIN(MX35_PAD_D6), - IMX_PINCTRL_PIN(MX35_PAD_D5), - IMX_PINCTRL_PIN(MX35_PAD_D4), - IMX_PINCTRL_PIN(MX35_PAD_D3), - IMX_PINCTRL_PIN(MX35_PAD_D2), - IMX_PINCTRL_PIN(MX35_PAD_D1), - IMX_PINCTRL_PIN(MX35_PAD_D0), IMX_PINCTRL_PIN(MX35_PAD_CSI_D8), IMX_PINCTRL_PIN(MX35_PAD_CSI_D9), IMX_PINCTRL_PIN(MX35_PAD_CSI_D10), @@ -1444,14 +619,6 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX35_PAD_TXD2), IMX_PINCTRL_PIN(MX35_PAD_RTS2), IMX_PINCTRL_PIN(MX35_PAD_CTS2), - IMX_PINCTRL_PIN(MX35_PAD_RTCK), - IMX_PINCTRL_PIN(MX35_PAD_TCK), - IMX_PINCTRL_PIN(MX35_PAD_TMS), - IMX_PINCTRL_PIN(MX35_PAD_TDI), - IMX_PINCTRL_PIN(MX35_PAD_TDO), - IMX_PINCTRL_PIN(MX35_PAD_TRSTB), - IMX_PINCTRL_PIN(MX35_PAD_DE_B), - IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD), IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR), IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC), IMX_PINCTRL_PIN(MX35_PAD_LD0), @@ -1548,6 +715,287 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2), IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3), IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B), + IMX_PINCTRL_PIN(MX35_PAD_POR_B), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0), + IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1), + IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0), + IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1), + IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE18), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE19), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE20), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE21), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE22), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE23), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE24), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE25), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE26), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE27), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE28), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE29), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE30), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE31), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE32), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE33), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE34), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE35), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE36), + IMX_PINCTRL_PIN(MX35_PAD_SDBA1), + IMX_PINCTRL_PIN(MX35_PAD_SDBA0), + IMX_PINCTRL_PIN(MX35_PAD_SD0), + IMX_PINCTRL_PIN(MX35_PAD_SD1), + IMX_PINCTRL_PIN(MX35_PAD_SD2), + IMX_PINCTRL_PIN(MX35_PAD_SD3), + IMX_PINCTRL_PIN(MX35_PAD_SD4), + IMX_PINCTRL_PIN(MX35_PAD_SD5), + IMX_PINCTRL_PIN(MX35_PAD_SD6), + IMX_PINCTRL_PIN(MX35_PAD_SD7), + IMX_PINCTRL_PIN(MX35_PAD_SD8), + IMX_PINCTRL_PIN(MX35_PAD_SD9), + IMX_PINCTRL_PIN(MX35_PAD_SD10), + IMX_PINCTRL_PIN(MX35_PAD_SD11), + IMX_PINCTRL_PIN(MX35_PAD_SD12), + IMX_PINCTRL_PIN(MX35_PAD_SD13), + IMX_PINCTRL_PIN(MX35_PAD_SD14), + IMX_PINCTRL_PIN(MX35_PAD_SD15), + IMX_PINCTRL_PIN(MX35_PAD_SD16), + IMX_PINCTRL_PIN(MX35_PAD_SD17), + IMX_PINCTRL_PIN(MX35_PAD_SD18), + IMX_PINCTRL_PIN(MX35_PAD_SD19), + IMX_PINCTRL_PIN(MX35_PAD_SD20), + IMX_PINCTRL_PIN(MX35_PAD_SD21), + IMX_PINCTRL_PIN(MX35_PAD_SD22), + IMX_PINCTRL_PIN(MX35_PAD_SD23), + IMX_PINCTRL_PIN(MX35_PAD_SD24), + IMX_PINCTRL_PIN(MX35_PAD_SD25), + IMX_PINCTRL_PIN(MX35_PAD_SD26), + IMX_PINCTRL_PIN(MX35_PAD_SD27), + IMX_PINCTRL_PIN(MX35_PAD_SD28), + IMX_PINCTRL_PIN(MX35_PAD_SD29), + IMX_PINCTRL_PIN(MX35_PAD_SD30), + IMX_PINCTRL_PIN(MX35_PAD_SD31), + IMX_PINCTRL_PIN(MX35_PAD_DQM0), + IMX_PINCTRL_PIN(MX35_PAD_DQM1), + IMX_PINCTRL_PIN(MX35_PAD_DQM2), + IMX_PINCTRL_PIN(MX35_PAD_DQM3), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE37), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE38), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE39), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE40), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE41), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE42), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE43), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE44), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE45), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE46), + IMX_PINCTRL_PIN(MX35_PAD_ECB), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE47), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE48), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE49), + IMX_PINCTRL_PIN(MX35_PAD_RAS), + IMX_PINCTRL_PIN(MX35_PAD_CAS), + IMX_PINCTRL_PIN(MX35_PAD_SDWE), + IMX_PINCTRL_PIN(MX35_PAD_SDCKE0), + IMX_PINCTRL_PIN(MX35_PAD_SDCKE1), + IMX_PINCTRL_PIN(MX35_PAD_SDCLK), + IMX_PINCTRL_PIN(MX35_PAD_SDQS0), + IMX_PINCTRL_PIN(MX35_PAD_SDQS1), + IMX_PINCTRL_PIN(MX35_PAD_SDQS2), + IMX_PINCTRL_PIN(MX35_PAD_SDQS3), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE50), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE51), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE52), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE53), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE54), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE55), + IMX_PINCTRL_PIN(MX35_PAD_D15), + IMX_PINCTRL_PIN(MX35_PAD_D14), + IMX_PINCTRL_PIN(MX35_PAD_D13), + IMX_PINCTRL_PIN(MX35_PAD_D12), + IMX_PINCTRL_PIN(MX35_PAD_D11), + IMX_PINCTRL_PIN(MX35_PAD_D10), + IMX_PINCTRL_PIN(MX35_PAD_D9), + IMX_PINCTRL_PIN(MX35_PAD_D8), + IMX_PINCTRL_PIN(MX35_PAD_D7), + IMX_PINCTRL_PIN(MX35_PAD_D6), + IMX_PINCTRL_PIN(MX35_PAD_D5), + IMX_PINCTRL_PIN(MX35_PAD_D4), + IMX_PINCTRL_PIN(MX35_PAD_D3), + IMX_PINCTRL_PIN(MX35_PAD_D2), + IMX_PINCTRL_PIN(MX35_PAD_D1), + IMX_PINCTRL_PIN(MX35_PAD_D0), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE56), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE57), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE58), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE59), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE60), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE61), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE62), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE63), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE64), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE65), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE66), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE67), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE68), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE69), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE70), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE71), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE72), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE73), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE74), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE75), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE76), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE77), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE78), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE79), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE80), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE81), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE82), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE83), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE84), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE85), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE86), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE87), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE88), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE89), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE90), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE91), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE92), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE93), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE94), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE95), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE96), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE97), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE98), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE99), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE100), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE101), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE102), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE103), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE104), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE105), + IMX_PINCTRL_PIN(MX35_PAD_RTCK), + IMX_PINCTRL_PIN(MX35_PAD_TCK), + IMX_PINCTRL_PIN(MX35_PAD_TMS), + IMX_PINCTRL_PIN(MX35_PAD_TDI), + IMX_PINCTRL_PIN(MX35_PAD_TDO), + IMX_PINCTRL_PIN(MX35_PAD_TRSTB), + IMX_PINCTRL_PIN(MX35_PAD_DE_B), + IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE106), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE107), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE108), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE109), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE110), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE111), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE112), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE113), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE114), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE115), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE116), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE117), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE118), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE119), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE120), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE121), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE122), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE123), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE124), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE125), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE126), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE127), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE128), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE129), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE130), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE131), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE132), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE133), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE134), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE135), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE136), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE137), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE138), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE139), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE140), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE141), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE142), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE143), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE144), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE145), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE146), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE147), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE148), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE149), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE150), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE151), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE152), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE153), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE154), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE155), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE156), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE157), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE158), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE159), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE160), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE161), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE162), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE163), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE164), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE165), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE166), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE167), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE168), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE169), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE170), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE171), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE172), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE173), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE174), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE175), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE176), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE177), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE178), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE179), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE180), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE181), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE182), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE183), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE184), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE185), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE186), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE187), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE188), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE189), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE190), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE191), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE192), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE193), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE194), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE195), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE196), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE197), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE198), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE199), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE200), + IMX_PINCTRL_PIN(MX35_PAD_RESERVE201), IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK), IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE), }; @@ -1555,8 +1003,6 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { static struct imx_pinctrl_soc_info imx35_pinctrl_info = { .pins = imx35_pinctrl_pads, .npins = ARRAY_SIZE(imx35_pinctrl_pads), - .pin_regs = imx35_pin_regs, - .npin_regs = ARRAY_SIZE(imx35_pin_regs), }; static struct of_device_id imx35_pinctrl_of_match[] = { @@ -1573,7 +1019,7 @@ static struct platform_driver imx35_pinctrl_driver = { .driver = { .name = "imx35-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx35_pinctrl_of_match), + .of_match_table = imx35_pinctrl_of_match, }, .probe = imx35_pinctrl_probe, .remove = imx_pinctrl_remove, diff --git a/drivers/pinctrl/pinctrl-imx50.c b/drivers/pinctrl/pinctrl-imx50.c new file mode 100644 index 00000000000..b06feed1b03 --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx50.c @@ -0,0 +1,426 @@ +/* + * imx50 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org> + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum imx50_pads { + MX50_PAD_RESERVE0 = 0, + MX50_PAD_RESERVE1 = 1, + MX50_PAD_RESERVE2 = 2, + MX50_PAD_RESERVE3 = 3, + MX50_PAD_RESERVE4 = 4, + MX50_PAD_RESERVE5 = 5, + MX50_PAD_RESERVE6 = 6, + MX50_PAD_RESERVE7 = 7, + MX50_PAD_KEY_COL0 = 8, + MX50_PAD_KEY_ROW0 = 9, + MX50_PAD_KEY_COL1 = 10, + MX50_PAD_KEY_ROW1 = 11, + MX50_PAD_KEY_COL2 = 12, + MX50_PAD_KEY_ROW2 = 13, + MX50_PAD_KEY_COL3 = 14, + MX50_PAD_KEY_ROW3 = 15, + MX50_PAD_I2C1_SCL = 16, + MX50_PAD_I2C1_SDA = 17, + MX50_PAD_I2C2_SCL = 18, + MX50_PAD_I2C2_SDA = 19, + MX50_PAD_I2C3_SCL = 20, + MX50_PAD_I2C3_SDA = 21, + MX50_PAD_PWM1 = 22, + MX50_PAD_PWM2 = 23, + MX50_PAD_0WIRE = 24, + MX50_PAD_EPITO = 25, + MX50_PAD_WDOG = 26, + MX50_PAD_SSI_TXFS = 27, + MX50_PAD_SSI_TXC = 28, + MX50_PAD_SSI_TXD = 29, + MX50_PAD_SSI_RXD = 30, + MX50_PAD_SSI_RXF = 31, + MX50_PAD_SSI_RXC = 32, + MX50_PAD_UART1_TXD = 33, + MX50_PAD_UART1_RXD = 34, + MX50_PAD_UART1_CTS = 35, + MX50_PAD_UART1_RTS = 36, + MX50_PAD_UART2_TXD = 37, + MX50_PAD_UART2_RXD = 38, + MX50_PAD_UART2_CTS = 39, + MX50_PAD_UART2_RTS = 40, + MX50_PAD_UART3_TXD = 41, + MX50_PAD_UART3_RXD = 42, + MX50_PAD_UART4_TXD = 43, + MX50_PAD_UART4_RXD = 44, + MX50_PAD_CSPI_CLK = 45, + MX50_PAD_CSPI_MOSI = 46, + MX50_PAD_CSPI_MISO = 47, + MX50_PAD_CSPI_SS0 = 48, + MX50_PAD_ECSPI1_CLK = 49, + MX50_PAD_ECSPI1_MOSI = 50, + MX50_PAD_ECSPI1_MISO = 51, + MX50_PAD_ECSPI1_SS0 = 52, + MX50_PAD_ECSPI2_CLK = 53, + MX50_PAD_ECSPI2_MOSI = 54, + MX50_PAD_ECSPI2_MISO = 55, + MX50_PAD_ECSPI2_SS0 = 56, + MX50_PAD_SD1_CLK = 57, + MX50_PAD_SD1_CMD = 58, + MX50_PAD_SD1_D0 = 59, + MX50_PAD_SD1_D1 = 60, + MX50_PAD_SD1_D2 = 61, + MX50_PAD_SD1_D3 = 62, + MX50_PAD_SD2_CLK = 63, + MX50_PAD_SD2_CMD = 64, + MX50_PAD_SD2_D0 = 65, + MX50_PAD_SD2_D1 = 66, + MX50_PAD_SD2_D2 = 67, + MX50_PAD_SD2_D3 = 68, + MX50_PAD_SD2_D4 = 69, + MX50_PAD_SD2_D5 = 70, + MX50_PAD_SD2_D6 = 71, + MX50_PAD_SD2_D7 = 72, + MX50_PAD_SD2_WP = 73, + MX50_PAD_SD2_CD = 74, + MX50_PAD_DISP_D0 = 75, + MX50_PAD_DISP_D1 = 76, + MX50_PAD_DISP_D2 = 77, + MX50_PAD_DISP_D3 = 78, + MX50_PAD_DISP_D4 = 79, + MX50_PAD_DISP_D5 = 80, + MX50_PAD_DISP_D6 = 81, + MX50_PAD_DISP_D7 = 82, + MX50_PAD_DISP_WR = 83, + MX50_PAD_DISP_RD = 84, + MX50_PAD_DISP_RS = 85, + MX50_PAD_DISP_CS = 86, + MX50_PAD_DISP_BUSY = 87, + MX50_PAD_DISP_RESET = 88, + MX50_PAD_SD3_CLK = 89, + MX50_PAD_SD3_CMD = 90, + MX50_PAD_SD3_D0 = 91, + MX50_PAD_SD3_D1 = 92, + MX50_PAD_SD3_D2 = 93, + MX50_PAD_SD3_D3 = 94, + MX50_PAD_SD3_D4 = 95, + MX50_PAD_SD3_D5 = 96, + MX50_PAD_SD3_D6 = 97, + MX50_PAD_SD3_D7 = 98, + MX50_PAD_SD3_WP = 99, + MX50_PAD_DISP_D8 = 100, + MX50_PAD_DISP_D9 = 101, + MX50_PAD_DISP_D10 = 102, + MX50_PAD_DISP_D11 = 103, + MX50_PAD_DISP_D12 = 104, + MX50_PAD_DISP_D13 = 105, + MX50_PAD_DISP_D14 = 106, + MX50_PAD_DISP_D15 = 107, + MX50_PAD_EPDC_D0 = 108, + MX50_PAD_EPDC_D1 = 109, + MX50_PAD_EPDC_D2 = 110, + MX50_PAD_EPDC_D3 = 111, + MX50_PAD_EPDC_D4 = 112, + MX50_PAD_EPDC_D5 = 113, + MX50_PAD_EPDC_D6 = 114, + MX50_PAD_EPDC_D7 = 115, + MX50_PAD_EPDC_D8 = 116, + MX50_PAD_EPDC_D9 = 117, + MX50_PAD_EPDC_D10 = 118, + MX50_PAD_EPDC_D11 = 119, + MX50_PAD_EPDC_D12 = 120, + MX50_PAD_EPDC_D13 = 121, + MX50_PAD_EPDC_D14 = 122, + MX50_PAD_EPDC_D15 = 123, + MX50_PAD_EPDC_GDCLK = 124, + MX50_PAD_EPDC_GDSP = 125, + MX50_PAD_EPDC_GDOE = 126, + MX50_PAD_EPDC_GDRL = 127, + MX50_PAD_EPDC_SDCLK = 128, + MX50_PAD_EPDC_SDOEZ = 129, + MX50_PAD_EPDC_SDOED = 130, + MX50_PAD_EPDC_SDOE = 131, + MX50_PAD_EPDC_SDLE = 132, + MX50_PAD_EPDC_SDCLKN = 133, + MX50_PAD_EPDC_SDSHR = 134, + MX50_PAD_EPDC_PWRCOM = 135, + MX50_PAD_EPDC_PWRSTAT = 136, + MX50_PAD_EPDC_PWRCTRL0 = 137, + MX50_PAD_EPDC_PWRCTRL1 = 138, + MX50_PAD_EPDC_PWRCTRL2 = 139, + MX50_PAD_EPDC_PWRCTRL3 = 140, + MX50_PAD_EPDC_VCOM0 = 141, + MX50_PAD_EPDC_VCOM1 = 142, + MX50_PAD_EPDC_BDR0 = 143, + MX50_PAD_EPDC_BDR1 = 144, + MX50_PAD_EPDC_SDCE0 = 145, + MX50_PAD_EPDC_SDCE1 = 146, + MX50_PAD_EPDC_SDCE2 = 147, + MX50_PAD_EPDC_SDCE3 = 148, + MX50_PAD_EPDC_SDCE4 = 149, + MX50_PAD_EPDC_SDCE5 = 150, + MX50_PAD_EIM_DA0 = 151, + MX50_PAD_EIM_DA1 = 152, + MX50_PAD_EIM_DA2 = 153, + MX50_PAD_EIM_DA3 = 154, + MX50_PAD_EIM_DA4 = 155, + MX50_PAD_EIM_DA5 = 156, + MX50_PAD_EIM_DA6 = 157, + MX50_PAD_EIM_DA7 = 158, + MX50_PAD_EIM_DA8 = 159, + MX50_PAD_EIM_DA9 = 160, + MX50_PAD_EIM_DA10 = 161, + MX50_PAD_EIM_DA11 = 162, + MX50_PAD_EIM_DA12 = 163, + MX50_PAD_EIM_DA13 = 164, + MX50_PAD_EIM_DA14 = 165, + MX50_PAD_EIM_DA15 = 166, + MX50_PAD_EIM_CS2 = 167, + MX50_PAD_EIM_CS1 = 168, + MX50_PAD_EIM_CS0 = 169, + MX50_PAD_EIM_EB0 = 170, + MX50_PAD_EIM_EB1 = 171, + MX50_PAD_EIM_WAIT = 172, + MX50_PAD_EIM_BCLK = 173, + MX50_PAD_EIM_RDY = 174, + MX50_PAD_EIM_OE = 175, + MX50_PAD_EIM_RW = 176, + MX50_PAD_EIM_LBA = 177, + MX50_PAD_EIM_CRE = 178, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX50_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX50_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL), + IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA), + IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL), + IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA), + IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL), + IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA), + IMX_PINCTRL_PIN(MX50_PAD_PWM1), + IMX_PINCTRL_PIN(MX50_PAD_PWM2), + IMX_PINCTRL_PIN(MX50_PAD_0WIRE), + IMX_PINCTRL_PIN(MX50_PAD_EPITO), + IMX_PINCTRL_PIN(MX50_PAD_WDOG), + IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS), + IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC), + IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD), + IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD), + IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF), + IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC), + IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD), + IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD), + IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD), + IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD), + IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK), + IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI), + IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO), + IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO), + IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0), + IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX50_PAD_SD1_D0), + IMX_PINCTRL_PIN(MX50_PAD_SD1_D1), + IMX_PINCTRL_PIN(MX50_PAD_SD1_D2), + IMX_PINCTRL_PIN(MX50_PAD_SD1_D3), + IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D0), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D1), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D2), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D3), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D4), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D5), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D6), + IMX_PINCTRL_PIN(MX50_PAD_SD2_D7), + IMX_PINCTRL_PIN(MX50_PAD_SD2_WP), + IMX_PINCTRL_PIN(MX50_PAD_SD2_CD), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D0), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D1), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D2), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D3), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D4), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D5), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D6), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D7), + IMX_PINCTRL_PIN(MX50_PAD_DISP_WR), + IMX_PINCTRL_PIN(MX50_PAD_DISP_RD), + IMX_PINCTRL_PIN(MX50_PAD_DISP_RS), + IMX_PINCTRL_PIN(MX50_PAD_DISP_CS), + IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY), + IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET), + IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D0), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D1), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D2), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D3), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D4), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D5), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D6), + IMX_PINCTRL_PIN(MX50_PAD_SD3_D7), + IMX_PINCTRL_PIN(MX50_PAD_SD3_WP), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D8), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D9), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D10), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D11), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D12), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D13), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D14), + IMX_PINCTRL_PIN(MX50_PAD_DISP_D15), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4), + IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14), + IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15), + IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2), + IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1), + IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0), + IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0), + IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1), + IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT), + IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK), + IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY), + IMX_PINCTRL_PIN(MX50_PAD_EIM_OE), + IMX_PINCTRL_PIN(MX50_PAD_EIM_RW), + IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA), + IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE), +}; + +static struct imx_pinctrl_soc_info imx50_pinctrl_info = { + .pins = imx50_pinctrl_pads, + .npins = ARRAY_SIZE(imx50_pinctrl_pads), +}; + +static struct of_device_id imx50_pinctrl_of_match[] = { + { .compatible = "fsl,imx50-iomuxc", }, + { /* sentinel */ } +}; + +static int imx50_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx50_pinctrl_info); +} + +static struct platform_driver imx50_pinctrl_driver = { + .driver = { + .name = "imx50-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx50_pinctrl_of_match), + }, + .probe = imx50_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx50_pinctrl_init(void) +{ + return platform_driver_register(&imx50_pinctrl_driver); +} +arch_initcall(imx50_pinctrl_init); + +static void __exit imx50_pinctrl_exit(void) +{ + platform_driver_unregister(&imx50_pinctrl_driver); +} +module_exit(imx50_pinctrl_exit); +MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c index 9a92aaad150..19ab182bef6 100644 --- a/drivers/pinctrl/pinctrl-imx51.c +++ b/drivers/pinctrl/pinctrl-imx51.c @@ -23,1015 +23,400 @@ #include "pinctrl-imx.h" enum imx51_pads { - MX51_PAD_EIM_D16 = 0, - MX51_PAD_EIM_D17 = 1, - MX51_PAD_EIM_D18 = 2, - MX51_PAD_EIM_D19 = 3, - MX51_PAD_EIM_D20 = 4, - MX51_PAD_EIM_D21 = 5, - MX51_PAD_EIM_D22 = 6, - MX51_PAD_EIM_D23 = 7, - MX51_PAD_EIM_D24 = 8, - MX51_PAD_EIM_D25 = 9, - MX51_PAD_EIM_D26 = 10, - MX51_PAD_EIM_D27 = 11, - MX51_PAD_EIM_D28 = 12, - MX51_PAD_EIM_D29 = 13, - MX51_PAD_EIM_D30 = 14, - MX51_PAD_EIM_D31 = 15, - MX51_PAD_EIM_A16 = 16, - MX51_PAD_EIM_A17 = 17, - MX51_PAD_EIM_A18 = 18, - MX51_PAD_EIM_A19 = 19, - MX51_PAD_EIM_A20 = 20, - MX51_PAD_EIM_A21 = 21, - MX51_PAD_EIM_A22 = 22, - MX51_PAD_EIM_A23 = 23, - MX51_PAD_EIM_A24 = 24, - MX51_PAD_EIM_A25 = 25, - MX51_PAD_EIM_A26 = 26, - MX51_PAD_EIM_A27 = 27, - MX51_PAD_EIM_EB0 = 28, - MX51_PAD_EIM_EB1 = 29, - MX51_PAD_EIM_EB2 = 30, - MX51_PAD_EIM_EB3 = 31, - MX51_PAD_EIM_OE = 32, - MX51_PAD_EIM_CS0 = 33, - MX51_PAD_EIM_CS1 = 34, - MX51_PAD_EIM_CS2 = 35, - MX51_PAD_EIM_CS3 = 36, - MX51_PAD_EIM_CS4 = 37, - MX51_PAD_EIM_CS5 = 38, - MX51_PAD_EIM_DTACK = 39, - MX51_PAD_EIM_LBA = 40, - MX51_PAD_EIM_CRE = 41, - MX51_PAD_DRAM_CS1 = 42, - MX51_PAD_NANDF_WE_B = 43, - MX51_PAD_NANDF_RE_B = 44, - MX51_PAD_NANDF_ALE = 45, - MX51_PAD_NANDF_CLE = 46, - MX51_PAD_NANDF_WP_B = 47, - MX51_PAD_NANDF_RB0 = 48, - MX51_PAD_NANDF_RB1 = 49, - MX51_PAD_NANDF_RB2 = 50, - MX51_PAD_NANDF_RB3 = 51, - MX51_PAD_GPIO_NAND = 52, - MX51_PAD_NANDF_CS0 = 53, - MX51_PAD_NANDF_CS1 = 54, - MX51_PAD_NANDF_CS2 = 55, - MX51_PAD_NANDF_CS3 = 56, - MX51_PAD_NANDF_CS4 = 57, - MX51_PAD_NANDF_CS5 = 58, - MX51_PAD_NANDF_CS6 = 59, - MX51_PAD_NANDF_CS7 = 60, - MX51_PAD_NANDF_RDY_INT = 61, - MX51_PAD_NANDF_D15 = 62, - MX51_PAD_NANDF_D14 = 63, - MX51_PAD_NANDF_D13 = 64, - MX51_PAD_NANDF_D12 = 65, - MX51_PAD_NANDF_D11 = 66, - MX51_PAD_NANDF_D10 = 67, - MX51_PAD_NANDF_D9 = 68, - MX51_PAD_NANDF_D8 = 69, - MX51_PAD_NANDF_D7 = 70, - MX51_PAD_NANDF_D6 = 71, - MX51_PAD_NANDF_D5 = 72, - MX51_PAD_NANDF_D4 = 73, - MX51_PAD_NANDF_D3 = 74, - MX51_PAD_NANDF_D2 = 75, - MX51_PAD_NANDF_D1 = 76, - MX51_PAD_NANDF_D0 = 77, - MX51_PAD_CSI1_D8 = 78, - MX51_PAD_CSI1_D9 = 79, - MX51_PAD_CSI1_D10 = 80, - MX51_PAD_CSI1_D11 = 81, - MX51_PAD_CSI1_D12 = 82, - MX51_PAD_CSI1_D13 = 83, - MX51_PAD_CSI1_D14 = 84, - MX51_PAD_CSI1_D15 = 85, - MX51_PAD_CSI1_D16 = 86, - MX51_PAD_CSI1_D17 = 87, - MX51_PAD_CSI1_D18 = 88, - MX51_PAD_CSI1_D19 = 89, - MX51_PAD_CSI1_VSYNC = 90, - MX51_PAD_CSI1_HSYNC = 91, - MX51_PAD_CSI1_PIXCLK = 92, - MX51_PAD_CSI1_MCLK = 93, - MX51_PAD_CSI2_D12 = 94, - MX51_PAD_CSI2_D13 = 95, - MX51_PAD_CSI2_D14 = 96, - MX51_PAD_CSI2_D15 = 97, - MX51_PAD_CSI2_D16 = 98, - MX51_PAD_CSI2_D17 = 99, - MX51_PAD_CSI2_D18 = 100, - MX51_PAD_CSI2_D19 = 101, - MX51_PAD_CSI2_VSYNC = 102, - MX51_PAD_CSI2_HSYNC = 103, - MX51_PAD_CSI2_PIXCLK = 104, - MX51_PAD_I2C1_CLK = 105, - MX51_PAD_I2C1_DAT = 106, - MX51_PAD_AUD3_BB_TXD = 107, - MX51_PAD_AUD3_BB_RXD = 108, - MX51_PAD_AUD3_BB_CK = 109, - MX51_PAD_AUD3_BB_FS = 110, - MX51_PAD_CSPI1_MOSI = 111, - MX51_PAD_CSPI1_MISO = 112, - MX51_PAD_CSPI1_SS0 = 113, - MX51_PAD_CSPI1_SS1 = 114, - MX51_PAD_CSPI1_RDY = 115, - MX51_PAD_CSPI1_SCLK = 116, - MX51_PAD_UART1_RXD = 117, - MX51_PAD_UART1_TXD = 118, - MX51_PAD_UART1_RTS = 119, - MX51_PAD_UART1_CTS = 120, - MX51_PAD_UART2_RXD = 121, - MX51_PAD_UART2_TXD = 122, - MX51_PAD_UART3_RXD = 123, - MX51_PAD_UART3_TXD = 124, - MX51_PAD_OWIRE_LINE = 125, - MX51_PAD_KEY_ROW0 = 126, - MX51_PAD_KEY_ROW1 = 127, - MX51_PAD_KEY_ROW2 = 128, - MX51_PAD_KEY_ROW3 = 129, - MX51_PAD_KEY_COL0 = 130, - MX51_PAD_KEY_COL1 = 131, - MX51_PAD_KEY_COL2 = 132, - MX51_PAD_KEY_COL3 = 133, - MX51_PAD_KEY_COL4 = 134, - MX51_PAD_KEY_COL5 = 135, - MX51_PAD_USBH1_CLK = 136, - MX51_PAD_USBH1_DIR = 137, - MX51_PAD_USBH1_STP = 138, - MX51_PAD_USBH1_NXT = 139, - MX51_PAD_USBH1_DATA0 = 140, - MX51_PAD_USBH1_DATA1 = 141, - MX51_PAD_USBH1_DATA2 = 142, - MX51_PAD_USBH1_DATA3 = 143, - MX51_PAD_USBH1_DATA4 = 144, - MX51_PAD_USBH1_DATA5 = 145, - MX51_PAD_USBH1_DATA6 = 146, - MX51_PAD_USBH1_DATA7 = 147, - MX51_PAD_DI1_PIN11 = 148, - MX51_PAD_DI1_PIN12 = 149, - MX51_PAD_DI1_PIN13 = 150, - MX51_PAD_DI1_D0_CS = 151, - MX51_PAD_DI1_D1_CS = 152, - MX51_PAD_DISPB2_SER_DIN = 153, - MX51_PAD_DISPB2_SER_DIO = 154, - MX51_PAD_DISPB2_SER_CLK = 155, - MX51_PAD_DISPB2_SER_RS = 156, - MX51_PAD_DISP1_DAT0 = 157, - MX51_PAD_DISP1_DAT1 = 158, - MX51_PAD_DISP1_DAT2 = 159, - MX51_PAD_DISP1_DAT3 = 160, - MX51_PAD_DISP1_DAT4 = 161, - MX51_PAD_DISP1_DAT5 = 162, - MX51_PAD_DISP1_DAT6 = 163, - MX51_PAD_DISP1_DAT7 = 164, - MX51_PAD_DISP1_DAT8 = 165, - MX51_PAD_DISP1_DAT9 = 166, - MX51_PAD_DISP1_DAT10 = 167, - MX51_PAD_DISP1_DAT11 = 168, - MX51_PAD_DISP1_DAT12 = 169, - MX51_PAD_DISP1_DAT13 = 170, - MX51_PAD_DISP1_DAT14 = 171, - MX51_PAD_DISP1_DAT15 = 172, - MX51_PAD_DISP1_DAT16 = 173, - MX51_PAD_DISP1_DAT17 = 174, - MX51_PAD_DISP1_DAT18 = 175, - MX51_PAD_DISP1_DAT19 = 176, - MX51_PAD_DISP1_DAT20 = 177, - MX51_PAD_DISP1_DAT21 = 178, - MX51_PAD_DISP1_DAT22 = 179, - MX51_PAD_DISP1_DAT23 = 180, - MX51_PAD_DI1_PIN3 = 181, - MX51_PAD_DI1_PIN2 = 182, - MX51_PAD_DI_GP2 = 183, - MX51_PAD_DI_GP3 = 184, - MX51_PAD_DI2_PIN4 = 185, - MX51_PAD_DI2_PIN2 = 186, - MX51_PAD_DI2_PIN3 = 187, - MX51_PAD_DI2_DISP_CLK = 188, - MX51_PAD_DI_GP4 = 189, - MX51_PAD_DISP2_DAT0 = 190, - MX51_PAD_DISP2_DAT1 = 191, - MX51_PAD_DISP2_DAT2 = 192, - MX51_PAD_DISP2_DAT3 = 193, - MX51_PAD_DISP2_DAT4 = 194, - MX51_PAD_DISP2_DAT5 = 195, - MX51_PAD_DISP2_DAT6 = 196, - MX51_PAD_DISP2_DAT7 = 197, - MX51_PAD_DISP2_DAT8 = 198, - MX51_PAD_DISP2_DAT9 = 199, - MX51_PAD_DISP2_DAT10 = 200, - MX51_PAD_DISP2_DAT11 = 201, - MX51_PAD_DISP2_DAT12 = 202, - MX51_PAD_DISP2_DAT13 = 203, - MX51_PAD_DISP2_DAT14 = 204, - MX51_PAD_DISP2_DAT15 = 205, - MX51_PAD_SD1_CMD = 206, - MX51_PAD_SD1_CLK = 207, - MX51_PAD_SD1_DATA0 = 208, - MX51_PAD_EIM_DA0 = 209, - MX51_PAD_EIM_DA1 = 210, - MX51_PAD_EIM_DA2 = 211, - MX51_PAD_EIM_DA3 = 212, - MX51_PAD_SD1_DATA1 = 213, - MX51_PAD_EIM_DA4 = 214, - MX51_PAD_EIM_DA5 = 215, - MX51_PAD_EIM_DA6 = 216, - MX51_PAD_EIM_DA7 = 217, - MX51_PAD_SD1_DATA2 = 218, - MX51_PAD_EIM_DA10 = 219, - MX51_PAD_EIM_DA11 = 220, - MX51_PAD_EIM_DA8 = 221, - MX51_PAD_EIM_DA9 = 222, - MX51_PAD_SD1_DATA3 = 223, - MX51_PAD_GPIO1_0 = 224, - MX51_PAD_GPIO1_1 = 225, - MX51_PAD_EIM_DA12 = 226, - MX51_PAD_EIM_DA13 = 227, - MX51_PAD_EIM_DA14 = 228, - MX51_PAD_EIM_DA15 = 229, - MX51_PAD_SD2_CMD = 230, - MX51_PAD_SD2_CLK = 231, - MX51_PAD_SD2_DATA0 = 232, - MX51_PAD_SD2_DATA1 = 233, - MX51_PAD_SD2_DATA2 = 234, - MX51_PAD_SD2_DATA3 = 235, - MX51_PAD_GPIO1_2 = 236, - MX51_PAD_GPIO1_3 = 237, - MX51_PAD_PMIC_INT_REQ = 238, - MX51_PAD_GPIO1_4 = 239, - MX51_PAD_GPIO1_5 = 240, - MX51_PAD_GPIO1_6 = 241, - MX51_PAD_GPIO1_7 = 242, - MX51_PAD_GPIO1_8 = 243, - MX51_PAD_GPIO1_9 = 244, -}; - -/* imx51 register maps */ -static struct imx_pin_reg imx51_pin_regs[] = { - IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /* MX51_PAD_EIM_D16__AUD4_RXFS */ - IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 7, 0x8d8, 0), /* MX51_PAD_EIM_D16__AUD5_TXD */ - IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 0, 0x000, 0), /* MX51_PAD_EIM_D16__EIM_D16 */ - IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 1, 0x000, 0), /* MX51_PAD_EIM_D16__GPIO2_0 */ - IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 4, 0x9b4, 0), /* MX51_PAD_EIM_D16__I2C1_SDA */ - IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 3, 0x000, 0), /* MX51_PAD_EIM_D16__UART2_CTS */ - IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 2, 0x000, 0), /* MX51_PAD_EIM_D16__USBH2_DATA0 */ - IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 7, 0x8d4, 0), /* MX51_PAD_EIM_D17__AUD5_RXD */ - IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 0, 0x000, 0), /* MX51_PAD_EIM_D17__EIM_D17 */ - IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 1, 0x000, 0), /* MX51_PAD_EIM_D17__GPIO2_1 */ - IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 3, 0x9ec, 0), /* MX51_PAD_EIM_D17__UART2_RXD */ - IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 4, 0x000, 0), /* MX51_PAD_EIM_D17__UART3_CTS */ - IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 2, 0x000, 0), /* MX51_PAD_EIM_D17__USBH2_DATA1 */ - IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 7, 0x8e4, 0), /* MX51_PAD_EIM_D18__AUD5_TXC */ - IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 0, 0x000, 0), /* MX51_PAD_EIM_D18__EIM_D18 */ - IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 1, 0x000, 0), /* MX51_PAD_EIM_D18__GPIO2_2 */ - IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 3, 0x000, 0), /* MX51_PAD_EIM_D18__UART2_TXD */ - IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 4, 0x9f0, 1), /* MX51_PAD_EIM_D18__UART3_RTS */ - IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 2, 0x000, 0), /* MX51_PAD_EIM_D18__USBH2_DATA2 */ - IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 5, 0x000, 0), /* MX51_PAD_EIM_D19__AUD4_RXC */ - IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 7, 0x8e8, 0), /* MX51_PAD_EIM_D19__AUD5_TXFS */ - IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 0, 0x000, 0), /* MX51_PAD_EIM_D19__EIM_D19 */ - IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 1, 0x000, 0), /* MX51_PAD_EIM_D19__GPIO2_3 */ - IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 4, 0x9b0, 0), /* MX51_PAD_EIM_D19__I2C1_SCL */ - IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 3, 0x9e8, 1), /* MX51_PAD_EIM_D19__UART2_RTS */ - IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 2, 0x000, 0), /* MX51_PAD_EIM_D19__USBH2_DATA3 */ - IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 5, 0x8c8, 0), /* MX51_PAD_EIM_D20__AUD4_TXD */ - IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 0, 0x000, 0), /* MX51_PAD_EIM_D20__EIM_D20 */ - IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 1, 0x000, 0), /* MX51_PAD_EIM_D20__GPIO2_4 */ - IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 4, 0x000, 0), /* MX51_PAD_EIM_D20__SRTC_ALARM_DEB */ - IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 2, 0x000, 0), /* MX51_PAD_EIM_D20__USBH2_DATA4 */ - IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 5, 0x8c4, 0), /* MX51_PAD_EIM_D21__AUD4_RXD */ - IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 0, 0x000, 0), /* MX51_PAD_EIM_D21__EIM_D21 */ - IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 1, 0x000, 0), /* MX51_PAD_EIM_D21__GPIO2_5 */ - IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 3, 0x000, 0), /* MX51_PAD_EIM_D21__SRTC_ALARM_DEB */ - IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 2, 0x000, 0), /* MX51_PAD_EIM_D21__USBH2_DATA5 */ - IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 5, 0x8cc, 0), /* MX51_PAD_EIM_D22__AUD4_TXC */ - IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 0, 0x000, 0), /* MX51_PAD_EIM_D22__EIM_D22 */ - IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 1, 0x000, 0), /* MX51_PAD_EIM_D22__GPIO2_6 */ - IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 2, 0x000, 0), /* MX51_PAD_EIM_D22__USBH2_DATA6 */ - IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 5, 0x8d0, 0), /* MX51_PAD_EIM_D23__AUD4_TXFS */ - IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 0, 0x000, 0), /* MX51_PAD_EIM_D23__EIM_D23 */ - IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 1, 0x000, 0), /* MX51_PAD_EIM_D23__GPIO2_7 */ - IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 4, 0x000, 0), /* MX51_PAD_EIM_D23__SPDIF_OUT1 */ - IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 2, 0x000, 0), /* MX51_PAD_EIM_D23__USBH2_DATA7 */ - IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 5, 0x8f8, 0), /* MX51_PAD_EIM_D24__AUD6_RXFS */ - IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 0, 0x000, 0), /* MX51_PAD_EIM_D24__EIM_D24 */ - IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 1, 0x000, 0), /* MX51_PAD_EIM_D24__GPIO2_8 */ - IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 4, 0x9bc, 0), /* MX51_PAD_EIM_D24__I2C2_SDA */ - IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 3, 0x000, 0), /* MX51_PAD_EIM_D24__UART3_CTS */ - IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 2, 0x000, 0), /* MX51_PAD_EIM_D24__USBOTG_DATA0 */ - IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 0, 0x000, 0), /* MX51_PAD_EIM_D25__EIM_D25 */ - IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 1, 0x9c8, 0), /* MX51_PAD_EIM_D25__KEY_COL6 */ - IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 4, 0x000, 0), /* MX51_PAD_EIM_D25__UART2_CTS */ - IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 3, 0x9f4, 0), /* MX51_PAD_EIM_D25__UART3_RXD */ - IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 2, 0x000, 0), /* MX51_PAD_EIM_D25__USBOTG_DATA1 */ - IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 0, 0x000, 0), /* MX51_PAD_EIM_D26__EIM_D26 */ - IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 1, 0x9cc, 0), /* MX51_PAD_EIM_D26__KEY_COL7 */ - IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 4, 0x9e8, 3), /* MX51_PAD_EIM_D26__UART2_RTS */ - IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 3, 0x000, 0), /* MX51_PAD_EIM_D26__UART3_TXD */ - IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 2, 0x000, 0), /* MX51_PAD_EIM_D26__USBOTG_DATA2 */ - IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 5, 0x8f4, 0), /* MX51_PAD_EIM_D27__AUD6_RXC */ - IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 0, 0x000, 0), /* MX51_PAD_EIM_D27__EIM_D27 */ - IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 1, 0x000, 0), /* MX51_PAD_EIM_D27__GPIO2_9 */ - IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 4, 0x9b8, 0), /* MX51_PAD_EIM_D27__I2C2_SCL */ - IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 3, 0x9f0, 3), /* MX51_PAD_EIM_D27__UART3_RTS */ - IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 2, 0x000, 0), /* MX51_PAD_EIM_D27__USBOTG_DATA3 */ - IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 5, 0x8f0, 0), /* MX51_PAD_EIM_D28__AUD6_TXD */ - IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 0, 0x000, 0), /* MX51_PAD_EIM_D28__EIM_D28 */ - IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 1, 0x9d0, 0), /* MX51_PAD_EIM_D28__KEY_ROW4 */ - IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 2, 0x000, 0), /* MX51_PAD_EIM_D28__USBOTG_DATA4 */ - IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 5, 0x8ec, 0), /* MX51_PAD_EIM_D29__AUD6_RXD */ - IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 0, 0x000, 0), /* MX51_PAD_EIM_D29__EIM_D29 */ - IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 1, 0x9d4, 0), /* MX51_PAD_EIM_D29__KEY_ROW5 */ - IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 2, 0x000, 0), /* MX51_PAD_EIM_D29__USBOTG_DATA5 */ - IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 5, 0x8fc, 0), /* MX51_PAD_EIM_D30__AUD6_TXC */ - IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 0, 0x000, 0), /* MX51_PAD_EIM_D30__EIM_D30 */ - IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 1, 0x9d8, 0), /* MX51_PAD_EIM_D30__KEY_ROW6 */ - IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 2, 0x000, 0), /* MX51_PAD_EIM_D30__USBOTG_DATA6 */ - IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 5, 0x900, 0), /* MX51_PAD_EIM_D31__AUD6_TXFS */ - IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 0, 0x000, 0), /* MX51_PAD_EIM_D31__EIM_D31 */ - IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 1, 0x9dc, 0), /* MX51_PAD_EIM_D31__KEY_ROW7 */ - IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 2, 0x000, 0), /* MX51_PAD_EIM_D31__USBOTG_DATA7 */ - IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 0, 0x000, 0), /* MX51_PAD_EIM_A16__EIM_A16 */ - IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 1, 0x000, 0), /* MX51_PAD_EIM_A16__GPIO2_10 */ - IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 7, 0x000, 0), /* MX51_PAD_EIM_A16__OSC_FREQ_SEL0 */ - IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 0, 0x000, 0), /* MX51_PAD_EIM_A17__EIM_A17 */ - IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 1, 0x000, 0), /* MX51_PAD_EIM_A17__GPIO2_11 */ - IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 7, 0x000, 0), /* MX51_PAD_EIM_A17__OSC_FREQ_SEL1 */ - IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 7, 0x000, 0), /* MX51_PAD_EIM_A18__BOOT_LPB0 */ - IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 0, 0x000, 0), /* MX51_PAD_EIM_A18__EIM_A18 */ - IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 1, 0x000, 0), /* MX51_PAD_EIM_A18__GPIO2_12 */ - IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 7, 0x000, 0), /* MX51_PAD_EIM_A19__BOOT_LPB1 */ - IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 0, 0x000, 0), /* MX51_PAD_EIM_A19__EIM_A19 */ - IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 1, 0x000, 0), /* MX51_PAD_EIM_A19__GPIO2_13 */ - IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 7, 0x000, 0), /* MX51_PAD_EIM_A20__BOOT_UART_SRC0 */ - IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 0, 0x000, 0), /* MX51_PAD_EIM_A20__EIM_A20 */ - IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 1, 0x000, 0), /* MX51_PAD_EIM_A20__GPIO2_14 */ - IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 7, 0x000, 0), /* MX51_PAD_EIM_A21__BOOT_UART_SRC1 */ - IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 0, 0x000, 0), /* MX51_PAD_EIM_A21__EIM_A21 */ - IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 1, 0x000, 0), /* MX51_PAD_EIM_A21__GPIO2_15 */ - IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 0, 0x000, 0), /* MX51_PAD_EIM_A22__EIM_A22 */ - IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 1, 0x000, 0), /* MX51_PAD_EIM_A22__GPIO2_16 */ - IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 7, 0x000, 0), /* MX51_PAD_EIM_A23__BOOT_HPN_EN */ - IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 0, 0x000, 0), /* MX51_PAD_EIM_A23__EIM_A23 */ - IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 1, 0x000, 0), /* MX51_PAD_EIM_A23__GPIO2_17 */ - IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 0, 0x000, 0), /* MX51_PAD_EIM_A24__EIM_A24 */ - IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 1, 0x000, 0), /* MX51_PAD_EIM_A24__GPIO2_18 */ - IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 2, 0x000, 0), /* MX51_PAD_EIM_A24__USBH2_CLK */ - IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 6, 0x000, 0), /* MX51_PAD_EIM_A25__DISP1_PIN4 */ - IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 0, 0x000, 0), /* MX51_PAD_EIM_A25__EIM_A25 */ - IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 1, 0x000, 0), /* MX51_PAD_EIM_A25__GPIO2_19 */ - IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 2, 0x000, 0), /* MX51_PAD_EIM_A25__USBH2_DIR */ - IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 5, 0x9a0, 0), /* MX51_PAD_EIM_A26__CSI1_DATA_EN */ - IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 6, 0x908, 0), /* MX51_PAD_EIM_A26__DISP2_EXT_CLK */ - IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 0, 0x000, 0), /* MX51_PAD_EIM_A26__EIM_A26 */ - IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 1, 0x000, 0), /* MX51_PAD_EIM_A26__GPIO2_20 */ - IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 2, 0x000, 0), /* MX51_PAD_EIM_A26__USBH2_STP */ - IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 5, 0x99c, 0), /* MX51_PAD_EIM_A27__CSI2_DATA_EN */ - IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 6, 0x9a4, 0), /* MX51_PAD_EIM_A27__DISP1_PIN1 */ - IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 0, 0x000, 0), /* MX51_PAD_EIM_A27__EIM_A27 */ - IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 1, 0x000, 0), /* MX51_PAD_EIM_A27__GPIO2_21 */ - IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 2, 0x000, 0), /* MX51_PAD_EIM_A27__USBH2_NXT */ - IMX_PIN_REG(MX51_PAD_EIM_EB0, 0x460, 0x0cc, 0, 0x000, 0), /* MX51_PAD_EIM_EB0__EIM_EB0 */ - IMX_PIN_REG(MX51_PAD_EIM_EB1, 0x464, 0x0d0, 0, 0x000, 0), /* MX51_PAD_EIM_EB1__EIM_EB1 */ - IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 6, 0x8e0, 0), /* MX51_PAD_EIM_EB2__AUD5_RXFS */ - IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 5, 0x000, 0), /* MX51_PAD_EIM_EB2__CSI1_D2 */ - IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 0, 0x000, 0), /* MX51_PAD_EIM_EB2__EIM_EB2 */ - IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 3, 0x954, 0), /* MX51_PAD_EIM_EB2__FEC_MDIO */ - IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 1, 0x000, 0), /* MX51_PAD_EIM_EB2__GPIO2_22 */ - IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 7, 0x000, 0), /* MX51_PAD_EIM_EB2__GPT_CMPOUT1 */ - IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 6, 0x8dc, 0), /* MX51_PAD_EIM_EB3__AUD5_RXC */ - IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 5, 0x000, 0), /* MX51_PAD_EIM_EB3__CSI1_D3 */ - IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 0, 0x000, 0), /* MX51_PAD_EIM_EB3__EIM_EB3 */ - IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 3, 0x95c, 0), /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ - IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 1, 0x000, 0), /* MX51_PAD_EIM_EB3__GPIO2_23 */ - IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 7, 0x000, 0), /* MX51_PAD_EIM_EB3__GPT_CMPOUT2 */ - IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 0, 0x000, 0), /* MX51_PAD_EIM_OE__EIM_OE */ - IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 1, 0x000, 0), /* MX51_PAD_EIM_OE__GPIO2_24 */ - IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 0, 0x000, 0), /* MX51_PAD_EIM_CS0__EIM_CS0 */ - IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 1, 0x000, 0), /* MX51_PAD_EIM_CS0__GPIO2_25 */ - IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 0, 0x000, 0), /* MX51_PAD_EIM_CS1__EIM_CS1 */ - IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 1, 0x000, 0), /* MX51_PAD_EIM_CS1__GPIO2_26 */ - IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 6, 0x8d8, 1), /* MX51_PAD_EIM_CS2__AUD5_TXD */ - IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 5, 0x000, 0), /* MX51_PAD_EIM_CS2__CSI1_D4 */ - IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 0, 0x000, 0), /* MX51_PAD_EIM_CS2__EIM_CS2 */ - IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 3, 0x960, 0), /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ - IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 1, 0x000, 0), /* MX51_PAD_EIM_CS2__GPIO2_27 */ - IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 2, 0x000, 0), /* MX51_PAD_EIM_CS2__USBOTG_STP */ - IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 6, 0x8d4, 1), /* MX51_PAD_EIM_CS3__AUD5_RXD */ - IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 5, 0x000, 0), /* MX51_PAD_EIM_CS3__CSI1_D5 */ - IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 0, 0x000, 0), /* MX51_PAD_EIM_CS3__EIM_CS3 */ - IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 3, 0x964, 0), /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ - IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 1, 0x000, 0), /* MX51_PAD_EIM_CS3__GPIO2_28 */ - IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 2, 0x000, 0), /* MX51_PAD_EIM_CS3__USBOTG_NXT */ - IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 6, 0x8e4, 1), /* MX51_PAD_EIM_CS4__AUD5_TXC */ - IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 5, 0x000, 0), /* MX51_PAD_EIM_CS4__CSI1_D6 */ - IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 0, 0x000, 0), /* MX51_PAD_EIM_CS4__EIM_CS4 */ - IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 3, 0x970, 0), /* MX51_PAD_EIM_CS4__FEC_RX_ER */ - IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 1, 0x000, 0), /* MX51_PAD_EIM_CS4__GPIO2_29 */ - IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 2, 0x000, 0), /* MX51_PAD_EIM_CS4__USBOTG_CLK */ - IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 6, 0x8e8, 1), /* MX51_PAD_EIM_CS5__AUD5_TXFS */ - IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 5, 0x000, 0), /* MX51_PAD_EIM_CS5__CSI1_D7 */ - IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 4, 0x904, 0), /* MX51_PAD_EIM_CS5__DISP1_EXT_CLK */ - IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 0, 0x000, 0), /* MX51_PAD_EIM_CS5__EIM_CS5 */ - IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 3, 0x950, 0), /* MX51_PAD_EIM_CS5__FEC_CRS */ - IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 1, 0x000, 0), /* MX51_PAD_EIM_CS5__GPIO2_30 */ - IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 2, 0x000, 0), /* MX51_PAD_EIM_CS5__USBOTG_DIR */ - IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 0, 0x000, 0), /* MX51_PAD_EIM_DTACK__EIM_DTACK */ - IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 1, 0x000, 0), /* MX51_PAD_EIM_DTACK__GPIO2_31 */ - IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 0, 0x000, 0), /* MX51_PAD_EIM_LBA__EIM_LBA */ - IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 1, 0x978, 0), /* MX51_PAD_EIM_LBA__GPIO3_1 */ - IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 0, 0x000, 0), /* MX51_PAD_EIM_CRE__EIM_CRE */ - IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 1, 0x97c, 0), /* MX51_PAD_EIM_CRE__GPIO3_2 */ - IMX_PIN_REG(MX51_PAD_DRAM_CS1, 0x4d0, 0x104, 0, 0x000, 0), /* MX51_PAD_DRAM_CS1__DRAM_CS1 */ - IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 3, 0x980, 0), /* MX51_PAD_NANDF_WE_B__GPIO3_3 */ - IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 0, 0x000, 0), /* MX51_PAD_NANDF_WE_B__NANDF_WE_B */ - IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 1, 0x000, 0), /* MX51_PAD_NANDF_WE_B__PATA_DIOW */ - IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 2, 0x93c, 0), /* MX51_PAD_NANDF_WE_B__SD3_DATA0 */ - IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 3, 0x984, 0), /* MX51_PAD_NANDF_RE_B__GPIO3_4 */ - IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 0, 0x000, 0), /* MX51_PAD_NANDF_RE_B__NANDF_RE_B */ - IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 1, 0x000, 0), /* MX51_PAD_NANDF_RE_B__PATA_DIOR */ - IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 2, 0x940, 0), /* MX51_PAD_NANDF_RE_B__SD3_DATA1 */ - IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 3, 0x988, 0), /* MX51_PAD_NANDF_ALE__GPIO3_5 */ - IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 0, 0x000, 0), /* MX51_PAD_NANDF_ALE__NANDF_ALE */ - IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 1, 0x000, 0), /* MX51_PAD_NANDF_ALE__PATA_BUFFER_EN */ - IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 3, 0x98c, 0), /* MX51_PAD_NANDF_CLE__GPIO3_6 */ - IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 0, 0x000, 0), /* MX51_PAD_NANDF_CLE__NANDF_CLE */ - IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 1, 0x000, 0), /* MX51_PAD_NANDF_CLE__PATA_RESET_B */ - IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 3, 0x990, 0), /* MX51_PAD_NANDF_WP_B__GPIO3_7 */ - IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 0, 0x000, 0), /* MX51_PAD_NANDF_WP_B__NANDF_WP_B */ - IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 1, 0x000, 0), /* MX51_PAD_NANDF_WP_B__PATA_DMACK */ - IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 2, 0x944, 0), /* MX51_PAD_NANDF_WP_B__SD3_DATA2 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 5, 0x930, 0), /* MX51_PAD_NANDF_RB0__ECSPI2_SS1 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 3, 0x994, 0), /* MX51_PAD_NANDF_RB0__GPIO3_8 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 0, 0x000, 0), /* MX51_PAD_NANDF_RB0__NANDF_RB0 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 1, 0x000, 0), /* MX51_PAD_NANDF_RB0__PATA_DMARQ */ - IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 2, 0x948, 0), /* MX51_PAD_NANDF_RB0__SD3_DATA3 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 6, 0x91c, 0), /* MX51_PAD_NANDF_RB1__CSPI_MOSI */ - IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 2, 0x000, 0), /* MX51_PAD_NANDF_RB1__ECSPI2_RDY */ - IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 3, 0x000, 0), /* MX51_PAD_NANDF_RB1__GPIO3_9 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 0, 0x000, 0), /* MX51_PAD_NANDF_RB1__NANDF_RB1 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 1, 0x000, 0), /* MX51_PAD_NANDF_RB1__PATA_IORDY */ - IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 5, 0x000, 0), /* MX51_PAD_NANDF_RB1__SD4_CMD */ - IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 5, 0x9a8, 0), /* MX51_PAD_NANDF_RB2__DISP2_WAIT */ - IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 2, 0x000, 0), /* MX51_PAD_NANDF_RB2__ECSPI2_SCLK */ - IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 1, 0x94c, 0), /* MX51_PAD_NANDF_RB2__FEC_COL */ - IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 3, 0x000, 0), /* MX51_PAD_NANDF_RB2__GPIO3_10 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 0, 0x000, 0), /* MX51_PAD_NANDF_RB2__NANDF_RB2 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 7, 0x000, 0), /* MX51_PAD_NANDF_RB2__USBH3_H3_DP */ - IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 6, 0xa20, 0), /* MX51_PAD_NANDF_RB2__USBH3_NXT */ - IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 5, 0x000, 0), /* MX51_PAD_NANDF_RB3__DISP1_WAIT */ - IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 2, 0x000, 0), /* MX51_PAD_NANDF_RB3__ECSPI2_MISO */ - IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 1, 0x968, 0), /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ - IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 3, 0x000, 0), /* MX51_PAD_NANDF_RB3__GPIO3_11 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 0, 0x000, 0), /* MX51_PAD_NANDF_RB3__NANDF_RB3 */ - IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 6, 0x9f8, 0), /* MX51_PAD_NANDF_RB3__USBH3_CLK */ - IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 7, 0x000, 0), /* MX51_PAD_NANDF_RB3__USBH3_H3_DM */ - IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 0, 0x998, 0), /* MX51_PAD_GPIO_NAND__GPIO_NAND */ - IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 1, 0x000, 0), /* MX51_PAD_GPIO_NAND__PATA_INTRQ */ - IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 3, 0x000, 0), /* MX51_PAD_NANDF_CS0__GPIO3_16 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 0, 0x000, 0), /* MX51_PAD_NANDF_CS0__NANDF_CS0 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 3, 0x000, 0), /* MX51_PAD_NANDF_CS1__GPIO3_17 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 0, 0x000, 0), /* MX51_PAD_NANDF_CS1__NANDF_CS1 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 6, 0x914, 0), /* MX51_PAD_NANDF_CS2__CSPI_SCLK */ - IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 2, 0x000, 0), /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ - IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 3, 0x000, 0), /* MX51_PAD_NANDF_CS2__GPIO3_18 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 0, 0x000, 0), /* MX51_PAD_NANDF_CS2__NANDF_CS2 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 1, 0x000, 0), /* MX51_PAD_NANDF_CS2__PATA_CS_0 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 5, 0x000, 0), /* MX51_PAD_NANDF_CS2__SD4_CLK */ - IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 7, 0x000, 0), /* MX51_PAD_NANDF_CS2__USBH3_H1_DP */ - IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 2, 0x000, 0), /* MX51_PAD_NANDF_CS3__FEC_MDC */ - IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS3__GPIO3_19 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS3__NANDF_CS3 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS3__PATA_CS_1 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS3__SD4_DAT0 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 7, 0x000, 0), /* MX51_PAD_NANDF_CS3__USBH3_H1_DM */ - IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 2, 0x000, 0), /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 3, 0x000, 0), /* MX51_PAD_NANDF_CS4__GPIO3_20 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 0, 0x000, 0), /* MX51_PAD_NANDF_CS4__NANDF_CS4 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 1, 0x000, 0), /* MX51_PAD_NANDF_CS4__PATA_DA_0 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 5, 0x000, 0), /* MX51_PAD_NANDF_CS4__SD4_DAT1 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 7, 0xa24, 0), /* MX51_PAD_NANDF_CS4__USBH3_STP */ - IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 2, 0x000, 0), /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 3, 0x000, 0), /* MX51_PAD_NANDF_CS5__GPIO3_21 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 0, 0x000, 0), /* MX51_PAD_NANDF_CS5__NANDF_CS5 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 1, 0x000, 0), /* MX51_PAD_NANDF_CS5__PATA_DA_1 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 5, 0x000, 0), /* MX51_PAD_NANDF_CS5__SD4_DAT2 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 7, 0xa1c, 0), /* MX51_PAD_NANDF_CS5__USBH3_DIR */ - IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 7, 0x928, 0), /* MX51_PAD_NANDF_CS6__CSPI_SS3 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 2, 0x000, 0), /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 3, 0x000, 0), /* MX51_PAD_NANDF_CS6__GPIO3_22 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 0, 0x000, 0), /* MX51_PAD_NANDF_CS6__NANDF_CS6 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 1, 0x000, 0), /* MX51_PAD_NANDF_CS6__PATA_DA_2 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 5, 0x000, 0), /* MX51_PAD_NANDF_CS6__SD4_DAT3 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ - IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS7__GPIO3_23 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS7__NANDF_CS7 */ - IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS7__SD3_CLK */ - IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 2, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 */ - IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 1, 0x974, 0), /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ - IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 3, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__GPIO3_24 */ - IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 0, 0x938, 0), /* MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT */ - IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 5, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__SD3_CMD */ - IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 2, 0x000, 0), /* MX51_PAD_NANDF_D15__ECSPI2_MOSI */ - IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 3, 0x000, 0), /* MX51_PAD_NANDF_D15__GPIO3_25 */ - IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 0, 0x000, 0), /* MX51_PAD_NANDF_D15__NANDF_D15 */ - IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 1, 0x000, 0), /* MX51_PAD_NANDF_D15__PATA_DATA15 */ - IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 5, 0x000, 0), /* MX51_PAD_NANDF_D15__SD3_DAT7 */ - IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 2, 0x934, 0), /* MX51_PAD_NANDF_D14__ECSPI2_SS3 */ - IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 3, 0x000, 0), /* MX51_PAD_NANDF_D14__GPIO3_26 */ - IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 0, 0x000, 0), /* MX51_PAD_NANDF_D14__NANDF_D14 */ - IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 1, 0x000, 0), /* MX51_PAD_NANDF_D14__PATA_DATA14 */ - IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 5, 0x000, 0), /* MX51_PAD_NANDF_D14__SD3_DAT6 */ - IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 2, 0x000, 0), /* MX51_PAD_NANDF_D13__ECSPI2_SS2 */ - IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 3, 0x000, 0), /* MX51_PAD_NANDF_D13__GPIO3_27 */ - IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 0, 0x000, 0), /* MX51_PAD_NANDF_D13__NANDF_D13 */ - IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 1, 0x000, 0), /* MX51_PAD_NANDF_D13__PATA_DATA13 */ - IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 5, 0x000, 0), /* MX51_PAD_NANDF_D13__SD3_DAT5 */ - IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 2, 0x930, 1), /* MX51_PAD_NANDF_D12__ECSPI2_SS1 */ - IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 3, 0x000, 0), /* MX51_PAD_NANDF_D12__GPIO3_28 */ - IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 0, 0x000, 0), /* MX51_PAD_NANDF_D12__NANDF_D12 */ - IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 1, 0x000, 0), /* MX51_PAD_NANDF_D12__PATA_DATA12 */ - IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 5, 0x000, 0), /* MX51_PAD_NANDF_D12__SD3_DAT4 */ - IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 2, 0x96c, 0), /* MX51_PAD_NANDF_D11__FEC_RX_DV */ - IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 3, 0x000, 0), /* MX51_PAD_NANDF_D11__GPIO3_29 */ - IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 0, 0x000, 0), /* MX51_PAD_NANDF_D11__NANDF_D11 */ - IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 1, 0x000, 0), /* MX51_PAD_NANDF_D11__PATA_DATA11 */ - IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 5, 0x948, 1), /* MX51_PAD_NANDF_D11__SD3_DATA3 */ - IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 3, 0x000, 0), /* MX51_PAD_NANDF_D10__GPIO3_30 */ - IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 0, 0x000, 0), /* MX51_PAD_NANDF_D10__NANDF_D10 */ - IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 1, 0x000, 0), /* MX51_PAD_NANDF_D10__PATA_DATA10 */ - IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 5, 0x944, 1), /* MX51_PAD_NANDF_D10__SD3_DATA2 */ - IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 2, 0x958, 0), /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ - IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 3, 0x000, 0), /* MX51_PAD_NANDF_D9__GPIO3_31 */ - IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 0, 0x000, 0), /* MX51_PAD_NANDF_D9__NANDF_D9 */ - IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 1, 0x000, 0), /* MX51_PAD_NANDF_D9__PATA_DATA9 */ - IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 5, 0x940, 1), /* MX51_PAD_NANDF_D9__SD3_DATA1 */ - IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 2, 0x000, 0), /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ - IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 3, 0x000, 0), /* MX51_PAD_NANDF_D8__GPIO4_0 */ - IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 0, 0x000, 0), /* MX51_PAD_NANDF_D8__NANDF_D8 */ - IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 1, 0x000, 0), /* MX51_PAD_NANDF_D8__PATA_DATA8 */ - IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 5, 0x93c, 1), /* MX51_PAD_NANDF_D8__SD3_DATA0 */ - IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 3, 0x000, 0), /* MX51_PAD_NANDF_D7__GPIO4_1 */ - IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 0, 0x000, 0), /* MX51_PAD_NANDF_D7__NANDF_D7 */ - IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 1, 0x000, 0), /* MX51_PAD_NANDF_D7__PATA_DATA7 */ - IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 5, 0x9fc, 0), /* MX51_PAD_NANDF_D7__USBH3_DATA0 */ - IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 3, 0x000, 0), /* MX51_PAD_NANDF_D6__GPIO4_2 */ - IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 0, 0x000, 0), /* MX51_PAD_NANDF_D6__NANDF_D6 */ - IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 1, 0x000, 0), /* MX51_PAD_NANDF_D6__PATA_DATA6 */ - IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 2, 0x000, 0), /* MX51_PAD_NANDF_D6__SD4_LCTL */ - IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 5, 0xa00, 0), /* MX51_PAD_NANDF_D6__USBH3_DATA1 */ - IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 3, 0x000, 0), /* MX51_PAD_NANDF_D5__GPIO4_3 */ - IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 0, 0x000, 0), /* MX51_PAD_NANDF_D5__NANDF_D5 */ - IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 1, 0x000, 0), /* MX51_PAD_NANDF_D5__PATA_DATA5 */ - IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 2, 0x000, 0), /* MX51_PAD_NANDF_D5__SD4_WP */ - IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 5, 0xa04, 0), /* MX51_PAD_NANDF_D5__USBH3_DATA2 */ - IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 3, 0x000, 0), /* MX51_PAD_NANDF_D4__GPIO4_4 */ - IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 0, 0x000, 0), /* MX51_PAD_NANDF_D4__NANDF_D4 */ - IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 1, 0x000, 0), /* MX51_PAD_NANDF_D4__PATA_DATA4 */ - IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 2, 0x000, 0), /* MX51_PAD_NANDF_D4__SD4_CD */ - IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 5, 0xa08, 0), /* MX51_PAD_NANDF_D4__USBH3_DATA3 */ - IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 3, 0x000, 0), /* MX51_PAD_NANDF_D3__GPIO4_5 */ - IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 0, 0x000, 0), /* MX51_PAD_NANDF_D3__NANDF_D3 */ - IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 1, 0x000, 0), /* MX51_PAD_NANDF_D3__PATA_DATA3 */ - IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 2, 0x000, 0), /* MX51_PAD_NANDF_D3__SD4_DAT4 */ - IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 5, 0xa0c, 0), /* MX51_PAD_NANDF_D3__USBH3_DATA4 */ - IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 3, 0x000, 0), /* MX51_PAD_NANDF_D2__GPIO4_6 */ - IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 0, 0x000, 0), /* MX51_PAD_NANDF_D2__NANDF_D2 */ - IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 1, 0x000, 0), /* MX51_PAD_NANDF_D2__PATA_DATA2 */ - IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 2, 0x000, 0), /* MX51_PAD_NANDF_D2__SD4_DAT5 */ - IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 5, 0xa10, 0), /* MX51_PAD_NANDF_D2__USBH3_DATA5 */ - IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 3, 0x000, 0), /* MX51_PAD_NANDF_D1__GPIO4_7 */ - IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 0, 0x000, 0), /* MX51_PAD_NANDF_D1__NANDF_D1 */ - IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 1, 0x000, 0), /* MX51_PAD_NANDF_D1__PATA_DATA1 */ - IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 2, 0x000, 0), /* MX51_PAD_NANDF_D1__SD4_DAT6 */ - IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 5, 0xa14, 0), /* MX51_PAD_NANDF_D1__USBH3_DATA6 */ - IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 3, 0x000, 0), /* MX51_PAD_NANDF_D0__GPIO4_8 */ - IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 0, 0x000, 0), /* MX51_PAD_NANDF_D0__NANDF_D0 */ - IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 1, 0x000, 0), /* MX51_PAD_NANDF_D0__PATA_DATA0 */ - IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 2, 0x000, 0), /* MX51_PAD_NANDF_D0__SD4_DAT7 */ - IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 5, 0xa18, 0), /* MX51_PAD_NANDF_D0__USBH3_DATA7 */ - IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 0, 0x000, 0), /* MX51_PAD_CSI1_D8__CSI1_D8 */ - IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 3, 0x998, 1), /* MX51_PAD_CSI1_D8__GPIO3_12 */ - IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 0, 0x000, 0), /* MX51_PAD_CSI1_D9__CSI1_D9 */ - IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 3, 0x000, 0), /* MX51_PAD_CSI1_D9__GPIO3_13 */ - IMX_PIN_REG(MX51_PAD_CSI1_D10, 0x584, 0x19c, 0, 0x000, 0), /* MX51_PAD_CSI1_D10__CSI1_D10 */ - IMX_PIN_REG(MX51_PAD_CSI1_D11, 0x588, 0x1a0, 0, 0x000, 0), /* MX51_PAD_CSI1_D11__CSI1_D11 */ - IMX_PIN_REG(MX51_PAD_CSI1_D12, 0x58c, 0x1a4, 0, 0x000, 0), /* MX51_PAD_CSI1_D12__CSI1_D12 */ - IMX_PIN_REG(MX51_PAD_CSI1_D13, 0x590, 0x1a8, 0, 0x000, 0), /* MX51_PAD_CSI1_D13__CSI1_D13 */ - IMX_PIN_REG(MX51_PAD_CSI1_D14, 0x594, 0x1ac, 0, 0x000, 0), /* MX51_PAD_CSI1_D14__CSI1_D14 */ - IMX_PIN_REG(MX51_PAD_CSI1_D15, 0x598, 0x1b0, 0, 0x000, 0), /* MX51_PAD_CSI1_D15__CSI1_D15 */ - IMX_PIN_REG(MX51_PAD_CSI1_D16, 0x59c, 0x1b4, 0, 0x000, 0), /* MX51_PAD_CSI1_D16__CSI1_D16 */ - IMX_PIN_REG(MX51_PAD_CSI1_D17, 0x5a0, 0x1b8, 0, 0x000, 0), /* MX51_PAD_CSI1_D17__CSI1_D17 */ - IMX_PIN_REG(MX51_PAD_CSI1_D18, 0x5a4, 0x1bc, 0, 0x000, 0), /* MX51_PAD_CSI1_D18__CSI1_D18 */ - IMX_PIN_REG(MX51_PAD_CSI1_D19, 0x5a8, 0x1c0, 0, 0x000, 0), /* MX51_PAD_CSI1_D19__CSI1_D19 */ - IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 0, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__CSI1_VSYNC */ - IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 3, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__GPIO3_14 */ - IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 0, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__CSI1_HSYNC */ - IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 3, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__GPIO3_15 */ - IMX_PIN_REG(MX51_PAD_CSI1_PIXCLK, 0x5b4, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK */ - IMX_PIN_REG(MX51_PAD_CSI1_MCLK, 0x5b8, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_MCLK__CSI1_MCLK */ - IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 0, 0x000, 0), /* MX51_PAD_CSI2_D12__CSI2_D12 */ - IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 3, 0x000, 0), /* MX51_PAD_CSI2_D12__GPIO4_9 */ - IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 0, 0x000, 0), /* MX51_PAD_CSI2_D13__CSI2_D13 */ - IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 3, 0x000, 0), /* MX51_PAD_CSI2_D13__GPIO4_10 */ - IMX_PIN_REG(MX51_PAD_CSI2_D14, 0x5c4, 0x1d4, 0, 0x000, 0), /* MX51_PAD_CSI2_D14__CSI2_D14 */ - IMX_PIN_REG(MX51_PAD_CSI2_D15, 0x5c8, 0x1d8, 0, 0x000, 0), /* MX51_PAD_CSI2_D15__CSI2_D15 */ - IMX_PIN_REG(MX51_PAD_CSI2_D16, 0x5cc, 0x1dc, 0, 0x000, 0), /* MX51_PAD_CSI2_D16__CSI2_D16 */ - IMX_PIN_REG(MX51_PAD_CSI2_D17, 0x5d0, 0x1e0, 0, 0x000, 0), /* MX51_PAD_CSI2_D17__CSI2_D17 */ - IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 0, 0x000, 0), /* MX51_PAD_CSI2_D18__CSI2_D18 */ - IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 3, 0x000, 0), /* MX51_PAD_CSI2_D18__GPIO4_11 */ - IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 0, 0x000, 0), /* MX51_PAD_CSI2_D19__CSI2_D19 */ - IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 3, 0x000, 0), /* MX51_PAD_CSI2_D19__GPIO4_12 */ - IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 0, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__CSI2_VSYNC */ - IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 3, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__GPIO4_13 */ - IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 0, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__CSI2_HSYNC */ - IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 3, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__GPIO4_14 */ - IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 0, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK */ - IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 3, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__GPIO4_15 */ - IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 3, 0x000, 0), /* MX51_PAD_I2C1_CLK__GPIO4_16 */ - IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 0, 0x000, 0), /* MX51_PAD_I2C1_CLK__I2C1_CLK */ - IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 3, 0x000, 0), /* MX51_PAD_I2C1_DAT__GPIO4_17 */ - IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 0, 0x000, 0), /* MX51_PAD_I2C1_DAT__I2C1_DAT */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__GPIO4_18 */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__GPIO4_19 */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 1, 0x9f4, 2), /* MX51_PAD_AUD3_BB_RXD__UART3_RXD */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__GPIO4_20 */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__GPIO4_21 */ - IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 1, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__UART3_TXD */ - IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 0, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ - IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 3, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__GPIO4_22 */ - IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 1, 0x9b4, 1), /* MX51_PAD_CSPI1_MOSI__I2C1_SDA */ - IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 1, 0x8c4, 1), /* MX51_PAD_CSPI1_MISO__AUD4_RXD */ - IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 0, 0x000, 0), /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ - IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 3, 0x000, 0), /* MX51_PAD_CSPI1_MISO__GPIO4_23 */ - IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 1, 0x8cc, 1), /* MX51_PAD_CSPI1_SS0__AUD4_TXC */ - IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS0__ECSPI1_SS0 */ - IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS0__GPIO4_24 */ - IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 1, 0x8c8, 1), /* MX51_PAD_CSPI1_SS1__AUD4_TXD */ - IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS1__ECSPI1_SS1 */ - IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS1__GPIO4_25 */ - IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 1, 0x8d0, 1), /* MX51_PAD_CSPI1_RDY__AUD4_TXFS */ - IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 0, 0x000, 0), /* MX51_PAD_CSPI1_RDY__ECSPI1_RDY */ - IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 3, 0x000, 0), /* MX51_PAD_CSPI1_RDY__GPIO4_26 */ - IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 0, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ - IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 3, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__GPIO4_27 */ - IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 1, 0x9b0, 1), /* MX51_PAD_CSPI1_SCLK__I2C1_SCL */ - IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 3, 0x000, 0), /* MX51_PAD_UART1_RXD__GPIO4_28 */ - IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 0, 0x9e4, 0), /* MX51_PAD_UART1_RXD__UART1_RXD */ - IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 3, 0x000, 0), /* MX51_PAD_UART1_TXD__GPIO4_29 */ - IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 1, 0x000, 0), /* MX51_PAD_UART1_TXD__PWM2_PWMO */ - IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 0, 0x000, 0), /* MX51_PAD_UART1_TXD__UART1_TXD */ - IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 3, 0x000, 0), /* MX51_PAD_UART1_RTS__GPIO4_30 */ - IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 0, 0x9e0, 0), /* MX51_PAD_UART1_RTS__UART1_RTS */ - IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 3, 0x000, 0), /* MX51_PAD_UART1_CTS__GPIO4_31 */ - IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 0, 0x000, 0), /* MX51_PAD_UART1_CTS__UART1_CTS */ - IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 1, 0x000, 0), /* MX51_PAD_UART2_RXD__FIRI_TXD */ - IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 3, 0x000, 0), /* MX51_PAD_UART2_RXD__GPIO1_20 */ - IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 0, 0x9ec, 2), /* MX51_PAD_UART2_RXD__UART2_RXD */ - IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 1, 0x000, 0), /* MX51_PAD_UART2_TXD__FIRI_RXD */ - IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 3, 0x000, 0), /* MX51_PAD_UART2_TXD__GPIO1_21 */ - IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 0, 0x000, 0), /* MX51_PAD_UART2_TXD__UART2_TXD */ - IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 2, 0x000, 0), /* MX51_PAD_UART3_RXD__CSI1_D0 */ - IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 3, 0x000, 0), /* MX51_PAD_UART3_RXD__GPIO1_22 */ - IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 0, 0x000, 0), /* MX51_PAD_UART3_RXD__UART1_DTR */ - IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 1, 0x9f4, 4), /* MX51_PAD_UART3_RXD__UART3_RXD */ - IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 2, 0x000, 0), /* MX51_PAD_UART3_TXD__CSI1_D1 */ - IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 3, 0x000, 0), /* MX51_PAD_UART3_TXD__GPIO1_23 */ - IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 0, 0x000, 0), /* MX51_PAD_UART3_TXD__UART1_DSR */ - IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 1, 0x000, 0), /* MX51_PAD_UART3_TXD__UART3_TXD */ - IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 3, 0x000, 0), /* MX51_PAD_OWIRE_LINE__GPIO1_24 */ - IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 0, 0x000, 0), /* MX51_PAD_OWIRE_LINE__OWIRE_LINE */ - IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 6, 0x000, 0), /* MX51_PAD_OWIRE_LINE__SPDIF_OUT */ - IMX_PIN_REG(MX51_PAD_KEY_ROW0, 0x63c, 0x24c, 0, 0x000, 0), /* MX51_PAD_KEY_ROW0__KEY_ROW0 */ - IMX_PIN_REG(MX51_PAD_KEY_ROW1, 0x640, 0x250, 0, 0x000, 0), /* MX51_PAD_KEY_ROW1__KEY_ROW1 */ - IMX_PIN_REG(MX51_PAD_KEY_ROW2, 0x644, 0x254, 0, 0x000, 0), /* MX51_PAD_KEY_ROW2__KEY_ROW2 */ - IMX_PIN_REG(MX51_PAD_KEY_ROW3, 0x648, 0x258, 0, 0x000, 0), /* MX51_PAD_KEY_ROW3__KEY_ROW3 */ - IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 0, 0x000, 0), /* MX51_PAD_KEY_COL0__KEY_COL0 */ - IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 7, 0x90c, 0), /* MX51_PAD_KEY_COL0__PLL1_BYP */ - IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 0, 0x000, 0), /* MX51_PAD_KEY_COL1__KEY_COL1 */ - IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 7, 0x910, 0), /* MX51_PAD_KEY_COL1__PLL2_BYP */ - IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 0, 0x000, 0), /* MX51_PAD_KEY_COL2__KEY_COL2 */ - IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 7, 0x000, 0), /* MX51_PAD_KEY_COL2__PLL3_BYP */ - IMX_PIN_REG(MX51_PAD_KEY_COL3, 0x658, 0x268, 0, 0x000, 0), /* MX51_PAD_KEY_COL3__KEY_COL3 */ - IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 3, 0x9b8, 1), /* MX51_PAD_KEY_COL4__I2C2_SCL */ - IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 0, 0x000, 0), /* MX51_PAD_KEY_COL4__KEY_COL4 */ - IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 6, 0x000, 0), /* MX51_PAD_KEY_COL4__SPDIF_OUT1 */ - IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 1, 0x000, 0), /* MX51_PAD_KEY_COL4__UART1_RI */ - IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 2, 0x9f0, 4), /* MX51_PAD_KEY_COL4__UART3_RTS */ - IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 3, 0x9bc, 1), /* MX51_PAD_KEY_COL5__I2C2_SDA */ - IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 0, 0x000, 0), /* MX51_PAD_KEY_COL5__KEY_COL5 */ - IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 1, 0x000, 0), /* MX51_PAD_KEY_COL5__UART1_DCD */ - IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 2, 0x000, 0), /* MX51_PAD_KEY_COL5__UART3_CTS */ - IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 1, 0x914, 1), /* MX51_PAD_USBH1_CLK__CSPI_SCLK */ - IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 2, 0x000, 0), /* MX51_PAD_USBH1_CLK__GPIO1_25 */ - IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 5, 0x9b8, 2), /* MX51_PAD_USBH1_CLK__I2C2_SCL */ - IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 0, 0x000, 0), /* MX51_PAD_USBH1_CLK__USBH1_CLK */ - IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 1, 0x91c, 1), /* MX51_PAD_USBH1_DIR__CSPI_MOSI */ - IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 2, 0x000, 0), /* MX51_PAD_USBH1_DIR__GPIO1_26 */ - IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 5, 0x9bc, 2), /* MX51_PAD_USBH1_DIR__I2C2_SDA */ - IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 0, 0x000, 0), /* MX51_PAD_USBH1_DIR__USBH1_DIR */ - IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 1, 0x000, 0), /* MX51_PAD_USBH1_STP__CSPI_RDY */ - IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 2, 0x000, 0), /* MX51_PAD_USBH1_STP__GPIO1_27 */ - IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 5, 0x9f4, 6), /* MX51_PAD_USBH1_STP__UART3_RXD */ - IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 0, 0x000, 0), /* MX51_PAD_USBH1_STP__USBH1_STP */ - IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 1, 0x918, 0), /* MX51_PAD_USBH1_NXT__CSPI_MISO */ - IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 2, 0x000, 0), /* MX51_PAD_USBH1_NXT__GPIO1_28 */ - IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 5, 0x000, 0), /* MX51_PAD_USBH1_NXT__UART3_TXD */ - IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 0, 0x000, 0), /* MX51_PAD_USBH1_NXT__USBH1_NXT */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA0__GPIO1_11 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA0__UART2_CTS */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA0__USBH1_DATA0 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA1__GPIO1_12 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 1, 0x9ec, 4), /* MX51_PAD_USBH1_DATA1__UART2_RXD */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA1__USBH1_DATA1 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA2__GPIO1_13 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA2__UART2_TXD */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA2__USBH1_DATA2 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA3__GPIO1_14 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 1, 0x9e8, 5), /* MX51_PAD_USBH1_DATA3__UART2_RTS */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA3__USBH1_DATA3 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA4__CSPI_SS0 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA4__GPIO1_15 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA4__USBH1_DATA4 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 1, 0x920, 0), /* MX51_PAD_USBH1_DATA5__CSPI_SS1 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA5__GPIO1_16 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA5__USBH1_DATA5 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 1, 0x928, 1), /* MX51_PAD_USBH1_DATA6__CSPI_SS3 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA6__GPIO1_17 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA6__USBH1_DATA6 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA7__ECSPI1_SS3 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 5, 0x934, 1), /* MX51_PAD_USBH1_DATA7__ECSPI2_SS3 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA7__GPIO1_18 */ - IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA7__USBH1_DATA7 */ - IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 0, 0x000, 0), /* MX51_PAD_DI1_PIN11__DI1_PIN11 */ - IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 7, 0x000, 0), /* MX51_PAD_DI1_PIN11__ECSPI1_SS2 */ - IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 4, 0x000, 0), /* MX51_PAD_DI1_PIN11__GPIO3_0 */ - IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 0, 0x000, 0), /* MX51_PAD_DI1_PIN12__DI1_PIN12 */ - IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 4, 0x978, 1), /* MX51_PAD_DI1_PIN12__GPIO3_1 */ - IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 0, 0x000, 0), /* MX51_PAD_DI1_PIN13__DI1_PIN13 */ - IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 4, 0x97c, 1), /* MX51_PAD_DI1_PIN13__GPIO3_2 */ - IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 0, 0x000, 0), /* MX51_PAD_DI1_D0_CS__DI1_D0_CS */ - IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 4, 0x980, 1), /* MX51_PAD_DI1_D0_CS__GPIO3_3 */ - IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 0, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DI1_D1_CS */ - IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 2, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN14 */ - IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 3, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN5 */ - IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 4, 0x984, 1), /* MX51_PAD_DI1_D1_CS__GPIO3_4 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 2, 0x9a4, 1), /* MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 0, 0x9c4, 0), /* MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 4, 0x988, 1), /* MX51_PAD_DISPB2_SER_DIN__GPIO3_5 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 0, 0x9c4, 1), /* MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 4, 0x98c, 1), /* MX51_PAD_DISPB2_SER_DIO__GPIO3_6 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 4, 0x990, 1), /* MX51_PAD_DISPB2_SER_CLK__GPIO3_7 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */ - IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 4, 0x994, 1), /* MX51_PAD_DISPB2_SER_RS__GPIO3_8 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT0, 0x6cc, 0x2cc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT1, 0x6d0, 0x2d0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT2, 0x6d4, 0x2d4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT3, 0x6d8, 0x2d8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT4, 0x6dc, 0x2dc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT5, 0x6e0, 0x2e0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT6__BOOT_USB_SRC */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT8__BOOT_SRC0 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT9__BOOT_SRC1 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN11 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN5 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN12 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN6 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN13 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN7 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN14 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN8 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_D0_CS */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_DAT16 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_D1_CS */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_DAT17 */ - IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_SER_CS */ - IMX_PIN_REG(MX51_PAD_DI1_PIN3, 0x72c, 0x32c, 0, 0x000, 0), /* MX51_PAD_DI1_PIN3__DI1_PIN3 */ - IMX_PIN_REG(MX51_PAD_DI1_PIN2, 0x734, 0x330, 0, 0x000, 0), /* MX51_PAD_DI1_PIN2__DI1_PIN2 */ - IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 0, 0x000, 0), /* MX51_PAD_DI_GP2__DISP1_SER_CLK */ - IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 2, 0x9a8, 1), /* MX51_PAD_DI_GP2__DISP2_WAIT */ - IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 3, 0x9a0, 1), /* MX51_PAD_DI_GP3__CSI1_DATA_EN */ - IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 0, 0x9c0, 0), /* MX51_PAD_DI_GP3__DISP1_SER_DIO */ - IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 2, 0x000, 0), /* MX51_PAD_DI_GP3__FEC_TX_ER */ - IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 3, 0x99c, 1), /* MX51_PAD_DI2_PIN4__CSI2_DATA_EN */ - IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 0, 0x000, 0), /* MX51_PAD_DI2_PIN4__DI2_PIN4 */ - IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 2, 0x950, 1), /* MX51_PAD_DI2_PIN4__FEC_CRS */ - IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 0, 0x000, 0), /* MX51_PAD_DI2_PIN2__DI2_PIN2 */ - IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 2, 0x000, 0), /* MX51_PAD_DI2_PIN2__FEC_MDC */ - IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 0, 0x000, 0), /* MX51_PAD_DI2_PIN3__DI2_PIN3 */ - IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 2, 0x954, 1), /* MX51_PAD_DI2_PIN3__FEC_MDIO */ - IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 0, 0x000, 0), /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */ - IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 2, 0x95c, 1), /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */ - IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 4, 0x000, 0), /* MX51_PAD_DI_GP4__DI2_PIN15 */ - IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 0, 0x9c0, 1), /* MX51_PAD_DI_GP4__DISP1_SER_DIN */ - IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 3, 0x000, 0), /* MX51_PAD_DI_GP4__DISP2_PIN1 */ - IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 2, 0x960, 1), /* MX51_PAD_DI_GP4__FEC_RDATA2 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 2, 0x964, 1), /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 4, 0x9c8, 1), /* MX51_PAD_DISP2_DAT0__KEY_COL6 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 5, 0x9f4, 8), /* MX51_PAD_DISP2_DAT0__UART3_RXD */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 3, 0x9f8, 1), /* MX51_PAD_DISP2_DAT0__USBH3_CLK */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 2, 0x970, 1), /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 4, 0x9cc, 1), /* MX51_PAD_DISP2_DAT1__KEY_COL7 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT1__UART3_TXD */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 3, 0xa1c, 1), /* MX51_PAD_DISP2_DAT1__USBH3_DIR */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT2, 0x764, 0x35c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT3, 0x768, 0x360, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT4, 0x76c, 0x364, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT5, 0x770, 0x368, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT6__GPIO1_19 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 4, 0x9d0, 1), /* MX51_PAD_DISP2_DAT6__KEY_ROW4 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 3, 0xa24, 1), /* MX51_PAD_DISP2_DAT6__USBH3_STP */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT7__GPIO1_29 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 4, 0x9d4, 1), /* MX51_PAD_DISP2_DAT7__KEY_ROW5 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 3, 0xa20, 1), /* MX51_PAD_DISP2_DAT7__USBH3_NXT */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT8__GPIO1_30 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 4, 0x9d8, 1), /* MX51_PAD_DISP2_DAT8__KEY_ROW6 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 3, 0x9fc, 1), /* MX51_PAD_DISP2_DAT8__USBH3_DATA0 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 4, 0x8f4, 1), /* MX51_PAD_DISP2_DAT9__AUD6_RXC */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT9__GPIO1_31 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 3, 0xa00, 1), /* MX51_PAD_DISP2_DAT9__USBH3_DATA1 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_SER_CS */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 2, 0x94c, 1), /* MX51_PAD_DISP2_DAT10__FEC_COL */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 4, 0x9dc, 1), /* MX51_PAD_DISP2_DAT10__KEY_ROW7 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 3, 0xa04, 1), /* MX51_PAD_DISP2_DAT10__USBH3_DATA2 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 4, 0x8f0, 1), /* MX51_PAD_DISP2_DAT11__AUD6_TXD */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 2, 0x968, 1), /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 7, 0x000, 0), /* MX51_PAD_DISP2_DAT11__GPIO1_10 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 3, 0xa08, 1), /* MX51_PAD_DISP2_DAT11__USBH3_DATA3 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 4, 0x8ec, 1), /* MX51_PAD_DISP2_DAT12__AUD6_RXD */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 2, 0x96c, 1), /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 3, 0xa0c, 1), /* MX51_PAD_DISP2_DAT12__USBH3_DATA4 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 4, 0x8fc, 1), /* MX51_PAD_DISP2_DAT13__AUD6_TXC */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 2, 0x974, 1), /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 3, 0xa10, 1), /* MX51_PAD_DISP2_DAT13__USBH3_DATA5 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 4, 0x900, 1), /* MX51_PAD_DISP2_DAT14__AUD6_TXFS */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 2, 0x958, 1), /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 3, 0xa14, 1), /* MX51_PAD_DISP2_DAT14__USBH3_DATA6 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 4, 0x8f8, 1), /* MX51_PAD_DISP2_DAT15__AUD6_RXFS */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP1_SER_CS */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */ - IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 3, 0xa18, 1), /* MX51_PAD_DISP2_DAT15__USBH3_DATA7 */ - IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 1, 0x8e0, 1), /* MX51_PAD_SD1_CMD__AUD5_RXFS */ - IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 2, 0x91c, 2), /* MX51_PAD_SD1_CMD__CSPI_MOSI */ - IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 0, 0x000, 0), /* MX51_PAD_SD1_CMD__SD1_CMD */ - IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 1, 0x8dc, 1), /* MX51_PAD_SD1_CLK__AUD5_RXC */ - IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 2, 0x914, 2), /* MX51_PAD_SD1_CLK__CSPI_SCLK */ - IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 0, 0x000, 0), /* MX51_PAD_SD1_CLK__SD1_CLK */ - IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 1, 0x8d8, 2), /* MX51_PAD_SD1_DATA0__AUD5_TXD */ - IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 2, 0x918, 1), /* MX51_PAD_SD1_DATA0__CSPI_MISO */ - IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 0, 0x000, 0), /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ - IMX_PIN_REG(MX51_PAD_EIM_DA0, NO_PAD, 0x01c, 0, 0x000, 0), /* MX51_PAD_EIM_DA0__EIM_DA0 */ - IMX_PIN_REG(MX51_PAD_EIM_DA1, NO_PAD, 0x020, 0, 0x000, 0), /* MX51_PAD_EIM_DA1__EIM_DA1 */ - IMX_PIN_REG(MX51_PAD_EIM_DA2, NO_PAD, 0x024, 0, 0x000, 0), /* MX51_PAD_EIM_DA2__EIM_DA2 */ - IMX_PIN_REG(MX51_PAD_EIM_DA3, NO_PAD, 0x028, 0, 0x000, 0), /* MX51_PAD_EIM_DA3__EIM_DA3 */ - IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 1, 0x8d4, 2), /* MX51_PAD_SD1_DATA1__AUD5_RXD */ - IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 0, 0x000, 0), /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ - IMX_PIN_REG(MX51_PAD_EIM_DA4, NO_PAD, 0x02c, 0, 0x000, 0), /* MX51_PAD_EIM_DA4__EIM_DA4 */ - IMX_PIN_REG(MX51_PAD_EIM_DA5, NO_PAD, 0x030, 0, 0x000, 0), /* MX51_PAD_EIM_DA5__EIM_DA5 */ - IMX_PIN_REG(MX51_PAD_EIM_DA6, NO_PAD, 0x034, 0, 0x000, 0), /* MX51_PAD_EIM_DA6__EIM_DA6 */ - IMX_PIN_REG(MX51_PAD_EIM_DA7, NO_PAD, 0x038, 0, 0x000, 0), /* MX51_PAD_EIM_DA7__EIM_DA7 */ - IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 1, 0x8e4, 2), /* MX51_PAD_SD1_DATA2__AUD5_TXC */ - IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 0, 0x000, 0), /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ - IMX_PIN_REG(MX51_PAD_EIM_DA10, NO_PAD, 0x044, 0, 0x000, 0), /* MX51_PAD_EIM_DA10__EIM_DA10 */ - IMX_PIN_REG(MX51_PAD_EIM_DA11, NO_PAD, 0x048, 0, 0x000, 0), /* MX51_PAD_EIM_DA11__EIM_DA11 */ - IMX_PIN_REG(MX51_PAD_EIM_DA8, NO_PAD, 0x03c, 0, 0x000, 0), /* MX51_PAD_EIM_DA8__EIM_DA8 */ - IMX_PIN_REG(MX51_PAD_EIM_DA9, NO_PAD, 0x040, 0, 0x000, 0), /* MX51_PAD_EIM_DA9__EIM_DA9 */ - IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 1, 0x8e8, 2), /* MX51_PAD_SD1_DATA3__AUD5_TXFS */ - IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 2, 0x920, 1), /* MX51_PAD_SD1_DATA3__CSPI_SS1 */ - IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 0, 0x000, 0), /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ - IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 2, 0x924, 0), /* MX51_PAD_GPIO1_0__CSPI_SS2 */ - IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 1, 0x000, 0), /* MX51_PAD_GPIO1_0__GPIO1_0 */ - IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 0, 0x000, 0), /* MX51_PAD_GPIO1_0__SD1_CD */ - IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 2, 0x918, 2), /* MX51_PAD_GPIO1_1__CSPI_MISO */ - IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 1, 0x000, 0), /* MX51_PAD_GPIO1_1__GPIO1_1 */ - IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 0, 0x000, 0), /* MX51_PAD_GPIO1_1__SD1_WP */ - IMX_PIN_REG(MX51_PAD_EIM_DA12, NO_PAD, 0x04c, 0, 0x000, 0), /* MX51_PAD_EIM_DA12__EIM_DA12 */ - IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */ - IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */ - IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */ - IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */ - IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */ - IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */ - IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */ - IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 1, 0x9b4, 2), /* MX51_PAD_SD2_CLK__I2C1_SDA */ - IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 0, 0x000, 0), /* MX51_PAD_SD2_CLK__SD2_CLK */ - IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 2, 0x918, 3), /* MX51_PAD_SD2_DATA0__CSPI_MISO */ - IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 1, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD1_DAT4 */ - IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 0, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ - IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 1, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD1_DAT5 */ - IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 0, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ - IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 2, 0x000, 0), /* MX51_PAD_SD2_DATA1__USBH3_H2_DP */ - IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 1, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD1_DAT6 */ - IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 0, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ - IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 2, 0x000, 0), /* MX51_PAD_SD2_DATA2__USBH3_H2_DM */ - IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 2, 0x924, 1), /* MX51_PAD_SD2_DATA3__CSPI_SS2 */ - IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 1, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD1_DAT7 */ - IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 0, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ - IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 5, 0x000, 0), /* MX51_PAD_GPIO1_2__CCM_OUT_2 */ - IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 0, 0x000, 0), /* MX51_PAD_GPIO1_2__GPIO1_2 */ - IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 2, 0x9b8, 3), /* MX51_PAD_GPIO1_2__I2C2_SCL */ - IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 7, 0x90c, 1), /* MX51_PAD_GPIO1_2__PLL1_BYP */ - IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 1, 0x000, 0), /* MX51_PAD_GPIO1_2__PWM1_PWMO */ - IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 0, 0x000, 0), /* MX51_PAD_GPIO1_3__GPIO1_3 */ - IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 2, 0x9bc, 3), /* MX51_PAD_GPIO1_3__I2C2_SDA */ - IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 7, 0x910, 1), /* MX51_PAD_GPIO1_3__PLL2_BYP */ - IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 1, 0x000, 0), /* MX51_PAD_GPIO1_3__PWM2_PWMO */ - IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 0, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ */ - IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 1, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B */ - IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 4, 0x908, 1), /* MX51_PAD_GPIO1_4__DISP2_EXT_CLK */ - IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 3, 0x938, 1), /* MX51_PAD_GPIO1_4__EIM_RDY */ - IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 0, 0x000, 0), /* MX51_PAD_GPIO1_4__GPIO1_4 */ - IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 2, 0x000, 0), /* MX51_PAD_GPIO1_4__WDOG1_WDOG_B */ - IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 6, 0x000, 0), /* MX51_PAD_GPIO1_5__CSI2_MCLK */ - IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 3, 0x000, 0), /* MX51_PAD_GPIO1_5__DISP2_PIN16 */ - IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 0, 0x000, 0), /* MX51_PAD_GPIO1_5__GPIO1_5 */ - IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 2, 0x000, 0), /* MX51_PAD_GPIO1_5__WDOG2_WDOG_B */ - IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 4, 0x000, 0), /* MX51_PAD_GPIO1_6__DISP2_PIN17 */ - IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 0, 0x000, 0), /* MX51_PAD_GPIO1_6__GPIO1_6 */ - IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 3, 0x000, 0), /* MX51_PAD_GPIO1_6__REF_EN_B */ - IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 3, 0x000, 0), /* MX51_PAD_GPIO1_7__CCM_OUT_0 */ - IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 0, 0x000, 0), /* MX51_PAD_GPIO1_7__GPIO1_7 */ - IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 6, 0x000, 0), /* MX51_PAD_GPIO1_7__SD2_WP */ - IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 2, 0x000, 0), /* MX51_PAD_GPIO1_7__SPDIF_OUT1 */ - IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 2, 0x99c, 2), /* MX51_PAD_GPIO1_8__CSI2_DATA_EN */ - IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 0, 0x000, 0), /* MX51_PAD_GPIO1_8__GPIO1_8 */ - IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 6, 0x000, 0), /* MX51_PAD_GPIO1_8__SD2_CD */ - IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 1, 0x000, 0), /* MX51_PAD_GPIO1_8__USBH3_PWR */ - IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 3, 0x000, 0), /* MX51_PAD_GPIO1_9__CCM_OUT_1 */ - IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 2, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_D1_CS */ - IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 7, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_SER_CS */ - IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 0, 0x000, 0), /* MX51_PAD_GPIO1_9__GPIO1_9 */ - IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 6, 0x000, 0), /* MX51_PAD_GPIO1_9__SD2_LCTL */ - IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 1, 0x000, 0), /* MX51_PAD_GPIO1_9__USBH3_OC */ + MX51_PAD_RESERVE0 = 0, + MX51_PAD_RESERVE1 = 1, + MX51_PAD_RESERVE2 = 2, + MX51_PAD_RESERVE3 = 3, + MX51_PAD_RESERVE4 = 4, + MX51_PAD_RESERVE5 = 5, + MX51_PAD_RESERVE6 = 6, + MX51_PAD_EIM_DA0 = 7, + MX51_PAD_EIM_DA1 = 8, + MX51_PAD_EIM_DA2 = 9, + MX51_PAD_EIM_DA3 = 10, + MX51_PAD_EIM_DA4 = 11, + MX51_PAD_EIM_DA5 = 12, + MX51_PAD_EIM_DA6 = 13, + MX51_PAD_EIM_DA7 = 14, + MX51_PAD_EIM_DA8 = 15, + MX51_PAD_EIM_DA9 = 16, + MX51_PAD_EIM_DA10 = 17, + MX51_PAD_EIM_DA11 = 18, + MX51_PAD_EIM_DA12 = 19, + MX51_PAD_EIM_DA13 = 20, + MX51_PAD_EIM_DA14 = 21, + MX51_PAD_EIM_DA15 = 22, + MX51_PAD_EIM_D16 = 23, + MX51_PAD_EIM_D17 = 24, + MX51_PAD_EIM_D18 = 25, + MX51_PAD_EIM_D19 = 26, + MX51_PAD_EIM_D20 = 27, + MX51_PAD_EIM_D21 = 28, + MX51_PAD_EIM_D22 = 29, + MX51_PAD_EIM_D23 = 30, + MX51_PAD_EIM_D24 = 31, + MX51_PAD_EIM_D25 = 32, + MX51_PAD_EIM_D26 = 33, + MX51_PAD_EIM_D27 = 34, + MX51_PAD_EIM_D28 = 35, + MX51_PAD_EIM_D29 = 36, + MX51_PAD_EIM_D30 = 37, + MX51_PAD_EIM_D31 = 38, + MX51_PAD_EIM_A16 = 39, + MX51_PAD_EIM_A17 = 40, + MX51_PAD_EIM_A18 = 41, + MX51_PAD_EIM_A19 = 42, + MX51_PAD_EIM_A20 = 43, + MX51_PAD_EIM_A21 = 44, + MX51_PAD_EIM_A22 = 45, + MX51_PAD_EIM_A23 = 46, + MX51_PAD_EIM_A24 = 47, + MX51_PAD_EIM_A25 = 48, + MX51_PAD_EIM_A26 = 49, + MX51_PAD_EIM_A27 = 50, + MX51_PAD_EIM_EB0 = 51, + MX51_PAD_EIM_EB1 = 52, + MX51_PAD_EIM_EB2 = 53, + MX51_PAD_EIM_EB3 = 54, + MX51_PAD_EIM_OE = 55, + MX51_PAD_EIM_CS0 = 56, + MX51_PAD_EIM_CS1 = 57, + MX51_PAD_EIM_CS2 = 58, + MX51_PAD_EIM_CS3 = 59, + MX51_PAD_EIM_CS4 = 60, + MX51_PAD_EIM_CS5 = 61, + MX51_PAD_EIM_DTACK = 62, + MX51_PAD_EIM_LBA = 63, + MX51_PAD_EIM_CRE = 64, + MX51_PAD_DRAM_CS1 = 65, + MX51_PAD_NANDF_WE_B = 66, + MX51_PAD_NANDF_RE_B = 67, + MX51_PAD_NANDF_ALE = 68, + MX51_PAD_NANDF_CLE = 69, + MX51_PAD_NANDF_WP_B = 70, + MX51_PAD_NANDF_RB0 = 71, + MX51_PAD_NANDF_RB1 = 72, + MX51_PAD_NANDF_RB2 = 73, + MX51_PAD_NANDF_RB3 = 74, + MX51_PAD_GPIO_NAND = 75, + MX51_PAD_NANDF_CS0 = 76, + MX51_PAD_NANDF_CS1 = 77, + MX51_PAD_NANDF_CS2 = 78, + MX51_PAD_NANDF_CS3 = 79, + MX51_PAD_NANDF_CS4 = 80, + MX51_PAD_NANDF_CS5 = 81, + MX51_PAD_NANDF_CS6 = 82, + MX51_PAD_NANDF_CS7 = 83, + MX51_PAD_NANDF_RDY_INT = 84, + MX51_PAD_NANDF_D15 = 85, + MX51_PAD_NANDF_D14 = 86, + MX51_PAD_NANDF_D13 = 87, + MX51_PAD_NANDF_D12 = 88, + MX51_PAD_NANDF_D11 = 89, + MX51_PAD_NANDF_D10 = 90, + MX51_PAD_NANDF_D9 = 91, + MX51_PAD_NANDF_D8 = 92, + MX51_PAD_NANDF_D7 = 93, + MX51_PAD_NANDF_D6 = 94, + MX51_PAD_NANDF_D5 = 95, + MX51_PAD_NANDF_D4 = 96, + MX51_PAD_NANDF_D3 = 97, + MX51_PAD_NANDF_D2 = 98, + MX51_PAD_NANDF_D1 = 99, + MX51_PAD_NANDF_D0 = 100, + MX51_PAD_CSI1_D8 = 101, + MX51_PAD_CSI1_D9 = 102, + MX51_PAD_CSI1_D10 = 103, + MX51_PAD_CSI1_D11 = 104, + MX51_PAD_CSI1_D12 = 105, + MX51_PAD_CSI1_D13 = 106, + MX51_PAD_CSI1_D14 = 107, + MX51_PAD_CSI1_D15 = 108, + MX51_PAD_CSI1_D16 = 109, + MX51_PAD_CSI1_D17 = 110, + MX51_PAD_CSI1_D18 = 111, + MX51_PAD_CSI1_D19 = 112, + MX51_PAD_CSI1_VSYNC = 113, + MX51_PAD_CSI1_HSYNC = 114, + MX51_PAD_CSI2_D12 = 115, + MX51_PAD_CSI2_D13 = 116, + MX51_PAD_CSI2_D14 = 117, + MX51_PAD_CSI2_D15 = 118, + MX51_PAD_CSI2_D16 = 119, + MX51_PAD_CSI2_D17 = 120, + MX51_PAD_CSI2_D18 = 121, + MX51_PAD_CSI2_D19 = 122, + MX51_PAD_CSI2_VSYNC = 123, + MX51_PAD_CSI2_HSYNC = 124, + MX51_PAD_CSI2_PIXCLK = 125, + MX51_PAD_I2C1_CLK = 126, + MX51_PAD_I2C1_DAT = 127, + MX51_PAD_AUD3_BB_TXD = 128, + MX51_PAD_AUD3_BB_RXD = 129, + MX51_PAD_AUD3_BB_CK = 130, + MX51_PAD_AUD3_BB_FS = 131, + MX51_PAD_CSPI1_MOSI = 132, + MX51_PAD_CSPI1_MISO = 133, + MX51_PAD_CSPI1_SS0 = 134, + MX51_PAD_CSPI1_SS1 = 135, + MX51_PAD_CSPI1_RDY = 136, + MX51_PAD_CSPI1_SCLK = 137, + MX51_PAD_UART1_RXD = 138, + MX51_PAD_UART1_TXD = 139, + MX51_PAD_UART1_RTS = 140, + MX51_PAD_UART1_CTS = 141, + MX51_PAD_UART2_RXD = 142, + MX51_PAD_UART2_TXD = 143, + MX51_PAD_UART3_RXD = 144, + MX51_PAD_UART3_TXD = 145, + MX51_PAD_OWIRE_LINE = 146, + MX51_PAD_KEY_ROW0 = 147, + MX51_PAD_KEY_ROW1 = 148, + MX51_PAD_KEY_ROW2 = 149, + MX51_PAD_KEY_ROW3 = 150, + MX51_PAD_KEY_COL0 = 151, + MX51_PAD_KEY_COL1 = 152, + MX51_PAD_KEY_COL2 = 153, + MX51_PAD_KEY_COL3 = 154, + MX51_PAD_KEY_COL4 = 155, + MX51_PAD_KEY_COL5 = 156, + MX51_PAD_RESERVE7 = 157, + MX51_PAD_USBH1_CLK = 158, + MX51_PAD_USBH1_DIR = 159, + MX51_PAD_USBH1_STP = 160, + MX51_PAD_USBH1_NXT = 161, + MX51_PAD_USBH1_DATA0 = 162, + MX51_PAD_USBH1_DATA1 = 163, + MX51_PAD_USBH1_DATA2 = 164, + MX51_PAD_USBH1_DATA3 = 165, + MX51_PAD_USBH1_DATA4 = 166, + MX51_PAD_USBH1_DATA5 = 167, + MX51_PAD_USBH1_DATA6 = 168, + MX51_PAD_USBH1_DATA7 = 169, + MX51_PAD_DI1_PIN11 = 170, + MX51_PAD_DI1_PIN12 = 171, + MX51_PAD_DI1_PIN13 = 172, + MX51_PAD_DI1_D0_CS = 173, + MX51_PAD_DI1_D1_CS = 174, + MX51_PAD_DISPB2_SER_DIN = 175, + MX51_PAD_DISPB2_SER_DIO = 176, + MX51_PAD_DISPB2_SER_CLK = 177, + MX51_PAD_DISPB2_SER_RS = 178, + MX51_PAD_DISP1_DAT0 = 179, + MX51_PAD_DISP1_DAT1 = 180, + MX51_PAD_DISP1_DAT2 = 181, + MX51_PAD_DISP1_DAT3 = 182, + MX51_PAD_DISP1_DAT4 = 183, + MX51_PAD_DISP1_DAT5 = 184, + MX51_PAD_DISP1_DAT6 = 185, + MX51_PAD_DISP1_DAT7 = 186, + MX51_PAD_DISP1_DAT8 = 187, + MX51_PAD_DISP1_DAT9 = 188, + MX51_PAD_DISP1_DAT10 = 189, + MX51_PAD_DISP1_DAT11 = 190, + MX51_PAD_DISP1_DAT12 = 191, + MX51_PAD_DISP1_DAT13 = 192, + MX51_PAD_DISP1_DAT14 = 193, + MX51_PAD_DISP1_DAT15 = 194, + MX51_PAD_DISP1_DAT16 = 195, + MX51_PAD_DISP1_DAT17 = 196, + MX51_PAD_DISP1_DAT18 = 197, + MX51_PAD_DISP1_DAT19 = 198, + MX51_PAD_DISP1_DAT20 = 199, + MX51_PAD_DISP1_DAT21 = 200, + MX51_PAD_DISP1_DAT22 = 201, + MX51_PAD_DISP1_DAT23 = 202, + MX51_PAD_DI1_PIN3 = 203, + MX51_PAD_DI1_PIN2 = 204, + MX51_PAD_RESERVE8 = 205, + MX51_PAD_DI_GP2 = 206, + MX51_PAD_DI_GP3 = 207, + MX51_PAD_DI2_PIN4 = 208, + MX51_PAD_DI2_PIN2 = 209, + MX51_PAD_DI2_PIN3 = 210, + MX51_PAD_DI2_DISP_CLK = 211, + MX51_PAD_DI_GP4 = 212, + MX51_PAD_DISP2_DAT0 = 213, + MX51_PAD_DISP2_DAT1 = 214, + MX51_PAD_DISP2_DAT2 = 215, + MX51_PAD_DISP2_DAT3 = 216, + MX51_PAD_DISP2_DAT4 = 217, + MX51_PAD_DISP2_DAT5 = 218, + MX51_PAD_DISP2_DAT6 = 219, + MX51_PAD_DISP2_DAT7 = 220, + MX51_PAD_DISP2_DAT8 = 221, + MX51_PAD_DISP2_DAT9 = 222, + MX51_PAD_DISP2_DAT10 = 223, + MX51_PAD_DISP2_DAT11 = 224, + MX51_PAD_DISP2_DAT12 = 225, + MX51_PAD_DISP2_DAT13 = 226, + MX51_PAD_DISP2_DAT14 = 227, + MX51_PAD_DISP2_DAT15 = 228, + MX51_PAD_SD1_CMD = 229, + MX51_PAD_SD1_CLK = 230, + MX51_PAD_SD1_DATA0 = 231, + MX51_PAD_SD1_DATA1 = 232, + MX51_PAD_SD1_DATA2 = 233, + MX51_PAD_SD1_DATA3 = 234, + MX51_PAD_GPIO1_0 = 235, + MX51_PAD_GPIO1_1 = 236, + MX51_PAD_SD2_CMD = 237, + MX51_PAD_SD2_CLK = 238, + MX51_PAD_SD2_DATA0 = 239, + MX51_PAD_SD2_DATA1 = 240, + MX51_PAD_SD2_DATA2 = 241, + MX51_PAD_SD2_DATA3 = 242, + MX51_PAD_GPIO1_2 = 243, + MX51_PAD_GPIO1_3 = 244, + MX51_PAD_PMIC_INT_REQ = 245, + MX51_PAD_GPIO1_4 = 246, + MX51_PAD_GPIO1_5 = 247, + MX51_PAD_GPIO1_6 = 248, + MX51_PAD_GPIO1_7 = 249, + MX51_PAD_GPIO1_8 = 250, + MX51_PAD_GPIO1_9 = 251, + MX51_PAD_RESERVE9 = 252, + MX51_PAD_RESERVE10 = 253, + MX51_PAD_RESERVE11 = 254, + MX51_PAD_RESERVE12 = 255, + MX51_PAD_RESERVE13 = 256, + MX51_PAD_RESERVE14 = 257, + MX51_PAD_RESERVE15 = 258, + MX51_PAD_RESERVE16 = 259, + MX51_PAD_RESERVE17 = 260, + MX51_PAD_RESERVE18 = 261, + MX51_PAD_RESERVE19 = 262, + MX51_PAD_RESERVE20 = 263, + MX51_PAD_RESERVE21 = 264, + MX51_PAD_RESERVE22 = 265, + MX51_PAD_RESERVE23 = 266, + MX51_PAD_RESERVE24 = 267, + MX51_PAD_RESERVE25 = 268, + MX51_PAD_RESERVE26 = 269, + MX51_PAD_RESERVE27 = 270, + MX51_PAD_RESERVE28 = 271, + MX51_PAD_RESERVE29 = 272, + MX51_PAD_RESERVE30 = 273, + MX51_PAD_RESERVE31 = 274, + MX51_PAD_RESERVE32 = 275, + MX51_PAD_RESERVE33 = 276, + MX51_PAD_RESERVE34 = 277, + MX51_PAD_RESERVE35 = 278, + MX51_PAD_RESERVE36 = 279, + MX51_PAD_RESERVE37 = 280, + MX51_PAD_RESERVE38 = 281, + MX51_PAD_RESERVE39 = 282, + MX51_PAD_RESERVE40 = 283, + MX51_PAD_RESERVE41 = 284, + MX51_PAD_RESERVE42 = 285, + MX51_PAD_RESERVE43 = 286, + MX51_PAD_RESERVE44 = 287, + MX51_PAD_RESERVE45 = 288, + MX51_PAD_RESERVE46 = 289, + MX51_PAD_RESERVE47 = 290, + MX51_PAD_RESERVE48 = 291, + MX51_PAD_RESERVE49 = 292, + MX51_PAD_RESERVE50 = 293, + MX51_PAD_RESERVE51 = 294, + MX51_PAD_RESERVE52 = 295, + MX51_PAD_RESERVE53 = 296, + MX51_PAD_RESERVE54 = 297, + MX51_PAD_RESERVE55 = 298, + MX51_PAD_RESERVE56 = 299, + MX51_PAD_RESERVE57 = 300, + MX51_PAD_RESERVE58 = 301, + MX51_PAD_RESERVE59 = 302, + MX51_PAD_RESERVE60 = 303, + MX51_PAD_RESERVE61 = 304, + MX51_PAD_RESERVE62 = 305, + MX51_PAD_RESERVE63 = 306, + MX51_PAD_RESERVE64 = 307, + MX51_PAD_RESERVE65 = 308, + MX51_PAD_RESERVE66 = 309, + MX51_PAD_RESERVE67 = 310, + MX51_PAD_RESERVE68 = 311, + MX51_PAD_RESERVE69 = 312, + MX51_PAD_RESERVE70 = 313, + MX51_PAD_RESERVE71 = 314, + MX51_PAD_RESERVE72 = 315, + MX51_PAD_RESERVE73 = 316, + MX51_PAD_RESERVE74 = 317, + MX51_PAD_RESERVE75 = 318, + MX51_PAD_RESERVE76 = 319, + MX51_PAD_RESERVE77 = 320, + MX51_PAD_RESERVE78 = 321, + MX51_PAD_RESERVE79 = 322, + MX51_PAD_RESERVE80 = 323, + MX51_PAD_RESERVE81 = 324, + MX51_PAD_RESERVE82 = 325, + MX51_PAD_RESERVE83 = 326, + MX51_PAD_RESERVE84 = 327, + MX51_PAD_RESERVE85 = 328, + MX51_PAD_RESERVE86 = 329, + MX51_PAD_RESERVE87 = 330, + MX51_PAD_RESERVE88 = 331, + MX51_PAD_RESERVE89 = 332, + MX51_PAD_RESERVE90 = 333, + MX51_PAD_RESERVE91 = 334, + MX51_PAD_RESERVE92 = 335, + MX51_PAD_RESERVE93 = 336, + MX51_PAD_RESERVE94 = 337, + MX51_PAD_RESERVE95 = 338, + MX51_PAD_RESERVE96 = 339, + MX51_PAD_RESERVE97 = 340, + MX51_PAD_RESERVE98 = 341, + MX51_PAD_RESERVE99 = 342, + MX51_PAD_RESERVE100 = 343, + MX51_PAD_RESERVE101 = 344, + MX51_PAD_RESERVE102 = 345, + MX51_PAD_RESERVE103 = 346, + MX51_PAD_RESERVE104 = 347, + MX51_PAD_RESERVE105 = 348, + MX51_PAD_RESERVE106 = 349, + MX51_PAD_RESERVE107 = 350, + MX51_PAD_RESERVE108 = 351, + MX51_PAD_RESERVE109 = 352, + MX51_PAD_RESERVE110 = 353, + MX51_PAD_RESERVE111 = 354, + MX51_PAD_RESERVE112 = 355, + MX51_PAD_RESERVE113 = 356, + MX51_PAD_RESERVE114 = 357, + MX51_PAD_RESERVE115 = 358, + MX51_PAD_RESERVE116 = 359, + MX51_PAD_RESERVE117 = 360, + MX51_PAD_RESERVE118 = 361, + MX51_PAD_RESERVE119 = 362, + MX51_PAD_RESERVE120 = 363, + MX51_PAD_RESERVE121 = 364, + MX51_PAD_CSI1_PIXCLK = 365, + MX51_PAD_CSI1_MCLK = 366, }; /* Pad names for the pinmux subsystem */ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX51_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14), + IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15), IMX_PINCTRL_PIN(MX51_PAD_EIM_D16), IMX_PINCTRL_PIN(MX51_PAD_EIM_D17), IMX_PINCTRL_PIN(MX51_PAD_EIM_D18), @@ -1124,8 +509,6 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19), IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC), IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK), - IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK), IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12), IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13), IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14), @@ -1168,6 +551,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3), IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4), IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE7), IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK), IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR), IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP), @@ -1215,6 +599,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23), IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3), IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE8), IMX_PINCTRL_PIN(MX51_PAD_DI_GP2), IMX_PINCTRL_PIN(MX51_PAD_DI_GP3), IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4), @@ -1241,27 +626,11 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD), IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK), IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3), IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7), IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9), IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3), IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0), IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14), - IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15), IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD), IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK), IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0), @@ -1277,13 +646,126 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7), IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8), IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE18), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE19), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE20), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE21), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE22), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE23), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE24), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE25), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE26), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE27), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE28), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE29), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE30), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE31), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE32), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE33), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE34), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE35), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE36), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE37), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE38), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE39), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE40), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE41), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE42), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE43), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE44), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE45), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE46), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE47), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE48), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE49), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE50), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE51), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE52), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE53), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE54), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE55), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE56), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE57), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE58), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE59), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE60), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE61), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE62), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE63), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE64), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE65), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE66), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE67), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE68), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE69), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE70), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE71), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE72), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE73), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE74), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE75), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE76), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE77), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE78), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE79), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE80), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE81), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE82), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE83), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE84), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE85), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE86), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE87), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE88), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE89), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE90), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE91), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE92), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE93), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE94), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE95), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE96), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE97), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE98), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE99), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE100), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE101), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE102), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE103), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE104), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE105), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE106), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE107), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE108), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE109), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE110), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE111), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE112), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE113), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE114), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE115), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE116), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE117), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE118), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE119), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE120), + IMX_PINCTRL_PIN(MX51_PAD_RESERVE121), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK), + IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK), }; static struct imx_pinctrl_soc_info imx51_pinctrl_info = { .pins = imx51_pinctrl_pads, .npins = ARRAY_SIZE(imx51_pinctrl_pads), - .pin_regs = imx51_pin_regs, - .npin_regs = ARRAY_SIZE(imx51_pin_regs), }; static struct of_device_id imx51_pinctrl_of_match[] = { @@ -1300,7 +782,7 @@ static struct platform_driver imx51_pinctrl_driver = { .driver = { .name = "imx51-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx51_pinctrl_of_match), + .of_match_table = imx51_pinctrl_of_match, }, .probe = imx51_pinctrl_probe, .remove = imx_pinctrl_remove, diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c index 2c9c8e2334d..f8d45c4cfde 100644 --- a/drivers/pinctrl/pinctrl-imx53.c +++ b/drivers/pinctrl/pinctrl-imx53.c @@ -23,1386 +23,228 @@ #include "pinctrl-imx.h" enum imx53_pads { - MX53_PAD_GPIO_19 = 0, - MX53_PAD_KEY_COL0 = 1, - MX53_PAD_KEY_ROW0 = 2, - MX53_PAD_KEY_COL1 = 3, - MX53_PAD_KEY_ROW1 = 4, - MX53_PAD_KEY_COL2 = 5, - MX53_PAD_KEY_ROW2 = 6, - MX53_PAD_KEY_COL3 = 7, - MX53_PAD_KEY_ROW3 = 8, - MX53_PAD_KEY_COL4 = 9, - MX53_PAD_KEY_ROW4 = 10, - MX53_PAD_DI0_DISP_CLK = 11, - MX53_PAD_DI0_PIN15 = 12, - MX53_PAD_DI0_PIN2 = 13, - MX53_PAD_DI0_PIN3 = 14, - MX53_PAD_DI0_PIN4 = 15, - MX53_PAD_DISP0_DAT0 = 16, - MX53_PAD_DISP0_DAT1 = 17, - MX53_PAD_DISP0_DAT2 = 18, - MX53_PAD_DISP0_DAT3 = 19, - MX53_PAD_DISP0_DAT4 = 20, - MX53_PAD_DISP0_DAT5 = 21, - MX53_PAD_DISP0_DAT6 = 22, - MX53_PAD_DISP0_DAT7 = 23, - MX53_PAD_DISP0_DAT8 = 24, - MX53_PAD_DISP0_DAT9 = 25, - MX53_PAD_DISP0_DAT10 = 26, - MX53_PAD_DISP0_DAT11 = 27, - MX53_PAD_DISP0_DAT12 = 28, - MX53_PAD_DISP0_DAT13 = 29, - MX53_PAD_DISP0_DAT14 = 30, - MX53_PAD_DISP0_DAT15 = 31, - MX53_PAD_DISP0_DAT16 = 32, - MX53_PAD_DISP0_DAT17 = 33, - MX53_PAD_DISP0_DAT18 = 34, - MX53_PAD_DISP0_DAT19 = 35, - MX53_PAD_DISP0_DAT20 = 36, - MX53_PAD_DISP0_DAT21 = 37, - MX53_PAD_DISP0_DAT22 = 38, - MX53_PAD_DISP0_DAT23 = 39, - MX53_PAD_CSI0_PIXCLK = 40, - MX53_PAD_CSI0_MCLK = 41, - MX53_PAD_CSI0_DATA_EN = 42, - MX53_PAD_CSI0_VSYNC = 43, - MX53_PAD_CSI0_DAT4 = 44, - MX53_PAD_CSI0_DAT5 = 45, - MX53_PAD_CSI0_DAT6 = 46, - MX53_PAD_CSI0_DAT7 = 47, - MX53_PAD_CSI0_DAT8 = 48, - MX53_PAD_CSI0_DAT9 = 49, - MX53_PAD_CSI0_DAT10 = 50, - MX53_PAD_CSI0_DAT11 = 51, - MX53_PAD_CSI0_DAT12 = 52, - MX53_PAD_CSI0_DAT13 = 53, - MX53_PAD_CSI0_DAT14 = 54, - MX53_PAD_CSI0_DAT15 = 55, - MX53_PAD_CSI0_DAT16 = 56, - MX53_PAD_CSI0_DAT17 = 57, - MX53_PAD_CSI0_DAT18 = 58, - MX53_PAD_CSI0_DAT19 = 59, - MX53_PAD_EIM_A25 = 60, - MX53_PAD_EIM_EB2 = 61, - MX53_PAD_EIM_D16 = 62, - MX53_PAD_EIM_D17 = 63, - MX53_PAD_EIM_D18 = 64, - MX53_PAD_EIM_D19 = 65, - MX53_PAD_EIM_D20 = 66, - MX53_PAD_EIM_D21 = 67, - MX53_PAD_EIM_D22 = 68, - MX53_PAD_EIM_D23 = 69, - MX53_PAD_EIM_EB3 = 70, - MX53_PAD_EIM_D24 = 71, - MX53_PAD_EIM_D25 = 72, - MX53_PAD_EIM_D26 = 73, - MX53_PAD_EIM_D27 = 74, - MX53_PAD_EIM_D28 = 75, - MX53_PAD_EIM_D29 = 76, - MX53_PAD_EIM_D30 = 77, - MX53_PAD_EIM_D31 = 78, - MX53_PAD_EIM_A24 = 79, - MX53_PAD_EIM_A23 = 80, - MX53_PAD_EIM_A22 = 81, - MX53_PAD_EIM_A21 = 82, - MX53_PAD_EIM_A20 = 83, - MX53_PAD_EIM_A19 = 84, - MX53_PAD_EIM_A18 = 85, - MX53_PAD_EIM_A17 = 86, - MX53_PAD_EIM_A16 = 87, - MX53_PAD_EIM_CS0 = 88, - MX53_PAD_EIM_CS1 = 89, - MX53_PAD_EIM_OE = 90, - MX53_PAD_EIM_RW = 91, - MX53_PAD_EIM_LBA = 92, - MX53_PAD_EIM_EB0 = 93, - MX53_PAD_EIM_EB1 = 94, - MX53_PAD_EIM_DA0 = 95, - MX53_PAD_EIM_DA1 = 96, - MX53_PAD_EIM_DA2 = 97, - MX53_PAD_EIM_DA3 = 98, - MX53_PAD_EIM_DA4 = 99, - MX53_PAD_EIM_DA5 = 100, - MX53_PAD_EIM_DA6 = 101, - MX53_PAD_EIM_DA7 = 102, - MX53_PAD_EIM_DA8 = 103, - MX53_PAD_EIM_DA9 = 104, - MX53_PAD_EIM_DA10 = 105, - MX53_PAD_EIM_DA11 = 106, - MX53_PAD_EIM_DA12 = 107, - MX53_PAD_EIM_DA13 = 108, - MX53_PAD_EIM_DA14 = 109, - MX53_PAD_EIM_DA15 = 110, - MX53_PAD_NANDF_WE_B = 111, - MX53_PAD_NANDF_RE_B = 112, - MX53_PAD_EIM_WAIT = 113, - MX53_PAD_LVDS1_TX3_P = 114, - MX53_PAD_LVDS1_TX2_P = 115, - MX53_PAD_LVDS1_CLK_P = 116, - MX53_PAD_LVDS1_TX1_P = 117, - MX53_PAD_LVDS1_TX0_P = 118, - MX53_PAD_LVDS0_TX3_P = 119, - MX53_PAD_LVDS0_CLK_P = 120, - MX53_PAD_LVDS0_TX2_P = 121, - MX53_PAD_LVDS0_TX1_P = 122, - MX53_PAD_LVDS0_TX0_P = 123, - MX53_PAD_GPIO_10 = 124, - MX53_PAD_GPIO_11 = 125, - MX53_PAD_GPIO_12 = 126, - MX53_PAD_GPIO_13 = 127, - MX53_PAD_GPIO_14 = 128, - MX53_PAD_NANDF_CLE = 129, - MX53_PAD_NANDF_ALE = 130, - MX53_PAD_NANDF_WP_B = 131, - MX53_PAD_NANDF_RB0 = 132, - MX53_PAD_NANDF_CS0 = 133, - MX53_PAD_NANDF_CS1 = 134, - MX53_PAD_NANDF_CS2 = 135, - MX53_PAD_NANDF_CS3 = 136, - MX53_PAD_FEC_MDIO = 137, - MX53_PAD_FEC_REF_CLK = 138, - MX53_PAD_FEC_RX_ER = 139, - MX53_PAD_FEC_CRS_DV = 140, - MX53_PAD_FEC_RXD1 = 141, - MX53_PAD_FEC_RXD0 = 142, - MX53_PAD_FEC_TX_EN = 143, - MX53_PAD_FEC_TXD1 = 144, - MX53_PAD_FEC_TXD0 = 145, - MX53_PAD_FEC_MDC = 146, - MX53_PAD_PATA_DIOW = 147, - MX53_PAD_PATA_DMACK = 148, - MX53_PAD_PATA_DMARQ = 149, - MX53_PAD_PATA_BUFFER_EN = 150, - MX53_PAD_PATA_INTRQ = 151, - MX53_PAD_PATA_DIOR = 152, - MX53_PAD_PATA_RESET_B = 153, - MX53_PAD_PATA_IORDY = 154, - MX53_PAD_PATA_DA_0 = 155, - MX53_PAD_PATA_DA_1 = 156, - MX53_PAD_PATA_DA_2 = 157, - MX53_PAD_PATA_CS_0 = 158, - MX53_PAD_PATA_CS_1 = 159, - MX53_PAD_PATA_DATA0 = 160, - MX53_PAD_PATA_DATA1 = 161, - MX53_PAD_PATA_DATA2 = 162, - MX53_PAD_PATA_DATA3 = 163, - MX53_PAD_PATA_DATA4 = 164, - MX53_PAD_PATA_DATA5 = 165, - MX53_PAD_PATA_DATA6 = 166, - MX53_PAD_PATA_DATA7 = 167, - MX53_PAD_PATA_DATA8 = 168, - MX53_PAD_PATA_DATA9 = 169, - MX53_PAD_PATA_DATA10 = 170, - MX53_PAD_PATA_DATA11 = 171, - MX53_PAD_PATA_DATA12 = 172, - MX53_PAD_PATA_DATA13 = 173, - MX53_PAD_PATA_DATA14 = 174, - MX53_PAD_PATA_DATA15 = 175, - MX53_PAD_SD1_DATA0 = 176, - MX53_PAD_SD1_DATA1 = 177, - MX53_PAD_SD1_CMD = 178, - MX53_PAD_SD1_DATA2 = 179, - MX53_PAD_SD1_CLK = 180, - MX53_PAD_SD1_DATA3 = 181, - MX53_PAD_SD2_CLK = 182, - MX53_PAD_SD2_CMD = 183, - MX53_PAD_SD2_DATA3 = 184, - MX53_PAD_SD2_DATA2 = 185, - MX53_PAD_SD2_DATA1 = 186, - MX53_PAD_SD2_DATA0 = 187, - MX53_PAD_GPIO_0 = 188, - MX53_PAD_GPIO_1 = 189, - MX53_PAD_GPIO_9 = 190, - MX53_PAD_GPIO_3 = 191, - MX53_PAD_GPIO_6 = 192, - MX53_PAD_GPIO_2 = 193, - MX53_PAD_GPIO_4 = 194, - MX53_PAD_GPIO_5 = 195, - MX53_PAD_GPIO_7 = 196, - MX53_PAD_GPIO_8 = 197, - MX53_PAD_GPIO_16 = 198, - MX53_PAD_GPIO_17 = 199, - MX53_PAD_GPIO_18 = 200, -}; - -/* imx53 register maps */ -static struct imx_pin_reg imx53_pin_regs[] = { - IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 0, 0x840, 0), /* MX53_PAD_GPIO_19__KPP_COL_5 */ - IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 1, 0x000, 0), /* MX53_PAD_GPIO_19__GPIO4_5 */ - IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 2, 0x000, 0), /* MX53_PAD_GPIO_19__CCM_CLKO */ - IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 3, 0x000, 0), /* MX53_PAD_GPIO_19__SPDIF_OUT1 */ - IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 4, 0x000, 0), /* MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 */ - IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 5, 0x000, 0), /* MX53_PAD_GPIO_19__ECSPI1_RDY */ - IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 6, 0x000, 0), /* MX53_PAD_GPIO_19__FEC_TDATA_3 */ - IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 7, 0x000, 0), /* MX53_PAD_GPIO_19__SRC_INT_BOOT */ - IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 0, 0x000, 0), /* MX53_PAD_KEY_COL0__KPP_COL_0 */ - IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 1, 0x000, 0), /* MX53_PAD_KEY_COL0__GPIO4_6 */ - IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 2, 0x758, 0), /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ - IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 4, 0x000, 0), /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 5, 0x79C, 0), /* MX53_PAD_KEY_COL0__ECSPI1_SCLK */ - IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 6, 0x000, 0), /* MX53_PAD_KEY_COL0__FEC_RDATA_3 */ - IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 7, 0x000, 0), /* MX53_PAD_KEY_COL0__SRC_ANY_PU_RST */ - IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 0, 0x000, 0), /* MX53_PAD_KEY_ROW0__KPP_ROW_0 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 1, 0x000, 0), /* MX53_PAD_KEY_ROW0__GPIO4_7 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 2, 0x74C, 0), /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ - IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 4, 0x890, 1), /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 5, 0x7A4, 0), /* MX53_PAD_KEY_ROW0__ECSPI1_MOSI */ - IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 6, 0x000, 0), /* MX53_PAD_KEY_ROW0__FEC_TX_ER */ - IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 0, 0x000, 0), /* MX53_PAD_KEY_COL1__KPP_COL_1 */ - IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 1, 0x000, 0), /* MX53_PAD_KEY_COL1__GPIO4_8 */ - IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 2, 0x75C, 0), /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ - IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 4, 0x000, 0), /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 5, 0x7A0, 0), /* MX53_PAD_KEY_COL1__ECSPI1_MISO */ - IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 6, 0x808, 0), /* MX53_PAD_KEY_COL1__FEC_RX_CLK */ - IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 7, 0x000, 0), /* MX53_PAD_KEY_COL1__USBPHY1_TXREADY */ - IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 0, 0x000, 0), /* MX53_PAD_KEY_ROW1__KPP_ROW_1 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 1, 0x000, 0), /* MX53_PAD_KEY_ROW1__GPIO4_9 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 2, 0x748, 0), /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ - IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 4, 0x898, 1), /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 5, 0x7A8, 0), /* MX53_PAD_KEY_ROW1__ECSPI1_SS0 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 6, 0x800, 0), /* MX53_PAD_KEY_ROW1__FEC_COL */ - IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 7, 0x000, 0), /* MX53_PAD_KEY_ROW1__USBPHY1_RXVALID */ - IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 0, 0x000, 0), /* MX53_PAD_KEY_COL2__KPP_COL_2 */ - IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 1, 0x000, 0), /* MX53_PAD_KEY_COL2__GPIO4_10 */ - IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 2, 0x000, 0), /* MX53_PAD_KEY_COL2__CAN1_TXCAN */ - IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 4, 0x804, 0), /* MX53_PAD_KEY_COL2__FEC_MDIO */ - IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 5, 0x7AC, 0), /* MX53_PAD_KEY_COL2__ECSPI1_SS1 */ - IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 6, 0x000, 0), /* MX53_PAD_KEY_COL2__FEC_RDATA_2 */ - IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 7, 0x000, 0), /* MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE */ - IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 0, 0x000, 0), /* MX53_PAD_KEY_ROW2__KPP_ROW_2 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 1, 0x000, 0), /* MX53_PAD_KEY_ROW2__GPIO4_11 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 2, 0x760, 0), /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */ - IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 4, 0x000, 0), /* MX53_PAD_KEY_ROW2__FEC_MDC */ - IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 5, 0x7B0, 0), /* MX53_PAD_KEY_ROW2__ECSPI1_SS2 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 6, 0x000, 0), /* MX53_PAD_KEY_ROW2__FEC_TDATA_2 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 7, 0x000, 0), /* MX53_PAD_KEY_ROW2__USBPHY1_RXERROR */ - IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 0, 0x000, 0), /* MX53_PAD_KEY_COL3__KPP_COL_3 */ - IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 1, 0x000, 0), /* MX53_PAD_KEY_COL3__GPIO4_12 */ - IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 2, 0x000, 0), /* MX53_PAD_KEY_COL3__USBOH3_H2_DP */ - IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 3, 0x870, 0), /* MX53_PAD_KEY_COL3__SPDIF_IN1 */ - IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 4, 0x81C, 0), /* MX53_PAD_KEY_COL3__I2C2_SCL */ - IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 5, 0x7B4, 0), /* MX53_PAD_KEY_COL3__ECSPI1_SS3 */ - IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 6, 0x000, 0), /* MX53_PAD_KEY_COL3__FEC_CRS */ - IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 7, 0x000, 0), /* MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK */ - IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 0, 0x000, 0), /* MX53_PAD_KEY_ROW3__KPP_ROW_3 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 1, 0x000, 0), /* MX53_PAD_KEY_ROW3__GPIO4_13 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 2, 0x000, 0), /* MX53_PAD_KEY_ROW3__USBOH3_H2_DM */ - IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 3, 0x768, 0), /* MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK */ - IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 4, 0x820, 0), /* MX53_PAD_KEY_ROW3__I2C2_SDA */ - IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 5, 0x000, 0), /* MX53_PAD_KEY_ROW3__OSC32K_32K_OUT */ - IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 6, 0x77C, 0), /* MX53_PAD_KEY_ROW3__CCM_PLL4_BYP */ - IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 7, 0x000, 0), /* MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 */ - IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 0, 0x000, 0), /* MX53_PAD_KEY_COL4__KPP_COL_4 */ - IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 1, 0x000, 0), /* MX53_PAD_KEY_COL4__GPIO4_14 */ - IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 2, 0x000, 0), /* MX53_PAD_KEY_COL4__CAN2_TXCAN */ - IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 3, 0x000, 0), /* MX53_PAD_KEY_COL4__IPU_SISG_4 */ - IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 4, 0x894, 0), /* MX53_PAD_KEY_COL4__UART5_RTS */ - IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 5, 0x89C, 0), /* MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC */ - IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 7, 0x000, 0), /* MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 0, 0x000, 0), /* MX53_PAD_KEY_ROW4__KPP_ROW_4 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 1, 0x000, 0), /* MX53_PAD_KEY_ROW4__GPIO4_15 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 2, 0x764, 0), /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */ - IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 3, 0x000, 0), /* MX53_PAD_KEY_ROW4__IPU_SISG_5 */ - IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 4, 0x000, 0), /* MX53_PAD_KEY_ROW4__UART5_CTS */ - IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 5, 0x000, 0), /* MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */ - IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 7, 0x000, 0), /* MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID */ - IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 0, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK */ - IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 1, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__GPIO4_16 */ - IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 2, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR */ - IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 5, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 */ - IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 6, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 */ - IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 7, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID */ - IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 0, 0x000, 0), /* MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 1, 0x000, 0), /* MX53_PAD_DI0_PIN15__GPIO4_17 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 2, 0x000, 0), /* MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */ - IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 5, 0x000, 0), /* MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 6, 0x000, 0), /* MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 7, 0x000, 0), /* MX53_PAD_DI0_PIN15__USBPHY1_BVALID */ - IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 0, 0x000, 0), /* MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 1, 0x000, 0), /* MX53_PAD_DI0_PIN2__GPIO4_18 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 2, 0x000, 0), /* MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */ - IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 5, 0x000, 0), /* MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 6, 0x000, 0), /* MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 7, 0x000, 0), /* MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION */ - IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 0, 0x000, 0), /* MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 1, 0x000, 0), /* MX53_PAD_DI0_PIN3__GPIO4_19 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 2, 0x000, 0), /* MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */ - IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 5, 0x000, 0), /* MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 6, 0x000, 0), /* MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 7, 0x000, 0), /* MX53_PAD_DI0_PIN3__USBPHY1_IDDIG */ - IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 0, 0x000, 0), /* MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 1, 0x000, 0), /* MX53_PAD_DI0_PIN4__GPIO4_20 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 2, 0x000, 0), /* MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */ - IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 3, 0x7FC, 0), /* MX53_PAD_DI0_PIN4__ESDHC1_WP */ - IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 5, 0x000, 0), /* MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */ - IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 6, 0x000, 0), /* MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 */ - IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 7, 0x000, 0), /* MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT0__GPIO4_21 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 2, 0x780, 0), /* MX53_PAD_DISP0_DAT0__CSPI_SCLK */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT1__GPIO4_22 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 2, 0x788, 0), /* MX53_PAD_DISP0_DAT1__CSPI_MOSI */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT2__GPIO4_23 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 2, 0x784, 0), /* MX53_PAD_DISP0_DAT2__CSPI_MISO */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT3__GPIO4_24 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 2, 0x78C, 0), /* MX53_PAD_DISP0_DAT3__CSPI_SS0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT4__GPIO4_25 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 2, 0x790, 0), /* MX53_PAD_DISP0_DAT4__CSPI_SS1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT5__GPIO4_26 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 2, 0x794, 0), /* MX53_PAD_DISP0_DAT5__CSPI_SS2 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT6__GPIO4_27 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 2, 0x798, 0), /* MX53_PAD_DISP0_DAT6__CSPI_SS3 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT7__GPIO4_28 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT7__CSPI_RDY */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT8__GPIO4_29 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT8__PWM1_PWMO */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT8__USBPHY2_AVALID */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT9__GPIO4_30 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT9__PWM2_PWMO */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT10__GPIO4_31 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT11__GPIO5_5 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT12__GPIO5_6 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT13__GPIO5_7 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 3, 0x754, 0), /* MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT14__GPIO5_8 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 3, 0x750, 0), /* MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT15__GPIO5_9 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 2, 0x7AC, 1), /* MX53_PAD_DISP0_DAT15__ECSPI1_SS1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 3, 0x7C8, 0), /* MX53_PAD_DISP0_DAT15__ECSPI2_SS1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT16__GPIO5_10 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 2, 0x7C0, 0), /* MX53_PAD_DISP0_DAT16__ECSPI2_MOSI */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 3, 0x758, 1), /* MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 4, 0x868, 0), /* MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT17__GPIO5_11 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 2, 0x7BC, 0), /* MX53_PAD_DISP0_DAT17__ECSPI2_MISO */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 3, 0x74C, 1), /* MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 4, 0x86C, 0), /* MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT18__GPIO5_12 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 2, 0x7C4, 0), /* MX53_PAD_DISP0_DAT18__ECSPI2_SS0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 3, 0x75C, 1), /* MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 4, 0x73C, 0), /* MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT19__GPIO5_13 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 2, 0x7B8, 0), /* MX53_PAD_DISP0_DAT19__ECSPI2_SCLK */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 3, 0x748, 1), /* MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 4, 0x738, 0), /* MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT20__GPIO5_14 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 2, 0x79C, 1), /* MX53_PAD_DISP0_DAT20__ECSPI1_SCLK */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 3, 0x740, 0), /* MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT20__SATA_PHY_TDI */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT21__GPIO5_15 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 2, 0x7A4, 1), /* MX53_PAD_DISP0_DAT21__ECSPI1_MOSI */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 3, 0x734, 0), /* MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT21__SATA_PHY_TDO */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT22__GPIO5_16 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 2, 0x7A0, 1), /* MX53_PAD_DISP0_DAT22__ECSPI1_MISO */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 3, 0x744, 0), /* MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT22__SATA_PHY_TCK */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT23__GPIO5_17 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 2, 0x7A8, 1), /* MX53_PAD_DISP0_DAT23__ECSPI1_SS0 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 3, 0x730, 0), /* MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 */ - IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT23__SATA_PHY_TMS */ - IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 0, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */ - IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 1, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__GPIO5_18 */ - IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 5, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */ - IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 6, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 */ - IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 0, 0x000, 0), /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */ - IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 1, 0x000, 0), /* MX53_PAD_CSI0_MCLK__GPIO5_19 */ - IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 2, 0x000, 0), /* MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK */ - IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 5, 0x000, 0), /* MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */ - IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 6, 0x000, 0), /* MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 */ - IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 7, 0x000, 0), /* MX53_PAD_CSI0_MCLK__TPIU_TRCTL */ - IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 0, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */ - IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 1, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__GPIO5_20 */ - IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 5, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */ - IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 6, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 */ - IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 7, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK */ - IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 0, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */ - IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 1, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__GPIO5_21 */ - IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 5, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */ - IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 6, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 */ - IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 7, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT4__GPIO5_22 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 2, 0x840, 1), /* MX53_PAD_CSI0_DAT4__KPP_COL_5 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 3, 0x79C, 2), /* MX53_PAD_CSI0_DAT4__ECSPI1_SCLK */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT5__GPIO5_23 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 2, 0x84C, 0), /* MX53_PAD_CSI0_DAT5__KPP_ROW_5 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 3, 0x7A4, 2), /* MX53_PAD_CSI0_DAT5__ECSPI1_MOSI */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT6__GPIO5_24 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 2, 0x844, 0), /* MX53_PAD_CSI0_DAT6__KPP_COL_6 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 3, 0x7A0, 2), /* MX53_PAD_CSI0_DAT6__ECSPI1_MISO */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT7__GPIO5_25 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 2, 0x850, 0), /* MX53_PAD_CSI0_DAT7__KPP_ROW_6 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 3, 0x7A8, 2), /* MX53_PAD_CSI0_DAT7__ECSPI1_SS0 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT8__GPIO5_26 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 2, 0x848, 0), /* MX53_PAD_CSI0_DAT8__KPP_COL_7 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 3, 0x7B8, 1), /* MX53_PAD_CSI0_DAT8__ECSPI2_SCLK */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 5, 0x818, 0), /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT9__GPIO5_27 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 2, 0x854, 0), /* MX53_PAD_CSI0_DAT9__KPP_ROW_7 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 3, 0x7C0, 1), /* MX53_PAD_CSI0_DAT9__ECSPI2_MOSI */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 5, 0x814, 0), /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT10__GPIO5_28 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 3, 0x7BC, 1), /* MX53_PAD_CSI0_DAT10__ECSPI2_MISO */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT11__GPIO5_29 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 2, 0x878, 1), /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 3, 0x7C4, 1), /* MX53_PAD_CSI0_DAT11__ECSPI2_SS0 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT12__GPIO5_30 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT12__UART4_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT13__GPIO5_31 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 2, 0x890, 3), /* MX53_PAD_CSI0_DAT13__UART4_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT14__GPIO6_0 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT14__UART5_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT15__GPIO6_1 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 2, 0x898, 3), /* MX53_PAD_CSI0_DAT15__UART5_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT16__GPIO6_2 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 2, 0x88C, 0), /* MX53_PAD_CSI0_DAT16__UART4_RTS */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT17__GPIO6_3 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT17__UART4_CTS */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT18__GPIO6_4 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 2, 0x894, 2), /* MX53_PAD_CSI0_DAT18__UART5_RTS */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT19__GPIO6_5 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT19__UART5_CTS */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 */ - IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK */ - IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 0, 0x000, 0), /* MX53_PAD_EIM_A25__EMI_WEIM_A_25 */ - IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 1, 0x000, 0), /* MX53_PAD_EIM_A25__GPIO5_2 */ - IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 2, 0x000, 0), /* MX53_PAD_EIM_A25__ECSPI2_RDY */ - IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 3, 0x000, 0), /* MX53_PAD_EIM_A25__IPU_DI1_PIN12 */ - IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 4, 0x790, 1), /* MX53_PAD_EIM_A25__CSPI_SS1 */ - IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 6, 0x000, 0), /* MX53_PAD_EIM_A25__IPU_DI0_D1_CS */ - IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 7, 0x000, 0), /* MX53_PAD_EIM_A25__USBPHY1_BISTOK */ - IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 0, 0x000, 0), /* MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 */ - IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 1, 0x000, 0), /* MX53_PAD_EIM_EB2__GPIO2_30 */ - IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 2, 0x76C, 0), /* MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK */ - IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 3, 0x000, 0), /* MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS */ - IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 4, 0x7A8, 3), /* MX53_PAD_EIM_EB2__ECSPI1_SS0 */ - IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 5, 0x81C, 1), /* MX53_PAD_EIM_EB2__I2C2_SCL */ - IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 0, 0x000, 0), /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */ - IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 1, 0x000, 0), /* MX53_PAD_EIM_D16__GPIO3_16 */ - IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 2, 0x000, 0), /* MX53_PAD_EIM_D16__IPU_DI0_PIN5 */ - IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 3, 0x000, 0), /* MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK */ - IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 4, 0x79C, 3), /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ - IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 5, 0x820, 1), /* MX53_PAD_EIM_D16__I2C2_SDA */ - IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 0, 0x000, 0), /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */ - IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 1, 0x000, 0), /* MX53_PAD_EIM_D17__GPIO3_17 */ - IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 2, 0x000, 0), /* MX53_PAD_EIM_D17__IPU_DI0_PIN6 */ - IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 3, 0x830, 0), /* MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN */ - IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 4, 0x7A0, 3), /* MX53_PAD_EIM_D17__ECSPI1_MISO */ - IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 5, 0x824, 0), /* MX53_PAD_EIM_D17__I2C3_SCL */ - IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 0, 0x000, 0), /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */ - IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 1, 0x000, 0), /* MX53_PAD_EIM_D18__GPIO3_18 */ - IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 2, 0x000, 0), /* MX53_PAD_EIM_D18__IPU_DI0_PIN7 */ - IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 3, 0x830, 1), /* MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO */ - IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 4, 0x7A4, 3), /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ - IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 5, 0x828, 0), /* MX53_PAD_EIM_D18__I2C3_SDA */ - IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 6, 0x000, 0), /* MX53_PAD_EIM_D18__IPU_DI1_D0_CS */ - IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 0, 0x000, 0), /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */ - IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 1, 0x000, 0), /* MX53_PAD_EIM_D19__GPIO3_19 */ - IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 2, 0x000, 0), /* MX53_PAD_EIM_D19__IPU_DI0_PIN8 */ - IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 3, 0x000, 0), /* MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS */ - IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 4, 0x7AC, 2), /* MX53_PAD_EIM_D19__ECSPI1_SS1 */ - IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 5, 0x000, 0), /* MX53_PAD_EIM_D19__EPIT1_EPITO */ - IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 6, 0x000, 0), /* MX53_PAD_EIM_D19__UART1_CTS */ - IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 7, 0x8A4, 0), /* MX53_PAD_EIM_D19__USBOH3_USBH2_OC */ - IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 0, 0x000, 0), /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */ - IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 1, 0x000, 0), /* MX53_PAD_EIM_D20__GPIO3_20 */ - IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 2, 0x000, 0), /* MX53_PAD_EIM_D20__IPU_DI0_PIN16 */ - IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 3, 0x000, 0), /* MX53_PAD_EIM_D20__IPU_SER_DISP0_CS */ - IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 4, 0x78C, 1), /* MX53_PAD_EIM_D20__CSPI_SS0 */ - IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 5, 0x000, 0), /* MX53_PAD_EIM_D20__EPIT2_EPITO */ - IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 6, 0x874, 1), /* MX53_PAD_EIM_D20__UART1_RTS */ - IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 7, 0x000, 0), /* MX53_PAD_EIM_D20__USBOH3_USBH2_PWR */ - IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 0, 0x000, 0), /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */ - IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 1, 0x000, 0), /* MX53_PAD_EIM_D21__GPIO3_21 */ - IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 2, 0x000, 0), /* MX53_PAD_EIM_D21__IPU_DI0_PIN17 */ - IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 3, 0x000, 0), /* MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK */ - IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 4, 0x780, 1), /* MX53_PAD_EIM_D21__CSPI_SCLK */ - IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 5, 0x814, 1), /* MX53_PAD_EIM_D21__I2C1_SCL */ - IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 6, 0x89C, 1), /* MX53_PAD_EIM_D21__USBOH3_USBOTG_OC */ - IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 0, 0x000, 0), /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */ - IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 1, 0x000, 0), /* MX53_PAD_EIM_D22__GPIO3_22 */ - IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 2, 0x000, 0), /* MX53_PAD_EIM_D22__IPU_DI0_PIN1 */ - IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 3, 0x82C, 0), /* MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN */ - IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 4, 0x784, 1), /* MX53_PAD_EIM_D22__CSPI_MISO */ - IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 6, 0x000, 0), /* MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR */ - IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 0, 0x000, 0), /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */ - IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 1, 0x000, 0), /* MX53_PAD_EIM_D23__GPIO3_23 */ - IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 2, 0x000, 0), /* MX53_PAD_EIM_D23__UART3_CTS */ - IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 3, 0x000, 0), /* MX53_PAD_EIM_D23__UART1_DCD */ - IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 4, 0x000, 0), /* MX53_PAD_EIM_D23__IPU_DI0_D0_CS */ - IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 5, 0x000, 0), /* MX53_PAD_EIM_D23__IPU_DI1_PIN2 */ - IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 6, 0x834, 0), /* MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN */ - IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 7, 0x000, 0), /* MX53_PAD_EIM_D23__IPU_DI1_PIN14 */ - IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 0, 0x000, 0), /* MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 */ - IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 1, 0x000, 0), /* MX53_PAD_EIM_EB3__GPIO2_31 */ - IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 2, 0x884, 1), /* MX53_PAD_EIM_EB3__UART3_RTS */ - IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 3, 0x000, 0), /* MX53_PAD_EIM_EB3__UART1_RI */ - IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 5, 0x000, 0), /* MX53_PAD_EIM_EB3__IPU_DI1_PIN3 */ - IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 6, 0x838, 0), /* MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC */ - IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 7, 0x000, 0), /* MX53_PAD_EIM_EB3__IPU_DI1_PIN16 */ - IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 0, 0x000, 0), /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */ - IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 1, 0x000, 0), /* MX53_PAD_EIM_D24__GPIO3_24 */ - IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 2, 0x000, 0), /* MX53_PAD_EIM_D24__UART3_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 3, 0x7B0, 1), /* MX53_PAD_EIM_D24__ECSPI1_SS2 */ - IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 4, 0x794, 1), /* MX53_PAD_EIM_D24__CSPI_SS2 */ - IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 5, 0x754, 1), /* MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS */ - IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 6, 0x000, 0), /* MX53_PAD_EIM_D24__ECSPI2_SS2 */ - IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 7, 0x000, 0), /* MX53_PAD_EIM_D24__UART1_DTR */ - IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 0, 0x000, 0), /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */ - IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 1, 0x000, 0), /* MX53_PAD_EIM_D25__GPIO3_25 */ - IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 2, 0x888, 1), /* MX53_PAD_EIM_D25__UART3_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 3, 0x7B4, 1), /* MX53_PAD_EIM_D25__ECSPI1_SS3 */ - IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 4, 0x798, 1), /* MX53_PAD_EIM_D25__CSPI_SS3 */ - IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 5, 0x750, 1), /* MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC */ - IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 6, 0x000, 0), /* MX53_PAD_EIM_D25__ECSPI2_SS3 */ - IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 7, 0x000, 0), /* MX53_PAD_EIM_D25__UART1_DSR */ - IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 0, 0x000, 0), /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */ - IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 1, 0x000, 0), /* MX53_PAD_EIM_D26__GPIO3_26 */ - IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 2, 0x000, 0), /* MX53_PAD_EIM_D26__UART2_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 3, 0x80C, 0), /* MX53_PAD_EIM_D26__FIRI_RXD */ - IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 4, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_CSI0_D_1 */ - IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 5, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_DI1_PIN11 */ - IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 6, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_SISG_2 */ - IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 7, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 */ - IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 0, 0x000, 0), /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */ - IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 1, 0x000, 0), /* MX53_PAD_EIM_D27__GPIO3_27 */ - IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 2, 0x880, 1), /* MX53_PAD_EIM_D27__UART2_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 3, 0x000, 0), /* MX53_PAD_EIM_D27__FIRI_TXD */ - IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 4, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_CSI0_D_0 */ - IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 5, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_DI1_PIN13 */ - IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 6, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_SISG_3 */ - IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 7, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 */ - IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 0, 0x000, 0), /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */ - IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 1, 0x000, 0), /* MX53_PAD_EIM_D28__GPIO3_28 */ - IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 2, 0x000, 0), /* MX53_PAD_EIM_D28__UART2_CTS */ - IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 3, 0x82C, 1), /* MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO */ - IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 4, 0x788, 1), /* MX53_PAD_EIM_D28__CSPI_MOSI */ - IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 5, 0x818, 1), /* MX53_PAD_EIM_D28__I2C1_SDA */ - IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 6, 0x000, 0), /* MX53_PAD_EIM_D28__IPU_EXT_TRIG */ - IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 7, 0x000, 0), /* MX53_PAD_EIM_D28__IPU_DI0_PIN13 */ - IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 0, 0x000, 0), /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */ - IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 1, 0x000, 0), /* MX53_PAD_EIM_D29__GPIO3_29 */ - IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 2, 0x87C, 1), /* MX53_PAD_EIM_D29__UART2_RTS */ - IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 3, 0x000, 0), /* MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS */ - IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 4, 0x78C, 2), /* MX53_PAD_EIM_D29__CSPI_SS0 */ - IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 5, 0x000, 0), /* MX53_PAD_EIM_D29__IPU_DI1_PIN15 */ - IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 6, 0x83C, 0), /* MX53_PAD_EIM_D29__IPU_CSI1_VSYNC */ - IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 7, 0x000, 0), /* MX53_PAD_EIM_D29__IPU_DI0_PIN14 */ - IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 0, 0x000, 0), /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */ - IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 1, 0x000, 0), /* MX53_PAD_EIM_D30__GPIO3_30 */ - IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 2, 0x000, 0), /* MX53_PAD_EIM_D30__UART3_CTS */ - IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 3, 0x000, 0), /* MX53_PAD_EIM_D30__IPU_CSI0_D_3 */ - IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 4, 0x000, 0), /* MX53_PAD_EIM_D30__IPU_DI0_PIN11 */ - IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 5, 0x000, 0), /* MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 */ - IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 6, 0x8A0, 0), /* MX53_PAD_EIM_D30__USBOH3_USBH1_OC */ - IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 7, 0x8A4, 1), /* MX53_PAD_EIM_D30__USBOH3_USBH2_OC */ - IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 0, 0x000, 0), /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */ - IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 1, 0x000, 0), /* MX53_PAD_EIM_D31__GPIO3_31 */ - IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 2, 0x884, 3), /* MX53_PAD_EIM_D31__UART3_RTS */ - IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 3, 0x000, 0), /* MX53_PAD_EIM_D31__IPU_CSI0_D_2 */ - IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 4, 0x000, 0), /* MX53_PAD_EIM_D31__IPU_DI0_PIN12 */ - IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 5, 0x000, 0), /* MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 */ - IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 6, 0x000, 0), /* MX53_PAD_EIM_D31__USBOH3_USBH1_PWR */ - IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 7, 0x000, 0), /* MX53_PAD_EIM_D31__USBOH3_USBH2_PWR */ - IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 0, 0x000, 0), /* MX53_PAD_EIM_A24__EMI_WEIM_A_24 */ - IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 1, 0x000, 0), /* MX53_PAD_EIM_A24__GPIO5_4 */ - IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 2, 0x000, 0), /* MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 */ - IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 3, 0x000, 0), /* MX53_PAD_EIM_A24__IPU_CSI1_D_19 */ - IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 6, 0x000, 0), /* MX53_PAD_EIM_A24__IPU_SISG_2 */ - IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 7, 0x000, 0), /* MX53_PAD_EIM_A24__USBPHY2_BVALID */ - IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 0, 0x000, 0), /* MX53_PAD_EIM_A23__EMI_WEIM_A_23 */ - IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 1, 0x000, 0), /* MX53_PAD_EIM_A23__GPIO6_6 */ - IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 2, 0x000, 0), /* MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 */ - IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 3, 0x000, 0), /* MX53_PAD_EIM_A23__IPU_CSI1_D_18 */ - IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 6, 0x000, 0), /* MX53_PAD_EIM_A23__IPU_SISG_3 */ - IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 7, 0x000, 0), /* MX53_PAD_EIM_A23__USBPHY2_ENDSESSION */ - IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 0, 0x000, 0), /* MX53_PAD_EIM_A22__EMI_WEIM_A_22 */ - IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 1, 0x000, 0), /* MX53_PAD_EIM_A22__GPIO2_16 */ - IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 2, 0x000, 0), /* MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 */ - IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 3, 0x000, 0), /* MX53_PAD_EIM_A22__IPU_CSI1_D_17 */ - IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 7, 0x000, 0), /* MX53_PAD_EIM_A22__SRC_BT_CFG1_7 */ - IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 0, 0x000, 0), /* MX53_PAD_EIM_A21__EMI_WEIM_A_21 */ - IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 1, 0x000, 0), /* MX53_PAD_EIM_A21__GPIO2_17 */ - IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 2, 0x000, 0), /* MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 */ - IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 3, 0x000, 0), /* MX53_PAD_EIM_A21__IPU_CSI1_D_16 */ - IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 7, 0x000, 0), /* MX53_PAD_EIM_A21__SRC_BT_CFG1_6 */ - IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 0, 0x000, 0), /* MX53_PAD_EIM_A20__EMI_WEIM_A_20 */ - IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 1, 0x000, 0), /* MX53_PAD_EIM_A20__GPIO2_18 */ - IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 2, 0x000, 0), /* MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 */ - IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 3, 0x000, 0), /* MX53_PAD_EIM_A20__IPU_CSI1_D_15 */ - IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 7, 0x000, 0), /* MX53_PAD_EIM_A20__SRC_BT_CFG1_5 */ - IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 0, 0x000, 0), /* MX53_PAD_EIM_A19__EMI_WEIM_A_19 */ - IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 1, 0x000, 0), /* MX53_PAD_EIM_A19__GPIO2_19 */ - IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 2, 0x000, 0), /* MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 */ - IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 3, 0x000, 0), /* MX53_PAD_EIM_A19__IPU_CSI1_D_14 */ - IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 7, 0x000, 0), /* MX53_PAD_EIM_A19__SRC_BT_CFG1_4 */ - IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 0, 0x000, 0), /* MX53_PAD_EIM_A18__EMI_WEIM_A_18 */ - IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 1, 0x000, 0), /* MX53_PAD_EIM_A18__GPIO2_20 */ - IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 2, 0x000, 0), /* MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 */ - IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 3, 0x000, 0), /* MX53_PAD_EIM_A18__IPU_CSI1_D_13 */ - IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 7, 0x000, 0), /* MX53_PAD_EIM_A18__SRC_BT_CFG1_3 */ - IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 0, 0x000, 0), /* MX53_PAD_EIM_A17__EMI_WEIM_A_17 */ - IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 1, 0x000, 0), /* MX53_PAD_EIM_A17__GPIO2_21 */ - IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 2, 0x000, 0), /* MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 */ - IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 3, 0x000, 0), /* MX53_PAD_EIM_A17__IPU_CSI1_D_12 */ - IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 7, 0x000, 0), /* MX53_PAD_EIM_A17__SRC_BT_CFG1_2 */ - IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 0, 0x000, 0), /* MX53_PAD_EIM_A16__EMI_WEIM_A_16 */ - IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 1, 0x000, 0), /* MX53_PAD_EIM_A16__GPIO2_22 */ - IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 2, 0x000, 0), /* MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK */ - IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 3, 0x000, 0), /* MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK */ - IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 7, 0x000, 0), /* MX53_PAD_EIM_A16__SRC_BT_CFG1_1 */ - IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 0, 0x000, 0), /* MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 */ - IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 1, 0x000, 0), /* MX53_PAD_EIM_CS0__GPIO2_23 */ - IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 2, 0x7B8, 2), /* MX53_PAD_EIM_CS0__ECSPI2_SCLK */ - IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 3, 0x000, 0), /* MX53_PAD_EIM_CS0__IPU_DI1_PIN5 */ - IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 0, 0x000, 0), /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */ - IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 1, 0x000, 0), /* MX53_PAD_EIM_CS1__GPIO2_24 */ - IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 2, 0x7C0, 2), /* MX53_PAD_EIM_CS1__ECSPI2_MOSI */ - IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 3, 0x000, 0), /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 */ - IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 0, 0x000, 0), /* MX53_PAD_EIM_OE__EMI_WEIM_OE */ - IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 1, 0x000, 0), /* MX53_PAD_EIM_OE__GPIO2_25 */ - IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 2, 0x7BC, 2), /* MX53_PAD_EIM_OE__ECSPI2_MISO */ - IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 3, 0x000, 0), /* MX53_PAD_EIM_OE__IPU_DI1_PIN7 */ - IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 7, 0x000, 0), /* MX53_PAD_EIM_OE__USBPHY2_IDDIG */ - IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 0, 0x000, 0), /* MX53_PAD_EIM_RW__EMI_WEIM_RW */ - IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 1, 0x000, 0), /* MX53_PAD_EIM_RW__GPIO2_26 */ - IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 2, 0x7C4, 2), /* MX53_PAD_EIM_RW__ECSPI2_SS0 */ - IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 3, 0x000, 0), /* MX53_PAD_EIM_RW__IPU_DI1_PIN8 */ - IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 7, 0x000, 0), /* MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT */ - IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 0, 0x000, 0), /* MX53_PAD_EIM_LBA__EMI_WEIM_LBA */ - IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 1, 0x000, 0), /* MX53_PAD_EIM_LBA__GPIO2_27 */ - IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 2, 0x7C8, 1), /* MX53_PAD_EIM_LBA__ECSPI2_SS1 */ - IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 3, 0x000, 0), /* MX53_PAD_EIM_LBA__IPU_DI1_PIN17 */ - IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 7, 0x000, 0), /* MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 */ - IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 0, 0x000, 0), /* MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 */ - IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 1, 0x000, 0), /* MX53_PAD_EIM_EB0__GPIO2_28 */ - IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 3, 0x000, 0), /* MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 */ - IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 4, 0x000, 0), /* MX53_PAD_EIM_EB0__IPU_CSI1_D_11 */ - IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 5, 0x810, 0), /* MX53_PAD_EIM_EB0__GPC_PMIC_RDY */ - IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 7, 0x000, 0), /* MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 */ - IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 0, 0x000, 0), /* MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 */ - IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 1, 0x000, 0), /* MX53_PAD_EIM_EB1__GPIO2_29 */ - IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 3, 0x000, 0), /* MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 */ - IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 4, 0x000, 0), /* MX53_PAD_EIM_EB1__IPU_CSI1_D_10 */ - IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 7, 0x000, 0), /* MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 */ - IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 0, 0x000, 0), /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */ - IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 1, 0x000, 0), /* MX53_PAD_EIM_DA0__GPIO3_0 */ - IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 3, 0x000, 0), /* MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 */ - IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 4, 0x000, 0), /* MX53_PAD_EIM_DA0__IPU_CSI1_D_9 */ - IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 7, 0x000, 0), /* MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 */ - IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 0, 0x000, 0), /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */ - IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 1, 0x000, 0), /* MX53_PAD_EIM_DA1__GPIO3_1 */ - IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 3, 0x000, 0), /* MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 */ - IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 4, 0x000, 0), /* MX53_PAD_EIM_DA1__IPU_CSI1_D_8 */ - IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 7, 0x000, 0), /* MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 */ - IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 0, 0x000, 0), /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */ - IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 1, 0x000, 0), /* MX53_PAD_EIM_DA2__GPIO3_2 */ - IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 3, 0x000, 0), /* MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 */ - IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 4, 0x000, 0), /* MX53_PAD_EIM_DA2__IPU_CSI1_D_7 */ - IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 7, 0x000, 0), /* MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 */ - IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 0, 0x000, 0), /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */ - IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 1, 0x000, 0), /* MX53_PAD_EIM_DA3__GPIO3_3 */ - IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 3, 0x000, 0), /* MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 */ - IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 4, 0x000, 0), /* MX53_PAD_EIM_DA3__IPU_CSI1_D_6 */ - IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 7, 0x000, 0), /* MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 */ - IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 0, 0x000, 0), /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */ - IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 1, 0x000, 0), /* MX53_PAD_EIM_DA4__GPIO3_4 */ - IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 3, 0x000, 0), /* MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 */ - IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 4, 0x000, 0), /* MX53_PAD_EIM_DA4__IPU_CSI1_D_5 */ - IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 7, 0x000, 0), /* MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 */ - IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 0, 0x000, 0), /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */ - IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 1, 0x000, 0), /* MX53_PAD_EIM_DA5__GPIO3_5 */ - IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 3, 0x000, 0), /* MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 */ - IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 4, 0x000, 0), /* MX53_PAD_EIM_DA5__IPU_CSI1_D_4 */ - IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 7, 0x000, 0), /* MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 */ - IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 0, 0x000, 0), /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */ - IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 1, 0x000, 0), /* MX53_PAD_EIM_DA6__GPIO3_6 */ - IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 3, 0x000, 0), /* MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 */ - IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 4, 0x000, 0), /* MX53_PAD_EIM_DA6__IPU_CSI1_D_3 */ - IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 7, 0x000, 0), /* MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 */ - IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 0, 0x000, 0), /* MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 */ - IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 1, 0x000, 0), /* MX53_PAD_EIM_DA7__GPIO3_7 */ - IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 3, 0x000, 0), /* MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 */ - IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 4, 0x000, 0), /* MX53_PAD_EIM_DA7__IPU_CSI1_D_2 */ - IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 7, 0x000, 0), /* MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 */ - IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 0, 0x000, 0), /* MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 */ - IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 1, 0x000, 0), /* MX53_PAD_EIM_DA8__GPIO3_8 */ - IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 3, 0x000, 0), /* MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 */ - IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 4, 0x000, 0), /* MX53_PAD_EIM_DA8__IPU_CSI1_D_1 */ - IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 7, 0x000, 0), /* MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 */ - IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 0, 0x000, 0), /* MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 */ - IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 1, 0x000, 0), /* MX53_PAD_EIM_DA9__GPIO3_9 */ - IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 3, 0x000, 0), /* MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 */ - IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 4, 0x000, 0), /* MX53_PAD_EIM_DA9__IPU_CSI1_D_0 */ - IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 7, 0x000, 0), /* MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 */ - IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 0, 0x000, 0), /* MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 */ - IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 1, 0x000, 0), /* MX53_PAD_EIM_DA10__GPIO3_10 */ - IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 3, 0x000, 0), /* MX53_PAD_EIM_DA10__IPU_DI1_PIN15 */ - IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 4, 0x834, 1), /* MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN */ - IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 7, 0x000, 0), /* MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 */ - IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 0, 0x000, 0), /* MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 */ - IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 1, 0x000, 0), /* MX53_PAD_EIM_DA11__GPIO3_11 */ - IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 3, 0x000, 0), /* MX53_PAD_EIM_DA11__IPU_DI1_PIN2 */ - IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 4, 0x838, 1), /* MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC */ - IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 0, 0x000, 0), /* MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 */ - IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 1, 0x000, 0), /* MX53_PAD_EIM_DA12__GPIO3_12 */ - IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 3, 0x000, 0), /* MX53_PAD_EIM_DA12__IPU_DI1_PIN3 */ - IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 4, 0x83C, 1), /* MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC */ - IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 0, 0x000, 0), /* MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 */ - IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 1, 0x000, 0), /* MX53_PAD_EIM_DA13__GPIO3_13 */ - IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 3, 0x000, 0), /* MX53_PAD_EIM_DA13__IPU_DI1_D0_CS */ - IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 4, 0x76C, 1), /* MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK */ - IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 0, 0x000, 0), /* MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 */ - IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 1, 0x000, 0), /* MX53_PAD_EIM_DA14__GPIO3_14 */ - IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 3, 0x000, 0), /* MX53_PAD_EIM_DA14__IPU_DI1_D1_CS */ - IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 4, 0x000, 0), /* MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK */ - IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 0, 0x000, 0), /* MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 */ - IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 1, 0x000, 0), /* MX53_PAD_EIM_DA15__GPIO3_15 */ - IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 3, 0x000, 0), /* MX53_PAD_EIM_DA15__IPU_DI1_PIN1 */ - IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 4, 0x000, 0), /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 */ - IMX_PIN_REG(MX53_PAD_NANDF_WE_B, 0x52C, 0x1DC, 0, 0x000, 0), /* MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B */ - IMX_PIN_REG(MX53_PAD_NANDF_WE_B, 0x52C, 0x1DC, 1, 0x000, 0), /* MX53_PAD_NANDF_WE_B__GPIO6_12 */ - IMX_PIN_REG(MX53_PAD_NANDF_RE_B, 0x530, 0x1E0, 0, 0x000, 0), /* MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B */ - IMX_PIN_REG(MX53_PAD_NANDF_RE_B, 0x530, 0x1E0, 1, 0x000, 0), /* MX53_PAD_NANDF_RE_B__GPIO6_13 */ - IMX_PIN_REG(MX53_PAD_EIM_WAIT, 0x534, 0x1E4, 0, 0x000, 0), /* MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT */ - IMX_PIN_REG(MX53_PAD_EIM_WAIT, 0x534, 0x1E4, 1, 0x000, 0), /* MX53_PAD_EIM_WAIT__GPIO5_0 */ - IMX_PIN_REG(MX53_PAD_EIM_WAIT, 0x534, 0x1E4, 2, 0x000, 0), /* MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B */ - IMX_PIN_REG(MX53_PAD_LVDS1_TX3_P, NO_PAD, 0x1EC, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX3_P__GPIO6_22 */ - IMX_PIN_REG(MX53_PAD_LVDS1_TX3_P, NO_PAD, 0x1EC, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */ - IMX_PIN_REG(MX53_PAD_LVDS1_TX2_P, NO_PAD, 0x1F0, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX2_P__GPIO6_24 */ - IMX_PIN_REG(MX53_PAD_LVDS1_TX2_P, NO_PAD, 0x1F0, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */ - IMX_PIN_REG(MX53_PAD_LVDS1_CLK_P, NO_PAD, 0x1F4, 0, 0x000, 0), /* MX53_PAD_LVDS1_CLK_P__GPIO6_26 */ - IMX_PIN_REG(MX53_PAD_LVDS1_CLK_P, NO_PAD, 0x1F4, 1, 0x000, 0), /* MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */ - IMX_PIN_REG(MX53_PAD_LVDS1_TX1_P, NO_PAD, 0x1F8, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX1_P__GPIO6_28 */ - IMX_PIN_REG(MX53_PAD_LVDS1_TX1_P, NO_PAD, 0x1F8, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */ - IMX_PIN_REG(MX53_PAD_LVDS1_TX0_P, NO_PAD, 0x1FC, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX0_P__GPIO6_30 */ - IMX_PIN_REG(MX53_PAD_LVDS1_TX0_P, NO_PAD, 0x1FC, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */ - IMX_PIN_REG(MX53_PAD_LVDS0_TX3_P, NO_PAD, 0x200, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX3_P__GPIO7_22 */ - IMX_PIN_REG(MX53_PAD_LVDS0_TX3_P, NO_PAD, 0x200, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */ - IMX_PIN_REG(MX53_PAD_LVDS0_CLK_P, NO_PAD, 0x204, 0, 0x000, 0), /* MX53_PAD_LVDS0_CLK_P__GPIO7_24 */ - IMX_PIN_REG(MX53_PAD_LVDS0_CLK_P, NO_PAD, 0x204, 1, 0x000, 0), /* MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */ - IMX_PIN_REG(MX53_PAD_LVDS0_TX2_P, NO_PAD, 0x208, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX2_P__GPIO7_26 */ - IMX_PIN_REG(MX53_PAD_LVDS0_TX2_P, NO_PAD, 0x208, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */ - IMX_PIN_REG(MX53_PAD_LVDS0_TX1_P, NO_PAD, 0x20C, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX1_P__GPIO7_28 */ - IMX_PIN_REG(MX53_PAD_LVDS0_TX1_P, NO_PAD, 0x20C, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */ - IMX_PIN_REG(MX53_PAD_LVDS0_TX0_P, NO_PAD, 0x210, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX0_P__GPIO7_30 */ - IMX_PIN_REG(MX53_PAD_LVDS0_TX0_P, NO_PAD, 0x210, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */ - IMX_PIN_REG(MX53_PAD_GPIO_10, 0x540, 0x214, 0, 0x000, 0), /* MX53_PAD_GPIO_10__GPIO4_0 */ - IMX_PIN_REG(MX53_PAD_GPIO_10, 0x540, 0x214, 1, 0x000, 0), /* MX53_PAD_GPIO_10__OSC32k_32K_OUT */ - IMX_PIN_REG(MX53_PAD_GPIO_11, 0x544, 0x218, 0, 0x000, 0), /* MX53_PAD_GPIO_11__GPIO4_1 */ - IMX_PIN_REG(MX53_PAD_GPIO_12, 0x548, 0x21C, 0, 0x000, 0), /* MX53_PAD_GPIO_12__GPIO4_2 */ - IMX_PIN_REG(MX53_PAD_GPIO_13, 0x54C, 0x220, 0, 0x000, 0), /* MX53_PAD_GPIO_13__GPIO4_3 */ - IMX_PIN_REG(MX53_PAD_GPIO_14, 0x550, 0x224, 0, 0x000, 0), /* MX53_PAD_GPIO_14__GPIO4_4 */ - IMX_PIN_REG(MX53_PAD_NANDF_CLE, 0x5A0, 0x228, 0, 0x000, 0), /* MX53_PAD_NANDF_CLE__EMI_NANDF_CLE */ - IMX_PIN_REG(MX53_PAD_NANDF_CLE, 0x5A0, 0x228, 1, 0x000, 0), /* MX53_PAD_NANDF_CLE__GPIO6_7 */ - IMX_PIN_REG(MX53_PAD_NANDF_CLE, 0x5A0, 0x228, 7, 0x000, 0), /* MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 */ - IMX_PIN_REG(MX53_PAD_NANDF_ALE, 0x5A4, 0x22C, 0, 0x000, 0), /* MX53_PAD_NANDF_ALE__EMI_NANDF_ALE */ - IMX_PIN_REG(MX53_PAD_NANDF_ALE, 0x5A4, 0x22C, 1, 0x000, 0), /* MX53_PAD_NANDF_ALE__GPIO6_8 */ - IMX_PIN_REG(MX53_PAD_NANDF_ALE, 0x5A4, 0x22C, 7, 0x000, 0), /* MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 */ - IMX_PIN_REG(MX53_PAD_NANDF_WP_B, 0x5A8, 0x230, 0, 0x000, 0), /* MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B */ - IMX_PIN_REG(MX53_PAD_NANDF_WP_B, 0x5A8, 0x230, 1, 0x000, 0), /* MX53_PAD_NANDF_WP_B__GPIO6_9 */ - IMX_PIN_REG(MX53_PAD_NANDF_WP_B, 0x5A8, 0x230, 7, 0x000, 0), /* MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 */ - IMX_PIN_REG(MX53_PAD_NANDF_RB0, 0x5AC, 0x234, 0, 0x000, 0), /* MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 */ - IMX_PIN_REG(MX53_PAD_NANDF_RB0, 0x5AC, 0x234, 1, 0x000, 0), /* MX53_PAD_NANDF_RB0__GPIO6_10 */ - IMX_PIN_REG(MX53_PAD_NANDF_RB0, 0x5AC, 0x234, 7, 0x000, 0), /* MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS0, 0x5B0, 0x238, 0, 0x000, 0), /* MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS0, 0x5B0, 0x238, 1, 0x000, 0), /* MX53_PAD_NANDF_CS0__GPIO6_11 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS0, 0x5B0, 0x238, 7, 0x000, 0), /* MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 0, 0x000, 0), /* MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 1, 0x000, 0), /* MX53_PAD_NANDF_CS1__GPIO6_14 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 6, 0x858, 0), /* MX53_PAD_NANDF_CS1__MLB_MLBCLK */ - IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 7, 0x000, 0), /* MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 0, 0x000, 0), /* MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 1, 0x000, 0), /* MX53_PAD_NANDF_CS2__GPIO6_15 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 2, 0x000, 0), /* MX53_PAD_NANDF_CS2__IPU_SISG_0 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 3, 0x7E4, 0), /* MX53_PAD_NANDF_CS2__ESAI1_TX0 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 4, 0x000, 0), /* MX53_PAD_NANDF_CS2__EMI_WEIM_CRE */ - IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 5, 0x000, 0), /* MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK */ - IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 6, 0x860, 0), /* MX53_PAD_NANDF_CS2__MLB_MLBSIG */ - IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 7, 0x000, 0), /* MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 0, 0x000, 0), /* MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 1, 0x000, 0), /* MX53_PAD_NANDF_CS3__GPIO6_16 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 2, 0x000, 0), /* MX53_PAD_NANDF_CS3__IPU_SISG_1 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 3, 0x7E8, 0), /* MX53_PAD_NANDF_CS3__ESAI1_TX1 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 4, 0x000, 0), /* MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 */ - IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 6, 0x85C, 0), /* MX53_PAD_NANDF_CS3__MLB_MLBDAT */ - IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 7, 0x000, 0), /* MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 */ - IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 0, 0x804, 1), /* MX53_PAD_FEC_MDIO__FEC_MDIO */ - IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 1, 0x000, 0), /* MX53_PAD_FEC_MDIO__GPIO1_22 */ - IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 2, 0x7DC, 0), /* MX53_PAD_FEC_MDIO__ESAI1_SCKR */ - IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 3, 0x800, 1), /* MX53_PAD_FEC_MDIO__FEC_COL */ - IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 4, 0x000, 0), /* MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 */ - IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 5, 0x000, 0), /* MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 */ - IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 6, 0x000, 0), /* MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 */ - IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 0, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ - IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 1, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__GPIO1_23 */ - IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 2, 0x7CC, 0), /* MX53_PAD_FEC_REF_CLK__ESAI1_FSR */ - IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 5, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 */ - IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 6, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 */ - IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 0, 0x000, 0), /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ - IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 1, 0x000, 0), /* MX53_PAD_FEC_RX_ER__GPIO1_24 */ - IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 2, 0x7D4, 0), /* MX53_PAD_FEC_RX_ER__ESAI1_HCKR */ - IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 3, 0x808, 1), /* MX53_PAD_FEC_RX_ER__FEC_RX_CLK */ - IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 4, 0x000, 0), /* MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 */ - IMX_PIN_REG(MX53_PAD_FEC_CRS_DV, 0x5D0, 0x254, 0, 0x000, 0), /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ - IMX_PIN_REG(MX53_PAD_FEC_CRS_DV, 0x5D0, 0x254, 1, 0x000, 0), /* MX53_PAD_FEC_CRS_DV__GPIO1_25 */ - IMX_PIN_REG(MX53_PAD_FEC_CRS_DV, 0x5D0, 0x254, 2, 0x7E0, 0), /* MX53_PAD_FEC_CRS_DV__ESAI1_SCKT */ - IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 0, 0x000, 0), /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ - IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 1, 0x000, 0), /* MX53_PAD_FEC_RXD1__GPIO1_26 */ - IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 2, 0x7D0, 0), /* MX53_PAD_FEC_RXD1__ESAI1_FST */ - IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 3, 0x860, 1), /* MX53_PAD_FEC_RXD1__MLB_MLBSIG */ - IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 4, 0x000, 0), /* MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 */ - IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 0, 0x000, 0), /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ - IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 1, 0x000, 0), /* MX53_PAD_FEC_RXD0__GPIO1_27 */ - IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 2, 0x7D8, 0), /* MX53_PAD_FEC_RXD0__ESAI1_HCKT */ - IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 3, 0x000, 0), /* MX53_PAD_FEC_RXD0__OSC32k_32K_OUT */ - IMX_PIN_REG(MX53_PAD_FEC_TX_EN, 0x5DC, 0x260, 0, 0x000, 0), /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ - IMX_PIN_REG(MX53_PAD_FEC_TX_EN, 0x5DC, 0x260, 1, 0x000, 0), /* MX53_PAD_FEC_TX_EN__GPIO1_28 */ - IMX_PIN_REG(MX53_PAD_FEC_TX_EN, 0x5DC, 0x260, 2, 0x7F0, 0), /* MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 */ - IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 0, 0x000, 0), /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ - IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 1, 0x000, 0), /* MX53_PAD_FEC_TXD1__GPIO1_29 */ - IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 2, 0x7EC, 0), /* MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 */ - IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 3, 0x858, 1), /* MX53_PAD_FEC_TXD1__MLB_MLBCLK */ - IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 4, 0x000, 0), /* MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK */ - IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 0, 0x000, 0), /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ - IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 1, 0x000, 0), /* MX53_PAD_FEC_TXD0__GPIO1_30 */ - IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 2, 0x7F4, 0), /* MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 */ - IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 7, 0x000, 0), /* MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 */ - IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 0, 0x000, 0), /* MX53_PAD_FEC_MDC__FEC_MDC */ - IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 1, 0x000, 0), /* MX53_PAD_FEC_MDC__GPIO1_31 */ - IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 2, 0x7F8, 0), /* MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 */ - IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 3, 0x85C, 1), /* MX53_PAD_FEC_MDC__MLB_MLBDAT */ - IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 4, 0x000, 0), /* MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG */ - IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 7, 0x000, 0), /* MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 */ - IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 0, 0x000, 0), /* MX53_PAD_PATA_DIOW__PATA_DIOW */ - IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 1, 0x000, 0), /* MX53_PAD_PATA_DIOW__GPIO6_17 */ - IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 3, 0x000, 0), /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 7, 0x000, 0), /* MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 */ - IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 0, 0x000, 0), /* MX53_PAD_PATA_DMACK__PATA_DMACK */ - IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 1, 0x000, 0), /* MX53_PAD_PATA_DMACK__GPIO6_18 */ - IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 3, 0x878, 3), /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 7, 0x000, 0), /* MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 */ - IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 0, 0x000, 0), /* MX53_PAD_PATA_DMARQ__PATA_DMARQ */ - IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 1, 0x000, 0), /* MX53_PAD_PATA_DMARQ__GPIO7_0 */ - IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 3, 0x000, 0), /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 5, 0x000, 0), /* MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 */ - IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 7, 0x000, 0), /* MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 */ - IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 0, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN */ - IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 1, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__GPIO7_1 */ - IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 3, 0x880, 3), /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 5, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 */ - IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 7, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 */ - IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 0, 0x000, 0), /* MX53_PAD_PATA_INTRQ__PATA_INTRQ */ - IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 1, 0x000, 0), /* MX53_PAD_PATA_INTRQ__GPIO7_2 */ - IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 3, 0x000, 0), /* MX53_PAD_PATA_INTRQ__UART2_CTS */ - IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 4, 0x000, 0), /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */ - IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 5, 0x000, 0), /* MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 */ - IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 7, 0x000, 0), /* MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 */ - IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 0, 0x000, 0), /* MX53_PAD_PATA_DIOR__PATA_DIOR */ - IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 1, 0x000, 0), /* MX53_PAD_PATA_DIOR__GPIO7_3 */ - IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 3, 0x87C, 3), /* MX53_PAD_PATA_DIOR__UART2_RTS */ - IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 4, 0x760, 1), /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */ - IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 7, 0x000, 0), /* MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 */ - IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 0, 0x000, 0), /* MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B */ - IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 1, 0x000, 0), /* MX53_PAD_PATA_RESET_B__GPIO7_4 */ - IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 2, 0x000, 0), /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ - IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 3, 0x000, 0), /* MX53_PAD_PATA_RESET_B__UART1_CTS */ - IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 4, 0x000, 0), /* MX53_PAD_PATA_RESET_B__CAN2_TXCAN */ - IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 7, 0x000, 0), /* MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 */ - IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 0, 0x000, 0), /* MX53_PAD_PATA_IORDY__PATA_IORDY */ - IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 1, 0x000, 0), /* MX53_PAD_PATA_IORDY__GPIO7_5 */ - IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 2, 0x000, 0), /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ - IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 3, 0x874, 3), /* MX53_PAD_PATA_IORDY__UART1_RTS */ - IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 4, 0x764, 1), /* MX53_PAD_PATA_IORDY__CAN2_RXCAN */ - IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 7, 0x000, 0), /* MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 */ - IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 0, 0x000, 0), /* MX53_PAD_PATA_DA_0__PATA_DA_0 */ - IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 1, 0x000, 0), /* MX53_PAD_PATA_DA_0__GPIO7_6 */ - IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 2, 0x000, 0), /* MX53_PAD_PATA_DA_0__ESDHC3_RST */ - IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 4, 0x864, 0), /* MX53_PAD_PATA_DA_0__OWIRE_LINE */ - IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 7, 0x000, 0), /* MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 */ - IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 0, 0x000, 0), /* MX53_PAD_PATA_DA_1__PATA_DA_1 */ - IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 1, 0x000, 0), /* MX53_PAD_PATA_DA_1__GPIO7_7 */ - IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 2, 0x000, 0), /* MX53_PAD_PATA_DA_1__ESDHC4_CMD */ - IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 4, 0x000, 0), /* MX53_PAD_PATA_DA_1__UART3_CTS */ - IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 7, 0x000, 0), /* MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 */ - IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 0, 0x000, 0), /* MX53_PAD_PATA_DA_2__PATA_DA_2 */ - IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 1, 0x000, 0), /* MX53_PAD_PATA_DA_2__GPIO7_8 */ - IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 2, 0x000, 0), /* MX53_PAD_PATA_DA_2__ESDHC4_CLK */ - IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 4, 0x884, 5), /* MX53_PAD_PATA_DA_2__UART3_RTS */ - IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 7, 0x000, 0), /* MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 */ - IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 0, 0x000, 0), /* MX53_PAD_PATA_CS_0__PATA_CS_0 */ - IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 1, 0x000, 0), /* MX53_PAD_PATA_CS_0__GPIO7_9 */ - IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 4, 0x000, 0), /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 7, 0x000, 0), /* MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 */ - IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 0, 0x000, 0), /* MX53_PAD_PATA_CS_1__PATA_CS_1 */ - IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 1, 0x000, 0), /* MX53_PAD_PATA_CS_1__GPIO7_10 */ - IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 4, 0x888, 3), /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 7, 0x000, 0), /* MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA0__PATA_DATA_0 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA0__GPIO2_0 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 7, 0x000, 0), /* MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA1__PATA_DATA_1 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA1__GPIO2_1 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA2__PATA_DATA_2 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA2__GPIO2_2 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA3__PATA_DATA_3 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA3__GPIO2_3 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA4__PATA_DATA_4 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA4__GPIO2_4 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA4__ESDHC4_DAT4 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA5__PATA_DATA_5 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA5__GPIO2_5 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA5__ESDHC4_DAT5 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA6__PATA_DATA_6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA6__GPIO2_6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA6__ESDHC4_DAT6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA7__PATA_DATA_7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA7__GPIO2_7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA7__ESDHC4_DAT7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA8__PATA_DATA_8 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA8__GPIO2_8 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 2, 0x000, 0), /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA9__PATA_DATA_9 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA9__GPIO2_9 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 2, 0x000, 0), /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA10__PATA_DATA_10 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA10__GPIO2_10 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 2, 0x000, 0), /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA11__PATA_DATA_11 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA11__GPIO2_11 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 2, 0x000, 0), /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA12__PATA_DATA_12 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA12__GPIO2_12 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 2, 0x000, 0), /* MX53_PAD_PATA_DATA12__ESDHC2_DAT4 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA12__ESDHC4_DAT0 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA13__PATA_DATA_13 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA13__GPIO2_13 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 2, 0x000, 0), /* MX53_PAD_PATA_DATA13__ESDHC2_DAT5 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA13__ESDHC4_DAT1 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA14__PATA_DATA_14 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA14__GPIO2_14 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 2, 0x000, 0), /* MX53_PAD_PATA_DATA14__ESDHC2_DAT6 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA14__ESDHC4_DAT2 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA15__PATA_DATA_15 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA15__GPIO2_15 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 2, 0x000, 0), /* MX53_PAD_PATA_DATA15__ESDHC2_DAT7 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA15__ESDHC4_DAT3 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 */ - IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 0, 0x000, 0), /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 1, 0x000, 0), /* MX53_PAD_SD1_DATA0__GPIO1_16 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 3, 0x000, 0), /* MX53_PAD_SD1_DATA0__GPT_CAPIN1 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 5, 0x784, 2), /* MX53_PAD_SD1_DATA0__CSPI_MISO */ - IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 7, 0x778, 0), /* MX53_PAD_SD1_DATA0__CCM_PLL3_BYP */ - IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 0, 0x000, 0), /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 1, 0x000, 0), /* MX53_PAD_SD1_DATA1__GPIO1_17 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 3, 0x000, 0), /* MX53_PAD_SD1_DATA1__GPT_CAPIN2 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 5, 0x78C, 3), /* MX53_PAD_SD1_DATA1__CSPI_SS0 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 7, 0x77C, 1), /* MX53_PAD_SD1_DATA1__CCM_PLL4_BYP */ - IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 0, 0x000, 0), /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ - IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 1, 0x000, 0), /* MX53_PAD_SD1_CMD__GPIO1_18 */ - IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 3, 0x000, 0), /* MX53_PAD_SD1_CMD__GPT_CMPOUT1 */ - IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 5, 0x788, 2), /* MX53_PAD_SD1_CMD__CSPI_MOSI */ - IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 7, 0x770, 0), /* MX53_PAD_SD1_CMD__CCM_PLL1_BYP */ - IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 0, 0x000, 0), /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 1, 0x000, 0), /* MX53_PAD_SD1_DATA2__GPIO1_19 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 2, 0x000, 0), /* MX53_PAD_SD1_DATA2__GPT_CMPOUT2 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 3, 0x000, 0), /* MX53_PAD_SD1_DATA2__PWM2_PWMO */ - IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 4, 0x000, 0), /* MX53_PAD_SD1_DATA2__WDOG1_WDOG_B */ - IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 5, 0x790, 2), /* MX53_PAD_SD1_DATA2__CSPI_SS1 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 6, 0x000, 0), /* MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB */ - IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 7, 0x774, 0), /* MX53_PAD_SD1_DATA2__CCM_PLL2_BYP */ - IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 0, 0x000, 0), /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ - IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 1, 0x000, 0), /* MX53_PAD_SD1_CLK__GPIO1_20 */ - IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 2, 0x000, 0), /* MX53_PAD_SD1_CLK__OSC32k_32K_OUT */ - IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 3, 0x000, 0), /* MX53_PAD_SD1_CLK__GPT_CLKIN */ - IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 5, 0x780, 2), /* MX53_PAD_SD1_CLK__CSPI_SCLK */ - IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 7, 0x000, 0), /* MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 0, 0x000, 0), /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 1, 0x000, 0), /* MX53_PAD_SD1_DATA3__GPIO1_21 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 2, 0x000, 0), /* MX53_PAD_SD1_DATA3__GPT_CMPOUT3 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 3, 0x000, 0), /* MX53_PAD_SD1_DATA3__PWM1_PWMO */ - IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 4, 0x000, 0), /* MX53_PAD_SD1_DATA3__WDOG2_WDOG_B */ - IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 5, 0x794, 2), /* MX53_PAD_SD1_DATA3__CSPI_SS2 */ - IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 6, 0x000, 0), /* MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB */ - IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 7, 0x000, 0), /* MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 */ - IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 0, 0x000, 0), /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ - IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 1, 0x000, 0), /* MX53_PAD_SD2_CLK__GPIO1_10 */ - IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 2, 0x840, 2), /* MX53_PAD_SD2_CLK__KPP_COL_5 */ - IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 3, 0x73C, 1), /* MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */ - IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 5, 0x780, 3), /* MX53_PAD_SD2_CLK__CSPI_SCLK */ - IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 7, 0x000, 0), /* MX53_PAD_SD2_CLK__SCC_RANDOM_V */ - IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 0, 0x000, 0), /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ - IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 1, 0x000, 0), /* MX53_PAD_SD2_CMD__GPIO1_11 */ - IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 2, 0x84C, 1), /* MX53_PAD_SD2_CMD__KPP_ROW_5 */ - IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 3, 0x738, 1), /* MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC */ - IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 5, 0x788, 3), /* MX53_PAD_SD2_CMD__CSPI_MOSI */ - IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 7, 0x000, 0), /* MX53_PAD_SD2_CMD__SCC_RANDOM */ - IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 0, 0x000, 0), /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 1, 0x000, 0), /* MX53_PAD_SD2_DATA3__GPIO1_12 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 2, 0x844, 1), /* MX53_PAD_SD2_DATA3__KPP_COL_6 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 3, 0x740, 1), /* MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC */ - IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 5, 0x794, 3), /* MX53_PAD_SD2_DATA3__CSPI_SS2 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 7, 0x000, 0), /* MX53_PAD_SD2_DATA3__SJC_DONE */ - IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 0, 0x000, 0), /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 1, 0x000, 0), /* MX53_PAD_SD2_DATA2__GPIO1_13 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 2, 0x850, 1), /* MX53_PAD_SD2_DATA2__KPP_ROW_6 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 3, 0x734, 1), /* MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD */ - IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 5, 0x790, 3), /* MX53_PAD_SD2_DATA2__CSPI_SS1 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 7, 0x000, 0), /* MX53_PAD_SD2_DATA2__SJC_FAIL */ - IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 0, 0x000, 0), /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 1, 0x000, 0), /* MX53_PAD_SD2_DATA1__GPIO1_14 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 2, 0x848, 1), /* MX53_PAD_SD2_DATA1__KPP_COL_7 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 3, 0x744, 0), /* MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS */ - IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 5, 0x78C, 4), /* MX53_PAD_SD2_DATA1__CSPI_SS0 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 7, 0x000, 0), /* MX53_PAD_SD2_DATA1__RTIC_SEC_VIO */ - IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 0, 0x000, 0), /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 1, 0x000, 0), /* MX53_PAD_SD2_DATA0__GPIO1_15 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 2, 0x854, 1), /* MX53_PAD_SD2_DATA0__KPP_ROW_7 */ - IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 3, 0x730, 1), /* MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD */ - IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 5, 0x784, 3), /* MX53_PAD_SD2_DATA0__CSPI_MISO */ - IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 7, 0x000, 0), /* MX53_PAD_SD2_DATA0__RTIC_DONE_INT */ - IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 0, 0x000, 0), /* MX53_PAD_GPIO_0__CCM_CLKO */ - IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 1, 0x000, 0), /* MX53_PAD_GPIO_0__GPIO1_0 */ - IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 2, 0x840, 3), /* MX53_PAD_GPIO_0__KPP_COL_5 */ - IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 3, 0x000, 0), /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */ - IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 4, 0x000, 0), /* MX53_PAD_GPIO_0__EPIT1_EPITO */ - IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 5, 0x000, 0), /* MX53_PAD_GPIO_0__SRTC_ALARM_DEB */ - IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 6, 0x000, 0), /* MX53_PAD_GPIO_0__USBOH3_USBH1_PWR */ - IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 7, 0x000, 0), /* MX53_PAD_GPIO_0__CSU_TD */ - IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 0, 0x7DC, 1), /* MX53_PAD_GPIO_1__ESAI1_SCKR */ - IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 1, 0x000, 0), /* MX53_PAD_GPIO_1__GPIO1_1 */ - IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 2, 0x84C, 2), /* MX53_PAD_GPIO_1__KPP_ROW_5 */ - IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 3, 0x000, 0), /* MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK */ - IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 4, 0x000, 0), /* MX53_PAD_GPIO_1__PWM2_PWMO */ - IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 5, 0x000, 0), /* MX53_PAD_GPIO_1__WDOG2_WDOG_B */ - IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 6, 0x000, 0), /* MX53_PAD_GPIO_1__ESDHC1_CD */ - IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 7, 0x000, 0), /* MX53_PAD_GPIO_1__SRC_TESTER_ACK */ - IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 0, 0x7CC, 1), /* MX53_PAD_GPIO_9__ESAI1_FSR */ - IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 1, 0x000, 0), /* MX53_PAD_GPIO_9__GPIO1_9 */ - IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 2, 0x844, 2), /* MX53_PAD_GPIO_9__KPP_COL_6 */ - IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 3, 0x000, 0), /* MX53_PAD_GPIO_9__CCM_REF_EN_B */ - IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 4, 0x000, 0), /* MX53_PAD_GPIO_9__PWM1_PWMO */ - IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 5, 0x000, 0), /* MX53_PAD_GPIO_9__WDOG1_WDOG_B */ - IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 6, 0x7FC, 1), /* MX53_PAD_GPIO_9__ESDHC1_WP */ - IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 7, 0x000, 0), /* MX53_PAD_GPIO_9__SCC_FAIL_STATE */ - IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 0, 0x7D4, 1), /* MX53_PAD_GPIO_3__ESAI1_HCKR */ - IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 1, 0x000, 0), /* MX53_PAD_GPIO_3__GPIO1_3 */ - IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 2, 0x824, 1), /* MX53_PAD_GPIO_3__I2C3_SCL */ - IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 3, 0x000, 0), /* MX53_PAD_GPIO_3__DPLLIP1_TOG_EN */ - IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 4, 0x000, 0), /* MX53_PAD_GPIO_3__CCM_CLKO2 */ - IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 5, 0x000, 0), /* MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 */ - IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 6, 0x8A0, 1), /* MX53_PAD_GPIO_3__USBOH3_USBH1_OC */ - IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 7, 0x858, 2), /* MX53_PAD_GPIO_3__MLB_MLBCLK */ - IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 0, 0x7E0, 1), /* MX53_PAD_GPIO_6__ESAI1_SCKT */ - IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 1, 0x000, 0), /* MX53_PAD_GPIO_6__GPIO1_6 */ - IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 2, 0x828, 1), /* MX53_PAD_GPIO_6__I2C3_SDA */ - IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 3, 0x000, 0), /* MX53_PAD_GPIO_6__CCM_CCM_OUT_0 */ - IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 4, 0x000, 0), /* MX53_PAD_GPIO_6__CSU_CSU_INT_DEB */ - IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 5, 0x000, 0), /* MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 */ - IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 6, 0x000, 0), /* MX53_PAD_GPIO_6__ESDHC2_LCTL */ - IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 7, 0x860, 2), /* MX53_PAD_GPIO_6__MLB_MLBSIG */ - IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 0, 0x7D0, 1), /* MX53_PAD_GPIO_2__ESAI1_FST */ - IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 1, 0x000, 0), /* MX53_PAD_GPIO_2__GPIO1_2 */ - IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 2, 0x850, 2), /* MX53_PAD_GPIO_2__KPP_ROW_6 */ - IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 3, 0x000, 0), /* MX53_PAD_GPIO_2__CCM_CCM_OUT_1 */ - IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 4, 0x000, 0), /* MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */ - IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 5, 0x000, 0), /* MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 */ - IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 6, 0x000, 0), /* MX53_PAD_GPIO_2__ESDHC2_WP */ - IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 7, 0x85C, 2), /* MX53_PAD_GPIO_2__MLB_MLBDAT */ - IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 0, 0x7D8, 1), /* MX53_PAD_GPIO_4__ESAI1_HCKT */ - IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 1, 0x000, 0), /* MX53_PAD_GPIO_4__GPIO1_4 */ - IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 2, 0x848, 2), /* MX53_PAD_GPIO_4__KPP_COL_7 */ - IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 3, 0x000, 0), /* MX53_PAD_GPIO_4__CCM_CCM_OUT_2 */ - IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 4, 0x000, 0), /* MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */ - IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 5, 0x000, 0), /* MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 */ - IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 6, 0x000, 0), /* MX53_PAD_GPIO_4__ESDHC2_CD */ - IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 7, 0x000, 0), /* MX53_PAD_GPIO_4__SCC_SEC_STATE */ - IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 0, 0x7EC, 1), /* MX53_PAD_GPIO_5__ESAI1_TX2_RX3 */ - IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 1, 0x000, 0), /* MX53_PAD_GPIO_5__GPIO1_5 */ - IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 2, 0x854, 2), /* MX53_PAD_GPIO_5__KPP_ROW_7 */ - IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 3, 0x000, 0), /* MX53_PAD_GPIO_5__CCM_CLKO */ - IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 4, 0x000, 0), /* MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */ - IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 5, 0x000, 0), /* MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 */ - IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 6, 0x824, 2), /* MX53_PAD_GPIO_5__I2C3_SCL */ - IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 7, 0x770, 1), /* MX53_PAD_GPIO_5__CCM_PLL1_BYP */ - IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 0, 0x7F4, 1), /* MX53_PAD_GPIO_7__ESAI1_TX4_RX1 */ - IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 1, 0x000, 0), /* MX53_PAD_GPIO_7__GPIO1_7 */ - IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 2, 0x000, 0), /* MX53_PAD_GPIO_7__EPIT1_EPITO */ - IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 3, 0x000, 0), /* MX53_PAD_GPIO_7__CAN1_TXCAN */ - IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 4, 0x000, 0), /* MX53_PAD_GPIO_7__UART2_TXD_MUX */ - IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 5, 0x80C, 1), /* MX53_PAD_GPIO_7__FIRI_RXD */ - IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 6, 0x000, 0), /* MX53_PAD_GPIO_7__SPDIF_PLOCK */ - IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 7, 0x774, 1), /* MX53_PAD_GPIO_7__CCM_PLL2_BYP */ - IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 0, 0x7F8, 1), /* MX53_PAD_GPIO_8__ESAI1_TX5_RX0 */ - IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 1, 0x000, 0), /* MX53_PAD_GPIO_8__GPIO1_8 */ - IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 2, 0x000, 0), /* MX53_PAD_GPIO_8__EPIT2_EPITO */ - IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 3, 0x760, 2), /* MX53_PAD_GPIO_8__CAN1_RXCAN */ - IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 4, 0x880, 5), /* MX53_PAD_GPIO_8__UART2_RXD_MUX */ - IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 5, 0x000, 0), /* MX53_PAD_GPIO_8__FIRI_TXD */ - IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 6, 0x000, 0), /* MX53_PAD_GPIO_8__SPDIF_SRCLK */ - IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 7, 0x778, 1), /* MX53_PAD_GPIO_8__CCM_PLL3_BYP */ - IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 0, 0x7F0, 1), /* MX53_PAD_GPIO_16__ESAI1_TX3_RX2 */ - IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 1, 0x000, 0), /* MX53_PAD_GPIO_16__GPIO7_11 */ - IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 2, 0x000, 0), /* MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT */ - IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 4, 0x000, 0), /* MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 */ - IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 5, 0x870, 1), /* MX53_PAD_GPIO_16__SPDIF_IN1 */ - IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 6, 0x828, 2), /* MX53_PAD_GPIO_16__I2C3_SDA */ - IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 7, 0x000, 0), /* MX53_PAD_GPIO_16__SJC_DE_B */ - IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 0, 0x7E4, 1), /* MX53_PAD_GPIO_17__ESAI1_TX0 */ - IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 1, 0x000, 0), /* MX53_PAD_GPIO_17__GPIO7_12 */ - IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 2, 0x868, 1), /* MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 */ - IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 3, 0x810, 1), /* MX53_PAD_GPIO_17__GPC_PMIC_RDY */ - IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 4, 0x000, 0), /* MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG */ - IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 5, 0x000, 0), /* MX53_PAD_GPIO_17__SPDIF_OUT1 */ - IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 6, 0x000, 0), /* MX53_PAD_GPIO_17__IPU_SNOOP2 */ - IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 7, 0x000, 0), /* MX53_PAD_GPIO_17__SJC_JTAG_ACT */ - IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 0, 0x7E8, 1), /* MX53_PAD_GPIO_18__ESAI1_TX1 */ - IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 1, 0x000, 0), /* MX53_PAD_GPIO_18__GPIO7_13 */ - IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 2, 0x86C, 1), /* MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 */ - IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 3, 0x864, 1), /* MX53_PAD_GPIO_18__OWIRE_LINE */ - IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 4, 0x000, 0), /* MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG */ - IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 5, 0x768, 1), /* MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK */ - IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 6, 0x000, 0), /* MX53_PAD_GPIO_18__ESDHC1_LCTL */ - IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 7, 0x000, 0), /* MX53_PAD_GPIO_18__SRC_SYSTEM_RST */ + MX53_PAD_RESERVE0 = 0, + MX53_PAD_RESERVE1 = 1, + MX53_PAD_RESERVE2 = 2, + MX53_PAD_RESERVE3 = 3, + MX53_PAD_RESERVE4 = 4, + MX53_PAD_RESERVE5 = 5, + MX53_PAD_RESERVE6 = 6, + MX53_PAD_RESERVE7 = 7, + MX53_PAD_GPIO_19 = 8, + MX53_PAD_KEY_COL0 = 9, + MX53_PAD_KEY_ROW0 = 10, + MX53_PAD_KEY_COL1 = 11, + MX53_PAD_KEY_ROW1 = 12, + MX53_PAD_KEY_COL2 = 13, + MX53_PAD_KEY_ROW2 = 14, + MX53_PAD_KEY_COL3 = 15, + MX53_PAD_KEY_ROW3 = 16, + MX53_PAD_KEY_COL4 = 17, + MX53_PAD_KEY_ROW4 = 18, + MX53_PAD_DI0_DISP_CLK = 19, + MX53_PAD_DI0_PIN15 = 20, + MX53_PAD_DI0_PIN2 = 21, + MX53_PAD_DI0_PIN3 = 22, + MX53_PAD_DI0_PIN4 = 23, + MX53_PAD_DISP0_DAT0 = 24, + MX53_PAD_DISP0_DAT1 = 25, + MX53_PAD_DISP0_DAT2 = 26, + MX53_PAD_DISP0_DAT3 = 27, + MX53_PAD_DISP0_DAT4 = 28, + MX53_PAD_DISP0_DAT5 = 29, + MX53_PAD_DISP0_DAT6 = 30, + MX53_PAD_DISP0_DAT7 = 31, + MX53_PAD_DISP0_DAT8 = 32, + MX53_PAD_DISP0_DAT9 = 33, + MX53_PAD_DISP0_DAT10 = 34, + MX53_PAD_DISP0_DAT11 = 35, + MX53_PAD_DISP0_DAT12 = 36, + MX53_PAD_DISP0_DAT13 = 37, + MX53_PAD_DISP0_DAT14 = 38, + MX53_PAD_DISP0_DAT15 = 39, + MX53_PAD_DISP0_DAT16 = 40, + MX53_PAD_DISP0_DAT17 = 41, + MX53_PAD_DISP0_DAT18 = 42, + MX53_PAD_DISP0_DAT19 = 43, + MX53_PAD_DISP0_DAT20 = 44, + MX53_PAD_DISP0_DAT21 = 45, + MX53_PAD_DISP0_DAT22 = 46, + MX53_PAD_DISP0_DAT23 = 47, + MX53_PAD_CSI0_PIXCLK = 48, + MX53_PAD_CSI0_MCLK = 49, + MX53_PAD_CSI0_DATA_EN = 50, + MX53_PAD_CSI0_VSYNC = 51, + MX53_PAD_CSI0_DAT4 = 52, + MX53_PAD_CSI0_DAT5 = 53, + MX53_PAD_CSI0_DAT6 = 54, + MX53_PAD_CSI0_DAT7 = 55, + MX53_PAD_CSI0_DAT8 = 56, + MX53_PAD_CSI0_DAT9 = 57, + MX53_PAD_CSI0_DAT10 = 58, + MX53_PAD_CSI0_DAT11 = 59, + MX53_PAD_CSI0_DAT12 = 60, + MX53_PAD_CSI0_DAT13 = 61, + MX53_PAD_CSI0_DAT14 = 62, + MX53_PAD_CSI0_DAT15 = 63, + MX53_PAD_CSI0_DAT16 = 64, + MX53_PAD_CSI0_DAT17 = 65, + MX53_PAD_CSI0_DAT18 = 66, + MX53_PAD_CSI0_DAT19 = 67, + MX53_PAD_EIM_A25 = 68, + MX53_PAD_EIM_EB2 = 69, + MX53_PAD_EIM_D16 = 70, + MX53_PAD_EIM_D17 = 71, + MX53_PAD_EIM_D18 = 72, + MX53_PAD_EIM_D19 = 73, + MX53_PAD_EIM_D20 = 74, + MX53_PAD_EIM_D21 = 75, + MX53_PAD_EIM_D22 = 76, + MX53_PAD_EIM_D23 = 77, + MX53_PAD_EIM_EB3 = 78, + MX53_PAD_EIM_D24 = 79, + MX53_PAD_EIM_D25 = 80, + MX53_PAD_EIM_D26 = 81, + MX53_PAD_EIM_D27 = 82, + MX53_PAD_EIM_D28 = 83, + MX53_PAD_EIM_D29 = 84, + MX53_PAD_EIM_D30 = 85, + MX53_PAD_EIM_D31 = 86, + MX53_PAD_EIM_A24 = 87, + MX53_PAD_EIM_A23 = 88, + MX53_PAD_EIM_A22 = 89, + MX53_PAD_EIM_A21 = 90, + MX53_PAD_EIM_A20 = 91, + MX53_PAD_EIM_A19 = 92, + MX53_PAD_EIM_A18 = 93, + MX53_PAD_EIM_A17 = 94, + MX53_PAD_EIM_A16 = 95, + MX53_PAD_EIM_CS0 = 96, + MX53_PAD_EIM_CS1 = 97, + MX53_PAD_EIM_OE = 98, + MX53_PAD_EIM_RW = 99, + MX53_PAD_EIM_LBA = 100, + MX53_PAD_EIM_EB0 = 101, + MX53_PAD_EIM_EB1 = 102, + MX53_PAD_EIM_DA0 = 103, + MX53_PAD_EIM_DA1 = 104, + MX53_PAD_EIM_DA2 = 105, + MX53_PAD_EIM_DA3 = 106, + MX53_PAD_EIM_DA4 = 107, + MX53_PAD_EIM_DA5 = 108, + MX53_PAD_EIM_DA6 = 109, + MX53_PAD_EIM_DA7 = 110, + MX53_PAD_EIM_DA8 = 111, + MX53_PAD_EIM_DA9 = 112, + MX53_PAD_EIM_DA10 = 113, + MX53_PAD_EIM_DA11 = 114, + MX53_PAD_EIM_DA12 = 115, + MX53_PAD_EIM_DA13 = 116, + MX53_PAD_EIM_DA14 = 117, + MX53_PAD_EIM_DA15 = 118, + MX53_PAD_NANDF_WE_B = 119, + MX53_PAD_NANDF_RE_B = 120, + MX53_PAD_EIM_WAIT = 121, + MX53_PAD_RESERVE8 = 122, + MX53_PAD_LVDS1_TX3_P = 123, + MX53_PAD_LVDS1_TX2_P = 124, + MX53_PAD_LVDS1_CLK_P = 125, + MX53_PAD_LVDS1_TX1_P = 126, + MX53_PAD_LVDS1_TX0_P = 127, + MX53_PAD_LVDS0_TX3_P = 128, + MX53_PAD_LVDS0_CLK_P = 129, + MX53_PAD_LVDS0_TX2_P = 130, + MX53_PAD_LVDS0_TX1_P = 131, + MX53_PAD_LVDS0_TX0_P = 132, + MX53_PAD_GPIO_10 = 133, + MX53_PAD_GPIO_11 = 134, + MX53_PAD_GPIO_12 = 135, + MX53_PAD_GPIO_13 = 136, + MX53_PAD_GPIO_14 = 137, + MX53_PAD_NANDF_CLE = 138, + MX53_PAD_NANDF_ALE = 139, + MX53_PAD_NANDF_WP_B = 140, + MX53_PAD_NANDF_RB0 = 141, + MX53_PAD_NANDF_CS0 = 142, + MX53_PAD_NANDF_CS1 = 143, + MX53_PAD_NANDF_CS2 = 144, + MX53_PAD_NANDF_CS3 = 145, + MX53_PAD_FEC_MDIO = 146, + MX53_PAD_FEC_REF_CLK = 147, + MX53_PAD_FEC_RX_ER = 148, + MX53_PAD_FEC_CRS_DV = 149, + MX53_PAD_FEC_RXD1 = 150, + MX53_PAD_FEC_RXD0 = 151, + MX53_PAD_FEC_TX_EN = 152, + MX53_PAD_FEC_TXD1 = 153, + MX53_PAD_FEC_TXD0 = 154, + MX53_PAD_FEC_MDC = 155, + MX53_PAD_PATA_DIOW = 156, + MX53_PAD_PATA_DMACK = 157, + MX53_PAD_PATA_DMARQ = 158, + MX53_PAD_PATA_BUFFER_EN = 159, + MX53_PAD_PATA_INTRQ = 160, + MX53_PAD_PATA_DIOR = 161, + MX53_PAD_PATA_RESET_B = 162, + MX53_PAD_PATA_IORDY = 163, + MX53_PAD_PATA_DA_0 = 164, + MX53_PAD_PATA_DA_1 = 165, + MX53_PAD_PATA_DA_2 = 166, + MX53_PAD_PATA_CS_0 = 167, + MX53_PAD_PATA_CS_1 = 168, + MX53_PAD_PATA_DATA0 = 169, + MX53_PAD_PATA_DATA1 = 170, + MX53_PAD_PATA_DATA2 = 171, + MX53_PAD_PATA_DATA3 = 172, + MX53_PAD_PATA_DATA4 = 173, + MX53_PAD_PATA_DATA5 = 174, + MX53_PAD_PATA_DATA6 = 175, + MX53_PAD_PATA_DATA7 = 176, + MX53_PAD_PATA_DATA8 = 177, + MX53_PAD_PATA_DATA9 = 178, + MX53_PAD_PATA_DATA10 = 179, + MX53_PAD_PATA_DATA11 = 180, + MX53_PAD_PATA_DATA12 = 181, + MX53_PAD_PATA_DATA13 = 182, + MX53_PAD_PATA_DATA14 = 183, + MX53_PAD_PATA_DATA15 = 184, + MX53_PAD_SD1_DATA0 = 185, + MX53_PAD_SD1_DATA1 = 186, + MX53_PAD_SD1_CMD = 187, + MX53_PAD_SD1_DATA2 = 188, + MX53_PAD_SD1_CLK = 189, + MX53_PAD_SD1_DATA3 = 190, + MX53_PAD_SD2_CLK = 191, + MX53_PAD_SD2_CMD = 192, + MX53_PAD_SD2_DATA3 = 193, + MX53_PAD_SD2_DATA2 = 194, + MX53_PAD_SD2_DATA1 = 195, + MX53_PAD_SD2_DATA0 = 196, + MX53_PAD_GPIO_0 = 197, + MX53_PAD_GPIO_1 = 198, + MX53_PAD_GPIO_9 = 199, + MX53_PAD_GPIO_3 = 200, + MX53_PAD_GPIO_6 = 201, + MX53_PAD_GPIO_2 = 202, + MX53_PAD_GPIO_4 = 203, + MX53_PAD_GPIO_5 = 204, + MX53_PAD_GPIO_7 = 205, + MX53_PAD_GPIO_8 = 206, + MX53_PAD_GPIO_16 = 207, + MX53_PAD_GPIO_17 = 208, + MX53_PAD_GPIO_18 = 209, }; /* Pad names for the pinmux subsystem */ static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX53_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE7), IMX_PINCTRL_PIN(MX53_PAD_GPIO_19), IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0), IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0), @@ -1517,6 +359,7 @@ static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B), IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B), IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT), + IMX_PINCTRL_PIN(MX53_PAD_RESERVE8), IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P), IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P), IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P), @@ -1609,8 +452,6 @@ static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = { static struct imx_pinctrl_soc_info imx53_pinctrl_info = { .pins = imx53_pinctrl_pads, .npins = ARRAY_SIZE(imx53_pinctrl_pads), - .pin_regs = imx53_pin_regs, - .npin_regs = ARRAY_SIZE(imx53_pin_regs), }; static struct of_device_id imx53_pinctrl_of_match[] = { @@ -1627,7 +468,7 @@ static struct platform_driver imx53_pinctrl_driver = { .driver = { .name = "imx53-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx53_pinctrl_of_match), + .of_match_table = imx53_pinctrl_of_match, }, .probe = imx53_pinctrl_probe, .remove = imx_pinctrl_remove, diff --git a/drivers/pinctrl/pinctrl-imx6dl.c b/drivers/pinctrl/pinctrl-imx6dl.c new file mode 100644 index 00000000000..db2a1489bd9 --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx6dl.c @@ -0,0 +1,497 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum imx6dl_pads { + MX6DL_PAD_RESERVE0 = 0, + MX6DL_PAD_RESERVE1 = 1, + MX6DL_PAD_RESERVE2 = 2, + MX6DL_PAD_RESERVE3 = 3, + MX6DL_PAD_RESERVE4 = 4, + MX6DL_PAD_RESERVE5 = 5, + MX6DL_PAD_RESERVE6 = 6, + MX6DL_PAD_RESERVE7 = 7, + MX6DL_PAD_RESERVE8 = 8, + MX6DL_PAD_RESERVE9 = 9, + MX6DL_PAD_RESERVE10 = 10, + MX6DL_PAD_RESERVE11 = 11, + MX6DL_PAD_RESERVE12 = 12, + MX6DL_PAD_RESERVE13 = 13, + MX6DL_PAD_RESERVE14 = 14, + MX6DL_PAD_RESERVE15 = 15, + MX6DL_PAD_RESERVE16 = 16, + MX6DL_PAD_RESERVE17 = 17, + MX6DL_PAD_RESERVE18 = 18, + MX6DL_PAD_CSI0_DAT10 = 19, + MX6DL_PAD_CSI0_DAT11 = 20, + MX6DL_PAD_CSI0_DAT12 = 21, + MX6DL_PAD_CSI0_DAT13 = 22, + MX6DL_PAD_CSI0_DAT14 = 23, + MX6DL_PAD_CSI0_DAT15 = 24, + MX6DL_PAD_CSI0_DAT16 = 25, + MX6DL_PAD_CSI0_DAT17 = 26, + MX6DL_PAD_CSI0_DAT18 = 27, + MX6DL_PAD_CSI0_DAT19 = 28, + MX6DL_PAD_CSI0_DAT4 = 29, + MX6DL_PAD_CSI0_DAT5 = 30, + MX6DL_PAD_CSI0_DAT6 = 31, + MX6DL_PAD_CSI0_DAT7 = 32, + MX6DL_PAD_CSI0_DAT8 = 33, + MX6DL_PAD_CSI0_DAT9 = 34, + MX6DL_PAD_CSI0_DATA_EN = 35, + MX6DL_PAD_CSI0_MCLK = 36, + MX6DL_PAD_CSI0_PIXCLK = 37, + MX6DL_PAD_CSI0_VSYNC = 38, + MX6DL_PAD_DI0_DISP_CLK = 39, + MX6DL_PAD_DI0_PIN15 = 40, + MX6DL_PAD_DI0_PIN2 = 41, + MX6DL_PAD_DI0_PIN3 = 42, + MX6DL_PAD_DI0_PIN4 = 43, + MX6DL_PAD_DISP0_DAT0 = 44, + MX6DL_PAD_DISP0_DAT1 = 45, + MX6DL_PAD_DISP0_DAT10 = 46, + MX6DL_PAD_DISP0_DAT11 = 47, + MX6DL_PAD_DISP0_DAT12 = 48, + MX6DL_PAD_DISP0_DAT13 = 49, + MX6DL_PAD_DISP0_DAT14 = 50, + MX6DL_PAD_DISP0_DAT15 = 51, + MX6DL_PAD_DISP0_DAT16 = 52, + MX6DL_PAD_DISP0_DAT17 = 53, + MX6DL_PAD_DISP0_DAT18 = 54, + MX6DL_PAD_DISP0_DAT19 = 55, + MX6DL_PAD_DISP0_DAT2 = 56, + MX6DL_PAD_DISP0_DAT20 = 57, + MX6DL_PAD_DISP0_DAT21 = 58, + MX6DL_PAD_DISP0_DAT22 = 59, + MX6DL_PAD_DISP0_DAT23 = 60, + MX6DL_PAD_DISP0_DAT3 = 61, + MX6DL_PAD_DISP0_DAT4 = 62, + MX6DL_PAD_DISP0_DAT5 = 63, + MX6DL_PAD_DISP0_DAT6 = 64, + MX6DL_PAD_DISP0_DAT7 = 65, + MX6DL_PAD_DISP0_DAT8 = 66, + MX6DL_PAD_DISP0_DAT9 = 67, + MX6DL_PAD_EIM_A16 = 68, + MX6DL_PAD_EIM_A17 = 69, + MX6DL_PAD_EIM_A18 = 70, + MX6DL_PAD_EIM_A19 = 71, + MX6DL_PAD_EIM_A20 = 72, + MX6DL_PAD_EIM_A21 = 73, + MX6DL_PAD_EIM_A22 = 74, + MX6DL_PAD_EIM_A23 = 75, + MX6DL_PAD_EIM_A24 = 76, + MX6DL_PAD_EIM_A25 = 77, + MX6DL_PAD_EIM_BCLK = 78, + MX6DL_PAD_EIM_CS0 = 79, + MX6DL_PAD_EIM_CS1 = 80, + MX6DL_PAD_EIM_D16 = 81, + MX6DL_PAD_EIM_D17 = 82, + MX6DL_PAD_EIM_D18 = 83, + MX6DL_PAD_EIM_D19 = 84, + MX6DL_PAD_EIM_D20 = 85, + MX6DL_PAD_EIM_D21 = 86, + MX6DL_PAD_EIM_D22 = 87, + MX6DL_PAD_EIM_D23 = 88, + MX6DL_PAD_EIM_D24 = 89, + MX6DL_PAD_EIM_D25 = 90, + MX6DL_PAD_EIM_D26 = 91, + MX6DL_PAD_EIM_D27 = 92, + MX6DL_PAD_EIM_D28 = 93, + MX6DL_PAD_EIM_D29 = 94, + MX6DL_PAD_EIM_D30 = 95, + MX6DL_PAD_EIM_D31 = 96, + MX6DL_PAD_EIM_DA0 = 97, + MX6DL_PAD_EIM_DA1 = 98, + MX6DL_PAD_EIM_DA10 = 99, + MX6DL_PAD_EIM_DA11 = 100, + MX6DL_PAD_EIM_DA12 = 101, + MX6DL_PAD_EIM_DA13 = 102, + MX6DL_PAD_EIM_DA14 = 103, + MX6DL_PAD_EIM_DA15 = 104, + MX6DL_PAD_EIM_DA2 = 105, + MX6DL_PAD_EIM_DA3 = 106, + MX6DL_PAD_EIM_DA4 = 107, + MX6DL_PAD_EIM_DA5 = 108, + MX6DL_PAD_EIM_DA6 = 109, + MX6DL_PAD_EIM_DA7 = 110, + MX6DL_PAD_EIM_DA8 = 111, + MX6DL_PAD_EIM_DA9 = 112, + MX6DL_PAD_EIM_EB0 = 113, + MX6DL_PAD_EIM_EB1 = 114, + MX6DL_PAD_EIM_EB2 = 115, + MX6DL_PAD_EIM_EB3 = 116, + MX6DL_PAD_EIM_LBA = 117, + MX6DL_PAD_EIM_OE = 118, + MX6DL_PAD_EIM_RW = 119, + MX6DL_PAD_EIM_WAIT = 120, + MX6DL_PAD_ENET_CRS_DV = 121, + MX6DL_PAD_ENET_MDC = 122, + MX6DL_PAD_ENET_MDIO = 123, + MX6DL_PAD_ENET_REF_CLK = 124, + MX6DL_PAD_ENET_RX_ER = 125, + MX6DL_PAD_ENET_RXD0 = 126, + MX6DL_PAD_ENET_RXD1 = 127, + MX6DL_PAD_ENET_TX_EN = 128, + MX6DL_PAD_ENET_TXD0 = 129, + MX6DL_PAD_ENET_TXD1 = 130, + MX6DL_PAD_GPIO_0 = 131, + MX6DL_PAD_GPIO_1 = 132, + MX6DL_PAD_GPIO_16 = 133, + MX6DL_PAD_GPIO_17 = 134, + MX6DL_PAD_GPIO_18 = 135, + MX6DL_PAD_GPIO_19 = 136, + MX6DL_PAD_GPIO_2 = 137, + MX6DL_PAD_GPIO_3 = 138, + MX6DL_PAD_GPIO_4 = 139, + MX6DL_PAD_GPIO_5 = 140, + MX6DL_PAD_GPIO_6 = 141, + MX6DL_PAD_GPIO_7 = 142, + MX6DL_PAD_GPIO_8 = 143, + MX6DL_PAD_GPIO_9 = 144, + MX6DL_PAD_KEY_COL0 = 145, + MX6DL_PAD_KEY_COL1 = 146, + MX6DL_PAD_KEY_COL2 = 147, + MX6DL_PAD_KEY_COL3 = 148, + MX6DL_PAD_KEY_COL4 = 149, + MX6DL_PAD_KEY_ROW0 = 150, + MX6DL_PAD_KEY_ROW1 = 151, + MX6DL_PAD_KEY_ROW2 = 152, + MX6DL_PAD_KEY_ROW3 = 153, + MX6DL_PAD_KEY_ROW4 = 154, + MX6DL_PAD_NANDF_ALE = 155, + MX6DL_PAD_NANDF_CLE = 156, + MX6DL_PAD_NANDF_CS0 = 157, + MX6DL_PAD_NANDF_CS1 = 158, + MX6DL_PAD_NANDF_CS2 = 159, + MX6DL_PAD_NANDF_CS3 = 160, + MX6DL_PAD_NANDF_D0 = 161, + MX6DL_PAD_NANDF_D1 = 162, + MX6DL_PAD_NANDF_D2 = 163, + MX6DL_PAD_NANDF_D3 = 164, + MX6DL_PAD_NANDF_D4 = 165, + MX6DL_PAD_NANDF_D5 = 166, + MX6DL_PAD_NANDF_D6 = 167, + MX6DL_PAD_NANDF_D7 = 168, + MX6DL_PAD_NANDF_RB0 = 169, + MX6DL_PAD_NANDF_WP_B = 170, + MX6DL_PAD_RGMII_RD0 = 171, + MX6DL_PAD_RGMII_RD1 = 172, + MX6DL_PAD_RGMII_RD2 = 173, + MX6DL_PAD_RGMII_RD3 = 174, + MX6DL_PAD_RGMII_RX_CTL = 175, + MX6DL_PAD_RGMII_RXC = 176, + MX6DL_PAD_RGMII_TD0 = 177, + MX6DL_PAD_RGMII_TD1 = 178, + MX6DL_PAD_RGMII_TD2 = 179, + MX6DL_PAD_RGMII_TD3 = 180, + MX6DL_PAD_RGMII_TX_CTL = 181, + MX6DL_PAD_RGMII_TXC = 182, + MX6DL_PAD_SD1_CLK = 183, + MX6DL_PAD_SD1_CMD = 184, + MX6DL_PAD_SD1_DAT0 = 185, + MX6DL_PAD_SD1_DAT1 = 186, + MX6DL_PAD_SD1_DAT2 = 187, + MX6DL_PAD_SD1_DAT3 = 188, + MX6DL_PAD_SD2_CLK = 189, + MX6DL_PAD_SD2_CMD = 190, + MX6DL_PAD_SD2_DAT0 = 191, + MX6DL_PAD_SD2_DAT1 = 192, + MX6DL_PAD_SD2_DAT2 = 193, + MX6DL_PAD_SD2_DAT3 = 194, + MX6DL_PAD_SD3_CLK = 195, + MX6DL_PAD_SD3_CMD = 196, + MX6DL_PAD_SD3_DAT0 = 197, + MX6DL_PAD_SD3_DAT1 = 198, + MX6DL_PAD_SD3_DAT2 = 199, + MX6DL_PAD_SD3_DAT3 = 200, + MX6DL_PAD_SD3_DAT4 = 201, + MX6DL_PAD_SD3_DAT5 = 202, + MX6DL_PAD_SD3_DAT6 = 203, + MX6DL_PAD_SD3_DAT7 = 204, + MX6DL_PAD_SD3_RST = 205, + MX6DL_PAD_SD4_CLK = 206, + MX6DL_PAD_SD4_CMD = 207, + MX6DL_PAD_SD4_DAT0 = 208, + MX6DL_PAD_SD4_DAT1 = 209, + MX6DL_PAD_SD4_DAT2 = 210, + MX6DL_PAD_SD4_DAT3 = 211, + MX6DL_PAD_SD4_DAT4 = 212, + MX6DL_PAD_SD4_DAT5 = 213, + MX6DL_PAD_SD4_DAT6 = 214, + MX6DL_PAD_SD4_DAT7 = 215, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE18), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT10), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT11), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT12), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT13), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT14), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT15), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT16), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT17), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT18), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT19), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT4), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT5), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT6), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT7), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT8), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT9), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DATA_EN), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_MCLK), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_PIXCLK), + IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_VSYNC), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_DISP_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN15), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN2), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN3), + IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN4), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT10), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT11), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT12), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT13), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT14), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT15), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT16), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT17), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT18), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT19), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT20), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT21), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT22), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT23), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT4), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT5), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT6), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT7), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT8), + IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT9), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A16), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A17), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A18), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A19), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A20), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A21), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A22), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A23), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A24), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A25), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_BCLK), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS0), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS1), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D16), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D17), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D18), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D19), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D20), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D21), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D22), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D23), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D24), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D25), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D26), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D27), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D28), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D29), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D30), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D31), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA0), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA1), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA10), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA11), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA12), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA13), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA14), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA15), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA2), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA3), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA4), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA5), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA6), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA7), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA8), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA9), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB0), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB1), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB2), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB3), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_LBA), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_OE), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_RW), + IMX_PINCTRL_PIN(MX6DL_PAD_EIM_WAIT), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_CRS_DV), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDC), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDIO), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_REF_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RX_ER), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD0), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD1), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TX_EN), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD0), + IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD1), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_0), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_1), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_16), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_17), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_18), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_19), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_2), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_3), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_4), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_5), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_6), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_7), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_8), + IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_9), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW4), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_ALE), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CLE), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS0), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS1), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS2), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS3), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D0), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D1), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D2), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D3), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D4), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D5), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D6), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D7), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_RB0), + IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_WP_B), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD0), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD1), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD2), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD3), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RX_CTL), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RXC), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD0), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD1), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD2), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD3), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TX_CTL), + IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TXC), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT4), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT5), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT6), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT7), + IMX_PINCTRL_PIN(MX6DL_PAD_SD3_RST), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CLK), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CMD), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT0), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT1), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT2), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT3), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT4), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6), + IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7), +}; + +static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = { + .pins = imx6dl_pinctrl_pads, + .npins = ARRAY_SIZE(imx6dl_pinctrl_pads), +}; + +static struct of_device_id imx6dl_pinctrl_of_match[] = { + { .compatible = "fsl,imx6dl-iomuxc", }, + { /* sentinel */ } +}; + +static int imx6dl_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6dl_pinctrl_info); +} + +static struct platform_driver imx6dl_pinctrl_driver = { + .driver = { + .name = "imx6dl-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx6dl_pinctrl_of_match, + }, + .probe = imx6dl_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6dl_pinctrl_init(void) +{ + return platform_driver_register(&imx6dl_pinctrl_driver); +} +arch_initcall(imx6dl_pinctrl_init); + +static void __exit imx6dl_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6dl_pinctrl_driver); +} +module_exit(imx6dl_pinctrl_exit); + +MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); +MODULE_DESCRIPTION("Freescale imx6dl pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c index 663346bb765..8eb5ac1bd5f 100644 --- a/drivers/pinctrl/pinctrl-imx6q.c +++ b/drivers/pinctrl/pinctrl-imx6q.c @@ -23,1939 +23,245 @@ #include "pinctrl-imx.h" enum imx6q_pads { - MX6Q_PAD_SD2_DAT1 = 0, - MX6Q_PAD_SD2_DAT2 = 1, - MX6Q_PAD_SD2_DAT0 = 2, - MX6Q_PAD_RGMII_TXC = 3, - MX6Q_PAD_RGMII_TD0 = 4, - MX6Q_PAD_RGMII_TD1 = 5, - MX6Q_PAD_RGMII_TD2 = 6, - MX6Q_PAD_RGMII_TD3 = 7, - MX6Q_PAD_RGMII_RX_CTL = 8, - MX6Q_PAD_RGMII_RD0 = 9, - MX6Q_PAD_RGMII_TX_CTL = 10, - MX6Q_PAD_RGMII_RD1 = 11, - MX6Q_PAD_RGMII_RD2 = 12, - MX6Q_PAD_RGMII_RD3 = 13, - MX6Q_PAD_RGMII_RXC = 14, - MX6Q_PAD_EIM_A25 = 15, - MX6Q_PAD_EIM_EB2 = 16, - MX6Q_PAD_EIM_D16 = 17, - MX6Q_PAD_EIM_D17 = 18, - MX6Q_PAD_EIM_D18 = 19, - MX6Q_PAD_EIM_D19 = 20, - MX6Q_PAD_EIM_D20 = 21, - MX6Q_PAD_EIM_D21 = 22, - MX6Q_PAD_EIM_D22 = 23, - MX6Q_PAD_EIM_D23 = 24, - MX6Q_PAD_EIM_EB3 = 25, - MX6Q_PAD_EIM_D24 = 26, - MX6Q_PAD_EIM_D25 = 27, - MX6Q_PAD_EIM_D26 = 28, - MX6Q_PAD_EIM_D27 = 29, - MX6Q_PAD_EIM_D28 = 30, - MX6Q_PAD_EIM_D29 = 31, - MX6Q_PAD_EIM_D30 = 32, - MX6Q_PAD_EIM_D31 = 33, - MX6Q_PAD_EIM_A24 = 34, - MX6Q_PAD_EIM_A23 = 35, - MX6Q_PAD_EIM_A22 = 36, - MX6Q_PAD_EIM_A21 = 37, - MX6Q_PAD_EIM_A20 = 38, - MX6Q_PAD_EIM_A19 = 39, - MX6Q_PAD_EIM_A18 = 40, - MX6Q_PAD_EIM_A17 = 41, - MX6Q_PAD_EIM_A16 = 42, - MX6Q_PAD_EIM_CS0 = 43, - MX6Q_PAD_EIM_CS1 = 44, - MX6Q_PAD_EIM_OE = 45, - MX6Q_PAD_EIM_RW = 46, - MX6Q_PAD_EIM_LBA = 47, - MX6Q_PAD_EIM_EB0 = 48, - MX6Q_PAD_EIM_EB1 = 49, - MX6Q_PAD_EIM_DA0 = 50, - MX6Q_PAD_EIM_DA1 = 51, - MX6Q_PAD_EIM_DA2 = 52, - MX6Q_PAD_EIM_DA3 = 53, - MX6Q_PAD_EIM_DA4 = 54, - MX6Q_PAD_EIM_DA5 = 55, - MX6Q_PAD_EIM_DA6 = 56, - MX6Q_PAD_EIM_DA7 = 57, - MX6Q_PAD_EIM_DA8 = 58, - MX6Q_PAD_EIM_DA9 = 59, - MX6Q_PAD_EIM_DA10 = 60, - MX6Q_PAD_EIM_DA11 = 61, - MX6Q_PAD_EIM_DA12 = 62, - MX6Q_PAD_EIM_DA13 = 63, - MX6Q_PAD_EIM_DA14 = 64, - MX6Q_PAD_EIM_DA15 = 65, - MX6Q_PAD_EIM_WAIT = 66, - MX6Q_PAD_EIM_BCLK = 67, - MX6Q_PAD_DI0_DISP_CLK = 68, - MX6Q_PAD_DI0_PIN15 = 69, - MX6Q_PAD_DI0_PIN2 = 70, - MX6Q_PAD_DI0_PIN3 = 71, - MX6Q_PAD_DI0_PIN4 = 72, - MX6Q_PAD_DISP0_DAT0 = 73, - MX6Q_PAD_DISP0_DAT1 = 74, - MX6Q_PAD_DISP0_DAT2 = 75, - MX6Q_PAD_DISP0_DAT3 = 76, - MX6Q_PAD_DISP0_DAT4 = 77, - MX6Q_PAD_DISP0_DAT5 = 78, - MX6Q_PAD_DISP0_DAT6 = 79, - MX6Q_PAD_DISP0_DAT7 = 80, - MX6Q_PAD_DISP0_DAT8 = 81, - MX6Q_PAD_DISP0_DAT9 = 82, - MX6Q_PAD_DISP0_DAT10 = 83, - MX6Q_PAD_DISP0_DAT11 = 84, - MX6Q_PAD_DISP0_DAT12 = 85, - MX6Q_PAD_DISP0_DAT13 = 86, - MX6Q_PAD_DISP0_DAT14 = 87, - MX6Q_PAD_DISP0_DAT15 = 88, - MX6Q_PAD_DISP0_DAT16 = 89, - MX6Q_PAD_DISP0_DAT17 = 90, - MX6Q_PAD_DISP0_DAT18 = 91, - MX6Q_PAD_DISP0_DAT19 = 92, - MX6Q_PAD_DISP0_DAT20 = 93, - MX6Q_PAD_DISP0_DAT21 = 94, - MX6Q_PAD_DISP0_DAT22 = 95, - MX6Q_PAD_DISP0_DAT23 = 96, - MX6Q_PAD_ENET_MDIO = 97, - MX6Q_PAD_ENET_REF_CLK = 98, - MX6Q_PAD_ENET_RX_ER = 99, - MX6Q_PAD_ENET_CRS_DV = 100, - MX6Q_PAD_ENET_RXD1 = 101, - MX6Q_PAD_ENET_RXD0 = 102, - MX6Q_PAD_ENET_TX_EN = 103, - MX6Q_PAD_ENET_TXD1 = 104, - MX6Q_PAD_ENET_TXD0 = 105, - MX6Q_PAD_ENET_MDC = 106, - MX6Q_PAD_DRAM_D40 = 107, - MX6Q_PAD_DRAM_D41 = 108, - MX6Q_PAD_DRAM_D42 = 109, - MX6Q_PAD_DRAM_D43 = 110, - MX6Q_PAD_DRAM_D44 = 111, - MX6Q_PAD_DRAM_D45 = 112, - MX6Q_PAD_DRAM_D46 = 113, - MX6Q_PAD_DRAM_D47 = 114, - MX6Q_PAD_DRAM_SDQS5 = 115, - MX6Q_PAD_DRAM_DQM5 = 116, - MX6Q_PAD_DRAM_D32 = 117, - MX6Q_PAD_DRAM_D33 = 118, - MX6Q_PAD_DRAM_D34 = 119, - MX6Q_PAD_DRAM_D35 = 120, - MX6Q_PAD_DRAM_D36 = 121, - MX6Q_PAD_DRAM_D37 = 122, - MX6Q_PAD_DRAM_D38 = 123, - MX6Q_PAD_DRAM_D39 = 124, - MX6Q_PAD_DRAM_DQM4 = 125, - MX6Q_PAD_DRAM_SDQS4 = 126, - MX6Q_PAD_DRAM_D24 = 127, - MX6Q_PAD_DRAM_D25 = 128, - MX6Q_PAD_DRAM_D26 = 129, - MX6Q_PAD_DRAM_D27 = 130, - MX6Q_PAD_DRAM_D28 = 131, - MX6Q_PAD_DRAM_D29 = 132, - MX6Q_PAD_DRAM_SDQS3 = 133, - MX6Q_PAD_DRAM_D30 = 134, - MX6Q_PAD_DRAM_D31 = 135, - MX6Q_PAD_DRAM_DQM3 = 136, - MX6Q_PAD_DRAM_D16 = 137, - MX6Q_PAD_DRAM_D17 = 138, - MX6Q_PAD_DRAM_D18 = 139, - MX6Q_PAD_DRAM_D19 = 140, - MX6Q_PAD_DRAM_D20 = 141, - MX6Q_PAD_DRAM_D21 = 142, - MX6Q_PAD_DRAM_D22 = 143, - MX6Q_PAD_DRAM_SDQS2 = 144, - MX6Q_PAD_DRAM_D23 = 145, - MX6Q_PAD_DRAM_DQM2 = 146, - MX6Q_PAD_DRAM_A0 = 147, - MX6Q_PAD_DRAM_A1 = 148, - MX6Q_PAD_DRAM_A2 = 149, - MX6Q_PAD_DRAM_A3 = 150, - MX6Q_PAD_DRAM_A4 = 151, - MX6Q_PAD_DRAM_A5 = 152, - MX6Q_PAD_DRAM_A6 = 153, - MX6Q_PAD_DRAM_A7 = 154, - MX6Q_PAD_DRAM_A8 = 155, - MX6Q_PAD_DRAM_A9 = 156, - MX6Q_PAD_DRAM_A10 = 157, - MX6Q_PAD_DRAM_A11 = 158, - MX6Q_PAD_DRAM_A12 = 159, - MX6Q_PAD_DRAM_A13 = 160, - MX6Q_PAD_DRAM_A14 = 161, - MX6Q_PAD_DRAM_A15 = 162, - MX6Q_PAD_DRAM_CAS = 163, - MX6Q_PAD_DRAM_CS0 = 164, - MX6Q_PAD_DRAM_CS1 = 165, - MX6Q_PAD_DRAM_RAS = 166, - MX6Q_PAD_DRAM_RESET = 167, - MX6Q_PAD_DRAM_SDBA0 = 168, - MX6Q_PAD_DRAM_SDBA1 = 169, - MX6Q_PAD_DRAM_SDCLK_0 = 170, - MX6Q_PAD_DRAM_SDBA2 = 171, - MX6Q_PAD_DRAM_SDCKE0 = 172, - MX6Q_PAD_DRAM_SDCLK_1 = 173, - MX6Q_PAD_DRAM_SDCKE1 = 174, - MX6Q_PAD_DRAM_SDODT0 = 175, - MX6Q_PAD_DRAM_SDODT1 = 176, - MX6Q_PAD_DRAM_SDWE = 177, - MX6Q_PAD_DRAM_D0 = 178, - MX6Q_PAD_DRAM_D1 = 179, - MX6Q_PAD_DRAM_D2 = 180, - MX6Q_PAD_DRAM_D3 = 181, - MX6Q_PAD_DRAM_D4 = 182, - MX6Q_PAD_DRAM_D5 = 183, - MX6Q_PAD_DRAM_SDQS0 = 184, - MX6Q_PAD_DRAM_D6 = 185, - MX6Q_PAD_DRAM_D7 = 186, - MX6Q_PAD_DRAM_DQM0 = 187, - MX6Q_PAD_DRAM_D8 = 188, - MX6Q_PAD_DRAM_D9 = 189, - MX6Q_PAD_DRAM_D10 = 190, - MX6Q_PAD_DRAM_D11 = 191, - MX6Q_PAD_DRAM_D12 = 192, - MX6Q_PAD_DRAM_D13 = 193, - MX6Q_PAD_DRAM_D14 = 194, - MX6Q_PAD_DRAM_SDQS1 = 195, - MX6Q_PAD_DRAM_D15 = 196, - MX6Q_PAD_DRAM_DQM1 = 197, - MX6Q_PAD_DRAM_D48 = 198, - MX6Q_PAD_DRAM_D49 = 199, - MX6Q_PAD_DRAM_D50 = 200, - MX6Q_PAD_DRAM_D51 = 201, - MX6Q_PAD_DRAM_D52 = 202, - MX6Q_PAD_DRAM_D53 = 203, - MX6Q_PAD_DRAM_D54 = 204, - MX6Q_PAD_DRAM_D55 = 205, - MX6Q_PAD_DRAM_SDQS6 = 206, - MX6Q_PAD_DRAM_DQM6 = 207, - MX6Q_PAD_DRAM_D56 = 208, - MX6Q_PAD_DRAM_SDQS7 = 209, - MX6Q_PAD_DRAM_D57 = 210, - MX6Q_PAD_DRAM_D58 = 211, - MX6Q_PAD_DRAM_D59 = 212, - MX6Q_PAD_DRAM_D60 = 213, - MX6Q_PAD_DRAM_DQM7 = 214, - MX6Q_PAD_DRAM_D61 = 215, - MX6Q_PAD_DRAM_D62 = 216, - MX6Q_PAD_DRAM_D63 = 217, - MX6Q_PAD_KEY_COL0 = 218, - MX6Q_PAD_KEY_ROW0 = 219, - MX6Q_PAD_KEY_COL1 = 220, - MX6Q_PAD_KEY_ROW1 = 221, - MX6Q_PAD_KEY_COL2 = 222, - MX6Q_PAD_KEY_ROW2 = 223, - MX6Q_PAD_KEY_COL3 = 224, - MX6Q_PAD_KEY_ROW3 = 225, - MX6Q_PAD_KEY_COL4 = 226, - MX6Q_PAD_KEY_ROW4 = 227, - MX6Q_PAD_GPIO_0 = 228, - MX6Q_PAD_GPIO_1 = 229, - MX6Q_PAD_GPIO_9 = 230, - MX6Q_PAD_GPIO_3 = 231, - MX6Q_PAD_GPIO_6 = 232, - MX6Q_PAD_GPIO_2 = 233, - MX6Q_PAD_GPIO_4 = 234, - MX6Q_PAD_GPIO_5 = 235, - MX6Q_PAD_GPIO_7 = 236, - MX6Q_PAD_GPIO_8 = 237, - MX6Q_PAD_GPIO_16 = 238, - MX6Q_PAD_GPIO_17 = 239, - MX6Q_PAD_GPIO_18 = 240, - MX6Q_PAD_GPIO_19 = 241, - MX6Q_PAD_CSI0_PIXCLK = 242, - MX6Q_PAD_CSI0_MCLK = 243, - MX6Q_PAD_CSI0_DATA_EN = 244, - MX6Q_PAD_CSI0_VSYNC = 245, - MX6Q_PAD_CSI0_DAT4 = 246, - MX6Q_PAD_CSI0_DAT5 = 247, - MX6Q_PAD_CSI0_DAT6 = 248, - MX6Q_PAD_CSI0_DAT7 = 249, - MX6Q_PAD_CSI0_DAT8 = 250, - MX6Q_PAD_CSI0_DAT9 = 251, - MX6Q_PAD_CSI0_DAT10 = 252, - MX6Q_PAD_CSI0_DAT11 = 253, - MX6Q_PAD_CSI0_DAT12 = 254, - MX6Q_PAD_CSI0_DAT13 = 255, - MX6Q_PAD_CSI0_DAT14 = 256, - MX6Q_PAD_CSI0_DAT15 = 257, - MX6Q_PAD_CSI0_DAT16 = 258, - MX6Q_PAD_CSI0_DAT17 = 259, - MX6Q_PAD_CSI0_DAT18 = 260, - MX6Q_PAD_CSI0_DAT19 = 261, - MX6Q_PAD_JTAG_TMS = 262, - MX6Q_PAD_JTAG_MOD = 263, - MX6Q_PAD_JTAG_TRSTB = 264, - MX6Q_PAD_JTAG_TDI = 265, - MX6Q_PAD_JTAG_TCK = 266, - MX6Q_PAD_JTAG_TDO = 267, - MX6Q_PAD_LVDS1_TX3_P = 268, - MX6Q_PAD_LVDS1_TX2_P = 269, - MX6Q_PAD_LVDS1_CLK_P = 270, - MX6Q_PAD_LVDS1_TX1_P = 271, - MX6Q_PAD_LVDS1_TX0_P = 272, - MX6Q_PAD_LVDS0_TX3_P = 273, - MX6Q_PAD_LVDS0_CLK_P = 274, - MX6Q_PAD_LVDS0_TX2_P = 275, - MX6Q_PAD_LVDS0_TX1_P = 276, - MX6Q_PAD_LVDS0_TX0_P = 277, - MX6Q_PAD_TAMPER = 278, - MX6Q_PAD_PMIC_ON_REQ = 279, - MX6Q_PAD_PMIC_STBY_REQ = 280, - MX6Q_PAD_POR_B = 281, - MX6Q_PAD_BOOT_MODE1 = 282, - MX6Q_PAD_RESET_IN_B = 283, - MX6Q_PAD_BOOT_MODE0 = 284, - MX6Q_PAD_TEST_MODE = 285, - MX6Q_PAD_SD3_DAT7 = 286, - MX6Q_PAD_SD3_DAT6 = 287, - MX6Q_PAD_SD3_DAT5 = 288, - MX6Q_PAD_SD3_DAT4 = 289, - MX6Q_PAD_SD3_CMD = 290, - MX6Q_PAD_SD3_CLK = 291, - MX6Q_PAD_SD3_DAT0 = 292, - MX6Q_PAD_SD3_DAT1 = 293, - MX6Q_PAD_SD3_DAT2 = 294, - MX6Q_PAD_SD3_DAT3 = 295, - MX6Q_PAD_SD3_RST = 296, - MX6Q_PAD_NANDF_CLE = 297, - MX6Q_PAD_NANDF_ALE = 298, - MX6Q_PAD_NANDF_WP_B = 299, - MX6Q_PAD_NANDF_RB0 = 300, - MX6Q_PAD_NANDF_CS0 = 301, - MX6Q_PAD_NANDF_CS1 = 302, - MX6Q_PAD_NANDF_CS2 = 303, - MX6Q_PAD_NANDF_CS3 = 304, - MX6Q_PAD_SD4_CMD = 305, - MX6Q_PAD_SD4_CLK = 306, - MX6Q_PAD_NANDF_D0 = 307, - MX6Q_PAD_NANDF_D1 = 308, - MX6Q_PAD_NANDF_D2 = 309, - MX6Q_PAD_NANDF_D3 = 310, - MX6Q_PAD_NANDF_D4 = 311, - MX6Q_PAD_NANDF_D5 = 312, - MX6Q_PAD_NANDF_D6 = 313, - MX6Q_PAD_NANDF_D7 = 314, - MX6Q_PAD_SD4_DAT0 = 315, - MX6Q_PAD_SD4_DAT1 = 316, - MX6Q_PAD_SD4_DAT2 = 317, - MX6Q_PAD_SD4_DAT3 = 318, - MX6Q_PAD_SD4_DAT4 = 319, - MX6Q_PAD_SD4_DAT5 = 320, - MX6Q_PAD_SD4_DAT6 = 321, - MX6Q_PAD_SD4_DAT7 = 322, - MX6Q_PAD_SD1_DAT1 = 323, - MX6Q_PAD_SD1_DAT0 = 324, - MX6Q_PAD_SD1_DAT3 = 325, - MX6Q_PAD_SD1_CMD = 326, - MX6Q_PAD_SD1_DAT2 = 327, - MX6Q_PAD_SD1_CLK = 328, - MX6Q_PAD_SD2_CLK = 329, - MX6Q_PAD_SD2_CMD = 330, - MX6Q_PAD_SD2_DAT3 = 331, -}; - -/* imx6q register maps */ -static struct imx_pin_reg imx6q_pin_regs[] = { - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */ - IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */ - IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */ - IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */ - IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */ - IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */ - IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */ - IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */ - IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */ - IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */ - IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */ - IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ + MX6Q_PAD_RESERVE0 = 0, + MX6Q_PAD_RESERVE1 = 1, + MX6Q_PAD_RESERVE2 = 2, + MX6Q_PAD_RESERVE3 = 3, + MX6Q_PAD_RESERVE4 = 4, + MX6Q_PAD_RESERVE5 = 5, + MX6Q_PAD_RESERVE6 = 6, + MX6Q_PAD_RESERVE7 = 7, + MX6Q_PAD_RESERVE8 = 8, + MX6Q_PAD_RESERVE9 = 9, + MX6Q_PAD_RESERVE10 = 10, + MX6Q_PAD_RESERVE11 = 11, + MX6Q_PAD_RESERVE12 = 12, + MX6Q_PAD_RESERVE13 = 13, + MX6Q_PAD_RESERVE14 = 14, + MX6Q_PAD_RESERVE15 = 15, + MX6Q_PAD_RESERVE16 = 16, + MX6Q_PAD_RESERVE17 = 17, + MX6Q_PAD_RESERVE18 = 18, + MX6Q_PAD_SD2_DAT1 = 19, + MX6Q_PAD_SD2_DAT2 = 20, + MX6Q_PAD_SD2_DAT0 = 21, + MX6Q_PAD_RGMII_TXC = 22, + MX6Q_PAD_RGMII_TD0 = 23, + MX6Q_PAD_RGMII_TD1 = 24, + MX6Q_PAD_RGMII_TD2 = 25, + MX6Q_PAD_RGMII_TD3 = 26, + MX6Q_PAD_RGMII_RX_CTL = 27, + MX6Q_PAD_RGMII_RD0 = 28, + MX6Q_PAD_RGMII_TX_CTL = 29, + MX6Q_PAD_RGMII_RD1 = 30, + MX6Q_PAD_RGMII_RD2 = 31, + MX6Q_PAD_RGMII_RD3 = 32, + MX6Q_PAD_RGMII_RXC = 33, + MX6Q_PAD_EIM_A25 = 34, + MX6Q_PAD_EIM_EB2 = 35, + MX6Q_PAD_EIM_D16 = 36, + MX6Q_PAD_EIM_D17 = 37, + MX6Q_PAD_EIM_D18 = 38, + MX6Q_PAD_EIM_D19 = 39, + MX6Q_PAD_EIM_D20 = 40, + MX6Q_PAD_EIM_D21 = 41, + MX6Q_PAD_EIM_D22 = 42, + MX6Q_PAD_EIM_D23 = 43, + MX6Q_PAD_EIM_EB3 = 44, + MX6Q_PAD_EIM_D24 = 45, + MX6Q_PAD_EIM_D25 = 46, + MX6Q_PAD_EIM_D26 = 47, + MX6Q_PAD_EIM_D27 = 48, + MX6Q_PAD_EIM_D28 = 49, + MX6Q_PAD_EIM_D29 = 50, + MX6Q_PAD_EIM_D30 = 51, + MX6Q_PAD_EIM_D31 = 52, + MX6Q_PAD_EIM_A24 = 53, + MX6Q_PAD_EIM_A23 = 54, + MX6Q_PAD_EIM_A22 = 55, + MX6Q_PAD_EIM_A21 = 56, + MX6Q_PAD_EIM_A20 = 57, + MX6Q_PAD_EIM_A19 = 58, + MX6Q_PAD_EIM_A18 = 59, + MX6Q_PAD_EIM_A17 = 60, + MX6Q_PAD_EIM_A16 = 61, + MX6Q_PAD_EIM_CS0 = 62, + MX6Q_PAD_EIM_CS1 = 63, + MX6Q_PAD_EIM_OE = 64, + MX6Q_PAD_EIM_RW = 65, + MX6Q_PAD_EIM_LBA = 66, + MX6Q_PAD_EIM_EB0 = 67, + MX6Q_PAD_EIM_EB1 = 68, + MX6Q_PAD_EIM_DA0 = 69, + MX6Q_PAD_EIM_DA1 = 70, + MX6Q_PAD_EIM_DA2 = 71, + MX6Q_PAD_EIM_DA3 = 72, + MX6Q_PAD_EIM_DA4 = 73, + MX6Q_PAD_EIM_DA5 = 74, + MX6Q_PAD_EIM_DA6 = 75, + MX6Q_PAD_EIM_DA7 = 76, + MX6Q_PAD_EIM_DA8 = 77, + MX6Q_PAD_EIM_DA9 = 78, + MX6Q_PAD_EIM_DA10 = 79, + MX6Q_PAD_EIM_DA11 = 80, + MX6Q_PAD_EIM_DA12 = 81, + MX6Q_PAD_EIM_DA13 = 82, + MX6Q_PAD_EIM_DA14 = 83, + MX6Q_PAD_EIM_DA15 = 84, + MX6Q_PAD_EIM_WAIT = 85, + MX6Q_PAD_EIM_BCLK = 86, + MX6Q_PAD_DI0_DISP_CLK = 87, + MX6Q_PAD_DI0_PIN15 = 88, + MX6Q_PAD_DI0_PIN2 = 89, + MX6Q_PAD_DI0_PIN3 = 90, + MX6Q_PAD_DI0_PIN4 = 91, + MX6Q_PAD_DISP0_DAT0 = 92, + MX6Q_PAD_DISP0_DAT1 = 93, + MX6Q_PAD_DISP0_DAT2 = 94, + MX6Q_PAD_DISP0_DAT3 = 95, + MX6Q_PAD_DISP0_DAT4 = 96, + MX6Q_PAD_DISP0_DAT5 = 97, + MX6Q_PAD_DISP0_DAT6 = 98, + MX6Q_PAD_DISP0_DAT7 = 99, + MX6Q_PAD_DISP0_DAT8 = 100, + MX6Q_PAD_DISP0_DAT9 = 101, + MX6Q_PAD_DISP0_DAT10 = 102, + MX6Q_PAD_DISP0_DAT11 = 103, + MX6Q_PAD_DISP0_DAT12 = 104, + MX6Q_PAD_DISP0_DAT13 = 105, + MX6Q_PAD_DISP0_DAT14 = 106, + MX6Q_PAD_DISP0_DAT15 = 107, + MX6Q_PAD_DISP0_DAT16 = 108, + MX6Q_PAD_DISP0_DAT17 = 109, + MX6Q_PAD_DISP0_DAT18 = 110, + MX6Q_PAD_DISP0_DAT19 = 111, + MX6Q_PAD_DISP0_DAT20 = 112, + MX6Q_PAD_DISP0_DAT21 = 113, + MX6Q_PAD_DISP0_DAT22 = 114, + MX6Q_PAD_DISP0_DAT23 = 115, + MX6Q_PAD_ENET_MDIO = 116, + MX6Q_PAD_ENET_REF_CLK = 117, + MX6Q_PAD_ENET_RX_ER = 118, + MX6Q_PAD_ENET_CRS_DV = 119, + MX6Q_PAD_ENET_RXD1 = 120, + MX6Q_PAD_ENET_RXD0 = 121, + MX6Q_PAD_ENET_TX_EN = 122, + MX6Q_PAD_ENET_TXD1 = 123, + MX6Q_PAD_ENET_TXD0 = 124, + MX6Q_PAD_ENET_MDC = 125, + MX6Q_PAD_KEY_COL0 = 126, + MX6Q_PAD_KEY_ROW0 = 127, + MX6Q_PAD_KEY_COL1 = 128, + MX6Q_PAD_KEY_ROW1 = 129, + MX6Q_PAD_KEY_COL2 = 130, + MX6Q_PAD_KEY_ROW2 = 131, + MX6Q_PAD_KEY_COL3 = 132, + MX6Q_PAD_KEY_ROW3 = 133, + MX6Q_PAD_KEY_COL4 = 134, + MX6Q_PAD_KEY_ROW4 = 135, + MX6Q_PAD_GPIO_0 = 136, + MX6Q_PAD_GPIO_1 = 137, + MX6Q_PAD_GPIO_9 = 138, + MX6Q_PAD_GPIO_3 = 139, + MX6Q_PAD_GPIO_6 = 140, + MX6Q_PAD_GPIO_2 = 141, + MX6Q_PAD_GPIO_4 = 142, + MX6Q_PAD_GPIO_5 = 143, + MX6Q_PAD_GPIO_7 = 144, + MX6Q_PAD_GPIO_8 = 145, + MX6Q_PAD_GPIO_16 = 146, + MX6Q_PAD_GPIO_17 = 147, + MX6Q_PAD_GPIO_18 = 148, + MX6Q_PAD_GPIO_19 = 149, + MX6Q_PAD_CSI0_PIXCLK = 150, + MX6Q_PAD_CSI0_MCLK = 151, + MX6Q_PAD_CSI0_DATA_EN = 152, + MX6Q_PAD_CSI0_VSYNC = 153, + MX6Q_PAD_CSI0_DAT4 = 154, + MX6Q_PAD_CSI0_DAT5 = 155, + MX6Q_PAD_CSI0_DAT6 = 156, + MX6Q_PAD_CSI0_DAT7 = 157, + MX6Q_PAD_CSI0_DAT8 = 158, + MX6Q_PAD_CSI0_DAT9 = 159, + MX6Q_PAD_CSI0_DAT10 = 160, + MX6Q_PAD_CSI0_DAT11 = 161, + MX6Q_PAD_CSI0_DAT12 = 162, + MX6Q_PAD_CSI0_DAT13 = 163, + MX6Q_PAD_CSI0_DAT14 = 164, + MX6Q_PAD_CSI0_DAT15 = 165, + MX6Q_PAD_CSI0_DAT16 = 166, + MX6Q_PAD_CSI0_DAT17 = 167, + MX6Q_PAD_CSI0_DAT18 = 168, + MX6Q_PAD_CSI0_DAT19 = 169, + MX6Q_PAD_SD3_DAT7 = 170, + MX6Q_PAD_SD3_DAT6 = 171, + MX6Q_PAD_SD3_DAT5 = 172, + MX6Q_PAD_SD3_DAT4 = 173, + MX6Q_PAD_SD3_CMD = 174, + MX6Q_PAD_SD3_CLK = 175, + MX6Q_PAD_SD3_DAT0 = 176, + MX6Q_PAD_SD3_DAT1 = 177, + MX6Q_PAD_SD3_DAT2 = 178, + MX6Q_PAD_SD3_DAT3 = 179, + MX6Q_PAD_SD3_RST = 180, + MX6Q_PAD_NANDF_CLE = 181, + MX6Q_PAD_NANDF_ALE = 182, + MX6Q_PAD_NANDF_WP_B = 183, + MX6Q_PAD_NANDF_RB0 = 184, + MX6Q_PAD_NANDF_CS0 = 185, + MX6Q_PAD_NANDF_CS1 = 186, + MX6Q_PAD_NANDF_CS2 = 187, + MX6Q_PAD_NANDF_CS3 = 188, + MX6Q_PAD_SD4_CMD = 189, + MX6Q_PAD_SD4_CLK = 190, + MX6Q_PAD_NANDF_D0 = 191, + MX6Q_PAD_NANDF_D1 = 192, + MX6Q_PAD_NANDF_D2 = 193, + MX6Q_PAD_NANDF_D3 = 194, + MX6Q_PAD_NANDF_D4 = 195, + MX6Q_PAD_NANDF_D5 = 196, + MX6Q_PAD_NANDF_D6 = 197, + MX6Q_PAD_NANDF_D7 = 198, + MX6Q_PAD_SD4_DAT0 = 199, + MX6Q_PAD_SD4_DAT1 = 200, + MX6Q_PAD_SD4_DAT2 = 201, + MX6Q_PAD_SD4_DAT3 = 202, + MX6Q_PAD_SD4_DAT4 = 203, + MX6Q_PAD_SD4_DAT5 = 204, + MX6Q_PAD_SD4_DAT6 = 205, + MX6Q_PAD_SD4_DAT7 = 206, + MX6Q_PAD_SD1_DAT1 = 207, + MX6Q_PAD_SD1_DAT0 = 208, + MX6Q_PAD_SD1_DAT3 = 209, + MX6Q_PAD_SD1_CMD = 210, + MX6Q_PAD_SD1_DAT2 = 211, + MX6Q_PAD_SD1_CLK = 212, + MX6Q_PAD_SD2_CLK = 213, + MX6Q_PAD_SD2_CMD = 214, + MX6Q_PAD_SD2_DAT3 = 215, }; /* Pad names for the pinmux subsystem */ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE18), IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1), IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2), IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0), @@ -2063,117 +369,6 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1), IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0), IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63), IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0), IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0), IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1), @@ -2218,30 +413,6 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17), IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18), IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P), - IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER), - IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ), - IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ), - IMX_PINCTRL_PIN(MX6Q_PAD_POR_B), - IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1), - IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B), - IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0), - IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE), IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7), IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6), IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5), @@ -2293,8 +464,6 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = { static struct imx_pinctrl_soc_info imx6q_pinctrl_info = { .pins = imx6q_pinctrl_pads, .npins = ARRAY_SIZE(imx6q_pinctrl_pads), - .pin_regs = imx6q_pin_regs, - .npin_regs = ARRAY_SIZE(imx6q_pin_regs), }; static struct of_device_id imx6q_pinctrl_of_match[] = { @@ -2311,7 +480,7 @@ static struct platform_driver imx6q_pinctrl_driver = { .driver = { .name = "imx6q-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx6q_pinctrl_of_match), + .of_match_table = imx6q_pinctrl_of_match, }, .probe = imx6q_pinctrl_probe, .remove = imx_pinctrl_remove, diff --git a/drivers/pinctrl/pinctrl-imx6sl.c b/drivers/pinctrl/pinctrl-imx6sl.c new file mode 100644 index 00000000000..f21b7389df3 --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx6sl.c @@ -0,0 +1,403 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum imx6sl_pads { + MX6SL_PAD_RESERVE0 = 0, + MX6SL_PAD_RESERVE1 = 1, + MX6SL_PAD_RESERVE2 = 2, + MX6SL_PAD_RESERVE3 = 3, + MX6SL_PAD_RESERVE4 = 4, + MX6SL_PAD_RESERVE5 = 5, + MX6SL_PAD_RESERVE6 = 6, + MX6SL_PAD_RESERVE7 = 7, + MX6SL_PAD_RESERVE8 = 8, + MX6SL_PAD_RESERVE9 = 9, + MX6SL_PAD_RESERVE10 = 10, + MX6SL_PAD_RESERVE11 = 11, + MX6SL_PAD_RESERVE12 = 12, + MX6SL_PAD_RESERVE13 = 13, + MX6SL_PAD_RESERVE14 = 14, + MX6SL_PAD_RESERVE15 = 15, + MX6SL_PAD_RESERVE16 = 16, + MX6SL_PAD_RESERVE17 = 17, + MX6SL_PAD_RESERVE18 = 18, + MX6SL_PAD_AUD_MCLK = 19, + MX6SL_PAD_AUD_RXC = 20, + MX6SL_PAD_AUD_RXD = 21, + MX6SL_PAD_AUD_RXFS = 22, + MX6SL_PAD_AUD_TXC = 23, + MX6SL_PAD_AUD_TXD = 24, + MX6SL_PAD_AUD_TXFS = 25, + MX6SL_PAD_ECSPI1_MISO = 26, + MX6SL_PAD_ECSPI1_MOSI = 27, + MX6SL_PAD_ECSPI1_SCLK = 28, + MX6SL_PAD_ECSPI1_SS0 = 29, + MX6SL_PAD_ECSPI2_MISO = 30, + MX6SL_PAD_ECSPI2_MOSI = 31, + MX6SL_PAD_ECSPI2_SCLK = 32, + MX6SL_PAD_ECSPI2_SS0 = 33, + MX6SL_PAD_EPDC_BDR0 = 34, + MX6SL_PAD_EPDC_BDR1 = 35, + MX6SL_PAD_EPDC_D0 = 36, + MX6SL_PAD_EPDC_D1 = 37, + MX6SL_PAD_EPDC_D10 = 38, + MX6SL_PAD_EPDC_D11 = 39, + MX6SL_PAD_EPDC_D12 = 40, + MX6SL_PAD_EPDC_D13 = 41, + MX6SL_PAD_EPDC_D14 = 42, + MX6SL_PAD_EPDC_D15 = 43, + MX6SL_PAD_EPDC_D2 = 44, + MX6SL_PAD_EPDC_D3 = 45, + MX6SL_PAD_EPDC_D4 = 46, + MX6SL_PAD_EPDC_D5 = 47, + MX6SL_PAD_EPDC_D6 = 48, + MX6SL_PAD_EPDC_D7 = 49, + MX6SL_PAD_EPDC_D8 = 50, + MX6SL_PAD_EPDC_D9 = 51, + MX6SL_PAD_EPDC_GDCLK = 52, + MX6SL_PAD_EPDC_GDOE = 53, + MX6SL_PAD_EPDC_GDRL = 54, + MX6SL_PAD_EPDC_GDSP = 55, + MX6SL_PAD_EPDC_PWRCOM = 56, + MX6SL_PAD_EPDC_PWRCTRL0 = 57, + MX6SL_PAD_EPDC_PWRCTRL1 = 58, + MX6SL_PAD_EPDC_PWRCTRL2 = 59, + MX6SL_PAD_EPDC_PWRCTRL3 = 60, + MX6SL_PAD_EPDC_PWRINT = 61, + MX6SL_PAD_EPDC_PWRSTAT = 62, + MX6SL_PAD_EPDC_PWRWAKEUP = 63, + MX6SL_PAD_EPDC_SDCE0 = 64, + MX6SL_PAD_EPDC_SDCE1 = 65, + MX6SL_PAD_EPDC_SDCE2 = 66, + MX6SL_PAD_EPDC_SDCE3 = 67, + MX6SL_PAD_EPDC_SDCLK = 68, + MX6SL_PAD_EPDC_SDLE = 69, + MX6SL_PAD_EPDC_SDOE = 70, + MX6SL_PAD_EPDC_SDSHR = 71, + MX6SL_PAD_EPDC_VCOM0 = 72, + MX6SL_PAD_EPDC_VCOM1 = 73, + MX6SL_PAD_FEC_CRS_DV = 74, + MX6SL_PAD_FEC_MDC = 75, + MX6SL_PAD_FEC_MDIO = 76, + MX6SL_PAD_FEC_REF_CLK = 77, + MX6SL_PAD_FEC_RX_ER = 78, + MX6SL_PAD_FEC_RXD0 = 79, + MX6SL_PAD_FEC_RXD1 = 80, + MX6SL_PAD_FEC_TX_CLK = 81, + MX6SL_PAD_FEC_TX_EN = 82, + MX6SL_PAD_FEC_TXD0 = 83, + MX6SL_PAD_FEC_TXD1 = 84, + MX6SL_PAD_HSIC_DAT = 85, + MX6SL_PAD_HSIC_STROBE = 86, + MX6SL_PAD_I2C1_SCL = 87, + MX6SL_PAD_I2C1_SDA = 88, + MX6SL_PAD_I2C2_SCL = 89, + MX6SL_PAD_I2C2_SDA = 90, + MX6SL_PAD_KEY_COL0 = 91, + MX6SL_PAD_KEY_COL1 = 92, + MX6SL_PAD_KEY_COL2 = 93, + MX6SL_PAD_KEY_COL3 = 94, + MX6SL_PAD_KEY_COL4 = 95, + MX6SL_PAD_KEY_COL5 = 96, + MX6SL_PAD_KEY_COL6 = 97, + MX6SL_PAD_KEY_COL7 = 98, + MX6SL_PAD_KEY_ROW0 = 99, + MX6SL_PAD_KEY_ROW1 = 100, + MX6SL_PAD_KEY_ROW2 = 101, + MX6SL_PAD_KEY_ROW3 = 102, + MX6SL_PAD_KEY_ROW4 = 103, + MX6SL_PAD_KEY_ROW5 = 104, + MX6SL_PAD_KEY_ROW6 = 105, + MX6SL_PAD_KEY_ROW7 = 106, + MX6SL_PAD_LCD_CLK = 107, + MX6SL_PAD_LCD_DAT0 = 108, + MX6SL_PAD_LCD_DAT1 = 109, + MX6SL_PAD_LCD_DAT10 = 110, + MX6SL_PAD_LCD_DAT11 = 111, + MX6SL_PAD_LCD_DAT12 = 112, + MX6SL_PAD_LCD_DAT13 = 113, + MX6SL_PAD_LCD_DAT14 = 114, + MX6SL_PAD_LCD_DAT15 = 115, + MX6SL_PAD_LCD_DAT16 = 116, + MX6SL_PAD_LCD_DAT17 = 117, + MX6SL_PAD_LCD_DAT18 = 118, + MX6SL_PAD_LCD_DAT19 = 119, + MX6SL_PAD_LCD_DAT2 = 120, + MX6SL_PAD_LCD_DAT20 = 121, + MX6SL_PAD_LCD_DAT21 = 122, + MX6SL_PAD_LCD_DAT22 = 123, + MX6SL_PAD_LCD_DAT23 = 124, + MX6SL_PAD_LCD_DAT3 = 125, + MX6SL_PAD_LCD_DAT4 = 126, + MX6SL_PAD_LCD_DAT5 = 127, + MX6SL_PAD_LCD_DAT6 = 128, + MX6SL_PAD_LCD_DAT7 = 129, + MX6SL_PAD_LCD_DAT8 = 130, + MX6SL_PAD_LCD_DAT9 = 131, + MX6SL_PAD_LCD_ENABLE = 132, + MX6SL_PAD_LCD_HSYNC = 133, + MX6SL_PAD_LCD_RESET = 134, + MX6SL_PAD_LCD_VSYNC = 135, + MX6SL_PAD_PWM1 = 136, + MX6SL_PAD_REF_CLK_24M = 137, + MX6SL_PAD_REF_CLK_32K = 138, + MX6SL_PAD_SD1_CLK = 139, + MX6SL_PAD_SD1_CMD = 140, + MX6SL_PAD_SD1_DAT0 = 141, + MX6SL_PAD_SD1_DAT1 = 142, + MX6SL_PAD_SD1_DAT2 = 143, + MX6SL_PAD_SD1_DAT3 = 144, + MX6SL_PAD_SD1_DAT4 = 145, + MX6SL_PAD_SD1_DAT5 = 146, + MX6SL_PAD_SD1_DAT6 = 147, + MX6SL_PAD_SD1_DAT7 = 148, + MX6SL_PAD_SD2_CLK = 149, + MX6SL_PAD_SD2_CMD = 150, + MX6SL_PAD_SD2_DAT0 = 151, + MX6SL_PAD_SD2_DAT1 = 152, + MX6SL_PAD_SD2_DAT2 = 153, + MX6SL_PAD_SD2_DAT3 = 154, + MX6SL_PAD_SD2_DAT4 = 155, + MX6SL_PAD_SD2_DAT5 = 156, + MX6SL_PAD_SD2_DAT6 = 157, + MX6SL_PAD_SD2_DAT7 = 158, + MX6SL_PAD_SD2_RST = 159, + MX6SL_PAD_SD3_CLK = 160, + MX6SL_PAD_SD3_CMD = 161, + MX6SL_PAD_SD3_DAT0 = 162, + MX6SL_PAD_SD3_DAT1 = 163, + MX6SL_PAD_SD3_DAT2 = 164, + MX6SL_PAD_SD3_DAT3 = 165, + MX6SL_PAD_UART1_RXD = 166, + MX6SL_PAD_UART1_TXD = 167, + MX6SL_PAD_WDOG_B = 168, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE17), + IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE18), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_MCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXC), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXD), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXFS), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXC), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXD), + IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXFS), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MISO), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MOSI), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SS0), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MISO), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MOSI), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SS0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR1), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D1), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D10), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D11), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D12), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D13), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D14), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D15), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D2), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D3), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D4), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D5), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D6), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D7), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D8), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D9), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDOE), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDRL), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDSP), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCOM), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL1), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL2), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL3), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRINT), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRSTAT), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRWAKEUP), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE1), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE2), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE3), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCLK), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDLE), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDOE), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDSHR), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM0), + IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM1), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_CRS_DV), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDC), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDIO), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_REF_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RX_ER), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD0), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD1), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_EN), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD0), + IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD1), + IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_DAT), + IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_STROBE), + IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SCL), + IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SDA), + IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SCL), + IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SDA), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL5), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL6), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL7), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW4), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW5), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW6), + IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW7), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT0), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT1), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT10), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT11), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT12), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT13), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT14), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT15), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT16), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT17), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT18), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT19), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT2), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT20), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT21), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT22), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT23), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT3), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT4), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT5), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT6), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT7), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT8), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT9), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_ENABLE), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_HSYNC), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_RESET), + IMX_PINCTRL_PIN(MX6SL_PAD_LCD_VSYNC), + IMX_PINCTRL_PIN(MX6SL_PAD_PWM1), + IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_24M), + IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_32K), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT0), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT1), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT2), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT3), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT4), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT5), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT6), + IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT7), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT0), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT1), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT2), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT3), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT4), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT5), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT6), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT7), + IMX_PINCTRL_PIN(MX6SL_PAD_SD2_RST), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT0), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT1), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT2), + IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT3), + IMX_PINCTRL_PIN(MX6SL_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX6SL_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B), +}; + +static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = { + .pins = imx6sl_pinctrl_pads, + .npins = ARRAY_SIZE(imx6sl_pinctrl_pads), +}; + +static struct of_device_id imx6sl_pinctrl_of_match[] = { + { .compatible = "fsl,imx6sl-iomuxc", }, + { /* sentinel */ } +}; + +static int imx6sl_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6sl_pinctrl_info); +} + +static struct platform_driver imx6sl_pinctrl_driver = { + .driver = { + .name = "imx6sl-pinctrl", + .owner = THIS_MODULE, + .of_match_table = imx6sl_pinctrl_of_match, + }, + .probe = imx6sl_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6sl_pinctrl_init(void) +{ + return platform_driver_register(&imx6sl_pinctrl_driver); +} +arch_initcall(imx6sl_pinctrl_init); + +static void __exit imx6sl_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6sl_pinctrl_driver); +} +module_exit(imx6sl_pinctrl_exit); + +MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); +MODULE_DESCRIPTION("Freescale imx6sl pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-imx6sx.c b/drivers/pinctrl/pinctrl-imx6sx.c new file mode 100644 index 00000000000..09758a56b9d --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx6sx.c @@ -0,0 +1,407 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum imx6sx_pads { + MX6Sx_PAD_RESERVE0 = 0, + MX6Sx_PAD_RESERVE1 = 1, + MX6Sx_PAD_RESERVE2 = 2, + MX6Sx_PAD_RESERVE3 = 3, + MX6Sx_PAD_RESERVE4 = 4, + MX6SX_PAD_GPIO1_IO00 = 5, + MX6SX_PAD_GPIO1_IO01 = 6, + MX6SX_PAD_GPIO1_IO02 = 7, + MX6SX_PAD_GPIO1_IO03 = 8, + MX6SX_PAD_GPIO1_IO04 = 9, + MX6SX_PAD_GPIO1_IO05 = 10, + MX6SX_PAD_GPIO1_IO06 = 11, + MX6SX_PAD_GPIO1_IO07 = 12, + MX6SX_PAD_GPIO1_IO08 = 13, + MX6SX_PAD_GPIO1_IO09 = 14, + MX6SX_PAD_GPIO1_IO10 = 15, + MX6SX_PAD_GPIO1_IO11 = 16, + MX6SX_PAD_GPIO1_IO12 = 17, + MX6SX_PAD_GPIO1_IO13 = 18, + MX6SX_PAD_CSI_DATA00 = 19, + MX6SX_PAD_CSI_DATA01 = 20, + MX6SX_PAD_CSI_DATA02 = 21, + MX6SX_PAD_CSI_DATA03 = 22, + MX6SX_PAD_CSI_DATA04 = 23, + MX6SX_PAD_CSI_DATA05 = 24, + MX6SX_PAD_CSI_DATA06 = 25, + MX6SX_PAD_CSI_DATA07 = 26, + MX6SX_PAD_CSI_HSYNC = 27, + MX6SX_PAD_CSI_MCLK = 28, + MX6SX_PAD_CSI_PIXCLK = 29, + MX6SX_PAD_CSI_VSYNC = 30, + MX6SX_PAD_ENET1_COL = 31, + MX6SX_PAD_ENET1_CRS = 32, + MX6SX_PAD_ENET1_MDC = 33, + MX6SX_PAD_ENET1_MDIO = 34, + MX6SX_PAD_ENET1_RX_CLK = 35, + MX6SX_PAD_ENET1_TX_CLK = 36, + MX6SX_PAD_ENET2_COL = 37, + MX6SX_PAD_ENET2_CRS = 38, + MX6SX_PAD_ENET2_RX_CLK = 39, + MX6SX_PAD_ENET2_TX_CLK = 40, + MX6SX_PAD_KEY_COL0 = 41, + MX6SX_PAD_KEY_COL1 = 42, + MX6SX_PAD_KEY_COL2 = 43, + MX6SX_PAD_KEY_COL3 = 44, + MX6SX_PAD_KEY_COL4 = 45, + MX6SX_PAD_KEY_ROW0 = 46, + MX6SX_PAD_KEY_ROW1 = 47, + MX6SX_PAD_KEY_ROW2 = 48, + MX6SX_PAD_KEY_ROW3 = 49, + MX6SX_PAD_KEY_ROW4 = 50, + MX6SX_PAD_LCD1_CLK = 51, + MX6SX_PAD_LCD1_DATA00 = 52, + MX6SX_PAD_LCD1_DATA01 = 53, + MX6SX_PAD_LCD1_DATA02 = 54, + MX6SX_PAD_LCD1_DATA03 = 55, + MX6SX_PAD_LCD1_DATA04 = 56, + MX6SX_PAD_LCD1_DATA05 = 57, + MX6SX_PAD_LCD1_DATA06 = 58, + MX6SX_PAD_LCD1_DATA07 = 59, + MX6SX_PAD_LCD1_DATA08 = 60, + MX6SX_PAD_LCD1_DATA09 = 61, + MX6SX_PAD_LCD1_DATA10 = 62, + MX6SX_PAD_LCD1_DATA11 = 63, + MX6SX_PAD_LCD1_DATA12 = 64, + MX6SX_PAD_LCD1_DATA13 = 65, + MX6SX_PAD_LCD1_DATA14 = 66, + MX6SX_PAD_LCD1_DATA15 = 67, + MX6SX_PAD_LCD1_DATA16 = 68, + MX6SX_PAD_LCD1_DATA17 = 69, + MX6SX_PAD_LCD1_DATA18 = 70, + MX6SX_PAD_LCD1_DATA19 = 71, + MX6SX_PAD_LCD1_DATA20 = 72, + MX6SX_PAD_LCD1_DATA21 = 73, + MX6SX_PAD_LCD1_DATA22 = 74, + MX6SX_PAD_LCD1_DATA23 = 75, + MX6SX_PAD_LCD1_ENABLE = 76, + MX6SX_PAD_LCD1_HSYNC = 77, + MX6SX_PAD_LCD1_RESET = 78, + MX6SX_PAD_LCD1_VSYNC = 79, + MX6SX_PAD_NAND_ALE = 80, + MX6SX_PAD_NAND_CE0_B = 81, + MX6SX_PAD_NAND_CE1_B = 82, + MX6SX_PAD_NAND_CLE = 83, + MX6SX_PAD_NAND_DATA00 = 84 , + MX6SX_PAD_NAND_DATA01 = 85, + MX6SX_PAD_NAND_DATA02 = 86, + MX6SX_PAD_NAND_DATA03 = 87, + MX6SX_PAD_NAND_DATA04 = 88, + MX6SX_PAD_NAND_DATA05 = 89, + MX6SX_PAD_NAND_DATA06 = 90, + MX6SX_PAD_NAND_DATA07 = 91, + MX6SX_PAD_NAND_RE_B = 92, + MX6SX_PAD_NAND_READY_B = 93, + MX6SX_PAD_NAND_WE_B = 94, + MX6SX_PAD_NAND_WP_B = 95, + MX6SX_PAD_QSPI1A_DATA0 = 96, + MX6SX_PAD_QSPI1A_DATA1 = 97, + MX6SX_PAD_QSPI1A_DATA2 = 98, + MX6SX_PAD_QSPI1A_DATA3 = 99, + MX6SX_PAD_QSPI1A_DQS = 100, + MX6SX_PAD_QSPI1A_SCLK = 101, + MX6SX_PAD_QSPI1A_SS0_B = 102, + MX6SX_PAD_QSPI1A_SS1_B = 103, + MX6SX_PAD_QSPI1B_DATA0 = 104, + MX6SX_PAD_QSPI1B_DATA1 = 105, + MX6SX_PAD_QSPI1B_DATA2 = 106, + MX6SX_PAD_QSPI1B_DATA3 = 107, + MX6SX_PAD_QSPI1B_DQS = 108, + MX6SX_PAD_QSPI1B_SCLK = 109, + MX6SX_PAD_QSPI1B_SS0_B = 110, + MX6SX_PAD_QSPI1B_SS1_B = 111, + MX6SX_PAD_RGMII1_RD0 = 112, + MX6SX_PAD_RGMII1_RD1 = 113, + MX6SX_PAD_RGMII1_RD2 = 114, + MX6SX_PAD_RGMII1_RD3 = 115, + MX6SX_PAD_RGMII1_RX_CTL = 116, + MX6SX_PAD_RGMII1_RXC = 117, + MX6SX_PAD_RGMII1_TD0 = 118, + MX6SX_PAD_RGMII1_TD1 = 119, + MX6SX_PAD_RGMII1_TD2 = 120, + MX6SX_PAD_RGMII1_TD3 = 121, + MX6SX_PAD_RGMII1_TX_CTL = 122, + MX6SX_PAD_RGMII1_TXC = 123, + MX6SX_PAD_RGMII2_RD0 = 124, + MX6SX_PAD_RGMII2_RD1 = 125, + MX6SX_PAD_RGMII2_RD2 = 126, + MX6SX_PAD_RGMII2_RD3 = 127, + MX6SX_PAD_RGMII2_RX_CTL = 128, + MX6SX_PAD_RGMII2_RXC = 129, + MX6SX_PAD_RGMII2_TD0 = 130, + MX6SX_PAD_RGMII2_TD1 = 131, + MX6SX_PAD_RGMII2_TD2 = 132, + MX6SX_PAD_RGMII2_TD3 = 133, + MX6SX_PAD_RGMII2_TX_CTL = 134, + MX6SX_PAD_RGMII2_TXC = 135, + MX6SX_PAD_SD1_CLK = 136, + MX6SX_PAD_SD1_CMD = 137, + MX6SX_PAD_SD1_DATA0 = 138, + MX6SX_PAD_SD1_DATA1 = 139, + MX6SX_PAD_SD1_DATA2 = 140, + MX6SX_PAD_SD1_DATA3 = 141, + MX6SX_PAD_SD2_CLK = 142, + MX6SX_PAD_SD2_CMD = 143, + MX6SX_PAD_SD2_DATA0 = 144, + MX6SX_PAD_SD2_DATA1 = 145, + MX6SX_PAD_SD2_DATA2 = 146, + MX6SX_PAD_SD2_DATA3 = 147, + MX6SX_PAD_SD3_CLK = 148, + MX6SX_PAD_SD3_CMD = 149, + MX6SX_PAD_SD3_DATA0 = 150, + MX6SX_PAD_SD3_DATA1 = 151, + MX6SX_PAD_SD3_DATA2 = 152, + MX6SX_PAD_SD3_DATA3 = 153, + MX6SX_PAD_SD3_DATA4 = 154, + MX6SX_PAD_SD3_DATA5 = 155, + MX6SX_PAD_SD3_DATA6 = 156, + MX6SX_PAD_SD3_DATA7 = 157, + MX6SX_PAD_SD4_CLK = 158, + MX6SX_PAD_SD4_CMD = 159, + MX6SX_PAD_SD4_DATA0 = 160, + MX6SX_PAD_SD4_DATA1 = 161, + MX6SX_PAD_SD4_DATA2 = 162, + MX6SX_PAD_SD4_DATA3 = 163, + MX6SX_PAD_SD4_DATA4 = 164, + MX6SX_PAD_SD4_DATA5 = 165, + MX6SX_PAD_SD4_DATA6 = 166, + MX6SX_PAD_SD4_DATA7 = 167, + MX6SX_PAD_SD4_RESET_B = 168, + MX6SX_PAD_USB_H_DATA = 169, + MX6SX_PAD_USB_H_STROBE = 170, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B), + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA), + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE), +}; + +static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = { + .pins = imx6sx_pinctrl_pads, + .npins = ARRAY_SIZE(imx6sx_pinctrl_pads), +}; + +static struct of_device_id imx6sx_pinctrl_of_match[] = { + { .compatible = "fsl,imx6sx-iomuxc", }, + { /* sentinel */ } +}; + +static int imx6sx_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info); +} + +static struct platform_driver imx6sx_pinctrl_driver = { + .driver = { + .name = "imx6sx-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match), + }, + .probe = imx6sx_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6sx_pinctrl_init(void) +{ + return platform_driver_register(&imx6sx_pinctrl_driver); +} +arch_initcall(imx6sx_pinctrl_init); + +static void __exit imx6sx_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6sx_pinctrl_driver); +} +module_exit(imx6sx_pinctrl_exit); + +MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>"); +MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-ipq8064.c b/drivers/pinctrl/pinctrl-ipq8064.c new file mode 100644 index 00000000000..acafea4c3a3 --- /dev/null +++ b/drivers/pinctrl/pinctrl-ipq8064.c @@ -0,0 +1,653 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc ipq8064_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + + PINCTRL_PIN(69, "SDC3_CLK"), + PINCTRL_PIN(70, "SDC3_CMD"), + PINCTRL_PIN(71, "SDC3_DATA"), +}; + +#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_IPQ_GPIO_PINS(0); +DECLARE_IPQ_GPIO_PINS(1); +DECLARE_IPQ_GPIO_PINS(2); +DECLARE_IPQ_GPIO_PINS(3); +DECLARE_IPQ_GPIO_PINS(4); +DECLARE_IPQ_GPIO_PINS(5); +DECLARE_IPQ_GPIO_PINS(6); +DECLARE_IPQ_GPIO_PINS(7); +DECLARE_IPQ_GPIO_PINS(8); +DECLARE_IPQ_GPIO_PINS(9); +DECLARE_IPQ_GPIO_PINS(10); +DECLARE_IPQ_GPIO_PINS(11); +DECLARE_IPQ_GPIO_PINS(12); +DECLARE_IPQ_GPIO_PINS(13); +DECLARE_IPQ_GPIO_PINS(14); +DECLARE_IPQ_GPIO_PINS(15); +DECLARE_IPQ_GPIO_PINS(16); +DECLARE_IPQ_GPIO_PINS(17); +DECLARE_IPQ_GPIO_PINS(18); +DECLARE_IPQ_GPIO_PINS(19); +DECLARE_IPQ_GPIO_PINS(20); +DECLARE_IPQ_GPIO_PINS(21); +DECLARE_IPQ_GPIO_PINS(22); +DECLARE_IPQ_GPIO_PINS(23); +DECLARE_IPQ_GPIO_PINS(24); +DECLARE_IPQ_GPIO_PINS(25); +DECLARE_IPQ_GPIO_PINS(26); +DECLARE_IPQ_GPIO_PINS(27); +DECLARE_IPQ_GPIO_PINS(28); +DECLARE_IPQ_GPIO_PINS(29); +DECLARE_IPQ_GPIO_PINS(30); +DECLARE_IPQ_GPIO_PINS(31); +DECLARE_IPQ_GPIO_PINS(32); +DECLARE_IPQ_GPIO_PINS(33); +DECLARE_IPQ_GPIO_PINS(34); +DECLARE_IPQ_GPIO_PINS(35); +DECLARE_IPQ_GPIO_PINS(36); +DECLARE_IPQ_GPIO_PINS(37); +DECLARE_IPQ_GPIO_PINS(38); +DECLARE_IPQ_GPIO_PINS(39); +DECLARE_IPQ_GPIO_PINS(40); +DECLARE_IPQ_GPIO_PINS(41); +DECLARE_IPQ_GPIO_PINS(42); +DECLARE_IPQ_GPIO_PINS(43); +DECLARE_IPQ_GPIO_PINS(44); +DECLARE_IPQ_GPIO_PINS(45); +DECLARE_IPQ_GPIO_PINS(46); +DECLARE_IPQ_GPIO_PINS(47); +DECLARE_IPQ_GPIO_PINS(48); +DECLARE_IPQ_GPIO_PINS(49); +DECLARE_IPQ_GPIO_PINS(50); +DECLARE_IPQ_GPIO_PINS(51); +DECLARE_IPQ_GPIO_PINS(52); +DECLARE_IPQ_GPIO_PINS(53); +DECLARE_IPQ_GPIO_PINS(54); +DECLARE_IPQ_GPIO_PINS(55); +DECLARE_IPQ_GPIO_PINS(56); +DECLARE_IPQ_GPIO_PINS(57); +DECLARE_IPQ_GPIO_PINS(58); +DECLARE_IPQ_GPIO_PINS(59); +DECLARE_IPQ_GPIO_PINS(60); +DECLARE_IPQ_GPIO_PINS(61); +DECLARE_IPQ_GPIO_PINS(62); +DECLARE_IPQ_GPIO_PINS(63); +DECLARE_IPQ_GPIO_PINS(64); +DECLARE_IPQ_GPIO_PINS(65); +DECLARE_IPQ_GPIO_PINS(66); +DECLARE_IPQ_GPIO_PINS(67); +DECLARE_IPQ_GPIO_PINS(68); + +static const unsigned int sdc3_clk_pins[] = { 69 }; +static const unsigned int sdc3_cmd_pins[] = { 70 }; +static const unsigned int sdc3_data_pins[] = { 71 }; + +#define FUNCTION(fname) \ + [IPQ_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + IPQ_MUX_NA, /* gpio mode */ \ + IPQ_MUX_##f1, \ + IPQ_MUX_##f2, \ + IPQ_MUX_##f3, \ + IPQ_MUX_##f4, \ + IPQ_MUX_##f5, \ + IPQ_MUX_##f6, \ + IPQ_MUX_##f7, \ + IPQ_MUX_##f8, \ + IPQ_MUX_##f9, \ + IPQ_MUX_##f10, \ + }, \ + .nfuncs = 11, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum ipq8064_functions { + IPQ_MUX_mdio, + IPQ_MUX_mi2s, + IPQ_MUX_pdm, + IPQ_MUX_ssbi, + IPQ_MUX_spmi, + IPQ_MUX_audio_pcm, + IPQ_MUX_gsbi1, + IPQ_MUX_gsbi2, + IPQ_MUX_gsbi4, + IPQ_MUX_gsbi5, + IPQ_MUX_gsbi5_spi_cs1, + IPQ_MUX_gsbi5_spi_cs2, + IPQ_MUX_gsbi5_spi_cs3, + IPQ_MUX_gsbi6, + IPQ_MUX_gsbi7, + IPQ_MUX_nss_spi, + IPQ_MUX_sdc1, + IPQ_MUX_spdif, + IPQ_MUX_nand, + IPQ_MUX_tsif1, + IPQ_MUX_tsif2, + IPQ_MUX_usb_fs_n, + IPQ_MUX_usb_fs, + IPQ_MUX_usb2_hsic, + IPQ_MUX_rgmii2, + IPQ_MUX_sata, + IPQ_MUX_pcie1_rst, + IPQ_MUX_pcie1_prsnt, + IPQ_MUX_pcie1_pwrflt, + IPQ_MUX_pcie1_pwren_n, + IPQ_MUX_pcie1_pwren, + IPQ_MUX_pcie1_clk_req, + IPQ_MUX_pcie2_rst, + IPQ_MUX_pcie2_prsnt, + IPQ_MUX_pcie2_pwrflt, + IPQ_MUX_pcie2_pwren_n, + IPQ_MUX_pcie2_pwren, + IPQ_MUX_pcie2_clk_req, + IPQ_MUX_pcie3_rst, + IPQ_MUX_pcie3_prsnt, + IPQ_MUX_pcie3_pwrflt, + IPQ_MUX_pcie3_pwren_n, + IPQ_MUX_pcie3_pwren, + IPQ_MUX_pcie3_clk_req, + IPQ_MUX_ps_hold, + IPQ_MUX_NA, +}; + +static const char * const mdio_groups[] = { + "gpio0", "gpio1", "gpio10", "gpio11", +}; + +static const char * const mi2s_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const pdm_groups[] = { + "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31", + "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58", + "gpio59", +}; + +static const char * const ssbi_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const spmi_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const audio_pcm_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const gsbi1_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54", +}; + +static const char * const gsbi2_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char * const gsbi4_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const gsbi5_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; + +static const char * const gsbi5_spi_cs1_groups[] = { + "gpio6", "gpio61", +}; + +static const char * const gsbi5_spi_cs2_groups[] = { + "gpio7", "gpio62", +}; + +static const char * const gsbi5_spi_cs3_groups[] = { + "gpio2", +}; + +static const char * const gsbi6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56", + "gpio57", "gpio58", +}; + +static const char * const gsbi7_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char * const nss_spi_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56", + "gpio57", "gpio58", +}; + +static const char * const sdc1_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const spdif_groups[] = { + "gpio10", "gpio48", +}; + +static const char * const nand_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", +}; + +static const char * const tsif1_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const tsif2_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const usb_fs_n_groups[] = { + "gpio6", +}; + +static const char * const usb_fs_groups[] = { + "gpio6", "gpio7", "gpio8", +}; + +static const char * const usb2_hsic_groups[] = { + "gpio67", "gpio68", +}; + +static const char * const rgmii2_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const sata_groups[] = { + "gpio10", +}; + +static const char * const pcie1_rst_groups[] = { + "gpio3", +}; + +static const char * const pcie1_prsnt_groups[] = { + "gpio3", "gpio11", +}; + +static const char * const pcie1_pwren_n_groups[] = { + "gpio4", "gpio12", +}; + +static const char * const pcie1_pwren_groups[] = { + "gpio4", "gpio12", +}; + +static const char * const pcie1_pwrflt_groups[] = { + "gpio5", "gpio13", +}; + +static const char * const pcie1_clk_req_groups[] = { + "gpio5", +}; + +static const char * const pcie2_rst_groups[] = { + "gpio48", +}; + +static const char * const pcie2_prsnt_groups[] = { + "gpio11", "gpio48", +}; + +static const char * const pcie2_pwren_n_groups[] = { + "gpio12", "gpio49", +}; + +static const char * const pcie2_pwren_groups[] = { + "gpio12", "gpio49", +}; + +static const char * const pcie2_pwrflt_groups[] = { + "gpio13", "gpio50", +}; + +static const char * const pcie2_clk_req_groups[] = { + "gpio50", +}; + +static const char * const pcie3_rst_groups[] = { + "gpio63", +}; + +static const char * const pcie3_prsnt_groups[] = { + "gpio11", +}; + +static const char * const pcie3_pwren_n_groups[] = { + "gpio12", +}; + +static const char * const pcie3_pwren_groups[] = { + "gpio12", +}; + +static const char * const pcie3_pwrflt_groups[] = { + "gpio13", +}; + +static const char * const pcie3_clk_req_groups[] = { + "gpio65", +}; + +static const char * const ps_hold_groups[] = { + "gpio26", +}; + +static const struct msm_function ipq8064_functions[] = { + FUNCTION(mdio), + FUNCTION(ssbi), + FUNCTION(spmi), + FUNCTION(mi2s), + FUNCTION(pdm), + FUNCTION(audio_pcm), + FUNCTION(gsbi1), + FUNCTION(gsbi2), + FUNCTION(gsbi4), + FUNCTION(gsbi5), + FUNCTION(gsbi5_spi_cs1), + FUNCTION(gsbi5_spi_cs2), + FUNCTION(gsbi5_spi_cs3), + FUNCTION(gsbi6), + FUNCTION(gsbi7), + FUNCTION(nss_spi), + FUNCTION(sdc1), + FUNCTION(spdif), + FUNCTION(nand), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(usb_fs_n), + FUNCTION(usb_fs), + FUNCTION(usb2_hsic), + FUNCTION(rgmii2), + FUNCTION(sata), + FUNCTION(pcie1_rst), + FUNCTION(pcie1_prsnt), + FUNCTION(pcie1_pwren_n), + FUNCTION(pcie1_pwren), + FUNCTION(pcie1_pwrflt), + FUNCTION(pcie1_clk_req), + FUNCTION(pcie2_rst), + FUNCTION(pcie2_prsnt), + FUNCTION(pcie2_pwren_n), + FUNCTION(pcie2_pwren), + FUNCTION(pcie2_pwrflt), + FUNCTION(pcie2_clk_req), + FUNCTION(pcie3_rst), + FUNCTION(pcie3_prsnt), + FUNCTION(pcie3_pwren_n), + FUNCTION(pcie3_pwren), + FUNCTION(pcie3_pwrflt), + FUNCTION(pcie3_clk_req), + FUNCTION(ps_hold), +}; + +static const struct msm_pingroup ipq8064_groups[] = { + PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA), + PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA), + PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA), + PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA), + PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA), + PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3), + SDC_PINGROUP(sdc3_data, 0x204a, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 69 + +static const struct msm_pinctrl_soc_data ipq8064_pinctrl = { + .pins = ipq8064_pins, + .npins = ARRAY_SIZE(ipq8064_pins), + .functions = ipq8064_functions, + .nfunctions = ARRAY_SIZE(ipq8064_functions), + .groups = ipq8064_groups, + .ngroups = ARRAY_SIZE(ipq8064_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int ipq8064_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq8064_pinctrl); +} + +static const struct of_device_id ipq8064_pinctrl_of_match[] = { + { .compatible = "qcom,ipq8064-pinctrl", }, + { }, +}; + +static struct platform_driver ipq8064_pinctrl_driver = { + .driver = { + .name = "ipq8064-pinctrl", + .owner = THIS_MODULE, + .of_match_table = ipq8064_pinctrl_of_match, + }, + .probe = ipq8064_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq8064_pinctrl_init(void) +{ + return platform_driver_register(&ipq8064_pinctrl_driver); +} +arch_initcall(ipq8064_pinctrl_init); + +static void __exit ipq8064_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq8064_pinctrl_driver); +} +module_exit(ipq8064_pinctrl_exit); + +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); +MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index 615c5002b75..d22ca252b80 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -52,7 +52,8 @@ static void ltq_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, int i; for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN || + map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) kfree(map[i].data.configs.configs); kfree(map); } diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h index 6d07f023853..c7cfad5527d 100644 --- a/drivers/pinctrl/pinctrl-lantiq.h +++ b/drivers/pinctrl/pinctrl-lantiq.h @@ -10,6 +10,7 @@ */ #ifndef __PINCTRL_LANTIQ_H +#define __PINCTRL_LANTIQ_H #include <linux/clkdev.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c new file mode 100644 index 00000000000..df6dda4ce80 --- /dev/null +++ b/drivers/pinctrl/pinctrl-msm.c @@ -0,0 +1,939 @@ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/slab.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/spinlock.h> + +#include "core.h" +#include "pinconf.h" +#include "pinctrl-msm.h" +#include "pinctrl-utils.h" + +#define MAX_NR_GPIO 300 + +/** + * struct msm_pinctrl - state for a pinctrl-msm device + * @dev: device handle. + * @pctrl: pinctrl handle. + * @chip: gpiochip handle. + * @irq: parent irq for the TLMM irq_chip. + * @lock: Spinlock to protect register resources as well + * as msm_pinctrl data structures. + * @enabled_irqs: Bitmap of currently enabled irqs. + * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge + * detection. + * @soc; Reference to soc_data of platform specific data. + * @regs: Base address for the TLMM register map. + */ +struct msm_pinctrl { + struct device *dev; + struct pinctrl_dev *pctrl; + struct gpio_chip chip; + int irq; + + spinlock_t lock; + + DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + + const struct msm_pinctrl_soc_data *soc; + void __iomem *regs; +}; + +static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) +{ + return container_of(gc, struct msm_pinctrl, chip); +} + +static int msm_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->ngroups; +} + +static const char *msm_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->groups[group].name; +} + +static int msm_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->soc->groups[group].pins; + *num_pins = pctrl->soc->groups[group].npins; + return 0; +} + +static const struct pinctrl_ops msm_pinctrl_ops = { + .get_groups_count = msm_get_groups_count, + .get_group_name = msm_get_group_name, + .get_group_pins = msm_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int msm_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->nfunctions; +} + +static const char *msm_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->functions[function].name; +} + +static int msm_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->soc->functions[function].groups; + *num_groups = pctrl->soc->functions[function].ngroups; + return 0; +} + +static int msm_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + int i; + + g = &pctrl->soc->groups[group]; + + if (WARN_ON(g->mux_bit < 0)) + return -EINVAL; + + for (i = 0; i < g->nfuncs; i++) { + if (g->funcs[i] == function) + break; + } + + if (WARN_ON(i == g->nfuncs)) + return -EINVAL; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->ctl_reg); + val &= ~(0x7 << g->mux_bit); + val |= i << g->mux_bit; + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static void msm_pinmux_disable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[group]; + + if (WARN_ON(g->mux_bit < 0)) + return; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* Clear the mux bits to select gpio mode */ + val = readl(pctrl->regs + g->ctl_reg); + val &= ~(0x7 << g->mux_bit); + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static const struct pinmux_ops msm_pinmux_ops = { + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, + .get_function_groups = msm_get_function_groups, + .enable = msm_pinmux_enable, + .disable = msm_pinmux_disable, +}; + +static int msm_config_reg(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g, + unsigned param, + unsigned *mask, + unsigned *bit) +{ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + *bit = g->pull_bit; + *mask = 3; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + *bit = g->drv_bit; + *mask = 7; + break; + case PIN_CONFIG_OUTPUT: + *bit = g->oe_bit; + *mask = 1; + break; + default: + dev_err(pctrl->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + + return 0; +} + +static int msm_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + dev_err(pctldev->dev, "pin_config_set op not supported\n"); + return -ENOTSUPP; +} + +static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +{ + dev_err(pctldev->dev, "pin_config_set op not supported\n"); + return -ENOTSUPP; +} + +#define MSM_NO_PULL 0 +#define MSM_PULL_DOWN 1 +#define MSM_PULL_UP 3 + +static unsigned msm_regval_to_drive(u32 val) +{ + return (val + 1) * 2; +} + +static int msm_config_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned param = pinconf_to_config_param(*config); + unsigned mask; + unsigned arg; + unsigned bit; + int ret; + u32 val; + + g = &pctrl->soc->groups[group]; + + ret = msm_config_reg(pctrl, g, param, &mask, &bit); + if (ret < 0) + return ret; + + val = readl(pctrl->regs + g->ctl_reg); + arg = (val >> bit) & mask; + + /* Convert register value to pinconf value */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = arg == MSM_NO_PULL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = arg == MSM_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = arg == MSM_PULL_UP; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = msm_regval_to_drive(arg); + break; + case PIN_CONFIG_OUTPUT: + /* Pin is not output */ + if (!arg) + return -EINVAL; + + val = readl(pctrl->regs + g->io_reg); + arg = !!(val & BIT(g->in_bit)); + break; + default: + dev_err(pctrl->dev, "Unsupported config parameter: %x\n", + param); + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int msm_config_group_set(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *configs, + unsigned num_configs) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + unsigned param; + unsigned mask; + unsigned arg; + unsigned bit; + int ret; + u32 val; + int i; + + g = &pctrl->soc->groups[group]; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + ret = msm_config_reg(pctrl, g, param, &mask, &bit); + if (ret < 0) + return ret; + + /* Convert pinconf values to register values */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = MSM_NO_PULL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = MSM_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = MSM_PULL_UP; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + /* Check for invalid values */ + if (arg > 16 || arg < 2 || (arg % 2) != 0) + arg = -1; + else + arg = (arg / 2) - 1; + break; + case PIN_CONFIG_OUTPUT: + /* set output value */ + spin_lock_irqsave(&pctrl->lock, flags); + val = readl(pctrl->regs + g->io_reg); + if (arg) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + + /* enable output */ + arg = 1; + break; + default: + dev_err(pctrl->dev, "Unsupported config parameter: %x\n", + param); + return -EINVAL; + } + + /* Range-check user-supplied value */ + if (arg & ~mask) { + dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); + return -EINVAL; + } + + spin_lock_irqsave(&pctrl->lock, flags); + val = readl(pctrl->regs + g->ctl_reg); + val &= ~(mask << bit); + val |= arg << bit; + writel(val, pctrl->regs + g->ctl_reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + } + + return 0; +} + +static const struct pinconf_ops msm_pinconf_ops = { + .pin_config_get = msm_config_get, + .pin_config_set = msm_config_set, + .pin_config_group_get = msm_config_group_get, + .pin_config_group_set = msm_config_group_set, +}; + +static struct pinctrl_desc msm_pinctrl_desc = { + .pctlops = &msm_pinctrl_ops, + .pmxops = &msm_pinmux_ops, + .confops = &msm_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->ctl_reg); + val &= ~BIT(g->oe_bit); + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->io_reg); + if (value) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + + val = readl(pctrl->regs + g->ctl_reg); + val |= BIT(g->oe_bit); + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + u32 val; + + g = &pctrl->soc->groups[offset]; + + val = readl(pctrl->regs + g->io_reg); + return !!(val & BIT(g->in_bit)); +} + +static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->io_reg); + if (value) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + return pinctrl_request_gpio(gpio); +} + +static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + return pinctrl_free_gpio(gpio); +} + +#ifdef CONFIG_DEBUG_FS +#include <linux/seq_file.h> + +static void msm_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, + unsigned gpio) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned func; + int is_out; + int drive; + int pull; + u32 ctl_reg; + + static const char * const pulls[] = { + "no pull", + "pull down", + "keeper", + "pull up" + }; + + g = &pctrl->soc->groups[offset]; + ctl_reg = readl(pctrl->regs + g->ctl_reg); + + is_out = !!(ctl_reg & BIT(g->oe_bit)); + func = (ctl_reg >> g->mux_bit) & 7; + drive = (ctl_reg >> g->drv_bit) & 7; + pull = (ctl_reg >> g->pull_bit) & 3; + + seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); + seq_printf(s, " %dmA", msm_regval_to_drive(drive)); + seq_printf(s, " %s", pulls[pull]); +} + +static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned gpio = chip->base; + unsigned i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define msm_gpio_dbg_show NULL +#endif + +static struct gpio_chip msm_gpio_template = { + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get = msm_gpio_get, + .set = msm_gpio_set, + .request = msm_gpio_request, + .free = msm_gpio_free, + .dbg_show = msm_gpio_dbg_show, +}; + +/* For dual-edge interrupts in software, since some hardware has no + * such support: + * + * At appropriate moments, this function may be called to flip the polarity + * settings of both-edge irq lines to try and catch the next edge. + * + * The attempt is considered successful if: + * - the status bit goes high, indicating that an edge was caught, or + * - the input value of the gpio doesn't change during the attempt. + * If the value changes twice during the process, that would cause the first + * test to fail but would force the second, as two opposite + * transitions would cause a detection no matter the polarity setting. + * + * The do-loop tries to sledge-hammer closed the timing hole between + * the initial value-read and the polarity-write - if the line value changes + * during that window, an interrupt is lost, the new polarity setting is + * incorrect, and the first success test will fail, causing a retry. + * + * Algorithm comes from Google's msmgpio driver. + */ +static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g, + struct irq_data *d) +{ + int loop_limit = 100; + unsigned val, val2, intstat; + unsigned pol; + + do { + val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); + + pol = readl(pctrl->regs + g->intr_cfg_reg); + pol ^= BIT(g->intr_polarity_bit); + writel(pol, pctrl->regs + g->intr_cfg_reg); + + val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); + intstat = readl(pctrl->regs + g->intr_status_reg); + if (intstat || (val == val2)) + return; + } while (loop_limit-- > 0); + dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", + val, val2); +} + +static void msm_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->intr_cfg_reg); + val &= ~BIT(g->intr_enable_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + + clear_bit(d->hwirq, pctrl->enabled_irqs); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void msm_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->intr_status_reg); + val &= ~BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + + val = readl(pctrl->regs + g->intr_cfg_reg); + val |= BIT(g->intr_enable_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + + set_bit(d->hwirq, pctrl->enabled_irqs); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void msm_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->intr_status_reg); + if (g->intr_ack_high) + val |= BIT(g->intr_status_bit); + else + val &= ~BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + + if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(pctrl, g, d); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +#define INTR_TARGET_PROC_APPS 4 + +static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* + * For hw without possibility of detecting both edges + */ + if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) + set_bit(d->hwirq, pctrl->dual_edge_irqs); + else + clear_bit(d->hwirq, pctrl->dual_edge_irqs); + + /* Route interrupts to application cpu */ + val = readl(pctrl->regs + g->intr_target_reg); + val &= ~(7 << g->intr_target_bit); + val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; + writel(val, pctrl->regs + g->intr_target_reg); + + /* Update configuration for gpio. + * RAW_STATUS_EN is left on for all gpio irqs. Due to the + * internal circuitry of TLMM, toggling the RAW_STATUS + * could cause the INTR_STATUS to be set for EDGE interrupts. + */ + val = readl(pctrl->regs + g->intr_cfg_reg); + val |= BIT(g->intr_raw_status_bit); + if (g->intr_detection_width == 2) { + val &= ~(3 << g->intr_detection_bit); + val &= ~(1 << g->intr_polarity_bit); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val |= 1 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_FALLING: + val |= 2 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_BOTH: + val |= 3 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_LEVEL_LOW: + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= BIT(g->intr_polarity_bit); + break; + } + } else if (g->intr_detection_width == 1) { + val &= ~(1 << g->intr_detection_bit); + val &= ~(1 << g->intr_polarity_bit); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val |= BIT(g->intr_detection_bit); + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_FALLING: + val |= BIT(g->intr_detection_bit); + break; + case IRQ_TYPE_EDGE_BOTH: + val |= BIT(g->intr_detection_bit); + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_LEVEL_LOW: + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= BIT(g->intr_polarity_bit); + break; + } + } else { + BUG(); + } + writel(val, pctrl->regs + g->intr_cfg_reg); + + if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(pctrl, g, d); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + __irq_set_handler_locked(d->irq, handle_level_irq); + else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + __irq_set_handler_locked(d->irq, handle_edge_irq); + + return 0; +} + +static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + unsigned long flags; + + spin_lock_irqsave(&pctrl->lock, flags); + + irq_set_irq_wake(pctrl->irq, on); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static struct irq_chip msm_gpio_irq_chip = { + .name = "msmgpio", + .irq_mask = msm_gpio_irq_mask, + .irq_unmask = msm_gpio_irq_unmask, + .irq_ack = msm_gpio_irq_ack, + .irq_set_type = msm_gpio_irq_set_type, + .irq_set_wake = msm_gpio_irq_set_wake, +}; + +static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + struct irq_chip *chip = irq_get_chip(irq); + int irq_pin; + int handled = 0; + u32 val; + int i; + + chained_irq_enter(chip, desc); + + /* + * Each pin has it's own IRQ status register, so use + * enabled_irq bitmap to limit the number of reads. + */ + for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { + g = &pctrl->soc->groups[i]; + val = readl(pctrl->regs + g->intr_status_reg); + if (val & BIT(g->intr_status_bit)) { + irq_pin = irq_find_mapping(gc->irqdomain, i); + generic_handle_irq(irq_pin); + handled++; + } + } + + /* No interrupts were flagged */ + if (handled == 0) + handle_bad_irq(irq, desc); + + chained_irq_exit(chip, desc); +} + +static int msm_gpio_init(struct msm_pinctrl *pctrl) +{ + struct gpio_chip *chip; + int ret; + unsigned ngpio = pctrl->soc->ngpios; + + if (WARN_ON(ngpio > MAX_NR_GPIO)) + return -EINVAL; + + chip = &pctrl->chip; + chip->base = 0; + chip->ngpio = ngpio; + chip->label = dev_name(pctrl->dev); + chip->dev = pctrl->dev; + chip->owner = THIS_MODULE; + chip->of_node = pctrl->dev->of_node; + + ret = gpiochip_add(&pctrl->chip); + if (ret) { + dev_err(pctrl->dev, "Failed register gpiochip\n"); + return ret; + } + + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); + if (ret) { + dev_err(pctrl->dev, "Failed to add pin range\n"); + return ret; + } + + ret = gpiochip_irqchip_add(chip, + &msm_gpio_irq_chip, + 0, + handle_edge_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); + return -ENOSYS; + } + + gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, + msm_gpio_irq_handler); + + return 0; +} + +int msm_pinctrl_probe(struct platform_device *pdev, + const struct msm_pinctrl_soc_data *soc_data) +{ + struct msm_pinctrl *pctrl; + struct resource *res; + int ret; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) { + dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); + return -ENOMEM; + } + pctrl->dev = &pdev->dev; + pctrl->soc = soc_data; + pctrl->chip = msm_gpio_template; + + spin_lock_init(&pctrl->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pctrl->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->regs)) + return PTR_ERR(pctrl->regs); + + pctrl->irq = platform_get_irq(pdev, 0); + if (pctrl->irq < 0) { + dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); + return pctrl->irq; + } + + msm_pinctrl_desc.name = dev_name(&pdev->dev); + msm_pinctrl_desc.pins = pctrl->soc->pins; + msm_pinctrl_desc.npins = pctrl->soc->npins; + pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); + if (!pctrl->pctrl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + + ret = msm_gpio_init(pctrl); + if (ret) { + pinctrl_unregister(pctrl->pctrl); + return ret; + } + + platform_set_drvdata(pdev, pctrl); + + dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); + + return 0; +} +EXPORT_SYMBOL(msm_pinctrl_probe); + +int msm_pinctrl_remove(struct platform_device *pdev) +{ + struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&pctrl->chip); + if (ret) { + dev_err(&pdev->dev, "Failed to remove gpiochip\n"); + return ret; + } + + pinctrl_unregister(pctrl->pctrl); + + return 0; +} +EXPORT_SYMBOL(msm_pinctrl_remove); + diff --git a/drivers/pinctrl/pinctrl-msm.h b/drivers/pinctrl/pinctrl-msm.h new file mode 100644 index 00000000000..7b2a227a590 --- /dev/null +++ b/drivers/pinctrl/pinctrl-msm.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __PINCTRL_MSM_H__ +#define __PINCTRL_MSM_H__ + +struct pinctrl_pin_desc; + +/** + * struct msm_function - a pinmux function + * @name: Name of the pinmux function. + * @groups: List of pingroups for this function. + * @ngroups: Number of entries in @groups. + */ +struct msm_function { + const char *name; + const char * const *groups; + unsigned ngroups; +}; + +/** + * struct msm_pingroup - Qualcomm pingroup definition + * @name: Name of the pingroup. + * @pins: A list of pins assigned to this pingroup. + * @npins: Number of entries in @pins. + * @funcs: A list of pinmux functions that can be selected for + * this group. The index of the selected function is used + * for programming the function selector. + * Entries should be indices into the groups list of the + * struct msm_pinctrl_soc_data. + * @ctl_reg: Offset of the register holding control bits for this group. + * @io_reg: Offset of the register holding input/output bits for this group. + * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. + * @intr_status_reg: Offset of the register holding the status bits for this group. + * @intr_target_reg: Offset of the register specifying routing of the interrupts + * from this group. + * @mux_bit: Offset in @ctl_reg for the pinmux function selection. + * @pull_bit: Offset in @ctl_reg for the bias configuration. + * @drv_bit: Offset in @ctl_reg for the drive strength configuration. + * @oe_bit: Offset in @ctl_reg for controlling output enable. + * @in_bit: Offset in @io_reg for the input bit value. + * @out_bit: Offset in @io_reg for the output bit value. + * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. + * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt + * status. + * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. + * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. + * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. + * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. + * @intr_detection_width: Number of bits used for specifying interrupt type, + * Should be 2 for SoCs that can detect both edges in hardware, + * otherwise 1. + */ +struct msm_pingroup { + const char *name; + const unsigned *pins; + unsigned npins; + + unsigned *funcs; + unsigned nfuncs; + + s16 ctl_reg; + s16 io_reg; + s16 intr_cfg_reg; + s16 intr_status_reg; + s16 intr_target_reg; + + unsigned mux_bit:5; + + unsigned pull_bit:5; + unsigned drv_bit:5; + + unsigned oe_bit:5; + unsigned in_bit:5; + unsigned out_bit:5; + + unsigned intr_enable_bit:5; + unsigned intr_status_bit:5; + unsigned intr_ack_high:1; + + unsigned intr_target_bit:5; + unsigned intr_raw_status_bit:5; + unsigned intr_polarity_bit:5; + unsigned intr_detection_bit:5; + unsigned intr_detection_width:5; +}; + +/** + * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration + * @pins: An array describing all pins the pin controller affects. + * @npins: The number of entries in @pins. + * @functions: An array describing all mux functions the SoC supports. + * @nfunctions: The number of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The numbmer of entries in @groups. + * @ngpio: The number of pingroups the driver should expose as GPIOs. + */ +struct msm_pinctrl_soc_data { + const struct pinctrl_pin_desc *pins; + unsigned npins; + const struct msm_function *functions; + unsigned nfunctions; + const struct msm_pingroup *groups; + unsigned ngroups; + unsigned ngpios; +}; + +int msm_pinctrl_probe(struct platform_device *pdev, + const struct msm_pinctrl_soc_data *soc_data); +int msm_pinctrl_remove(struct platform_device *pdev); + +#endif diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c new file mode 100644 index 00000000000..418306911a6 --- /dev/null +++ b/drivers/pinctrl/pinctrl-msm8x74.c @@ -0,0 +1,1040 @@ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8x74_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + + PINCTRL_PIN(146, "SDC1_CLK"), + PINCTRL_PIN(147, "SDC1_CMD"), + PINCTRL_PIN(148, "SDC1_DATA"), + PINCTRL_PIN(149, "SDC2_CLK"), + PINCTRL_PIN(150, "SDC2_CMD"), + PINCTRL_PIN(151, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); + +static const unsigned int sdc1_clk_pins[] = { 146 }; +static const unsigned int sdc1_cmd_pins[] = { 147 }; +static const unsigned int sdc1_data_pins[] = { 148 }; +static const unsigned int sdc2_clk_pins[] = { 149 }; +static const unsigned int sdc2_cmd_pins[] = { 150 }; +static const unsigned int sdc2_data_pins[] = { 151 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_NA, /* gpio mode */ \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7 \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +/* + * TODO: Add the rest of the possible functions and fill out + * the pingroup table below. + */ +enum msm8x74_functions { + MSM_MUX_cci_i2c0, + MSM_MUX_cci_i2c1, + MSM_MUX_blsp_i2c1, + MSM_MUX_blsp_i2c2, + MSM_MUX_blsp_i2c3, + MSM_MUX_blsp_i2c4, + MSM_MUX_blsp_i2c5, + MSM_MUX_blsp_i2c6, + MSM_MUX_blsp_i2c7, + MSM_MUX_blsp_i2c8, + MSM_MUX_blsp_i2c9, + MSM_MUX_blsp_i2c10, + MSM_MUX_blsp_i2c11, + MSM_MUX_blsp_i2c12, + MSM_MUX_blsp_spi1, + MSM_MUX_blsp_spi1_cs1, + MSM_MUX_blsp_spi1_cs2, + MSM_MUX_blsp_spi1_cs3, + MSM_MUX_blsp_spi2, + MSM_MUX_blsp_spi2_cs1, + MSM_MUX_blsp_spi2_cs2, + MSM_MUX_blsp_spi2_cs3, + MSM_MUX_blsp_spi3, + MSM_MUX_blsp_spi4, + MSM_MUX_blsp_spi5, + MSM_MUX_blsp_spi6, + MSM_MUX_blsp_spi7, + MSM_MUX_blsp_spi8, + MSM_MUX_blsp_spi9, + MSM_MUX_blsp_spi10, + MSM_MUX_blsp_spi10_cs1, + MSM_MUX_blsp_spi10_cs2, + MSM_MUX_blsp_spi10_cs3, + MSM_MUX_blsp_spi11, + MSM_MUX_blsp_spi12, + MSM_MUX_blsp_uart1, + MSM_MUX_blsp_uart2, + MSM_MUX_blsp_uart3, + MSM_MUX_blsp_uart4, + MSM_MUX_blsp_uart5, + MSM_MUX_blsp_uart6, + MSM_MUX_blsp_uart7, + MSM_MUX_blsp_uart8, + MSM_MUX_blsp_uart9, + MSM_MUX_blsp_uart10, + MSM_MUX_blsp_uart11, + MSM_MUX_blsp_uart12, + MSM_MUX_blsp_uim1, + MSM_MUX_blsp_uim2, + MSM_MUX_blsp_uim3, + MSM_MUX_blsp_uim4, + MSM_MUX_blsp_uim5, + MSM_MUX_blsp_uim6, + MSM_MUX_blsp_uim7, + MSM_MUX_blsp_uim8, + MSM_MUX_blsp_uim9, + MSM_MUX_blsp_uim10, + MSM_MUX_blsp_uim11, + MSM_MUX_blsp_uim12, + MSM_MUX_uim1, + MSM_MUX_uim2, + MSM_MUX_uim_batt_alarm, + MSM_MUX_sdc3, + MSM_MUX_sdc4, + MSM_MUX_gcc_gp_clk1, + MSM_MUX_gcc_gp_clk2, + MSM_MUX_gcc_gp_clk3, + MSM_MUX_qua_mi2s, + MSM_MUX_pri_mi2s, + MSM_MUX_spkr_mi2s, + MSM_MUX_ter_mi2s, + MSM_MUX_sec_mi2s, + MSM_MUX_hdmi_cec, + MSM_MUX_hdmi_ddc, + MSM_MUX_hdmi_hpd, + MSM_MUX_edp_hpd, + MSM_MUX_mdp_vsync, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_cam_mclk2, + MSM_MUX_cam_mclk3, + MSM_MUX_cci_timer0, + MSM_MUX_cci_timer1, + MSM_MUX_cci_timer2, + MSM_MUX_cci_timer3, + MSM_MUX_cci_timer4, + MSM_MUX_cci_async_in0, + MSM_MUX_cci_async_in1, + MSM_MUX_cci_async_in2, + MSM_MUX_gp_pdm0, + MSM_MUX_gp_pdm1, + MSM_MUX_gp_pdm2, + MSM_MUX_gp0_clk, + MSM_MUX_gp1_clk, + MSM_MUX_gp_mn, + MSM_MUX_tsif1, + MSM_MUX_tsif2, + MSM_MUX_hsic, + MSM_MUX_grfc, + MSM_MUX_audio_ref_clk, + MSM_MUX_bt, + MSM_MUX_fm, + MSM_MUX_wlan, + MSM_MUX_slimbus, + MSM_MUX_NA, +}; + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi1_cs1_groups[] = { "gpio8" }; +static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" }; +static const char * const blsp_spi1_cs3_groups[] = { "gpio10" }; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; +static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" }; +static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" }; +static const char * const blsp_spi2_cs3_groups[] = { "gpio66" }; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" }; +static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" }; + +static const char * const blsp_uart4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; +static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" }; +static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" }; +static const char * const blsp_spi4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; + +static const char * const blsp_uart5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; +static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" }; +static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" }; +static const char * const blsp_spi5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; + +static const char * const blsp_uart6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; +static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" }; +static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; +static const char * const blsp_spi6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; + +static const char * const blsp_uart7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" }; +static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" }; +static const char * const blsp_spi7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const char * const blsp_uart8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; +static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" }; +static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" }; +static const char * const blsp_spi8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; + +static const char * const blsp_uart9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" }; +static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" }; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const blsp_uart10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" }; +static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" }; +static const char * const blsp_spi10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" }; +static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" }; +static const char * const blsp_spi10_cs3_groups[] = { "gpio90" }; + +static const char * const blsp_uart11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; +static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" }; +static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; +static const char * const blsp_spi11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; + +static const char * const blsp_uart12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; +static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" }; +static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" }; +static const char * const blsp_spi12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const char * const uim1_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100" +}; + +static const char * const uim2_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const uim_batt_alarm_groups[] = { "gpio101" }; + +static const char * const sdc3_groups[] = { + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + +static const char * const sdc4_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const gp0_clk_groups[] = { "gpio26" }; +static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" }; +static const char * const gp_mn_groups[] = { "gpio29" }; +static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" }; +static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" }; +static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" }; + +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; + +static const char * const spkr_mi2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; + +static const char * const ter_mi2s_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77" +}; + +static const char * const sec_mi2s_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; + +static const char * const hdmi_cec_groups[] = { "gpio31" }; +static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" }; +static const char * const hdmi_hpd_groups[] = { "gpio34" }; +static const char * const edp_hpd_groups[] = { "gpio102" }; + +static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" }; +static const char * const cam_mclk0_groups[] = { "gpio15" }; +static const char * const cam_mclk1_groups[] = { "gpio16" }; +static const char * const cam_mclk2_groups[] = { "gpio17" }; +static const char * const cam_mclk3_groups[] = { "gpio18" }; + +static const char * const cci_timer0_groups[] = { "gpio23" }; +static const char * const cci_timer1_groups[] = { "gpio24" }; +static const char * const cci_timer2_groups[] = { "gpio25" }; +static const char * const cci_timer3_groups[] = { "gpio26" }; +static const char * const cci_timer4_groups[] = { "gpio27" }; +static const char * const cci_async_in0_groups[] = { "gpio28" }; +static const char * const cci_async_in1_groups[] = { "gpio26" }; +static const char * const cci_async_in2_groups[] = { "gpio27" }; + +static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" }; +static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" }; +static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" }; + +static const char * const tsif1_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92" +}; + +static const char * const tsif2_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const hsic_groups[] = { "gpio144", "gpio145" }; +static const char * const grfc_groups[] = { + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", + "gpio128", "gpio136", "gpio137", "gpio141", "gpio143" +}; + +static const char * const audio_ref_clk_groups[] = { "gpio69" }; + +static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" }; + +static const char * const fm_groups[] = { "gpio41", "gpio42" }; + +static const char * const wlan_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + +static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; + +static const struct msm_function msm8x74_functions[] = { + FUNCTION(cci_i2c0), + FUNCTION(cci_i2c1), + FUNCTION(uim1), + FUNCTION(uim2), + FUNCTION(uim_batt_alarm), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(blsp_uim3), + FUNCTION(blsp_uim4), + FUNCTION(blsp_uim5), + FUNCTION(blsp_uim6), + FUNCTION(blsp_uim7), + FUNCTION(blsp_uim8), + FUNCTION(blsp_uim9), + FUNCTION(blsp_uim10), + FUNCTION(blsp_uim11), + FUNCTION(blsp_uim12), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_i2c6), + FUNCTION(blsp_i2c7), + FUNCTION(blsp_i2c8), + FUNCTION(blsp_i2c9), + FUNCTION(blsp_i2c10), + FUNCTION(blsp_i2c11), + FUNCTION(blsp_i2c12), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi1_cs1), + FUNCTION(blsp_spi1_cs2), + FUNCTION(blsp_spi1_cs3), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi2_cs1), + FUNCTION(blsp_spi2_cs2), + FUNCTION(blsp_spi2_cs3), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_spi7), + FUNCTION(blsp_spi8), + FUNCTION(blsp_spi9), + FUNCTION(blsp_spi10), + FUNCTION(blsp_spi10_cs1), + FUNCTION(blsp_spi10_cs2), + FUNCTION(blsp_spi10_cs3), + FUNCTION(blsp_spi11), + FUNCTION(blsp_spi12), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(blsp_uart5), + FUNCTION(blsp_uart6), + FUNCTION(blsp_uart7), + FUNCTION(blsp_uart8), + FUNCTION(blsp_uart9), + FUNCTION(blsp_uart10), + FUNCTION(blsp_uart11), + FUNCTION(blsp_uart12), + FUNCTION(sdc3), + FUNCTION(sdc4), + FUNCTION(gcc_gp_clk1), + FUNCTION(gcc_gp_clk2), + FUNCTION(gcc_gp_clk3), + FUNCTION(qua_mi2s), + FUNCTION(pri_mi2s), + FUNCTION(spkr_mi2s), + FUNCTION(ter_mi2s), + FUNCTION(sec_mi2s), + FUNCTION(mdp_vsync), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(cam_mclk2), + FUNCTION(cam_mclk3), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cci_async_in0), + FUNCTION(cci_async_in1), + FUNCTION(cci_async_in2), + FUNCTION(hdmi_cec), + FUNCTION(hdmi_ddc), + FUNCTION(hdmi_hpd), + FUNCTION(edp_hpd), + FUNCTION(gp_pdm0), + FUNCTION(gp_pdm1), + FUNCTION(gp_pdm2), + FUNCTION(gp0_clk), + FUNCTION(gp1_clk), + FUNCTION(gp_mn), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(hsic), + FUNCTION(grfc), + FUNCTION(audio_ref_clk), + FUNCTION(bt), + FUNCTION(fm), + FUNCTION(wlan), + FUNCTION(slimbus), +}; + +static const struct msm_pingroup msm8x74_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA), + PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA), + PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA), + PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA), + PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA), + PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA), + PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA), + PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA), + PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA), + PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA), + PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA), + PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA), + PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA), + PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA), + PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA), + PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA), + PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA), + PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA), + PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA), + PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA), + PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA), + PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA), + PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA), + PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA), + PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA), + PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA), + PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA), + PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA), + PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA), + PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA), + PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 146 + +static const struct msm_pinctrl_soc_data msm8x74_pinctrl = { + .pins = msm8x74_pins, + .npins = ARRAY_SIZE(msm8x74_pins), + .functions = msm8x74_functions, + .nfunctions = ARRAY_SIZE(msm8x74_functions), + .groups = msm8x74_groups, + .ngroups = ARRAY_SIZE(msm8x74_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8x74_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8x74_pinctrl); +} + +static const struct of_device_id msm8x74_pinctrl_of_match[] = { + { .compatible = "qcom,msm8974-pinctrl", }, + { }, +}; + +static struct platform_driver msm8x74_pinctrl_driver = { + .driver = { + .name = "msm8x74-pinctrl", + .owner = THIS_MODULE, + .of_match_table = msm8x74_pinctrl_of_match, + }, + .probe = msm8x74_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8x74_pinctrl_init(void) +{ + return platform_driver_register(&msm8x74_pinctrl_driver); +} +arch_initcall(msm8x74_pinctrl_init); + +static void __exit msm8x74_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8x74_pinctrl_driver); +} +module_exit(msm8x74_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); +MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); + diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c index b45c4eb3579..40c76f26998 100644 --- a/drivers/pinctrl/pinctrl-mxs.c +++ b/drivers/pinctrl/pinctrl-mxs.c @@ -233,7 +233,8 @@ static int mxs_pinconf_get(struct pinctrl_dev *pctldev, } static int mxs_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { return -ENOTSUPP; } @@ -249,7 +250,8 @@ static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev, } static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); struct mxs_group *g = &d->soc->groups[group]; @@ -257,49 +259,56 @@ static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, u8 ma, vol, pull, bank, shift; u16 pin; u32 i; + int n; + unsigned long config; - ma = CONFIG_TO_MA(config); - vol = CONFIG_TO_VOL(config); - pull = CONFIG_TO_PULL(config); - - for (i = 0; i < g->npins; i++) { - bank = PINID_TO_BANK(g->pins[i]); - pin = PINID_TO_PIN(g->pins[i]); - - /* drive */ - reg = d->base + d->soc->regs->drive; - reg += bank * 0x40 + pin / 8 * 0x10; - - /* mA */ - if (config & MA_PRESENT) { - shift = pin % 8 * 4; - writel(0x3 << shift, reg + CLR); - writel(ma << shift, reg + SET); - } - - /* vol */ - if (config & VOL_PRESENT) { - shift = pin % 8 * 4 + 2; - if (vol) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); + for (n = 0; n < num_configs; n++) { + config = configs[n]; + + ma = CONFIG_TO_MA(config); + vol = CONFIG_TO_VOL(config); + pull = CONFIG_TO_PULL(config); + + for (i = 0; i < g->npins; i++) { + bank = PINID_TO_BANK(g->pins[i]); + pin = PINID_TO_PIN(g->pins[i]); + + /* drive */ + reg = d->base + d->soc->regs->drive; + reg += bank * 0x40 + pin / 8 * 0x10; + + /* mA */ + if (config & MA_PRESENT) { + shift = pin % 8 * 4; + writel(0x3 << shift, reg + CLR); + writel(ma << shift, reg + SET); + } + + /* vol */ + if (config & VOL_PRESENT) { + shift = pin % 8 * 4 + 2; + if (vol) + writel(1 << shift, reg + SET); + else + writel(1 << shift, reg + CLR); + } + + /* pull */ + if (config & PULL_PRESENT) { + reg = d->base + d->soc->regs->pull; + reg += bank * 0x10; + shift = pin; + if (pull) + writel(1 << shift, reg + SET); + else + writel(1 << shift, reg + CLR); + } } - /* pull */ - if (config & PULL_PRESENT) { - reg = d->base + d->soc->regs->pull; - reg += bank * 0x10; - shift = pin; - if (pull) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); - } - } + /* cache the config value for mxs_pinconf_group_get() */ + g->config = config; - /* cache the config value for mxs_pinconf_group_get() */ - g->config = config; + } /* for each config */ return 0; } @@ -515,7 +524,6 @@ int mxs_pinctrl_probe(struct platform_device *pdev, return 0; err: - platform_set_drvdata(pdev, NULL); iounmap(d->base); return ret; } @@ -525,7 +533,6 @@ int mxs_pinctrl_remove(struct platform_device *pdev) { struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); - platform_set_drvdata(pdev, NULL); pinctrl_unregister(d->pctl); iounmap(d->base); diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 435bf3078d2..8f6f16ef73f 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -4,7 +4,7 @@ * Copyright (C) 2008,2009 STMicroelectronics * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> - * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> + * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -21,8 +21,6 @@ #include <linux/gpio.h> #include <linux/spinlock.h> #include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> #include <linux/slab.h> #include <linux/of_device.h> #include <linux/of_address.h> @@ -32,8 +30,6 @@ #include <linux/pinctrl/pinconf.h> /* Since we request GPIOs from ourself */ #include <linux/pinctrl/consumer.h> -#include <linux/platform_data/pinctrl-nomadik.h> -#include <asm/mach/irq.h> #include "pinctrl-nomadik.h" #include "core.h" @@ -45,15 +41,216 @@ * Symbols in this file are called "nmk_gpio" for "nomadik gpio" */ +/* + * pin configurations are represented by 32-bit integers: + * + * bit 0.. 8 - Pin Number (512 Pins Maximum) + * bit 9..10 - Alternate Function Selection + * bit 11..12 - Pull up/down state + * bit 13 - Sleep mode behaviour + * bit 14 - Direction + * bit 15 - Value (if output) + * bit 16..18 - SLPM pull up/down state + * bit 19..20 - SLPM direction + * bit 21..22 - SLPM Value (if output) + * bit 23..25 - PDIS value (if input) + * bit 26 - Gpio mode + * bit 27 - Sleep mode + * + * to facilitate the definition, the following macros are provided + * + * PIN_CFG_DEFAULT - default config (0): + * pull up/down = disabled + * sleep mode = input/wakeup + * direction = input + * value = low + * SLPM direction = same as normal + * SLPM pull = same as normal + * SLPM value = same as normal + * + * PIN_CFG - default config with alternate function + */ + +typedef unsigned long pin_cfg_t; + +#define PIN_NUM_MASK 0x1ff +#define PIN_NUM(x) ((x) & PIN_NUM_MASK) + +#define PIN_ALT_SHIFT 9 +#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) +#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) +#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) +#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) +#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) +#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) + +#define PIN_PULL_SHIFT 11 +#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) +#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) +#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) +#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) +#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) + +#define PIN_SLPM_SHIFT 13 +#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) +#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) +#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) +#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) +/* These two replace the above in DB8500v2+ */ +#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) +#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) +#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE + +#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ +#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ + +#define PIN_DIR_SHIFT 14 +#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) +#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) +#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) +#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) + +#define PIN_VAL_SHIFT 15 +#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) +#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) +#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) +#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) + +#define PIN_SLPM_PULL_SHIFT 16 +#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL(x) \ + (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_NONE \ + ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_UP \ + ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_DOWN \ + ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) + +#define PIN_SLPM_DIR_SHIFT 19 +#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR(x) \ + (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) + +#define PIN_SLPM_VAL_SHIFT 21 +#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL(x) \ + (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) + +#define PIN_SLPM_PDIS_SHIFT 23 +#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) +#define PIN_SLPM_PDIS(x) \ + (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) +#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) +#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) +#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) + +#define PIN_LOWEMI_SHIFT 25 +#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) +#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) +#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) +#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) + +#define PIN_GPIOMODE_SHIFT 26 +#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) +#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) +#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) +#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) + +#define PIN_SLEEPMODE_SHIFT 27 +#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) +#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) +#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) +#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) + + +/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ +#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) +#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) +#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) +#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) +#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) + +#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) +#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) +#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) +#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) +#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) + +#define PIN_CFG_DEFAULT (0) + +#define PIN_CFG(num, alt) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt)) + +#define PIN_CFG_INPUT(num, alt, pull) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) + +#define PIN_CFG_OUTPUT(num, alt, val) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) + +/* + * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving + * the "gpio" namespace for generic and cross-machine functions + */ + +#define GPIO_BLOCK_SHIFT 5 +#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) + +/* Register in the logic block */ +#define NMK_GPIO_DAT 0x00 +#define NMK_GPIO_DATS 0x04 +#define NMK_GPIO_DATC 0x08 +#define NMK_GPIO_PDIS 0x0c +#define NMK_GPIO_DIR 0x10 +#define NMK_GPIO_DIRS 0x14 +#define NMK_GPIO_DIRC 0x18 +#define NMK_GPIO_SLPC 0x1c +#define NMK_GPIO_AFSLA 0x20 +#define NMK_GPIO_AFSLB 0x24 +#define NMK_GPIO_LOWEMI 0x28 + +#define NMK_GPIO_RIMSC 0x40 +#define NMK_GPIO_FIMSC 0x44 +#define NMK_GPIO_IS 0x48 +#define NMK_GPIO_IC 0x4c +#define NMK_GPIO_RWIMSC 0x50 +#define NMK_GPIO_FWIMSC 0x54 +#define NMK_GPIO_WKS 0x58 +/* These appear in DB8540 and later ASICs */ +#define NMK_GPIO_EDGELEVEL 0x5C +#define NMK_GPIO_LEVEL 0x60 + + +/* Pull up/down values */ +enum nmk_gpio_pull { + NMK_GPIO_PULL_NONE, + NMK_GPIO_PULL_UP, + NMK_GPIO_PULL_DOWN, +}; + +/* Sleep mode */ +enum nmk_gpio_slpm { + NMK_GPIO_SLPM_INPUT, + NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, + NMK_GPIO_SLPM_NOCHANGE, + NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, +}; + struct nmk_gpio_chip { struct gpio_chip chip; - struct irq_domain *domain; void __iomem *addr; struct clk *clk; unsigned int bank; unsigned int parent_irq; - int secondary_parent_irq; - u32 (*get_secondary_status)(unsigned int bank); + int latent_parent_irq; + u32 (*get_latent_status)(unsigned int bank); void (*set_ioforce)(bool enable); spinlock_t lock; bool sleepmode; @@ -218,7 +415,7 @@ nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) u32 falling = nmk_chip->fimsc & BIT(offset); u32 rising = nmk_chip->rimsc & BIT(offset); int gpio = nmk_chip->chip.base + offset; - int irq = irq_find_mapping(nmk_chip->domain, offset); + int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); struct irq_data *d = irq_get_irq_data(irq); if (!rising && !falling) @@ -337,97 +534,6 @@ static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); } -static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, - pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) -{ - static const char *afnames[] = { - [NMK_GPIO_ALT_GPIO] = "GPIO", - [NMK_GPIO_ALT_A] = "A", - [NMK_GPIO_ALT_B] = "B", - [NMK_GPIO_ALT_C] = "C" - }; - static const char *pullnames[] = { - [NMK_GPIO_PULL_NONE] = "none", - [NMK_GPIO_PULL_UP] = "up", - [NMK_GPIO_PULL_DOWN] = "down", - [3] /* illegal */ = "??" - }; - static const char *slpmnames[] = { - [NMK_GPIO_SLPM_INPUT] = "input/wakeup", - [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", - }; - - int pin = PIN_NUM(cfg); - int pull = PIN_PULL(cfg); - int af = PIN_ALT(cfg); - int slpm = PIN_SLPM(cfg); - int output = PIN_DIR(cfg); - int val = PIN_VAL(cfg); - bool glitch = af == NMK_GPIO_ALT_C; - - dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", - pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], - output ? "output " : "input", - output ? (val ? "high" : "low") : ""); - - if (sleep) { - int slpm_pull = PIN_SLPM_PULL(cfg); - int slpm_output = PIN_SLPM_DIR(cfg); - int slpm_val = PIN_SLPM_VAL(cfg); - - af = NMK_GPIO_ALT_GPIO; - - /* - * The SLPM_* values are normal values + 1 to allow zero to - * mean "same as normal". - */ - if (slpm_pull) - pull = slpm_pull - 1; - if (slpm_output) - output = slpm_output - 1; - if (slpm_val) - val = slpm_val - 1; - - dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", - pin, - slpm_pull ? pullnames[pull] : "same", - slpm_output ? (output ? "output" : "input") : "same", - slpm_val ? (val ? "high" : "low") : "same"); - } - - if (output) - __nmk_gpio_make_output(nmk_chip, offset, val); - else { - __nmk_gpio_make_input(nmk_chip, offset); - __nmk_gpio_set_pull(nmk_chip, offset, pull); - } - - __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); - - /* - * If the pin is switching to altfunc, and there was an interrupt - * installed on it which has been lazy disabled, actually mask the - * interrupt to prevent spurious interrupts that would occur while the - * pin is under control of the peripheral. Only SKE does this. - */ - if (af != NMK_GPIO_ALT_GPIO) - nmk_gpio_disable_lazy_irq(nmk_chip, offset); - - /* - * If we've backed up the SLPM registers (glitch workaround), modify - * the backups since they will be restored. - */ - if (slpmregs) { - if (slpm == NMK_GPIO_SLPM_NOCHANGE) - slpmregs[nmk_chip->bank] |= BIT(offset); - else - slpmregs[nmk_chip->bank] &= ~BIT(offset); - } else - __nmk_gpio_set_slpm(nmk_chip, offset, slpm); - - __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); -} - /* * Safe sequence used to switch IOs between GPIO and Alternate-C mode: * - Save SLPM registers @@ -474,210 +580,6 @@ static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) } } -static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) -{ - static unsigned int slpm[NUM_BANKS]; - unsigned long flags; - bool glitch = false; - int ret = 0; - int i; - - for (i = 0; i < num; i++) { - if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { - glitch = true; - break; - } - } - - spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); - - if (glitch) { - memset(slpm, 0xff, sizeof(slpm)); - - for (i = 0; i < num; i++) { - int pin = PIN_NUM(cfgs[i]); - int offset = pin % NMK_GPIO_PER_CHIP; - - if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) - slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); - } - - nmk_gpio_glitch_slpm_init(slpm); - } - - for (i = 0; i < num; i++) { - struct nmk_gpio_chip *nmk_chip; - int pin = PIN_NUM(cfgs[i]); - - nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; - if (!nmk_chip) { - ret = -EINVAL; - break; - } - - clk_enable(nmk_chip->clk); - spin_lock(&nmk_chip->lock); - __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, - cfgs[i], sleep, glitch ? slpm : NULL); - spin_unlock(&nmk_chip->lock); - clk_disable(nmk_chip->clk); - } - - if (glitch) - nmk_gpio_glitch_slpm_restore(slpm); - - spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); - - return ret; -} - -/** - * nmk_config_pin - configure a pin's mux attributes - * @cfg: pin confguration - * @sleep: Non-zero to apply the sleep mode configuration - * Configures a pin's mode (alternate function or GPIO), its pull up status, - * and its sleep mode based on the specified configuration. The @cfg is - * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These - * are constructed using, and can be further enhanced with, the macros in - * <linux/platform_data/pinctrl-nomadik.h> - * - * If a pin's mode is set to GPIO, it is configured as an input to avoid - * side-effects. The gpio can be manipulated later using standard GPIO API - * calls. - */ -int nmk_config_pin(pin_cfg_t cfg, bool sleep) -{ - return __nmk_config_pins(&cfg, 1, sleep); -} -EXPORT_SYMBOL(nmk_config_pin); - -/** - * nmk_config_pins - configure several pins at once - * @cfgs: array of pin configurations - * @num: number of elments in the array - * - * Configures several pins using nmk_config_pin(). Refer to that function for - * further information. - */ -int nmk_config_pins(pin_cfg_t *cfgs, int num) -{ - return __nmk_config_pins(cfgs, num, false); -} -EXPORT_SYMBOL(nmk_config_pins); - -int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) -{ - return __nmk_config_pins(cfgs, num, true); -} -EXPORT_SYMBOL(nmk_config_pins_sleep); - -/** - * nmk_gpio_set_slpm() - configure the sleep mode of a pin - * @gpio: pin number - * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, - * - * This register is actually in the pinmux layer, not the GPIO block itself. - * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP - * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). - * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is - * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. - * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), - * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. - * - * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO - * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is - * entered) regardless of the altfunction selected. Also wake-up detection is - * ENABLED. - * - * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains - * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS - * (for altfunction GPIO) or respective on-chip peripherals (for other - * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. - * - * Note that enable_irq_wake() will automatically enable wakeup detection. - */ -int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) -{ - struct nmk_gpio_chip *nmk_chip; - unsigned long flags; - - nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; - if (!nmk_chip) - return -EINVAL; - - clk_enable(nmk_chip->clk); - spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); - spin_lock(&nmk_chip->lock); - - __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); - - spin_unlock(&nmk_chip->lock); - spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); - clk_disable(nmk_chip->clk); - - return 0; -} - -/** - * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio - * @gpio: pin number - * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE - * - * Enables/disables pull up/down on a specified pin. This only takes effect if - * the pin is configured as an input (either explicitly or by the alternate - * function). - * - * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is - * configured as an input. Otherwise, due to the way the controller registers - * work, this function will change the value output on the pin. - */ -int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) -{ - struct nmk_gpio_chip *nmk_chip; - unsigned long flags; - - nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; - if (!nmk_chip) - return -EINVAL; - - clk_enable(nmk_chip->clk); - spin_lock_irqsave(&nmk_chip->lock, flags); - __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); - spin_unlock_irqrestore(&nmk_chip->lock, flags); - clk_disable(nmk_chip->clk); - - return 0; -} - -/* Mode functions */ -/** - * nmk_gpio_set_mode() - set the mux mode of a gpio pin - * @gpio: pin number - * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, - * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C - * - * Sets the mode of the specified pin to one of the alternate functions or - * plain GPIO. - */ -int nmk_gpio_set_mode(int gpio, int gpio_mode) -{ - struct nmk_gpio_chip *nmk_chip; - unsigned long flags; - - nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; - if (!nmk_chip) - return -EINVAL; - - clk_enable(nmk_chip->clk); - spin_lock_irqsave(&nmk_chip->lock, flags); - __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); - spin_unlock_irqrestore(&nmk_chip->lock, flags); - clk_disable(nmk_chip->clk); - - return 0; -} -EXPORT_SYMBOL(nmk_gpio_set_mode); - static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) { int i; @@ -741,11 +643,8 @@ static inline int nmk_gpio_get_bitmask(int gpio) static void nmk_gpio_irq_ack(struct irq_data *d) { - struct nmk_gpio_chip *nmk_chip; - - nmk_chip = irq_data_get_irq_chip_data(d); - if (!nmk_chip) - return; + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); clk_enable(nmk_chip->clk); writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); @@ -957,16 +856,15 @@ static struct irq_chip nmk_gpio_irq_chip = { static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, u32 status) { - struct nmk_gpio_chip *nmk_chip; struct irq_chip *host_chip = irq_get_chip(irq); + struct gpio_chip *chip = irq_desc_get_handler_data(desc); chained_irq_enter(host_chip, desc); - nmk_chip = irq_get_handler_data(irq); while (status) { int bit = __ffs(status); - generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit)); + generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); status &= ~BIT(bit); } @@ -975,7 +873,8 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { - struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); u32 status; clk_enable(nmk_chip->clk); @@ -985,29 +884,16 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) __nmk_gpio_irq_handler(irq, desc, status); } -static void nmk_gpio_secondary_irq_handler(unsigned int irq, +static void nmk_gpio_latent_irq_handler(unsigned int irq, struct irq_desc *desc) { - struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); - u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + u32 status = nmk_chip->get_latent_status(nmk_chip->bank); __nmk_gpio_irq_handler(irq, desc, status); } -static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) -{ - irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); - irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); - - if (nmk_chip->secondary_parent_irq >= 0) { - irq_set_chained_handler(nmk_chip->secondary_parent_irq, - nmk_gpio_secondary_irq_handler); - irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); - } - - return 0; -} - /* I/O Functions */ static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) @@ -1086,14 +972,6 @@ static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, return 0; } -static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct nmk_gpio_chip *nmk_chip = - container_of(chip, struct nmk_gpio_chip, chip); - - return irq_create_mapping(nmk_chip->domain, offset); -} - #ifdef CONFIG_DEBUG_FS #include <linux/seq_file.h> @@ -1136,14 +1014,14 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, (mode < 0) ? "unknown" : modes[mode], pull ? "pull" : "none"); - if (label && !is_out) { - int irq = gpio_to_irq(gpio); + if (!is_out) { + int irq = gpio_to_irq(gpio); struct irq_desc *desc = irq_to_desc(irq); /* This races with request_irq(), set_irq_type(), * and set_irq_wake() ... but those are "rare". */ - if (irq >= 0 && desc->action) { + if (irq > 0 && desc && desc->action) { char *trigger; u32 bitmask = nmk_gpio_get_bitmask(gpio); @@ -1192,9 +1070,8 @@ static struct gpio_chip nmk_gpio_template = { .get = nmk_gpio_get_input, .direction_output = nmk_gpio_make_output, .set = nmk_gpio_set_output, - .to_irq = nmk_gpio_to_irq, .dbg_show = nmk_gpio_dbg_show, - .can_sleep = 0, + .can_sleep = false, }; void nmk_gpio_clocks_enable(void) @@ -1293,75 +1170,37 @@ void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) } } -static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - struct nmk_gpio_chip *nmk_chip = d->host_data; - - if (!nmk_chip) - return -EINVAL; - - irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); - set_irq_flags(irq, IRQF_VALID); - irq_set_chip_data(irq, nmk_chip); - irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); - - return 0; -} - -const struct irq_domain_ops nmk_gpio_irq_simple_ops = { - .map = nmk_gpio_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - static int nmk_gpio_probe(struct platform_device *dev) { - struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; struct device_node *np = dev->dev.of_node; struct nmk_gpio_chip *nmk_chip; struct gpio_chip *chip; struct resource *res; struct clk *clk; - int secondary_irq; + int latent_irq; + bool supports_sleepmode; void __iomem *base; - int irq_start = 0; int irq; int ret; - if (!pdata && !np) { - dev_err(&dev->dev, "No platform data or device tree found\n"); - return -ENODEV; - } - - if (np) { - pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return -ENOMEM; - - if (of_get_property(np, "st,supports-sleepmode", NULL)) - pdata->supports_sleepmode = true; - - if (of_property_read_u32(np, "gpio-bank", &dev->id)) { - dev_err(&dev->dev, "gpio-bank property not found\n"); - return -EINVAL; - } + if (of_get_property(np, "st,supports-sleepmode", NULL)) + supports_sleepmode = true; + else + supports_sleepmode = false; - pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; - pdata->num_gpio = NMK_GPIO_PER_CHIP; + if (of_property_read_u32(np, "gpio-bank", &dev->id)) { + dev_err(&dev->dev, "gpio-bank property not found\n"); + return -EINVAL; } - res = platform_get_resource(dev, IORESOURCE_MEM, 0); - if (!res) - return -ENOENT; - irq = platform_get_irq(dev, 0); if (irq < 0) return irq; - secondary_irq = platform_get_irq(dev, 1); - if (secondary_irq >= 0 && !pdata->get_secondary_status) - return -EINVAL; + /* It's OK for this IRQ not to be present */ + latent_irq = platform_get_irq(dev, 1); + res = platform_get_resource(dev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&dev->dev, res); if (IS_ERR(base)) return PTR_ERR(base); @@ -1384,26 +1223,21 @@ static int nmk_gpio_probe(struct platform_device *dev) nmk_chip->addr = base; nmk_chip->chip = nmk_gpio_template; nmk_chip->parent_irq = irq; - nmk_chip->secondary_parent_irq = secondary_irq; - nmk_chip->get_secondary_status = pdata->get_secondary_status; - nmk_chip->set_ioforce = pdata->set_ioforce; - nmk_chip->sleepmode = pdata->supports_sleepmode; + nmk_chip->latent_parent_irq = latent_irq; + nmk_chip->sleepmode = supports_sleepmode; spin_lock_init(&nmk_chip->lock); chip = &nmk_chip->chip; - chip->base = pdata->first_gpio; - chip->ngpio = pdata->num_gpio; - chip->label = pdata->name ?: dev_name(&dev->dev); + chip->base = dev->id * NMK_GPIO_PER_CHIP; + chip->ngpio = NMK_GPIO_PER_CHIP; + chip->label = dev_name(&dev->dev); chip->dev = &dev->dev; chip->owner = THIS_MODULE; clk_enable(nmk_chip->clk); nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); clk_disable(nmk_chip->clk); - -#ifdef CONFIG_OF_GPIO chip->of_node = np; -#endif ret = gpiochip_add(&nmk_chip->chip); if (ret) @@ -1415,19 +1249,31 @@ static int nmk_gpio_probe(struct platform_device *dev) platform_set_drvdata(dev, nmk_chip); - if (!np) - irq_start = pdata->first_irq; - nmk_chip->domain = irq_domain_add_simple(np, - NMK_GPIO_PER_CHIP, irq_start, - &nmk_gpio_irq_simple_ops, nmk_chip); - if (!nmk_chip->domain) { - dev_err(&dev->dev, "failed to create irqdomain\n"); - /* Just do this, no matter if it fails */ + /* + * Let the generic code handle this edge IRQ, the the chained + * handler will perform the actual work of handling the parent + * interrupt. + */ + ret = gpiochip_irqchip_add(&nmk_chip->chip, + &nmk_gpio_irq_chip, + 0, + handle_edge_irq, + IRQ_TYPE_EDGE_FALLING); + if (ret) { + dev_err(&dev->dev, "could not add irqchip\n"); ret = gpiochip_remove(&nmk_chip->chip); - return -ENOSYS; + return -ENODEV; } - - nmk_gpio_init_irq(nmk_chip); + /* Then register the chain on the parent IRQ */ + gpiochip_set_chained_irqchip(&nmk_chip->chip, + &nmk_gpio_irq_chip, + nmk_chip->parent_irq, + nmk_gpio_irq_handler); + if (nmk_chip->latent_parent_irq > 0) + gpiochip_set_chained_irqchip(&nmk_chip->chip, + &nmk_gpio_irq_chip, + nmk_chip->latent_parent_irq, + nmk_gpio_latent_irq_handler); dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); @@ -1681,7 +1527,7 @@ static bool nmk_pinctrl_dt_get_config(struct device_node *np, return has_config; } -int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, +static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned *reserved_maps, @@ -1740,7 +1586,7 @@ exit: return ret; } -int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, +static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, unsigned *num_maps) { @@ -1807,7 +1653,7 @@ static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); const struct nmk_pingroup *g; static unsigned int slpm[NUM_BANKS]; - unsigned long flags; + unsigned long flags = 0; bool glitch; int ret = -EINVAL; int i; @@ -1993,7 +1839,7 @@ static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, } static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) + unsigned long *configs, unsigned num_configs) { static const char *pullnames[] = { [NMK_GPIO_PULL_NONE] = "none", @@ -2010,20 +1856,9 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, struct pinctrl_gpio_range *range; struct gpio_chip *chip; unsigned bit; - - /* - * The pin config contains pin number and altfunction fields, here - * we just ignore that part. It's being handled by the framework and - * pinmux callback respectively. - */ - pin_cfg_t cfg = (pin_cfg_t) config; - int pull = PIN_PULL(cfg); - int slpm = PIN_SLPM(cfg); - int output = PIN_DIR(cfg); - int val = PIN_VAL(cfg); - bool lowemi = PIN_LOWEMI(cfg); - bool gpiomode = PIN_GPIOMODE(cfg); - bool sleep = PIN_SLEEPMODE(cfg); + pin_cfg_t cfg; + int pull, slpm, output, val, i; + bool lowemi, gpiomode, sleep; range = nmk_match_gpio_range(pctldev, pin); if (!range) { @@ -2038,54 +1873,74 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, chip = range->gc; nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - if (sleep) { - int slpm_pull = PIN_SLPM_PULL(cfg); - int slpm_output = PIN_SLPM_DIR(cfg); - int slpm_val = PIN_SLPM_VAL(cfg); - - /* All pins go into GPIO mode at sleep */ - gpiomode = true; - + for (i = 0; i < num_configs; i++) { /* - * The SLPM_* values are normal values + 1 to allow zero to - * mean "same as normal". + * The pin config contains pin number and altfunction fields, + * here we just ignore that part. It's being handled by the + * framework and pinmux callback respectively. */ - if (slpm_pull) - pull = slpm_pull - 1; - if (slpm_output) - output = slpm_output - 1; - if (slpm_val) - val = slpm_val - 1; - - dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", - pin, - slpm_pull ? pullnames[pull] : "same", - slpm_output ? (output ? "output" : "input") : "same", - slpm_val ? (val ? "high" : "low") : "same"); - } + cfg = (pin_cfg_t) configs[i]; + pull = PIN_PULL(cfg); + slpm = PIN_SLPM(cfg); + output = PIN_DIR(cfg); + val = PIN_VAL(cfg); + lowemi = PIN_LOWEMI(cfg); + gpiomode = PIN_GPIOMODE(cfg); + sleep = PIN_SLEEPMODE(cfg); + + if (sleep) { + int slpm_pull = PIN_SLPM_PULL(cfg); + int slpm_output = PIN_SLPM_DIR(cfg); + int slpm_val = PIN_SLPM_VAL(cfg); + + /* All pins go into GPIO mode at sleep */ + gpiomode = true; + + /* + * The SLPM_* values are normal values + 1 to allow zero + * to mean "same as normal". + */ + if (slpm_pull) + pull = slpm_pull - 1; + if (slpm_output) + output = slpm_output - 1; + if (slpm_val) + val = slpm_val - 1; + + dev_dbg(nmk_chip->chip.dev, + "pin %d: sleep pull %s, dir %s, val %s\n", + pin, + slpm_pull ? pullnames[pull] : "same", + slpm_output ? (output ? "output" : "input") + : "same", + slpm_val ? (val ? "high" : "low") : "same"); + } - dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", - pin, cfg, pullnames[pull], slpmnames[slpm], - output ? "output " : "input", - output ? (val ? "high" : "low") : "", - lowemi ? "on" : "off"); + dev_dbg(nmk_chip->chip.dev, + "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", + pin, cfg, pullnames[pull], slpmnames[slpm], + output ? "output " : "input", + output ? (val ? "high" : "low") : "", + lowemi ? "on" : "off"); - clk_enable(nmk_chip->clk); - bit = pin % NMK_GPIO_PER_CHIP; - if (gpiomode) - /* No glitch when going to GPIO mode */ - __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); - if (output) - __nmk_gpio_make_output(nmk_chip, bit, val); - else { - __nmk_gpio_make_input(nmk_chip, bit); - __nmk_gpio_set_pull(nmk_chip, bit, pull); - } - /* TODO: isn't this only applicable on output pins? */ - __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); + clk_enable(nmk_chip->clk); + bit = pin % NMK_GPIO_PER_CHIP; + if (gpiomode) + /* No glitch when going to GPIO mode */ + __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); + if (output) + __nmk_gpio_make_output(nmk_chip, bit, val); + else { + __nmk_gpio_make_input(nmk_chip, bit); + __nmk_gpio_set_pull(nmk_chip, bit, pull); + } + /* TODO: isn't this only applicable on output pins? */ + __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); + + __nmk_gpio_set_slpm(nmk_chip, bit, slpm); + clk_disable(nmk_chip->clk); + } /* for each config */ - __nmk_gpio_set_slpm(nmk_chip, bit, slpm); - clk_disable(nmk_chip->clk); return 0; } @@ -2104,49 +1959,50 @@ static struct pinctrl_desc nmk_pinctrl_desc = { static const struct of_device_id nmk_pinctrl_match[] = { { - .compatible = "stericsson,nmk-pinctrl-stn8815", + .compatible = "stericsson,stn8815-pinctrl", .data = (void *)PINCTRL_NMK_STN8815, }, { - .compatible = "stericsson,nmk-pinctrl", + .compatible = "stericsson,db8500-pinctrl", .data = (void *)PINCTRL_NMK_DB8500, }, { - .compatible = "stericsson,nmk-pinctrl-db8540", + .compatible = "stericsson,db8540-pinctrl", .data = (void *)PINCTRL_NMK_DB8540, }, {}, }; -static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) +#ifdef CONFIG_PM_SLEEP +static int nmk_pinctrl_suspend(struct device *dev) { struct nmk_pinctrl *npct; - npct = platform_get_drvdata(pdev); + npct = dev_get_drvdata(dev); if (!npct) return -EINVAL; return pinctrl_force_sleep(npct->pctl); } -static int nmk_pinctrl_resume(struct platform_device *pdev) +static int nmk_pinctrl_resume(struct device *dev) { struct nmk_pinctrl *npct; - npct = platform_get_drvdata(pdev); + npct = dev_get_drvdata(dev); if (!npct) return -EINVAL; return pinctrl_force_default(npct->pctl); } +#endif static int nmk_pinctrl_probe(struct platform_device *pdev) { - const struct platform_device_id *platid = platform_get_device_id(pdev); + const struct of_device_id *match; struct device_node *np = pdev->dev.of_node; struct device_node *prcm_np; struct nmk_pinctrl *npct; - struct resource *res; unsigned int version = 0; int i; @@ -2154,16 +2010,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev) if (!npct) return -ENOMEM; - if (platid) - version = platid->driver_data; - else if (np) { - const struct of_device_id *match; - - match = of_match_device(nmk_pinctrl_match, &pdev->dev); - if (!match) - return -ENODEV; - version = (unsigned int) match->data; - } + match = of_match_device(nmk_pinctrl_match, &pdev->dev); + if (!match) + return -ENODEV; + version = (unsigned int) match->data; /* Poke in other ASIC variants here */ if (version == PINCTRL_NMK_STN8815) @@ -2173,17 +2023,9 @@ static int nmk_pinctrl_probe(struct platform_device *pdev) if (version == PINCTRL_NMK_DB8540) nmk_pinctrl_db8540_init(&npct->soc); - if (np) { - prcm_np = of_parse_phandle(np, "prcm", 0); - if (prcm_np) - npct->prcm_base = of_iomap(prcm_np, 0); - } - - /* Allow platform passed information to over-write DT. */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res) - npct->prcm_base = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); + prcm_np = of_parse_phandle(np, "prcm", 0); + if (prcm_np) + npct->prcm_base = of_iomap(prcm_np, 0); if (!npct->prcm_base) { if (version == PINCTRL_NMK_STN8815) { dev_info(&pdev->dev, @@ -2242,25 +2084,18 @@ static struct platform_driver nmk_gpio_driver = { .probe = nmk_gpio_probe, }; -static const struct platform_device_id nmk_pinctrl_id[] = { - { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, - { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, - { "pinctrl-db8540", PINCTRL_NMK_DB8540 }, - { } -}; +static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, + nmk_pinctrl_suspend, + nmk_pinctrl_resume); static struct platform_driver nmk_pinctrl_driver = { .driver = { .owner = THIS_MODULE, .name = "pinctrl-nomadik", .of_match_table = nmk_pinctrl_match, + .pm = &nmk_pinctrl_pm_ops, }, .probe = nmk_pinctrl_probe, - .id_table = nmk_pinctrl_id, -#ifdef CONFIG_PM - .suspend = nmk_pinctrl_suspend, - .resume = nmk_pinctrl_resume, -#endif }; static int __init nmk_gpio_init(void) diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h index bcd4191e10e..d8215f1e70c 100644 --- a/drivers/pinctrl/pinctrl-nomadik.h +++ b/drivers/pinctrl/pinctrl-nomadik.h @@ -1,13 +1,23 @@ #ifndef PINCTRL_PINCTRL_NOMADIK_H #define PINCTRL_PINCTRL_NOMADIK_H -#include <linux/platform_data/pinctrl-nomadik.h> - /* Package definitions */ #define PINCTRL_NMK_STN8815 0 #define PINCTRL_NMK_DB8500 1 #define PINCTRL_NMK_DB8540 2 +/* Alternate functions: function C is set in hw by setting both A and B */ +#define NMK_GPIO_ALT_GPIO 0 +#define NMK_GPIO_ALT_A 1 +#define NMK_GPIO_ALT_B 2 +#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) + +#define NMK_GPIO_ALT_CX_SHIFT 2 +#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C) +#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C) +#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C) +#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C) + #define PRCM_GPIOCR_ALTCX(pin_num,\ altc1_used, altc1_ri, altc1_cb,\ altc2_used, altc2_ri, altc2_cb,\ diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c new file mode 100644 index 00000000000..f13d0e78a41 --- /dev/null +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -0,0 +1,1076 @@ +/* + * pinctrl-palmas.c -- TI PALMAS series pin control driver. + * + * Copyright (c) 2013, NVIDIA Corporation. + * + * Author: Laxman Dewangan <ldewangan@nvidia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include <linux/delay.h> +#include <linux/module.h> +#include <linux/mfd/palmas.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pm.h> +#include <linux/slab.h> + +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + +#define PALMAS_PIN_GPIO0_ID 0 +#define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1 1 +#define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2 2 +#define PALMAS_PIN_GPIO3_CHRG_DET 3 +#define PALMAS_PIN_GPIO4_SYSEN1 4 +#define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL 5 +#define PALMAS_PIN_GPIO6_SYSEN2 6 +#define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD 7 +#define PALMAS_PIN_GPIO8_SIM1RSTI 8 +#define PALMAS_PIN_GPIO9_LOW_VBAT 9 +#define PALMAS_PIN_GPIO10_WIRELESS_CHRG1 10 +#define PALMAS_PIN_GPIO11_RCM 11 +#define PALMAS_PIN_GPIO12_SIM2RSTO 12 +#define PALMAS_PIN_GPIO13 13 +#define PALMAS_PIN_GPIO14 14 +#define PALMAS_PIN_GPIO15_SIM2RSTI 15 +#define PALMAS_PIN_VAC 16 +#define PALMAS_PIN_POWERGOOD_USB_PSEL 17 +#define PALMAS_PIN_NRESWARM 18 +#define PALMAS_PIN_PWRDOWN 19 +#define PALMAS_PIN_GPADC_START 20 +#define PALMAS_PIN_RESET_IN 21 +#define PALMAS_PIN_NSLEEP 22 +#define PALMAS_PIN_ENABLE1 23 +#define PALMAS_PIN_ENABLE2 24 +#define PALMAS_PIN_INT 25 +#define PALMAS_PIN_NUM (PALMAS_PIN_INT + 1) + +struct palmas_pin_function { + const char *name; + const char * const *groups; + unsigned ngroups; +}; + +struct palmas_pctrl_chip_info { + struct device *dev; + struct pinctrl_dev *pctl; + struct palmas *palmas; + int pins_current_opt[PALMAS_PIN_NUM]; + const struct palmas_pin_function *functions; + unsigned num_functions; + const struct palmas_pingroup *pin_groups; + int num_pin_groups; + const struct pinctrl_pin_desc *pins; + unsigned num_pins; +}; + +static const struct pinctrl_pin_desc palmas_pins_desc[] = { + PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"), + PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"), + PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"), + PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"), + PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"), + PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"), + PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"), + PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"), + PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"), + PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"), + PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"), + PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"), + PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"), + PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"), + PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"), + PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"), + PINCTRL_PIN(PALMAS_PIN_VAC, "vac"), + PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"), + PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"), + PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"), + PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"), + PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"), + PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"), + PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"), + PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"), + PINCTRL_PIN(PALMAS_PIN_INT, "int"), +}; + +static const char * const opt0_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", + "vac", + "powergood", + "nreswarm", + "pwrdown", + "gpadc_start", + "reset_in", + "nsleep", + "enable1", + "enable2", + "int", +}; + +static const char * const opt1_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio15", + "vac", + "powergood", +}; + +static const char * const opt2_groups[] = { + "gpio1", + "gpio2", + "gpio5", + "gpio7", +}; + +static const char * const opt3_groups[] = { + "gpio1", + "gpio2", +}; + +static const char * const gpio_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", +}; + +static const char * const led_groups[] = { + "gpio1", + "gpio2", +}; + +static const char * const pwm_groups[] = { + "gpio1", + "gpio2", +}; + +static const char * const regen_groups[] = { + "gpio2", +}; + +static const char * const sysen_groups[] = { + "gpio4", + "gpio6", +}; + +static const char * const clk32kgaudio_groups[] = { + "gpio5", +}; + +static const char * const id_groups[] = { + "gpio0", +}; + +static const char * const vbus_det_groups[] = { + "gpio1", +}; + +static const char * const chrg_det_groups[] = { + "gpio3", +}; + +static const char * const vac_groups[] = { + "vac", +}; + +static const char * const vacok_groups[] = { + "vac", +}; + +static const char * const powergood_groups[] = { + "powergood", +}; + +static const char * const usb_psel_groups[] = { + "gpio5", + "powergood", +}; + +static const char * const msecure_groups[] = { + "gpio7", +}; + +static const char * const pwrhold_groups[] = { + "gpio7", +}; + +static const char * const int_groups[] = { + "int", +}; + +static const char * const nreswarm_groups[] = { + "nreswarm", +}; + +static const char * const simrsto_groups[] = { + "gpio12", +}; + +static const char * const simrsti_groups[] = { + "gpio8", + "gpio15", +}; + +static const char * const low_vbat_groups[] = { + "gpio9", +}; + +static const char * const wireless_chrg1_groups[] = { + "gpio10", +}; + +static const char * const rcm_groups[] = { + "gpio11", +}; + +static const char * const pwrdown_groups[] = { + "pwrdown", +}; + +static const char * const gpadc_start_groups[] = { + "gpadc_start", +}; + +static const char * const reset_in_groups[] = { + "reset_in", +}; + +static const char * const nsleep_groups[] = { + "nsleep", +}; + +static const char * const enable_groups[] = { + "enable1", + "enable2", +}; + +#define FUNCTION_GROUPS \ + FUNCTION_GROUP(opt0, OPTION0), \ + FUNCTION_GROUP(opt1, OPTION1), \ + FUNCTION_GROUP(opt2, OPTION2), \ + FUNCTION_GROUP(opt3, OPTION3), \ + FUNCTION_GROUP(gpio, GPIO), \ + FUNCTION_GROUP(led, LED), \ + FUNCTION_GROUP(pwm, PWM), \ + FUNCTION_GROUP(regen, REGEN), \ + FUNCTION_GROUP(sysen, SYSEN), \ + FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO), \ + FUNCTION_GROUP(id, ID), \ + FUNCTION_GROUP(vbus_det, VBUS_DET), \ + FUNCTION_GROUP(chrg_det, CHRG_DET), \ + FUNCTION_GROUP(vac, VAC), \ + FUNCTION_GROUP(vacok, VACOK), \ + FUNCTION_GROUP(powergood, POWERGOOD), \ + FUNCTION_GROUP(usb_psel, USB_PSEL), \ + FUNCTION_GROUP(msecure, MSECURE), \ + FUNCTION_GROUP(pwrhold, PWRHOLD), \ + FUNCTION_GROUP(int, INT), \ + FUNCTION_GROUP(nreswarm, NRESWARM), \ + FUNCTION_GROUP(simrsto, SIMRSTO), \ + FUNCTION_GROUP(simrsti, SIMRSTI), \ + FUNCTION_GROUP(low_vbat, LOW_VBAT), \ + FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \ + FUNCTION_GROUP(rcm, RCM), \ + FUNCTION_GROUP(pwrdown, PWRDOWN), \ + FUNCTION_GROUP(gpadc_start, GPADC_START), \ + FUNCTION_GROUP(reset_in, RESET_IN), \ + FUNCTION_GROUP(nsleep, NSLEEP), \ + FUNCTION_GROUP(enable, ENABLE) + +static const struct palmas_pin_function palmas_pin_function[] = { +#undef FUNCTION_GROUP +#define FUNCTION_GROUP(fname, mux) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + + FUNCTION_GROUPS, +}; + +enum palmas_pinmux { +#undef FUNCTION_GROUP +#define FUNCTION_GROUP(fname, mux) PALMAS_PINMUX_##mux + FUNCTION_GROUPS, + PALMAS_PINMUX_NA = 0xFFFF, +}; + +struct palmas_pins_pullup_dn_info { + int pullup_dn_reg_base; + int pullup_dn_reg_add; + int pullup_dn_mask; + int normal_val; + int pull_up_val; + int pull_dn_val; +}; + +struct palmas_pins_od_info { + int od_reg_base; + int od_reg_add; + int od_mask; + int od_enable; + int od_disable; +}; + +struct palmas_pin_info { + enum palmas_pinmux mux_opt; + const struct palmas_pins_pullup_dn_info *pud_info; + const struct palmas_pins_od_info *od_info; +}; + +struct palmas_pingroup { + const char *name; + const unsigned pins[1]; + unsigned npins; + unsigned mux_reg_base; + unsigned mux_reg_add; + unsigned mux_reg_mask; + unsigned mux_bit_shift; + const struct palmas_pin_info *opt[4]; +}; + +#define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv) \ +static const struct palmas_pins_pullup_dn_info pud_##_name##_info = { \ + .pullup_dn_reg_base = PALMAS_##_rbase##_BASE, \ + .pullup_dn_reg_add = _add, \ + .pullup_dn_mask = _mask, \ + .normal_val = _nv, \ + .pull_up_val = _uv, \ + .pull_dn_val = _dv, \ +} + +PULL_UP_DN(nreswarm, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x2, 0x0, 0x2, -1); +PULL_UP_DN(pwrdown, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x4, 0x0, -1, 0x4); +PULL_UP_DN(gpadc_start, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(reset_in, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x40, 0x0, -1, 0x40); +PULL_UP_DN(nsleep, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x3, 0x0, 0x2, 0x1); +PULL_UP_DN(enable1, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0xC, 0x0, 0x8, 0x4); +PULL_UP_DN(enable2, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(vacok, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x40, 0x0, -1, 0x40); +PULL_UP_DN(chrg_det, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x10, 0x0, -1, 0x10); +PULL_UP_DN(pwrhold, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x4, 0x0, -1, 0x4); +PULL_UP_DN(msecure, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x1, 0x0, -1, 0x1); +PULL_UP_DN(id, USB_OTG, PALMAS_USB_ID_CTRL_SET, 0x40, 0x0, 0x40, -1); +PULL_UP_DN(gpio0, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x04, 0, -1, 1); +PULL_UP_DN(gpio1, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x0C, 0, 0x8, 0x4); +PULL_UP_DN(gpio2, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(gpio3, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x40, 0x0, -1, 0x40); +PULL_UP_DN(gpio4, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x03, 0x0, 0x2, 0x1); +PULL_UP_DN(gpio5, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x0c, 0x0, 0x8, 0x4); +PULL_UP_DN(gpio6, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(gpio7, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x40, 0x0, -1, 0x40); +PULL_UP_DN(gpio9, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x0C, 0x0, 0x8, 0x4); +PULL_UP_DN(gpio10, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(gpio11, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0xC0, 0x0, 0x80, 0x40); +PULL_UP_DN(gpio13, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x04, 0x0, -1, 0x04); +PULL_UP_DN(gpio14, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x30, 0x0, 0x20, 0x10); + +#define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv) \ +static const struct palmas_pins_od_info od_##_name##_info = { \ + .od_reg_base = PALMAS_##_rbase##_BASE, \ + .od_reg_add = _add, \ + .od_mask = _mask, \ + .od_enable = _ev, \ + .od_disable = _dv, \ +} + +OD_INFO(gpio1, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x1, 0x1, 0x0); +OD_INFO(gpio2, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x2, 0x2, 0x0); +OD_INFO(gpio5, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x20, 0x20, 0x0); +OD_INFO(gpio10, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x04, 0x04, 0x0); +OD_INFO(gpio13, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x20, 0x20, 0x0); +OD_INFO(int, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x8, 0x8, 0x0); +OD_INFO(pwm1, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x20, 0x20, 0x0); +OD_INFO(pwm2, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x80, 0x80, 0x0); +OD_INFO(vbus_det, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x40, 0x40, 0x0); + +#define PIN_INFO(_name, _id, _pud_info, _od_info) \ +static const struct palmas_pin_info pin_##_name##_info = { \ + .mux_opt = PALMAS_PINMUX_##_id, \ + .pud_info = _pud_info, \ + .od_info = _od_info \ +} + +PIN_INFO(gpio0, GPIO, &pud_gpio0_info, NULL); +PIN_INFO(gpio1, GPIO, &pud_gpio1_info, &od_gpio1_info); +PIN_INFO(gpio2, GPIO, &pud_gpio2_info, &od_gpio2_info); +PIN_INFO(gpio3, GPIO, &pud_gpio3_info, NULL); +PIN_INFO(gpio4, GPIO, &pud_gpio4_info, NULL); +PIN_INFO(gpio5, GPIO, &pud_gpio5_info, &od_gpio5_info); +PIN_INFO(gpio6, GPIO, &pud_gpio6_info, NULL); +PIN_INFO(gpio7, GPIO, &pud_gpio7_info, NULL); +PIN_INFO(gpio8, GPIO, NULL, NULL); +PIN_INFO(gpio9, GPIO, &pud_gpio9_info, NULL); +PIN_INFO(gpio10, GPIO, &pud_gpio10_info, &od_gpio10_info); +PIN_INFO(gpio11, GPIO, &pud_gpio11_info, NULL); +PIN_INFO(gpio12, GPIO, NULL, NULL); +PIN_INFO(gpio13, GPIO, &pud_gpio13_info, &od_gpio13_info); +PIN_INFO(gpio14, GPIO, &pud_gpio14_info, NULL); +PIN_INFO(gpio15, GPIO, NULL, NULL); +PIN_INFO(id, ID, &pud_id_info, NULL); +PIN_INFO(led1, LED, NULL, NULL); +PIN_INFO(led2, LED, NULL, NULL); +PIN_INFO(regen, REGEN, NULL, NULL); +PIN_INFO(sysen1, SYSEN, NULL, NULL); +PIN_INFO(sysen2, SYSEN, NULL, NULL); +PIN_INFO(int, INT, NULL, &od_int_info); +PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info); +PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info); +PIN_INFO(vacok, VACOK, &pud_vacok_info, NULL); +PIN_INFO(chrg_det, CHRG_DET, &pud_chrg_det_info, NULL); +PIN_INFO(pwrhold, PWRHOLD, &pud_pwrhold_info, NULL); +PIN_INFO(msecure, MSECURE, &pud_msecure_info, NULL); +PIN_INFO(nreswarm, NA, &pud_nreswarm_info, NULL); +PIN_INFO(pwrdown, NA, &pud_pwrdown_info, NULL); +PIN_INFO(gpadc_start, NA, &pud_gpadc_start_info, NULL); +PIN_INFO(reset_in, NA, &pud_reset_in_info, NULL); +PIN_INFO(nsleep, NA, &pud_nsleep_info, NULL); +PIN_INFO(enable1, NA, &pud_enable1_info, NULL); +PIN_INFO(enable2, NA, &pud_enable2_info, NULL); +PIN_INFO(clk32kgaudio, CLK32KGAUDIO, NULL, NULL); +PIN_INFO(usb_psel, USB_PSEL, NULL, NULL); +PIN_INFO(vac, VAC, NULL, NULL); +PIN_INFO(powergood, POWERGOOD, NULL, NULL); +PIN_INFO(vbus_det, VBUS_DET, NULL, &od_vbus_det_info); +PIN_INFO(sim1rsti, SIMRSTI, NULL, NULL); +PIN_INFO(low_vbat, LOW_VBAT, NULL, NULL); +PIN_INFO(rcm, RCM, NULL, NULL); +PIN_INFO(sim2rsto, SIMRSTO, NULL, NULL); +PIN_INFO(sim2rsti, SIMRSTI, NULL, NULL); +PIN_INFO(wireless_chrg1, WIRELESS_CHRG1, NULL, NULL); + +#define PALMAS_PRIMARY_SECONDARY_NONE 0 +#define PALMAS_NONE_BASE 0 +#define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3 + +#define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \ + { \ + .name = #pg_name, \ + .pins = {PALMAS_PIN_##pin_id}, \ + .npins = 1, \ + .mux_reg_base = PALMAS_##base##_BASE, \ + .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg, \ + .mux_reg_mask = _mask, \ + .mux_bit_shift = _bshift, \ + .opt = { \ + o0, \ + o1, \ + o2, \ + o3, \ + }, \ + } + +static const struct palmas_pingroup tps65913_pingroups[] = { + PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL), + PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info), + PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info), + PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL), + PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL), + PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL), + PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL), + PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL), + PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL), + PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL), + PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL), + PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL), + PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL), + PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL), + PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL), + PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL), + PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL), + PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL), +}; + +static const struct palmas_pingroup tps80036_pingroups[] = { + PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL), + PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info), + PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info), + PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL), + PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL), + PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL), + PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL), + PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL), + PALMAS_PINGROUP(gpio8, GPIO8_SIM1RSTI, PU_PD_OD, PAD4, 0x01, 0x0, &pin_gpio8_info, &pin_sim1rsti_info, NULL, NULL), + PALMAS_PINGROUP(gpio9, GPIO9_LOW_VBAT, PU_PD_OD, PAD4, 0x02, 0x1, &pin_gpio9_info, &pin_low_vbat_info, NULL, NULL), + PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1, PU_PD_OD, PAD4, 0x04, 0x2, &pin_gpio10_info, &pin_wireless_chrg1_info, NULL, NULL), + PALMAS_PINGROUP(gpio11, GPIO11_RCM, PU_PD_OD, PAD4, 0x08, 0x3, &pin_gpio11_info, &pin_rcm_info, NULL, NULL), + PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO, PU_PD_OD, PAD4, 0x10, 0x4, &pin_gpio12_info, &pin_sim2rsto_info, NULL, NULL), + PALMAS_PINGROUP(gpio13, GPIO13, NONE, NONE, 0x00, 0x0, &pin_gpio13_info, NULL, NULL, NULL), + PALMAS_PINGROUP(gpio14, GPIO14, NONE, NONE, 0x00, 0x0, &pin_gpio14_info, NULL, NULL, NULL), + PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI, PU_PD_OD, PAD4, 0x80, 0x7, &pin_gpio15_info, &pin_sim2rsti_info, NULL, NULL), + PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL), + PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL), + PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL), + PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL), + PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL), + PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL), + PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL), + PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL), + PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL), + PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL), +}; + +static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci) +{ + const struct palmas_pingroup *g; + unsigned int val; + int ret; + int i; + + for (i = 0; i < pci->num_pin_groups; ++i) { + g = &pci->pin_groups[i]; + if (g->mux_reg_base == PALMAS_NONE_BASE) { + pci->pins_current_opt[i] = 0; + continue; + } + ret = palmas_read(pci->palmas, g->mux_reg_base, + g->mux_reg_add, &val); + if (ret < 0) { + dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n", + g->mux_reg_add, ret); + return ret; + } + val &= g->mux_reg_mask; + pci->pins_current_opt[i] = val >> g->mux_bit_shift; + } + return 0; +} + +static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci, + bool enable) +{ + int ret; + int val; + + val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0; + ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE, + PALMAS_PRIMARY_SECONDARY_PAD3, + PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val); + if (ret < 0) + dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret); + return ret; +} + +static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci, + bool enable) +{ + int ret; + int val; + + val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0; + ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE, + PALMAS_PRIMARY_SECONDARY_PAD3, + PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val); + if (ret < 0) + dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret); + return ret; +} + +static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->num_pin_groups; +} + +static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->pin_groups[group].name; +} + +static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, unsigned *num_pins) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + *pins = pci->pin_groups[group].pins; + *num_pins = pci->pin_groups[group].npins; + return 0; +} + +static const struct pinctrl_ops palmas_pinctrl_ops = { + .get_groups_count = palmas_pinctrl_get_groups_count, + .get_group_name = palmas_pinctrl_get_group_name, + .get_group_pins = palmas_pinctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->num_functions; +} + +static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->functions[function].name; +} + +static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, const char * const **groups, + unsigned * const num_groups) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + *groups = pci->functions[function].groups; + *num_groups = pci->functions[function].ngroups; + return 0; +} + +static int palmas_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + const struct palmas_pingroup *g; + int i; + int ret; + + g = &pci->pin_groups[group]; + + /* If direct option is provided here */ + if (function <= PALMAS_PINMUX_OPTION3) { + if (!g->opt[function]) { + dev_err(pci->dev, "Pin %s does not support option %d\n", + g->name, function); + return -EINVAL; + } + i = function; + } else { + for (i = 0; i < ARRAY_SIZE(g->opt); i++) { + if (!g->opt[i]) + continue; + if (g->opt[i]->mux_opt == function) + break; + } + if (WARN_ON(i == ARRAY_SIZE(g->opt))) { + dev_err(pci->dev, "Pin %s does not support option %d\n", + g->name, function); + return -EINVAL; + } + } + + if (g->mux_reg_base == PALMAS_NONE_BASE) { + if (WARN_ON(i != 0)) + return -EINVAL; + return 0; + } + + dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n", + __func__, g->mux_reg_base, g->mux_reg_add, + g->mux_reg_mask, i << g->mux_bit_shift); + + ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add, + g->mux_reg_mask, i << g->mux_bit_shift); + if (ret < 0) { + dev_err(pci->dev, "Reg 0x%02x update failed: %d\n", + g->mux_reg_add, ret); + return ret; + } + pci->pins_current_opt[group] = i; + return 0; +} + +static const struct pinmux_ops palmas_pinmux_ops = { + .get_functions_count = palmas_pinctrl_get_funcs_count, + .get_function_name = palmas_pinctrl_get_func_name, + .get_function_groups = palmas_pinctrl_get_func_groups, + .enable = palmas_pinctrl_enable, +}; + +static int palmas_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *config) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + const struct palmas_pingroup *g; + const struct palmas_pin_info *opt; + unsigned int val; + int ret; + int base, add; + int rval; + int arg; + int group_nr; + + for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) { + if (pci->pin_groups[group_nr].pins[0] == pin) + break; + } + + if (group_nr == pci->num_pin_groups) { + dev_err(pci->dev, + "Pinconf is not supported for pin-id %d\n", pin); + return -ENOTSUPP; + } + + g = &pci->pin_groups[group_nr]; + opt = g->opt[pci->pins_current_opt[group_nr]]; + if (!opt) { + dev_err(pci->dev, + "Pinconf is not supported for pin %s\n", g->name); + return -ENOTSUPP; + } + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!opt->pud_info) { + dev_err(pci->dev, + "PULL control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->pud_info->pullup_dn_reg_base; + add = opt->pud_info->pullup_dn_reg_add; + ret = palmas_read(pci->palmas, base, add, &val); + if (ret < 0) { + dev_err(pci->dev, "Reg 0x%02x read failed: %d\n", + add, ret); + return ret; + } + + rval = val & opt->pud_info->pullup_dn_mask; + arg = 0; + if ((opt->pud_info->normal_val >= 0) && + (opt->pud_info->normal_val == rval) && + (param == PIN_CONFIG_BIAS_DISABLE)) + arg = 1; + else if ((opt->pud_info->pull_up_val >= 0) && + (opt->pud_info->pull_up_val == rval) && + (param == PIN_CONFIG_BIAS_PULL_UP)) + arg = 1; + else if ((opt->pud_info->pull_dn_val >= 0) && + (opt->pud_info->pull_dn_val == rval) && + (param == PIN_CONFIG_BIAS_PULL_DOWN)) + arg = 1; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!opt->od_info) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->od_info->od_reg_base; + add = opt->od_info->od_reg_add; + ret = palmas_read(pci->palmas, base, add, &val); + if (ret < 0) { + dev_err(pci->dev, "Reg 0x%02x read failed: %d\n", + add, ret); + return ret; + } + rval = val & opt->od_info->od_mask; + arg = -1; + if ((opt->od_info->od_disable >= 0) && + (opt->od_info->od_disable == rval)) + arg = 0; + else if ((opt->od_info->od_enable >= 0) && + (opt->od_info->od_enable == rval)) + arg = 1; + if (arg < 0) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + break; + + default: + dev_err(pci->dev, "Properties not supported\n"); + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, (u16)arg); + return 0; +} + +static int palmas_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *configs, + unsigned num_configs) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + u16 param_val; + const struct palmas_pingroup *g; + const struct palmas_pin_info *opt; + int ret; + int base, add, mask; + int rval; + int group_nr; + int i; + + for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) { + if (pci->pin_groups[group_nr].pins[0] == pin) + break; + } + + if (group_nr == pci->num_pin_groups) { + dev_err(pci->dev, + "Pinconf is not supported for pin-id %d\n", pin); + return -ENOTSUPP; + } + + g = &pci->pin_groups[group_nr]; + opt = g->opt[pci->pins_current_opt[group_nr]]; + if (!opt) { + dev_err(pci->dev, + "Pinconf is not supported for pin %s\n", g->name); + return -ENOTSUPP; + } + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + param_val = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!opt->pud_info) { + dev_err(pci->dev, + "PULL control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->pud_info->pullup_dn_reg_base; + add = opt->pud_info->pullup_dn_reg_add; + mask = opt->pud_info->pullup_dn_mask; + + if (param == PIN_CONFIG_BIAS_DISABLE) + rval = opt->pud_info->normal_val; + else if (param == PIN_CONFIG_BIAS_PULL_UP) + rval = opt->pud_info->pull_up_val; + else + rval = opt->pud_info->pull_dn_val; + + if (rval < 0) { + dev_err(pci->dev, + "PULL control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!opt->od_info) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->od_info->od_reg_base; + add = opt->od_info->od_reg_add; + mask = opt->od_info->od_mask; + if (param_val == 0) + rval = opt->od_info->od_disable; + else + rval = opt->od_info->od_enable; + if (rval < 0) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + break; + default: + dev_err(pci->dev, "Properties not supported\n"); + return -ENOTSUPP; + } + + dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n", + __func__, base, add, mask, rval); + ret = palmas_update_bits(pci->palmas, base, add, mask, rval); + if (ret < 0) { + dev_err(pci->dev, "Reg 0x%02x update failed: %d\n", + add, ret); + return ret; + } + } /* for each config */ + + return 0; +} + +static const struct pinconf_ops palmas_pinconf_ops = { + .pin_config_get = palmas_pinconf_get, + .pin_config_set = palmas_pinconf_set, +}; + +static struct pinctrl_desc palmas_pinctrl_desc = { + .pctlops = &palmas_pinctrl_ops, + .pmxops = &palmas_pinmux_ops, + .confops = &palmas_pinconf_ops, + .owner = THIS_MODULE, +}; + +struct palmas_pinctrl_data { + const struct palmas_pingroup *pin_groups; + int num_pin_groups; +}; + +static struct palmas_pinctrl_data tps65913_pinctrl_data = { + .pin_groups = tps65913_pingroups, + .num_pin_groups = ARRAY_SIZE(tps65913_pingroups), +}; + +static struct palmas_pinctrl_data tps80036_pinctrl_data = { + .pin_groups = tps80036_pingroups, + .num_pin_groups = ARRAY_SIZE(tps80036_pingroups), +}; + +static struct of_device_id palmas_pinctrl_of_match[] = { + { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data}, + { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data}, + { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data}, + { }, +}; +MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match); + +static int palmas_pinctrl_probe(struct platform_device *pdev) +{ + struct palmas_pctrl_chip_info *pci; + const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data; + int ret; + bool enable_dvfs1 = false; + bool enable_dvfs2 = false; + + if (pdev->dev.of_node) { + const struct of_device_id *match; + match = of_match_device(palmas_pinctrl_of_match, &pdev->dev); + pinctrl_data = match->data; + enable_dvfs1 = of_property_read_bool(pdev->dev.of_node, + "ti,palmas-enable-dvfs1"); + enable_dvfs2 = of_property_read_bool(pdev->dev.of_node, + "ti,palmas-enable-dvfs2"); + } + + pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL); + if (!pci) { + dev_err(&pdev->dev, "Malloc for pci failed\n"); + return -ENOMEM; + } + + pci->dev = &pdev->dev; + pci->palmas = dev_get_drvdata(pdev->dev.parent); + + pci->pins = palmas_pins_desc; + pci->num_pins = ARRAY_SIZE(palmas_pins_desc); + pci->functions = palmas_pin_function; + pci->num_functions = ARRAY_SIZE(palmas_pin_function); + pci->pin_groups = pinctrl_data->pin_groups; + pci->num_pin_groups = pinctrl_data->num_pin_groups; + + platform_set_drvdata(pdev, pci); + + palmas_pinctrl_set_dvfs1(pci, enable_dvfs1); + palmas_pinctrl_set_dvfs2(pci, enable_dvfs2); + ret = palmas_pinctrl_get_pin_mux(pci); + if (ret < 0) { + dev_err(&pdev->dev, + "Reading pinctrol option register failed: %d\n", ret); + return ret; + } + + palmas_pinctrl_desc.name = dev_name(&pdev->dev); + palmas_pinctrl_desc.pins = palmas_pins_desc; + palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc); + pci->pctl = pinctrl_register(&palmas_pinctrl_desc, &pdev->dev, pci); + if (!pci->pctl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + return 0; +} + +static int palmas_pinctrl_remove(struct platform_device *pdev) +{ + struct palmas_pctrl_chip_info *pci = platform_get_drvdata(pdev); + + pinctrl_unregister(pci->pctl); + return 0; +} + +static struct platform_driver palmas_pinctrl_driver = { + .driver = { + .name = "palmas-pinctrl", + .owner = THIS_MODULE, + .of_match_table = palmas_pinctrl_of_match, + }, + .probe = palmas_pinctrl_probe, + .remove = palmas_pinctrl_remove, +}; + +module_platform_driver(palmas_pinctrl_driver); + +MODULE_DESCRIPTION("Palmas pin control driver"); +MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>"); +MODULE_ALIAS("platform:palmas-pinctrl"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c new file mode 100644 index 00000000000..bb805d5e9ff --- /dev/null +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -0,0 +1,1730 @@ +/* + * Pinctrl driver for Rockchip SoCs + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * With some ideas taken from pinctrl-samsung: + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * + * and pinctrl-at91: + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/bitops.h> +#include <linux/gpio.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/clk.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "core.h" +#include "pinconf.h" + +/* GPIO control registers */ +#define GPIO_SWPORT_DR 0x00 +#define GPIO_SWPORT_DDR 0x04 +#define GPIO_INTEN 0x30 +#define GPIO_INTMASK 0x34 +#define GPIO_INTTYPE_LEVEL 0x38 +#define GPIO_INT_POLARITY 0x3c +#define GPIO_INT_STATUS 0x40 +#define GPIO_INT_RAWSTATUS 0x44 +#define GPIO_DEBOUNCE 0x48 +#define GPIO_PORTS_EOI 0x4c +#define GPIO_EXT_PORT 0x50 +#define GPIO_LS_SYNC 0x60 + +enum rockchip_pinctrl_type { + RK2928, + RK3066B, + RK3188, +}; + +enum rockchip_pin_bank_type { + COMMON_BANK, + RK3188_BANK0, +}; + +/** + * @reg_base: register base of the gpio bank + * @reg_pull: optional separate register for additional pull settings + * @clk: clock of the gpio bank + * @irq: interrupt of the gpio bank + * @pin_base: first pin number + * @nr_pins: number of pins in this bank + * @name: name of the bank + * @bank_num: number of the bank, to account for holes + * @valid: are all necessary informations present + * @of_node: dt node of this bank + * @drvdata: common pinctrl basedata + * @domain: irqdomain of the gpio bank + * @gpio_chip: gpiolib chip + * @grange: gpio range + * @slock: spinlock for the gpio bank + */ +struct rockchip_pin_bank { + void __iomem *reg_base; + struct regmap *regmap_pull; + struct clk *clk; + int irq; + u32 pin_base; + u8 nr_pins; + char *name; + u8 bank_num; + enum rockchip_pin_bank_type bank_type; + bool valid; + struct device_node *of_node; + struct rockchip_pinctrl *drvdata; + struct irq_domain *domain; + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range grange; + spinlock_t slock; + u32 toggle_edge_mode; +}; + +#define PIN_BANK(id, pins, label) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + } + +/** + */ +struct rockchip_pin_ctrl { + struct rockchip_pin_bank *pin_banks; + u32 nr_banks; + u32 nr_pins; + char *label; + enum rockchip_pinctrl_type type; + int mux_offset; + void (*pull_calc_reg)(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit); +}; + +struct rockchip_pin_config { + unsigned int func; + unsigned long *configs; + unsigned int nconfigs; +}; + +/** + * struct rockchip_pin_group: represent group of pins of a pinmux function. + * @name: name of the pin group, used to lookup the group. + * @pins: the pins included in this group. + * @npins: number of pins included in this group. + * @func: the mux function number to be programmed when selected. + * @configs: the config values to be set for each pin + * @nconfigs: number of configs for each pin + */ +struct rockchip_pin_group { + const char *name; + unsigned int npins; + unsigned int *pins; + struct rockchip_pin_config *data; +}; + +/** + * struct rockchip_pmx_func: represent a pin function. + * @name: name of the pin function, used to lookup the function. + * @groups: one or more names of pin groups that provide this function. + * @num_groups: number of groups included in @groups. + */ +struct rockchip_pmx_func { + const char *name; + const char **groups; + u8 ngroups; +}; + +struct rockchip_pinctrl { + struct regmap *regmap_base; + int reg_size; + struct regmap *regmap_pull; + struct regmap *regmap_pmu; + struct device *dev; + struct rockchip_pin_ctrl *ctrl; + struct pinctrl_desc pctl; + struct pinctrl_dev *pctl_dev; + struct rockchip_pin_group *groups; + unsigned int ngroups; + struct rockchip_pmx_func *functions; + unsigned int nfunctions; +}; + +static struct regmap_config rockchip_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) +{ + return container_of(gc, struct rockchip_pin_bank, gpio_chip); +} + +static const inline struct rockchip_pin_group *pinctrl_name_to_group( + const struct rockchip_pinctrl *info, + const char *name) +{ + int i; + + for (i = 0; i < info->ngroups; i++) { + if (!strcmp(info->groups[i].name, name)) + return &info->groups[i]; + } + + return NULL; +} + +/* + * given a pin number that is local to a pin controller, find out the pin bank + * and the register base of the pin bank. + */ +static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, + unsigned pin) +{ + struct rockchip_pin_bank *b = info->ctrl->pin_banks; + + while (pin >= (b->pin_base + b->nr_pins)) + b++; + + return b; +} + +static struct rockchip_pin_bank *bank_num_to_bank( + struct rockchip_pinctrl *info, + unsigned num) +{ + struct rockchip_pin_bank *b = info->ctrl->pin_banks; + int i; + + for (i = 0; i < info->ctrl->nr_banks; i++, b++) { + if (b->bank_num == num) + return b; + } + + return ERR_PTR(-EINVAL); +} + +/* + * Pinctrl_ops handling + */ + +static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->ngroups; +} + +static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->groups[selector].name; +} + +static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, const unsigned **pins, + unsigned *npins) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pins; + *npins = info->groups[selector].npins; + + return 0; +} + +static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const struct rockchip_pin_group *grp; + struct pinctrl_map *new_map; + struct device_node *parent; + int map_num = 1; + int i; + + /* + * first find the group of this node and check if we need to create + * config maps for pins + */ + grp = pinctrl_name_to_group(info, np->name); + if (!grp) { + dev_err(info->dev, "unable to find group for node %s\n", + np->name); + return -EINVAL; + } + + map_num += grp->npins; + new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, + GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + *map = new_map; + *num_maps = map_num; + + /* create mux map */ + parent = of_get_parent(np); + if (!parent) { + devm_kfree(pctldev->dev, new_map); + return -EINVAL; + } + new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; + new_map[0].data.mux.function = parent->name; + new_map[0].data.mux.group = np->name; + of_node_put(parent); + + /* create config map */ + new_map++; + for (i = 0; i < grp->npins; i++) { + new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[i].data.configs.group_or_pin = + pin_get_name(pctldev, grp->pins[i]); + new_map[i].data.configs.configs = grp->data[i].configs; + new_map[i].data.configs.num_configs = grp->data[i].nconfigs; + } + + dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", + (*map)->data.mux.function, (*map)->data.mux.group, map_num); + + return 0; +} + +static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ +} + +static const struct pinctrl_ops rockchip_pctrl_ops = { + .get_groups_count = rockchip_get_groups_count, + .get_group_name = rockchip_get_group_name, + .get_group_pins = rockchip_get_group_pins, + .dt_node_to_map = rockchip_dt_node_to_map, + .dt_free_map = rockchip_dt_free_map, +}; + +/* + * Hardware access + */ + +static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) +{ + struct rockchip_pinctrl *info = bank->drvdata; + unsigned int val; + int reg, ret; + u8 bit; + + if (bank->bank_type == RK3188_BANK0 && pin < 16) + return RK_FUNC_GPIO; + + /* get basic quadrupel of mux registers and the correct reg inside */ + reg = info->ctrl->mux_offset; + reg += bank->bank_num * 0x10; + reg += (pin / 8) * 4; + bit = (pin % 8) * 2; + + ret = regmap_read(info->regmap_base, reg, &val); + if (ret) + return ret; + + return ((val >> bit) & 3); +} + +/* + * Set a new mux function for a pin. + * + * The register is divided into the upper and lower 16 bit. When changing + * a value, the previous register value is not read and changed. Instead + * it seems the changed bits are marked in the upper 16 bit, while the + * changed value gets set in the same offset in the lower 16 bit. + * All pin settings seem to be 2 bit wide in both the upper and lower + * parts. + * @bank: pin bank to change + * @pin: pin to change + * @mux: new mux function to set + */ +static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int reg, ret; + unsigned long flags; + u8 bit; + u32 data; + + /* + * The first 16 pins of rk3188_bank0 are always gpios and do not have + * a mux register at all. + */ + if (bank->bank_type == RK3188_BANK0 && pin < 16) { + if (mux != RK_FUNC_GPIO) { + dev_err(info->dev, + "pin %d only supports a gpio mux\n", pin); + return -ENOTSUPP; + } else { + return 0; + } + } + + dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", + bank->bank_num, pin, mux); + + /* get basic quadrupel of mux registers and the correct reg inside */ + reg = info->ctrl->mux_offset; + reg += bank->bank_num * 0x10; + reg += (pin / 8) * 4; + bit = (pin % 8) * 2; + + spin_lock_irqsave(&bank->slock, flags); + + data = (3 << (bit + 16)); + data |= (mux & 3) << bit; + ret = regmap_write(info->regmap_base, reg, data); + + spin_unlock_irqrestore(&bank->slock, flags); + + return ret; +} + +#define RK2928_PULL_OFFSET 0x118 +#define RK2928_PULL_PINS_PER_REG 16 +#define RK2928_PULL_BANK_STRIDE 8 + +static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK2928_PULL_OFFSET; + *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; + *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; + + *bit = pin_num % RK2928_PULL_PINS_PER_REG; +}; + +#define RK3188_PULL_OFFSET 0x164 +#define RK3188_PULL_BITS_PER_PIN 2 +#define RK3188_PULL_PINS_PER_REG 8 +#define RK3188_PULL_BANK_STRIDE 16 +#define RK3188_PULL_PMU_OFFSET 0x64 + +static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 12 pins of the first bank are located elsewhere */ + if (bank->bank_type == RK3188_BANK0 && pin_num < 12) { + *regmap = info->regmap_pmu ? info->regmap_pmu + : bank->regmap_pull; + *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3188_PULL_PINS_PER_REG; + *bit *= RK3188_PULL_BITS_PER_PIN; + } else { + *regmap = info->regmap_pull ? info->regmap_pull + : info->regmap_base; + *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; + + /* correct the offset, as it is the 2nd pull register */ + *reg -= 4; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + /* + * The bits in these registers have an inverse ordering + * with the lowest pin being in bits 15:14 and the highest + * pin in bits 1:0 + */ + *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; + } +} + +static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) +{ + struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct regmap *regmap; + int reg, ret; + u8 bit; + u32 data; + + /* rk3066b does support any pulls */ + if (ctrl->type == RK3066B) + return PIN_CONFIG_BIAS_DISABLE; + + ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); + + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + + switch (ctrl->type) { + case RK2928: + return !(data & BIT(bit)) + ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT + : PIN_CONFIG_BIAS_DISABLE; + case RK3188: + data >>= bit; + data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; + + switch (data) { + case 0: + return PIN_CONFIG_BIAS_DISABLE; + case 1: + return PIN_CONFIG_BIAS_PULL_UP; + case 2: + return PIN_CONFIG_BIAS_PULL_DOWN; + case 3: + return PIN_CONFIG_BIAS_BUS_HOLD; + } + + dev_err(info->dev, "unknown pull setting\n"); + return -EIO; + default: + dev_err(info->dev, "unsupported pinctrl type\n"); + return -EINVAL; + }; +} + +static int rockchip_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct regmap *regmap; + int reg, ret; + unsigned long flags; + u8 bit; + u32 data; + + dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", + bank->bank_num, pin_num, pull); + + /* rk3066b does support any pulls */ + if (ctrl->type == RK3066B) + return pull ? -EINVAL : 0; + + ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); + + switch (ctrl->type) { + case RK2928: + spin_lock_irqsave(&bank->slock, flags); + + data = BIT(bit + 16); + if (pull == PIN_CONFIG_BIAS_DISABLE) + data |= BIT(bit); + ret = regmap_write(regmap, reg, data); + + spin_unlock_irqrestore(&bank->slock, flags); + break; + case RK3188: + spin_lock_irqsave(&bank->slock, flags); + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); + + switch (pull) { + case PIN_CONFIG_BIAS_DISABLE: + break; + case PIN_CONFIG_BIAS_PULL_UP: + data |= (1 << bit); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + data |= (2 << bit); + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + data |= (3 << bit); + break; + default: + spin_unlock_irqrestore(&bank->slock, flags); + dev_err(info->dev, "unsupported pull setting %d\n", + pull); + return -EINVAL; + } + + ret = regmap_write(regmap, reg, data); + + spin_unlock_irqrestore(&bank->slock, flags); + break; + default: + dev_err(info->dev, "unsupported pinctrl type\n"); + return -EINVAL; + } + + return ret; +} + +/* + * Pinmux_ops handling + */ + +static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->nfunctions; +} + +static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->functions[selector].name; +} + +static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, const char * const **groups, + unsigned * const num_groups) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + *groups = info->functions[selector].groups; + *num_groups = info->functions[selector].ngroups; + + return 0; +} + +static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins = info->groups[group].pins; + const struct rockchip_pin_config *data = info->groups[group].data; + struct rockchip_pin_bank *bank; + int cnt, ret = 0; + + dev_dbg(info->dev, "enable function %s group %s\n", + info->functions[selector].name, info->groups[group].name); + + /* + * for each pin in the pin group selected, program the correspoding pin + * pin function number in the config register. + */ + for (cnt = 0; cnt < info->groups[group].npins; cnt++) { + bank = pin_to_bank(info, pins[cnt]); + ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, + data[cnt].func); + if (ret) + break; + } + + if (ret) { + /* revert the already done pin settings */ + for (cnt--; cnt >= 0; cnt--) + rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); + + return ret; + } + + return 0; +} + +static void rockchip_pmx_disable(struct pinctrl_dev *pctldev, + unsigned selector, unsigned group) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins = info->groups[group].pins; + struct rockchip_pin_bank *bank; + int cnt; + + dev_dbg(info->dev, "disable function %s group %s\n", + info->functions[selector].name, info->groups[group].name); + + for (cnt = 0; cnt < info->groups[group].npins; cnt++) { + bank = pin_to_bank(info, pins[cnt]); + rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); + } +} + +/* + * The calls to gpio_direction_output() and gpio_direction_input() + * leads to this function call (via the pinctrl_gpio_direction_{input|output}() + * function called from the gpiolib interface). + */ +static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, bool input) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct rockchip_pin_bank *bank; + struct gpio_chip *chip; + int pin, ret; + u32 data; + + chip = range->gc; + bank = gc_to_pin_bank(chip); + pin = offset - chip->base; + + dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", + offset, range->name, pin, input ? "input" : "output"); + + ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); + if (ret < 0) + return ret; + + data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); + /* set bit to 1 for output, 0 for input */ + if (!input) + data |= BIT(pin); + else + data &= ~BIT(pin); + writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); + + return 0; +} + +static const struct pinmux_ops rockchip_pmx_ops = { + .get_functions_count = rockchip_pmx_get_funcs_count, + .get_function_name = rockchip_pmx_get_func_name, + .get_function_groups = rockchip_pmx_get_groups, + .enable = rockchip_pmx_enable, + .disable = rockchip_pmx_disable, + .gpio_set_direction = rockchip_pmx_gpio_set_direction, +}; + +/* + * Pinconf_ops handling + */ + +static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, + enum pin_config_param pull) +{ + switch (ctrl->type) { + case RK2928: + return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || + pull == PIN_CONFIG_BIAS_DISABLE); + case RK3066B: + return pull ? false : true; + case RK3188: + return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); + } + + return false; +} + +static int rockchip_gpio_direction_output(struct gpio_chip *gc, + unsigned offset, int value); +static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); + +/* set the pin config settings for a specified pin */ +static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct rockchip_pin_bank *bank = pin_to_bank(info, pin); + enum pin_config_param param; + u16 arg; + int i; + int rc; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + rc = rockchip_set_pull(bank, pin - bank->pin_base, + param); + if (rc) + return rc; + break; + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + case PIN_CONFIG_BIAS_BUS_HOLD: + if (!rockchip_pinconf_pull_valid(info->ctrl, param)) + return -ENOTSUPP; + + if (!arg) + return -EINVAL; + + rc = rockchip_set_pull(bank, pin - bank->pin_base, + param); + if (rc) + return rc; + break; + case PIN_CONFIG_OUTPUT: + rc = rockchip_gpio_direction_output(&bank->gpio_chip, + pin - bank->pin_base, + arg); + if (rc) + return rc; + break; + default: + return -ENOTSUPP; + break; + } + } /* for each config */ + + return 0; +} + +/* get the pin config settings for a specified pin */ +static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct rockchip_pin_bank *bank = pin_to_bank(info, pin); + enum pin_config_param param = pinconf_to_config_param(*config); + u16 arg; + int rc; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (rockchip_get_pull(bank, pin - bank->pin_base) != param) + return -EINVAL; + + arg = 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + case PIN_CONFIG_BIAS_BUS_HOLD: + if (!rockchip_pinconf_pull_valid(info->ctrl, param)) + return -ENOTSUPP; + + if (rockchip_get_pull(bank, pin - bank->pin_base) != param) + return -EINVAL; + + arg = 1; + break; + case PIN_CONFIG_OUTPUT: + rc = rockchip_get_mux(bank, pin - bank->pin_base); + if (rc != RK_FUNC_GPIO) + return -EINVAL; + + rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); + if (rc < 0) + return rc; + + arg = rc ? 1 : 0; + break; + default: + return -ENOTSUPP; + break; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static const struct pinconf_ops rockchip_pinconf_ops = { + .pin_config_get = rockchip_pinconf_get, + .pin_config_set = rockchip_pinconf_set, +}; + +static const struct of_device_id rockchip_bank_match[] = { + { .compatible = "rockchip,gpio-bank" }, + { .compatible = "rockchip,rk3188-gpio-bank0" }, + {}, +}; + +static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, + struct device_node *np) +{ + struct device_node *child; + + for_each_child_of_node(np, child) { + if (of_match_node(rockchip_bank_match, child)) + continue; + + info->nfunctions++; + info->ngroups += of_get_child_count(child); + } +} + +static int rockchip_pinctrl_parse_groups(struct device_node *np, + struct rockchip_pin_group *grp, + struct rockchip_pinctrl *info, + u32 index) +{ + struct rockchip_pin_bank *bank; + int size; + const __be32 *list; + int num; + int i, j; + int ret; + + dev_dbg(info->dev, "group(%d): %s\n", index, np->name); + + /* Initialise group */ + grp->name = np->name; + + /* + * the binding format is rockchip,pins = <bank pin mux CONFIG>, + * do sanity check and calculate pins number + */ + list = of_get_property(np, "rockchip,pins", &size); + /* we do not check return since it's safe node passed down */ + size /= sizeof(*list); + if (!size || size % 4) { + dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); + return -EINVAL; + } + + grp->npins = size / 4; + + grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), + GFP_KERNEL); + grp->data = devm_kzalloc(info->dev, grp->npins * + sizeof(struct rockchip_pin_config), + GFP_KERNEL); + if (!grp->pins || !grp->data) + return -ENOMEM; + + for (i = 0, j = 0; i < size; i += 4, j++) { + const __be32 *phandle; + struct device_node *np_config; + + num = be32_to_cpu(*list++); + bank = bank_num_to_bank(info, num); + if (IS_ERR(bank)) + return PTR_ERR(bank); + + grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); + grp->data[j].func = be32_to_cpu(*list++); + + phandle = list++; + if (!phandle) + return -EINVAL; + + np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); + ret = pinconf_generic_parse_dt_config(np_config, + &grp->data[j].configs, &grp->data[j].nconfigs); + if (ret) + return ret; + } + + return 0; +} + +static int rockchip_pinctrl_parse_functions(struct device_node *np, + struct rockchip_pinctrl *info, + u32 index) +{ + struct device_node *child; + struct rockchip_pmx_func *func; + struct rockchip_pin_group *grp; + int ret; + static u32 grp_index; + u32 i = 0; + + dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); + + func = &info->functions[index]; + + /* Initialise function */ + func->name = np->name; + func->ngroups = of_get_child_count(np); + if (func->ngroups <= 0) + return 0; + + func->groups = devm_kzalloc(info->dev, + func->ngroups * sizeof(char *), GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + for_each_child_of_node(np, child) { + func->groups[i] = child->name; + grp = &info->groups[grp_index++]; + ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); + if (ret) + return ret; + } + + return 0; +} + +static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *child; + int ret; + int i; + + rockchip_pinctrl_child_count(info, np); + + dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); + dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); + + info->functions = devm_kzalloc(dev, info->nfunctions * + sizeof(struct rockchip_pmx_func), + GFP_KERNEL); + if (!info->functions) { + dev_err(dev, "failed to allocate memory for function list\n"); + return -EINVAL; + } + + info->groups = devm_kzalloc(dev, info->ngroups * + sizeof(struct rockchip_pin_group), + GFP_KERNEL); + if (!info->groups) { + dev_err(dev, "failed allocate memory for ping group list\n"); + return -EINVAL; + } + + i = 0; + + for_each_child_of_node(np, child) { + if (of_match_node(rockchip_bank_match, child)) + continue; + + ret = rockchip_pinctrl_parse_functions(child, info, i++); + if (ret) { + dev_err(&pdev->dev, "failed to parse function\n"); + return ret; + } + } + + return 0; +} + +static int rockchip_pinctrl_register(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct pinctrl_desc *ctrldesc = &info->pctl; + struct pinctrl_pin_desc *pindesc, *pdesc; + struct rockchip_pin_bank *pin_bank; + int pin, bank, ret; + int k; + + ctrldesc->name = "rockchip-pinctrl"; + ctrldesc->owner = THIS_MODULE; + ctrldesc->pctlops = &rockchip_pctrl_ops; + ctrldesc->pmxops = &rockchip_pmx_ops; + ctrldesc->confops = &rockchip_pinconf_ops; + + pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * + info->ctrl->nr_pins, GFP_KERNEL); + if (!pindesc) { + dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); + return -ENOMEM; + } + ctrldesc->pins = pindesc; + ctrldesc->npins = info->ctrl->nr_pins; + + pdesc = pindesc; + for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { + pin_bank = &info->ctrl->pin_banks[bank]; + for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { + pdesc->number = k; + pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", + pin_bank->name, pin); + pdesc++; + } + } + + info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); + if (!info->pctl_dev) { + dev_err(&pdev->dev, "could not register pinctrl driver\n"); + return -EINVAL; + } + + for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { + pin_bank = &info->ctrl->pin_banks[bank]; + pin_bank->grange.name = pin_bank->name; + pin_bank->grange.id = bank; + pin_bank->grange.pin_base = pin_bank->pin_base; + pin_bank->grange.base = pin_bank->gpio_chip.base; + pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; + pin_bank->grange.gc = &pin_bank->gpio_chip; + pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); + } + + ret = rockchip_pinctrl_parse_dt(pdev, info); + if (ret) { + pinctrl_unregister(info->pctl_dev); + return ret; + } + + return 0; +} + +/* + * GPIO handling + */ + +static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) +{ + struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); + void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; + unsigned long flags; + u32 data; + + spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg); + data &= ~BIT(offset); + if (value) + data |= BIT(offset); + writel(data, reg); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +/* + * Returns the level of the pin for input direction and setting of the DR + * register for output gpios. + */ +static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) +{ + struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); + u32 data; + + data = readl(bank->reg_base + GPIO_EXT_PORT); + data >>= offset; + data &= 1; + return data; +} + +/* + * gpiolib gpio_direction_input callback function. The setting of the pin + * mux function as 'gpio input' will be handled by the pinctrl susbsystem + * interface. + */ +static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) +{ + return pinctrl_gpio_direction_input(gc->base + offset); +} + +/* + * gpiolib gpio_direction_output callback function. The setting of the pin + * mux function as 'gpio output' will be handled by the pinctrl susbsystem + * interface. + */ +static int rockchip_gpio_direction_output(struct gpio_chip *gc, + unsigned offset, int value) +{ + rockchip_gpio_set(gc, offset, value); + return pinctrl_gpio_direction_output(gc->base + offset); +} + +/* + * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin + * and a virtual IRQ, if not already present. + */ +static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +{ + struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); + unsigned int virq; + + if (!bank->domain) + return -ENXIO; + + virq = irq_create_mapping(bank->domain, offset); + + return (virq) ? : -ENXIO; +} + +static const struct gpio_chip rockchip_gpiolib_chip = { + .request = rockchip_gpio_request, + .free = rockchip_gpio_free, + .set = rockchip_gpio_set, + .get = rockchip_gpio_get, + .direction_input = rockchip_gpio_direction_input, + .direction_output = rockchip_gpio_direction_output, + .to_irq = rockchip_gpio_to_irq, + .owner = THIS_MODULE, +}; + +/* + * Interrupt handling + */ + +static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct rockchip_pin_bank *bank = irq_get_handler_data(irq); + u32 polarity = 0, data = 0; + u32 pend; + bool edge_changed = false; + + dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); + + chained_irq_enter(chip, desc); + + pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); + + if (bank->toggle_edge_mode) { + polarity = readl_relaxed(bank->reg_base + + GPIO_INT_POLARITY); + data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); + } + + while (pend) { + unsigned int virq; + + irq = __ffs(pend); + pend &= ~BIT(irq); + virq = irq_linear_revmap(bank->domain, irq); + + if (!virq) { + dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); + continue; + } + + dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); + + /* + * Triggering IRQ on both rising and falling edge + * needs manual intervention. + */ + if (bank->toggle_edge_mode & BIT(irq)) { + if (data & BIT(irq)) + polarity &= ~BIT(irq); + else + polarity |= BIT(irq); + + edge_changed = true; + } + + generic_handle_irq(virq); + } + + if (bank->toggle_edge_mode && edge_changed) { + /* Interrupt params should only be set with ints disabled */ + data = readl_relaxed(bank->reg_base + GPIO_INTEN); + writel_relaxed(0, bank->reg_base + GPIO_INTEN); + writel(polarity, bank->reg_base + GPIO_INT_POLARITY); + writel(data, bank->reg_base + GPIO_INTEN); + } + + chained_irq_exit(chip, desc); +} + +static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + u32 mask = BIT(d->hwirq); + u32 polarity; + u32 level; + u32 data; + int ret; + + /* make sure the pin is configured as gpio input */ + ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); + if (ret < 0) + return ret; + + data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); + data &= ~mask; + writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); + + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(d->irq, handle_edge_irq); + else + __irq_set_handler_locked(d->irq, handle_level_irq); + + irq_gc_lock(gc); + + level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); + polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); + + switch (type) { + case IRQ_TYPE_EDGE_BOTH: + bank->toggle_edge_mode |= mask; + level |= mask; + + /* + * Determine gpio state. If 1 next interrupt should be falling + * otherwise rising. + */ + data = readl(bank->reg_base + GPIO_EXT_PORT); + if (data & mask) + polarity &= ~mask; + else + polarity |= mask; + break; + case IRQ_TYPE_EDGE_RISING: + bank->toggle_edge_mode &= ~mask; + level |= mask; + polarity |= mask; + break; + case IRQ_TYPE_EDGE_FALLING: + bank->toggle_edge_mode &= ~mask; + level |= mask; + polarity &= ~mask; + break; + case IRQ_TYPE_LEVEL_HIGH: + bank->toggle_edge_mode &= ~mask; + level &= ~mask; + polarity |= mask; + break; + case IRQ_TYPE_LEVEL_LOW: + bank->toggle_edge_mode &= ~mask; + level &= ~mask; + polarity &= ~mask; + break; + default: + irq_gc_unlock(gc); + return -EINVAL; + } + + writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); + writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); + + irq_gc_unlock(gc); + + return 0; +} + +static int rockchip_interrupts_register(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + struct irq_chip_generic *gc; + int ret; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + if (!bank->valid) { + dev_warn(&pdev->dev, "bank %s is not valid\n", + bank->name); + continue; + } + + bank->domain = irq_domain_add_linear(bank->of_node, 32, + &irq_generic_chip_ops, NULL); + if (!bank->domain) { + dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", + bank->name); + continue; + } + + ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, + "rockchip_gpio_irq", handle_level_irq, + clr, 0, IRQ_GC_INIT_MASK_CACHE); + if (ret) { + dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", + bank->name); + irq_domain_remove(bank->domain); + continue; + } + + gc = irq_get_domain_generic_chip(bank->domain, 0); + gc->reg_base = bank->reg_base; + gc->private = bank; + gc->chip_types[0].regs.mask = GPIO_INTEN; + gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; + gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; + gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; + gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; + + irq_set_handler_data(bank->irq, bank); + irq_set_chained_handler(bank->irq, rockchip_irq_demux); + } + + return 0; +} + +static int rockchip_gpiolib_register(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + struct gpio_chip *gc; + int ret; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + if (!bank->valid) { + dev_warn(&pdev->dev, "bank %s is not valid\n", + bank->name); + continue; + } + + bank->gpio_chip = rockchip_gpiolib_chip; + + gc = &bank->gpio_chip; + gc->base = bank->pin_base; + gc->ngpio = bank->nr_pins; + gc->dev = &pdev->dev; + gc->of_node = bank->of_node; + gc->label = bank->name; + + ret = gpiochip_add(gc); + if (ret) { + dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", + gc->label, ret); + goto fail; + } + } + + rockchip_interrupts_register(pdev, info); + + return 0; + +fail: + for (--i, --bank; i >= 0; --i, --bank) { + if (!bank->valid) + continue; + + if (gpiochip_remove(&bank->gpio_chip)) + dev_err(&pdev->dev, "gpio chip %s remove failed\n", + bank->gpio_chip.label); + } + return ret; +} + +static int rockchip_gpiolib_unregister(struct platform_device *pdev, + struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + int ret = 0; + int i; + + for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) { + if (!bank->valid) + continue; + + ret = gpiochip_remove(&bank->gpio_chip); + } + + if (ret) + dev_err(&pdev->dev, "gpio chip remove failed\n"); + + return ret; +} + +static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, + struct rockchip_pinctrl *info) +{ + struct resource res; + void __iomem *base; + + if (of_address_to_resource(bank->of_node, 0, &res)) { + dev_err(info->dev, "cannot find IO resource for bank\n"); + return -ENOENT; + } + + bank->reg_base = devm_ioremap_resource(info->dev, &res); + if (IS_ERR(bank->reg_base)) + return PTR_ERR(bank->reg_base); + + /* + * special case, where parts of the pull setting-registers are + * part of the PMU register space + */ + if (of_device_is_compatible(bank->of_node, + "rockchip,rk3188-gpio-bank0")) { + struct device_node *node; + + bank->bank_type = RK3188_BANK0; + + node = of_parse_phandle(bank->of_node->parent, + "rockchip,pmu", 0); + if (!node) { + if (of_address_to_resource(bank->of_node, 1, &res)) { + dev_err(info->dev, "cannot find IO resource for bank\n"); + return -ENOENT; + } + + base = devm_ioremap_resource(info->dev, &res); + if (IS_ERR(base)) + return PTR_ERR(base); + rockchip_regmap_config.max_register = + resource_size(&res) - 4; + rockchip_regmap_config.name = + "rockchip,rk3188-gpio-bank0-pull"; + bank->regmap_pull = devm_regmap_init_mmio(info->dev, + base, + &rockchip_regmap_config); + } + + } else { + bank->bank_type = COMMON_BANK; + } + + bank->irq = irq_of_parse_and_map(bank->of_node, 0); + + bank->clk = of_clk_get(bank->of_node, 0); + if (IS_ERR(bank->clk)) + return PTR_ERR(bank->clk); + + return clk_prepare_enable(bank->clk); +} + +static const struct of_device_id rockchip_pinctrl_dt_match[]; + +/* retrieve the soc specific data */ +static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( + struct rockchip_pinctrl *d, + struct platform_device *pdev) +{ + const struct of_device_id *match; + struct device_node *node = pdev->dev.of_node; + struct device_node *np; + struct rockchip_pin_ctrl *ctrl; + struct rockchip_pin_bank *bank; + int i; + + match = of_match_node(rockchip_pinctrl_dt_match, node); + ctrl = (struct rockchip_pin_ctrl *)match->data; + + for_each_child_of_node(node, np) { + if (!of_find_property(np, "gpio-controller", NULL)) + continue; + + bank = ctrl->pin_banks; + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + if (!strcmp(bank->name, np->name)) { + bank->of_node = np; + + if (!rockchip_get_bank_data(bank, d)) + bank->valid = true; + + break; + } + } + } + + bank = ctrl->pin_banks; + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + spin_lock_init(&bank->slock); + bank->drvdata = d; + bank->pin_base = ctrl->nr_pins; + ctrl->nr_pins += bank->nr_pins; + } + + return ctrl; +} + +static int rockchip_pinctrl_probe(struct platform_device *pdev) +{ + struct rockchip_pinctrl *info; + struct device *dev = &pdev->dev; + struct rockchip_pin_ctrl *ctrl; + struct device_node *np = pdev->dev.of_node, *node; + struct resource *res; + void __iomem *base; + int ret; + + if (!dev->of_node) { + dev_err(dev, "device tree node not found\n"); + return -ENODEV; + } + + info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev = dev; + + ctrl = rockchip_pinctrl_get_soc_data(info, pdev); + if (!ctrl) { + dev_err(dev, "driver data not available\n"); + return -EINVAL; + } + info->ctrl = ctrl; + + node = of_parse_phandle(np, "rockchip,grf", 0); + if (node) { + info->regmap_base = syscon_node_to_regmap(node); + if (IS_ERR(info->regmap_base)) + return PTR_ERR(info->regmap_base); + } else { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rockchip_regmap_config.max_register = resource_size(res) - 4; + rockchip_regmap_config.name = "rockchip,pinctrl"; + info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, + &rockchip_regmap_config); + + /* to check for the old dt-bindings */ + info->reg_size = resource_size(res); + + /* Honor the old binding, with pull registers as 2nd resource */ + if (ctrl->type == RK3188 && info->reg_size < 0x200) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rockchip_regmap_config.max_register = + resource_size(res) - 4; + rockchip_regmap_config.name = "rockchip,pinctrl-pull"; + info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, + base, + &rockchip_regmap_config); + } + } + + /* try to find the optional reference to the pmu syscon */ + node = of_parse_phandle(np, "rockchip,pmu", 0); + if (node) { + info->regmap_pmu = syscon_node_to_regmap(node); + if (IS_ERR(info->regmap_pmu)) + return PTR_ERR(info->regmap_pmu); + } + + ret = rockchip_gpiolib_register(pdev, info); + if (ret) + return ret; + + ret = rockchip_pinctrl_register(pdev, info); + if (ret) { + rockchip_gpiolib_unregister(pdev, info); + return ret; + } + + platform_set_drvdata(pdev, info); + + return 0; +} + +static struct rockchip_pin_bank rk2928_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk2928_pin_ctrl = { + .pin_banks = rk2928_pin_banks, + .nr_banks = ARRAY_SIZE(rk2928_pin_banks), + .label = "RK2928-GPIO", + .type = RK2928, + .mux_offset = 0xa8, + .pull_calc_reg = rk2928_calc_pull_reg_and_bit, +}; + +static struct rockchip_pin_bank rk3066a_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), + PIN_BANK(4, 32, "gpio4"), + PIN_BANK(6, 16, "gpio6"), +}; + +static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { + .pin_banks = rk3066a_pin_banks, + .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), + .label = "RK3066a-GPIO", + .type = RK2928, + .mux_offset = 0xa8, + .pull_calc_reg = rk2928_calc_pull_reg_and_bit, +}; + +static struct rockchip_pin_bank rk3066b_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { + .pin_banks = rk3066b_pin_banks, + .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), + .label = "RK3066b-GPIO", + .type = RK3066B, + .mux_offset = 0x60, +}; + +static struct rockchip_pin_bank rk3188_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3188_pin_ctrl = { + .pin_banks = rk3188_pin_banks, + .nr_banks = ARRAY_SIZE(rk3188_pin_banks), + .label = "RK3188-GPIO", + .type = RK3188, + .mux_offset = 0x60, + .pull_calc_reg = rk3188_calc_pull_reg_and_bit, +}; + +static const struct of_device_id rockchip_pinctrl_dt_match[] = { + { .compatible = "rockchip,rk2928-pinctrl", + .data = (void *)&rk2928_pin_ctrl }, + { .compatible = "rockchip,rk3066a-pinctrl", + .data = (void *)&rk3066a_pin_ctrl }, + { .compatible = "rockchip,rk3066b-pinctrl", + .data = (void *)&rk3066b_pin_ctrl }, + { .compatible = "rockchip,rk3188-pinctrl", + .data = (void *)&rk3188_pin_ctrl }, + {}, +}; +MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); + +static struct platform_driver rockchip_pinctrl_driver = { + .probe = rockchip_pinctrl_probe, + .driver = { + .name = "rockchip-pinctrl", + .owner = THIS_MODULE, + .of_match_table = rockchip_pinctrl_dt_match, + }, +}; + +static int __init rockchip_pinctrl_drv_register(void) +{ + return platform_driver_register(&rockchip_pinctrl_driver); +} +postcore_initcall(rockchip_pinctrl_drv_register); + +MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); +MODULE_DESCRIPTION("Rockchip pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-s3c24xx.c b/drivers/pinctrl/pinctrl-s3c24xx.c new file mode 100644 index 00000000000..ad3eaad1700 --- /dev/null +++ b/drivers/pinctrl/pinctrl-s3c24xx.c @@ -0,0 +1,651 @@ +/* + * S3C24XX specific support for Samsung pinctrl/gpiolib driver. + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file contains the SamsungS3C24XX specific information required by the + * Samsung pinctrl/gpiolib driver. It also includes the implementation of + * external gpio and wakeup interrupt support. + */ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/irqdomain.h> +#include <linux/irq.h> +#include <linux/of_irq.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/err.h> + +#include "pinctrl-samsung.h" + +#define NUM_EINT 24 +#define NUM_EINT_IRQ 6 +#define EINT_MAX_PER_GROUP 8 + +#define EINTPEND_REG 0xa8 +#define EINTMASK_REG 0xa4 + +#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP)) +#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88) +#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4) + +#define EINT_LEVEL_LOW 0 +#define EINT_LEVEL_HIGH 1 +#define EINT_EDGE_FALLING 2 +#define EINT_EDGE_RISING 4 +#define EINT_EDGE_BOTH 6 +#define EINT_MASK 0xf + +static struct samsung_pin_bank_type bank_type_1bit = { + .fld_width = { 1, 1, }, + .reg_offset = { 0x00, 0x04, }, +}; + +static struct samsung_pin_bank_type bank_type_2bit = { + .fld_width = { 2, 1, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, }, +}; + +#define PIN_BANK_A(pins, reg, id) \ + { \ + .type = &bank_type_1bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT(pins, reg, id) \ + { \ + .type = &bank_type_2bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\ + { \ + .type = &bank_type_2bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 2, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +/** + * struct s3c24xx_eint_data: EINT common data + * @drvdata: pin controller driver data + * @domains: IRQ domains of particular EINT interrupts + * @parents: mapped parent irqs in the main interrupt controller + */ +struct s3c24xx_eint_data { + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *domains[NUM_EINT]; + int parents[NUM_EINT_IRQ]; +}; + +/** + * struct s3c24xx_eint_domain_data: per irq-domain data + * @bank: pin bank related to the domain + * @eint_data: common data + * eint0_3_parent_only: live eints 0-3 only in the main intc + */ +struct s3c24xx_eint_domain_data { + struct samsung_pin_bank *bank; + struct s3c24xx_eint_data *eint_data; + bool eint0_3_parent_only; +}; + +static int s3c24xx_eint_get_trigger(unsigned int type) +{ + switch (type) { + case IRQ_TYPE_EDGE_RISING: + return EINT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + return EINT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + return EINT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + return EINT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + return EINT_LEVEL_LOW; + break; + default: + return -EINVAL; + } +} + +static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type) +{ + /* Edge- and level-triggered interrupts need different handlers */ + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(irq, handle_edge_irq); + else + __irq_set_handler_locked(irq, handle_level_irq); +} + +static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, + struct samsung_pin_bank *bank, int pin) +{ + struct samsung_pin_bank_type *bank_type = bank->type; + unsigned long flags; + void __iomem *reg; + u8 shift; + u32 mask; + u32 val; + + /* Make sure that pin is configured as interrupt */ + reg = d->virt_base + bank->pctl_offset; + shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + spin_lock_irqsave(&bank->slock, flags); + + val = readl(reg); + val &= ~(mask << shift); + val |= bank->eint_func << shift; + writel(val, reg); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +static int s3c24xx_eint_type(struct irq_data *data, unsigned int type) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + int index = bank->eint_offset + data->hwirq; + void __iomem *reg; + int trigger; + u8 shift; + u32 val; + + trigger = s3c24xx_eint_get_trigger(type); + if (trigger < 0) { + dev_err(d->dev, "unsupported external interrupt type\n"); + return -EINVAL; + } + + s3c24xx_eint_set_handler(data->irq, type); + + /* Set up interrupt trigger */ + reg = d->virt_base + EINT_REG(index); + shift = EINT_OFFS(index); + + val = readl(reg); + val &= ~(EINT_MASK << shift); + val |= trigger << shift; + writel(val, reg); + + s3c24xx_eint_set_function(d, bank, data->hwirq); + + return 0; +} + +/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */ + +static void s3c2410_eint0_3_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_ack(irq_get_irq_data(parent_irq)); +} + +static void s3c2410_eint0_3_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_mask(irq_get_irq_data(parent_irq)); +} + +static void s3c2410_eint0_3_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_unmask(irq_get_irq_data(parent_irq)); +} + +static struct irq_chip s3c2410_eint0_3_chip = { + .name = "s3c2410-eint0_3", + .irq_ack = s3c2410_eint0_3_ack, + .irq_mask = s3c2410_eint0_3_mask, + .irq_unmask = s3c2410_eint0_3_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + struct irq_data *data = irq_desc_get_irq_data(desc); + struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + unsigned int virq; + + /* the first 4 eints have a simple 1 to 1 mapping */ + virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); + /* Something must be really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); +} + +/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */ + +static void s3c2412_eint0_3_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + + unsigned long bitval = 1UL << data->hwirq; + writel(bitval, d->virt_base + EINTPEND_REG); +} + +static void s3c2412_eint0_3_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask |= (1UL << data->hwirq); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static void s3c2412_eint0_3_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask &= ~(1UL << data->hwirq); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static struct irq_chip s3c2412_eint0_3_chip = { + .name = "s3c2412-eint0_3", + .irq_ack = s3c2412_eint0_3_ack, + .irq_mask = s3c2412_eint0_3_mask, + .irq_unmask = s3c2412_eint0_3_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct irq_data *data = irq_desc_get_irq_data(desc); + struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + unsigned int virq; + + chained_irq_enter(chip, desc); + + /* the first 4 eints have a simple 1 to 1 mapping */ + virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); + /* Something must be really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); + + chained_irq_exit(chip, desc); +} + +/* Handling of all other eints */ + +static void s3c24xx_eint_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + + writel(1UL << index, d->virt_base + EINTPEND_REG); +} + +static void s3c24xx_eint_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask |= (1UL << index); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static void s3c24xx_eint_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask &= ~(1UL << index); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static struct irq_chip s3c24xx_eint_chip = { + .name = "s3c-eint", + .irq_ack = s3c24xx_eint_ack, + .irq_mask = s3c24xx_eint_mask, + .irq_unmask = s3c24xx_eint_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc, + u32 offset, u32 range) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct s3c24xx_eint_data *data = irq_get_handler_data(irq); + struct samsung_pinctrl_drv_data *d = data->drvdata; + unsigned int pend, mask; + + chained_irq_enter(chip, desc); + + pend = readl(d->virt_base + EINTPEND_REG); + mask = readl(d->virt_base + EINTMASK_REG); + + pend &= ~mask; + pend &= range; + + while (pend) { + unsigned int virq; + + irq = __ffs(pend); + pend &= ~(1 << irq); + virq = irq_linear_revmap(data->domains[irq], irq - offset); + /* Something is really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); + } + + chained_irq_exit(chip, desc); +} + +static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc) +{ + s3c24xx_demux_eint(irq, desc, 0, 0xf0); +} + +static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc) +{ + s3c24xx_demux_eint(irq, desc, 8, 0xffff00); +} + +static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = { + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c24xx_demux_eint4_7, + s3c24xx_demux_eint8_23, +}; + +static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = { + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c24xx_demux_eint4_7, + s3c24xx_demux_eint8_23, +}; + +static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c24xx_eint_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) + return -EINVAL; + + if (hw <= 3) { + if (ddata->eint0_3_parent_only) + irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip, + handle_edge_irq); + else + irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip, + handle_edge_irq); + } else { + irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, + handle_edge_irq); + } + irq_set_chip_data(virq, bank); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +static const struct irq_domain_ops s3c24xx_gpf_irq_ops = { + .map = s3c24xx_gpf_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c24xx_eint_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) + return -EINVAL; + + irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq); + irq_set_chip_data(virq, bank); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +static const struct irq_domain_ops s3c24xx_gpg_irq_ops = { + .map = s3c24xx_gpg_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static const struct of_device_id s3c24xx_eint_irq_ids[] = { + { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 }, + { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 }, + { } +}; + +static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d) +{ + struct device *dev = d->dev; + const struct of_device_id *match; + struct device_node *eint_np = NULL; + struct device_node *np; + struct samsung_pin_bank *bank; + struct s3c24xx_eint_data *eint_data; + const struct irq_domain_ops *ops; + unsigned int i; + bool eint0_3_parent_only; + irq_flow_handler_t *handlers; + + for_each_child_of_node(dev->of_node, np) { + match = of_match_node(s3c24xx_eint_irq_ids, np); + if (match) { + eint_np = np; + eint0_3_parent_only = (bool)match->data; + break; + } + } + if (!eint_np) + return -ENODEV; + + eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL); + if (!eint_data) + return -ENOMEM; + + eint_data->drvdata = d; + + handlers = eint0_3_parent_only ? s3c2410_eint_handlers + : s3c2412_eint_handlers; + for (i = 0; i < NUM_EINT_IRQ; ++i) { + unsigned int irq; + + irq = irq_of_parse_and_map(eint_np, i); + if (!irq) { + dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i); + return -ENXIO; + } + + eint_data->parents[i] = irq; + irq_set_chained_handler(irq, handlers[i]); + irq_set_handler_data(irq, eint_data); + } + + bank = d->ctrl->pin_banks; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + struct s3c24xx_eint_domain_data *ddata; + unsigned int mask; + unsigned int irq; + unsigned int pin; + + if (bank->eint_type != EINT_TYPE_WKUP) + continue; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->bank = bank; + ddata->eint_data = eint_data; + ddata->eint0_3_parent_only = eint0_3_parent_only; + + ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops + : &s3c24xx_gpg_irq_ops; + + bank->irq_domain = irq_domain_add_linear(bank->of_node, + bank->nr_pins, ops, ddata); + if (!bank->irq_domain) { + dev_err(dev, "wkup irq domain add failed\n"); + return -ENXIO; + } + + irq = bank->eint_offset; + mask = bank->eint_mask; + for (pin = 0; mask; ++pin, mask >>= 1) { + if (irq >= NUM_EINT) + break; + if (!(mask & 1)) + continue; + eint_data->domains[irq] = bank->irq_domain; + ++irq; + } + } + + return 0; +} + +static struct samsung_pin_bank s3c2412_pin_banks[] = { + PIN_BANK_A(23, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(11, 0x070, "gph"), + PIN_BANK_2BIT(13, 0x080, "gpj"), +}; + +struct samsung_pin_ctrl s3c2412_pin_ctrl[] = { + { + .pin_banks = s3c2412_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2412_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2412-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2416_pin_banks[] = { + PIN_BANK_A(27, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00), + PIN_BANK_2BIT(15, 0x070, "gph"), + PIN_BANK_2BIT(16, 0x0e0, "gpk"), + PIN_BANK_2BIT(14, 0x0f0, "gpl"), + PIN_BANK_2BIT(2, 0x100, "gpm"), +}; + +struct samsung_pin_ctrl s3c2416_pin_ctrl[] = { + { + .pin_banks = s3c2416_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2416_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2416-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2440_pin_banks[] = { + PIN_BANK_A(25, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(11, 0x070, "gph"), + PIN_BANK_2BIT(13, 0x0d0, "gpj"), +}; + +struct samsung_pin_ctrl s3c2440_pin_ctrl[] = { + { + .pin_banks = s3c2440_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2440_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2440-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2450_pin_banks[] = { + PIN_BANK_A(28, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(15, 0x070, "gph"), + PIN_BANK_2BIT(16, 0x0d0, "gpj"), + PIN_BANK_2BIT(16, 0x0e0, "gpk"), + PIN_BANK_2BIT(15, 0x0f0, "gpl"), + PIN_BANK_2BIT(2, 0x100, "gpm"), +}; + +struct samsung_pin_ctrl s3c2450_pin_ctrl[] = { + { + .pin_banks = s3c2450_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2450_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2450-GPIO", + }, +}; diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 4f54faf2971..3e61d0f8f14 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -28,6 +28,7 @@ #include <linux/gpio.h> #include <linux/irqdomain.h> #include <linux/spinlock.h> +#include <linux/syscore_ops.h> #include "core.h" #include "pinctrl-samsung.h" @@ -48,6 +49,9 @@ static struct pin_config { { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN }, }; +/* Global list of devices (struct samsung_pinctrl_drv_data) */ +static LIST_HEAD(drvdata_list); + static unsigned int pin_base; static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) @@ -438,9 +442,17 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, /* set the pin config settings for a specified pin */ static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long config) + unsigned long *configs, unsigned num_configs) { - return samsung_pinconf_rw(pctldev, pin, &config, true); + int i, ret; + + for (i = 0; i < num_configs; i++) { + ret = samsung_pinconf_rw(pctldev, pin, &configs[i], true); + if (ret < 0) + return ret; + } /* for each config */ + + return 0; } /* get the pin config settings for a specified pin */ @@ -452,7 +464,8 @@ static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, /* set the pin config settings for a specified pin group */ static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { struct samsung_pinctrl_drv_data *drvdata; const unsigned int *pins; @@ -462,7 +475,7 @@ static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev, pins = drvdata->pin_groups[group].pins; for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) - samsung_pinconf_set(pctldev, pins[cnt], config); + samsung_pinconf_set(pctldev, pins[cnt], configs, num_configs); return 0; } @@ -763,6 +776,10 @@ static int samsung_pinctrl_register(struct platform_device *pdev, } } + ret = samsung_pinctrl_parse_dt(pdev, drvdata); + if (ret) + return ret; + drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata); if (!drvdata->pctl_dev) { dev_err(&pdev->dev, "could not register pinctrl driver\n"); @@ -780,12 +797,6 @@ static int samsung_pinctrl_register(struct platform_device *pdev, pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange); } - ret = samsung_pinctrl_parse_dt(pdev, drvdata); - if (ret) { - pinctrl_unregister(drvdata->pctl_dev); - return ret; - } - return 0; } @@ -932,11 +943,6 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) drvdata->dev = dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "cannot find IO resource\n"); - return -ENOENT; - } - drvdata->virt_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(drvdata->virt_base)) return PTR_ERR(drvdata->virt_base); @@ -961,20 +967,182 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) ctrl->eint_wkup_init(drvdata); platform_set_drvdata(pdev, drvdata); + + /* Add to the global list */ + list_add_tail(&drvdata->node, &drvdata_list); + return 0; } +#ifdef CONFIG_PM + +/** + * samsung_pinctrl_suspend_dev - save pinctrl state for suspend for a device + * + * Save data for all banks handled by this device. + */ +static void samsung_pinctrl_suspend_dev( + struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + void __iomem *virt_base = drvdata->virt_base; + int i; + + for (i = 0; i < ctrl->nr_banks; i++) { + struct samsung_pin_bank *bank = &ctrl->pin_banks[i]; + void __iomem *reg = virt_base + bank->pctl_offset; + + u8 *offs = bank->type->reg_offset; + u8 *widths = bank->type->fld_width; + enum pincfg_type type; + + /* Registers without a powerdown config aren't lost */ + if (!widths[PINCFG_TYPE_CON_PDN]) + continue; + + for (type = 0; type < PINCFG_TYPE_NUM; type++) + if (widths[type]) + bank->pm_save[type] = readl(reg + offs[type]); + + if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { + /* Some banks have two config registers */ + bank->pm_save[PINCFG_TYPE_NUM] = + readl(reg + offs[PINCFG_TYPE_FUNC] + 4); + pr_debug("Save %s @ %p (con %#010x %08x)\n", + bank->name, reg, + bank->pm_save[PINCFG_TYPE_FUNC], + bank->pm_save[PINCFG_TYPE_NUM]); + } else { + pr_debug("Save %s @ %p (con %#010x)\n", bank->name, + reg, bank->pm_save[PINCFG_TYPE_FUNC]); + } + } + + if (ctrl->suspend) + ctrl->suspend(drvdata); +} + +/** + * samsung_pinctrl_resume_dev - restore pinctrl state from suspend for a device + * + * Restore one of the banks that was saved during suspend. + * + * We don't bother doing anything complicated to avoid glitching lines since + * we're called before pad retention is turned off. + */ +static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_ctrl *ctrl = drvdata->ctrl; + void __iomem *virt_base = drvdata->virt_base; + int i; + + if (ctrl->resume) + ctrl->resume(drvdata); + + for (i = 0; i < ctrl->nr_banks; i++) { + struct samsung_pin_bank *bank = &ctrl->pin_banks[i]; + void __iomem *reg = virt_base + bank->pctl_offset; + + u8 *offs = bank->type->reg_offset; + u8 *widths = bank->type->fld_width; + enum pincfg_type type; + + /* Registers without a powerdown config aren't lost */ + if (!widths[PINCFG_TYPE_CON_PDN]) + continue; + + if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { + /* Some banks have two config registers */ + pr_debug("%s @ %p (con %#010x %08x => %#010x %08x)\n", + bank->name, reg, + readl(reg + offs[PINCFG_TYPE_FUNC]), + readl(reg + offs[PINCFG_TYPE_FUNC] + 4), + bank->pm_save[PINCFG_TYPE_FUNC], + bank->pm_save[PINCFG_TYPE_NUM]); + writel(bank->pm_save[PINCFG_TYPE_NUM], + reg + offs[PINCFG_TYPE_FUNC] + 4); + } else { + pr_debug("%s @ %p (con %#010x => %#010x)\n", bank->name, + reg, readl(reg + offs[PINCFG_TYPE_FUNC]), + bank->pm_save[PINCFG_TYPE_FUNC]); + } + for (type = 0; type < PINCFG_TYPE_NUM; type++) + if (widths[type]) + writel(bank->pm_save[type], reg + offs[type]); + } +} + +/** + * samsung_pinctrl_suspend - save pinctrl state for suspend + * + * Save data for all banks across all devices. + */ +static int samsung_pinctrl_suspend(void) +{ + struct samsung_pinctrl_drv_data *drvdata; + + list_for_each_entry(drvdata, &drvdata_list, node) { + samsung_pinctrl_suspend_dev(drvdata); + } + + return 0; +} + +/** + * samsung_pinctrl_resume - restore pinctrl state for suspend + * + * Restore data for all banks across all devices. + */ +static void samsung_pinctrl_resume(void) +{ + struct samsung_pinctrl_drv_data *drvdata; + + list_for_each_entry_reverse(drvdata, &drvdata_list, node) { + samsung_pinctrl_resume_dev(drvdata); + } +} + +#else +#define samsung_pinctrl_suspend NULL +#define samsung_pinctrl_resume NULL +#endif + +static struct syscore_ops samsung_pinctrl_syscore_ops = { + .suspend = samsung_pinctrl_suspend, + .resume = samsung_pinctrl_resume, +}; + static const struct of_device_id samsung_pinctrl_dt_match[] = { #ifdef CONFIG_PINCTRL_EXYNOS + { .compatible = "samsung,exynos3250-pinctrl", + .data = (void *)exynos3250_pin_ctrl }, { .compatible = "samsung,exynos4210-pinctrl", .data = (void *)exynos4210_pin_ctrl }, { .compatible = "samsung,exynos4x12-pinctrl", .data = (void *)exynos4x12_pin_ctrl }, + { .compatible = "samsung,exynos5250-pinctrl", + .data = (void *)exynos5250_pin_ctrl }, + { .compatible = "samsung,exynos5260-pinctrl", + .data = (void *)exynos5260_pin_ctrl }, + { .compatible = "samsung,exynos5420-pinctrl", + .data = (void *)exynos5420_pin_ctrl }, + { .compatible = "samsung,s5pv210-pinctrl", + .data = (void *)s5pv210_pin_ctrl }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", .data = s3c64xx_pin_ctrl }, #endif +#ifdef CONFIG_PINCTRL_S3C24XX + { .compatible = "samsung,s3c2412-pinctrl", + .data = s3c2412_pin_ctrl }, + { .compatible = "samsung,s3c2416-pinctrl", + .data = s3c2416_pin_ctrl }, + { .compatible = "samsung,s3c2440-pinctrl", + .data = s3c2440_pin_ctrl }, + { .compatible = "samsung,s3c2450-pinctrl", + .data = s3c2450_pin_ctrl }, +#endif {}, }; MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match); @@ -984,12 +1152,20 @@ static struct platform_driver samsung_pinctrl_driver = { .driver = { .name = "samsung-pinctrl", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(samsung_pinctrl_dt_match), + .of_match_table = samsung_pinctrl_dt_match, }, }; static int __init samsung_pinctrl_drv_register(void) { + /* + * Register syscore ops for save/restore of registers across suspend. + * It's important to ensure that this driver is running at an earlier + * initcall level than any arch-specific init calls that install syscore + * ops that turn off pad retention (like exynos_pm_resume). + */ + register_syscore_ops(&samsung_pinctrl_syscore_ops); + return platform_driver_register(&samsung_pinctrl_driver); } postcore_initcall(samsung_pinctrl_drv_register); diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h index 45f27b41e30..b3e41fa5798 100644 --- a/drivers/pinctrl/pinctrl-samsung.h +++ b/drivers/pinctrl/pinctrl-samsung.h @@ -127,6 +127,7 @@ struct samsung_pin_bank_type { * @gpio_chip: GPIO chip of the bank. * @grange: linux gpio pin range supported by this bank. * @slock: spinlock protecting bank registers + * @pm_save: saved register values during suspend */ struct samsung_pin_bank { struct samsung_pin_bank_type *type; @@ -138,12 +139,15 @@ struct samsung_pin_bank { u32 eint_mask; u32 eint_offset; char *name; + void *soc_priv; struct device_node *of_node; struct samsung_pinctrl_drv_data *drvdata; struct irq_domain *irq_domain; struct gpio_chip gpio_chip; struct pinctrl_gpio_range grange; spinlock_t slock; + + u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ }; /** @@ -184,11 +188,15 @@ struct samsung_pin_ctrl { int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); + void (*suspend)(struct samsung_pinctrl_drv_data *); + void (*resume)(struct samsung_pinctrl_drv_data *); + char *label; }; /** * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. + * @node: global list node * @virt_base: register base address of the controller. * @dev: device instance representing the controller. * @irq: interrpt number used by the controller to notify gpio interrupts. @@ -201,6 +209,7 @@ struct samsung_pin_ctrl { * @nr_function: number of such pin functions. */ struct samsung_pinctrl_drv_data { + struct list_head node; void __iomem *virt_base; struct device *dev; int irq; @@ -242,8 +251,17 @@ struct samsung_pmx_func { }; /* list of all exported SoC specific data */ +extern struct samsung_pin_ctrl exynos3250_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2416_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2440_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2450_pin_ctrl[]; +extern struct samsung_pin_ctrl s5pv210_pin_ctrl[]; #endif /* __PINCTRL_SAMSUNG_H */ diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5f2d2bfd356..2960557bfed 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -15,22 +15,28 @@ #include <linux/slab.h> #include <linux/err.h> #include <linux/list.h> +#include <linux/interrupt.h> + +#include <linux/irqchip/chained_irq.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/of_address.h> +#include <linux/of_irq.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/platform_data/pinctrl-single.h> + #include "core.h" #include "pinconf.h" #define DRIVER_NAME "pinctrl-single" #define PCS_MUX_PINS_NAME "pinctrl-single,pins" #define PCS_MUX_BITS_NAME "pinctrl-single,bits" -#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) +#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3) #define PCS_OFF_DISABLED ~0U /** @@ -150,19 +156,37 @@ struct pcs_name { }; /** + * struct pcs_soc_data - SoC specific settings + * @flags: initial SoC specific PCS_FEAT_xxx values + * @irq: optional interrupt for the controller + * @irq_enable_mask: optional SoC specific interrupt enable mask + * @irq_status_mask: optional SoC specific interrupt status mask + * @rearm: optional SoC specific wake-up rearm function + */ +struct pcs_soc_data { + unsigned flags; + int irq; + unsigned irq_enable_mask; + unsigned irq_status_mask; + void (*rearm)(void); +}; + +/** * struct pcs_device - pinctrl device instance * @res: resources * @base: virtual address of the controller * @size: size of the ioremapped area * @dev: device entry * @pctl: pin controller device + * @flags: mask of PCS_FEAT_xxx values + * @lock: spinlock for register access * @mutex: mutex protecting the lists * @width: bits per mux register * @fmask: function register mask * @fshift: function register shift * @foff: value to turn mux off * @fmax: max number of functions in fmask - * @is_pinconf: whether supports pinconf + * @bits_per_pin:number of bits per pin * @names: array of register names for pins * @pins: physical pins on the SoC * @pgtree: pingroup index radix tree @@ -170,6 +194,9 @@ struct pcs_name { * @pingroups: list of pingroups * @functions: list of functions * @gpiofuncs: list of gpio functions + * @irqs: list of interrupt registers + * @chip: chip container for this instance + * @domain: IRQ domain for this instance * @ngroups: number of pingroups * @nfuncs: number of functions * @desc: pin controller descriptor @@ -182,6 +209,12 @@ struct pcs_device { unsigned size; struct device *dev; struct pinctrl_dev *pctl; + unsigned flags; +#define PCS_QUIRK_SHARED_IRQ (1 << 2) +#define PCS_FEAT_IRQ (1 << 1) +#define PCS_FEAT_PINCONF (1 << 0) + struct pcs_soc_data socdata; + raw_spinlock_t lock; struct mutex mutex; unsigned width; unsigned fmask; @@ -189,7 +222,7 @@ struct pcs_device { unsigned foff; unsigned fmax; bool bits_per_mux; - bool is_pinconf; + unsigned bits_per_pin; struct pcs_name *names; struct pcs_data pins; struct radix_tree_root pgtree; @@ -197,6 +230,9 @@ struct pcs_device { struct list_head pingroups; struct list_head functions; struct list_head gpiofuncs; + struct list_head irqs; + struct irq_chip chip; + struct irq_domain *domain; unsigned ngroups; unsigned nfuncs; struct pinctrl_desc desc; @@ -204,10 +240,14 @@ struct pcs_device { void (*write)(unsigned val, void __iomem *reg); }; +#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ) +#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ) +#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF) + static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config); static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config); + unsigned long *configs, unsigned num_configs); static enum pin_config_param pcs_bias[] = { PIN_CONFIG_BIAS_PULL_DOWN, @@ -427,18 +467,22 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, for (i = 0; i < func->nvals; i++) { struct pcs_func_vals *vals; + unsigned long flags; unsigned val, mask; vals = &func->vals[i]; + raw_spin_lock_irqsave(&pcs->lock, flags); val = pcs->read(vals->reg); - if (!vals->mask) - mask = pcs->fmask; + + if (pcs->bits_per_mux) + mask = vals->mask; else - mask = pcs->fmask & vals->mask; + mask = pcs->fmask; val &= ~mask; val |= (vals->val & mask); pcs->write(val, vals->reg); + raw_spin_unlock_irqrestore(&pcs->lock, flags); } return 0; @@ -480,13 +524,22 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, for (i = 0; i < func->nvals; i++) { struct pcs_func_vals *vals; - unsigned val; + unsigned long flags; + unsigned val, mask; vals = &func->vals[i]; + raw_spin_lock_irqsave(&pcs->lock, flags); val = pcs->read(vals->reg); - val &= ~pcs->fmask; + + if (pcs->bits_per_mux) + mask = vals->mask; + else + mask = pcs->fmask; + + val &= ~mask; val |= pcs->foff << pcs->fshift; pcs->write(val, vals->reg); + raw_spin_unlock_irqrestore(&pcs->lock, flags); } } @@ -533,7 +586,7 @@ static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) int i; for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { config = pinconf_to_config_packed(pcs_bias[i], 0); - pcs_pinconf_set(pctldev, pin, config); + pcs_pinconf_set(pctldev, pin, &config, 1); } } @@ -609,6 +662,7 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: + case PIN_CONFIG_LOW_POWER_MODE: default: *config = data; break; @@ -619,27 +673,34 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev, } static int pcs_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); struct pcs_function *func; unsigned offset = 0, shift = 0, i, data, ret; u16 arg; + int j; ret = pcs_get_function(pctldev, pin, &func); if (ret) return ret; - for (i = 0; i < func->nconfs; i++) { - if (pinconf_to_config_param(config) == func->conf[i].param) { + for (j = 0; j < num_configs; j++) { + for (i = 0; i < func->nconfs; i++) { + if (pinconf_to_config_param(configs[j]) + != func->conf[i].param) + continue; + offset = pin * (pcs->width / BITS_PER_BYTE); data = pcs->read(pcs->base + offset); - arg = pinconf_to_config_argument(config); + arg = pinconf_to_config_argument(configs[j]); switch (func->conf[i].param) { /* 2 parameters */ case PIN_CONFIG_INPUT_SCHMITT: case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: + case PIN_CONFIG_LOW_POWER_MODE: shift = ffs(func->conf[i].mask) - 1; data &= ~func->conf[i].mask; data |= (arg << shift) & func->conf[i].mask; @@ -664,10 +725,14 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev, return -ENOTSUPP; } pcs->write(data, pcs->base + offset); - return 0; + + break; } - } - return -ENOTSUPP; + if (i >= func->nconfs) + return -ENOTSUPP; + } /* for each config */ + + return 0; } static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, @@ -692,7 +757,8 @@ static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, } static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { const unsigned *pins; unsigned npins; @@ -702,7 +768,7 @@ static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, if (ret) return ret; for (i = 0; i < npins; i++) { - if (pcs_pinconf_set(pctldev, pins[i], config)) + if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs)) return -ENOTSUPP; } return 0; @@ -741,8 +807,10 @@ static const struct pinconf_ops pcs_pinconf_ops = { * @pcs: pcs driver instance * @offset: register offset from base */ -static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) +static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, + unsigned pin_pos) { + struct pcs_soc_data *pcs_soc = &pcs->socdata; struct pinctrl_pin_desc *pin; struct pcs_name *pn; int i; @@ -754,10 +822,22 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) return -ENOMEM; } + if (pcs_soc->irq_enable_mask) { + unsigned val; + + val = pcs->read(pcs->base + offset); + if (val & pcs_soc->irq_enable_mask) { + dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", + (unsigned long)pcs->res->start + offset, val); + val &= ~pcs_soc->irq_enable_mask; + pcs->write(val, pcs->base + offset); + } + } + pin = &pcs->pins.pa[i]; pn = &pcs->names[i]; - sprintf(pn->name, "%lx", - (unsigned long)pcs->res->start + offset); + sprintf(pn->name, "%lx.%d", + (unsigned long)pcs->res->start + offset, pin_pos); pin->name = pn->name; pin->number = i; pcs->pins.cur++; @@ -777,9 +857,17 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) static int pcs_allocate_pin_table(struct pcs_device *pcs) { int mux_bytes, nr_pins, i; + int num_pins_in_register = 0; mux_bytes = pcs->width / BITS_PER_BYTE; - nr_pins = pcs->size / mux_bytes; + + if (pcs->bits_per_mux) { + pcs->bits_per_pin = fls(pcs->fmask); + nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; + num_pins_in_register = pcs->width / pcs->bits_per_pin; + } else { + nr_pins = pcs->size / mux_bytes; + } dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); pcs->pins.pa = devm_kzalloc(pcs->dev, @@ -800,9 +888,17 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) for (i = 0; i < pcs->desc.npins; i++) { unsigned offset; int res; - - offset = i * mux_bytes; - res = pcs_add_pin(pcs, offset); + int byte_num; + int pin_pos = 0; + + if (pcs->bits_per_mux) { + byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; + offset = (byte_num / mux_bytes) * mux_bytes; + pin_pos = i % num_pins_in_register; + } else { + offset = i * mux_bytes; + } + res = pcs_add_pin(pcs, offset, pin_pos); if (res < 0) { dev_err(pcs->dev, "error adding pins: %i\n", res); return res; @@ -919,7 +1015,10 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) return -EINVAL; } - index = offset / (pcs->width / BITS_PER_BYTE); + if (pcs->bits_per_mux) + index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; + else + index = offset / (pcs->width / BITS_PER_BYTE); return index; } @@ -1017,6 +1116,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, + { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, }; struct pcs_conf_type prop4[] = { { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, @@ -1026,7 +1126,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, }; /* If pinconf isn't supported, don't parse properties in below. */ - if (!pcs->is_pinconf) + if (!PCS_HAS_PINCONF) return 0; /* cacluate how much properties are supported in current node */ @@ -1097,29 +1197,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, { struct pcs_func_vals *vals; const __be32 *mux; - int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; struct pcs_function *function; - if (pcs->bits_per_mux) { - params = 3; - mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); - } else { - params = 2; - mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); - } - - if (!mux) { - dev_err(pcs->dev, "no valid property for %s\n", np->name); - return -EINVAL; - } - - if (size < (sizeof(*mux) * params)) { - dev_err(pcs->dev, "bad data for %s\n", np->name); + mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); + if ((!mux) || (size < sizeof(*mux) * 2)) { + dev_err(pcs->dev, "bad data for mux %s\n", + np->name); return -EINVAL; } size /= sizeof(*mux); /* Number of elements in array */ - rows = size / params; + rows = size / 2; vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); if (!vals) @@ -1137,10 +1226,6 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, val = be32_to_cpup(mux + index++); vals[found].reg = pcs->base + offset; vals[found].val = val; - if (params == 3) { - val = be32_to_cpup(mux + index++); - vals[found].mask = val; - } pin = pcs_get_pin_by_offset(pcs, offset); if (pin < 0) { @@ -1165,8 +1250,9 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, (*map)->data.mux.group = np->name; (*map)->data.mux.function = np->name; - if (pcs->is_pinconf) { - if (pcs_parse_pinconf(pcs, np, function, map)) + if (PCS_HAS_PINCONF) { + res = pcs_parse_pinconf(pcs, np, function, map); + if (res) goto free_pingroups; *num_maps = 2; } else { @@ -1188,6 +1274,133 @@ free_vals: return res; } + +#define PARAMS_FOR_BITS_PER_MUX 3 + +static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, + struct device_node *np, + struct pinctrl_map **map, + unsigned *num_maps, + const char **pgnames) +{ + struct pcs_func_vals *vals; + const __be32 *mux; + int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int npins_in_row; + struct pcs_function *function; + + mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); + + if (!mux) { + dev_err(pcs->dev, "no valid property for %s\n", np->name); + return -EINVAL; + } + + if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) { + dev_err(pcs->dev, "bad data for %s\n", np->name); + return -EINVAL; + } + + /* Number of elements in array */ + size /= sizeof(*mux); + + rows = size / PARAMS_FOR_BITS_PER_MUX; + npins_in_row = pcs->width / pcs->bits_per_pin; + + vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row, + GFP_KERNEL); + if (!vals) + return -ENOMEM; + + pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row, + GFP_KERNEL); + if (!pins) + goto free_vals; + + while (index < size) { + unsigned offset, val; + unsigned mask, bit_pos, val_pos, mask_pos, submask; + unsigned pin_num_from_lsb; + int pin; + + offset = be32_to_cpup(mux + index++); + val = be32_to_cpup(mux + index++); + mask = be32_to_cpup(mux + index++); + + /* Parse pins in each row from LSB */ + while (mask) { + bit_pos = ffs(mask); + pin_num_from_lsb = bit_pos / pcs->bits_per_pin; + mask_pos = ((pcs->fmask) << (bit_pos - 1)); + val_pos = val & mask_pos; + submask = mask & mask_pos; + + if ((mask & mask_pos) == 0) { + dev_err(pcs->dev, + "Invalid mask for %s at 0x%x\n", + np->name, offset); + break; + } + + mask &= ~mask_pos; + + if (submask != mask_pos) { + dev_warn(pcs->dev, + "Invalid submask 0x%x for %s at 0x%x\n", + submask, np->name, offset); + continue; + } + + vals[found].mask = submask; + vals[found].reg = pcs->base + offset; + vals[found].val = val_pos; + + pin = pcs_get_pin_by_offset(pcs, offset); + if (pin < 0) { + dev_err(pcs->dev, + "could not add functions for %s %ux\n", + np->name, offset); + break; + } + pins[found++] = pin + pin_num_from_lsb; + } + } + + pgnames[0] = np->name; + function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); + if (!function) + goto free_pins; + + res = pcs_add_pingroup(pcs, np, np->name, pins, found); + if (res < 0) + goto free_function; + + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->data.mux.group = np->name; + (*map)->data.mux.function = np->name; + + if (PCS_HAS_PINCONF) { + dev_err(pcs->dev, "pinconf not supported\n"); + goto free_pingroups; + } + + *num_maps = 1; + return 0; + +free_pingroups: + pcs_free_pingroups(pcs); + *num_maps = 1; +free_function: + pcs_remove_function(pcs, function); + +free_pins: + devm_kfree(pcs->dev, pins); + +free_vals: + devm_kfree(pcs->dev, vals); + + return res; +} /** * pcs_dt_node_to_map() - allocates and parses pinctrl maps * @pctldev: pinctrl instance @@ -1218,12 +1431,22 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, goto free_map; } - ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps, - pgnames); - if (ret < 0) { - dev_err(pcs->dev, "no pins entries for %s\n", - np_config->name); - goto free_pgnames; + if (pcs->bits_per_mux) { + ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } + } else { + ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, + num_maps, pgnames); + if (ret < 0) { + dev_err(pcs->dev, "no pins entries for %s\n", + np_config->name); + goto free_pgnames; + } } return 0; @@ -1291,11 +1514,33 @@ static void pcs_free_pingroups(struct pcs_device *pcs) } /** + * pcs_irq_free() - free interrupt + * @pcs: pcs driver instance + */ +static void pcs_irq_free(struct pcs_device *pcs) +{ + struct pcs_soc_data *pcs_soc = &pcs->socdata; + + if (pcs_soc->irq < 0) + return; + + if (pcs->domain) + irq_domain_remove(pcs->domain); + + if (PCS_QUIRK_HAS_SHARED_IRQ) + free_irq(pcs_soc->irq, pcs_soc); + else + irq_set_chained_handler(pcs_soc->irq, NULL); +} + +/** * pcs_free_resources() - free memory used by this driver * @pcs: pcs driver instance */ static void pcs_free_resources(struct pcs_device *pcs) { + pcs_irq_free(pcs); + if (pcs->pctl) pinctrl_unregister(pcs->pctl); @@ -1344,13 +1589,298 @@ static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) } return ret; } +/** + * @reg: virtual address of interrupt register + * @hwirq: hardware irq number + * @irq: virtual irq number + * @node: list node + */ +struct pcs_interrupt { + void __iomem *reg; + irq_hw_number_t hwirq; + unsigned int irq; + struct list_head node; +}; + +/** + * pcs_irq_set() - enables or disables an interrupt + * + * Note that this currently assumes one interrupt per pinctrl + * register that is typically used for wake-up events. + */ +static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc, + int irq, const bool enable) +{ + struct pcs_device *pcs; + struct list_head *pos; + unsigned mask; + + pcs = container_of(pcs_soc, struct pcs_device, socdata); + list_for_each(pos, &pcs->irqs) { + struct pcs_interrupt *pcswi; + unsigned soc_mask; + + pcswi = list_entry(pos, struct pcs_interrupt, node); + if (irq != pcswi->irq) + continue; + + soc_mask = pcs_soc->irq_enable_mask; + raw_spin_lock(&pcs->lock); + mask = pcs->read(pcswi->reg); + if (enable) + mask |= soc_mask; + else + mask &= ~soc_mask; + pcs->write(mask, pcswi->reg); + raw_spin_unlock(&pcs->lock); + } + + if (pcs_soc->rearm) + pcs_soc->rearm(); +} + +/** + * pcs_irq_mask() - mask pinctrl interrupt + * @d: interrupt data + */ +static void pcs_irq_mask(struct irq_data *d) +{ + struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); + + pcs_irq_set(pcs_soc, d->irq, false); +} + +/** + * pcs_irq_unmask() - unmask pinctrl interrupt + * @d: interrupt data + */ +static void pcs_irq_unmask(struct irq_data *d) +{ + struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); + + pcs_irq_set(pcs_soc, d->irq, true); +} + +/** + * pcs_irq_set_wake() - toggle the suspend and resume wake up + * @d: interrupt data + * @state: wake-up state + * + * Note that this should be called only for suspend and resume. + * For runtime PM, the wake-up events should be enabled by default. + */ +static int pcs_irq_set_wake(struct irq_data *d, unsigned int state) +{ + if (state) + pcs_irq_unmask(d); + else + pcs_irq_mask(d); + + return 0; +} + +/** + * pcs_irq_handle() - common interrupt handler + * @pcs_irq: interrupt data + * + * Note that this currently assumes we have one interrupt bit per + * mux register. This interrupt is typically used for wake-up events. + * For more complex interrupts different handlers can be specified. + */ +static int pcs_irq_handle(struct pcs_soc_data *pcs_soc) +{ + struct pcs_device *pcs; + struct list_head *pos; + int count = 0; + + pcs = container_of(pcs_soc, struct pcs_device, socdata); + list_for_each(pos, &pcs->irqs) { + struct pcs_interrupt *pcswi; + unsigned mask; + + pcswi = list_entry(pos, struct pcs_interrupt, node); + raw_spin_lock(&pcs->lock); + mask = pcs->read(pcswi->reg); + raw_spin_unlock(&pcs->lock); + if (mask & pcs_soc->irq_status_mask) { + generic_handle_irq(irq_find_mapping(pcs->domain, + pcswi->hwirq)); + count++; + } + } + + return count; +} + +/** + * pcs_irq_handler() - handler for the shared interrupt case + * @irq: interrupt + * @d: data + * + * Use this for cases where multiple instances of + * pinctrl-single share a single interrupt like on omaps. + */ +static irqreturn_t pcs_irq_handler(int irq, void *d) +{ + struct pcs_soc_data *pcs_soc = d; + + return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE; +} + +/** + * pcs_irq_handle() - handler for the dedicated chained interrupt case + * @irq: interrupt + * @desc: interrupt descriptor + * + * Use this if you have a separate interrupt for each + * pinctrl-single instance. + */ +static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc) +{ + struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); + struct irq_chip *chip; + int res; + + chip = irq_get_chip(irq); + chained_irq_enter(chip, desc); + res = pcs_irq_handle(pcs_soc); + /* REVISIT: export and add handle_bad_irq(irq, desc)? */ + chained_irq_exit(chip, desc); + + return; +} + +static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct pcs_soc_data *pcs_soc = d->host_data; + struct pcs_device *pcs; + struct pcs_interrupt *pcswi; + + pcs = container_of(pcs_soc, struct pcs_device, socdata); + pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); + if (!pcswi) + return -ENOMEM; + + pcswi->reg = pcs->base + hwirq; + pcswi->hwirq = hwirq; + pcswi->irq = irq; + + mutex_lock(&pcs->mutex); + list_add_tail(&pcswi->node, &pcs->irqs); + mutex_unlock(&pcs->mutex); + + irq_set_chip_data(irq, pcs_soc); + irq_set_chip_and_handler(irq, &pcs->chip, + handle_level_irq); + +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); +#else + irq_set_noprobe(irq); +#endif + + return 0; +} + +static struct irq_domain_ops pcs_irqdomain_ops = { + .map = pcs_irqdomain_map, + .xlate = irq_domain_xlate_onecell, +}; + +/** + * pcs_irq_init_chained_handler() - set up a chained interrupt handler + * @pcs: pcs driver instance + * @np: device node pointer + */ +static int pcs_irq_init_chained_handler(struct pcs_device *pcs, + struct device_node *np) +{ + struct pcs_soc_data *pcs_soc = &pcs->socdata; + const char *name = "pinctrl"; + int num_irqs; + + if (!pcs_soc->irq_enable_mask || + !pcs_soc->irq_status_mask) { + pcs_soc->irq = -1; + return -EINVAL; + } + + INIT_LIST_HEAD(&pcs->irqs); + pcs->chip.name = name; + pcs->chip.irq_ack = pcs_irq_mask; + pcs->chip.irq_mask = pcs_irq_mask; + pcs->chip.irq_unmask = pcs_irq_unmask; + pcs->chip.irq_set_wake = pcs_irq_set_wake; + + if (PCS_QUIRK_HAS_SHARED_IRQ) { + int res; + + res = request_irq(pcs_soc->irq, pcs_irq_handler, + IRQF_SHARED | IRQF_NO_SUSPEND, + name, pcs_soc); + if (res) { + pcs_soc->irq = -1; + return res; + } + } else { + irq_set_handler_data(pcs_soc->irq, pcs_soc); + irq_set_chained_handler(pcs_soc->irq, + pcs_irq_chain_handler); + } + + /* + * We can use the register offset as the hardirq + * number as irq_domain_add_simple maps them lazily. + * This way we can easily support more than one + * interrupt per function if needed. + */ + num_irqs = pcs->size; + + pcs->domain = irq_domain_add_simple(np, num_irqs, 0, + &pcs_irqdomain_ops, + pcs_soc); + if (!pcs->domain) { + irq_set_chained_handler(pcs_soc->irq, NULL); + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_PM +static int pinctrl_single_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct pcs_device *pcs; + + pcs = platform_get_drvdata(pdev); + if (!pcs) + return -EINVAL; + + return pinctrl_force_sleep(pcs->pctl); +} + +static int pinctrl_single_resume(struct platform_device *pdev) +{ + struct pcs_device *pcs; + + pcs = platform_get_drvdata(pdev); + if (!pcs) + return -EINVAL; + + return pinctrl_force_default(pcs->pctl); +} +#endif static int pcs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; const struct of_device_id *match; + struct pcs_pdata *pdata; struct resource *res; struct pcs_device *pcs; + const struct pcs_soc_data *soc; int ret; match = of_match_device(pcs_of_match, &pdev->dev); @@ -1363,11 +1893,14 @@ static int pcs_probe(struct platform_device *pdev) return -ENOMEM; } pcs->dev = &pdev->dev; + raw_spin_lock_init(&pcs->lock); mutex_init(&pcs->mutex); INIT_LIST_HEAD(&pcs->pingroups); INIT_LIST_HEAD(&pcs->functions); INIT_LIST_HEAD(&pcs->gpiofuncs); - pcs->is_pinconf = match->data; + soc = match->data; + pcs->flags = soc->flags; + memcpy(&pcs->socdata, soc, sizeof(*soc)); PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, "register width not specified\n"); @@ -1436,7 +1969,7 @@ static int pcs_probe(struct platform_device *pdev) pcs->desc.name = DRIVER_NAME; pcs->desc.pctlops = &pcs_pinctrl_ops; pcs->desc.pmxops = &pcs_pinmux_ops; - if (pcs->is_pinconf) + if (PCS_HAS_PINCONF) pcs->desc.confops = &pcs_pinconf_ops; pcs->desc.owner = THIS_MODULE; @@ -1455,6 +1988,27 @@ static int pcs_probe(struct platform_device *pdev) if (ret < 0) goto free; + pcs->socdata.irq = irq_of_parse_and_map(np, 0); + if (pcs->socdata.irq) + pcs->flags |= PCS_FEAT_IRQ; + + /* We still need auxdata for some omaps for PRM interrupts */ + pdata = dev_get_platdata(&pdev->dev); + if (pdata) { + if (pdata->rearm) + pcs->socdata.rearm = pdata->rearm; + if (pdata->irq) { + pcs->socdata.irq = pdata->irq; + pcs->flags |= PCS_FEAT_IRQ; + } + } + + if (PCS_HAS_IRQ) { + ret = pcs_irq_init_chained_handler(pcs, np); + if (ret < 0) + dev_warn(pcs->dev, "initialized with no interrupts\n"); + } + dev_info(pcs->dev, "%i pins at pa %p size %u\n", pcs->desc.npins, pcs->base, pcs->size); @@ -1478,9 +2032,25 @@ static int pcs_remove(struct platform_device *pdev) return 0; } +static const struct pcs_soc_data pinctrl_single_omap_wkup = { + .flags = PCS_QUIRK_SHARED_IRQ, + .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */ + .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ +}; + +static const struct pcs_soc_data pinctrl_single = { +}; + +static const struct pcs_soc_data pinconf_single = { + .flags = PCS_FEAT_PINCONF, +}; + static struct of_device_id pcs_of_match[] = { - { .compatible = "pinctrl-single", .data = (void *)false }, - { .compatible = "pinconf-single", .data = (void *)true }, + { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, + { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, + { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, + { .compatible = "pinctrl-single", .data = &pinctrl_single }, + { .compatible = "pinconf-single", .data = &pinconf_single }, { }, }; MODULE_DEVICE_TABLE(of, pcs_of_match); @@ -1493,6 +2063,10 @@ static struct platform_driver pcs_driver = { .name = DRIVER_NAME, .of_match_table = pcs_of_match, }, +#ifdef CONFIG_PM + .suspend = pinctrl_single_suspend, + .resume = pinctrl_single_resume, +#endif }; module_platform_driver(pcs_driver); diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c deleted file mode 100644 index fb906257074..00000000000 --- a/drivers/pinctrl/pinctrl-sirf.c +++ /dev/null @@ -1,1814 +0,0 @@ -/* - * pinmux driver for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/err.h> -#include <linux/irqdomain.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/machine.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> -#include <linux/bitops.h> -#include <linux/gpio.h> -#include <linux/of_gpio.h> -#include <asm/mach/irq.h> - -#define DRIVER_NAME "pinmux-sirf" - -#define SIRFSOC_NUM_PADS 622 -#define SIRFSOC_RSC_PIN_MUX 0x4 - -#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) -#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90) -#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4) -#define SIRFSOC_GPIO_DSP_EN0 (0x80) -#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C) - -#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1 -#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2 -#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4 -#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8 -#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10 -#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20 -#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40 -#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80 -#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100 -#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200 -#define SIRFSOC_GPIO_CTL_DSP_INT 0x400 - -#define SIRFSOC_GPIO_NO_OF_BANKS 5 -#define SIRFSOC_GPIO_BANK_SIZE 32 -#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index)) - -struct sirfsoc_gpio_bank { - struct of_mm_gpio_chip chip; - struct irq_domain *domain; - int id; - int parent_irq; - spinlock_t lock; - bool is_marco; /* for marco, some registers are different with prima2 */ -}; - -static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; -static DEFINE_SPINLOCK(sgpio_lock); - -/* - * pad list for the pinmux subsystem - * refer to CS-131858-DC-6A.xls - */ -static const struct pinctrl_pin_desc sirfsoc_pads[] = { - PINCTRL_PIN(0, "gpio0-0"), - PINCTRL_PIN(1, "gpio0-1"), - PINCTRL_PIN(2, "gpio0-2"), - PINCTRL_PIN(3, "gpio0-3"), - PINCTRL_PIN(4, "pwm0"), - PINCTRL_PIN(5, "pwm1"), - PINCTRL_PIN(6, "pwm2"), - PINCTRL_PIN(7, "pwm3"), - PINCTRL_PIN(8, "warm_rst_b"), - PINCTRL_PIN(9, "odo_0"), - PINCTRL_PIN(10, "odo_1"), - PINCTRL_PIN(11, "dr_dir"), - PINCTRL_PIN(12, "viprom_fa"), - PINCTRL_PIN(13, "scl_1"), - PINCTRL_PIN(14, "ntrst"), - PINCTRL_PIN(15, "sda_1"), - PINCTRL_PIN(16, "x_ldd[16]"), - PINCTRL_PIN(17, "x_ldd[17]"), - PINCTRL_PIN(18, "x_ldd[18]"), - PINCTRL_PIN(19, "x_ldd[19]"), - PINCTRL_PIN(20, "x_ldd[20]"), - PINCTRL_PIN(21, "x_ldd[21]"), - PINCTRL_PIN(22, "x_ldd[22]"), - PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"), - PINCTRL_PIN(24, "gps_sgn"), - PINCTRL_PIN(25, "gps_mag"), - PINCTRL_PIN(26, "gps_clk"), - PINCTRL_PIN(27, "sd_cd_b_1"), - PINCTRL_PIN(28, "sd_vcc_on_1"), - PINCTRL_PIN(29, "sd_wp_b_1"), - PINCTRL_PIN(30, "sd_clk_3"), - PINCTRL_PIN(31, "sd_cmd_3"), - - PINCTRL_PIN(32, "x_sd_dat_3[0]"), - PINCTRL_PIN(33, "x_sd_dat_3[1]"), - PINCTRL_PIN(34, "x_sd_dat_3[2]"), - PINCTRL_PIN(35, "x_sd_dat_3[3]"), - PINCTRL_PIN(36, "x_sd_clk_4"), - PINCTRL_PIN(37, "x_sd_cmd_4"), - PINCTRL_PIN(38, "x_sd_dat_4[0]"), - PINCTRL_PIN(39, "x_sd_dat_4[1]"), - PINCTRL_PIN(40, "x_sd_dat_4[2]"), - PINCTRL_PIN(41, "x_sd_dat_4[3]"), - PINCTRL_PIN(42, "x_cko_1"), - PINCTRL_PIN(43, "x_ac97_bit_clk"), - PINCTRL_PIN(44, "x_ac97_dout"), - PINCTRL_PIN(45, "x_ac97_din"), - PINCTRL_PIN(46, "x_ac97_sync"), - PINCTRL_PIN(47, "x_txd_1"), - PINCTRL_PIN(48, "x_txd_2"), - PINCTRL_PIN(49, "x_rxd_1"), - PINCTRL_PIN(50, "x_rxd_2"), - PINCTRL_PIN(51, "x_usclk_0"), - PINCTRL_PIN(52, "x_utxd_0"), - PINCTRL_PIN(53, "x_urxd_0"), - PINCTRL_PIN(54, "x_utfs_0"), - PINCTRL_PIN(55, "x_urfs_0"), - PINCTRL_PIN(56, "x_usclk_1"), - PINCTRL_PIN(57, "x_utxd_1"), - PINCTRL_PIN(58, "x_urxd_1"), - PINCTRL_PIN(59, "x_utfs_1"), - PINCTRL_PIN(60, "x_urfs_1"), - PINCTRL_PIN(61, "x_usclk_2"), - PINCTRL_PIN(62, "x_utxd_2"), - PINCTRL_PIN(63, "x_urxd_2"), - - PINCTRL_PIN(64, "x_utfs_2"), - PINCTRL_PIN(65, "x_urfs_2"), - PINCTRL_PIN(66, "x_df_we_b"), - PINCTRL_PIN(67, "x_df_re_b"), - PINCTRL_PIN(68, "x_txd_0"), - PINCTRL_PIN(69, "x_rxd_0"), - PINCTRL_PIN(78, "x_cko_0"), - PINCTRL_PIN(79, "x_vip_pxd[7]"), - PINCTRL_PIN(80, "x_vip_pxd[6]"), - PINCTRL_PIN(81, "x_vip_pxd[5]"), - PINCTRL_PIN(82, "x_vip_pxd[4]"), - PINCTRL_PIN(83, "x_vip_pxd[3]"), - PINCTRL_PIN(84, "x_vip_pxd[2]"), - PINCTRL_PIN(85, "x_vip_pxd[1]"), - PINCTRL_PIN(86, "x_vip_pxd[0]"), - PINCTRL_PIN(87, "x_vip_vsync"), - PINCTRL_PIN(88, "x_vip_hsync"), - PINCTRL_PIN(89, "x_vip_pxclk"), - PINCTRL_PIN(90, "x_sda_0"), - PINCTRL_PIN(91, "x_scl_0"), - PINCTRL_PIN(92, "x_df_ry_by"), - PINCTRL_PIN(93, "x_df_cs_b[1]"), - PINCTRL_PIN(94, "x_df_cs_b[0]"), - PINCTRL_PIN(95, "x_l_pclk"), - - PINCTRL_PIN(96, "x_l_lck"), - PINCTRL_PIN(97, "x_l_fck"), - PINCTRL_PIN(98, "x_l_de"), - PINCTRL_PIN(99, "x_ldd[0]"), - PINCTRL_PIN(100, "x_ldd[1]"), - PINCTRL_PIN(101, "x_ldd[2]"), - PINCTRL_PIN(102, "x_ldd[3]"), - PINCTRL_PIN(103, "x_ldd[4]"), - PINCTRL_PIN(104, "x_ldd[5]"), - PINCTRL_PIN(105, "x_ldd[6]"), - PINCTRL_PIN(106, "x_ldd[7]"), - PINCTRL_PIN(107, "x_ldd[8]"), - PINCTRL_PIN(108, "x_ldd[9]"), - PINCTRL_PIN(109, "x_ldd[10]"), - PINCTRL_PIN(110, "x_ldd[11]"), - PINCTRL_PIN(111, "x_ldd[12]"), - PINCTRL_PIN(112, "x_ldd[13]"), - PINCTRL_PIN(113, "x_ldd[14]"), - PINCTRL_PIN(114, "x_ldd[15]"), -}; - -/** - * @dev: a pointer back to containing device - * @virtbase: the offset to the controller in virtual memory - */ -struct sirfsoc_pmx { - struct device *dev; - struct pinctrl_dev *pmx; - void __iomem *gpio_virtbase; - void __iomem *rsc_virtbase; - bool is_marco; -}; - -/* SIRFSOC_GPIO_PAD_EN set */ -struct sirfsoc_muxmask { - unsigned long group; - unsigned long mask; -}; - -struct sirfsoc_padmux { - unsigned long muxmask_counts; - const struct sirfsoc_muxmask *muxmask; - /* RSC_PIN_MUX set */ - unsigned long funcmask; - unsigned long funcval; -}; - - /** - * struct sirfsoc_pin_group - describes a SiRFprimaII pin group - * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @num_pins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - */ -struct sirfsoc_pin_group { - const char *name; - const unsigned int *pins; - const unsigned num_pins; -}; - -static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { - { - .group = 3, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | - BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | - BIT(17) | BIT(18), - }, { - .group = 2, - .mask = BIT(31), - }, -}; - -static const struct sirfsoc_padmux lcd_16bits_padmux = { - .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), - .muxmask = lcd_16bits_sirfsoc_muxmask, - .funcmask = BIT(4), - .funcval = 0, -}; - -static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; - -static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { - { - .group = 3, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | - BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | - BIT(17) | BIT(18), - }, { - .group = 2, - .mask = BIT(31), - }, { - .group = 0, - .mask = BIT(16) | BIT(17), - }, -}; - -static const struct sirfsoc_padmux lcd_18bits_padmux = { - .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), - .muxmask = lcd_18bits_muxmask, - .funcmask = BIT(4), - .funcval = 0, -}; - -static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; - -static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { - { - .group = 3, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | - BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | - BIT(17) | BIT(18), - }, { - .group = 2, - .mask = BIT(31), - }, { - .group = 0, - .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), - }, -}; - -static const struct sirfsoc_padmux lcd_24bits_padmux = { - .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), - .muxmask = lcd_24bits_muxmask, - .funcmask = BIT(4), - .funcval = 0, -}; - -static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; - -static const struct sirfsoc_muxmask lcdrom_muxmask[] = { - { - .group = 3, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | - BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | - BIT(17) | BIT(18), - }, { - .group = 2, - .mask = BIT(31), - }, { - .group = 0, - .mask = BIT(23), - }, -}; - -static const struct sirfsoc_padmux lcdrom_padmux = { - .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), - .muxmask = lcdrom_muxmask, - .funcmask = BIT(4), - .funcval = BIT(4), -}; - -static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; - -static const struct sirfsoc_muxmask uart0_muxmask[] = { - { - .group = 2, - .mask = BIT(4) | BIT(5), - }, { - .group = 1, - .mask = BIT(23) | BIT(28), - }, -}; - -static const struct sirfsoc_padmux uart0_padmux = { - .muxmask_counts = ARRAY_SIZE(uart0_muxmask), - .muxmask = uart0_muxmask, - .funcmask = BIT(9), - .funcval = BIT(9), -}; - -static const unsigned uart0_pins[] = { 55, 60, 68, 69 }; - -static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { - { - .group = 2, - .mask = BIT(4) | BIT(5), - }, -}; - -static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { - .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask), - .muxmask = uart0_nostreamctrl_muxmask, -}; - -static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 }; - -static const struct sirfsoc_muxmask uart1_muxmask[] = { - { - .group = 1, - .mask = BIT(15) | BIT(17), - }, -}; - -static const struct sirfsoc_padmux uart1_padmux = { - .muxmask_counts = ARRAY_SIZE(uart1_muxmask), - .muxmask = uart1_muxmask, -}; - -static const unsigned uart1_pins[] = { 47, 49 }; - -static const struct sirfsoc_muxmask uart2_muxmask[] = { - { - .group = 1, - .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27), - }, -}; - -static const struct sirfsoc_padmux uart2_padmux = { - .muxmask_counts = ARRAY_SIZE(uart2_muxmask), - .muxmask = uart2_muxmask, - .funcmask = BIT(10), - .funcval = BIT(10), -}; - -static const unsigned uart2_pins[] = { 48, 50, 56, 59 }; - -static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { - { - .group = 1, - .mask = BIT(16) | BIT(18), - }, -}; - -static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { - .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask), - .muxmask = uart2_nostreamctrl_muxmask, -}; - -static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; - -static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { - { - .group = 0, - .mask = BIT(30) | BIT(31), - }, { - .group = 1, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), - }, -}; - -static const struct sirfsoc_padmux sdmmc3_padmux = { - .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), - .muxmask = sdmmc3_muxmask, - .funcmask = BIT(7), - .funcval = 0, -}; - -static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; - -static const struct sirfsoc_muxmask spi0_muxmask[] = { - { - .group = 1, - .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), - }, -}; - -static const struct sirfsoc_padmux spi0_padmux = { - .muxmask_counts = ARRAY_SIZE(spi0_muxmask), - .muxmask = spi0_muxmask, - .funcmask = BIT(7), - .funcval = BIT(7), -}; - -static const unsigned spi0_pins[] = { 32, 33, 34, 35 }; - -static const struct sirfsoc_muxmask sdmmc4_muxmask[] = { - { - .group = 1, - .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9), - }, -}; - -static const struct sirfsoc_padmux sdmmc4_padmux = { - .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask), - .muxmask = sdmmc4_muxmask, -}; - -static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 }; - -static const struct sirfsoc_muxmask cko1_muxmask[] = { - { - .group = 1, - .mask = BIT(10), - }, -}; - -static const struct sirfsoc_padmux cko1_padmux = { - .muxmask_counts = ARRAY_SIZE(cko1_muxmask), - .muxmask = cko1_muxmask, - .funcmask = BIT(3), - .funcval = 0, -}; - -static const unsigned cko1_pins[] = { 42 }; - -static const struct sirfsoc_muxmask i2s_muxmask[] = { - { - .group = 1, - .mask = - BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19) - | BIT(23) | BIT(28), - }, -}; - -static const struct sirfsoc_padmux i2s_padmux = { - .muxmask_counts = ARRAY_SIZE(i2s_muxmask), - .muxmask = i2s_muxmask, - .funcmask = BIT(3) | BIT(9), - .funcval = BIT(3), -}; - -static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 }; - -static const struct sirfsoc_muxmask ac97_muxmask[] = { - { - .group = 1, - .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), - }, -}; - -static const struct sirfsoc_padmux ac97_padmux = { - .muxmask_counts = ARRAY_SIZE(ac97_muxmask), - .muxmask = ac97_muxmask, - .funcmask = BIT(8), - .funcval = 0, -}; - -static const unsigned ac97_pins[] = { 33, 34, 35, 36 }; - -static const struct sirfsoc_muxmask spi1_muxmask[] = { - { - .group = 1, - .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), - }, -}; - -static const struct sirfsoc_padmux spi1_padmux = { - .muxmask_counts = ARRAY_SIZE(spi1_muxmask), - .muxmask = spi1_muxmask, - .funcmask = BIT(8), - .funcval = BIT(8), -}; - -static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; - -static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { - { - .group = 0, - .mask = BIT(27) | BIT(28) | BIT(29), - }, -}; - -static const struct sirfsoc_padmux sdmmc1_padmux = { - .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), - .muxmask = sdmmc1_muxmask, -}; - -static const unsigned sdmmc1_pins[] = { 27, 28, 29 }; - -static const struct sirfsoc_muxmask gps_muxmask[] = { - { - .group = 0, - .mask = BIT(24) | BIT(25) | BIT(26), - }, -}; - -static const struct sirfsoc_padmux gps_padmux = { - .muxmask_counts = ARRAY_SIZE(gps_muxmask), - .muxmask = gps_muxmask, - .funcmask = BIT(12) | BIT(13) | BIT(14), - .funcval = BIT(12), -}; - -static const unsigned gps_pins[] = { 24, 25, 26 }; - -static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { - { - .group = 0, - .mask = BIT(24) | BIT(25) | BIT(26), - }, { - .group = 1, - .mask = BIT(29), - }, { - .group = 2, - .mask = BIT(0) | BIT(1), - }, -}; - -static const struct sirfsoc_padmux sdmmc5_padmux = { - .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), - .muxmask = sdmmc5_muxmask, - .funcmask = BIT(13) | BIT(14), - .funcval = BIT(13) | BIT(14), -}; - -static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 }; - -static const struct sirfsoc_muxmask usp0_muxmask[] = { - { - .group = 1, - .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), - }, -}; - -static const struct sirfsoc_padmux usp0_padmux = { - .muxmask_counts = ARRAY_SIZE(usp0_muxmask), - .muxmask = usp0_muxmask, - .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9), - .funcval = 0, -}; - -static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; - -static const struct sirfsoc_muxmask usp1_muxmask[] = { - { - .group = 1, - .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28), - }, -}; - -static const struct sirfsoc_padmux usp1_padmux = { - .muxmask_counts = ARRAY_SIZE(usp1_muxmask), - .muxmask = usp1_muxmask, - .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11), - .funcval = 0, -}; - -static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 }; - -static const struct sirfsoc_muxmask usp2_muxmask[] = { - { - .group = 1, - .mask = BIT(29) | BIT(30) | BIT(31), - }, { - .group = 2, - .mask = BIT(0) | BIT(1), - }, -}; - -static const struct sirfsoc_padmux usp2_padmux = { - .muxmask_counts = ARRAY_SIZE(usp2_muxmask), - .muxmask = usp2_muxmask, - .funcmask = BIT(13) | BIT(14), - .funcval = 0, -}; - -static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 }; - -static const struct sirfsoc_muxmask nand_muxmask[] = { - { - .group = 2, - .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), - }, -}; - -static const struct sirfsoc_padmux nand_padmux = { - .muxmask_counts = ARRAY_SIZE(nand_muxmask), - .muxmask = nand_muxmask, - .funcmask = BIT(5), - .funcval = 0, -}; - -static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 }; - -static const struct sirfsoc_padmux sdmmc0_padmux = { - .muxmask_counts = 0, - .funcmask = BIT(5), - .funcval = 0, -}; - -static const unsigned sdmmc0_pins[] = { }; - -static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { - { - .group = 2, - .mask = BIT(2) | BIT(3), - }, -}; - -static const struct sirfsoc_padmux sdmmc2_padmux = { - .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), - .muxmask = sdmmc2_muxmask, - .funcmask = BIT(5), - .funcval = BIT(5), -}; - -static const unsigned sdmmc2_pins[] = { 66, 67 }; - -static const struct sirfsoc_muxmask cko0_muxmask[] = { - { - .group = 2, - .mask = BIT(14), - }, -}; - -static const struct sirfsoc_padmux cko0_padmux = { - .muxmask_counts = ARRAY_SIZE(cko0_muxmask), - .muxmask = cko0_muxmask, -}; - -static const unsigned cko0_pins[] = { 78 }; - -static const struct sirfsoc_muxmask vip_muxmask[] = { - { - .group = 2, - .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) - | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | - BIT(25), - }, -}; - -static const struct sirfsoc_padmux vip_padmux = { - .muxmask_counts = ARRAY_SIZE(vip_muxmask), - .muxmask = vip_muxmask, - .funcmask = BIT(0), - .funcval = 0, -}; - -static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; - -static const struct sirfsoc_muxmask i2c0_muxmask[] = { - { - .group = 2, - .mask = BIT(26) | BIT(27), - }, -}; - -static const struct sirfsoc_padmux i2c0_padmux = { - .muxmask_counts = ARRAY_SIZE(i2c0_muxmask), - .muxmask = i2c0_muxmask, -}; - -static const unsigned i2c0_pins[] = { 90, 91 }; - -static const struct sirfsoc_muxmask i2c1_muxmask[] = { - { - .group = 0, - .mask = BIT(13) | BIT(15), - }, -}; - -static const struct sirfsoc_padmux i2c1_padmux = { - .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), - .muxmask = i2c1_muxmask, -}; - -static const unsigned i2c1_pins[] = { 13, 15 }; - -static const struct sirfsoc_muxmask viprom_muxmask[] = { - { - .group = 2, - .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) - | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | - BIT(25), - }, { - .group = 0, - .mask = BIT(12), - }, -}; - -static const struct sirfsoc_padmux viprom_padmux = { - .muxmask_counts = ARRAY_SIZE(viprom_muxmask), - .muxmask = viprom_muxmask, - .funcmask = BIT(0), - .funcval = BIT(0), -}; - -static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; - -static const struct sirfsoc_muxmask pwm0_muxmask[] = { - { - .group = 0, - .mask = BIT(4), - }, -}; - -static const struct sirfsoc_padmux pwm0_padmux = { - .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), - .muxmask = pwm0_muxmask, - .funcmask = BIT(12), - .funcval = 0, -}; - -static const unsigned pwm0_pins[] = { 4 }; - -static const struct sirfsoc_muxmask pwm1_muxmask[] = { - { - .group = 0, - .mask = BIT(5), - }, -}; - -static const struct sirfsoc_padmux pwm1_padmux = { - .muxmask_counts = ARRAY_SIZE(pwm1_muxmask), - .muxmask = pwm1_muxmask, -}; - -static const unsigned pwm1_pins[] = { 5 }; - -static const struct sirfsoc_muxmask pwm2_muxmask[] = { - { - .group = 0, - .mask = BIT(6), - }, -}; - -static const struct sirfsoc_padmux pwm2_padmux = { - .muxmask_counts = ARRAY_SIZE(pwm2_muxmask), - .muxmask = pwm2_muxmask, -}; - -static const unsigned pwm2_pins[] = { 6 }; - -static const struct sirfsoc_muxmask pwm3_muxmask[] = { - { - .group = 0, - .mask = BIT(7), - }, -}; - -static const struct sirfsoc_padmux pwm3_padmux = { - .muxmask_counts = ARRAY_SIZE(pwm3_muxmask), - .muxmask = pwm3_muxmask, -}; - -static const unsigned pwm3_pins[] = { 7 }; - -static const struct sirfsoc_muxmask warm_rst_muxmask[] = { - { - .group = 0, - .mask = BIT(8), - }, -}; - -static const struct sirfsoc_padmux warm_rst_padmux = { - .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), - .muxmask = warm_rst_muxmask, -}; - -static const unsigned warm_rst_pins[] = { 8 }; - -static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = { - { - .group = 1, - .mask = BIT(22), - }, -}; -static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = { - .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask), - .muxmask = usb0_utmi_drvbus_muxmask, - .funcmask = BIT(6), - .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */ -}; - -static const unsigned usb0_utmi_drvbus_pins[] = { 54 }; - -static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { - { - .group = 1, - .mask = BIT(27), - }, -}; - -static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { - .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), - .muxmask = usb1_utmi_drvbus_muxmask, - .funcmask = BIT(11), - .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ -}; - -static const unsigned usb1_utmi_drvbus_pins[] = { 59 }; - -static const struct sirfsoc_muxmask pulse_count_muxmask[] = { - { - .group = 0, - .mask = BIT(9) | BIT(10) | BIT(11), - }, -}; - -static const struct sirfsoc_padmux pulse_count_padmux = { - .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask), - .muxmask = pulse_count_muxmask, -}; - -static const unsigned pulse_count_pins[] = { 9, 10, 11 }; - -#define SIRFSOC_PIN_GROUP(n, p) \ - { \ - .name = n, \ - .pins = p, \ - .num_pins = ARRAY_SIZE(p), \ - } - -static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { - SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), - SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), - SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), - SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), - SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), - SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), - SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), - SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), - SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), - SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), - SIRFSOC_PIN_GROUP("usp2grp", usp2_pins), - SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), - SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), - SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), - SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins), - SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins), - SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins), - SIRFSOC_PIN_GROUP("vipgrp", vip_pins), - SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins), - SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), - SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins), - SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins), - SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), - SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), - SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), - SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins), - SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins), - SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), - SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins), - SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), - SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), - SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), - SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), - SIRFSOC_PIN_GROUP("nandgrp", nand_pins), - SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), - SIRFSOC_PIN_GROUP("spi1grp", spi1_pins), - SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), -}; - -static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(sirfsoc_pin_groups); -} - -static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return sirfsoc_pin_groups[selector].name; -} - -static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - *pins = sirfsoc_pin_groups[selector].pins; - *num_pins = sirfsoc_pin_groups[selector].num_pins; - return 0; -} - -static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, " " DRIVER_NAME); -} - -static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); - struct device_node *np; - struct property *prop; - const char *function, *group; - int ret, index = 0, count = 0; - - /* calculate number of maps required */ - for_each_child_of_node(np_config, np) { - ret = of_property_read_string(np, "sirf,function", &function); - if (ret < 0) - return ret; - - ret = of_property_count_strings(np, "sirf,pins"); - if (ret < 0) - return ret; - - count += ret; - } - - if (!count) { - dev_err(spmx->dev, "No child nodes passed via DT\n"); - return -ENODEV; - } - - *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); - if (!*map) - return -ENOMEM; - - for_each_child_of_node(np_config, np) { - of_property_read_string(np, "sirf,function", &function); - of_property_for_each_string(np, "sirf,pins", prop, group) { - (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[index].data.mux.group = group; - (*map)[index].data.mux.function = function; - index++; - } - } - - *num_maps = count; - - return 0; -} - -static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - kfree(map); -} - -static const struct pinctrl_ops sirfsoc_pctrl_ops = { - .get_groups_count = sirfsoc_get_groups_count, - .get_group_name = sirfsoc_get_group_name, - .get_group_pins = sirfsoc_get_group_pins, - .pin_dbg_show = sirfsoc_pin_dbg_show, - .dt_node_to_map = sirfsoc_dt_node_to_map, - .dt_free_map = sirfsoc_dt_free_map, -}; - -struct sirfsoc_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; - const struct sirfsoc_padmux *padmux; -}; - -static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; -static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; -static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; -static const char * const lcdromgrp[] = { "lcdromgrp" }; -static const char * const uart0grp[] = { "uart0grp" }; -static const char * const uart1grp[] = { "uart1grp" }; -static const char * const uart2grp[] = { "uart2grp" }; -static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; -static const char * const usp0grp[] = { "usp0grp" }; -static const char * const usp1grp[] = { "usp1grp" }; -static const char * const usp2grp[] = { "usp2grp" }; -static const char * const i2c0grp[] = { "i2c0grp" }; -static const char * const i2c1grp[] = { "i2c1grp" }; -static const char * const pwm0grp[] = { "pwm0grp" }; -static const char * const pwm1grp[] = { "pwm1grp" }; -static const char * const pwm2grp[] = { "pwm2grp" }; -static const char * const pwm3grp[] = { "pwm3grp" }; -static const char * const vipgrp[] = { "vipgrp" }; -static const char * const vipromgrp[] = { "vipromgrp" }; -static const char * const warm_rstgrp[] = { "warm_rstgrp" }; -static const char * const cko0grp[] = { "cko0grp" }; -static const char * const cko1grp[] = { "cko1grp" }; -static const char * const sdmmc0grp[] = { "sdmmc0grp" }; -static const char * const sdmmc1grp[] = { "sdmmc1grp" }; -static const char * const sdmmc2grp[] = { "sdmmc2grp" }; -static const char * const sdmmc3grp[] = { "sdmmc3grp" }; -static const char * const sdmmc4grp[] = { "sdmmc4grp" }; -static const char * const sdmmc5grp[] = { "sdmmc5grp" }; -static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; -static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; -static const char * const pulse_countgrp[] = { "pulse_countgrp" }; -static const char * const i2sgrp[] = { "i2sgrp" }; -static const char * const ac97grp[] = { "ac97grp" }; -static const char * const nandgrp[] = { "nandgrp" }; -static const char * const spi0grp[] = { "spi0grp" }; -static const char * const spi1grp[] = { "spi1grp" }; -static const char * const gpsgrp[] = { "gpsgrp" }; - -#define SIRFSOC_PMX_FUNCTION(n, g, m) \ - { \ - .name = n, \ - .groups = g, \ - .num_groups = ARRAY_SIZE(g), \ - .padmux = &m, \ - } - -static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { - SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), - SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), - SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), - SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), - SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), - SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), - SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), - SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), - SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), - SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), - SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux), - SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), - SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), - SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), - SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux), - SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux), - SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux), - SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux), - SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux), - SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux), - SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux), - SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux), - SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux), - SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux), - SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), - SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), - SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux), - SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), - SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), - SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), - SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), - SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), - SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), - SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), - SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), - SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux), - SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), -}; - -static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, - bool enable) -{ - int i; - const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; - const struct sirfsoc_muxmask *mask = mux->muxmask; - - for (i = 0; i < mux->muxmask_counts; i++) { - u32 muxval; - if (!spmx->is_marco) { - muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); - if (enable) - muxval = muxval & ~mask[i].mask; - else - muxval = muxval | mask[i].mask; - writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); - } else { - if (enable) - writel(mask[i].mask, spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group)); - else - writel(mask[i].mask, spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(mask[i].group)); - } - } - - if (mux->funcmask && enable) { - u32 func_en_val; - func_en_val = - readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); - func_en_val = - (func_en_val & ~mux->funcmask) | (mux-> - funcval); - writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); - } -} - -static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, - unsigned group) -{ - struct sirfsoc_pmx *spmx; - - spmx = pinctrl_dev_get_drvdata(pmxdev); - sirfsoc_pinmux_endisable(spmx, selector, true); - - return 0; -} - -static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector, - unsigned group) -{ - struct sirfsoc_pmx *spmx; - - spmx = pinctrl_dev_get_drvdata(pmxdev); - sirfsoc_pinmux_endisable(spmx, selector, false); -} - -static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) -{ - return ARRAY_SIZE(sirfsoc_pmx_functions); -} - -static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return sirfsoc_pmx_functions[selector].name; -} - -static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - *groups = sirfsoc_pmx_functions[selector].groups; - *num_groups = sirfsoc_pmx_functions[selector].num_groups; - return 0; -} - -static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, - struct pinctrl_gpio_range *range, unsigned offset) -{ - struct sirfsoc_pmx *spmx; - - int group = range->id; - - u32 muxval; - - spmx = pinctrl_dev_get_drvdata(pmxdev); - - if (!spmx->is_marco) { - muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); - muxval = muxval | (1 << (offset - range->pin_base)); - writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); - } else { - writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(group)); - } - - return 0; -} - -static const struct pinmux_ops sirfsoc_pinmux_ops = { - .enable = sirfsoc_pinmux_enable, - .disable = sirfsoc_pinmux_disable, - .get_functions_count = sirfsoc_pinmux_get_funcs_count, - .get_function_name = sirfsoc_pinmux_get_func_name, - .get_function_groups = sirfsoc_pinmux_get_groups, - .gpio_request_enable = sirfsoc_pinmux_request_gpio, -}; - -static struct pinctrl_desc sirfsoc_pinmux_desc = { - .name = DRIVER_NAME, - .pins = sirfsoc_pads, - .npins = ARRAY_SIZE(sirfsoc_pads), - .pctlops = &sirfsoc_pctrl_ops, - .pmxops = &sirfsoc_pinmux_ops, - .owner = THIS_MODULE, -}; - -/* - * Todo: bind irq_chip to every pinctrl_gpio_range - */ -static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = { - { - .name = "sirfsoc-gpio*", - .id = 0, - .base = 0, - .pin_base = 0, - .npins = 32, - }, { - .name = "sirfsoc-gpio*", - .id = 1, - .base = 32, - .pin_base = 32, - .npins = 32, - }, { - .name = "sirfsoc-gpio*", - .id = 2, - .base = 64, - .pin_base = 64, - .npins = 32, - }, { - .name = "sirfsoc-gpio*", - .id = 3, - .base = 96, - .pin_base = 96, - .npins = 19, - }, -}; - -static void __iomem *sirfsoc_rsc_of_iomap(void) -{ - const struct of_device_id rsc_ids[] = { - { .compatible = "sirf,prima2-rsc" }, - { .compatible = "sirf,marco-rsc" }, - {} - }; - struct device_node *np; - - np = of_find_matching_node(NULL, rsc_ids); - if (!np) - panic("unable to find compatible rsc node in dtb\n"); - - return of_iomap(np, 0); -} - -static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, - const struct of_phandle_args *gpiospec, - u32 *flags) -{ - if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) - return -EINVAL; - - if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc) - return -EINVAL; - - if (flags) - *flags = gpiospec->args[1]; - - return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE; -} - -static int sirfsoc_pinmux_probe(struct platform_device *pdev) -{ - int ret; - struct sirfsoc_pmx *spmx; - struct device_node *np = pdev->dev.of_node; - int i; - - /* Create state holders etc for this driver */ - spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); - if (!spmx) - return -ENOMEM; - - spmx->dev = &pdev->dev; - - platform_set_drvdata(pdev, spmx); - - spmx->gpio_virtbase = of_iomap(np, 0); - if (!spmx->gpio_virtbase) { - ret = -ENOMEM; - dev_err(&pdev->dev, "can't map gpio registers\n"); - goto out_no_gpio_remap; - } - - spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); - if (!spmx->rsc_virtbase) { - ret = -ENOMEM; - dev_err(&pdev->dev, "can't map rsc registers\n"); - goto out_no_rsc_remap; - } - - if (of_device_is_compatible(np, "sirf,marco-pinctrl")) - spmx->is_marco = 1; - - /* Now register the pin controller and all pins it handles */ - spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); - if (!spmx->pmx) { - dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); - ret = -EINVAL; - goto out_no_pmx; - } - - for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) { - sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc; - pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]); - } - - dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); - - return 0; - -out_no_pmx: - iounmap(spmx->rsc_virtbase); -out_no_rsc_remap: - iounmap(spmx->gpio_virtbase); -out_no_gpio_remap: - platform_set_drvdata(pdev, NULL); - return ret; -} - -static const struct of_device_id pinmux_ids[] = { - { .compatible = "sirf,prima2-pinctrl" }, - { .compatible = "sirf,marco-pinctrl" }, - {} -}; - -static struct platform_driver sirfsoc_pinmux_driver = { - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - .of_match_table = pinmux_ids, - }, - .probe = sirfsoc_pinmux_probe, -}; - -static int __init sirfsoc_pinmux_init(void) -{ - return platform_driver_register(&sirfsoc_pinmux_driver); -} -arch_initcall(sirfsoc_pinmux_init); - -static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), - struct sirfsoc_gpio_bank, chip); - - return irq_find_mapping(bank->domain, offset); -} - -static inline int sirfsoc_gpio_to_offset(unsigned int gpio) -{ - return gpio % SIRFSOC_GPIO_BANK_SIZE; -} - -static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio) -{ - return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE]; -} - -static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip) -{ - return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip); -} - -static void sirfsoc_gpio_irq_ack(struct irq_data *d) -{ - struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); - int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; - u32 val, offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - val = readl(bank->chip.regs + offset); - - writel(val, bank->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio_lock, flags); -} - -static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx) -{ - u32 val, offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - val = readl(bank->chip.regs + offset); - val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; - val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; - writel(val, bank->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio_lock, flags); -} - -static void sirfsoc_gpio_irq_mask(struct irq_data *d) -{ - struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); - - __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); -} - -static void sirfsoc_gpio_irq_unmask(struct irq_data *d) -{ - struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); - int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; - u32 val, offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - val = readl(bank->chip.regs + offset); - val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; - val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; - writel(val, bank->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio_lock, flags); -} - -static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) -{ - struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); - int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; - u32 val, offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - val = readl(bank->chip.regs + offset); - val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; - - switch (type) { - case IRQ_TYPE_NONE: - break; - case IRQ_TYPE_EDGE_RISING: - val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; - val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; - break; - case IRQ_TYPE_EDGE_FALLING: - val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; - val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; - break; - case IRQ_TYPE_EDGE_BOTH: - val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | - SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; - break; - case IRQ_TYPE_LEVEL_LOW: - val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); - val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; - break; - case IRQ_TYPE_LEVEL_HIGH: - val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; - val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); - break; - } - - writel(val, bank->chip.regs + offset); - - spin_unlock_irqrestore(&sgpio_lock, flags); - - return 0; -} - -static struct irq_chip sirfsoc_irq_chip = { - .name = "sirf-gpio-irq", - .irq_ack = sirfsoc_gpio_irq_ack, - .irq_mask = sirfsoc_gpio_irq_mask, - .irq_unmask = sirfsoc_gpio_irq_unmask, - .irq_set_type = sirfsoc_gpio_irq_type, -}; - -static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) -{ - struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq); - u32 status, ctrl; - int idx = 0; - unsigned int first_irq; - struct irq_chip *chip = irq_get_chip(irq); - - chained_irq_enter(chip, desc); - - status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); - if (!status) { - printk(KERN_WARNING - "%s: gpio id %d status %#x no interrupt is flaged\n", - __func__, bank->id, status); - handle_bad_irq(irq, desc); - return; - } - - first_irq = bank->domain->revmap_data.legacy.first_irq; - - while (status) { - ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); - - /* - * Here we must check whether the corresponding GPIO's interrupt - * has been enabled, otherwise just skip it - */ - if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { - pr_debug("%s: gpio id %d idx %d happens\n", - __func__, bank->id, idx); - generic_handle_irq(first_irq + idx); - } - - idx++; - status = status >> 1; - } - - chained_irq_exit(chip, desc); -} - -static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset) -{ - u32 val; - - val = readl(bank->chip.regs + ctrl_offset); - val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; - writel(val, bank->chip.regs + ctrl_offset); -} - -static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - unsigned long flags; - - if (pinctrl_request_gpio(chip->base + offset)) - return -ENODEV; - - spin_lock_irqsave(&bank->lock, flags); - - /* - * default status: - * set direction as input and mask irq - */ - sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); - __sirfsoc_gpio_irq_mask(bank, offset); - - spin_unlock_irqrestore(&bank->lock, flags); - - return 0; -} - -static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - __sirfsoc_gpio_irq_mask(bank, offset); - sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); - - spin_unlock_irqrestore(&bank->lock, flags); - - pinctrl_free_gpio(chip->base + offset); -} - -static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - int idx = sirfsoc_gpio_to_offset(gpio); - unsigned long flags; - unsigned offset; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&bank->lock, flags); - - sirfsoc_gpio_set_input(bank, offset); - - spin_unlock_irqrestore(&bank->lock, flags); - - return 0; -} - -static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset, - int value) -{ - u32 out_ctrl; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - out_ctrl = readl(bank->chip.regs + offset); - if (value) - out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; - else - out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; - - out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; - out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; - writel(out_ctrl, bank->chip.regs + offset); - - spin_unlock_irqrestore(&bank->lock, flags); -} - -static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - int idx = sirfsoc_gpio_to_offset(gpio); - u32 offset; - unsigned long flags; - - offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - - spin_lock_irqsave(&sgpio_lock, flags); - - sirfsoc_gpio_set_output(bank, offset, value); - - spin_unlock_irqrestore(&sgpio_lock, flags); - - return 0; -} - -static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - u32 val; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); - - spin_unlock_irqrestore(&bank->lock, flags); - - return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); -} - -static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, - int value) -{ - struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); - u32 ctrl; - unsigned long flags; - - spin_lock_irqsave(&bank->lock, flags); - - ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); - if (value) - ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; - else - ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; - writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); - - spin_unlock_irqrestore(&bank->lock, flags); -} - -static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - struct sirfsoc_gpio_bank *bank = d->host_data; - - if (!bank) - return -EINVAL; - - irq_set_chip(irq, &sirfsoc_irq_chip); - irq_set_handler(irq, handle_level_irq); - irq_set_chip_data(irq, bank); - set_irq_flags(irq, IRQF_VALID); - - return 0; -} - -const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = { - .map = sirfsoc_gpio_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static void sirfsoc_gpio_set_pullup(const u32 *pullups) -{ - int i, n; - const unsigned long *p = (const unsigned long *)pullups; - - for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { - for_each_set_bit(n, p + i, BITS_PER_LONG) { - u32 offset = SIRFSOC_GPIO_CTRL(i, n); - u32 val = readl(sgpio_bank[i].chip.regs + offset); - val |= SIRFSOC_GPIO_CTL_PULL_MASK; - val |= SIRFSOC_GPIO_CTL_PULL_HIGH; - writel(val, sgpio_bank[i].chip.regs + offset); - } - } -} - -static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns) -{ - int i, n; - const unsigned long *p = (const unsigned long *)pulldowns; - - for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { - for_each_set_bit(n, p + i, BITS_PER_LONG) { - u32 offset = SIRFSOC_GPIO_CTRL(i, n); - u32 val = readl(sgpio_bank[i].chip.regs + offset); - val |= SIRFSOC_GPIO_CTL_PULL_MASK; - val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; - writel(val, sgpio_bank[i].chip.regs + offset); - } - } -} - -static int sirfsoc_gpio_probe(struct device_node *np) -{ - int i, err = 0; - struct sirfsoc_gpio_bank *bank; - void *regs; - struct platform_device *pdev; - bool is_marco = false; - - u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; - - pdev = of_find_device_by_node(np); - if (!pdev) - return -ENODEV; - - regs = of_iomap(np, 0); - if (!regs) - return -ENOMEM; - - if (of_device_is_compatible(np, "sirf,marco-pinctrl")) - is_marco = 1; - - for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { - bank = &sgpio_bank[i]; - spin_lock_init(&bank->lock); - bank->chip.gc.request = sirfsoc_gpio_request; - bank->chip.gc.free = sirfsoc_gpio_free; - bank->chip.gc.direction_input = sirfsoc_gpio_direction_input; - bank->chip.gc.get = sirfsoc_gpio_get_value; - bank->chip.gc.direction_output = sirfsoc_gpio_direction_output; - bank->chip.gc.set = sirfsoc_gpio_set_value; - bank->chip.gc.to_irq = sirfsoc_gpio_to_irq; - bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE; - bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE; - bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); - bank->chip.gc.of_node = np; - bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; - bank->chip.gc.of_gpio_n_cells = 2; - bank->chip.regs = regs; - bank->id = i; - bank->is_marco = is_marco; - bank->parent_irq = platform_get_irq(pdev, i); - if (bank->parent_irq < 0) { - err = bank->parent_irq; - goto out; - } - - err = gpiochip_add(&bank->chip.gc); - if (err) { - pr_err("%s: error in probe function with status %d\n", - np->full_name, err); - goto out; - } - - bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE, - SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0, - &sirfsoc_gpio_irq_simple_ops, bank); - - if (!bank->domain) { - pr_err("%s: Failed to create irqdomain\n", np->full_name); - err = -ENOSYS; - goto out; - } - - irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq); - irq_set_handler_data(bank->parent_irq, bank); - } - - if (!of_property_read_u32_array(np, "sirf,pullups", pullups, - SIRFSOC_GPIO_NO_OF_BANKS)) - sirfsoc_gpio_set_pullup(pullups); - - if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, - SIRFSOC_GPIO_NO_OF_BANKS)) - sirfsoc_gpio_set_pulldown(pulldowns); - - return 0; - -out: - iounmap(regs); - return err; -} - -static int __init sirfsoc_gpio_init(void) -{ - - struct device_node *np; - - np = of_find_matching_node(NULL, pinmux_ids); - - if (!np) - return -ENODEV; - - return sirfsoc_gpio_probe(np); -} -subsys_initcall(sirfsoc_gpio_init); - -MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " - "Yuping Luo <yuping.luo@csr.com>, " - "Barry Song <baohua.song@csr.com>"); -MODULE_DESCRIPTION("SIRFSOC pin control driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c new file mode 100644 index 00000000000..9f43916637c --- /dev/null +++ b/drivers/pinctrl/pinctrl-st.c @@ -0,0 +1,1708 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Authors: + * Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_gpio.h> +#include <linux/of_address.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/platform_device.h> +#include "core.h" + +/* PIO Block registers */ +/* PIO output */ +#define REG_PIO_POUT 0x00 +/* Set bits of POUT */ +#define REG_PIO_SET_POUT 0x04 +/* Clear bits of POUT */ +#define REG_PIO_CLR_POUT 0x08 +/* PIO input */ +#define REG_PIO_PIN 0x10 +/* PIO configuration */ +#define REG_PIO_PC(n) (0x20 + (n) * 0x10) +/* Set bits of PC[2:0] */ +#define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) +/* Clear bits of PC[2:0] */ +#define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) +/* PIO input comparison */ +#define REG_PIO_PCOMP 0x50 +/* Set bits of PCOMP */ +#define REG_PIO_SET_PCOMP 0x54 +/* Clear bits of PCOMP */ +#define REG_PIO_CLR_PCOMP 0x58 +/* PIO input comparison mask */ +#define REG_PIO_PMASK 0x60 +/* Set bits of PMASK */ +#define REG_PIO_SET_PMASK 0x64 +/* Clear bits of PMASK */ +#define REG_PIO_CLR_PMASK 0x68 + +#define ST_GPIO_DIRECTION_BIDIR 0x1 +#define ST_GPIO_DIRECTION_OUT 0x2 +#define ST_GPIO_DIRECTION_IN 0x4 + +/** + * Packed style retime configuration. + * There are two registers cfg0 and cfg1 in this style for each bank. + * Each field in this register is 8 bit corresponding to 8 pins in the bank. + */ +#define RT_P_CFGS_PER_BANK 2 +#define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) +#define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) +#define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) +#define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) +#define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) +#define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) +#define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) + +/** + * Dedicated style retime Configuration register + * each register is dedicated per pin. + */ +#define RT_D_CFGS_PER_BANK 8 +#define RT_D_CFG_CLK_SHIFT 0 +#define RT_D_CFG_CLK_MASK (0x3 << 0) +#define RT_D_CFG_CLKNOTDATA_SHIFT 2 +#define RT_D_CFG_CLKNOTDATA_MASK BIT(2) +#define RT_D_CFG_DELAY_SHIFT 3 +#define RT_D_CFG_DELAY_MASK (0xf << 3) +#define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 +#define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) +#define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 +#define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) +#define RT_D_CFG_INVERTCLK_SHIFT 9 +#define RT_D_CFG_INVERTCLK_MASK BIT(9) +#define RT_D_CFG_RETIME_SHIFT 10 +#define RT_D_CFG_RETIME_MASK BIT(10) + +/* + * Pinconf is represented in an opaque unsigned long variable. + * Below is the bit allocation details for each possible configuration. + * All the bit fields can be encapsulated into four variables + * (direction, retime-type, retime-clk, retime-delay) + * + * +----------------+ + *[31:28]| reserved-3 | + * +----------------+------------- + *[27] | oe | | + * +----------------+ v + *[26] | pu | [Direction ] + * +----------------+ ^ + *[25] | od | | + * +----------------+------------- + *[24] | reserved-2 | + * +----------------+------------- + *[23] | retime | | + * +----------------+ | + *[22] | retime-invclk | | + * +----------------+ v + *[21] |retime-clknotdat| [Retime-type ] + * +----------------+ ^ + *[20] | retime-de | | + * +----------------+------------- + *[19:18]| retime-clk |------>[Retime-Clk ] + * +----------------+ + *[17:16]| reserved-1 | + * +----------------+ + *[15..0]| retime-delay |------>[Retime Delay] + * +----------------+ + */ + +#define ST_PINCONF_UNPACK(conf, param)\ + ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ + & ST_PINCONF_ ##param ##_MASK) + +#define ST_PINCONF_PACK(conf, val, param) (conf |=\ + ((val & ST_PINCONF_ ##param ##_MASK) << \ + ST_PINCONF_ ##param ##_SHIFT)) + +/* Output enable */ +#define ST_PINCONF_OE_MASK 0x1 +#define ST_PINCONF_OE_SHIFT 27 +#define ST_PINCONF_OE BIT(27) +#define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) +#define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) + +/* Pull Up */ +#define ST_PINCONF_PU_MASK 0x1 +#define ST_PINCONF_PU_SHIFT 26 +#define ST_PINCONF_PU BIT(26) +#define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) +#define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) + +/* Open Drain */ +#define ST_PINCONF_OD_MASK 0x1 +#define ST_PINCONF_OD_SHIFT 25 +#define ST_PINCONF_OD BIT(25) +#define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) +#define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) + +#define ST_PINCONF_RT_MASK 0x1 +#define ST_PINCONF_RT_SHIFT 23 +#define ST_PINCONF_RT BIT(23) +#define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) +#define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) + +#define ST_PINCONF_RT_INVERTCLK_MASK 0x1 +#define ST_PINCONF_RT_INVERTCLK_SHIFT 22 +#define ST_PINCONF_RT_INVERTCLK BIT(22) +#define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ + ST_PINCONF_UNPACK(conf, RT_INVERTCLK) +#define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ + ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) + +#define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 +#define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 +#define ST_PINCONF_RT_CLKNOTDATA BIT(21) +#define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ + ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) +#define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ + ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) + +#define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 +#define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 +#define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) +#define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ + ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) +#define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ + ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) + +#define ST_PINCONF_RT_CLK_MASK 0x3 +#define ST_PINCONF_RT_CLK_SHIFT 18 +#define ST_PINCONF_RT_CLK BIT(18) +#define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) +#define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) + +/* RETIME_DELAY in Pico Secs */ +#define ST_PINCONF_RT_DELAY_MASK 0xffff +#define ST_PINCONF_RT_DELAY_SHIFT 0 +#define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) +#define ST_PINCONF_PACK_RT_DELAY(conf, val) \ + ST_PINCONF_PACK(conf, val, RT_DELAY) + +#define ST_GPIO_PINS_PER_BANK (8) +#define OF_GPIO_ARGS_MIN (4) +#define OF_RT_ARGS_MIN (2) + +#define gpio_range_to_bank(chip) \ + container_of(chip, struct st_gpio_bank, range) + +#define gpio_chip_to_bank(chip) \ + container_of(chip, struct st_gpio_bank, gpio_chip) + + +enum st_retime_style { + st_retime_style_none, + st_retime_style_packed, + st_retime_style_dedicated, +}; + +struct st_retime_dedicated { + struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; +}; + +struct st_retime_packed { + struct regmap_field *clk1notclk0; + struct regmap_field *delay_0; + struct regmap_field *delay_1; + struct regmap_field *invertclk; + struct regmap_field *retime; + struct regmap_field *clknotdata; + struct regmap_field *double_edge; +}; + +struct st_pio_control { + u32 rt_pin_mask; + struct regmap_field *alt, *oe, *pu, *od; + /* retiming */ + union { + struct st_retime_packed rt_p; + struct st_retime_dedicated rt_d; + } rt; +}; + +struct st_pctl_data { + const enum st_retime_style rt_style; + const unsigned int *input_delays; + const int ninput_delays; + const unsigned int *output_delays; + const int noutput_delays; + /* register offset information */ + const int alt, oe, pu, od, rt; +}; + +struct st_pinconf { + int pin; + const char *name; + unsigned long config; + int altfunc; +}; + +struct st_pmx_func { + const char *name; + const char **groups; + unsigned ngroups; +}; + +struct st_pctl_group { + const char *name; + unsigned int *pins; + unsigned npins; + struct st_pinconf *pin_conf; +}; + +/* + * Edge triggers are not supported at hardware level, it is supported by + * software by exploiting the level trigger support in hardware. + * Software uses a virtual register (EDGE_CONF) for edge trigger configuration + * of each gpio pin in a GPIO bank. + * + * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of + * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. + * + * bit allocation per pin is: + * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] + * -------------------------------------------------------- + * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | + * -------------------------------------------------------- + * + * A pin can have one of following the values in its edge configuration field. + * + * ------- ---------------------------- + * [0-3] - Description + * ------- ---------------------------- + * 0000 - No edge IRQ. + * 0001 - Falling edge IRQ. + * 0010 - Rising edge IRQ. + * 0011 - Rising and Falling edge IRQ. + * ------- ---------------------------- + */ + +#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 +#define ST_IRQ_EDGE_MASK 0xf +#define ST_IRQ_EDGE_FALLING BIT(0) +#define ST_IRQ_EDGE_RISING BIT(1) +#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) + +#define ST_IRQ_RISING_EDGE_CONF(pin) \ + (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) + +#define ST_IRQ_FALLING_EDGE_CONF(pin) \ + (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) + +#define ST_IRQ_BOTH_EDGE_CONF(pin) \ + (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) + +#define ST_IRQ_EDGE_CONF(conf, pin) \ + (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) + +struct st_gpio_bank { + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range range; + void __iomem *base; + struct st_pio_control pc; + unsigned long irq_edge_conf; + spinlock_t lock; +}; + +struct st_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + struct st_gpio_bank *banks; + int nbanks; + struct st_pmx_func *functions; + int nfunctions; + struct st_pctl_group *groups; + int ngroups; + struct regmap *regmap; + const struct st_pctl_data *data; + void __iomem *irqmux_base; +}; + +/* SOC specific data */ +/* STiH415 data */ +static const unsigned int stih415_input_delays[] = {0, 500, 1000, 1500}; +static const unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000}; + +#define STIH415_PCTRL_COMMON_DATA \ + .rt_style = st_retime_style_packed, \ + .input_delays = stih415_input_delays, \ + .ninput_delays = ARRAY_SIZE(stih415_input_delays), \ + .output_delays = stih415_output_delays, \ + .noutput_delays = ARRAY_SIZE(stih415_output_delays) + +static const struct st_pctl_data stih415_sbc_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 16, +}; + +static const struct st_pctl_data stih415_front_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 16, +}; + +static const struct st_pctl_data stih415_rear_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 6, .pu = 8, .od = 10, .rt = 38, +}; + +static const struct st_pctl_data stih415_left_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 3, .pu = 4, .od = 5, .rt = 6, +}; + +static const struct st_pctl_data stih415_right_data = { + STIH415_PCTRL_COMMON_DATA, + .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 11, +}; + +/* STiH416 data */ +static const unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, + 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; + +static const struct st_pctl_data stih416_data = { + .rt_style = st_retime_style_dedicated, + .input_delays = stih416_delays, + .ninput_delays = ARRAY_SIZE(stih416_delays), + .output_delays = stih416_delays, + .noutput_delays = ARRAY_SIZE(stih416_delays), + .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, +}; + +static const struct st_pctl_data stih407_flashdata = { + .rt_style = st_retime_style_none, + .input_delays = stih416_delays, + .ninput_delays = ARRAY_SIZE(stih416_delays), + .output_delays = stih416_delays, + .noutput_delays = ARRAY_SIZE(stih416_delays), + .alt = 0, + .oe = -1, /* Not Available */ + .pu = -1, /* Not Available */ + .od = 60, + .rt = 100, +}; + +/* Low level functions.. */ +static inline int st_gpio_bank(int gpio) +{ + return gpio/ST_GPIO_PINS_PER_BANK; +} + +static inline int st_gpio_pin(int gpio) +{ + return gpio%ST_GPIO_PINS_PER_BANK; +} + +static void st_pinconf_set_config(struct st_pio_control *pc, + int pin, unsigned long config) +{ + struct regmap_field *output_enable = pc->oe; + struct regmap_field *pull_up = pc->pu; + struct regmap_field *open_drain = pc->od; + unsigned int oe_value, pu_value, od_value; + unsigned long mask = BIT(pin); + + if (output_enable) { + regmap_field_read(output_enable, &oe_value); + oe_value &= ~mask; + if (config & ST_PINCONF_OE) + oe_value |= mask; + regmap_field_write(output_enable, oe_value); + } + + if (pull_up) { + regmap_field_read(pull_up, &pu_value); + pu_value &= ~mask; + if (config & ST_PINCONF_PU) + pu_value |= mask; + regmap_field_write(pull_up, pu_value); + } + + if (open_drain) { + regmap_field_read(open_drain, &od_value); + od_value &= ~mask; + if (config & ST_PINCONF_OD) + od_value |= mask; + regmap_field_write(open_drain, od_value); + } +} + +static void st_pctl_set_function(struct st_pio_control *pc, + int pin_id, int function) +{ + struct regmap_field *alt = pc->alt; + unsigned int val; + int pin = st_gpio_pin(pin_id); + int offset = pin * 4; + + if (!alt) + return; + + regmap_field_read(alt, &val); + val &= ~(0xf << offset); + val |= function << offset; + regmap_field_write(alt, val); +} + +static unsigned long st_pinconf_delay_to_bit(unsigned int delay, + const struct st_pctl_data *data, unsigned long config) +{ + const unsigned int *delay_times; + int num_delay_times, i, closest_index = -1; + unsigned int closest_divergence = UINT_MAX; + + if (ST_PINCONF_UNPACK_OE(config)) { + delay_times = data->output_delays; + num_delay_times = data->noutput_delays; + } else { + delay_times = data->input_delays; + num_delay_times = data->ninput_delays; + } + + for (i = 0; i < num_delay_times; i++) { + unsigned int divergence = abs(delay - delay_times[i]); + + if (divergence == 0) + return i; + + if (divergence < closest_divergence) { + closest_divergence = divergence; + closest_index = i; + } + } + + pr_warn("Attempt to set delay %d, closest available %d\n", + delay, delay_times[closest_index]); + + return closest_index; +} + +static unsigned long st_pinconf_bit_to_delay(unsigned int index, + const struct st_pctl_data *data, unsigned long output) +{ + const unsigned int *delay_times; + int num_delay_times; + + if (output) { + delay_times = data->output_delays; + num_delay_times = data->noutput_delays; + } else { + delay_times = data->input_delays; + num_delay_times = data->ninput_delays; + } + + if (index < num_delay_times) { + return delay_times[index]; + } else { + pr_warn("Delay not found in/out delay list\n"); + return 0; + } +} + +static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, + int enable, int pin) +{ + unsigned int val = 0; + + regmap_field_read(field, &val); + if (enable) + val |= BIT(pin); + else + val &= ~BIT(pin); + regmap_field_write(field, val); +} + +static void st_pinconf_set_retime_packed(struct st_pinctrl *info, + struct st_pio_control *pc, unsigned long config, int pin) +{ + const struct st_pctl_data *data = info->data; + struct st_retime_packed *rt_p = &pc->rt.rt_p; + unsigned int delay; + + st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, + ST_PINCONF_UNPACK_RT_CLK(config), pin); + + st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, + ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); + + st_regmap_field_bit_set_clear_pin(rt_p->double_edge, + ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); + + st_regmap_field_bit_set_clear_pin(rt_p->invertclk, + ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); + + st_regmap_field_bit_set_clear_pin(rt_p->retime, + ST_PINCONF_UNPACK_RT(config), pin); + + delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), + data, config); + /* 2 bit delay, lsb */ + st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); + /* 2 bit delay, msb */ + st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); + +} + +static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, + struct st_pio_control *pc, unsigned long config, int pin) +{ + int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; + int clk = ST_PINCONF_UNPACK_RT_CLK(config); + int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); + int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); + int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); + int retime = ST_PINCONF_UNPACK_RT(config); + + unsigned long delay = st_pinconf_delay_to_bit( + ST_PINCONF_UNPACK_RT_DELAY(config), + info->data, config); + struct st_retime_dedicated *rt_d = &pc->rt.rt_d; + + unsigned long retime_config = + ((clk) << RT_D_CFG_CLK_SHIFT) | + ((delay) << RT_D_CFG_DELAY_SHIFT) | + ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | + ((retime) << RT_D_CFG_RETIME_SHIFT) | + ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | + ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | + ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); + + regmap_field_write(rt_d->rt[pin], retime_config); +} + +static void st_pinconf_get_direction(struct st_pio_control *pc, + int pin, unsigned long *config) +{ + unsigned int oe_value, pu_value, od_value; + + if (pc->oe) { + regmap_field_read(pc->oe, &oe_value); + if (oe_value & BIT(pin)) + ST_PINCONF_PACK_OE(*config); + } + + if (pc->pu) { + regmap_field_read(pc->pu, &pu_value); + if (pu_value & BIT(pin)) + ST_PINCONF_PACK_PU(*config); + } + + if (pc->od) { + regmap_field_read(pc->od, &od_value); + if (od_value & BIT(pin)) + ST_PINCONF_PACK_OD(*config); + } +} + +static int st_pinconf_get_retime_packed(struct st_pinctrl *info, + struct st_pio_control *pc, int pin, unsigned long *config) +{ + const struct st_pctl_data *data = info->data; + struct st_retime_packed *rt_p = &pc->rt.rt_p; + unsigned int delay_bits, delay, delay0, delay1, val; + int output = ST_PINCONF_UNPACK_OE(*config); + + if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT(*config); + + if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT_CLK(*config, 1); + + if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT_CLKNOTDATA(*config); + + if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); + + if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) + ST_PINCONF_PACK_RT_INVERTCLK(*config); + + regmap_field_read(rt_p->delay_0, &delay0); + regmap_field_read(rt_p->delay_1, &delay1); + delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | + (((delay0 & BIT(pin)) ? 1 : 0)); + delay = st_pinconf_bit_to_delay(delay_bits, data, output); + ST_PINCONF_PACK_RT_DELAY(*config, delay); + + return 0; +} + +static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, + struct st_pio_control *pc, int pin, unsigned long *config) +{ + unsigned int value; + unsigned long delay_bits, delay, rt_clk; + int output = ST_PINCONF_UNPACK_OE(*config); + struct st_retime_dedicated *rt_d = &pc->rt.rt_d; + + regmap_field_read(rt_d->rt[pin], &value); + + rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; + ST_PINCONF_PACK_RT_CLK(*config, rt_clk); + + delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; + delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); + ST_PINCONF_PACK_RT_DELAY(*config, delay); + + if (value & RT_D_CFG_CLKNOTDATA_MASK) + ST_PINCONF_PACK_RT_CLKNOTDATA(*config); + + if (value & RT_D_CFG_DOUBLE_EDGE_MASK) + ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); + + if (value & RT_D_CFG_INVERTCLK_MASK) + ST_PINCONF_PACK_RT_INVERTCLK(*config); + + if (value & RT_D_CFG_RETIME_MASK) + ST_PINCONF_PACK_RT(*config); + + return 0; +} + +/* GPIO related functions */ + +static inline void __st_gpio_set(struct st_gpio_bank *bank, + unsigned offset, int value) +{ + if (value) + writel(BIT(offset), bank->base + REG_PIO_SET_POUT); + else + writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); +} + +static void st_gpio_direction(struct st_gpio_bank *bank, + unsigned int gpio, unsigned int direction) +{ + int offset = st_gpio_pin(gpio); + int i = 0; + /** + * There are three configuration registers (PIOn_PC0, PIOn_PC1 + * and PIOn_PC2) for each port. These are used to configure the + * PIO port pins. Each pin can be configured as an input, output, + * bidirectional, or alternative function pin. Three bits, one bit + * from each of the three registers, configure the corresponding bit of + * the port. Valid bit settings is: + * + * PC2 PC1 PC0 Direction. + * 0 0 0 [Input Weak pull-up] + * 0 0 or 1 1 [Bidirection] + * 0 1 0 [Output] + * 1 0 0 [Input] + * + * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits + * individually. + */ + for (i = 0; i <= 2; i++) { + if (direction & BIT(i)) + writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); + else + writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); + } +} + +static int st_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void st_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int st_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct st_gpio_bank *bank = gpio_chip_to_bank(chip); + + return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); +} + +static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct st_gpio_bank *bank = gpio_chip_to_bank(chip); + __st_gpio_set(bank, offset, value); +} + +static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_gpio_direction_input(chip->base + offset); + + return 0; +} + +static int st_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct st_gpio_bank *bank = gpio_chip_to_bank(chip); + + __st_gpio_set(bank, offset, value); + pinctrl_gpio_direction_output(chip->base + offset); + + return 0; +} + +static int st_gpio_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, u32 *flags) +{ + if (WARN_ON(gc->of_gpio_n_cells < 1)) + return -EINVAL; + + if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) + return -EINVAL; + + if (gpiospec->args[0] > gc->ngpio) + return -EINVAL; + + return gpiospec->args[0]; +} + +/* Pinctrl Groups */ +static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->ngroups; +} + +static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->groups[selector].name; +} + +static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, const unsigned **pins, unsigned *npins) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pins; + *npins = info->groups[selector].npins; + + return 0; +} + +static const inline struct st_pctl_group *st_pctl_find_group_by_name( + const struct st_pinctrl *info, const char *name) +{ + int i; + + for (i = 0; i < info->ngroups; i++) { + if (!strcmp(info->groups[i].name, name)) + return &info->groups[i]; + } + + return NULL; +} + +static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const struct st_pctl_group *grp; + struct pinctrl_map *new_map; + struct device_node *parent; + int map_num, i; + + grp = st_pctl_find_group_by_name(info, np->name); + if (!grp) { + dev_err(info->dev, "unable to find group for node %s\n", + np->name); + return -EINVAL; + } + + map_num = grp->npins + 1; + new_map = devm_kzalloc(pctldev->dev, + sizeof(*new_map) * map_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + parent = of_get_parent(np); + if (!parent) { + devm_kfree(pctldev->dev, new_map); + return -EINVAL; + } + + *map = new_map; + *num_maps = map_num; + new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; + new_map[0].data.mux.function = parent->name; + new_map[0].data.mux.group = np->name; + of_node_put(parent); + + /* create config map per pin */ + new_map++; + for (i = 0; i < grp->npins; i++) { + new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[i].data.configs.group_or_pin = + pin_get_name(pctldev, grp->pins[i]); + new_map[i].data.configs.configs = &grp->pin_conf[i].config; + new_map[i].data.configs.num_configs = 1; + } + dev_info(pctldev->dev, "maps: function %s group %s num %d\n", + (*map)->data.mux.function, grp->name, map_num); + + return 0; +} + +static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ +} + +static struct pinctrl_ops st_pctlops = { + .get_groups_count = st_pctl_get_groups_count, + .get_group_pins = st_pctl_get_group_pins, + .get_group_name = st_pctl_get_group_name, + .dt_node_to_map = st_pctl_dt_node_to_map, + .dt_free_map = st_pctl_dt_free_map, +}; + +/* Pinmux */ +static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->nfunctions; +} + +static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->functions[selector].name; +} + +static int st_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, const char * const **grps, unsigned * const ngrps) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + *grps = info->functions[selector].groups; + *ngrps = info->functions[selector].ngroups; + + return 0; +} + +static struct st_pio_control *st_get_pio_control( + struct pinctrl_dev *pctldev, int pin) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(pctldev, pin); + struct st_gpio_bank *bank = gpio_range_to_bank(range); + + return &bank->pc; +} + +static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector, + unsigned group) +{ + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct st_pinconf *conf = info->groups[group].pin_conf; + struct st_pio_control *pc; + int i; + + for (i = 0; i < info->groups[group].npins; i++) { + pc = st_get_pio_control(pctldev, conf[i].pin); + st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); + } + + return 0; +} + +static void st_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ +} + +static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned gpio, + bool input) +{ + struct st_gpio_bank *bank = gpio_range_to_bank(range); + /* + * When a PIO bank is used in its primary function mode (altfunc = 0) + * Output Enable (OE), Open Drain(OD), and Pull Up (PU) + * for the primary PIO functions are driven by the related PIO block + */ + st_pctl_set_function(&bank->pc, gpio, 0); + st_gpio_direction(bank, gpio, input ? + ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); + + return 0; +} + +static struct pinmux_ops st_pmxops = { + .get_functions_count = st_pmx_get_funcs_count, + .get_function_name = st_pmx_get_fname, + .get_function_groups = st_pmx_get_groups, + .enable = st_pmx_enable, + .disable = st_pmx_disable, + .gpio_set_direction = st_pmx_set_gpio_direction, +}; + +/* Pinconf */ +static void st_pinconf_get_retime(struct st_pinctrl *info, + struct st_pio_control *pc, int pin, unsigned long *config) +{ + if (info->data->rt_style == st_retime_style_packed) + st_pinconf_get_retime_packed(info, pc, pin, config); + else if (info->data->rt_style == st_retime_style_dedicated) + if ((BIT(pin) & pc->rt_pin_mask)) + st_pinconf_get_retime_dedicated(info, pc, + pin, config); +} + +static void st_pinconf_set_retime(struct st_pinctrl *info, + struct st_pio_control *pc, int pin, unsigned long config) +{ + if (info->data->rt_style == st_retime_style_packed) + st_pinconf_set_retime_packed(info, pc, config, pin); + else if (info->data->rt_style == st_retime_style_dedicated) + if ((BIT(pin) & pc->rt_pin_mask)) + st_pinconf_set_retime_dedicated(info, pc, + config, pin); +} + +static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *configs, unsigned num_configs) +{ + int pin = st_gpio_pin(pin_id); + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); + int i; + + for (i = 0; i < num_configs; i++) { + st_pinconf_set_config(pc, pin, configs[i]); + st_pinconf_set_retime(info, pc, pin, configs[i]); + } /* for each config */ + + return 0; +} + +static int st_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *config) +{ + int pin = st_gpio_pin(pin_id); + struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); + + *config = 0; + st_pinconf_get_direction(pc, pin, config); + st_pinconf_get_retime(info, pc, pin, config); + + return 0; +} + +static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin_id) +{ + unsigned long config; + st_pinconf_get(pctldev, pin_id, &config); + + seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n" + "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," + "de:%ld,rt-clk:%ld,rt-delay:%ld]", + ST_PINCONF_UNPACK_OE(config), + ST_PINCONF_UNPACK_PU(config), + ST_PINCONF_UNPACK_OD(config), + ST_PINCONF_UNPACK_RT(config), + ST_PINCONF_UNPACK_RT_INVERTCLK(config), + ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), + ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), + ST_PINCONF_UNPACK_RT_CLK(config), + ST_PINCONF_UNPACK_RT_DELAY(config)); +} + +static struct pinconf_ops st_confops = { + .pin_config_get = st_pinconf_get, + .pin_config_set = st_pinconf_set, + .pin_config_dbg_show = st_pinconf_dbg_show, +}; + +static void st_pctl_dt_child_count(struct st_pinctrl *info, + struct device_node *np) +{ + struct device_node *child; + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + info->nbanks++; + } else { + info->nfunctions++; + info->ngroups += of_get_child_count(child); + } + } +} + +static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, + int bank, struct st_pio_control *pc) +{ + struct device *dev = info->dev; + struct regmap *rm = info->regmap; + const struct st_pctl_data *data = info->data; + /* 2 registers per bank */ + int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; + struct st_retime_packed *rt_p = &pc->rt.rt_p; + /* cfg0 */ + struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); + struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); + struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); + /* cfg1 */ + struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); + struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); + struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); + struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); + + rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); + rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); + rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); + rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); + rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); + rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); + rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); + + if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || + IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || + IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || + IS_ERR(rt_p->double_edge)) + return -EINVAL; + + return 0; +} + +static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, + int bank, struct st_pio_control *pc) +{ + struct device *dev = info->dev; + struct regmap *rm = info->regmap; + const struct st_pctl_data *data = info->data; + /* 8 registers per bank */ + int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; + struct st_retime_dedicated *rt_d = &pc->rt.rt_d; + unsigned int j; + u32 pin_mask = pc->rt_pin_mask; + + for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { + if (BIT(j) & pin_mask) { + struct reg_field reg = REG_FIELD(reg_offset, 0, 31); + rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); + if (IS_ERR(rt_d->rt[j])) + return -EINVAL; + reg_offset += 4; + } + } + return 0; +} + +static int st_pctl_dt_setup_retime(struct st_pinctrl *info, + int bank, struct st_pio_control *pc) +{ + const struct st_pctl_data *data = info->data; + if (data->rt_style == st_retime_style_packed) + return st_pctl_dt_setup_retime_packed(info, bank, pc); + else if (data->rt_style == st_retime_style_dedicated) + return st_pctl_dt_setup_retime_dedicated(info, bank, pc); + + return -EINVAL; +} + + +static struct regmap_field *st_pc_get_value(struct device *dev, + struct regmap *regmap, int bank, + int data, int lsb, int msb) +{ + struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); + + if (data < 0) + return NULL; + + return devm_regmap_field_alloc(dev, regmap, reg); +} + +static void st_parse_syscfgs(struct st_pinctrl *info, int bank, + struct device_node *np) +{ + const struct st_pctl_data *data = info->data; + /** + * For a given shared register like OE/PU/OD, there are 8 bits per bank + * 0:7 belongs to bank0, 8:15 belongs to bank1 ... + * So each register is shared across 4 banks. + */ + int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; + int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; + struct st_pio_control *pc = &info->banks[bank].pc; + struct device *dev = info->dev; + struct regmap *regmap = info->regmap; + + pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); + pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); + pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); + pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); + + /* retime avaiable for all pins by default */ + pc->rt_pin_mask = 0xff; + of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); + st_pctl_dt_setup_retime(info, bank, pc); + + return; +} + +/* + * Each pin is represented in of the below forms. + * <bank offset mux direction rt_type rt_delay rt_clk> + */ +static int st_pctl_dt_parse_groups(struct device_node *np, + struct st_pctl_group *grp, struct st_pinctrl *info, int idx) +{ + /* bank pad direction val altfunction */ + const __be32 *list; + struct property *pp; + struct st_pinconf *conf; + phandle phandle; + struct device_node *pins; + u32 pin; + int i = 0, npins = 0, nr_props; + + pins = of_get_child_by_name(np, "st,pins"); + if (!pins) + return -ENODATA; + + for_each_property_of_node(pins, pp) { + /* Skip those we do not want to proceed */ + if (!strcmp(pp->name, "name")) + continue; + + if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) { + npins++; + } else { + pr_warn("Invalid st,pins in %s node\n", np->name); + return -EINVAL; + } + } + + grp->npins = npins; + grp->name = np->name; + grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL); + grp->pin_conf = devm_kzalloc(info->dev, + npins * sizeof(*conf), GFP_KERNEL); + + if (!grp->pins || !grp->pin_conf) + return -ENOMEM; + + /* <bank offset mux direction rt_type rt_delay rt_clk> */ + for_each_property_of_node(pins, pp) { + if (!strcmp(pp->name, "name")) + continue; + nr_props = pp->length/sizeof(u32); + list = pp->value; + conf = &grp->pin_conf[i]; + + /* bank & offset */ + phandle = be32_to_cpup(list++); + pin = be32_to_cpup(list++); + conf->pin = of_get_named_gpio(pins, pp->name, 0); + conf->name = pp->name; + grp->pins[i] = conf->pin; + /* mux */ + conf->altfunc = be32_to_cpup(list++); + conf->config = 0; + /* direction */ + conf->config |= be32_to_cpup(list++); + /* rt_type rt_delay rt_clk */ + if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { + /* rt_type */ + conf->config |= be32_to_cpup(list++); + /* rt_delay */ + conf->config |= be32_to_cpup(list++); + /* rt_clk */ + if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) + conf->config |= be32_to_cpup(list++); + } + i++; + } + of_node_put(pins); + + return 0; +} + +static int st_pctl_parse_functions(struct device_node *np, + struct st_pinctrl *info, u32 index, int *grp_index) +{ + struct device_node *child; + struct st_pmx_func *func; + struct st_pctl_group *grp; + int ret, i; + + func = &info->functions[index]; + func->name = np->name; + func->ngroups = of_get_child_count(np); + if (func->ngroups <= 0) { + dev_err(info->dev, "No groups defined\n"); + return -EINVAL; + } + func->groups = devm_kzalloc(info->dev, + func->ngroups * sizeof(char *), GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + i = 0; + for_each_child_of_node(np, child) { + func->groups[i] = child->name; + grp = &info->groups[*grp_index]; + *grp_index += 1; + ret = st_pctl_dt_parse_groups(child, grp, info, i++); + if (ret) + return ret; + } + dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", + index, func->name, func->ngroups); + + return 0; +} + +static void st_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct st_gpio_bank *bank = gpio_chip_to_bank(gc); + + writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); +} + +static void st_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct st_gpio_bank *bank = gpio_chip_to_bank(gc); + + writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); +} + +static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct st_gpio_bank *bank = gpio_chip_to_bank(gc); + unsigned long flags; + int comp, pin = d->hwirq; + u32 val; + u32 pin_edge_conf = 0; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + comp = 0; + break; + case IRQ_TYPE_EDGE_FALLING: + comp = 0; + pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); + break; + case IRQ_TYPE_LEVEL_LOW: + comp = 1; + break; + case IRQ_TYPE_EDGE_RISING: + comp = 1; + pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); + break; + case IRQ_TYPE_EDGE_BOTH: + comp = st_gpio_get(&bank->gpio_chip, pin); + pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); + break; + default: + return -EINVAL; + } + + spin_lock_irqsave(&bank->lock, flags); + bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( + pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); + bank->irq_edge_conf |= pin_edge_conf; + spin_unlock_irqrestore(&bank->lock, flags); + + val = readl(bank->base + REG_PIO_PCOMP); + val &= ~BIT(pin); + val |= (comp << pin); + writel(val, bank->base + REG_PIO_PCOMP); + + return 0; +} + +/* + * As edge triggers are not supported at hardware level, it is supported by + * software by exploiting the level trigger support in hardware. + * + * Steps for detection raising edge interrupt in software. + * + * Step 1: CONFIGURE pin to detect level LOW interrupts. + * + * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, + * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. + * IGNORE calling the actual interrupt handler for the pin at this stage. + * + * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler + * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then + * DISPATCH the interrupt to the interrupt handler of the pin. + * + * step-1 ________ __________ + * | | step - 3 + * | | + * step -2 |_____| + * + * falling edge is also detected int the same way. + * + */ +static void __gpio_irq_handler(struct st_gpio_bank *bank) +{ + unsigned long port_in, port_mask, port_comp, active_irqs; + unsigned long bank_edge_mask, flags; + int n, val, ecfg; + + spin_lock_irqsave(&bank->lock, flags); + bank_edge_mask = bank->irq_edge_conf; + spin_unlock_irqrestore(&bank->lock, flags); + + for (;;) { + port_in = readl(bank->base + REG_PIO_PIN); + port_comp = readl(bank->base + REG_PIO_PCOMP); + port_mask = readl(bank->base + REG_PIO_PMASK); + + active_irqs = (port_in ^ port_comp) & port_mask; + + if (active_irqs == 0) + break; + + for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { + /* check if we are detecting fake edges ... */ + ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); + + if (ecfg) { + /* edge detection. */ + val = st_gpio_get(&bank->gpio_chip, n); + + writel(BIT(n), + val ? bank->base + REG_PIO_SET_PCOMP : + bank->base + REG_PIO_CLR_PCOMP); + + if (ecfg != ST_IRQ_EDGE_BOTH && + !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) + continue; + } + + generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n)); + } + } +} + +static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +{ + /* interrupt dedicated per bank */ + struct irq_chip *chip = irq_get_chip(irq); + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct st_gpio_bank *bank = gpio_chip_to_bank(gc); + + chained_irq_enter(chip, desc); + __gpio_irq_handler(bank); + chained_irq_exit(chip, desc); +} + +static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct st_pinctrl *info = irq_get_handler_data(irq); + unsigned long status; + int n; + + chained_irq_enter(chip, desc); + + status = readl(info->irqmux_base); + + for_each_set_bit(n, &status, info->nbanks) + __gpio_irq_handler(&info->banks[n]); + + chained_irq_exit(chip, desc); +} + +static struct gpio_chip st_gpio_template = { + .request = st_gpio_request, + .free = st_gpio_free, + .get = st_gpio_get, + .set = st_gpio_set, + .direction_input = st_gpio_direction_input, + .direction_output = st_gpio_direction_output, + .ngpio = ST_GPIO_PINS_PER_BANK, + .of_gpio_n_cells = 1, + .of_xlate = st_gpio_xlate, +}; + +static struct irq_chip st_gpio_irqchip = { + .name = "GPIO", + .irq_mask = st_gpio_irq_mask, + .irq_unmask = st_gpio_irq_unmask, + .irq_set_type = st_gpio_irq_set_type, +}; + +static int st_gpiolib_register_bank(struct st_pinctrl *info, + int bank_nr, struct device_node *np) +{ + struct st_gpio_bank *bank = &info->banks[bank_nr]; + struct pinctrl_gpio_range *range = &bank->range; + struct device *dev = info->dev; + int bank_num = of_alias_get_id(np, "gpio"); + struct resource res, irq_res; + int gpio_irq = 0, err; + + if (of_address_to_resource(np, 0, &res)) + return -ENODEV; + + bank->base = devm_ioremap_resource(dev, &res); + if (IS_ERR(bank->base)) + return PTR_ERR(bank->base); + + bank->gpio_chip = st_gpio_template; + bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; + bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; + bank->gpio_chip.of_node = np; + bank->gpio_chip.dev = dev; + spin_lock_init(&bank->lock); + + of_property_read_string(np, "st,bank-name", &range->name); + bank->gpio_chip.label = range->name; + + range->id = bank_num; + range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; + range->npins = bank->gpio_chip.ngpio; + range->gc = &bank->gpio_chip; + err = gpiochip_add(&bank->gpio_chip); + if (err) { + dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); + return err; + } + dev_info(dev, "%s bank added.\n", range->name); + + /** + * GPIO bank can have one of the two possible types of + * interrupt-wirings. + * + * First type is via irqmux, single interrupt is used by multiple + * gpio banks. This reduces number of overall interrupts numbers + * required. All these banks belong to a single pincontroller. + * _________ + * | |----> [gpio-bank (n) ] + * | |----> [gpio-bank (n + 1)] + * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] + * | |----> [gpio-bank (... )] + * |_________|----> [gpio-bank (n + 7)] + * + * Second type has a dedicated interrupt per each gpio bank. + * + * [irqN]----> [gpio-bank (n)] + */ + + if (of_irq_to_resource(np, 0, &irq_res)) { + gpio_irq = irq_res.start; + gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, + gpio_irq, st_gpio_irq_handler); + } + + if (info->irqmux_base > 0 || gpio_irq > 0) { + err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, + 0, handle_simple_irq, + IRQ_TYPE_LEVEL_LOW); + if (err) { + dev_info(dev, "could not add irqchip\n"); + return err; + } + } else { + dev_info(dev, "No IRQ support for %s bank\n", np->full_name); + } + + return 0; +} + +static struct of_device_id st_pctl_of_match[] = { + { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data }, + { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data }, + { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data }, + { .compatible = "st,stih415-right-pinctrl", + .data = &stih415_right_data }, + { .compatible = "st,stih415-front-pinctrl", + .data = &stih415_front_data }, + { .compatible = "st,stih416-sbc-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih416-front-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih407-sbc-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih407-front-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih407-rear-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, + { /* sentinel */ } +}; + +static int st_pctl_probe_dt(struct platform_device *pdev, + struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) +{ + int ret = 0; + int i = 0, j = 0, k = 0, bank; + struct pinctrl_pin_desc *pdesc; + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + int grp_index = 0; + int irq = 0; + struct resource *res; + + st_pctl_dt_child_count(info, np); + if (!info->nbanks) { + dev_err(&pdev->dev, "you need atleast one gpio bank\n"); + return -EINVAL; + } + + dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); + dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); + dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); + + info->functions = devm_kzalloc(&pdev->dev, + info->nfunctions * sizeof(*info->functions), GFP_KERNEL); + + info->groups = devm_kzalloc(&pdev->dev, + info->ngroups * sizeof(*info->groups) , GFP_KERNEL); + + info->banks = devm_kzalloc(&pdev->dev, + info->nbanks * sizeof(*info->banks), GFP_KERNEL); + + if (!info->functions || !info->groups || !info->banks) + return -ENOMEM; + + info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + if (IS_ERR(info->regmap)) { + dev_err(info->dev, "No syscfg phandle specified\n"); + return PTR_ERR(info->regmap); + } + info->data = of_match_node(st_pctl_of_match, np)->data; + + irq = platform_get_irq(pdev, 0); + + if (irq > 0) { + res = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "irqmux"); + info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); + + if (IS_ERR(info->irqmux_base)) + return PTR_ERR(info->irqmux_base); + + irq_set_chained_handler(irq, st_gpio_irqmux_handler); + irq_set_handler_data(irq, info); + + } + + pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; + pdesc = devm_kzalloc(&pdev->dev, + sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL); + if (!pdesc) + return -ENOMEM; + + pctl_desc->pins = pdesc; + + bank = 0; + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + const char *bank_name = NULL; + ret = st_gpiolib_register_bank(info, bank, child); + if (ret) + return ret; + + k = info->banks[bank].range.pin_base; + bank_name = info->banks[bank].range.name; + for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { + pdesc->number = k; + pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", + bank_name, j); + pdesc++; + } + st_parse_syscfgs(info, bank, child); + bank++; + } else { + ret = st_pctl_parse_functions(child, info, + i++, &grp_index); + if (ret) { + dev_err(&pdev->dev, "No functions found.\n"); + return ret; + } + } + } + + return 0; +} + +static int st_pctl_probe(struct platform_device *pdev) +{ + struct st_pinctrl *info; + struct pinctrl_desc *pctl_desc; + int ret, i; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "device node not found.\n"); + return -EINVAL; + } + + pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); + if (!pctl_desc) + return -ENOMEM; + + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev = &pdev->dev; + platform_set_drvdata(pdev, info); + ret = st_pctl_probe_dt(pdev, pctl_desc, info); + if (ret) + return ret; + + pctl_desc->owner = THIS_MODULE; + pctl_desc->pctlops = &st_pctlops; + pctl_desc->pmxops = &st_pmxops; + pctl_desc->confops = &st_confops; + pctl_desc->name = dev_name(&pdev->dev); + + info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info); + if (!info->pctl) { + dev_err(&pdev->dev, "Failed pinctrl registration\n"); + return -EINVAL; + } + + for (i = 0; i < info->nbanks; i++) + pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); + + return 0; +} + +static struct platform_driver st_pctl_driver = { + .driver = { + .name = "st-pinctrl", + .owner = THIS_MODULE, + .of_match_table = st_pctl_of_match, + }, + .probe = st_pctl_probe, +}; + +static int __init st_pctl_init(void) +{ + return platform_driver_register(&st_pctl_driver); +} +arch_initcall(st_pctl_init); diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c deleted file mode 100644 index c52fc2c0873..00000000000 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ /dev/null @@ -1,2021 +0,0 @@ -/* - * Allwinner A1X SoCs pinctrl driver. - * - * Copyright (C) 2012 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/gpio.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/slab.h> - -#include "core.h" -#include "pinctrl-sunxi.h" - -static const struct sunxi_desc_pin sun4i_a10_pins[] = { - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ - SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ - SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ - SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x4, "uart2")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ - SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x4, "uart2")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ - SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ - SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ - SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ - SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ - SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ - SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ - SUNXI_FUNCTION(0x3, "uart6"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ - SUNXI_FUNCTION(0x3, "uart6"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ - SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ - SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ - SUNXI_FUNCTION(0x3, "can"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ - SUNXI_FUNCTION(0x3, "can"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1")), /* RING */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ - SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ - SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ - SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ - SUNXI_FUNCTION(0x3, "ac97")), /* DO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* DI */ - SUNXI_FUNCTION(0x3, "ac97")), /* DI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ - SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ - SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ - SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ - SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0"), /* TX */ - SUNXI_FUNCTION(0x3, "ir1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0"), /* RX */ - SUNXI_FUNCTION(0x3, "ir1")), /* RX */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ - SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ - SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ - SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ - SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ - SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ - SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ - SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ - SUNXI_FUNCTION(0x3, "sim")), /* DET */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ - SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ - SUNXI_FUNCTION(0x3, "sim")), /* RST */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "sim")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "sim")), /* SDA */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ - SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ - SUNXI_FUNCTION(0x3, "csi0")), /* CK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ - SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ - SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ - SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ - SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart0")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ - SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart0")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ - SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ - SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ - SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ - SUNXI_FUNCTION(0x3, "csi1"), /* CK */ - SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ - SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ - SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ - SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ - SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ - SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ - SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ - SUNXI_FUNCTION(0x4, "uart3"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ - SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart4"), /* RX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ - SUNXI_FUNCTION(0x4, "uart3"), /* TX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ - SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ - SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ - SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ - SUNXI_FUNCTION(0x4, "uart4"), /* RX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ - SUNXI_FUNCTION(0x4, "uart5"), /* TX */ - SUNXI_FUNCTION(0x5, "ms"), /* BS */ - SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ - SUNXI_FUNCTION(0x4, "uart5"), /* RX */ - SUNXI_FUNCTION(0x5, "ms"), /* CLK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ - SUNXI_FUNCTION(0x5, "ms"), /* D0 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ - SUNXI_FUNCTION(0x5, "ms"), /* D1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ - SUNXI_FUNCTION(0x5, "ms"), /* D2 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ - SUNXI_FUNCTION(0x5, "ms"), /* D3 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ - SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ - SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ - SUNXI_FUNCTION(0x5, "sim"), /* RST */ - SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ - SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ - SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ - SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ - SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ - SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ - SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ - SUNXI_FUNCTION(0x5, "sim"), /* SCK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ - SUNXI_FUNCTION(0x5, "sim"), /* SDA */ - SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ - SUNXI_FUNCTION(0x4, "can"), /* TX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ - SUNXI_FUNCTION(0x4, "can"), /* RX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ - SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ - SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ - SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ - SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ - SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart5")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart5")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart6")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart6")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ - SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ - SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ - SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ - SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart2")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart2")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ - SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ - SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ -}; - -static const struct sunxi_desc_pin sun5i_a13_pins[] = { - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* RX */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ - SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ - SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ - SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ - SUNXI_FUNCTION(0x4, "spi2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ -/* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart3")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart3")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ -}; - -static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { - .pins = sun4i_a10_pins, - .npins = ARRAY_SIZE(sun4i_a10_pins), -}; - -static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { - .pins = sun5i_a13_pins, - .npins = ARRAY_SIZE(sun5i_a13_pins), -}; - -static struct sunxi_pinctrl_group * -sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) -{ - int i; - - for (i = 0; i < pctl->ngroups; i++) { - struct sunxi_pinctrl_group *grp = pctl->groups + i; - - if (!strcmp(grp->name, group)) - return grp; - } - - return NULL; -} - -static struct sunxi_pinctrl_function * -sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, - const char *name) -{ - struct sunxi_pinctrl_function *func = pctl->functions; - int i; - - for (i = 0; i < pctl->nfunctions; i++) { - if (!func[i].name) - break; - - if (!strcmp(func[i].name, name)) - return func + i; - } - - return NULL; -} - -static struct sunxi_desc_function * -sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, - const char *pin_name, - const char *func_name) -{ - int i; - - for (i = 0; i < pctl->desc->npins; i++) { - const struct sunxi_desc_pin *pin = pctl->desc->pins + i; - - if (!strcmp(pin->pin.name, pin_name)) { - struct sunxi_desc_function *func = pin->functions; - - while (func->name) { - if (!strcmp(func->name, func_name)) - return func; - - func++; - } - } - } - - return NULL; -} - -static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->ngroups; -} - -static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->groups[group].name; -} - -static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned group, - const unsigned **pins, - unsigned *num_pins) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - *pins = (unsigned *)&pctl->groups[group].pin; - *num_pins = 1; - - return 0; -} - -static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *node, - struct pinctrl_map **map, - unsigned *num_maps) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - unsigned long *pinconfig; - struct property *prop; - const char *function; - const char *group; - int ret, nmaps, i = 0; - u32 val; - - *map = NULL; - *num_maps = 0; - - ret = of_property_read_string(node, "allwinner,function", &function); - if (ret) { - dev_err(pctl->dev, - "missing allwinner,function property in node %s\n", - node->name); - return -EINVAL; - } - - nmaps = of_property_count_strings(node, "allwinner,pins") * 2; - if (nmaps < 0) { - dev_err(pctl->dev, - "missing allwinner,pins property in node %s\n", - node->name); - return -EINVAL; - } - - *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); - if (!map) - return -ENOMEM; - - of_property_for_each_string(node, "allwinner,pins", prop, group) { - struct sunxi_pinctrl_group *grp = - sunxi_pinctrl_find_group_by_name(pctl, group); - int j = 0, configlen = 0; - - if (!grp) { - dev_err(pctl->dev, "unknown pin %s", group); - continue; - } - - if (!sunxi_pinctrl_desc_find_function_by_name(pctl, - grp->name, - function)) { - dev_err(pctl->dev, "unsupported function %s on pin %s", - function, group); - continue; - } - - (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[i].data.mux.group = group; - (*map)[i].data.mux.function = function; - - i++; - - (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; - (*map)[i].data.configs.group_or_pin = group; - - if (of_find_property(node, "allwinner,drive", NULL)) - configlen++; - if (of_find_property(node, "allwinner,pull", NULL)) - configlen++; - - pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); - - if (!of_property_read_u32(node, "allwinner,drive", &val)) { - u16 strength = (val + 1) * 10; - pinconfig[j++] = - pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, - strength); - } - - if (!of_property_read_u32(node, "allwinner,pull", &val)) { - enum pin_config_param pull = PIN_CONFIG_END; - if (val == 1) - pull = PIN_CONFIG_BIAS_PULL_UP; - else if (val == 2) - pull = PIN_CONFIG_BIAS_PULL_DOWN; - pinconfig[j++] = pinconf_to_config_packed(pull, 0); - } - - (*map)[i].data.configs.configs = pinconfig; - (*map)[i].data.configs.num_configs = configlen; - - i++; - } - - *num_maps = nmaps; - - return 0; -} - -static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, - unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) { - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - } - - kfree(map); -} - -static const struct pinctrl_ops sunxi_pctrl_ops = { - .dt_node_to_map = sunxi_pctrl_dt_node_to_map, - .dt_free_map = sunxi_pctrl_dt_free_map, - .get_groups_count = sunxi_pctrl_get_groups_count, - .get_group_name = sunxi_pctrl_get_group_name, - .get_group_pins = sunxi_pctrl_get_group_pins, -}; - -static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, - unsigned group, - unsigned long *config) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - *config = pctl->groups[group].config; - - return 0; -} - -static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, - unsigned long config) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct sunxi_pinctrl_group *g = &pctl->groups[group]; - u32 val, mask; - u16 strength; - u8 dlevel; - - switch (pinconf_to_config_param(config)) { - case PIN_CONFIG_DRIVE_STRENGTH: - strength = pinconf_to_config_argument(config); - if (strength > 40) - return -EINVAL; - /* - * We convert from mA to what the register expects: - * 0: 10mA - * 1: 20mA - * 2: 30mA - * 3: 40mA - */ - dlevel = strength / 10 - 1; - val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); - mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); - writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin), - pctl->membase + sunxi_dlevel_reg(g->pin)); - break; - case PIN_CONFIG_BIAS_PULL_UP: - val = readl(pctl->membase + sunxi_pull_reg(g->pin)); - mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); - writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), - pctl->membase + sunxi_pull_reg(g->pin)); - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - val = readl(pctl->membase + sunxi_pull_reg(g->pin)); - mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); - writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), - pctl->membase + sunxi_pull_reg(g->pin)); - break; - default: - break; - } - - /* cache the config value */ - g->config = config; - - return 0; -} - -static const struct pinconf_ops sunxi_pconf_ops = { - .pin_config_group_get = sunxi_pconf_group_get, - .pin_config_group_set = sunxi_pconf_group_set, -}; - -static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->nfunctions; -} - -static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->functions[function].name; -} - -static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, - unsigned function, - const char * const **groups, - unsigned * const num_groups) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pctl->functions[function].groups; - *num_groups = pctl->functions[function].ngroups; - - return 0; -} - -static void sunxi_pmx_set(struct pinctrl_dev *pctldev, - unsigned pin, - u8 config) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - u32 val = readl(pctl->membase + sunxi_mux_reg(pin)); - u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); - writel((val & ~mask) | config << sunxi_mux_offset(pin), - pctl->membase + sunxi_mux_reg(pin)); -} - -static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct sunxi_pinctrl_group *g = pctl->groups + group; - struct sunxi_pinctrl_function *func = pctl->functions + function; - struct sunxi_desc_function *desc = - sunxi_pinctrl_desc_find_function_by_name(pctl, - g->name, - func->name); - - if (!desc) - return -EINVAL; - - sunxi_pmx_set(pctldev, g->pin, desc->muxval); - - return 0; -} - -static int -sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset, - bool input) -{ - struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct sunxi_desc_function *desc; - char pin_name[SUNXI_PIN_NAME_MAX_LEN]; - const char *func; - u8 bank, pin; - int ret; - - bank = (offset) / PINS_PER_BANK; - pin = (offset) % PINS_PER_BANK; - - ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin); - if (!ret) - goto error; - - if (input) - func = "gpio_in"; - else - func = "gpio_out"; - - desc = sunxi_pinctrl_desc_find_function_by_name(pctl, - pin_name, - func); - if (!desc) { - ret = -EINVAL; - goto error; - } - - sunxi_pmx_set(pctldev, offset, desc->muxval); - - ret = 0; - -error: - return ret; -} - -static const struct pinmux_ops sunxi_pmx_ops = { - .get_functions_count = sunxi_pmx_get_funcs_cnt, - .get_function_name = sunxi_pmx_get_func_name, - .get_function_groups = sunxi_pmx_get_func_groups, - .enable = sunxi_pmx_enable, - .gpio_set_direction = sunxi_pmx_gpio_set_direction, -}; - -static struct pinctrl_desc sunxi_pctrl_desc = { - .confops = &sunxi_pconf_ops, - .pctlops = &sunxi_pctrl_ops, - .pmxops = &sunxi_pmx_ops, -}; - -static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - return pinctrl_request_gpio(chip->base + offset); -} - -static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - pinctrl_free_gpio(chip->base + offset); -} - -static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, - unsigned offset) -{ - return pinctrl_gpio_direction_input(chip->base + offset); -} - -static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); - - u32 reg = sunxi_data_reg(offset); - u8 index = sunxi_data_offset(offset); - u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; - - return val; -} - -static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - return pinctrl_gpio_direction_output(chip->base + offset); -} - -static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); - u32 reg = sunxi_data_reg(offset); - u8 index = sunxi_data_offset(offset); - - writel((value & DATA_PINS_MASK) << index, pctl->membase + reg); -} - -static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, - const struct of_phandle_args *gpiospec, - u32 *flags) -{ - int pin, base; - - base = PINS_PER_BANK * gpiospec->args[0]; - pin = base + gpiospec->args[1]; - - if (pin > (gc->base + gc->ngpio)) - return -EINVAL; - - if (flags) - *flags = gpiospec->args[2]; - - return pin; -} - -static struct gpio_chip sunxi_pinctrl_gpio_chip = { - .owner = THIS_MODULE, - .request = sunxi_pinctrl_gpio_request, - .free = sunxi_pinctrl_gpio_free, - .direction_input = sunxi_pinctrl_gpio_direction_input, - .direction_output = sunxi_pinctrl_gpio_direction_output, - .get = sunxi_pinctrl_gpio_get, - .set = sunxi_pinctrl_gpio_set, - .of_xlate = sunxi_pinctrl_gpio_of_xlate, - .of_gpio_n_cells = 3, - .can_sleep = 0, -}; - -static struct of_device_id sunxi_pinctrl_match[] = { - { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data }, - { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data }, - {} -}; -MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match); - -static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, - const char *name) -{ - struct sunxi_pinctrl_function *func = pctl->functions; - - while (func->name) { - /* function already there */ - if (strcmp(func->name, name) == 0) { - func->ngroups++; - return -EEXIST; - } - func++; - } - - func->name = name; - func->ngroups = 1; - - pctl->nfunctions++; - - return 0; -} - -static int sunxi_pinctrl_build_state(struct platform_device *pdev) -{ - struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); - int i; - - pctl->ngroups = pctl->desc->npins; - - /* Allocate groups */ - pctl->groups = devm_kzalloc(&pdev->dev, - pctl->ngroups * sizeof(*pctl->groups), - GFP_KERNEL); - if (!pctl->groups) - return -ENOMEM; - - for (i = 0; i < pctl->desc->npins; i++) { - const struct sunxi_desc_pin *pin = pctl->desc->pins + i; - struct sunxi_pinctrl_group *group = pctl->groups + i; - - group->name = pin->pin.name; - group->pin = pin->pin.number; - } - - /* - * We suppose that we won't have any more functions than pins, - * we'll reallocate that later anyway - */ - pctl->functions = devm_kzalloc(&pdev->dev, - pctl->desc->npins * sizeof(*pctl->functions), - GFP_KERNEL); - if (!pctl->functions) - return -ENOMEM; - - /* Count functions and their associated groups */ - for (i = 0; i < pctl->desc->npins; i++) { - const struct sunxi_desc_pin *pin = pctl->desc->pins + i; - struct sunxi_desc_function *func = pin->functions; - - while (func->name) { - sunxi_pinctrl_add_function(pctl, func->name); - func++; - } - } - - pctl->functions = krealloc(pctl->functions, - pctl->nfunctions * sizeof(*pctl->functions), - GFP_KERNEL); - - for (i = 0; i < pctl->desc->npins; i++) { - const struct sunxi_desc_pin *pin = pctl->desc->pins + i; - struct sunxi_desc_function *func = pin->functions; - - while (func->name) { - struct sunxi_pinctrl_function *func_item; - const char **func_grp; - - func_item = sunxi_pinctrl_find_function_by_name(pctl, - func->name); - if (!func_item) - return -EINVAL; - - if (!func_item->groups) { - func_item->groups = - devm_kzalloc(&pdev->dev, - func_item->ngroups * sizeof(*func_item->groups), - GFP_KERNEL); - if (!func_item->groups) - return -ENOMEM; - } - - func_grp = func_item->groups; - while (*func_grp) - func_grp++; - - *func_grp = pin->pin.name; - func++; - } - } - - return 0; -} - -static int sunxi_pinctrl_probe(struct platform_device *pdev) -{ - struct device_node *node = pdev->dev.of_node; - const struct of_device_id *device; - struct pinctrl_pin_desc *pins; - struct sunxi_pinctrl *pctl; - int i, ret, last_pin; - struct clk *clk; - - pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); - if (!pctl) - return -ENOMEM; - platform_set_drvdata(pdev, pctl); - - pctl->membase = of_iomap(node, 0); - if (!pctl->membase) - return -ENOMEM; - - device = of_match_device(sunxi_pinctrl_match, &pdev->dev); - if (!device) - return -ENODEV; - - pctl->desc = (struct sunxi_pinctrl_desc *)device->data; - - ret = sunxi_pinctrl_build_state(pdev); - if (ret) { - dev_err(&pdev->dev, "dt probe failed: %d\n", ret); - return ret; - } - - pins = devm_kzalloc(&pdev->dev, - pctl->desc->npins * sizeof(*pins), - GFP_KERNEL); - if (!pins) - return -ENOMEM; - - for (i = 0; i < pctl->desc->npins; i++) - pins[i] = pctl->desc->pins[i].pin; - - sunxi_pctrl_desc.name = dev_name(&pdev->dev); - sunxi_pctrl_desc.owner = THIS_MODULE; - sunxi_pctrl_desc.pins = pins; - sunxi_pctrl_desc.npins = pctl->desc->npins; - pctl->dev = &pdev->dev; - pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc, - &pdev->dev, pctl); - if (!pctl->pctl_dev) { - dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); - return -EINVAL; - } - - pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); - if (!pctl->chip) { - ret = -ENOMEM; - goto pinctrl_error; - } - - last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; - pctl->chip = &sunxi_pinctrl_gpio_chip; - pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK); - pctl->chip->label = dev_name(&pdev->dev); - pctl->chip->dev = &pdev->dev; - pctl->chip->base = 0; - - ret = gpiochip_add(pctl->chip); - if (ret) - goto pinctrl_error; - - for (i = 0; i < pctl->desc->npins; i++) { - const struct sunxi_desc_pin *pin = pctl->desc->pins + i; - - ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), - pin->pin.number, - pin->pin.number, 1); - if (ret) - goto gpiochip_error; - } - - clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(clk)) - goto gpiochip_error; - - clk_prepare_enable(clk); - - dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); - - return 0; - -gpiochip_error: - ret = gpiochip_remove(pctl->chip); -pinctrl_error: - pinctrl_unregister(pctl->pctl_dev); - return ret; -} - -static struct platform_driver sunxi_pinctrl_driver = { - .probe = sunxi_pinctrl_probe, - .driver = { - .name = "sunxi-pinctrl", - .owner = THIS_MODULE, - .of_match_table = sunxi_pinctrl_match, - }, -}; -module_platform_driver(sunxi_pinctrl_driver); - -MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); -MODULE_DESCRIPTION("Allwinner A1X pinctrl driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h deleted file mode 100644 index e921621059c..00000000000 --- a/drivers/pinctrl/pinctrl-sunxi.h +++ /dev/null @@ -1,478 +0,0 @@ -/* - * Allwinner A1X SoCs pinctrl driver. - * - * Copyright (C) 2012 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PINCTRL_SUNXI_H -#define __PINCTRL_SUNXI_H - -#include <linux/kernel.h> - -#define PA_BASE 0 -#define PB_BASE 32 -#define PC_BASE 64 -#define PD_BASE 96 -#define PE_BASE 128 -#define PF_BASE 160 -#define PG_BASE 192 -#define PH_BASE 224 -#define PI_BASE 256 - -#define SUNXI_PINCTRL_PIN_PA0 PINCTRL_PIN(PA_BASE + 0, "PA0") -#define SUNXI_PINCTRL_PIN_PA1 PINCTRL_PIN(PA_BASE + 1, "PA1") -#define SUNXI_PINCTRL_PIN_PA2 PINCTRL_PIN(PA_BASE + 2, "PA2") -#define SUNXI_PINCTRL_PIN_PA3 PINCTRL_PIN(PA_BASE + 3, "PA3") -#define SUNXI_PINCTRL_PIN_PA4 PINCTRL_PIN(PA_BASE + 4, "PA4") -#define SUNXI_PINCTRL_PIN_PA5 PINCTRL_PIN(PA_BASE + 5, "PA5") -#define SUNXI_PINCTRL_PIN_PA6 PINCTRL_PIN(PA_BASE + 6, "PA6") -#define SUNXI_PINCTRL_PIN_PA7 PINCTRL_PIN(PA_BASE + 7, "PA7") -#define SUNXI_PINCTRL_PIN_PA8 PINCTRL_PIN(PA_BASE + 8, "PA8") -#define SUNXI_PINCTRL_PIN_PA9 PINCTRL_PIN(PA_BASE + 9, "PA9") -#define SUNXI_PINCTRL_PIN_PA10 PINCTRL_PIN(PA_BASE + 10, "PA10") -#define SUNXI_PINCTRL_PIN_PA11 PINCTRL_PIN(PA_BASE + 11, "PA11") -#define SUNXI_PINCTRL_PIN_PA12 PINCTRL_PIN(PA_BASE + 12, "PA12") -#define SUNXI_PINCTRL_PIN_PA13 PINCTRL_PIN(PA_BASE + 13, "PA13") -#define SUNXI_PINCTRL_PIN_PA14 PINCTRL_PIN(PA_BASE + 14, "PA14") -#define SUNXI_PINCTRL_PIN_PA15 PINCTRL_PIN(PA_BASE + 15, "PA15") -#define SUNXI_PINCTRL_PIN_PA16 PINCTRL_PIN(PA_BASE + 16, "PA16") -#define SUNXI_PINCTRL_PIN_PA17 PINCTRL_PIN(PA_BASE + 17, "PA17") -#define SUNXI_PINCTRL_PIN_PA18 PINCTRL_PIN(PA_BASE + 18, "PA18") -#define SUNXI_PINCTRL_PIN_PA19 PINCTRL_PIN(PA_BASE + 19, "PA19") -#define SUNXI_PINCTRL_PIN_PA20 PINCTRL_PIN(PA_BASE + 20, "PA20") -#define SUNXI_PINCTRL_PIN_PA21 PINCTRL_PIN(PA_BASE + 21, "PA21") -#define SUNXI_PINCTRL_PIN_PA22 PINCTRL_PIN(PA_BASE + 22, "PA22") -#define SUNXI_PINCTRL_PIN_PA23 PINCTRL_PIN(PA_BASE + 23, "PA23") -#define SUNXI_PINCTRL_PIN_PA24 PINCTRL_PIN(PA_BASE + 24, "PA24") -#define SUNXI_PINCTRL_PIN_PA25 PINCTRL_PIN(PA_BASE + 25, "PA25") -#define SUNXI_PINCTRL_PIN_PA26 PINCTRL_PIN(PA_BASE + 26, "PA26") -#define SUNXI_PINCTRL_PIN_PA27 PINCTRL_PIN(PA_BASE + 27, "PA27") -#define SUNXI_PINCTRL_PIN_PA28 PINCTRL_PIN(PA_BASE + 28, "PA28") -#define SUNXI_PINCTRL_PIN_PA29 PINCTRL_PIN(PA_BASE + 29, "PA29") -#define SUNXI_PINCTRL_PIN_PA30 PINCTRL_PIN(PA_BASE + 30, "PA30") -#define SUNXI_PINCTRL_PIN_PA31 PINCTRL_PIN(PA_BASE + 31, "PA31") - -#define SUNXI_PINCTRL_PIN_PB0 PINCTRL_PIN(PB_BASE + 0, "PB0") -#define SUNXI_PINCTRL_PIN_PB1 PINCTRL_PIN(PB_BASE + 1, "PB1") -#define SUNXI_PINCTRL_PIN_PB2 PINCTRL_PIN(PB_BASE + 2, "PB2") -#define SUNXI_PINCTRL_PIN_PB3 PINCTRL_PIN(PB_BASE + 3, "PB3") -#define SUNXI_PINCTRL_PIN_PB4 PINCTRL_PIN(PB_BASE + 4, "PB4") -#define SUNXI_PINCTRL_PIN_PB5 PINCTRL_PIN(PB_BASE + 5, "PB5") -#define SUNXI_PINCTRL_PIN_PB6 PINCTRL_PIN(PB_BASE + 6, "PB6") -#define SUNXI_PINCTRL_PIN_PB7 PINCTRL_PIN(PB_BASE + 7, "PB7") -#define SUNXI_PINCTRL_PIN_PB8 PINCTRL_PIN(PB_BASE + 8, "PB8") -#define SUNXI_PINCTRL_PIN_PB9 PINCTRL_PIN(PB_BASE + 9, "PB9") -#define SUNXI_PINCTRL_PIN_PB10 PINCTRL_PIN(PB_BASE + 10, "PB10") -#define SUNXI_PINCTRL_PIN_PB11 PINCTRL_PIN(PB_BASE + 11, "PB11") -#define SUNXI_PINCTRL_PIN_PB12 PINCTRL_PIN(PB_BASE + 12, "PB12") -#define SUNXI_PINCTRL_PIN_PB13 PINCTRL_PIN(PB_BASE + 13, "PB13") -#define SUNXI_PINCTRL_PIN_PB14 PINCTRL_PIN(PB_BASE + 14, "PB14") -#define SUNXI_PINCTRL_PIN_PB15 PINCTRL_PIN(PB_BASE + 15, "PB15") -#define SUNXI_PINCTRL_PIN_PB16 PINCTRL_PIN(PB_BASE + 16, "PB16") -#define SUNXI_PINCTRL_PIN_PB17 PINCTRL_PIN(PB_BASE + 17, "PB17") -#define SUNXI_PINCTRL_PIN_PB18 PINCTRL_PIN(PB_BASE + 18, "PB18") -#define SUNXI_PINCTRL_PIN_PB19 PINCTRL_PIN(PB_BASE + 19, "PB19") -#define SUNXI_PINCTRL_PIN_PB20 PINCTRL_PIN(PB_BASE + 20, "PB20") -#define SUNXI_PINCTRL_PIN_PB21 PINCTRL_PIN(PB_BASE + 21, "PB21") -#define SUNXI_PINCTRL_PIN_PB22 PINCTRL_PIN(PB_BASE + 22, "PB22") -#define SUNXI_PINCTRL_PIN_PB23 PINCTRL_PIN(PB_BASE + 23, "PB23") -#define SUNXI_PINCTRL_PIN_PB24 PINCTRL_PIN(PB_BASE + 24, "PB24") -#define SUNXI_PINCTRL_PIN_PB25 PINCTRL_PIN(PB_BASE + 25, "PB25") -#define SUNXI_PINCTRL_PIN_PB26 PINCTRL_PIN(PB_BASE + 26, "PB26") -#define SUNXI_PINCTRL_PIN_PB27 PINCTRL_PIN(PB_BASE + 27, "PB27") -#define SUNXI_PINCTRL_PIN_PB28 PINCTRL_PIN(PB_BASE + 28, "PB28") -#define SUNXI_PINCTRL_PIN_PB29 PINCTRL_PIN(PB_BASE + 29, "PB29") -#define SUNXI_PINCTRL_PIN_PB30 PINCTRL_PIN(PB_BASE + 30, "PB30") -#define SUNXI_PINCTRL_PIN_PB31 PINCTRL_PIN(PB_BASE + 31, "PB31") - -#define SUNXI_PINCTRL_PIN_PC0 PINCTRL_PIN(PC_BASE + 0, "PC0") -#define SUNXI_PINCTRL_PIN_PC1 PINCTRL_PIN(PC_BASE + 1, "PC1") -#define SUNXI_PINCTRL_PIN_PC2 PINCTRL_PIN(PC_BASE + 2, "PC2") -#define SUNXI_PINCTRL_PIN_PC3 PINCTRL_PIN(PC_BASE + 3, "PC3") -#define SUNXI_PINCTRL_PIN_PC4 PINCTRL_PIN(PC_BASE + 4, "PC4") -#define SUNXI_PINCTRL_PIN_PC5 PINCTRL_PIN(PC_BASE + 5, "PC5") -#define SUNXI_PINCTRL_PIN_PC6 PINCTRL_PIN(PC_BASE + 6, "PC6") -#define SUNXI_PINCTRL_PIN_PC7 PINCTRL_PIN(PC_BASE + 7, "PC7") -#define SUNXI_PINCTRL_PIN_PC8 PINCTRL_PIN(PC_BASE + 8, "PC8") -#define SUNXI_PINCTRL_PIN_PC9 PINCTRL_PIN(PC_BASE + 9, "PC9") -#define SUNXI_PINCTRL_PIN_PC10 PINCTRL_PIN(PC_BASE + 10, "PC10") -#define SUNXI_PINCTRL_PIN_PC11 PINCTRL_PIN(PC_BASE + 11, "PC11") -#define SUNXI_PINCTRL_PIN_PC12 PINCTRL_PIN(PC_BASE + 12, "PC12") -#define SUNXI_PINCTRL_PIN_PC13 PINCTRL_PIN(PC_BASE + 13, "PC13") -#define SUNXI_PINCTRL_PIN_PC14 PINCTRL_PIN(PC_BASE + 14, "PC14") -#define SUNXI_PINCTRL_PIN_PC15 PINCTRL_PIN(PC_BASE + 15, "PC15") -#define SUNXI_PINCTRL_PIN_PC16 PINCTRL_PIN(PC_BASE + 16, "PC16") -#define SUNXI_PINCTRL_PIN_PC17 PINCTRL_PIN(PC_BASE + 17, "PC17") -#define SUNXI_PINCTRL_PIN_PC18 PINCTRL_PIN(PC_BASE + 18, "PC18") -#define SUNXI_PINCTRL_PIN_PC19 PINCTRL_PIN(PC_BASE + 19, "PC19") -#define SUNXI_PINCTRL_PIN_PC20 PINCTRL_PIN(PC_BASE + 20, "PC20") -#define SUNXI_PINCTRL_PIN_PC21 PINCTRL_PIN(PC_BASE + 21, "PC21") -#define SUNXI_PINCTRL_PIN_PC22 PINCTRL_PIN(PC_BASE + 22, "PC22") -#define SUNXI_PINCTRL_PIN_PC23 PINCTRL_PIN(PC_BASE + 23, "PC23") -#define SUNXI_PINCTRL_PIN_PC24 PINCTRL_PIN(PC_BASE + 24, "PC24") -#define SUNXI_PINCTRL_PIN_PC25 PINCTRL_PIN(PC_BASE + 25, "PC25") -#define SUNXI_PINCTRL_PIN_PC26 PINCTRL_PIN(PC_BASE + 26, "PC26") -#define SUNXI_PINCTRL_PIN_PC27 PINCTRL_PIN(PC_BASE + 27, "PC27") -#define SUNXI_PINCTRL_PIN_PC28 PINCTRL_PIN(PC_BASE + 28, "PC28") -#define SUNXI_PINCTRL_PIN_PC29 PINCTRL_PIN(PC_BASE + 29, "PC29") -#define SUNXI_PINCTRL_PIN_PC30 PINCTRL_PIN(PC_BASE + 30, "PC30") -#define SUNXI_PINCTRL_PIN_PC31 PINCTRL_PIN(PC_BASE + 31, "PC31") - -#define SUNXI_PINCTRL_PIN_PD0 PINCTRL_PIN(PD_BASE + 0, "PD0") -#define SUNXI_PINCTRL_PIN_PD1 PINCTRL_PIN(PD_BASE + 1, "PD1") -#define SUNXI_PINCTRL_PIN_PD2 PINCTRL_PIN(PD_BASE + 2, "PD2") -#define SUNXI_PINCTRL_PIN_PD3 PINCTRL_PIN(PD_BASE + 3, "PD3") -#define SUNXI_PINCTRL_PIN_PD4 PINCTRL_PIN(PD_BASE + 4, "PD4") -#define SUNXI_PINCTRL_PIN_PD5 PINCTRL_PIN(PD_BASE + 5, "PD5") -#define SUNXI_PINCTRL_PIN_PD6 PINCTRL_PIN(PD_BASE + 6, "PD6") -#define SUNXI_PINCTRL_PIN_PD7 PINCTRL_PIN(PD_BASE + 7, "PD7") -#define SUNXI_PINCTRL_PIN_PD8 PINCTRL_PIN(PD_BASE + 8, "PD8") -#define SUNXI_PINCTRL_PIN_PD9 PINCTRL_PIN(PD_BASE + 9, "PD9") -#define SUNXI_PINCTRL_PIN_PD10 PINCTRL_PIN(PD_BASE + 10, "PD10") -#define SUNXI_PINCTRL_PIN_PD11 PINCTRL_PIN(PD_BASE + 11, "PD11") -#define SUNXI_PINCTRL_PIN_PD12 PINCTRL_PIN(PD_BASE + 12, "PD12") -#define SUNXI_PINCTRL_PIN_PD13 PINCTRL_PIN(PD_BASE + 13, "PD13") -#define SUNXI_PINCTRL_PIN_PD14 PINCTRL_PIN(PD_BASE + 14, "PD14") -#define SUNXI_PINCTRL_PIN_PD15 PINCTRL_PIN(PD_BASE + 15, "PD15") -#define SUNXI_PINCTRL_PIN_PD16 PINCTRL_PIN(PD_BASE + 16, "PD16") -#define SUNXI_PINCTRL_PIN_PD17 PINCTRL_PIN(PD_BASE + 17, "PD17") -#define SUNXI_PINCTRL_PIN_PD18 PINCTRL_PIN(PD_BASE + 18, "PD18") -#define SUNXI_PINCTRL_PIN_PD19 PINCTRL_PIN(PD_BASE + 19, "PD19") -#define SUNXI_PINCTRL_PIN_PD20 PINCTRL_PIN(PD_BASE + 20, "PD20") -#define SUNXI_PINCTRL_PIN_PD21 PINCTRL_PIN(PD_BASE + 21, "PD21") -#define SUNXI_PINCTRL_PIN_PD22 PINCTRL_PIN(PD_BASE + 22, "PD22") -#define SUNXI_PINCTRL_PIN_PD23 PINCTRL_PIN(PD_BASE + 23, "PD23") -#define SUNXI_PINCTRL_PIN_PD24 PINCTRL_PIN(PD_BASE + 24, "PD24") -#define SUNXI_PINCTRL_PIN_PD25 PINCTRL_PIN(PD_BASE + 25, "PD25") -#define SUNXI_PINCTRL_PIN_PD26 PINCTRL_PIN(PD_BASE + 26, "PD26") -#define SUNXI_PINCTRL_PIN_PD27 PINCTRL_PIN(PD_BASE + 27, "PD27") -#define SUNXI_PINCTRL_PIN_PD28 PINCTRL_PIN(PD_BASE + 28, "PD28") -#define SUNXI_PINCTRL_PIN_PD29 PINCTRL_PIN(PD_BASE + 29, "PD29") -#define SUNXI_PINCTRL_PIN_PD30 PINCTRL_PIN(PD_BASE + 30, "PD30") -#define SUNXI_PINCTRL_PIN_PD31 PINCTRL_PIN(PD_BASE + 31, "PD31") - -#define SUNXI_PINCTRL_PIN_PE0 PINCTRL_PIN(PE_BASE + 0, "PE0") -#define SUNXI_PINCTRL_PIN_PE1 PINCTRL_PIN(PE_BASE + 1, "PE1") -#define SUNXI_PINCTRL_PIN_PE2 PINCTRL_PIN(PE_BASE + 2, "PE2") -#define SUNXI_PINCTRL_PIN_PE3 PINCTRL_PIN(PE_BASE + 3, "PE3") -#define SUNXI_PINCTRL_PIN_PE4 PINCTRL_PIN(PE_BASE + 4, "PE4") -#define SUNXI_PINCTRL_PIN_PE5 PINCTRL_PIN(PE_BASE + 5, "PE5") -#define SUNXI_PINCTRL_PIN_PE6 PINCTRL_PIN(PE_BASE + 6, "PE6") -#define SUNXI_PINCTRL_PIN_PE7 PINCTRL_PIN(PE_BASE + 7, "PE7") -#define SUNXI_PINCTRL_PIN_PE8 PINCTRL_PIN(PE_BASE + 8, "PE8") -#define SUNXI_PINCTRL_PIN_PE9 PINCTRL_PIN(PE_BASE + 9, "PE9") -#define SUNXI_PINCTRL_PIN_PE10 PINCTRL_PIN(PE_BASE + 10, "PE10") -#define SUNXI_PINCTRL_PIN_PE11 PINCTRL_PIN(PE_BASE + 11, "PE11") -#define SUNXI_PINCTRL_PIN_PE12 PINCTRL_PIN(PE_BASE + 12, "PE12") -#define SUNXI_PINCTRL_PIN_PE13 PINCTRL_PIN(PE_BASE + 13, "PE13") -#define SUNXI_PINCTRL_PIN_PE14 PINCTRL_PIN(PE_BASE + 14, "PE14") -#define SUNXI_PINCTRL_PIN_PE15 PINCTRL_PIN(PE_BASE + 15, "PE15") -#define SUNXI_PINCTRL_PIN_PE16 PINCTRL_PIN(PE_BASE + 16, "PE16") -#define SUNXI_PINCTRL_PIN_PE17 PINCTRL_PIN(PE_BASE + 17, "PE17") -#define SUNXI_PINCTRL_PIN_PE18 PINCTRL_PIN(PE_BASE + 18, "PE18") -#define SUNXI_PINCTRL_PIN_PE19 PINCTRL_PIN(PE_BASE + 19, "PE19") -#define SUNXI_PINCTRL_PIN_PE20 PINCTRL_PIN(PE_BASE + 20, "PE20") -#define SUNXI_PINCTRL_PIN_PE21 PINCTRL_PIN(PE_BASE + 21, "PE21") -#define SUNXI_PINCTRL_PIN_PE22 PINCTRL_PIN(PE_BASE + 22, "PE22") -#define SUNXI_PINCTRL_PIN_PE23 PINCTRL_PIN(PE_BASE + 23, "PE23") -#define SUNXI_PINCTRL_PIN_PE24 PINCTRL_PIN(PE_BASE + 24, "PE24") -#define SUNXI_PINCTRL_PIN_PE25 PINCTRL_PIN(PE_BASE + 25, "PE25") -#define SUNXI_PINCTRL_PIN_PE26 PINCTRL_PIN(PE_BASE + 26, "PE26") -#define SUNXI_PINCTRL_PIN_PE27 PINCTRL_PIN(PE_BASE + 27, "PE27") -#define SUNXI_PINCTRL_PIN_PE28 PINCTRL_PIN(PE_BASE + 28, "PE28") -#define SUNXI_PINCTRL_PIN_PE29 PINCTRL_PIN(PE_BASE + 29, "PE29") -#define SUNXI_PINCTRL_PIN_PE30 PINCTRL_PIN(PE_BASE + 30, "PE30") -#define SUNXI_PINCTRL_PIN_PE31 PINCTRL_PIN(PE_BASE + 31, "PE31") - -#define SUNXI_PINCTRL_PIN_PF0 PINCTRL_PIN(PF_BASE + 0, "PF0") -#define SUNXI_PINCTRL_PIN_PF1 PINCTRL_PIN(PF_BASE + 1, "PF1") -#define SUNXI_PINCTRL_PIN_PF2 PINCTRL_PIN(PF_BASE + 2, "PF2") -#define SUNXI_PINCTRL_PIN_PF3 PINCTRL_PIN(PF_BASE + 3, "PF3") -#define SUNXI_PINCTRL_PIN_PF4 PINCTRL_PIN(PF_BASE + 4, "PF4") -#define SUNXI_PINCTRL_PIN_PF5 PINCTRL_PIN(PF_BASE + 5, "PF5") -#define SUNXI_PINCTRL_PIN_PF6 PINCTRL_PIN(PF_BASE + 6, "PF6") -#define SUNXI_PINCTRL_PIN_PF7 PINCTRL_PIN(PF_BASE + 7, "PF7") -#define SUNXI_PINCTRL_PIN_PF8 PINCTRL_PIN(PF_BASE + 8, "PF8") -#define SUNXI_PINCTRL_PIN_PF9 PINCTRL_PIN(PF_BASE + 9, "PF9") -#define SUNXI_PINCTRL_PIN_PF10 PINCTRL_PIN(PF_BASE + 10, "PF10") -#define SUNXI_PINCTRL_PIN_PF11 PINCTRL_PIN(PF_BASE + 11, "PF11") -#define SUNXI_PINCTRL_PIN_PF12 PINCTRL_PIN(PF_BASE + 12, "PF12") -#define SUNXI_PINCTRL_PIN_PF13 PINCTRL_PIN(PF_BASE + 13, "PF13") -#define SUNXI_PINCTRL_PIN_PF14 PINCTRL_PIN(PF_BASE + 14, "PF14") -#define SUNXI_PINCTRL_PIN_PF15 PINCTRL_PIN(PF_BASE + 15, "PF15") -#define SUNXI_PINCTRL_PIN_PF16 PINCTRL_PIN(PF_BASE + 16, "PF16") -#define SUNXI_PINCTRL_PIN_PF17 PINCTRL_PIN(PF_BASE + 17, "PF17") -#define SUNXI_PINCTRL_PIN_PF18 PINCTRL_PIN(PF_BASE + 18, "PF18") -#define SUNXI_PINCTRL_PIN_PF19 PINCTRL_PIN(PF_BASE + 19, "PF19") -#define SUNXI_PINCTRL_PIN_PF20 PINCTRL_PIN(PF_BASE + 20, "PF20") -#define SUNXI_PINCTRL_PIN_PF21 PINCTRL_PIN(PF_BASE + 21, "PF21") -#define SUNXI_PINCTRL_PIN_PF22 PINCTRL_PIN(PF_BASE + 22, "PF22") -#define SUNXI_PINCTRL_PIN_PF23 PINCTRL_PIN(PF_BASE + 23, "PF23") -#define SUNXI_PINCTRL_PIN_PF24 PINCTRL_PIN(PF_BASE + 24, "PF24") -#define SUNXI_PINCTRL_PIN_PF25 PINCTRL_PIN(PF_BASE + 25, "PF25") -#define SUNXI_PINCTRL_PIN_PF26 PINCTRL_PIN(PF_BASE + 26, "PF26") -#define SUNXI_PINCTRL_PIN_PF27 PINCTRL_PIN(PF_BASE + 27, "PF27") -#define SUNXI_PINCTRL_PIN_PF28 PINCTRL_PIN(PF_BASE + 28, "PF28") -#define SUNXI_PINCTRL_PIN_PF29 PINCTRL_PIN(PF_BASE + 29, "PF29") -#define SUNXI_PINCTRL_PIN_PF30 PINCTRL_PIN(PF_BASE + 30, "PF30") -#define SUNXI_PINCTRL_PIN_PF31 PINCTRL_PIN(PF_BASE + 31, "PF31") - -#define SUNXI_PINCTRL_PIN_PG0 PINCTRL_PIN(PG_BASE + 0, "PG0") -#define SUNXI_PINCTRL_PIN_PG1 PINCTRL_PIN(PG_BASE + 1, "PG1") -#define SUNXI_PINCTRL_PIN_PG2 PINCTRL_PIN(PG_BASE + 2, "PG2") -#define SUNXI_PINCTRL_PIN_PG3 PINCTRL_PIN(PG_BASE + 3, "PG3") -#define SUNXI_PINCTRL_PIN_PG4 PINCTRL_PIN(PG_BASE + 4, "PG4") -#define SUNXI_PINCTRL_PIN_PG5 PINCTRL_PIN(PG_BASE + 5, "PG5") -#define SUNXI_PINCTRL_PIN_PG6 PINCTRL_PIN(PG_BASE + 6, "PG6") -#define SUNXI_PINCTRL_PIN_PG7 PINCTRL_PIN(PG_BASE + 7, "PG7") -#define SUNXI_PINCTRL_PIN_PG8 PINCTRL_PIN(PG_BASE + 8, "PG8") -#define SUNXI_PINCTRL_PIN_PG9 PINCTRL_PIN(PG_BASE + 9, "PG9") -#define SUNXI_PINCTRL_PIN_PG10 PINCTRL_PIN(PG_BASE + 10, "PG10") -#define SUNXI_PINCTRL_PIN_PG11 PINCTRL_PIN(PG_BASE + 11, "PG11") -#define SUNXI_PINCTRL_PIN_PG12 PINCTRL_PIN(PG_BASE + 12, "PG12") -#define SUNXI_PINCTRL_PIN_PG13 PINCTRL_PIN(PG_BASE + 13, "PG13") -#define SUNXI_PINCTRL_PIN_PG14 PINCTRL_PIN(PG_BASE + 14, "PG14") -#define SUNXI_PINCTRL_PIN_PG15 PINCTRL_PIN(PG_BASE + 15, "PG15") -#define SUNXI_PINCTRL_PIN_PG16 PINCTRL_PIN(PG_BASE + 16, "PG16") -#define SUNXI_PINCTRL_PIN_PG17 PINCTRL_PIN(PG_BASE + 17, "PG17") -#define SUNXI_PINCTRL_PIN_PG18 PINCTRL_PIN(PG_BASE + 18, "PG18") -#define SUNXI_PINCTRL_PIN_PG19 PINCTRL_PIN(PG_BASE + 19, "PG19") -#define SUNXI_PINCTRL_PIN_PG20 PINCTRL_PIN(PG_BASE + 20, "PG20") -#define SUNXI_PINCTRL_PIN_PG21 PINCTRL_PIN(PG_BASE + 21, "PG21") -#define SUNXI_PINCTRL_PIN_PG22 PINCTRL_PIN(PG_BASE + 22, "PG22") -#define SUNXI_PINCTRL_PIN_PG23 PINCTRL_PIN(PG_BASE + 23, "PG23") -#define SUNXI_PINCTRL_PIN_PG24 PINCTRL_PIN(PG_BASE + 24, "PG24") -#define SUNXI_PINCTRL_PIN_PG25 PINCTRL_PIN(PG_BASE + 25, "PG25") -#define SUNXI_PINCTRL_PIN_PG26 PINCTRL_PIN(PG_BASE + 26, "PG26") -#define SUNXI_PINCTRL_PIN_PG27 PINCTRL_PIN(PG_BASE + 27, "PG27") -#define SUNXI_PINCTRL_PIN_PG28 PINCTRL_PIN(PG_BASE + 28, "PG28") -#define SUNXI_PINCTRL_PIN_PG29 PINCTRL_PIN(PG_BASE + 29, "PG29") -#define SUNXI_PINCTRL_PIN_PG30 PINCTRL_PIN(PG_BASE + 30, "PG30") -#define SUNXI_PINCTRL_PIN_PG31 PINCTRL_PIN(PG_BASE + 31, "PG31") - -#define SUNXI_PINCTRL_PIN_PH0 PINCTRL_PIN(PH_BASE + 0, "PH0") -#define SUNXI_PINCTRL_PIN_PH1 PINCTRL_PIN(PH_BASE + 1, "PH1") -#define SUNXI_PINCTRL_PIN_PH2 PINCTRL_PIN(PH_BASE + 2, "PH2") -#define SUNXI_PINCTRL_PIN_PH3 PINCTRL_PIN(PH_BASE + 3, "PH3") -#define SUNXI_PINCTRL_PIN_PH4 PINCTRL_PIN(PH_BASE + 4, "PH4") -#define SUNXI_PINCTRL_PIN_PH5 PINCTRL_PIN(PH_BASE + 5, "PH5") -#define SUNXI_PINCTRL_PIN_PH6 PINCTRL_PIN(PH_BASE + 6, "PH6") -#define SUNXI_PINCTRL_PIN_PH7 PINCTRL_PIN(PH_BASE + 7, "PH7") -#define SUNXI_PINCTRL_PIN_PH8 PINCTRL_PIN(PH_BASE + 8, "PH8") -#define SUNXI_PINCTRL_PIN_PH9 PINCTRL_PIN(PH_BASE + 9, "PH9") -#define SUNXI_PINCTRL_PIN_PH10 PINCTRL_PIN(PH_BASE + 10, "PH10") -#define SUNXI_PINCTRL_PIN_PH11 PINCTRL_PIN(PH_BASE + 11, "PH11") -#define SUNXI_PINCTRL_PIN_PH12 PINCTRL_PIN(PH_BASE + 12, "PH12") -#define SUNXI_PINCTRL_PIN_PH13 PINCTRL_PIN(PH_BASE + 13, "PH13") -#define SUNXI_PINCTRL_PIN_PH14 PINCTRL_PIN(PH_BASE + 14, "PH14") -#define SUNXI_PINCTRL_PIN_PH15 PINCTRL_PIN(PH_BASE + 15, "PH15") -#define SUNXI_PINCTRL_PIN_PH16 PINCTRL_PIN(PH_BASE + 16, "PH16") -#define SUNXI_PINCTRL_PIN_PH17 PINCTRL_PIN(PH_BASE + 17, "PH17") -#define SUNXI_PINCTRL_PIN_PH18 PINCTRL_PIN(PH_BASE + 18, "PH18") -#define SUNXI_PINCTRL_PIN_PH19 PINCTRL_PIN(PH_BASE + 19, "PH19") -#define SUNXI_PINCTRL_PIN_PH20 PINCTRL_PIN(PH_BASE + 20, "PH20") -#define SUNXI_PINCTRL_PIN_PH21 PINCTRL_PIN(PH_BASE + 21, "PH21") -#define SUNXI_PINCTRL_PIN_PH22 PINCTRL_PIN(PH_BASE + 22, "PH22") -#define SUNXI_PINCTRL_PIN_PH23 PINCTRL_PIN(PH_BASE + 23, "PH23") -#define SUNXI_PINCTRL_PIN_PH24 PINCTRL_PIN(PH_BASE + 24, "PH24") -#define SUNXI_PINCTRL_PIN_PH25 PINCTRL_PIN(PH_BASE + 25, "PH25") -#define SUNXI_PINCTRL_PIN_PH26 PINCTRL_PIN(PH_BASE + 26, "PH26") -#define SUNXI_PINCTRL_PIN_PH27 PINCTRL_PIN(PH_BASE + 27, "PH27") -#define SUNXI_PINCTRL_PIN_PH28 PINCTRL_PIN(PH_BASE + 28, "PH28") -#define SUNXI_PINCTRL_PIN_PH29 PINCTRL_PIN(PH_BASE + 29, "PH29") -#define SUNXI_PINCTRL_PIN_PH30 PINCTRL_PIN(PH_BASE + 30, "PH30") -#define SUNXI_PINCTRL_PIN_PH31 PINCTRL_PIN(PH_BASE + 31, "PH31") - -#define SUNXI_PINCTRL_PIN_PI0 PINCTRL_PIN(PI_BASE + 0, "PI0") -#define SUNXI_PINCTRL_PIN_PI1 PINCTRL_PIN(PI_BASE + 1, "PI1") -#define SUNXI_PINCTRL_PIN_PI2 PINCTRL_PIN(PI_BASE + 2, "PI2") -#define SUNXI_PINCTRL_PIN_PI3 PINCTRL_PIN(PI_BASE + 3, "PI3") -#define SUNXI_PINCTRL_PIN_PI4 PINCTRL_PIN(PI_BASE + 4, "PI4") -#define SUNXI_PINCTRL_PIN_PI5 PINCTRL_PIN(PI_BASE + 5, "PI5") -#define SUNXI_PINCTRL_PIN_PI6 PINCTRL_PIN(PI_BASE + 6, "PI6") -#define SUNXI_PINCTRL_PIN_PI7 PINCTRL_PIN(PI_BASE + 7, "PI7") -#define SUNXI_PINCTRL_PIN_PI8 PINCTRL_PIN(PI_BASE + 8, "PI8") -#define SUNXI_PINCTRL_PIN_PI9 PINCTRL_PIN(PI_BASE + 9, "PI9") -#define SUNXI_PINCTRL_PIN_PI10 PINCTRL_PIN(PI_BASE + 10, "PI10") -#define SUNXI_PINCTRL_PIN_PI11 PINCTRL_PIN(PI_BASE + 11, "PI11") -#define SUNXI_PINCTRL_PIN_PI12 PINCTRL_PIN(PI_BASE + 12, "PI12") -#define SUNXI_PINCTRL_PIN_PI13 PINCTRL_PIN(PI_BASE + 13, "PI13") -#define SUNXI_PINCTRL_PIN_PI14 PINCTRL_PIN(PI_BASE + 14, "PI14") -#define SUNXI_PINCTRL_PIN_PI15 PINCTRL_PIN(PI_BASE + 15, "PI15") -#define SUNXI_PINCTRL_PIN_PI16 PINCTRL_PIN(PI_BASE + 16, "PI16") -#define SUNXI_PINCTRL_PIN_PI17 PINCTRL_PIN(PI_BASE + 17, "PI17") -#define SUNXI_PINCTRL_PIN_PI18 PINCTRL_PIN(PI_BASE + 18, "PI18") -#define SUNXI_PINCTRL_PIN_PI19 PINCTRL_PIN(PI_BASE + 19, "PI19") -#define SUNXI_PINCTRL_PIN_PI20 PINCTRL_PIN(PI_BASE + 20, "PI20") -#define SUNXI_PINCTRL_PIN_PI21 PINCTRL_PIN(PI_BASE + 21, "PI21") -#define SUNXI_PINCTRL_PIN_PI22 PINCTRL_PIN(PI_BASE + 22, "PI22") -#define SUNXI_PINCTRL_PIN_PI23 PINCTRL_PIN(PI_BASE + 23, "PI23") -#define SUNXI_PINCTRL_PIN_PI24 PINCTRL_PIN(PI_BASE + 24, "PI24") -#define SUNXI_PINCTRL_PIN_PI25 PINCTRL_PIN(PI_BASE + 25, "PI25") -#define SUNXI_PINCTRL_PIN_PI26 PINCTRL_PIN(PI_BASE + 26, "PI26") -#define SUNXI_PINCTRL_PIN_PI27 PINCTRL_PIN(PI_BASE + 27, "PI27") -#define SUNXI_PINCTRL_PIN_PI28 PINCTRL_PIN(PI_BASE + 28, "PI28") -#define SUNXI_PINCTRL_PIN_PI29 PINCTRL_PIN(PI_BASE + 29, "PI29") -#define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30") -#define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31") - -#define SUNXI_PIN_NAME_MAX_LEN 5 - -#define BANK_MEM_SIZE 0x24 -#define MUX_REGS_OFFSET 0x0 -#define DATA_REGS_OFFSET 0x10 -#define DLEVEL_REGS_OFFSET 0x14 -#define PULL_REGS_OFFSET 0x1c - -#define PINS_PER_BANK 32 -#define MUX_PINS_PER_REG 8 -#define MUX_PINS_BITS 4 -#define MUX_PINS_MASK 0x0f -#define DATA_PINS_PER_REG 32 -#define DATA_PINS_BITS 1 -#define DATA_PINS_MASK 0x01 -#define DLEVEL_PINS_PER_REG 16 -#define DLEVEL_PINS_BITS 2 -#define DLEVEL_PINS_MASK 0x03 -#define PULL_PINS_PER_REG 16 -#define PULL_PINS_BITS 2 -#define PULL_PINS_MASK 0x03 - -struct sunxi_desc_function { - const char *name; - u8 muxval; -}; - -struct sunxi_desc_pin { - struct pinctrl_pin_desc pin; - struct sunxi_desc_function *functions; -}; - -struct sunxi_pinctrl_desc { - const struct sunxi_desc_pin *pins; - int npins; - struct pinctrl_gpio_range *ranges; - int nranges; -}; - -struct sunxi_pinctrl_function { - const char *name; - const char **groups; - unsigned ngroups; -}; - -struct sunxi_pinctrl_group { - const char *name; - unsigned long config; - unsigned pin; -}; - -struct sunxi_pinctrl { - void __iomem *membase; - struct gpio_chip *chip; - struct sunxi_pinctrl_desc *desc; - struct device *dev; - struct sunxi_pinctrl_function *functions; - unsigned nfunctions; - struct sunxi_pinctrl_group *groups; - unsigned ngroups; - struct pinctrl_dev *pctl_dev; -}; - -#define SUNXI_PIN(_pin, ...) \ - { \ - .pin = _pin, \ - .functions = (struct sunxi_desc_function[]){ \ - __VA_ARGS__, { } }, \ - } - -#define SUNXI_FUNCTION(_val, _name) \ - { \ - .name = _name, \ - .muxval = _val, \ - } - -/* - * The sunXi PIO registers are organized as is: - * 0x00 - 0x0c Muxing values. - * 8 pins per register, each pin having a 4bits value - * 0x10 Pin values - * 32 bits per register, each pin corresponding to one bit - * 0x14 - 0x18 Drive level - * 16 pins per register, each pin having a 2bits value - * 0x1c - 0x20 Pull-Up values - * 16 pins per register, each pin having a 2bits value - * - * This is for the first bank. Each bank will have the same layout, - * with an offset being a multiple of 0x24. - * - * The following functions calculate from the pin number the register - * and the bit offset that we should access. - */ -static inline u32 sunxi_mux_reg(u16 pin) -{ - u8 bank = pin / PINS_PER_BANK; - u32 offset = bank * BANK_MEM_SIZE; - offset += MUX_REGS_OFFSET; - offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; - return round_down(offset, 4); -} - -static inline u32 sunxi_mux_offset(u16 pin) -{ - u32 pin_num = pin % MUX_PINS_PER_REG; - return pin_num * MUX_PINS_BITS; -} - -static inline u32 sunxi_data_reg(u16 pin) -{ - u8 bank = pin / PINS_PER_BANK; - u32 offset = bank * BANK_MEM_SIZE; - offset += DATA_REGS_OFFSET; - offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; - return round_down(offset, 4); -} - -static inline u32 sunxi_data_offset(u16 pin) -{ - u32 pin_num = pin % DATA_PINS_PER_REG; - return pin_num * DATA_PINS_BITS; -} - -static inline u32 sunxi_dlevel_reg(u16 pin) -{ - u8 bank = pin / PINS_PER_BANK; - u32 offset = bank * BANK_MEM_SIZE; - offset += DLEVEL_REGS_OFFSET; - offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; - return round_down(offset, 4); -} - -static inline u32 sunxi_dlevel_offset(u16 pin) -{ - u32 pin_num = pin % DLEVEL_PINS_PER_REG; - return pin_num * DLEVEL_PINS_BITS; -} - -static inline u32 sunxi_pull_reg(u16 pin) -{ - u8 bank = pin / PINS_PER_BANK; - u32 offset = bank * BANK_MEM_SIZE; - offset += PULL_REGS_OFFSET; - offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; - return round_down(offset, 4); -} - -static inline u32 sunxi_pull_offset(u16 pin) -{ - u32 pin_num = pin % PULL_PINS_PER_REG; - return pin_num * PULL_PINS_BITS; -} - -#endif /* __PINCTRL_SUNXI_H */ diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c new file mode 100644 index 00000000000..26ca6855f47 --- /dev/null +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -0,0 +1,874 @@ +/* + * Abilis Systems TB10x pin control driver + * + * Copyright (C) Abilis Systems 2012 + * + * Author: Christian Ruppert <christian.ruppert@abilis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/stringify.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/machine.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/slab.h> + +#include "pinctrl-utils.h" + +#define TB10X_PORT1 (0) +#define TB10X_PORT2 (16) +#define TB10X_PORT3 (32) +#define TB10X_PORT4 (48) +#define TB10X_PORT5 (128) +#define TB10X_PORT6 (64) +#define TB10X_PORT7 (80) +#define TB10X_PORT8 (96) +#define TB10X_PORT9 (112) +#define TB10X_GPIOS (256) + +#define PCFG_PORT_BITWIDTH (2) +#define PCFG_PORT_MASK(PORT) \ + (((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT))) + +static const struct pinctrl_pin_desc tb10x_pins[] = { + /* Port 1 */ + PINCTRL_PIN(TB10X_PORT1 + 0, "MICLK_S0"), + PINCTRL_PIN(TB10X_PORT1 + 1, "MISTRT_S0"), + PINCTRL_PIN(TB10X_PORT1 + 2, "MIVAL_S0"), + PINCTRL_PIN(TB10X_PORT1 + 3, "MDI_S0"), + PINCTRL_PIN(TB10X_PORT1 + 4, "GPIOA0"), + PINCTRL_PIN(TB10X_PORT1 + 5, "GPIOA1"), + PINCTRL_PIN(TB10X_PORT1 + 6, "GPIOA2"), + PINCTRL_PIN(TB10X_PORT1 + 7, "MDI_S1"), + PINCTRL_PIN(TB10X_PORT1 + 8, "MIVAL_S1"), + PINCTRL_PIN(TB10X_PORT1 + 9, "MISTRT_S1"), + PINCTRL_PIN(TB10X_PORT1 + 10, "MICLK_S1"), + /* Port 2 */ + PINCTRL_PIN(TB10X_PORT2 + 0, "MICLK_S2"), + PINCTRL_PIN(TB10X_PORT2 + 1, "MISTRT_S2"), + PINCTRL_PIN(TB10X_PORT2 + 2, "MIVAL_S2"), + PINCTRL_PIN(TB10X_PORT2 + 3, "MDI_S2"), + PINCTRL_PIN(TB10X_PORT2 + 4, "GPIOC0"), + PINCTRL_PIN(TB10X_PORT2 + 5, "GPIOC1"), + PINCTRL_PIN(TB10X_PORT2 + 6, "GPIOC2"), + PINCTRL_PIN(TB10X_PORT2 + 7, "MDI_S3"), + PINCTRL_PIN(TB10X_PORT2 + 8, "MIVAL_S3"), + PINCTRL_PIN(TB10X_PORT2 + 9, "MISTRT_S3"), + PINCTRL_PIN(TB10X_PORT2 + 10, "MICLK_S3"), + /* Port 3 */ + PINCTRL_PIN(TB10X_PORT3 + 0, "MICLK_S4"), + PINCTRL_PIN(TB10X_PORT3 + 1, "MISTRT_S4"), + PINCTRL_PIN(TB10X_PORT3 + 2, "MIVAL_S4"), + PINCTRL_PIN(TB10X_PORT3 + 3, "MDI_S4"), + PINCTRL_PIN(TB10X_PORT3 + 4, "GPIOE0"), + PINCTRL_PIN(TB10X_PORT3 + 5, "GPIOE1"), + PINCTRL_PIN(TB10X_PORT3 + 6, "GPIOE2"), + PINCTRL_PIN(TB10X_PORT3 + 7, "MDI_S5"), + PINCTRL_PIN(TB10X_PORT3 + 8, "MIVAL_S5"), + PINCTRL_PIN(TB10X_PORT3 + 9, "MISTRT_S5"), + PINCTRL_PIN(TB10X_PORT3 + 10, "MICLK_S5"), + /* Port 4 */ + PINCTRL_PIN(TB10X_PORT4 + 0, "MICLK_S6"), + PINCTRL_PIN(TB10X_PORT4 + 1, "MISTRT_S6"), + PINCTRL_PIN(TB10X_PORT4 + 2, "MIVAL_S6"), + PINCTRL_PIN(TB10X_PORT4 + 3, "MDI_S6"), + PINCTRL_PIN(TB10X_PORT4 + 4, "GPIOG0"), + PINCTRL_PIN(TB10X_PORT4 + 5, "GPIOG1"), + PINCTRL_PIN(TB10X_PORT4 + 6, "GPIOG2"), + PINCTRL_PIN(TB10X_PORT4 + 7, "MDI_S7"), + PINCTRL_PIN(TB10X_PORT4 + 8, "MIVAL_S7"), + PINCTRL_PIN(TB10X_PORT4 + 9, "MISTRT_S7"), + PINCTRL_PIN(TB10X_PORT4 + 10, "MICLK_S7"), + /* Port 5 */ + PINCTRL_PIN(TB10X_PORT5 + 0, "PC_CE1N"), + PINCTRL_PIN(TB10X_PORT5 + 1, "PC_CE2N"), + PINCTRL_PIN(TB10X_PORT5 + 2, "PC_REGN"), + PINCTRL_PIN(TB10X_PORT5 + 3, "PC_INPACKN"), + PINCTRL_PIN(TB10X_PORT5 + 4, "PC_OEN"), + PINCTRL_PIN(TB10X_PORT5 + 5, "PC_WEN"), + PINCTRL_PIN(TB10X_PORT5 + 6, "PC_IORDN"), + PINCTRL_PIN(TB10X_PORT5 + 7, "PC_IOWRN"), + PINCTRL_PIN(TB10X_PORT5 + 8, "PC_RDYIRQN"), + PINCTRL_PIN(TB10X_PORT5 + 9, "PC_WAITN"), + PINCTRL_PIN(TB10X_PORT5 + 10, "PC_A0"), + PINCTRL_PIN(TB10X_PORT5 + 11, "PC_A1"), + PINCTRL_PIN(TB10X_PORT5 + 12, "PC_A2"), + PINCTRL_PIN(TB10X_PORT5 + 13, "PC_A3"), + PINCTRL_PIN(TB10X_PORT5 + 14, "PC_A4"), + PINCTRL_PIN(TB10X_PORT5 + 15, "PC_A5"), + PINCTRL_PIN(TB10X_PORT5 + 16, "PC_A6"), + PINCTRL_PIN(TB10X_PORT5 + 17, "PC_A7"), + PINCTRL_PIN(TB10X_PORT5 + 18, "PC_A8"), + PINCTRL_PIN(TB10X_PORT5 + 19, "PC_A9"), + PINCTRL_PIN(TB10X_PORT5 + 20, "PC_A10"), + PINCTRL_PIN(TB10X_PORT5 + 21, "PC_A11"), + PINCTRL_PIN(TB10X_PORT5 + 22, "PC_A12"), + PINCTRL_PIN(TB10X_PORT5 + 23, "PC_A13"), + PINCTRL_PIN(TB10X_PORT5 + 24, "PC_A14"), + PINCTRL_PIN(TB10X_PORT5 + 25, "PC_D0"), + PINCTRL_PIN(TB10X_PORT5 + 26, "PC_D1"), + PINCTRL_PIN(TB10X_PORT5 + 27, "PC_D2"), + PINCTRL_PIN(TB10X_PORT5 + 28, "PC_D3"), + PINCTRL_PIN(TB10X_PORT5 + 29, "PC_D4"), + PINCTRL_PIN(TB10X_PORT5 + 30, "PC_D5"), + PINCTRL_PIN(TB10X_PORT5 + 31, "PC_D6"), + PINCTRL_PIN(TB10X_PORT5 + 32, "PC_D7"), + PINCTRL_PIN(TB10X_PORT5 + 33, "PC_MOSTRT"), + PINCTRL_PIN(TB10X_PORT5 + 34, "PC_MOVAL"), + PINCTRL_PIN(TB10X_PORT5 + 35, "PC_MDO0"), + PINCTRL_PIN(TB10X_PORT5 + 36, "PC_MDO1"), + PINCTRL_PIN(TB10X_PORT5 + 37, "PC_MDO2"), + PINCTRL_PIN(TB10X_PORT5 + 38, "PC_MDO3"), + PINCTRL_PIN(TB10X_PORT5 + 39, "PC_MDO4"), + PINCTRL_PIN(TB10X_PORT5 + 40, "PC_MDO5"), + PINCTRL_PIN(TB10X_PORT5 + 41, "PC_MDO6"), + PINCTRL_PIN(TB10X_PORT5 + 42, "PC_MDO7"), + PINCTRL_PIN(TB10X_PORT5 + 43, "PC_MISTRT"), + PINCTRL_PIN(TB10X_PORT5 + 44, "PC_MIVAL"), + PINCTRL_PIN(TB10X_PORT5 + 45, "PC_MDI0"), + PINCTRL_PIN(TB10X_PORT5 + 46, "PC_MDI1"), + PINCTRL_PIN(TB10X_PORT5 + 47, "PC_MDI2"), + PINCTRL_PIN(TB10X_PORT5 + 48, "PC_MDI3"), + PINCTRL_PIN(TB10X_PORT5 + 49, "PC_MDI4"), + PINCTRL_PIN(TB10X_PORT5 + 50, "PC_MDI5"), + PINCTRL_PIN(TB10X_PORT5 + 51, "PC_MDI6"), + PINCTRL_PIN(TB10X_PORT5 + 52, "PC_MDI7"), + PINCTRL_PIN(TB10X_PORT5 + 53, "PC_MICLK"), + /* Port 6 */ + PINCTRL_PIN(TB10X_PORT6 + 0, "T_MOSTRT_S0"), + PINCTRL_PIN(TB10X_PORT6 + 1, "T_MOVAL_S0"), + PINCTRL_PIN(TB10X_PORT6 + 2, "T_MDO_S0"), + PINCTRL_PIN(TB10X_PORT6 + 3, "T_MOSTRT_S1"), + PINCTRL_PIN(TB10X_PORT6 + 4, "T_MOVAL_S1"), + PINCTRL_PIN(TB10X_PORT6 + 5, "T_MDO_S1"), + PINCTRL_PIN(TB10X_PORT6 + 6, "T_MOSTRT_S2"), + PINCTRL_PIN(TB10X_PORT6 + 7, "T_MOVAL_S2"), + PINCTRL_PIN(TB10X_PORT6 + 8, "T_MDO_S2"), + PINCTRL_PIN(TB10X_PORT6 + 9, "T_MOSTRT_S3"), + /* Port 7 */ + PINCTRL_PIN(TB10X_PORT7 + 0, "UART0_TXD"), + PINCTRL_PIN(TB10X_PORT7 + 1, "UART0_RXD"), + PINCTRL_PIN(TB10X_PORT7 + 2, "UART0_CTS"), + PINCTRL_PIN(TB10X_PORT7 + 3, "UART0_RTS"), + PINCTRL_PIN(TB10X_PORT7 + 4, "UART1_TXD"), + PINCTRL_PIN(TB10X_PORT7 + 5, "UART1_RXD"), + PINCTRL_PIN(TB10X_PORT7 + 6, "UART1_CTS"), + PINCTRL_PIN(TB10X_PORT7 + 7, "UART1_RTS"), + /* Port 8 */ + PINCTRL_PIN(TB10X_PORT8 + 0, "SPI3_CLK"), + PINCTRL_PIN(TB10X_PORT8 + 1, "SPI3_MISO"), + PINCTRL_PIN(TB10X_PORT8 + 2, "SPI3_MOSI"), + PINCTRL_PIN(TB10X_PORT8 + 3, "SPI3_SSN"), + /* Port 9 */ + PINCTRL_PIN(TB10X_PORT9 + 0, "SPI1_CLK"), + PINCTRL_PIN(TB10X_PORT9 + 1, "SPI1_MISO"), + PINCTRL_PIN(TB10X_PORT9 + 2, "SPI1_MOSI"), + PINCTRL_PIN(TB10X_PORT9 + 3, "SPI1_SSN0"), + PINCTRL_PIN(TB10X_PORT9 + 4, "SPI1_SSN1"), + /* Unmuxed GPIOs */ + PINCTRL_PIN(TB10X_GPIOS + 0, "GPIOB0"), + PINCTRL_PIN(TB10X_GPIOS + 1, "GPIOB1"), + + PINCTRL_PIN(TB10X_GPIOS + 2, "GPIOD0"), + PINCTRL_PIN(TB10X_GPIOS + 3, "GPIOD1"), + + PINCTRL_PIN(TB10X_GPIOS + 4, "GPIOF0"), + PINCTRL_PIN(TB10X_GPIOS + 5, "GPIOF1"), + + PINCTRL_PIN(TB10X_GPIOS + 6, "GPIOH0"), + PINCTRL_PIN(TB10X_GPIOS + 7, "GPIOH1"), + + PINCTRL_PIN(TB10X_GPIOS + 8, "GPIOI0"), + PINCTRL_PIN(TB10X_GPIOS + 9, "GPIOI1"), + PINCTRL_PIN(TB10X_GPIOS + 10, "GPIOI2"), + PINCTRL_PIN(TB10X_GPIOS + 11, "GPIOI3"), + PINCTRL_PIN(TB10X_GPIOS + 12, "GPIOI4"), + PINCTRL_PIN(TB10X_GPIOS + 13, "GPIOI5"), + PINCTRL_PIN(TB10X_GPIOS + 14, "GPIOI6"), + PINCTRL_PIN(TB10X_GPIOS + 15, "GPIOI7"), + PINCTRL_PIN(TB10X_GPIOS + 16, "GPIOI8"), + PINCTRL_PIN(TB10X_GPIOS + 17, "GPIOI9"), + PINCTRL_PIN(TB10X_GPIOS + 18, "GPIOI10"), + PINCTRL_PIN(TB10X_GPIOS + 19, "GPIOI11"), + + PINCTRL_PIN(TB10X_GPIOS + 20, "GPION0"), + PINCTRL_PIN(TB10X_GPIOS + 21, "GPION1"), + PINCTRL_PIN(TB10X_GPIOS + 22, "GPION2"), + PINCTRL_PIN(TB10X_GPIOS + 23, "GPION3"), +#define MAX_PIN (TB10X_GPIOS + 24) + PINCTRL_PIN(MAX_PIN, "GPION4"), +}; + + +/* Port 1 */ +static const unsigned mis0_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1, + TB10X_PORT1 + 2, TB10X_PORT1 + 3}; +static const unsigned gpioa_pins[] = { TB10X_PORT1 + 4, TB10X_PORT1 + 5, + TB10X_PORT1 + 6}; +static const unsigned mis1_pins[] = { TB10X_PORT1 + 7, TB10X_PORT1 + 8, + TB10X_PORT1 + 9, TB10X_PORT1 + 10}; +static const unsigned mip1_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1, + TB10X_PORT1 + 2, TB10X_PORT1 + 3, + TB10X_PORT1 + 4, TB10X_PORT1 + 5, + TB10X_PORT1 + 6, TB10X_PORT1 + 7, + TB10X_PORT1 + 8, TB10X_PORT1 + 9, + TB10X_PORT1 + 10}; + +/* Port 2 */ +static const unsigned mis2_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1, + TB10X_PORT2 + 2, TB10X_PORT2 + 3}; +static const unsigned gpioc_pins[] = { TB10X_PORT2 + 4, TB10X_PORT2 + 5, + TB10X_PORT2 + 6}; +static const unsigned mis3_pins[] = { TB10X_PORT2 + 7, TB10X_PORT2 + 8, + TB10X_PORT2 + 9, TB10X_PORT2 + 10}; +static const unsigned mip3_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1, + TB10X_PORT2 + 2, TB10X_PORT2 + 3, + TB10X_PORT2 + 4, TB10X_PORT2 + 5, + TB10X_PORT2 + 6, TB10X_PORT2 + 7, + TB10X_PORT2 + 8, TB10X_PORT2 + 9, + TB10X_PORT2 + 10}; + +/* Port 3 */ +static const unsigned mis4_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1, + TB10X_PORT3 + 2, TB10X_PORT3 + 3}; +static const unsigned gpioe_pins[] = { TB10X_PORT3 + 4, TB10X_PORT3 + 5, + TB10X_PORT3 + 6}; +static const unsigned mis5_pins[] = { TB10X_PORT3 + 7, TB10X_PORT3 + 8, + TB10X_PORT3 + 9, TB10X_PORT3 + 10}; +static const unsigned mip5_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1, + TB10X_PORT3 + 2, TB10X_PORT3 + 3, + TB10X_PORT3 + 4, TB10X_PORT3 + 5, + TB10X_PORT3 + 6, TB10X_PORT3 + 7, + TB10X_PORT3 + 8, TB10X_PORT3 + 9, + TB10X_PORT3 + 10}; + +/* Port 4 */ +static const unsigned mis6_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1, + TB10X_PORT4 + 2, TB10X_PORT4 + 3}; +static const unsigned gpiog_pins[] = { TB10X_PORT4 + 4, TB10X_PORT4 + 5, + TB10X_PORT4 + 6}; +static const unsigned mis7_pins[] = { TB10X_PORT4 + 7, TB10X_PORT4 + 8, + TB10X_PORT4 + 9, TB10X_PORT4 + 10}; +static const unsigned mip7_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1, + TB10X_PORT4 + 2, TB10X_PORT4 + 3, + TB10X_PORT4 + 4, TB10X_PORT4 + 5, + TB10X_PORT4 + 6, TB10X_PORT4 + 7, + TB10X_PORT4 + 8, TB10X_PORT4 + 9, + TB10X_PORT4 + 10}; + +/* Port 6 */ +static const unsigned mop_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1, + TB10X_PORT6 + 2, TB10X_PORT6 + 3, + TB10X_PORT6 + 4, TB10X_PORT6 + 5, + TB10X_PORT6 + 6, TB10X_PORT6 + 7, + TB10X_PORT6 + 8, TB10X_PORT6 + 9}; +static const unsigned mos0_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1, + TB10X_PORT6 + 2}; +static const unsigned mos1_pins[] = { TB10X_PORT6 + 3, TB10X_PORT6 + 4, + TB10X_PORT6 + 5}; +static const unsigned mos2_pins[] = { TB10X_PORT6 + 6, TB10X_PORT6 + 7, + TB10X_PORT6 + 8}; +static const unsigned mos3_pins[] = { TB10X_PORT6 + 9}; + +/* Port 7 */ +static const unsigned uart0_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1, + TB10X_PORT7 + 2, TB10X_PORT7 + 3}; +static const unsigned uart1_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5, + TB10X_PORT7 + 6, TB10X_PORT7 + 7}; +static const unsigned gpiol_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1, + TB10X_PORT7 + 2, TB10X_PORT7 + 3}; +static const unsigned gpiom_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5, + TB10X_PORT7 + 6, TB10X_PORT7 + 7}; + +/* Port 8 */ +static const unsigned spi3_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1, + TB10X_PORT8 + 2, TB10X_PORT8 + 3}; +static const unsigned jtag_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1, + TB10X_PORT8 + 2, TB10X_PORT8 + 3}; + +/* Port 9 */ +static const unsigned spi1_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1, + TB10X_PORT9 + 2, TB10X_PORT9 + 3, + TB10X_PORT9 + 4}; +static const unsigned gpion_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1, + TB10X_PORT9 + 2, TB10X_PORT9 + 3, + TB10X_PORT9 + 4}; + +/* Port 5 */ +static const unsigned gpioj_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1, + TB10X_PORT5 + 2, TB10X_PORT5 + 3, + TB10X_PORT5 + 4, TB10X_PORT5 + 5, + TB10X_PORT5 + 6, TB10X_PORT5 + 7, + TB10X_PORT5 + 8, TB10X_PORT5 + 9, + TB10X_PORT5 + 10, TB10X_PORT5 + 11, + TB10X_PORT5 + 12, TB10X_PORT5 + 13, + TB10X_PORT5 + 14, TB10X_PORT5 + 15, + TB10X_PORT5 + 16, TB10X_PORT5 + 17, + TB10X_PORT5 + 18, TB10X_PORT5 + 19, + TB10X_PORT5 + 20, TB10X_PORT5 + 21, + TB10X_PORT5 + 22, TB10X_PORT5 + 23, + TB10X_PORT5 + 24, TB10X_PORT5 + 25, + TB10X_PORT5 + 26, TB10X_PORT5 + 27, + TB10X_PORT5 + 28, TB10X_PORT5 + 29, + TB10X_PORT5 + 30, TB10X_PORT5 + 31}; +static const unsigned gpiok_pins[] = { TB10X_PORT5 + 32, TB10X_PORT5 + 33, + TB10X_PORT5 + 34, TB10X_PORT5 + 35, + TB10X_PORT5 + 36, TB10X_PORT5 + 37, + TB10X_PORT5 + 38, TB10X_PORT5 + 39, + TB10X_PORT5 + 40, TB10X_PORT5 + 41, + TB10X_PORT5 + 42, TB10X_PORT5 + 43, + TB10X_PORT5 + 44, TB10X_PORT5 + 45, + TB10X_PORT5 + 46, TB10X_PORT5 + 47, + TB10X_PORT5 + 48, TB10X_PORT5 + 49, + TB10X_PORT5 + 50, TB10X_PORT5 + 51, + TB10X_PORT5 + 52, TB10X_PORT5 + 53}; +static const unsigned ciplus_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1, + TB10X_PORT5 + 2, TB10X_PORT5 + 3, + TB10X_PORT5 + 4, TB10X_PORT5 + 5, + TB10X_PORT5 + 6, TB10X_PORT5 + 7, + TB10X_PORT5 + 8, TB10X_PORT5 + 9, + TB10X_PORT5 + 10, TB10X_PORT5 + 11, + TB10X_PORT5 + 12, TB10X_PORT5 + 13, + TB10X_PORT5 + 14, TB10X_PORT5 + 15, + TB10X_PORT5 + 16, TB10X_PORT5 + 17, + TB10X_PORT5 + 18, TB10X_PORT5 + 19, + TB10X_PORT5 + 20, TB10X_PORT5 + 21, + TB10X_PORT5 + 22, TB10X_PORT5 + 23, + TB10X_PORT5 + 24, TB10X_PORT5 + 25, + TB10X_PORT5 + 26, TB10X_PORT5 + 27, + TB10X_PORT5 + 28, TB10X_PORT5 + 29, + TB10X_PORT5 + 30, TB10X_PORT5 + 31, + TB10X_PORT5 + 32, TB10X_PORT5 + 33, + TB10X_PORT5 + 34, TB10X_PORT5 + 35, + TB10X_PORT5 + 36, TB10X_PORT5 + 37, + TB10X_PORT5 + 38, TB10X_PORT5 + 39, + TB10X_PORT5 + 40, TB10X_PORT5 + 41, + TB10X_PORT5 + 42, TB10X_PORT5 + 43, + TB10X_PORT5 + 44, TB10X_PORT5 + 45, + TB10X_PORT5 + 46, TB10X_PORT5 + 47, + TB10X_PORT5 + 48, TB10X_PORT5 + 49, + TB10X_PORT5 + 50, TB10X_PORT5 + 51, + TB10X_PORT5 + 52, TB10X_PORT5 + 53}; +static const unsigned mcard_pins[] = { TB10X_PORT5 + 3, TB10X_PORT5 + 10, + TB10X_PORT5 + 11, TB10X_PORT5 + 12, + TB10X_PORT5 + 22, TB10X_PORT5 + 23, + TB10X_PORT5 + 33, TB10X_PORT5 + 35, + TB10X_PORT5 + 36, TB10X_PORT5 + 37, + TB10X_PORT5 + 38, TB10X_PORT5 + 39, + TB10X_PORT5 + 40, TB10X_PORT5 + 41, + TB10X_PORT5 + 42, TB10X_PORT5 + 43, + TB10X_PORT5 + 45, TB10X_PORT5 + 46, + TB10X_PORT5 + 47, TB10X_PORT5 + 48, + TB10X_PORT5 + 49, TB10X_PORT5 + 50, + TB10X_PORT5 + 51, TB10X_PORT5 + 52, + TB10X_PORT5 + 53}; +static const unsigned stc0_pins[] = { TB10X_PORT5 + 34, TB10X_PORT5 + 35, + TB10X_PORT5 + 36, TB10X_PORT5 + 37, + TB10X_PORT5 + 38, TB10X_PORT5 + 39, + TB10X_PORT5 + 40}; +static const unsigned stc1_pins[] = { TB10X_PORT5 + 25, TB10X_PORT5 + 26, + TB10X_PORT5 + 27, TB10X_PORT5 + 28, + TB10X_PORT5 + 29, TB10X_PORT5 + 30, + TB10X_PORT5 + 44}; + +/* Unmuxed GPIOs */ +static const unsigned gpiob_pins[] = { TB10X_GPIOS + 0, TB10X_GPIOS + 1}; +static const unsigned gpiod_pins[] = { TB10X_GPIOS + 2, TB10X_GPIOS + 3}; +static const unsigned gpiof_pins[] = { TB10X_GPIOS + 4, TB10X_GPIOS + 5}; +static const unsigned gpioh_pins[] = { TB10X_GPIOS + 6, TB10X_GPIOS + 7}; +static const unsigned gpioi_pins[] = { TB10X_GPIOS + 8, TB10X_GPIOS + 9, + TB10X_GPIOS + 10, TB10X_GPIOS + 11, + TB10X_GPIOS + 12, TB10X_GPIOS + 13, + TB10X_GPIOS + 14, TB10X_GPIOS + 15, + TB10X_GPIOS + 16, TB10X_GPIOS + 17, + TB10X_GPIOS + 18, TB10X_GPIOS + 19}; + +struct tb10x_pinfuncgrp { + const char *name; + const unsigned int *pins; + const unsigned int pincnt; + const int port; + const unsigned int mode; + const int isgpio; +}; +#define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \ + .name = __stringify(NAME), \ + .pins = NAME##_pins, .pincnt = ARRAY_SIZE(NAME##_pins), \ + .port = (PORT), .mode = (MODE), \ + .isgpio = (ISGPIO), \ + } +static const struct tb10x_pinfuncgrp tb10x_pingroups[] = { + DEFPINFUNCGRP(mis0, 0, 0, 0), + DEFPINFUNCGRP(gpioa, 0, 0, 1), + DEFPINFUNCGRP(mis1, 0, 0, 0), + DEFPINFUNCGRP(mip1, 0, 1, 0), + DEFPINFUNCGRP(mis2, 1, 0, 0), + DEFPINFUNCGRP(gpioc, 1, 0, 1), + DEFPINFUNCGRP(mis3, 1, 0, 0), + DEFPINFUNCGRP(mip3, 1, 1, 0), + DEFPINFUNCGRP(mis4, 2, 0, 0), + DEFPINFUNCGRP(gpioe, 2, 0, 1), + DEFPINFUNCGRP(mis5, 2, 0, 0), + DEFPINFUNCGRP(mip5, 2, 1, 0), + DEFPINFUNCGRP(mis6, 3, 0, 0), + DEFPINFUNCGRP(gpiog, 3, 0, 1), + DEFPINFUNCGRP(mis7, 3, 0, 0), + DEFPINFUNCGRP(mip7, 3, 1, 0), + DEFPINFUNCGRP(gpioj, 4, 0, 1), + DEFPINFUNCGRP(gpiok, 4, 0, 1), + DEFPINFUNCGRP(ciplus, 4, 1, 0), + DEFPINFUNCGRP(mcard, 4, 2, 0), + DEFPINFUNCGRP(stc0, 4, 3, 0), + DEFPINFUNCGRP(stc1, 4, 3, 0), + DEFPINFUNCGRP(mop, 5, 0, 0), + DEFPINFUNCGRP(mos0, 5, 1, 0), + DEFPINFUNCGRP(mos1, 5, 1, 0), + DEFPINFUNCGRP(mos2, 5, 1, 0), + DEFPINFUNCGRP(mos3, 5, 1, 0), + DEFPINFUNCGRP(uart0, 6, 0, 0), + DEFPINFUNCGRP(uart1, 6, 0, 0), + DEFPINFUNCGRP(gpiol, 6, 1, 1), + DEFPINFUNCGRP(gpiom, 6, 1, 1), + DEFPINFUNCGRP(spi3, 7, 0, 0), + DEFPINFUNCGRP(jtag, 7, 1, 0), + DEFPINFUNCGRP(spi1, 8, 0, 0), + DEFPINFUNCGRP(gpion, 8, 1, 1), + DEFPINFUNCGRP(gpiob, -1, 0, 1), + DEFPINFUNCGRP(gpiod, -1, 0, 1), + DEFPINFUNCGRP(gpiof, -1, 0, 1), + DEFPINFUNCGRP(gpioh, -1, 0, 1), + DEFPINFUNCGRP(gpioi, -1, 0, 1), +}; +#undef DEFPINFUNCGRP + +struct tb10x_of_pinfunc { + const char *name; + const char *group; +}; + +#define TB10X_PORTS (9) + +/** + * struct tb10x_port - state of an I/O port + * @mode: Node this port is currently in. + * @count: Number of enabled functions which require this port to be + * configured in @mode. + */ +struct tb10x_port { + unsigned int mode; + unsigned int count; +}; + +/** + * struct tb10x_pinctrl - TB10x pin controller internal state + * @pctl: pointer to the pinctrl_dev structure of this pin controller. + * @base: register set base address. + * @pingroups: pointer to an array of the pin groups this driver manages. + * @pinfuncgrpcnt: number of pingroups in @pingroups. + * @pinfuncs: pointer to an array of pin functions this driver manages. + * @pinfuncnt: number of pin functions in @pinfuncs. + * @mutex: mutex for exclusive access to a pin controller's state. + * @ports: current state of each port. + * @gpios: Indicates if a given pin is currently used as GPIO (1) or not (0). + */ +struct tb10x_pinctrl { + struct pinctrl_dev *pctl; + void *base; + const struct tb10x_pinfuncgrp *pingroups; + unsigned int pinfuncgrpcnt; + struct tb10x_of_pinfunc *pinfuncs; + unsigned int pinfuncnt; + struct mutex mutex; + struct tb10x_port ports[TB10X_PORTS]; + DECLARE_BITMAP(gpios, MAX_PIN + 1); +}; + +static inline void tb10x_pinctrl_set_config(struct tb10x_pinctrl *state, + unsigned int port, unsigned int mode) +{ + u32 pcfg; + + if (state->ports[port].count) + return; + + state->ports[port].mode = mode; + + pcfg = ioread32(state->base) & ~(PCFG_PORT_MASK(port)); + pcfg |= (mode << (PCFG_PORT_BITWIDTH * port)) & PCFG_PORT_MASK(port); + iowrite32(pcfg, state->base); +} + +static inline unsigned int tb10x_pinctrl_get_config( + struct tb10x_pinctrl *state, + unsigned int port) +{ + return (ioread32(state->base) & PCFG_PORT_MASK(port)) + >> (PCFG_PORT_BITWIDTH * port); +} + +static int tb10x_get_groups_count(struct pinctrl_dev *pctl) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + return state->pinfuncgrpcnt; +} + +static const char *tb10x_get_group_name(struct pinctrl_dev *pctl, unsigned n) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + return state->pingroups[n].name; +} + +static int tb10x_get_group_pins(struct pinctrl_dev *pctl, unsigned n, + unsigned const **pins, + unsigned * const num_pins) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + + *pins = state->pingroups[n].pins; + *num_pins = state->pingroups[n].pincnt; + + return 0; +} + +static int tb10x_dt_node_to_map(struct pinctrl_dev *pctl, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + const char *string; + unsigned reserved_maps = 0; + int ret = 0; + + if (of_property_read_string(np_config, "abilis,function", &string)) { + pr_err("%s: No abilis,function property in device tree.\n", + np_config->full_name); + return -EINVAL; + } + + *map = NULL; + *num_maps = 0; + + ret = pinctrl_utils_reserve_map(pctl, map, &reserved_maps, + num_maps, 1); + if (ret) + goto out; + + ret = pinctrl_utils_add_map_mux(pctl, map, &reserved_maps, + num_maps, string, np_config->name); + +out: + return ret; +} + +static struct pinctrl_ops tb10x_pinctrl_ops = { + .get_groups_count = tb10x_get_groups_count, + .get_group_name = tb10x_get_group_name, + .get_group_pins = tb10x_get_group_pins, + .dt_node_to_map = tb10x_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int tb10x_get_functions_count(struct pinctrl_dev *pctl) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + return state->pinfuncnt; +} + +static const char *tb10x_get_function_name(struct pinctrl_dev *pctl, + unsigned n) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + return state->pinfuncs[n].name; +} + +static int tb10x_get_function_groups(struct pinctrl_dev *pctl, + unsigned n, const char * const **groups, + unsigned * const num_groups) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + + *groups = &state->pinfuncs[n].group; + *num_groups = 1; + + return 0; +} + +static int tb10x_gpio_request_enable(struct pinctrl_dev *pctl, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + int muxport = -1; + int muxmode = -1; + int i; + + mutex_lock(&state->mutex); + + /* + * Figure out to which port the requested GPIO belongs and how to + * configure that port. + * This loop also checks for pin conflicts between GPIOs and other + * functions. + */ + for (i = 0; i < state->pinfuncgrpcnt; i++) { + const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i]; + unsigned int mode = pfg->mode; + int j, port = pfg->port; + + /* + * Skip pin groups which are always mapped and don't need + * to be configured. + */ + if (port < 0) + continue; + + for (j = 0; j < pfg->pincnt; j++) { + if (pin == pfg->pins[j]) { + if (pfg->isgpio) { + /* + * Remember the GPIO-only setting of + * the port this pin belongs to. + */ + muxport = port; + muxmode = mode; + } else if (state->ports[port].count + && (state->ports[port].mode == mode)) { + /* + * Error: The requested pin is already + * used for something else. + */ + mutex_unlock(&state->mutex); + return -EBUSY; + } + break; + } + } + } + + /* + * If we haven't returned an error at this point, the GPIO pin is not + * used by another function and the GPIO request can be granted: + * Register pin as being used as GPIO so we don't allocate it to + * another function later. + */ + set_bit(pin, state->gpios); + + /* + * Potential conflicts between GPIOs and pin functions were caught + * earlier in this function and tb10x_pinctrl_set_config will do the + * Right Thing, either configure the port in GPIO only mode or leave + * another mode compatible with this GPIO request untouched. + */ + if (muxport >= 0) + tb10x_pinctrl_set_config(state, muxport, muxmode); + + mutex_unlock(&state->mutex); + + return 0; +} + +static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + + mutex_lock(&state->mutex); + + clear_bit(pin, state->gpios); + + mutex_unlock(&state->mutex); +} + +static int tb10x_pctl_enable(struct pinctrl_dev *pctl, + unsigned func_selector, unsigned group_selector) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector]; + int i; + + if (grp->port < 0) + return 0; + + mutex_lock(&state->mutex); + + /* + * Check if the requested function is compatible with previously + * requested functions. + */ + if (state->ports[grp->port].count + && (state->ports[grp->port].mode != grp->mode)) { + mutex_unlock(&state->mutex); + return -EBUSY; + } + + /* + * Check if the requested function is compatible with previously + * requested GPIOs. + */ + for (i = 0; i < grp->pincnt; i++) + if (test_bit(grp->pins[i], state->gpios)) { + mutex_unlock(&state->mutex); + return -EBUSY; + } + + tb10x_pinctrl_set_config(state, grp->port, grp->mode); + + state->ports[grp->port].count++; + + mutex_unlock(&state->mutex); + + return 0; +} + +static void tb10x_pctl_disable(struct pinctrl_dev *pctl, + unsigned func_selector, unsigned group_selector) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector]; + + if (grp->port < 0) + return; + + mutex_lock(&state->mutex); + + state->ports[grp->port].count--; + + mutex_unlock(&state->mutex); +} + +static struct pinmux_ops tb10x_pinmux_ops = { + .get_functions_count = tb10x_get_functions_count, + .get_function_name = tb10x_get_function_name, + .get_function_groups = tb10x_get_function_groups, + .gpio_request_enable = tb10x_gpio_request_enable, + .gpio_disable_free = tb10x_gpio_disable_free, + .enable = tb10x_pctl_enable, + .disable = tb10x_pctl_disable, +}; + +static struct pinctrl_desc tb10x_pindesc = { + .name = "TB10x", + .pins = tb10x_pins, + .npins = ARRAY_SIZE(tb10x_pins), + .owner = THIS_MODULE, + .pctlops = &tb10x_pinctrl_ops, + .pmxops = &tb10x_pinmux_ops, +}; + +static int tb10x_pinctrl_probe(struct platform_device *pdev) +{ + int ret = -EINVAL; + struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct device *dev = &pdev->dev; + struct device_node *of_node = dev->of_node; + struct device_node *child; + struct tb10x_pinctrl *state; + int i; + + if (!of_node) { + dev_err(dev, "No device tree node found.\n"); + return -EINVAL; + } + + if (!mem) { + dev_err(dev, "No memory resource defined.\n"); + return -EINVAL; + } + + state = devm_kzalloc(dev, sizeof(struct tb10x_pinctrl) + + of_get_child_count(of_node) + * sizeof(struct tb10x_of_pinfunc), + GFP_KERNEL); + if (!state) + return -ENOMEM; + + platform_set_drvdata(pdev, state); + state->pinfuncs = (struct tb10x_of_pinfunc *)(state + 1); + mutex_init(&state->mutex); + + state->base = devm_ioremap_resource(dev, mem); + if (IS_ERR(state->base)) { + ret = PTR_ERR(state->base); + goto fail; + } + + state->pingroups = tb10x_pingroups; + state->pinfuncgrpcnt = ARRAY_SIZE(tb10x_pingroups); + + for (i = 0; i < TB10X_PORTS; i++) + state->ports[i].mode = tb10x_pinctrl_get_config(state, i); + + for_each_child_of_node(of_node, child) { + const char *name; + + if (!of_property_read_string(child, "abilis,function", + &name)) { + state->pinfuncs[state->pinfuncnt].name = child->name; + state->pinfuncs[state->pinfuncnt].group = name; + state->pinfuncnt++; + } + } + + state->pctl = pinctrl_register(&tb10x_pindesc, dev, state); + if (!state->pctl) { + dev_err(dev, "could not register TB10x pin driver\n"); + ret = -EINVAL; + goto fail; + } + + return 0; + +fail: + mutex_destroy(&state->mutex); + return ret; +} + +static int tb10x_pinctrl_remove(struct platform_device *pdev) +{ + struct tb10x_pinctrl *state = platform_get_drvdata(pdev); + + pinctrl_unregister(state->pctl); + mutex_destroy(&state->mutex); + + return 0; +} + + +static const struct of_device_id tb10x_pinctrl_dt_ids[] = { + { .compatible = "abilis,tb10x-iomux" }, + { } +}; +MODULE_DEVICE_TABLE(of, tb10x_pinctrl_dt_ids); + +static struct platform_driver tb10x_pinctrl_pdrv = { + .probe = tb10x_pinctrl_probe, + .remove = tb10x_pinctrl_remove, + .driver = { + .name = "tb10x_pinctrl", + .of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids), + .owner = THIS_MODULE + } +}; + +module_platform_driver(tb10x_pinctrl_pdrv); + +MODULE_AUTHOR("Christian Ruppert <christian.ruppert@abilis.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index 2fa9bc6cd7a..2d43bff74f5 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -32,12 +32,14 @@ #include "core.h" #include "pinctrl-tegra.h" +#include "pinctrl-utils.h" struct tegra_pmx { struct device *dev; struct pinctrl_dev *pctl; const struct tegra_pinctrl_soc_data *soc; + const char **group_pins; int nbanks; void __iomem **regs; @@ -90,107 +92,6 @@ static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, } #endif -static int reserve_map(struct device *dev, struct pinctrl_map **map, - unsigned *reserved_maps, unsigned *num_maps, - unsigned reserve) -{ - unsigned old_num = *reserved_maps; - unsigned new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) { - dev_err(dev, "krealloc(map) failed\n"); - return -ENOMEM; - } - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, - unsigned *num_maps, const char *group, - const char *function) -{ - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -static int add_map_configs(struct device *dev, struct pinctrl_map **map, - unsigned *reserved_maps, unsigned *num_maps, - const char *group, unsigned long *configs, - unsigned num_configs) -{ - unsigned long *dup_configs; - - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) { - dev_err(dev, "kmemdup(configs) failed\n"); - return -ENOMEM; - } - - (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -static int add_config(struct device *dev, unsigned long **configs, - unsigned *num_configs, unsigned long config) -{ - unsigned old_num = *num_configs; - unsigned new_num = old_num + 1; - unsigned long *new_configs; - - new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, - GFP_KERNEL); - if (!new_configs) { - dev_err(dev, "krealloc(configs) failed\n"); - return -ENOMEM; - } - - new_configs[old_num] = config; - - *configs = new_configs; - *num_configs = new_num; - - return 0; -} - -static void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, - unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - - kfree(map); -} - static const struct cfg_param { const char *property; enum tegra_pinconf_param param; @@ -212,12 +113,13 @@ static const struct cfg_param { {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, }; -static int tegra_pinctrl_dt_subnode_to_map(struct device *dev, +static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps) { + struct device *dev = pctldev->dev; int ret, i; const char *function; u32 val; @@ -241,7 +143,8 @@ static int tegra_pinctrl_dt_subnode_to_map(struct device *dev, ret = of_property_read_u32(np, cfg_params[i].property, &val); if (!ret) { config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); - ret = add_config(dev, &configs, &num_configs, config); + ret = pinctrl_utils_add_config(pctldev, &configs, + &num_configs, config); if (ret < 0) goto exit; /* EINVAL=missing, which is fine since it's optional */ @@ -263,22 +166,25 @@ static int tegra_pinctrl_dt_subnode_to_map(struct device *dev, } reserve *= ret; - ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, + num_maps, reserve); if (ret < 0) goto exit; of_property_for_each_string(np, "nvidia,pins", prop, group) { if (function) { - ret = add_map_mux(map, reserved_maps, num_maps, - group, function); + ret = pinctrl_utils_add_map_mux(pctldev, map, + reserved_maps, num_maps, group, + function); if (ret < 0) goto exit; } if (num_configs) { - ret = add_map_configs(dev, map, reserved_maps, - num_maps, group, configs, - num_configs); + ret = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, group, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_GROUP); if (ret < 0) goto exit; } @@ -305,10 +211,11 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, *num_maps = 0; for_each_child_of_node(np_config, np) { - ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map, + ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map, &reserved_maps, num_maps); if (ret < 0) { - tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps); + pinctrl_utils_dt_free_map(pctldev, *map, + *num_maps); return ret; } } @@ -324,7 +231,7 @@ static const struct pinctrl_ops tegra_pinctrl_ops = { .pin_dbg_show = tegra_pinctrl_pin_dbg_show, #endif .dt_node_to_map = tegra_pinctrl_dt_node_to_map, - .dt_free_map = tegra_pinctrl_dt_free_map, + .dt_free_map = pinctrl_utils_dt_free_map, }; static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) @@ -388,17 +295,11 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); const struct tegra_pingroup *g; - u32 val; g = &pmx->soc->groups[group]; if (WARN_ON(g->mux_reg < 0)) return; - - val = pmx_readl(pmx, g->mux_bank, g->mux_reg); - val &= ~(0x3 << g->mux_bit); - val |= g->func_safe << g->mux_bit; - pmx_writel(pmx, val, g->mux_bank, g->mux_reg); } static const struct pinmux_ops tegra_pinmux_ops = { @@ -429,32 +330,32 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *width = 1; break; case TEGRA_PINCONF_PARAM_ENABLE_INPUT: - *bank = g->einput_bank; - *reg = g->einput_reg; + *bank = g->mux_bank; + *reg = g->mux_reg; *bit = g->einput_bit; *width = 1; break; case TEGRA_PINCONF_PARAM_OPEN_DRAIN: - *bank = g->odrain_bank; - *reg = g->odrain_reg; + *bank = g->mux_bank; + *reg = g->mux_reg; *bit = g->odrain_bit; *width = 1; break; case TEGRA_PINCONF_PARAM_LOCK: - *bank = g->lock_bank; - *reg = g->lock_reg; + *bank = g->mux_bank; + *reg = g->mux_reg; *bit = g->lock_bit; *width = 1; break; case TEGRA_PINCONF_PARAM_IORESET: - *bank = g->ioreset_bank; - *reg = g->ioreset_reg; + *bank = g->mux_bank; + *reg = g->mux_reg; *bit = g->ioreset_bit; *width = 1; break; case TEGRA_PINCONF_PARAM_RCV_SEL: - *bank = g->rcv_sel_bank; - *reg = g->rcv_sel_reg; + *bank = g->mux_bank; + *reg = g->mux_reg; *bit = g->rcv_sel_bit; *width = 1; break; @@ -501,8 +402,8 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *width = g->slwr_width; break; case TEGRA_PINCONF_PARAM_DRIVE_TYPE: - *bank = g->drvtype_bank; - *reg = g->drvtype_reg; + *bank = g->drv_bank; + *reg = g->drv_reg; *bit = g->drvtype_bit; *width = 2; break; @@ -511,11 +412,22 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, return -ENOTSUPP; } - if (*reg < 0) { - if (report_err) + if (*reg < 0 || *bit > 31) { + if (report_err) { + const char *prop = "unknown"; + int i; + + for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { + if (cfg_params[i].param == param) { + prop = cfg_params[i].property; + break; + } + } + dev_err(pmx->dev, - "Config param %04x not supported on group %s\n", - param, g->name); + "Config param %04x (%s) not supported on group %s\n", + param, prop, g->name); + } return -ENOTSUPP; } @@ -530,7 +442,8 @@ static int tegra_pinconf_get(struct pinctrl_dev *pctldev, } static int tegra_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { dev_err(pctldev->dev, "pin_config_set op not supported\n"); return -ENOTSUPP; @@ -565,51 +478,57 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, } static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); - u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); + enum tegra_pinconf_param param; + u16 arg; const struct tegra_pingroup *g; - int ret; + int ret, i; s8 bank, bit, width; s16 reg; u32 val, mask; g = &pmx->soc->groups[group]; - ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, - &width); - if (ret < 0) - return ret; + for (i = 0; i < num_configs; i++) { + param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]); + arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]); - val = pmx_readl(pmx, bank, reg); + ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, + &width); + if (ret < 0) + return ret; - /* LOCK can't be cleared */ - if (param == TEGRA_PINCONF_PARAM_LOCK) { - if ((val & BIT(bit)) && !arg) { - dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); - return -EINVAL; + val = pmx_readl(pmx, bank, reg); + + /* LOCK can't be cleared */ + if (param == TEGRA_PINCONF_PARAM_LOCK) { + if ((val & BIT(bit)) && !arg) { + dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); + return -EINVAL; + } } - } - /* Special-case Boolean values; allow any non-zero as true */ - if (width == 1) - arg = !!arg; + /* Special-case Boolean values; allow any non-zero as true */ + if (width == 1) + arg = !!arg; - /* Range-check user-supplied value */ - mask = (1 << width) - 1; - if (arg & ~mask) { - dev_err(pctldev->dev, - "config %lx: %x too big for %d bit register\n", - config, arg, width); - return -EINVAL; - } + /* Range-check user-supplied value */ + mask = (1 << width) - 1; + if (arg & ~mask) { + dev_err(pctldev->dev, + "config %lx: %x too big for %d bit register\n", + configs[i], arg, width); + return -EINVAL; + } - /* Update register */ - val &= ~(mask << bit); - val |= arg << bit; - pmx_writel(pmx, val, bank, reg); + /* Update register */ + val &= ~(mask << bit); + val |= arg << bit; + pmx_writel(pmx, val, bank, reg); + } /* for each config */ return 0; } @@ -707,6 +626,8 @@ int tegra_pinctrl_probe(struct platform_device *pdev, struct tegra_pmx *pmx; struct resource *res; int i; + const char **group_pins; + int fn, gn, gfn; pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); if (!pmx) { @@ -716,6 +637,41 @@ int tegra_pinctrl_probe(struct platform_device *pdev, pmx->dev = &pdev->dev; pmx->soc = soc_data; + /* + * Each mux group will appear in 4 functions' list of groups. + * This over-allocates slightly, since not all groups are mux groups. + */ + pmx->group_pins = devm_kzalloc(&pdev->dev, + soc_data->ngroups * 4 * sizeof(*pmx->group_pins), + GFP_KERNEL); + if (!pmx->group_pins) + return -ENOMEM; + + group_pins = pmx->group_pins; + for (fn = 0; fn < soc_data->nfunctions; fn++) { + struct tegra_function *func = &soc_data->functions[fn]; + + func->groups = group_pins; + + for (gn = 0; gn < soc_data->ngroups; gn++) { + const struct tegra_pingroup *g = &soc_data->groups[gn]; + + if (g->mux_reg == -1) + continue; + + for (gfn = 0; gfn < 4; gfn++) + if (g->funcs[gfn] == fn) + break; + if (gfn == 4) + continue; + + BUG_ON(group_pins - pmx->group_pins >= + soc_data->ngroups * 4); + *group_pins++ = g->name; + func->ngroups++; + } + } + tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; tegra_pinctrl_desc.name = dev_name(&pdev->dev); tegra_pinctrl_desc.pins = pmx->soc->pins; @@ -732,30 +688,14 @@ int tegra_pinctrl_probe(struct platform_device *pdev, GFP_KERNEL); if (!pmx->regs) { dev_err(&pdev->dev, "Can't alloc regs pointer\n"); - return -ENODEV; + return -ENOMEM; } for (i = 0; i < pmx->nbanks; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); - if (!res) { - dev_err(&pdev->dev, "Missing MEM resource\n"); - return -ENODEV; - } - - if (!devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), - dev_name(&pdev->dev))) { - dev_err(&pdev->dev, - "Couldn't request MEM resource %d\n", i); - return -ENODEV; - } - - pmx->regs[i] = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (!pmx->regs[i]) { - dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i); - return -ENODEV; - } + pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmx->regs[i])) + return PTR_ERR(pmx->regs[i]); } pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx); diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h index 817f7061dc4..8d94d1332e7 100644 --- a/drivers/pinctrl/pinctrl-tegra.h +++ b/drivers/pinctrl/pinctrl-tegra.h @@ -72,104 +72,89 @@ enum tegra_pinconf_tristate { */ struct tegra_function { const char *name; - const char * const *groups; + const char **groups; unsigned ngroups; }; /** * struct tegra_pingroup - Tegra pin group - * @mux_reg: Mux register offset. -1 if unsupported. - * @mux_bank: Mux register bank. 0 if unsupported. - * @mux_bit: Mux register bit. 0 if unsupported. - * @pupd_reg: Pull-up/down register offset. -1 if unsupported. - * @pupd_bank: Pull-up/down register bank. 0 if unsupported. - * @pupd_bit: Pull-up/down register bit. 0 if unsupported. - * @tri_reg: Tri-state register offset. -1 if unsupported. - * @tri_bank: Tri-state register bank. 0 if unsupported. - * @tri_bit: Tri-state register bit. 0 if unsupported. - * @einput_reg: Enable-input register offset. -1 if unsupported. - * @einput_bank: Enable-input register bank. 0 if unsupported. - * @einput_bit: Enable-input register bit. 0 if unsupported. - * @odrain_reg: Open-drain register offset. -1 if unsupported. - * @odrain_bank: Open-drain register bank. 0 if unsupported. - * @odrain_bit: Open-drain register bit. 0 if unsupported. - * @lock_reg: Lock register offset. -1 if unsupported. - * @lock_bank: Lock register bank. 0 if unsupported. - * @lock_bit: Lock register bit. 0 if unsupported. - * @ioreset_reg: IO reset register offset. -1 if unsupported. - * @ioreset_bank: IO reset register bank. 0 if unsupported. - * @ioreset_bit: IO reset register bit. 0 if unsupported. - * @rcv_sel_reg: Receiver select offset. -1 if unsupported. - * @rcv_sel_bank: Receiver select bank. 0 if unsupported. - * @rcv_sel_bit: Receiver select bit. 0 if unsupported. - * @drv_reg: Drive fields register offset. -1 if unsupported. - * This register contains the hsm, schmitt, lpmd, drvdn, - * drvup, slwr, and slwf parameters. - * @drv_bank: Drive fields register bank. 0 if unsupported. - * @hsm_bit: High Speed Mode register bit. 0 if unsupported. - * @schmitt_bit: Scmitt register bit. 0 if unsupported. - * @lpmd_bit: Low Power Mode register bit. 0 if unsupported. - * @drvdn_bit: Drive Down register bit. 0 if unsupported. - * @drvdn_width: Drive Down field width. 0 if unsupported. - * @drvup_bit: Drive Up register bit. 0 if unsupported. - * @drvup_width: Drive Up field width. 0 if unsupported. - * @slwr_bit: Slew Rising register bit. 0 if unsupported. - * @slwr_width: Slew Rising field width. 0 if unsupported. - * @slwf_bit: Slew Falling register bit. 0 if unsupported. - * @slwf_width: Slew Falling field width. 0 if unsupported. - * @drvtype_reg: Drive type fields register offset. -1 if unsupported. - * @drvtype_bank: Drive type fields register bank. 0 if unsupported. - * @drvtype_bit: Drive type register bit. 0 if unsupported. + * @name The name of the pin group. + * @pins An array of pin IDs included in this pin group. + * @npins The number of entries in @pins. + * @funcs The mux functions which can be muxed onto this group. + * @mux_reg: Mux register offset. + * This register contains the mux, einput, odrain, lock, + * ioreset, rcv_sel parameters. + * @mux_bank: Mux register bank. + * @mux_bit: Mux register bit. + * @pupd_reg: Pull-up/down register offset. + * @pupd_bank: Pull-up/down register bank. + * @pupd_bit: Pull-up/down register bit. + * @tri_reg: Tri-state register offset. + * @tri_bank: Tri-state register bank. + * @tri_bit: Tri-state register bit. + * @einput_bit: Enable-input register bit. + * @odrain_bit: Open-drain register bit. + * @lock_bit: Lock register bit. + * @ioreset_bit: IO reset register bit. + * @rcv_sel_bit: Receiver select bit. + * @drv_reg: Drive fields register offset. + * This register contains hsm, schmitt, lpmd, drvdn, + * drvup, slwr, slwf, and drvtype parameters. + * @drv_bank: Drive fields register bank. + * @hsm_bit: High Speed Mode register bit. + * @schmitt_bit: Scmitt register bit. + * @lpmd_bit: Low Power Mode register bit. + * @drvdn_bit: Drive Down register bit. + * @drvdn_width: Drive Down field width. + * @drvup_bit: Drive Up register bit. + * @drvup_width: Drive Up field width. + * @slwr_bit: Slew Rising register bit. + * @slwr_width: Slew Rising field width. + * @slwf_bit: Slew Falling register bit. + * @slwf_width: Slew Falling field width. + * @drvtype_bit: Drive type register bit. + * + * -1 in a *_reg field means that feature is unsupported for this group. + * *_bank and *_reg values are irrelevant when *_reg is -1. + * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature. * * A representation of a group of pins (possibly just one pin) in the Tegra * pin controller. Each group allows some parameter or parameters to be * configured. The most common is mux function selection. Many others exist * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex; * certain groups may only support configuring certain parameters, hence - * each parameter is optional, represented by a -1 "reg" value. + * each parameter is optional. */ struct tegra_pingroup { const char *name; const unsigned *pins; - unsigned npins; - unsigned funcs[4]; - unsigned func_safe; + u8 npins; + u8 funcs[4]; s16 mux_reg; s16 pupd_reg; s16 tri_reg; - s16 einput_reg; - s16 odrain_reg; - s16 lock_reg; - s16 ioreset_reg; - s16 rcv_sel_reg; s16 drv_reg; - s16 drvtype_reg; u32 mux_bank:2; u32 pupd_bank:2; u32 tri_bank:2; - u32 einput_bank:2; - u32 odrain_bank:2; - u32 ioreset_bank:2; - u32 rcv_sel_bank:2; - u32 lock_bank:2; u32 drv_bank:2; - u32 drvtype_bank:2; - u32 mux_bit:5; - u32 pupd_bit:5; - u32 tri_bit:5; - u32 einput_bit:5; - u32 odrain_bit:5; - u32 lock_bit:5; - u32 ioreset_bit:5; - u32 rcv_sel_bit:5; - u32 hsm_bit:5; - u32 schmitt_bit:5; - u32 lpmd_bit:5; - u32 drvdn_bit:5; - u32 drvup_bit:5; - u32 slwr_bit:5; - u32 slwf_bit:5; - u32 drvtype_bit:5; + u32 mux_bit:6; + u32 pupd_bit:6; + u32 tri_bit:6; + u32 einput_bit:6; + u32 odrain_bit:6; + u32 lock_bit:6; + u32 ioreset_bit:6; + u32 rcv_sel_bit:6; + u32 hsm_bit:6; + u32 schmitt_bit:6; + u32 lpmd_bit:6; + u32 drvdn_bit:6; + u32 drvup_bit:6; + u32 slwr_bit:6; + u32 slwf_bit:6; + u32 drvtype_bit:6; u32 drvdn_width:6; u32 drvup_width:6; u32 slwr_width:6; @@ -193,7 +178,7 @@ struct tegra_pinctrl_soc_data { unsigned ngpios; const struct pinctrl_pin_desc *pins; unsigned npins; - const struct tegra_function *functions; + struct tegra_function *functions; unsigned nfunctions; const struct tegra_pingroup *groups; unsigned ngroups; diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c index 622c4854977..33614baab4c 100644 --- a/drivers/pinctrl/pinctrl-tegra114.c +++ b/drivers/pinctrl/pinctrl-tegra114.c @@ -1,10 +1,8 @@ /* - * Pinctrl data and driver for the NVIDIA Tegra114 pinmux + * Pinctrl data for the NVIDIA Tegra114 pinmux * * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. * - * Arthur: Pritesh Raithatha <praithatha@nvidia.com> - * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. @@ -13,9 +11,6 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/module.h> @@ -203,8 +198,8 @@ #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245) /* All non-GPIO pins follow */ -#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1) -#define _PIN(offset) (NUM_GPIOS + (offset)) +#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1) +#define _PIN(offset) (NUM_GPIOS + (offset)) /* Non-GPIO pins */ #define TEGRA_PIN_CORE_PWR_REQ _PIN(0) @@ -212,8 +207,11 @@ #define TEGRA_PIN_PWR_INT_N _PIN(2) #define TEGRA_PIN_RESET_OUT_N _PIN(3) #define TEGRA_PIN_OWR _PIN(4) +#define TEGRA_PIN_JTAG_RTCK _PIN(5) +#define TEGRA_PIN_CLK_32K_IN _PIN(6) +#define TEGRA_PIN_GMI_CLK_LB _PIN(7) -static const struct pinctrl_pin_desc tegra114_pins[] = { +static const struct pinctrl_pin_desc tegra114_pins[] = { PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"), PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"), @@ -385,9 +383,12 @@ static const struct pinctrl_pin_desc tegra114_pins[] = { PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"), PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"), PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"), - PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"), PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"), PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"), + PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"), + PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), + PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), + PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"), }; static const unsigned clk_32k_out_pa0_pins[] = { @@ -1074,10 +1075,6 @@ static const unsigned cpu_pwr_req_pins[] = { TEGRA_PIN_CPU_PWR_REQ, }; -static const unsigned owr_pins[] = { - TEGRA_PIN_OWR, -}; - static const unsigned pwr_int_n_pins[] = { TEGRA_PIN_PWR_INT_N, }; @@ -1086,6 +1083,22 @@ static const unsigned reset_out_n_pins[] = { TEGRA_PIN_RESET_OUT_N, }; +static const unsigned owr_pins[] = { + TEGRA_PIN_OWR, +}; + +static const unsigned jtag_rtck_pins[] = { + TEGRA_PIN_JTAG_RTCK, +}; + +static const unsigned clk_32k_in_pins[] = { + TEGRA_PIN_CLK_32K_IN, +}; + +static const unsigned gmi_clk_lb_pins[] = { + TEGRA_PIN_GMI_CLK_LB, +}; + static const unsigned drive_ao1_pins[] = { TEGRA_PIN_KB_ROW0_PR0, TEGRA_PIN_KB_ROW1_PR1, @@ -1127,7 +1140,6 @@ static const unsigned drive_at1_pins[] = { TEGRA_PIN_GMI_AD13_PH5, TEGRA_PIN_GMI_AD14_PH6, TEGRA_PIN_GMI_AD15_PH7, - TEGRA_PIN_GMI_IORDY_PI5, TEGRA_PIN_GMI_CS7_N_PI6, }; @@ -1141,15 +1153,12 @@ static const unsigned drive_at2_pins[] = { TEGRA_PIN_GMI_AD5_PG5, TEGRA_PIN_GMI_AD6_PG6, TEGRA_PIN_GMI_AD7_PG7, - TEGRA_PIN_GMI_WR_N_PI0, TEGRA_PIN_GMI_OE_N_PI1, TEGRA_PIN_GMI_CS6_N_PI3, TEGRA_PIN_GMI_RST_N_PI4, TEGRA_PIN_GMI_WAIT_PI7, - TEGRA_PIN_GMI_DQS_P_PJ3, - TEGRA_PIN_GMI_ADV_N_PK0, TEGRA_PIN_GMI_CLK_PK1, TEGRA_PIN_GMI_CS4_N_PK2, @@ -1342,14 +1351,37 @@ static const unsigned drive_uda_pins[] = { }; static const unsigned drive_dev3_pins[] = { - TEGRA_PIN_CLK3_OUT_PEE0, - TEGRA_PIN_CLK3_REQ_PEE1, +}; + +static const unsigned drive_cec_pins[] = { +}; + +static const unsigned drive_at6_pins[] = { +}; + +static const unsigned drive_dap5_pins[] = { +}; + +static const unsigned drive_usb_vbus_en_pins[] = { +}; + +static const unsigned drive_ao3_pins[] = { +}; + +static const unsigned drive_hv0_pins[] = { +}; + +static const unsigned drive_sdio4_pins[] = { +}; + +static const unsigned drive_ao0_pins[] = { }; enum tegra_mux { TEGRA_MUX_BLINK, TEGRA_MUX_CEC, TEGRA_MUX_CLDVFS, + TEGRA_MUX_CLK, TEGRA_MUX_CLK12, TEGRA_MUX_CPU, TEGRA_MUX_DAP, @@ -1394,6 +1426,7 @@ enum tegra_mux { TEGRA_MUX_RSVD2, TEGRA_MUX_RSVD3, TEGRA_MUX_RSVD4, + TEGRA_MUX_RTCK, TEGRA_MUX_SDMMC1, TEGRA_MUX_SDMMC2, TEGRA_MUX_SDMMC3, @@ -1425,944 +1458,16 @@ enum tegra_mux { TEGRA_MUX_VI_ALT3, }; -static const char * const blink_groups[] = { - "clk_32k_out_pa0", -}; - -static const char * const cec_groups[] = { - "hdmi_cec_pee3", -}; - -static const char * const cldvfs_groups[] = { - "gmi_ad9_ph1", - "gmi_ad10_ph2", - "kb_row7_pr7", - "kb_row8_ps0", - "dvfs_pwm_px0", - "dvfs_clk_px2", -}; - -static const char * const clk12_groups[] = { - "sdmmc1_wp_n_pv3", - "sdmmc1_clk_pz0", -}; - -static const char * const cpu_groups[] = { - "cpu_pwr_req", -}; - -static const char * const dap_groups[] = { - "clk1_req_pee2", - "clk2_req_pcc5", -}; - -static const char * const dap1_groups[] = { - "clk1_req_pee2", -}; - -static const char * const dap2_groups[] = { - "clk1_out_pw4", - "gpio_x4_aud_px4", -}; - -static const char * const dev3_groups[] = { - "clk3_req_pee1", -}; - -static const char * const displaya_groups[] = { - "dap3_fs_pp0", - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_sclk_pp3", - "uart3_rts_n_pc0", - "pu3", - "pu4", - "pu5", - "pbb3", - "pbb4", - "pbb5", - "pbb6", - "kb_row3_pr3", - "kb_row4_pr4", - "kb_row5_pr5", - "kb_row6_pr6", - "kb_col3_pq3", - "sdmmc3_dat2_pb5", -}; - -static const char * const displaya_alt_groups[] = { - "kb_row6_pr6", -}; - -static const char * const displayb_groups[] = { - "dap3_fs_pp0", - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_sclk_pp3", - "pu3", - "pu4", - "pu5", - "pu6", - "pbb3", - "pbb4", - "pbb5", - "pbb6", - "kb_row3_pr3", - "kb_row4_pr4", - "kb_row5_pr5", - "kb_row6_pr6", - "sdmmc3_dat3_pb4", -}; - -static const char * const dtv_groups[] = { - "uart3_cts_n_pa1", - "uart3_rts_n_pc0", - "dap4_fs_pp4", - "dap4_dout_pp6", - "gmi_wait_pi7", - "gmi_ad8_ph0", - "gmi_ad14_ph6", - "gmi_ad15_ph7", -}; - -static const char * const emc_dll_groups[] = { - "kb_col0_pq0", - "kb_col1_pq1", -}; - -static const char * const extperiph1_groups[] = { - "clk1_out_pw4", -}; - -static const char * const extperiph2_groups[] = { - "clk2_out_pw5", -}; - -static const char * const extperiph3_groups[] = { - "clk3_out_pee0", -}; - -static const char * const gmi_groups[] = { - "gmi_wp_n_pc7", - - "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_wr_n_pi0", - "gmi_oe_n_pi1", - "gmi_cs6_n_pi3", - "gmi_rst_n_pi4", - "gmi_iordy_pi5", - "gmi_cs7_n_pi6", - "gmi_wait_pi7", - "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_dqs_p_pj3", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs4_n_pk2", - "gmi_cs2_n_pk3", - "gmi_cs3_n_pk4", - "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7", - "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7", - "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3", -}; - -static const char * const gmi_alt_groups[] = { - "gmi_wp_n_pc7", - "gmi_cs3_n_pk4", - "gmi_a16_pj7", -}; - -static const char * const hda_groups[] = { - "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3", - "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", -}; - -static const char * const hsi_groups[] = { - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0", -}; - -static const char * const i2c1_groups[] = { - "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5", - "gpio_w2_aud_pw2", - "gpio_w3_aud_pw3", -}; - -static const char * const i2c2_groups[] = { - "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6", -}; - -static const char * const i2c3_groups[] = { - "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2", -}; - -static const char * const i2c4_groups[] = { - "ddc_scl_pv4", - "ddc_sda_pv5", -}; - -static const char * const i2cpwr_groups[] = { - "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7", -}; - -static const char * const i2s0_groups[] = { - "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3", -}; - -static const char * const i2s1_groups[] = { - "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", -}; - -static const char * const i2s2_groups[] = { - "dap3_fs_pp0", - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_sclk_pp3", -}; - -static const char * const i2s3_groups[] = { - "dap4_fs_pp4", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_sclk_pp7", -}; - -static const char * const i2s4_groups[] = { - "pcc1", - "pbb0", - "pbb7", - "pcc2", -}; - -static const char * const irda_groups[] = { - "uart2_rxd_pc3", - "uart2_txd_pc2", -}; - -static const char * const kbc_groups[] = { - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3", - "kb_row4_pr4", - "kb_row5_pr5", - "kb_row6_pr6", - "kb_row7_pr7", - "kb_row8_ps0", - "kb_row9_ps1", - "kb_row10_ps2", - "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_col5_pq5", - "kb_col6_pq6", - "kb_col7_pq7", -}; - -static const char * const nand_groups[] = { - "gmi_wp_n_pc7", - "gmi_wait_pi7", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs2_n_pk3", - "gmi_cs3_n_pk4", - "gmi_cs4_n_pk2", - "gmi_cs6_n_pi3", - "gmi_cs7_n_pi6", - "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_wr_n_pi0", - "gmi_oe_n_pi1", - "gmi_dqs_p_pj3", - "gmi_rst_n_pi4", -}; - -static const char * const nand_alt_groups[] = { - "gmi_cs6_n_pi3", - "gmi_cs7_n_pi6", - "gmi_rst_n_pi4", -}; - -static const char * const owr_groups[] = { - "pu0", - "kb_col4_pq4", - "owr", - "sdmmc3_cd_n_pv2", -}; - -static const char * const pmi_groups[] = { - "pwr_int_n", -}; - -static const char * const pwm0_groups[] = { - "sdmmc1_dat2_py5", - "uart3_rts_n_pc0", - "pu3", - "gmi_ad8_ph0", - "sdmmc3_dat3_pb4", -}; - -static const char * const pwm1_groups[] = { - "sdmmc1_dat1_py6", - "pu4", - "gmi_ad9_ph1", - "sdmmc3_dat2_pb5", -}; - -static const char * const pwm2_groups[] = { - "pu5", - "gmi_ad10_ph2", - "kb_col3_pq3", - "sdmmc3_dat1_pb6", -}; - -static const char * const pwm3_groups[] = { - "pu6", - "gmi_ad11_ph3", - "sdmmc3_cmd_pa7", -}; - -static const char * const pwron_groups[] = { - "core_pwr_req", -}; - -static const char * const reset_out_n_groups[] = { - "reset_out_n", -}; - -static const char * const rsvd1_groups[] = { - "pv1", - "hdmi_int_pn7", - "pu1", - "pu2", - "gmi_wp_n_pc7", - "gmi_adv_n_pk0", - "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_wr_n_pi0", - "gmi_oe_n_pi1", - "gpio_x4_aud_px4", - "gpio_x5_aud_px5", - "gpio_x7_aud_px7", - - "reset_out_n", -}; - -static const char * const rsvd2_groups[] = { - "pv0", - "pv1", - "sdmmc1_dat0_py7", - "clk2_out_pw5", - "clk2_req_pcc5", - "hdmi_int_pn7", - "ddc_scl_pv4", - "ddc_sda_pv5", - "uart3_txd_pw6", - "uart3_rxd_pw7", - "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5", - "dap4_fs_pp4", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_sclk_pp7", - "clk3_out_pee0", - "clk3_req_pee1", - "gmi_iordy_pi5", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6", - "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_dat7_paa7", - "pcc1", - "pbb7", - "pcc2", - "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row7_pr7", - "kb_row8_ps0", - "kb_row9_ps1", - "kb_row10_ps2", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_col5_pq5", - "kb_col6_pq6", - "kb_col7_pq7", - "sys_clk_req_pz5", - "core_pwr_req", - "cpu_pwr_req", - "pwr_int_n", - "owr", - "spdif_out_pk5", - "gpio_x1_aud_px1", - "sdmmc3_clk_pa6", - "sdmmc3_dat0_pb7", - "gpio_w2_aud_pw2", - "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5", - "reset_out_n", -}; - -static const char * const rsvd3_groups[] = { - "pv0", - "pv1", - "sdmmc1_clk_pz0", - "clk2_out_pw5", - "clk2_req_pcc5", - "hdmi_int_pn7", - "ddc_scl_pv4", - "ddc_sda_pv5", - "uart2_rts_n_pj6", - "uart2_cts_n_pj5", - "uart3_txd_pw6", - "uart3_rxd_pw7", - "pu0", - "pu1", - "pu2", - "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5", - "dap4_din_pp5", - "dap4_sclk_pp7", - "clk3_out_pee0", - "clk3_req_pee1", - "pcc1", - "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2", - "pbb7", - "pcc2", - "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3", - "kb_row9_ps1", - "kb_row10_ps2", - "clk_32k_out_pa0", - "sys_clk_req_pz5", - "core_pwr_req", - "cpu_pwr_req", - "pwr_int_n", - "owr", - "clk1_req_pee2", - "clk1_out_pw4", - "spdif_out_pk5", - "spdif_in_pk6", - "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", - "dvfs_pwm_px0", - "gpio_x1_aud_px1", - "gpio_x3_aud_px3", - "dvfs_clk_px2", - "sdmmc3_clk_pa6", - "sdmmc3_dat0_pb7", - "hdmi_cec_pee3", - "sdmmc3_cd_n_pv2", - "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5", - "reset_out_n", -}; - -static const char * const rsvd4_groups[] = { - "pv0", - "pv1", - "sdmmc1_clk_pz0", - "clk2_out_pw5", - "clk2_req_pcc5", - "hdmi_int_pn7", - "ddc_scl_pv4", - "ddc_sda_pv5", - "pu0", - "pu1", - "pu2", - "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5", - "dap4_fs_pp4", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_sclk_pp7", - "clk3_out_pee0", - "clk3_req_pee1", - "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_rst_n_pi4", - "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6", - "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7", - "cam_mclk_pcc0", - "pcc1", - "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2", - "pbb3", - "pbb4", - "pbb5", - "pbb6", - "pbb7", - "pcc2", - "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_col2_pq2", - "kb_col5_pq5", - "kb_col6_pq6", - "kb_col7_pq7", - "clk_32k_out_pa0", - "sys_clk_req_pz5", - "core_pwr_req", - "cpu_pwr_req", - "pwr_int_n", - "owr", - "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3", - "clk1_req_pee2", - "clk1_out_pw4", - "spdif_in_pk6", - "spdif_out_pk5", - "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", - "dvfs_pwm_px0", - "gpio_x1_aud_px1", - "gpio_x3_aud_px3", - "dvfs_clk_px2", - "gpio_x5_aud_px5", - "gpio_x6_aud_px6", - "gpio_x7_aud_px7", - "sdmmc3_cd_n_pv2", - "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5", - "sdmmc3_clk_lb_in_pee5", - "sdmmc3_clk_lb_out_pee4", -}; - -static const char * const sdmmc1_groups[] = { - - "sdmmc1_clk_pz0", - "sdmmc1_cmd_pz1", - "sdmmc1_dat3_py4", - "sdmmc1_dat2_py5", - "sdmmc1_dat1_py6", - "sdmmc1_dat0_py7", - "uart3_cts_n_pa1", - "kb_col5_pq5", - "sdmmc1_wp_n_pv3", -}; - -static const char * const sdmmc2_groups[] = { - "gmi_iordy_pi5", - "gmi_clk_pk1", - "gmi_cs2_n_pk3", - "gmi_cs3_n_pk4", - "gmi_cs7_n_pi6", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_dqs_p_pj3", -}; - -static const char * const sdmmc3_groups[] = { - "kb_col4_pq4", - "sdmmc3_clk_pa6", - "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "hdmi_cec_pee3", - "sdmmc3_cd_n_pv2", - "sdmmc3_clk_lb_in_pee5", - "sdmmc3_clk_lb_out_pee4", -}; - -static const char * const sdmmc4_groups[] = { - "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7", -}; - -static const char * const soc_groups[] = { - "gmi_cs1_n_pj2", - "gmi_oe_n_pi1", - "clk_32k_out_pa0", - "hdmi_cec_pee3", -}; - -static const char * const spdif_groups[] = { - "sdmmc1_cmd_pz1", - "sdmmc1_dat3_py4", - "uart2_rxd_pc3", - "uart2_txd_pc2", - "spdif_in_pk6", - "spdif_out_pk5", -}; - -static const char * const spi1_groups[] = { - "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3", - "gpio_x3_aud_px3", - "gpio_x4_aud_px4", - "gpio_x5_aud_px5", - "gpio_x6_aud_px6", - "gpio_x7_aud_px7", - "gpio_w3_aud_pw3", -}; - -static const char * const spi2_groups[] = { - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0", - "kb_row4_pr4", - "kb_row5_pr5", - "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_col6_pq6", - "kb_col7_pq7", - "gpio_x4_aud_px4", - "gpio_x5_aud_px5", - "gpio_x6_aud_px6", - "gpio_x7_aud_px7", - "gpio_w2_aud_pw2", - "gpio_w3_aud_pw3", -}; - -static const char * const spi3_groups[] = { - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc3_clk_pa6", - "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", -}; - -static const char * const spi4_groups[] = { - "sdmmc1_cmd_pz1", - "sdmmc1_dat3_py4", - "sdmmc1_dat2_py5", - "sdmmc1_dat1_py6", - "sdmmc1_dat0_py7", - "uart2_rxd_pc3", - "uart2_txd_pc2", - "uart2_rts_n_pj6", - "uart2_cts_n_pj5", - "uart3_txd_pw6", - "uart3_rxd_pw7", - "uart3_cts_n_pa1", - "gmi_wait_pi7", - "gmi_cs6_n_pi3", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_a19_pk7", - "gmi_wr_n_pi0", - "sdmmc1_wp_n_pv3", -}; - -static const char * const spi5_groups[] = { - "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3", - "dap3_fs_pp0", - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_sclk_pp3", -}; - -static const char * const spi6_groups[] = { - "dvfs_pwm_px0", - "gpio_x1_aud_px1", - "gpio_x3_aud_px3", - "dvfs_clk_px2", - "gpio_x6_aud_px6", - "gpio_w2_aud_pw2", - "gpio_w3_aud_pw3", -}; - -static const char * const sysclk_groups[] = { - "sys_clk_req_pz5", -}; - -static const char * const trace_groups[] = { - "gmi_iordy_pi5", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs2_n_pk3", - "gmi_cs4_n_pk2", - "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7", - "gmi_dqs_p_pj3", -}; - -static const char * const uarta_groups[] = { - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0", - "sdmmc1_cmd_pz1", - "sdmmc1_dat3_py4", - "sdmmc1_dat2_py5", - "sdmmc1_dat1_py6", - "sdmmc1_dat0_py7", - "uart2_rxd_pc3", - "uart2_txd_pc2", - "uart2_rts_n_pj6", - "uart2_cts_n_pj5", - "pu0", - "pu1", - "pu2", - "pu3", - "pu4", - "pu5", - "pu6", - "kb_row7_pr7", - "kb_row8_ps0", - "kb_row9_ps1", - "kb_row10_ps2", - "kb_col3_pq3", - "kb_col4_pq4", - "sdmmc3_cmd_pa7", - "sdmmc3_dat1_pb6", - "sdmmc1_wp_n_pv3", -}; - -static const char * const uartb_groups[] = { - "uart2_rts_n_pj6", - "uart2_cts_n_pj5", -}; - -static const char * const uartc_groups[] = { - "uart3_txd_pw6", - "uart3_rxd_pw7", - "uart3_cts_n_pa1", - "uart3_rts_n_pc0", -}; - -static const char * const uartd_groups[] = { - "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3", - "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7", -}; - -static const char * const ulpi_groups[] = { - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0", - "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3", -}; - -static const char * const usb_groups[] = { - "pv0", - "pu6", - "gmi_cs0_n_pj0", - "gmi_cs4_n_pk2", - "gmi_ad11_ph3", - "kb_col0_pq0", - "spdif_in_pk6", - "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5", -}; - -static const char * const vgp1_groups[] = { - "cam_i2c_scl_pbb1", -}; - -static const char * const vgp2_groups[] = { - "cam_i2c_sda_pbb2", -}; - -static const char * const vgp3_groups[] = { - "pbb3", -}; - -static const char * const vgp4_groups[] = { - "pbb4", -}; - -static const char * const vgp5_groups[] = { - "pbb5", -}; - -static const char * const vgp6_groups[] = { - "pbb6", -}; - -static const char * const vi_groups[] = { - "cam_mclk_pcc0", - "pbb0", -}; - -static const char * const vi_alt1_groups[] = { - "cam_mclk_pcc0", - "pbb0", -}; - -static const char * const vi_alt3_groups[] = { - "cam_mclk_pcc0", - "pbb0", -}; - #define FUNCTION(fname) \ { \ .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ } -static const struct tegra_function tegra114_functions[] = { +static struct tegra_function tegra114_functions[] = { FUNCTION(blink), FUNCTION(cec), FUNCTION(cldvfs), + FUNCTION(clk), FUNCTION(clk12), FUNCTION(cpu), FUNCTION(dap), @@ -2407,6 +1512,7 @@ static const struct tegra_function tegra114_functions[] = { FUNCTION(rsvd2), FUNCTION(rsvd3), FUNCTION(rsvd4), + FUNCTION(rtck), FUNCTION(sdmmc1), FUNCTION(sdmmc2), FUNCTION(sdmmc3), @@ -2438,13 +1544,15 @@ static const struct tegra_function tegra114_functions[] = { FUNCTION(vi_alt3), }; -#define DRV_PINGROUP_REG_START 0x868 /* bank 0 */ -#define PINGROUP_REG_START 0x3000 /* bank 1 */ +#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ +#define PINGROUP_REG_A 0x3000 /* bank 1 */ + +#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) -#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_START) -#define PINGROUP_REG_N(r) -1 +#define PINGROUP_BIT_Y(b) (b) +#define PINGROUP_BIT_N(b) (-1) -#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \ +#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \ { \ .name = #pg_name, \ .pins = pg_name##_pins, \ @@ -2455,42 +1563,29 @@ static const struct tegra_function tegra114_functions[] = { TEGRA_MUX_##f2, \ TEGRA_MUX_##f3, \ }, \ - .func_safe = TEGRA_MUX_##f_safe, \ - .mux_reg = PINGROUP_REG_Y(r), \ + .mux_reg = PINGROUP_REG(r), \ .mux_bank = 1, \ .mux_bit = 0, \ - .pupd_reg = PINGROUP_REG_Y(r), \ + .pupd_reg = PINGROUP_REG(r), \ .pupd_bank = 1, \ .pupd_bit = 2, \ - .tri_reg = PINGROUP_REG_Y(r), \ + .tri_reg = PINGROUP_REG(r), \ .tri_bank = 1, \ .tri_bit = 4, \ - .einput_reg = PINGROUP_REG_Y(r), \ - .einput_bank = 1, \ - .einput_bit = 5, \ - .odrain_reg = PINGROUP_REG_##od(r), \ - .odrain_bank = 1, \ - .odrain_bit = 6, \ - .lock_reg = PINGROUP_REG_Y(r), \ - .lock_bank = 1, \ - .lock_bit = 7, \ - .ioreset_reg = PINGROUP_REG_##ior(r), \ - .ioreset_bank = 1, \ - .ioreset_bit = 8, \ - .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r), \ - .rcv_sel_bank = 1, \ - .rcv_sel_bit = 9, \ + .einput_bit = PINGROUP_BIT_Y(5), \ + .odrain_bit = PINGROUP_BIT_##od(6), \ + .lock_bit = PINGROUP_BIT_Y(7), \ + .ioreset_bit = PINGROUP_BIT_##ior(8), \ + .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ .drv_reg = -1, \ - .drvtype_reg = -1, \ } -#define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_START) -#define DRV_PINGROUP_DVRTYPE_N(r) -1 +#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ - drvdn_b, drvdn_w, drvup_b, drvup_w, \ - slwr_b, slwr_w, slwf_b, slwf_w, \ - drvtype) \ + drvdn_b, drvdn_w, drvup_b, drvup_w, \ + slwr_b, slwr_w, slwf_b, slwf_w, \ + drvtype) \ { \ .name = "drive_" #pg_name, \ .pins = drive_##pg_name##_pins, \ @@ -2498,12 +1593,12 @@ static const struct tegra_function tegra114_functions[] = { .mux_reg = -1, \ .pupd_reg = -1, \ .tri_reg = -1, \ - .einput_reg = -1, \ - .odrain_reg = -1, \ - .lock_reg = -1, \ - .ioreset_reg = -1, \ - .rcv_sel_reg = -1, \ - .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \ + .einput_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .ioreset_bit = -1, \ + .rcv_sel_bit = -1, \ + .drv_reg = DRV_PINGROUP_REG(r), \ .drv_bank = 0, \ .hsm_bit = hsm_b, \ .schmitt_bit = schmitt_b, \ @@ -2516,219 +1611,228 @@ static const struct tegra_function tegra114_functions[] = { .slwr_width = slwr_w, \ .slwf_bit = slwf_b, \ .slwf_width = slwf_w, \ - .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \ - .drvtype_bank = 0, \ - .drvtype_bit = 6, \ + .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ } static const struct tegra_pingroup tegra114_groups[] = { - /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */ - /* FIXME: Fill in correct data in safe column */ - PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N, N), - PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N, N), - PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N, N), - PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, ULPI, 0x300c, N, N, N), - PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, ULPI, 0x3010, N, N, N), - PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, ULPI, 0x3014, N, N, N), - PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, ULPI, 0x3018, N, N, N), - PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, ULPI, 0x301c, N, N, N), - PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3020, N, N, N), - PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3024, N, N, N), - PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3028, N, N, N), - PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, ULPI, 0x302c, N, N, N), - PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3030, N, N, N), - PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3034, N, N, N), - PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3038, N, N, N), - PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x303c, N, N, N), - PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x3040, N, N, N), - PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3044, N, N, N), - PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, RSVD4, 0x3048, N, N, N), - PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x304c, N, N, N), - PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x3050, N, N, N), - PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, SDMMC1, 0x3054, N, N, N), - PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, SDMMC1, 0x3058, N, N, N), - PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, RSVD2, 0x305c, N, N, N), - PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, RSVD4, 0x3068, N, N, N), - PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, RSVD4, 0x306c, N, N, N), - PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3110, N, N, Y), - PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3114, N, N, Y), - PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3118, N, N, Y), - PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3164, N, N, N), - PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3168, N, N, N), - PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, RSVD3, 0x316c, N, N, N), - PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, RSVD3, 0x3170, N, N, N), - PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, RSVD3, 0x3174, N, N, N), - PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, RSVD3, 0x3178, N, N, N), - PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, UARTC, 0x317c, N, N, N), - PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, UARTC, 0x3180, N, N, N), - PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, RSVD4, 0x3184, N, N, N), - PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, RSVD4, 0x3188, N, N, N), - PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, RSVD4, 0x318c, N, N, N), - PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, PWM0, 0x3190, N, N, N), - PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, PWM1, 0x3194, N, N, N), - PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, PWM2, 0x3198, N, N, N), - PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, PWM3, 0x319c, N, N, N), - PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a0, Y, N, N), - PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a4, Y, N, N), - PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, RSVD4, 0x31a8, N, N, N), - PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31ac, N, N, N), - PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, RSVD4, 0x31b0, N, N, N), - PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b4, N, N, N), - PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b8, N, N, N), - PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31bc, N, N, N), - PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, RSVD1, 0x31c0, N, N, N), - PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, RSVD2, 0x31c4, N, N, N), - PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, NAND, 0x31c8, N, N, N), - PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, RSVD1, 0x31cc, N, N, N), - PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, GMI, 0x31d0, N, N, N), - PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, RSVD1, 0x31d4, N, N, N), - PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, RSVD1, 0x31d8, N, N, N), - PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, GMI, 0x31dc, N, N, N), - PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, GMI, 0x31e0, N, N, N), - PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, GMI, 0x31e4, N, N, N), - PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, NAND, 0x31e8, N, N, N), - PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, NAND, 0x31ec, N, N, N), - PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f0, N, N, N), - PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f4, N, N, N), - PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f8, N, N, N), - PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31fc, N, N, N), - PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3200, N, N, N), - PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3204, N, N, N), - PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3208, N, N, N), - PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, RSVD1, 0x320c, N, N, N), - PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, GMI, 0x3210, N, N, N), - PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, GMI, 0x3214, N, N, N), - PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, GMI, 0x3218, N, N, N), - PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, GMI, 0x321c, N, N, N), - PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, RSVD4, 0x3220, N, N, N), - PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, RSVD4, 0x3224, N, N, N), - PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, GMI, 0x3228, N, N, N), - PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, GMI, 0x322c, N, N, N), - PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, GMI, 0x3230, N, N, N), - PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, RSVD2, 0x3234, N, N, N), - PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, RSVD2, 0x3238, N, N, N), - PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, GMI, 0x323c, N, N, N), - PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3240, N, N, N), - PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, RSVD1, 0x3244, N, N, N), - PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, NAND, 0x3248, N, N, N), - PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, RSVD4, 0x324c, N, N, N), - PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, RSVD4, 0x3250, Y, N, N), - PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, RSVD4, 0x3254, Y, N, N), - PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x3258, N, Y, N), - PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x325c, N, Y, N), - PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3260, N, Y, N), - PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3264, N, Y, N), - PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3268, N, Y, N), - PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x326c, N, Y, N), - PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3270, N, Y, N), - PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3274, N, Y, N), - PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3278, N, Y, N), - PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x327c, N, Y, N), - PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, RSVD4, 0x3284, N, N, N), - PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3288, N, N, N), - PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, I2S4, 0x328c, N, N, N), - PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, RSVD4, 0x3290, Y, N, N), - PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, RSVD4, 0x3294, Y, N, N), - PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x3298, N, N, N), - PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x329c, N, N, N), - PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a0, N, N, N), - PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a4, N, N, N), - PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32a8, N, N, N), - PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32ac, N, N, N), - PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b4, Y, N, N), - PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b8, Y, N, N), - PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32bc, N, N, N), - PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c0, N, N, N), - PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c4, N, N, N), - PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32c8, N, N, N), - PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, KBC, 0x32cc, N, N, N), - PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, KBC, 0x32d0, N, N, N), - PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, KBC, 0x32d4, N, N, N), - PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32d8, N, N, N), - PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32dc, N, N, N), - PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, RSVD3, 0x32e0, N, N, N), - PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, RSVD3, 0x32e4, N, N, N), - PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, KBC, 0x32fc, N, N, N), - PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, RSVD2, 0x3300, N, N, N), - PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, RSVD2, 0x3304, N, N, N), - PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, KBC, 0x3308, N, N, N), - PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, KBC, 0x330c, N, N, N), - PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, RSVD4, 0x3310, N, N, N), - PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3314, N, N, N), - PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3318, N, N, N), - PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, RSVD4, 0x331c, N, N, N), - PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, RSVD4, 0x3320, N, N, N), - PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, RSVD4, 0x3324, N, N, N), - PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, RSVD4, 0x3328, N, N, N), - PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, RSVD4, 0x332c, N, N, N), - PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x3334, N, N, Y), - PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3338, N, N, N), - PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, RSVD4, 0x333c, N, N, N), - PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3340, N, N, N), - PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3344, N, N, N), - PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, RSVD4, 0x3348, N, N, N), - PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, RSVD4, 0x334c, N, N, N), - PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, RSVD4, 0x3350, N, N, N), - PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, RSVD4, 0x3354, N, N, N), - PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3358, N, N, N), - PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x335c, N, N, N), - PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3360, N, N, N), - PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3364, N, N, N), - PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, RSVD4, 0x3368, N, N, N), - PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, RSVD4, 0x336c, N, N, N), - PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, RSVD4, 0x3370, N, N, N), - PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, RSVD4, 0x3374, N, N, N), - PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, RSVD1, 0x3378, N, N, N), - PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, RSVD1, 0x337c, N, N, N), - PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, RSVD4, 0x3380, N, N, N), - PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, RSVD4, 0x3384, N, N, N), - PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, RSVD3, 0x3390, N, N, N), - PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, SDMMC3, 0x3394, N, N, N), - PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, RSVD3, 0x3398, N, N, N), - PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, SDMMC3, 0x339c, N, N, N), - PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, SDMMC3, 0x33a0, N, N, N), - PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, SDMMC3, 0x33a4, N, N, N), - PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, RSVD3, 0x33e0, Y, N, N), - PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, SDMMC1, 0x33e4, N, N, N), - PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, RSVD4, 0x33e8, N, N, N), - PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, RSVD2, 0x33ec, N, N, N), - PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, SPI6, 0x33f0, N, N, N), - PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f4, Y, N, N), - PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f8, Y, N, N), - PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x33fc, N, N, N), - PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x3400, N, N, N), - PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD3, 0x3408, N, N, N), + /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */ + PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N), + PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N), + PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N), + PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N), + PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N), + PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N), + PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N), + PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N), + PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N), + PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N), + PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N), + PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N), + PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N), + PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N), + PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3038, N, N, N), + PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x303c, N, N, N), + PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N), + PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N), + PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N), + PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N), + PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N), + PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N), + PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N), + PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N), + PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N), + PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N), + PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y), + PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y), + PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y), + PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N), + PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N), + PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, 0x316c, N, N, N), + PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, 0x3170, N, N, N), + PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, 0x3174, N, N, N), + PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, 0x3178, N, N, N), + PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, 0x317c, N, N, N), + PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, 0x3180, N, N, N), + PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, 0x3184, N, N, N), + PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, 0x3188, N, N, N), + PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, 0x318c, N, N, N), + PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, 0x3190, N, N, N), + PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, 0x3194, N, N, N), + PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, 0x3198, N, N, N), + PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, 0x319c, N, N, N), + PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N), + PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N), + PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, 0x31a8, N, N, N), + PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, 0x31ac, N, N, N), + PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, 0x31b0, N, N, N), + PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, 0x31b4, N, N, N), + PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N), + PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N), + PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N, N), + PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, 0x31c4, N, N, N), + PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N, N), + PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N, N), + PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N, N), + PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N, N), + PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N, N), + PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N, N), + PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N, N), + PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N, N), + PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N, N), + PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, 0x31ec, N, N, N), + PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N, N), + PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N, N), + PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N, N), + PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N, N), + PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N, N), + PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, 0x3204, N, N, N), + PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, 0x3208, N, N, N), + PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, 0x320c, N, N, N), + PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, 0x3210, N, N, N), + PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, 0x3214, N, N, N), + PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, 0x3218, N, N, N), + PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, 0x321c, N, N, N), + PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, 0x3220, N, N, N), + PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, 0x3224, N, N, N), + PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, 0x3228, N, N, N), + PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, 0x322c, N, N, N), + PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, 0x3230, N, N, N), + PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, 0x3234, N, N, N), + PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, 0x3238, N, N, N), + PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, 0x323c, N, N, N), + PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, 0x3240, N, N, N), + PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, 0x3244, N, N, N), + PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, 0x3248, N, N, N), + PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N, N), + PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N), + PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N), + PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N), + PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N), + PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N), + PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N), + PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N), + PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N), + PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N), + PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, 0x3274, N, Y, N), + PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N), + PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N), + PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, 0x3284, N, N, N), + PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, 0x3288, N, N, N), + PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, 0x328c, N, N, N), + PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, 0x3290, Y, N, N), + PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, 0x3294, Y, N, N), + PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, 0x3298, N, N, N), + PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, 0x329c, N, N, N), + PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, 0x32a0, N, N, N), + PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, 0x32a4, N, N, N), + PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, 0x32a8, N, N, N), + PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N, N), + PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N), + PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N), + PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N), + PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N), + PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N), + PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N), + PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32c8, N, N, N), + PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32cc, N, N, N), + PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32d0, N, N, N), + PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N), + PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N), + PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N), + PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N), + PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N), + PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, 0x32fc, N, N, N), + PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, 0x3300, N, N, N), + PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N), + PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N), + PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N), + PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, 0x3310, N, N, N), + PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, 0x3314, N, N, N), + PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, 0x3318, N, N, N), + PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N), + PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N, N), + PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N), + PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N), + PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N), + PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N), + PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y), + PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N), + PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N), + PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, 0x3340, N, N, N), + PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N), + PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, 0x3348, N, N, N), + PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N), + PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, 0x3350, N, N, N), + PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, 0x3354, N, N, N), + PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, 0x3358, N, N, N), + PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, 0x335c, N, N, N), + PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, 0x3360, N, N, N), + PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, 0x3364, N, N, N), + PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, 0x3368, N, N, N), + PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, 0x336c, N, N, N), + PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, 0x3370, N, N, N), + PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, 0x3374, N, N, N), + PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, 0x3378, N, N, N), + PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, 0x337c, N, N, N), + PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, 0x3380, N, N, N), + PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N), + PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N), + PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N), + PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N), + PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N), + PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N), + PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N), + PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, 0x33e0, Y, N, N), + PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N), + PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N), + PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N), + PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N), + PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N), + PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N), + PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N), + PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N), + PINGROUP(gmi_clk_lb, SDMMC2, NAND, GMI, RSVD4, 0x3404, N, N, N), + PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N), /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */ - DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), - DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), - DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), - DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), - DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), - DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), - DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y), - DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), - DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(at1, 0x870, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y), + DRV_PINGROUP(at2, 0x874, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y), + DRV_PINGROUP(at3, 0x878, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y), + DRV_PINGROUP(at4, 0x87c, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y), + DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), + DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), + DRV_PINGROUP(ddc, 0x8fc, 2, 3, -1, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gma, 0x900, 2, 3, -1, 14, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, Y), + DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(ao3, 0x9a0, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), + DRV_PINGROUP(hv0, 0x9a4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), + DRV_PINGROUP(sdio4, 0x9a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(ao0, 0x9ac, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), }; static const struct tegra_pinctrl_soc_data tegra114_pinctrl = { @@ -2763,7 +1867,6 @@ static struct platform_driver tegra114_pinctrl_driver = { }; module_platform_driver(tegra114_pinctrl_driver); -MODULE_ALIAS("platform:tegra114-pinctrl"); MODULE_AUTHOR("Pritesh Raithatha <praithatha@nvidia.com>"); -MODULE_DESCRIPTION("NVIDIA Tegra114 pincontrol driver"); +MODULE_DESCRIPTION("NVIDIA Tegra114 pinctrl driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c new file mode 100644 index 00000000000..e80797e2001 --- /dev/null +++ b/drivers/pinctrl/pinctrl-tegra124.c @@ -0,0 +1,2018 @@ +/* + * Pinctrl data for the NVIDIA Tegra124 pinmux + * + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinctrl-tegra.h" + +/* + * Most pins affected by the pinmux can also be GPIOs. Define these first. + * These must match how the GPIO driver names/numbers its pins. + */ +#define _GPIO(offset) (offset) + +#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0) +#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1) +#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2) +#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3) +#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4) +#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5) +#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6) +#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7) +#define TEGRA_PIN_PB0 _GPIO(8) +#define TEGRA_PIN_PB1 _GPIO(9) +#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12) +#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13) +#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14) +#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15) +#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16) +#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18) +#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19) +#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20) +#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21) +#define TEGRA_PIN_PC7 _GPIO(23) +#define TEGRA_PIN_PG0 _GPIO(48) +#define TEGRA_PIN_PG1 _GPIO(49) +#define TEGRA_PIN_PG2 _GPIO(50) +#define TEGRA_PIN_PG3 _GPIO(51) +#define TEGRA_PIN_PG4 _GPIO(52) +#define TEGRA_PIN_PG5 _GPIO(53) +#define TEGRA_PIN_PG6 _GPIO(54) +#define TEGRA_PIN_PG7 _GPIO(55) +#define TEGRA_PIN_PH0 _GPIO(56) +#define TEGRA_PIN_PH1 _GPIO(57) +#define TEGRA_PIN_PH2 _GPIO(58) +#define TEGRA_PIN_PH3 _GPIO(59) +#define TEGRA_PIN_PH4 _GPIO(60) +#define TEGRA_PIN_PH5 _GPIO(61) +#define TEGRA_PIN_PH6 _GPIO(62) +#define TEGRA_PIN_PH7 _GPIO(63) +#define TEGRA_PIN_PI0 _GPIO(64) +#define TEGRA_PIN_PI1 _GPIO(65) +#define TEGRA_PIN_PI2 _GPIO(66) +#define TEGRA_PIN_PI3 _GPIO(67) +#define TEGRA_PIN_PI4 _GPIO(68) +#define TEGRA_PIN_PI5 _GPIO(69) +#define TEGRA_PIN_PI6 _GPIO(70) +#define TEGRA_PIN_PI7 _GPIO(71) +#define TEGRA_PIN_PJ0 _GPIO(72) +#define TEGRA_PIN_PJ2 _GPIO(74) +#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77) +#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78) +#define TEGRA_PIN_PJ7 _GPIO(79) +#define TEGRA_PIN_PK0 _GPIO(80) +#define TEGRA_PIN_PK1 _GPIO(81) +#define TEGRA_PIN_PK2 _GPIO(82) +#define TEGRA_PIN_PK3 _GPIO(83) +#define TEGRA_PIN_PK4 _GPIO(84) +#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85) +#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86) +#define TEGRA_PIN_PK7 _GPIO(87) +#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104) +#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105) +#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106) +#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107) +#define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108) +#define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109) +#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111) +#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112) +#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113) +#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114) +#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115) +#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116) +#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117) +#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118) +#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119) +#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120) +#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121) +#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122) +#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123) +#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124) +#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125) +#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126) +#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127) +#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128) +#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129) +#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130) +#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131) +#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132) +#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133) +#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134) +#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135) +#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136) +#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137) +#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138) +#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139) +#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140) +#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141) +#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142) +#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143) +#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144) +#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145) +#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146) +#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147) +#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148) +#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149) +#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150) +#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151) +#define TEGRA_PIN_KB_ROW16_PT0 _GPIO(152) +#define TEGRA_PIN_KB_ROW17_PT1 _GPIO(153) +#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157) +#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158) +#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159) +#define TEGRA_PIN_PU0 _GPIO(160) +#define TEGRA_PIN_PU1 _GPIO(161) +#define TEGRA_PIN_PU2 _GPIO(162) +#define TEGRA_PIN_PU3 _GPIO(163) +#define TEGRA_PIN_PU4 _GPIO(164) +#define TEGRA_PIN_PU5 _GPIO(165) +#define TEGRA_PIN_PU6 _GPIO(166) +#define TEGRA_PIN_PV0 _GPIO(168) +#define TEGRA_PIN_PV1 _GPIO(169) +#define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170) +#define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171) +#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172) +#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173) +#define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178) +#define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179) +#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180) +#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181) +#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182) +#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183) +#define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184) +#define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185) +#define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186) +#define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187) +#define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188) +#define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189) +#define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190) +#define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191) +#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192) +#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193) +#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194) +#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195) +#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196) +#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197) +#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198) +#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199) +#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200) +#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201) +#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206) +#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207) +#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208) +#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209) +#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210) +#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211) +#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212) +#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213) +#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214) +#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215) +#define TEGRA_PIN_PBB0 _GPIO(216) +#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217) +#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218) +#define TEGRA_PIN_PBB3 _GPIO(219) +#define TEGRA_PIN_PBB4 _GPIO(220) +#define TEGRA_PIN_PBB5 _GPIO(221) +#define TEGRA_PIN_PBB6 _GPIO(222) +#define TEGRA_PIN_PBB7 _GPIO(223) +#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224) +#define TEGRA_PIN_PCC1 _GPIO(225) +#define TEGRA_PIN_PCC2 _GPIO(226) +#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228) +#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229) +#define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233) +#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234) +#define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235) +#define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237) +#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238) +#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240) +#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241) +#define TEGRA_PIN_DAP_MCLK1_REQ_PEE2 _GPIO(242) +#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243) +#define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244) +#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245) +#define TEGRA_PIN_DP_HPD_PFF0 _GPIO(248) +#define TEGRA_PIN_USB_VBUS_EN2_PFF1 _GPIO(249) +#define TEGRA_PIN_PFF2 _GPIO(250) + +/* All non-GPIO pins follow */ +#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1) +#define _PIN(offset) (NUM_GPIOS + (offset)) + +/* Non-GPIO pins */ +#define TEGRA_PIN_CORE_PWR_REQ _PIN(0) +#define TEGRA_PIN_CPU_PWR_REQ _PIN(1) +#define TEGRA_PIN_PWR_INT_N _PIN(2) +#define TEGRA_PIN_GMI_CLK_LB _PIN(3) +#define TEGRA_PIN_RESET_OUT_N _PIN(4) +#define TEGRA_PIN_OWR _PIN(5) +#define TEGRA_PIN_CLK_32K_IN _PIN(6) +#define TEGRA_PIN_JTAG_RTCK _PIN(7) + +static const struct pinctrl_pin_desc tegra124_pins[] = { + PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), + PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"), + PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"), + PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"), + PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"), + PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"), + PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"), + PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"), + PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"), + PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"), + PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"), + PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"), + PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"), + PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"), + PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"), + PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"), + PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"), + PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"), + PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"), + PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"), + PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"), + PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"), + PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"), + PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"), + PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"), + PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"), + PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"), + PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"), + PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"), + PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"), + PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"), + PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"), + PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"), + PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"), + PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"), + PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"), + PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"), + PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"), + PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"), + PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"), + PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"), + PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"), + PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"), + PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"), + PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"), + PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"), + PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"), + PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"), + PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"), + PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"), + PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"), + PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"), + PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"), + PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"), + PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"), + PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"), + PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"), + PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"), + PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"), + PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"), + PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"), + PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"), + PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"), + PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"), + PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"), + PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"), + PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"), + PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"), + PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"), + PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"), + PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"), + PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"), + PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"), + PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"), + PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"), + PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"), + PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"), + PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"), + PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"), + PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"), + PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"), + PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"), + PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"), + PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"), + PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"), + PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"), + PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"), + PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"), + PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"), + PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"), + PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"), + PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"), + PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"), + PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"), + PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"), + PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"), + PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"), + PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"), + PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"), + PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"), + PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"), + PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"), + PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"), + PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"), + PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"), + PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"), + PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"), + PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"), + PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"), + PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"), + PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"), + PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"), + PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"), + PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"), + PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"), + PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"), + PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"), + PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"), + PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"), + PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"), + PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"), + PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"), + PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"), + PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"), + PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"), + PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"), + PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"), + PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"), + PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"), + PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"), + PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"), + PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"), + PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"), + PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"), + PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"), + PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"), + PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"), + PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"), + PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"), + PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"), + PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"), + PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"), + PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"), + PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"), + PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), + PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), +}; + +static const unsigned clk_32k_out_pa0_pins[] = { + TEGRA_PIN_CLK_32K_OUT_PA0, +}; + +static const unsigned uart3_cts_n_pa1_pins[] = { + TEGRA_PIN_UART3_CTS_N_PA1, +}; + +static const unsigned dap2_fs_pa2_pins[] = { + TEGRA_PIN_DAP2_FS_PA2, +}; + +static const unsigned dap2_sclk_pa3_pins[] = { + TEGRA_PIN_DAP2_SCLK_PA3, +}; + +static const unsigned dap2_din_pa4_pins[] = { + TEGRA_PIN_DAP2_DIN_PA4, +}; + +static const unsigned dap2_dout_pa5_pins[] = { + TEGRA_PIN_DAP2_DOUT_PA5, +}; + +static const unsigned sdmmc3_clk_pa6_pins[] = { + TEGRA_PIN_SDMMC3_CLK_PA6, +}; + +static const unsigned sdmmc3_cmd_pa7_pins[] = { + TEGRA_PIN_SDMMC3_CMD_PA7, +}; + +static const unsigned pb0_pins[] = { + TEGRA_PIN_PB0, +}; + +static const unsigned pb1_pins[] = { + TEGRA_PIN_PB1, +}; + +static const unsigned sdmmc3_dat3_pb4_pins[] = { + TEGRA_PIN_SDMMC3_DAT3_PB4, +}; + +static const unsigned sdmmc3_dat2_pb5_pins[] = { + TEGRA_PIN_SDMMC3_DAT2_PB5, +}; + +static const unsigned sdmmc3_dat1_pb6_pins[] = { + TEGRA_PIN_SDMMC3_DAT1_PB6, +}; + +static const unsigned sdmmc3_dat0_pb7_pins[] = { + TEGRA_PIN_SDMMC3_DAT0_PB7, +}; + +static const unsigned uart3_rts_n_pc0_pins[] = { + TEGRA_PIN_UART3_RTS_N_PC0, +}; + +static const unsigned uart2_txd_pc2_pins[] = { + TEGRA_PIN_UART2_TXD_PC2, +}; + +static const unsigned uart2_rxd_pc3_pins[] = { + TEGRA_PIN_UART2_RXD_PC3, +}; + +static const unsigned gen1_i2c_scl_pc4_pins[] = { + TEGRA_PIN_GEN1_I2C_SCL_PC4, +}; + +static const unsigned gen1_i2c_sda_pc5_pins[] = { + TEGRA_PIN_GEN1_I2C_SDA_PC5, +}; + +static const unsigned pc7_pins[] = { + TEGRA_PIN_PC7, +}; + +static const unsigned pg0_pins[] = { + TEGRA_PIN_PG0, +}; + +static const unsigned pg1_pins[] = { + TEGRA_PIN_PG1, +}; + +static const unsigned pg2_pins[] = { + TEGRA_PIN_PG2, +}; + +static const unsigned pg3_pins[] = { + TEGRA_PIN_PG3, +}; + +static const unsigned pg4_pins[] = { + TEGRA_PIN_PG4, +}; + +static const unsigned pg5_pins[] = { + TEGRA_PIN_PG5, +}; + +static const unsigned pg6_pins[] = { + TEGRA_PIN_PG6, +}; + +static const unsigned pg7_pins[] = { + TEGRA_PIN_PG7, +}; + +static const unsigned ph0_pins[] = { + TEGRA_PIN_PH0, +}; + +static const unsigned ph1_pins[] = { + TEGRA_PIN_PH1, +}; + +static const unsigned ph2_pins[] = { + TEGRA_PIN_PH2, +}; + +static const unsigned ph3_pins[] = { + TEGRA_PIN_PH3, +}; + +static const unsigned ph4_pins[] = { + TEGRA_PIN_PH4, +}; + +static const unsigned ph5_pins[] = { + TEGRA_PIN_PH5, +}; + +static const unsigned ph6_pins[] = { + TEGRA_PIN_PH6, +}; + +static const unsigned ph7_pins[] = { + TEGRA_PIN_PH7, +}; + +static const unsigned pi0_pins[] = { + TEGRA_PIN_PI0, +}; + +static const unsigned pi1_pins[] = { + TEGRA_PIN_PI1, +}; + +static const unsigned pi2_pins[] = { + TEGRA_PIN_PI2, +}; + +static const unsigned pi3_pins[] = { + TEGRA_PIN_PI3, +}; + +static const unsigned pi4_pins[] = { + TEGRA_PIN_PI4, +}; + +static const unsigned pi5_pins[] = { + TEGRA_PIN_PI5, +}; + +static const unsigned pi6_pins[] = { + TEGRA_PIN_PI6, +}; + +static const unsigned pi7_pins[] = { + TEGRA_PIN_PI7, +}; + +static const unsigned pj0_pins[] = { + TEGRA_PIN_PJ0, +}; + +static const unsigned pj2_pins[] = { + TEGRA_PIN_PJ2, +}; + +static const unsigned uart2_cts_n_pj5_pins[] = { + TEGRA_PIN_UART2_CTS_N_PJ5, +}; + +static const unsigned uart2_rts_n_pj6_pins[] = { + TEGRA_PIN_UART2_RTS_N_PJ6, +}; + +static const unsigned pj7_pins[] = { + TEGRA_PIN_PJ7, +}; + +static const unsigned pk0_pins[] = { + TEGRA_PIN_PK0, +}; + +static const unsigned pk1_pins[] = { + TEGRA_PIN_PK1, +}; + +static const unsigned pk2_pins[] = { + TEGRA_PIN_PK2, +}; + +static const unsigned pk3_pins[] = { + TEGRA_PIN_PK3, +}; + +static const unsigned pk4_pins[] = { + TEGRA_PIN_PK4, +}; + +static const unsigned spdif_out_pk5_pins[] = { + TEGRA_PIN_SPDIF_OUT_PK5, +}; + +static const unsigned spdif_in_pk6_pins[] = { + TEGRA_PIN_SPDIF_IN_PK6, +}; + +static const unsigned pk7_pins[] = { + TEGRA_PIN_PK7, +}; + +static const unsigned dap1_fs_pn0_pins[] = { + TEGRA_PIN_DAP1_FS_PN0, +}; + +static const unsigned dap1_din_pn1_pins[] = { + TEGRA_PIN_DAP1_DIN_PN1, +}; + +static const unsigned dap1_dout_pn2_pins[] = { + TEGRA_PIN_DAP1_DOUT_PN2, +}; + +static const unsigned dap1_sclk_pn3_pins[] = { + TEGRA_PIN_DAP1_SCLK_PN3, +}; + +static const unsigned usb_vbus_en0_pn4_pins[] = { + TEGRA_PIN_USB_VBUS_EN0_PN4, +}; + +static const unsigned usb_vbus_en1_pn5_pins[] = { + TEGRA_PIN_USB_VBUS_EN1_PN5, +}; + +static const unsigned hdmi_int_pn7_pins[] = { + TEGRA_PIN_HDMI_INT_PN7, +}; + +static const unsigned ulpi_data7_po0_pins[] = { + TEGRA_PIN_ULPI_DATA7_PO0, +}; + +static const unsigned ulpi_data0_po1_pins[] = { + TEGRA_PIN_ULPI_DATA0_PO1, +}; + +static const unsigned ulpi_data1_po2_pins[] = { + TEGRA_PIN_ULPI_DATA1_PO2, +}; + +static const unsigned ulpi_data2_po3_pins[] = { + TEGRA_PIN_ULPI_DATA2_PO3, +}; + +static const unsigned ulpi_data3_po4_pins[] = { + TEGRA_PIN_ULPI_DATA3_PO4, +}; + +static const unsigned ulpi_data4_po5_pins[] = { + TEGRA_PIN_ULPI_DATA4_PO5, +}; + +static const unsigned ulpi_data5_po6_pins[] = { + TEGRA_PIN_ULPI_DATA5_PO6, +}; + +static const unsigned ulpi_data6_po7_pins[] = { + TEGRA_PIN_ULPI_DATA6_PO7, +}; + +static const unsigned dap3_fs_pp0_pins[] = { + TEGRA_PIN_DAP3_FS_PP0, +}; + +static const unsigned dap3_din_pp1_pins[] = { + TEGRA_PIN_DAP3_DIN_PP1, +}; + +static const unsigned dap3_dout_pp2_pins[] = { + TEGRA_PIN_DAP3_DOUT_PP2, +}; + +static const unsigned dap3_sclk_pp3_pins[] = { + TEGRA_PIN_DAP3_SCLK_PP3, +}; + +static const unsigned dap4_fs_pp4_pins[] = { + TEGRA_PIN_DAP4_FS_PP4, +}; + +static const unsigned dap4_din_pp5_pins[] = { + TEGRA_PIN_DAP4_DIN_PP5, +}; + +static const unsigned dap4_dout_pp6_pins[] = { + TEGRA_PIN_DAP4_DOUT_PP6, +}; + +static const unsigned dap4_sclk_pp7_pins[] = { + TEGRA_PIN_DAP4_SCLK_PP7, +}; + +static const unsigned kb_col0_pq0_pins[] = { + TEGRA_PIN_KB_COL0_PQ0, +}; + +static const unsigned kb_col1_pq1_pins[] = { + TEGRA_PIN_KB_COL1_PQ1, +}; + +static const unsigned kb_col2_pq2_pins[] = { + TEGRA_PIN_KB_COL2_PQ2, +}; + +static const unsigned kb_col3_pq3_pins[] = { + TEGRA_PIN_KB_COL3_PQ3, +}; + +static const unsigned kb_col4_pq4_pins[] = { + TEGRA_PIN_KB_COL4_PQ4, +}; + +static const unsigned kb_col5_pq5_pins[] = { + TEGRA_PIN_KB_COL5_PQ5, +}; + +static const unsigned kb_col6_pq6_pins[] = { + TEGRA_PIN_KB_COL6_PQ6, +}; + +static const unsigned kb_col7_pq7_pins[] = { + TEGRA_PIN_KB_COL7_PQ7, +}; + +static const unsigned kb_row0_pr0_pins[] = { + TEGRA_PIN_KB_ROW0_PR0, +}; + +static const unsigned kb_row1_pr1_pins[] = { + TEGRA_PIN_KB_ROW1_PR1, +}; + +static const unsigned kb_row2_pr2_pins[] = { + TEGRA_PIN_KB_ROW2_PR2, +}; + +static const unsigned kb_row3_pr3_pins[] = { + TEGRA_PIN_KB_ROW3_PR3, +}; + +static const unsigned kb_row4_pr4_pins[] = { + TEGRA_PIN_KB_ROW4_PR4, +}; + +static const unsigned kb_row5_pr5_pins[] = { + TEGRA_PIN_KB_ROW5_PR5, +}; + +static const unsigned kb_row6_pr6_pins[] = { + TEGRA_PIN_KB_ROW6_PR6, +}; + +static const unsigned kb_row7_pr7_pins[] = { + TEGRA_PIN_KB_ROW7_PR7, +}; + +static const unsigned kb_row8_ps0_pins[] = { + TEGRA_PIN_KB_ROW8_PS0, +}; + +static const unsigned kb_row9_ps1_pins[] = { + TEGRA_PIN_KB_ROW9_PS1, +}; + +static const unsigned kb_row10_ps2_pins[] = { + TEGRA_PIN_KB_ROW10_PS2, +}; + +static const unsigned kb_row11_ps3_pins[] = { + TEGRA_PIN_KB_ROW11_PS3, +}; + +static const unsigned kb_row12_ps4_pins[] = { + TEGRA_PIN_KB_ROW12_PS4, +}; + +static const unsigned kb_row13_ps5_pins[] = { + TEGRA_PIN_KB_ROW13_PS5, +}; + +static const unsigned kb_row14_ps6_pins[] = { + TEGRA_PIN_KB_ROW14_PS6, +}; + +static const unsigned kb_row15_ps7_pins[] = { + TEGRA_PIN_KB_ROW15_PS7, +}; + +static const unsigned kb_row16_pt0_pins[] = { + TEGRA_PIN_KB_ROW16_PT0, +}; + +static const unsigned kb_row17_pt1_pins[] = { + TEGRA_PIN_KB_ROW17_PT1, +}; + +static const unsigned gen2_i2c_scl_pt5_pins[] = { + TEGRA_PIN_GEN2_I2C_SCL_PT5, +}; + +static const unsigned gen2_i2c_sda_pt6_pins[] = { + TEGRA_PIN_GEN2_I2C_SDA_PT6, +}; + +static const unsigned sdmmc4_cmd_pt7_pins[] = { + TEGRA_PIN_SDMMC4_CMD_PT7, +}; + +static const unsigned pu0_pins[] = { + TEGRA_PIN_PU0, +}; + +static const unsigned pu1_pins[] = { + TEGRA_PIN_PU1, +}; + +static const unsigned pu2_pins[] = { + TEGRA_PIN_PU2, +}; + +static const unsigned pu3_pins[] = { + TEGRA_PIN_PU3, +}; + +static const unsigned pu4_pins[] = { + TEGRA_PIN_PU4, +}; + +static const unsigned pu5_pins[] = { + TEGRA_PIN_PU5, +}; + +static const unsigned pu6_pins[] = { + TEGRA_PIN_PU6, +}; + +static const unsigned pv0_pins[] = { + TEGRA_PIN_PV0, +}; + +static const unsigned pv1_pins[] = { + TEGRA_PIN_PV1, +}; + +static const unsigned sdmmc3_cd_n_pv2_pins[] = { + TEGRA_PIN_SDMMC3_CD_N_PV2, +}; + +static const unsigned sdmmc1_wp_n_pv3_pins[] = { + TEGRA_PIN_SDMMC1_WP_N_PV3, +}; + +static const unsigned ddc_scl_pv4_pins[] = { + TEGRA_PIN_DDC_SCL_PV4, +}; + +static const unsigned ddc_sda_pv5_pins[] = { + TEGRA_PIN_DDC_SDA_PV5, +}; + +static const unsigned gpio_w2_aud_pw2_pins[] = { + TEGRA_PIN_GPIO_W2_AUD_PW2, +}; + +static const unsigned gpio_w3_aud_pw3_pins[] = { + TEGRA_PIN_GPIO_W3_AUD_PW3, +}; + +static const unsigned dap_mclk1_pw4_pins[] = { + TEGRA_PIN_DAP_MCLK1_PW4, +}; + +static const unsigned clk2_out_pw5_pins[] = { + TEGRA_PIN_CLK2_OUT_PW5, +}; + +static const unsigned uart3_txd_pw6_pins[] = { + TEGRA_PIN_UART3_TXD_PW6, +}; + +static const unsigned uart3_rxd_pw7_pins[] = { + TEGRA_PIN_UART3_RXD_PW7, +}; + +static const unsigned dvfs_pwm_px0_pins[] = { + TEGRA_PIN_DVFS_PWM_PX0, +}; + +static const unsigned gpio_x1_aud_px1_pins[] = { + TEGRA_PIN_GPIO_X1_AUD_PX1, +}; + +static const unsigned dvfs_clk_px2_pins[] = { + TEGRA_PIN_DVFS_CLK_PX2, +}; + +static const unsigned gpio_x3_aud_px3_pins[] = { + TEGRA_PIN_GPIO_X3_AUD_PX3, +}; + +static const unsigned gpio_x4_aud_px4_pins[] = { + TEGRA_PIN_GPIO_X4_AUD_PX4, +}; + +static const unsigned gpio_x5_aud_px5_pins[] = { + TEGRA_PIN_GPIO_X5_AUD_PX5, +}; + +static const unsigned gpio_x6_aud_px6_pins[] = { + TEGRA_PIN_GPIO_X6_AUD_PX6, +}; + +static const unsigned gpio_x7_aud_px7_pins[] = { + TEGRA_PIN_GPIO_X7_AUD_PX7, +}; + +static const unsigned ulpi_clk_py0_pins[] = { + TEGRA_PIN_ULPI_CLK_PY0, +}; + +static const unsigned ulpi_dir_py1_pins[] = { + TEGRA_PIN_ULPI_DIR_PY1, +}; + +static const unsigned ulpi_nxt_py2_pins[] = { + TEGRA_PIN_ULPI_NXT_PY2, +}; + +static const unsigned ulpi_stp_py3_pins[] = { + TEGRA_PIN_ULPI_STP_PY3, +}; + +static const unsigned sdmmc1_dat3_py4_pins[] = { + TEGRA_PIN_SDMMC1_DAT3_PY4, +}; + +static const unsigned sdmmc1_dat2_py5_pins[] = { + TEGRA_PIN_SDMMC1_DAT2_PY5, +}; + +static const unsigned sdmmc1_dat1_py6_pins[] = { + TEGRA_PIN_SDMMC1_DAT1_PY6, +}; + +static const unsigned sdmmc1_dat0_py7_pins[] = { + TEGRA_PIN_SDMMC1_DAT0_PY7, +}; + +static const unsigned sdmmc1_clk_pz0_pins[] = { + TEGRA_PIN_SDMMC1_CLK_PZ0, +}; + +static const unsigned sdmmc1_cmd_pz1_pins[] = { + TEGRA_PIN_SDMMC1_CMD_PZ1, +}; + +static const unsigned pwr_i2c_scl_pz6_pins[] = { + TEGRA_PIN_PWR_I2C_SCL_PZ6, +}; + +static const unsigned pwr_i2c_sda_pz7_pins[] = { + TEGRA_PIN_PWR_I2C_SDA_PZ7, +}; + +static const unsigned sdmmc4_dat0_paa0_pins[] = { + TEGRA_PIN_SDMMC4_DAT0_PAA0, +}; + +static const unsigned sdmmc4_dat1_paa1_pins[] = { + TEGRA_PIN_SDMMC4_DAT1_PAA1, +}; + +static const unsigned sdmmc4_dat2_paa2_pins[] = { + TEGRA_PIN_SDMMC4_DAT2_PAA2, +}; + +static const unsigned sdmmc4_dat3_paa3_pins[] = { + TEGRA_PIN_SDMMC4_DAT3_PAA3, +}; + +static const unsigned sdmmc4_dat4_paa4_pins[] = { + TEGRA_PIN_SDMMC4_DAT4_PAA4, +}; + +static const unsigned sdmmc4_dat5_paa5_pins[] = { + TEGRA_PIN_SDMMC4_DAT5_PAA5, +}; + +static const unsigned sdmmc4_dat6_paa6_pins[] = { + TEGRA_PIN_SDMMC4_DAT6_PAA6, +}; + +static const unsigned sdmmc4_dat7_paa7_pins[] = { + TEGRA_PIN_SDMMC4_DAT7_PAA7, +}; + +static const unsigned pbb0_pins[] = { + TEGRA_PIN_PBB0, +}; + +static const unsigned cam_i2c_scl_pbb1_pins[] = { + TEGRA_PIN_CAM_I2C_SCL_PBB1, +}; + +static const unsigned cam_i2c_sda_pbb2_pins[] = { + TEGRA_PIN_CAM_I2C_SDA_PBB2, +}; + +static const unsigned pbb3_pins[] = { + TEGRA_PIN_PBB3, +}; + +static const unsigned pbb4_pins[] = { + TEGRA_PIN_PBB4, +}; + +static const unsigned pbb5_pins[] = { + TEGRA_PIN_PBB5, +}; + +static const unsigned pbb6_pins[] = { + TEGRA_PIN_PBB6, +}; + +static const unsigned pbb7_pins[] = { + TEGRA_PIN_PBB7, +}; + +static const unsigned cam_mclk_pcc0_pins[] = { + TEGRA_PIN_CAM_MCLK_PCC0, +}; + +static const unsigned pcc1_pins[] = { + TEGRA_PIN_PCC1, +}; + +static const unsigned pcc2_pins[] = { + TEGRA_PIN_PCC2, +}; + +static const unsigned sdmmc4_clk_pcc4_pins[] = { + TEGRA_PIN_SDMMC4_CLK_PCC4, +}; + +static const unsigned clk2_req_pcc5_pins[] = { + TEGRA_PIN_CLK2_REQ_PCC5, +}; + +static const unsigned pex_l0_rst_n_pdd1_pins[] = { + TEGRA_PIN_PEX_L0_RST_N_PDD1, +}; + +static const unsigned pex_l0_clkreq_n_pdd2_pins[] = { + TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, +}; + +static const unsigned pex_wake_n_pdd3_pins[] = { + TEGRA_PIN_PEX_WAKE_N_PDD3, +}; + +static const unsigned pex_l1_rst_n_pdd5_pins[] = { + TEGRA_PIN_PEX_L1_RST_N_PDD5, +}; + +static const unsigned pex_l1_clkreq_n_pdd6_pins[] = { + TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, +}; + +static const unsigned clk3_out_pee0_pins[] = { + TEGRA_PIN_CLK3_OUT_PEE0, +}; + +static const unsigned clk3_req_pee1_pins[] = { + TEGRA_PIN_CLK3_REQ_PEE1, +}; + +static const unsigned dap_mclk1_req_pee2_pins[] = { + TEGRA_PIN_DAP_MCLK1_REQ_PEE2, +}; + +static const unsigned hdmi_cec_pee3_pins[] = { + TEGRA_PIN_HDMI_CEC_PEE3, +}; + +static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = { + TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, +}; + +static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = { + TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, +}; + +static const unsigned dp_hpd_pff0_pins[] = { + TEGRA_PIN_DP_HPD_PFF0, +}; + +static const unsigned usb_vbus_en2_pff1_pins[] = { + TEGRA_PIN_USB_VBUS_EN2_PFF1, +}; + +static const unsigned pff2_pins[] = { + TEGRA_PIN_PFF2, +}; + +static const unsigned core_pwr_req_pins[] = { + TEGRA_PIN_CORE_PWR_REQ, +}; + +static const unsigned cpu_pwr_req_pins[] = { + TEGRA_PIN_CPU_PWR_REQ, +}; + +static const unsigned pwr_int_n_pins[] = { + TEGRA_PIN_PWR_INT_N, +}; + +static const unsigned gmi_clk_lb_pins[] = { + TEGRA_PIN_GMI_CLK_LB, +}; + +static const unsigned reset_out_n_pins[] = { + TEGRA_PIN_RESET_OUT_N, +}; + +static const unsigned owr_pins[] = { + TEGRA_PIN_OWR, +}; + +static const unsigned clk_32k_in_pins[] = { + TEGRA_PIN_CLK_32K_IN, +}; + +static const unsigned jtag_rtck_pins[] = { + TEGRA_PIN_JTAG_RTCK, +}; + +static const unsigned drive_ao1_pins[] = { + TEGRA_PIN_KB_ROW0_PR0, + TEGRA_PIN_KB_ROW1_PR1, + TEGRA_PIN_KB_ROW2_PR2, + TEGRA_PIN_KB_ROW3_PR3, + TEGRA_PIN_KB_ROW4_PR4, + TEGRA_PIN_KB_ROW5_PR5, + TEGRA_PIN_KB_ROW6_PR6, + TEGRA_PIN_KB_ROW7_PR7, + TEGRA_PIN_PWR_I2C_SCL_PZ6, + TEGRA_PIN_PWR_I2C_SDA_PZ7, +}; + +static const unsigned drive_ao2_pins[] = { + TEGRA_PIN_CLK_32K_OUT_PA0, + TEGRA_PIN_CLK_32K_IN, + TEGRA_PIN_KB_COL0_PQ0, + TEGRA_PIN_KB_COL1_PQ1, + TEGRA_PIN_KB_COL2_PQ2, + TEGRA_PIN_KB_COL3_PQ3, + TEGRA_PIN_KB_COL4_PQ4, + TEGRA_PIN_KB_COL5_PQ5, + TEGRA_PIN_KB_COL6_PQ6, + TEGRA_PIN_KB_COL7_PQ7, + TEGRA_PIN_KB_ROW8_PS0, + TEGRA_PIN_KB_ROW9_PS1, + TEGRA_PIN_KB_ROW10_PS2, + TEGRA_PIN_KB_ROW11_PS3, + TEGRA_PIN_KB_ROW12_PS4, + TEGRA_PIN_KB_ROW13_PS5, + TEGRA_PIN_KB_ROW14_PS6, + TEGRA_PIN_KB_ROW15_PS7, + TEGRA_PIN_KB_ROW16_PT0, + TEGRA_PIN_KB_ROW17_PT1, + TEGRA_PIN_SDMMC3_CD_N_PV2, + TEGRA_PIN_CORE_PWR_REQ, + TEGRA_PIN_CPU_PWR_REQ, + TEGRA_PIN_PWR_INT_N, +}; + +static const unsigned drive_at1_pins[] = { + TEGRA_PIN_PH0, + TEGRA_PIN_PH1, + TEGRA_PIN_PH2, + TEGRA_PIN_PH3, +}; + +static const unsigned drive_at2_pins[] = { + TEGRA_PIN_PG0, + TEGRA_PIN_PG1, + TEGRA_PIN_PG2, + TEGRA_PIN_PG3, + TEGRA_PIN_PG4, + TEGRA_PIN_PG5, + TEGRA_PIN_PG6, + TEGRA_PIN_PG7, + TEGRA_PIN_PI0, + TEGRA_PIN_PI1, + TEGRA_PIN_PI3, + TEGRA_PIN_PI4, + TEGRA_PIN_PI7, + TEGRA_PIN_PK0, + TEGRA_PIN_PK2, +}; + +static const unsigned drive_at3_pins[] = { + TEGRA_PIN_PC7, + TEGRA_PIN_PJ0, +}; + +static const unsigned drive_at4_pins[] = { + TEGRA_PIN_PB0, + TEGRA_PIN_PB1, + TEGRA_PIN_PJ0, + TEGRA_PIN_PJ7, + TEGRA_PIN_PK7, +}; + +static const unsigned drive_at5_pins[] = { + TEGRA_PIN_GEN2_I2C_SCL_PT5, + TEGRA_PIN_GEN2_I2C_SDA_PT6, +}; + +static const unsigned drive_cdev1_pins[] = { + TEGRA_PIN_DAP_MCLK1_PW4, + TEGRA_PIN_DAP_MCLK1_REQ_PEE2, +}; + +static const unsigned drive_cdev2_pins[] = { + TEGRA_PIN_CLK2_OUT_PW5, + TEGRA_PIN_CLK2_REQ_PCC5, +}; + +static const unsigned drive_dap1_pins[] = { + TEGRA_PIN_DAP1_FS_PN0, + TEGRA_PIN_DAP1_DIN_PN1, + TEGRA_PIN_DAP1_DOUT_PN2, + TEGRA_PIN_DAP1_SCLK_PN3, +}; + +static const unsigned drive_dap2_pins[] = { + TEGRA_PIN_DAP2_FS_PA2, + TEGRA_PIN_DAP2_SCLK_PA3, + TEGRA_PIN_DAP2_DIN_PA4, + TEGRA_PIN_DAP2_DOUT_PA5, +}; + +static const unsigned drive_dap3_pins[] = { + TEGRA_PIN_DAP3_FS_PP0, + TEGRA_PIN_DAP3_DIN_PP1, + TEGRA_PIN_DAP3_DOUT_PP2, + TEGRA_PIN_DAP3_SCLK_PP3, +}; + +static const unsigned drive_dap4_pins[] = { + TEGRA_PIN_DAP4_FS_PP4, + TEGRA_PIN_DAP4_DIN_PP5, + TEGRA_PIN_DAP4_DOUT_PP6, + TEGRA_PIN_DAP4_SCLK_PP7, +}; + +static const unsigned drive_dbg_pins[] = { + TEGRA_PIN_GEN1_I2C_SCL_PC4, + TEGRA_PIN_GEN1_I2C_SDA_PC5, + TEGRA_PIN_PU0, + TEGRA_PIN_PU1, + TEGRA_PIN_PU2, + TEGRA_PIN_PU3, + TEGRA_PIN_PU4, + TEGRA_PIN_PU5, + TEGRA_PIN_PU6, +}; + +static const unsigned drive_sdio3_pins[] = { + TEGRA_PIN_SDMMC3_CLK_PA6, + TEGRA_PIN_SDMMC3_CMD_PA7, + TEGRA_PIN_SDMMC3_DAT3_PB4, + TEGRA_PIN_SDMMC3_DAT2_PB5, + TEGRA_PIN_SDMMC3_DAT1_PB6, + TEGRA_PIN_SDMMC3_DAT0_PB7, + TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, + TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, +}; + +static const unsigned drive_spi_pins[] = { + TEGRA_PIN_DVFS_PWM_PX0, + TEGRA_PIN_GPIO_X1_AUD_PX1, + TEGRA_PIN_DVFS_CLK_PX2, + TEGRA_PIN_GPIO_X3_AUD_PX3, + TEGRA_PIN_GPIO_X4_AUD_PX4, + TEGRA_PIN_GPIO_X5_AUD_PX5, + TEGRA_PIN_GPIO_X6_AUD_PX6, + TEGRA_PIN_GPIO_X7_AUD_PX7, + TEGRA_PIN_GPIO_W2_AUD_PW2, + TEGRA_PIN_GPIO_W3_AUD_PW3, +}; + +static const unsigned drive_uaa_pins[] = { + TEGRA_PIN_ULPI_DATA0_PO1, + TEGRA_PIN_ULPI_DATA1_PO2, + TEGRA_PIN_ULPI_DATA2_PO3, + TEGRA_PIN_ULPI_DATA3_PO4, +}; + +static const unsigned drive_uab_pins[] = { + TEGRA_PIN_ULPI_DATA7_PO0, + TEGRA_PIN_ULPI_DATA4_PO5, + TEGRA_PIN_ULPI_DATA5_PO6, + TEGRA_PIN_ULPI_DATA6_PO7, + TEGRA_PIN_PV0, + TEGRA_PIN_PV1, +}; + +static const unsigned drive_uart2_pins[] = { + TEGRA_PIN_UART2_TXD_PC2, + TEGRA_PIN_UART2_RXD_PC3, + TEGRA_PIN_UART2_CTS_N_PJ5, + TEGRA_PIN_UART2_RTS_N_PJ6, +}; + +static const unsigned drive_uart3_pins[] = { + TEGRA_PIN_UART3_CTS_N_PA1, + TEGRA_PIN_UART3_RTS_N_PC0, + TEGRA_PIN_UART3_TXD_PW6, + TEGRA_PIN_UART3_RXD_PW7, +}; + +static const unsigned drive_sdio1_pins[] = { + TEGRA_PIN_SDMMC1_DAT3_PY4, + TEGRA_PIN_SDMMC1_DAT2_PY5, + TEGRA_PIN_SDMMC1_DAT1_PY6, + TEGRA_PIN_SDMMC1_DAT0_PY7, + TEGRA_PIN_SDMMC1_CLK_PZ0, + TEGRA_PIN_SDMMC1_CMD_PZ1, +}; + +static const unsigned drive_ddc_pins[] = { + TEGRA_PIN_DDC_SCL_PV4, + TEGRA_PIN_DDC_SDA_PV5, +}; + +static const unsigned drive_gma_pins[] = { + TEGRA_PIN_SDMMC4_CLK_PCC4, + TEGRA_PIN_SDMMC4_CMD_PT7, + TEGRA_PIN_SDMMC4_DAT0_PAA0, + TEGRA_PIN_SDMMC4_DAT1_PAA1, + TEGRA_PIN_SDMMC4_DAT2_PAA2, + TEGRA_PIN_SDMMC4_DAT3_PAA3, + TEGRA_PIN_SDMMC4_DAT4_PAA4, + TEGRA_PIN_SDMMC4_DAT5_PAA5, + TEGRA_PIN_SDMMC4_DAT6_PAA6, + TEGRA_PIN_SDMMC4_DAT7_PAA7, +}; + +static const unsigned drive_gme_pins[] = { + TEGRA_PIN_PBB0, + TEGRA_PIN_CAM_I2C_SCL_PBB1, + TEGRA_PIN_CAM_I2C_SDA_PBB2, + TEGRA_PIN_PBB3, + TEGRA_PIN_PCC2, +}; + +static const unsigned drive_gmf_pins[] = { + TEGRA_PIN_PBB4, + TEGRA_PIN_PBB5, + TEGRA_PIN_PBB6, + TEGRA_PIN_PBB7, +}; + +static const unsigned drive_gmg_pins[] = { + TEGRA_PIN_CAM_MCLK_PCC0, +}; + +static const unsigned drive_gmh_pins[] = { + TEGRA_PIN_PCC1, +}; + +static const unsigned drive_owr_pins[] = { + TEGRA_PIN_SDMMC3_CD_N_PV2, + TEGRA_PIN_OWR, +}; + +static const unsigned drive_uda_pins[] = { + TEGRA_PIN_ULPI_CLK_PY0, + TEGRA_PIN_ULPI_DIR_PY1, + TEGRA_PIN_ULPI_NXT_PY2, + TEGRA_PIN_ULPI_STP_PY3, +}; + +static const unsigned drive_gpv_pins[] = { + TEGRA_PIN_PEX_L0_RST_N_PDD1, + TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, + TEGRA_PIN_PEX_WAKE_N_PDD3, + TEGRA_PIN_PEX_L1_RST_N_PDD5, + TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, + TEGRA_PIN_USB_VBUS_EN2_PFF1, + TEGRA_PIN_PFF2, +}; + +static const unsigned drive_dev3_pins[] = { + TEGRA_PIN_CLK3_OUT_PEE0, + TEGRA_PIN_CLK3_REQ_PEE1, +}; + +static const unsigned drive_cec_pins[] = { + TEGRA_PIN_HDMI_CEC_PEE3, +}; + +static const unsigned drive_at6_pins[] = { + TEGRA_PIN_PK1, + TEGRA_PIN_PK3, + TEGRA_PIN_PK4, + TEGRA_PIN_PI2, + TEGRA_PIN_PI5, + TEGRA_PIN_PI6, + TEGRA_PIN_PH4, + TEGRA_PIN_PH5, + TEGRA_PIN_PH6, + TEGRA_PIN_PH7, +}; + +static const unsigned drive_dap5_pins[] = { + TEGRA_PIN_SPDIF_IN_PK6, + TEGRA_PIN_SPDIF_OUT_PK5, + TEGRA_PIN_DP_HPD_PFF0, +}; + +static const unsigned drive_usb_vbus_en_pins[] = { + TEGRA_PIN_USB_VBUS_EN0_PN4, + TEGRA_PIN_USB_VBUS_EN1_PN5, +}; + +static const unsigned drive_ao3_pins[] = { + TEGRA_PIN_RESET_OUT_N, +}; + +static const unsigned drive_ao0_pins[] = { + TEGRA_PIN_JTAG_RTCK, +}; + +static const unsigned drive_hv0_pins[] = { + TEGRA_PIN_HDMI_INT_PN7, +}; + +static const unsigned drive_sdio4_pins[] = { + TEGRA_PIN_SDMMC1_WP_N_PV3, +}; + +static const unsigned drive_ao4_pins[] = { + TEGRA_PIN_JTAG_RTCK, +}; + +enum tegra_mux { + TEGRA_MUX_BLINK, + TEGRA_MUX_CCLA, + TEGRA_MUX_CEC, + TEGRA_MUX_CLDVFS, + TEGRA_MUX_CLK, + TEGRA_MUX_CLK12, + TEGRA_MUX_CPU, + TEGRA_MUX_DAP, + TEGRA_MUX_DAP1, + TEGRA_MUX_DAP2, + TEGRA_MUX_DEV3, + TEGRA_MUX_DISPLAYA, + TEGRA_MUX_DISPLAYA_ALT, + TEGRA_MUX_DISPLAYB, + TEGRA_MUX_DP, + TEGRA_MUX_DTV, + TEGRA_MUX_EXTPERIPH1, + TEGRA_MUX_EXTPERIPH2, + TEGRA_MUX_EXTPERIPH3, + TEGRA_MUX_GMI, + TEGRA_MUX_GMI_ALT, + TEGRA_MUX_HDA, + TEGRA_MUX_HSI, + TEGRA_MUX_I2C1, + TEGRA_MUX_I2C2, + TEGRA_MUX_I2C3, + TEGRA_MUX_I2C4, + TEGRA_MUX_I2CPWR, + TEGRA_MUX_I2S0, + TEGRA_MUX_I2S1, + TEGRA_MUX_I2S2, + TEGRA_MUX_I2S3, + TEGRA_MUX_I2S4, + TEGRA_MUX_IRDA, + TEGRA_MUX_KBC, + TEGRA_MUX_OWR, + TEGRA_MUX_PE, + TEGRA_MUX_PE0, + TEGRA_MUX_PE1, + TEGRA_MUX_PMI, + TEGRA_MUX_PWM0, + TEGRA_MUX_PWM1, + TEGRA_MUX_PWM2, + TEGRA_MUX_PWM3, + TEGRA_MUX_PWRON, + TEGRA_MUX_RESET_OUT_N, + TEGRA_MUX_RSVD1, + TEGRA_MUX_RSVD2, + TEGRA_MUX_RSVD3, + TEGRA_MUX_RSVD4, + TEGRA_MUX_RTCK, + TEGRA_MUX_SATA, + TEGRA_MUX_SDMMC1, + TEGRA_MUX_SDMMC2, + TEGRA_MUX_SDMMC3, + TEGRA_MUX_SDMMC4, + TEGRA_MUX_SOC, + TEGRA_MUX_SPDIF, + TEGRA_MUX_SPI1, + TEGRA_MUX_SPI2, + TEGRA_MUX_SPI3, + TEGRA_MUX_SPI4, + TEGRA_MUX_SPI5, + TEGRA_MUX_SPI6, + TEGRA_MUX_SYS, + TEGRA_MUX_TMDS, + TEGRA_MUX_TRACE, + TEGRA_MUX_UARTA, + TEGRA_MUX_UARTB, + TEGRA_MUX_UARTC, + TEGRA_MUX_UARTD, + TEGRA_MUX_ULPI, + TEGRA_MUX_USB, + TEGRA_MUX_VGP1, + TEGRA_MUX_VGP2, + TEGRA_MUX_VGP3, + TEGRA_MUX_VGP4, + TEGRA_MUX_VGP5, + TEGRA_MUX_VGP6, + TEGRA_MUX_VI, + TEGRA_MUX_VI_ALT1, + TEGRA_MUX_VI_ALT3, + TEGRA_MUX_VIMCLK2, + TEGRA_MUX_VIMCLK2_ALT, +}; + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + } + +static struct tegra_function tegra124_functions[] = { + FUNCTION(blink), + FUNCTION(ccla), + FUNCTION(cec), + FUNCTION(cldvfs), + FUNCTION(clk), + FUNCTION(clk12), + FUNCTION(cpu), + FUNCTION(dap), + FUNCTION(dap1), + FUNCTION(dap2), + FUNCTION(dev3), + FUNCTION(displaya), + FUNCTION(displaya_alt), + FUNCTION(displayb), + FUNCTION(dp), + FUNCTION(dtv), + FUNCTION(extperiph1), + FUNCTION(extperiph2), + FUNCTION(extperiph3), + FUNCTION(gmi), + FUNCTION(gmi_alt), + FUNCTION(hda), + FUNCTION(hsi), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(i2c4), + FUNCTION(i2cpwr), + FUNCTION(i2s0), + FUNCTION(i2s1), + FUNCTION(i2s2), + FUNCTION(i2s3), + FUNCTION(i2s4), + FUNCTION(irda), + FUNCTION(kbc), + FUNCTION(owr), + FUNCTION(pe), + FUNCTION(pe0), + FUNCTION(pe1), + FUNCTION(pmi), + FUNCTION(pwm0), + FUNCTION(pwm1), + FUNCTION(pwm2), + FUNCTION(pwm3), + FUNCTION(pwron), + FUNCTION(reset_out_n), + FUNCTION(rsvd1), + FUNCTION(rsvd2), + FUNCTION(rsvd3), + FUNCTION(rsvd4), + FUNCTION(rtck), + FUNCTION(sata), + FUNCTION(sdmmc1), + FUNCTION(sdmmc2), + FUNCTION(sdmmc3), + FUNCTION(sdmmc4), + FUNCTION(soc), + FUNCTION(spdif), + FUNCTION(spi1), + FUNCTION(spi2), + FUNCTION(spi3), + FUNCTION(spi4), + FUNCTION(spi5), + FUNCTION(spi6), + FUNCTION(sys), + FUNCTION(tmds), + FUNCTION(trace), + FUNCTION(uarta), + FUNCTION(uartb), + FUNCTION(uartc), + FUNCTION(uartd), + FUNCTION(ulpi), + FUNCTION(usb), + FUNCTION(vgp1), + FUNCTION(vgp2), + FUNCTION(vgp3), + FUNCTION(vgp4), + FUNCTION(vgp5), + FUNCTION(vgp6), + FUNCTION(vi), + FUNCTION(vi_alt1), + FUNCTION(vi_alt3), + FUNCTION(vimclk2), + FUNCTION(vimclk2_alt), +}; + +#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ +#define PINGROUP_REG_A 0x3000 /* bank 1 */ + +#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) + +#define PINGROUP_BIT_Y(b) (b) +#define PINGROUP_BIT_N(b) (-1) + +#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .funcs = { \ + TEGRA_MUX_##f0, \ + TEGRA_MUX_##f1, \ + TEGRA_MUX_##f2, \ + TEGRA_MUX_##f3, \ + }, \ + .mux_reg = PINGROUP_REG(r), \ + .mux_bank = 1, \ + .mux_bit = 0, \ + .pupd_reg = PINGROUP_REG(r), \ + .pupd_bank = 1, \ + .pupd_bit = 2, \ + .tri_reg = PINGROUP_REG(r), \ + .tri_bank = 1, \ + .tri_bit = 4, \ + .einput_bit = PINGROUP_BIT_Y(5), \ + .odrain_bit = PINGROUP_BIT_##od(6), \ + .lock_bit = PINGROUP_BIT_Y(7), \ + .ioreset_bit = PINGROUP_BIT_##ior(8), \ + .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ + .drv_reg = -1, \ + } + +#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) + +#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ + drvdn_b, drvdn_w, drvup_b, drvup_w, \ + slwr_b, slwr_w, slwf_b, slwf_w, \ + drvtype) \ + { \ + .name = "drive_" #pg_name, \ + .pins = drive_##pg_name##_pins, \ + .npins = ARRAY_SIZE(drive_##pg_name##_pins), \ + .mux_reg = -1, \ + .pupd_reg = -1, \ + .tri_reg = -1, \ + .einput_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .ioreset_bit = -1, \ + .rcv_sel_bit = -1, \ + .drv_reg = DRV_PINGROUP_REG(r), \ + .drv_bank = 0, \ + .hsm_bit = hsm_b, \ + .schmitt_bit = schmitt_b, \ + .lpmd_bit = lpmd_b, \ + .drvdn_bit = drvdn_b, \ + .drvdn_width = drvdn_w, \ + .drvup_bit = drvup_b, \ + .drvup_width = drvup_w, \ + .slwr_bit = slwr_b, \ + .slwr_width = slwr_w, \ + .slwf_bit = slwf_b, \ + .slwf_width = slwf_w, \ + .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ + } + +static const struct tegra_pingroup tegra124_groups[] = { + /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */ + PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N), + PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N), + PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N), + PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N), + PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N), + PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N), + PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N), + PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N), + PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N), + PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N), + PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N), + PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N), + PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N), + PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N), + PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, 0x3038, N, N, N), + PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, 0x303c, N, N, N), + PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N), + PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N), + PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N), + PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N), + PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N), + PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N), + PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N), + PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N), + PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N), + PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N), + PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y), + PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y), + PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y), + PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N), + PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N), + PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N, N), + PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N, N), + PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, 0x3174, N, N, N), + PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, 0x3178, N, N, N), + PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, 0x317c, N, N, N), + PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, 0x3180, N, N, N), + PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N, N), + PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N, N), + PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N, N), + PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, 0x3190, N, N, N), + PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, 0x3194, N, N, N), + PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, 0x3198, N, N, N), + PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, 0x319c, N, N, N), + PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N), + PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N), + PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, 0x31a8, N, N, N), + PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, 0x31ac, N, N, N), + PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, 0x31b0, N, N, N), + PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, 0x31b4, N, N, N), + PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N), + PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N), + PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, 0x31c0, N, N, N), + PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, 0x31c4, N, N, N), + PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, 0x31c8, N, N, N), + PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, 0x31cc, N, N, N), + PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, 0x31d0, N, N, N), + PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, 0x31d4, N, N, N), + PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, 0x31d8, N, N, N), + PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, 0x31dc, N, N, N), + PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, 0x31e0, N, N, N), + PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, 0x31e4, N, N, N), + PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, 0x31e8, N, N, N), + PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, 0x31ec, N, N, N), + PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, 0x31f0, N, N, N), + PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, 0x31f4, N, N, N), + PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, 0x31f8, N, N, N), + PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, 0x31fc, N, N, N), + PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, 0x3200, N, N, N), + PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, 0x3204, N, N, N), + PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, 0x3208, N, N, N), + PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, 0x320c, N, N, N), + PINGROUP(ph0, PWM0, TRACE, GMI, DTV, 0x3210, N, N, N), + PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, 0x3214, N, N, N), + PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, 0x3218, N, N, N), + PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, 0x321c, N, N, N), + PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, 0x3220, N, N, N), + PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, 0x3224, N, N, N), + PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, 0x3228, N, N, N), + PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, 0x322c, N, N, N), + PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, 0x3230, N, N, N), + PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, 0x3234, N, N, N), + PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, 0x3238, N, N, N), + PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, 0x323c, N, N, N), + PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, 0x3240, N, N, N), + PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, 0x3244, N, N, N), + PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, 0x3248, N, N, N), + PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, 0x324c, N, N, N), + PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N), + PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N), + PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N), + PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N), + PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N), + PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N), + PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N), + PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N), + PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N), + PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, 0x3274, N, Y, N), + PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N), + PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N), + PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, 0x3284, N, N, N), + PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, 0x3288, N, N, N), + PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, 0x328c, N, N, N), + PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, 0x3290, Y, N, N), + PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, 0x3294, Y, N, N), + PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, 0x3298, N, N, N), + PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, 0x329c, N, N, N), + PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, 0x32a0, N, N, N), + PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, 0x32a4, N, N, N), + PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, 0x32a8, N, N, N), + PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, 0x32ac, N, N, N), + PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N), + PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N), + PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N), + PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N), + PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N), + PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N), + PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, 0x32c8, N, N, N), + PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32cc, N, N, N), + PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32d0, N, N, N), + PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N), + PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N), + PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N), + PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N), + PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N), + PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, 0x32e8, N, N, N), + PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, 0x32ec, N, N, N), + PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, 0x32f0, N, N, N), + PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, 0x32f4, N, N, N), + PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, 0x32f8, N, N, N), + PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, 0x32fc, N, N, N), + PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, 0x3300, N, N, N), + PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N), + PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N), + PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N), + PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, 0x3310, N, N, N), + PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, 0x3314, N, N, N), + PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, 0x3318, N, N, N), + PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N), + PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N), + PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N), + PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N), + PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N), + PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y), + PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N), + PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N), + PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, 0x3340, N, N, N), + PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N), + PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, 0x3348, N, N, N), + PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N), + PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, 0x3350, N, N, N), + PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, 0x3354, N, N, N), + PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, 0x3358, N, N, N), + PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, 0x335c, N, N, N), + PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, 0x3360, N, N, N), + PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, 0x3364, N, N, N), + PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, 0x3368, N, N, N), + PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, 0x336c, N, N, N), + PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, 0x3370, N, N, N), + PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, 0x3374, N, N, N), + PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, 0x3378, N, N, N), + PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, 0x337c, N, N, N), + PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, 0x3380, N, N, N), + PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N), + PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N), + PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N), + PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N), + PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N), + PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N), + PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N), + PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, 0x33bc, N, N, N), + PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, 0x33c0, N, N, N), + PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, 0x33c4, N, N, N), + PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, 0x33cc, N, N, N), + PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, 0x33d0, N, N, N), + PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N, N), + PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N), + PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N), + PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N), + PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N), + PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N), + PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N), + PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N), + PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N), + PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, 0x3404, N, N, N), + PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N), + PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, 0x340c, N, N, N), + PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, 0x3410, N, N, N), + PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, 0x3414, Y, N, N), + PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, 0x3418, Y, N, N), + PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, 0x3430, N, N, N), + + /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */ + DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), + DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), + DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), + DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), + DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), + DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), + DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y), + DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), + DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), + DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), + DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), + DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), +}; + +static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { + .ngpios = NUM_GPIOS, + .pins = tegra124_pins, + .npins = ARRAY_SIZE(tegra124_pins), + .functions = tegra124_functions, + .nfunctions = ARRAY_SIZE(tegra124_functions), + .groups = tegra124_groups, + .ngroups = ARRAY_SIZE(tegra124_groups), +}; + +static int tegra124_pinctrl_probe(struct platform_device *pdev) +{ + return tegra_pinctrl_probe(pdev, &tegra124_pinctrl); +} + +static struct of_device_id tegra124_pinctrl_of_match[] = { + { .compatible = "nvidia,tegra124-pinmux", }, + { }, +}; +MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match); + +static struct platform_driver tegra124_pinctrl_driver = { + .driver = { + .name = "tegra124-pinctrl", + .owner = THIS_MODULE, + .of_match_table = tegra124_pinctrl_of_match, + }, + .probe = tegra124_pinctrl_probe, + .remove = tegra_pinctrl_remove, +}; +module_platform_driver(tegra124_pinctrl_driver); + +MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>"); +MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c index fcfb7d012c5..7563ebc9c79 100644 --- a/drivers/pinctrl/pinctrl-tegra20.c +++ b/drivers/pinctrl/pinctrl-tegra20.c @@ -1894,637 +1894,12 @@ enum tegra_mux { TEGRA_MUX_XIO, }; -static const char * const ahb_clk_groups[] = { - "cdev2", -}; - -static const char * const apb_clk_groups[] = { - "cdev2", -}; - -static const char * const audio_sync_groups[] = { - "cdev1", -}; - -static const char * const crt_groups[] = { - "crtp", - "lm1", -}; - -static const char * const dap1_groups[] = { - "dap1", -}; - -static const char * const dap2_groups[] = { - "dap2", -}; - -static const char * const dap3_groups[] = { - "dap3", -}; - -static const char * const dap4_groups[] = { - "dap4", -}; - -static const char * const dap5_groups[] = { - "gme", -}; - -static const char * const displaya_groups[] = { - "lcsn", - "ld0", - "ld1", - "ld10", - "ld11", - "ld12", - "ld13", - "ld14", - "ld15", - "ld16", - "ld17", - "ld2", - "ld3", - "ld4", - "ld5", - "ld6", - "ld7", - "ld8", - "ld9", - "ldc", - "ldi", - "lhp0", - "lhp1", - "lhp2", - "lhs", - "lm0", - "lm1", - "lpp", - "lpw0", - "lpw1", - "lpw2", - "lsc0", - "lsc1", - "lsck", - "lsda", - "lsdi", - "lspi", - "lvp0", - "lvp1", - "lvs", -}; - -static const char * const displayb_groups[] = { - "lcsn", - "ld0", - "ld1", - "ld10", - "ld11", - "ld12", - "ld13", - "ld14", - "ld15", - "ld16", - "ld17", - "ld2", - "ld3", - "ld4", - "ld5", - "ld6", - "ld7", - "ld8", - "ld9", - "ldc", - "ldi", - "lhp0", - "lhp1", - "lhp2", - "lhs", - "lm0", - "lm1", - "lpp", - "lpw0", - "lpw1", - "lpw2", - "lsc0", - "lsc1", - "lsck", - "lsda", - "lsdi", - "lspi", - "lvp0", - "lvp1", - "lvs", -}; - -static const char * const emc_test0_dll_groups[] = { - "kbca", -}; - -static const char * const emc_test1_dll_groups[] = { - "kbcc", -}; - -static const char * const gmi_groups[] = { - "ata", - "atb", - "atc", - "atd", - "ate", - "dap1", - "dap2", - "dap4", - "gma", - "gmb", - "gmc", - "gmd", - "gme", - "gpu", - "irrx", - "irtx", - "pta", - "spia", - "spib", - "spic", - "spid", - "spie", - "uca", - "ucb", -}; - -static const char * const gmi_int_groups[] = { - "gmb", -}; - -static const char * const hdmi_groups[] = { - "hdint", - "lpw0", - "lpw2", - "lsc1", - "lsck", - "lsda", - "lspi", - "pta", -}; - -static const char * const i2cp_groups[] = { - "i2cp", -}; - -static const char * const i2c1_groups[] = { - "rm", - "spdi", - "spdo", - "spig", - "spih", -}; - -static const char * const i2c2_groups[] = { - "ddc", - "pta", -}; - -static const char * const i2c3_groups[] = { - "dtf", -}; - -static const char * const ide_groups[] = { - "ata", - "atb", - "atc", - "atd", - "ate", - "gmb", -}; - -static const char * const irda_groups[] = { - "uad", -}; - -static const char * const kbc_groups[] = { - "kbca", - "kbcb", - "kbcc", - "kbcd", - "kbce", - "kbcf", -}; - -static const char * const mio_groups[] = { - "kbcb", - "kbcd", - "kbcf", -}; - -static const char * const mipi_hs_groups[] = { - "uaa", - "uab", -}; - -static const char * const nand_groups[] = { - "ata", - "atb", - "atc", - "atd", - "ate", - "gmb", - "gmd", - "kbca", - "kbcb", - "kbcc", - "kbcd", - "kbce", - "kbcf", -}; - -static const char * const osc_groups[] = { - "cdev1", - "cdev2", -}; - -static const char * const owr_groups[] = { - "kbce", - "owc", - "uac", -}; - -static const char * const pcie_groups[] = { - "gpv", - "slxa", - "slxk", -}; - -static const char * const plla_out_groups[] = { - "cdev1", -}; - -static const char * const pllc_out1_groups[] = { - "csus", -}; - -static const char * const pllm_out1_groups[] = { - "cdev1", -}; - -static const char * const pllp_out2_groups[] = { - "csus", -}; - -static const char * const pllp_out3_groups[] = { - "csus", -}; - -static const char * const pllp_out4_groups[] = { - "cdev2", -}; - -static const char * const pwm_groups[] = { - "gpu", - "sdb", - "sdc", - "sdd", - "ucb", -}; - -static const char * const pwr_intr_groups[] = { - "pmc", -}; - -static const char * const pwr_on_groups[] = { - "pmc", -}; - -static const char * const rsvd1_groups[] = { - "dta", - "dtb", - "dtc", - "dtd", - "dte", - "gmd", - "gme", -}; - -static const char * const rsvd2_groups[] = { - "crtp", - "dap1", - "dap3", - "dap4", - "ddc", - "dtb", - "dtc", - "dte", - "dtf", - "gpu7", - "gpv", - "hdint", - "i2cp", - "owc", - "rm", - "sdio1", - "spdi", - "spdo", - "uac", - "uca", - "uda", -}; - -static const char * const rsvd3_groups[] = { - "crtp", - "dap2", - "dap3", - "ddc", - "gpu7", - "gpv", - "hdint", - "i2cp", - "ld17", - "ldc", - "ldi", - "lhp0", - "lhp1", - "lhp2", - "lm1", - "lpp", - "lpw1", - "lvp0", - "lvp1", - "owc", - "pmc", - "rm", - "uac", -}; - -static const char * const rsvd4_groups[] = { - "ata", - "ate", - "crtp", - "dap3", - "dap4", - "ddc", - "dta", - "dtc", - "dtd", - "dtf", - "gpu", - "gpu7", - "gpv", - "hdint", - "i2cp", - "kbce", - "lcsn", - "ld0", - "ld1", - "ld2", - "ld3", - "ld4", - "ld5", - "ld6", - "ld7", - "ld8", - "ld9", - "ld10", - "ld11", - "ld12", - "ld13", - "ld14", - "ld15", - "ld16", - "ld17", - "ldc", - "ldi", - "lhp0", - "lhp1", - "lhp2", - "lhs", - "lm0", - "lpp", - "lpw1", - "lsc0", - "lsdi", - "lvp0", - "lvp1", - "lvs", - "owc", - "pmc", - "pta", - "rm", - "spif", - "uac", - "uca", - "ucb", -}; - -static const char * const rtck_groups[] = { - "gpu7", -}; - -static const char * const sdio1_groups[] = { - "sdio1", -}; - -static const char * const sdio2_groups[] = { - "dap1", - "dta", - "dtd", - "kbca", - "kbcb", - "kbcd", - "spdi", - "spdo", -}; - -static const char * const sdio3_groups[] = { - "sdb", - "sdc", - "sdd", - "slxa", - "slxc", - "slxd", - "slxk", -}; - -static const char * const sdio4_groups[] = { - "atb", - "atc", - "atd", - "gma", - "gme", -}; - -static const char * const sflash_groups[] = { - "gmc", - "gmd", -}; - -static const char * const spdif_groups[] = { - "slxc", - "slxd", - "spdi", - "spdo", - "uad", -}; - -static const char * const spi1_groups[] = { - "dtb", - "dte", - "spia", - "spib", - "spic", - "spid", - "spie", - "spif", - "uda", -}; - -static const char * const spi2_groups[] = { - "sdb", - "slxa", - "slxc", - "slxd", - "slxk", - "spia", - "spib", - "spic", - "spid", - "spie", - "spif", - "spig", - "spih", - "uab", -}; - -static const char * const spi2_alt_groups[] = { - "spid", - "spie", - "spig", - "spih", -}; - -static const char * const spi3_groups[] = { - "gma", - "lcsn", - "lm0", - "lpw0", - "lpw2", - "lsc1", - "lsck", - "lsda", - "lsdi", - "sdc", - "sdd", - "spia", - "spib", - "spic", - "spif", - "spig", - "spih", - "uaa", -}; - -static const char * const spi4_groups[] = { - "gmc", - "irrx", - "irtx", - "slxa", - "slxc", - "slxd", - "slxk", - "uad", -}; - -static const char * const trace_groups[] = { - "kbcc", - "kbcf", -}; - -static const char * const twc_groups[] = { - "dap2", - "sdc", -}; - -static const char * const uarta_groups[] = { - "gpu", - "irrx", - "irtx", - "sdb", - "sdd", - "sdio1", - "uaa", - "uab", - "uad", -}; - -static const char * const uartb_groups[] = { - "irrx", - "irtx", -}; - -static const char * const uartc_groups[] = { - "uca", - "ucb", -}; - -static const char * const uartd_groups[] = { - "gmc", - "uda", -}; - -static const char * const uarte_groups[] = { - "gma", - "sdio1", -}; - -static const char * const ulpi_groups[] = { - "uaa", - "uab", - "uda", -}; - -static const char * const vi_groups[] = { - "dta", - "dtb", - "dtc", - "dtd", - "dte", - "dtf", -}; - -static const char * const vi_sensor_clk_groups[] = { - "csus", -}; - -static const char * const xio_groups[] = { - "ld0", - "ld1", - "ld10", - "ld11", - "ld12", - "ld13", - "ld14", - "ld15", - "ld16", - "ld2", - "ld3", - "ld4", - "ld5", - "ld6", - "ld7", - "ld8", - "ld9", - "lhs", - "lsc0", - "lspi", - "lvs", -}; - #define FUNCTION(fname) \ { \ .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ } -static const struct tegra_function tegra20_functions[] = { +static struct tegra_function tegra20_functions[] = { FUNCTION(ahb_clk), FUNCTION(apb_clk), FUNCTION(audio_sync), @@ -2598,7 +1973,7 @@ static const struct tegra_function tegra20_functions[] = { #define PINGROUP_REG_A 0x868 /* Pin group with mux control, and typically tri-state and pull-up/down too */ -#define MUX_PG(pg_name, f0, f1, f2, f3, f_safe, \ +#define MUX_PG(pg_name, f0, f1, f2, f3, \ tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \ { \ .name = #pg_name, \ @@ -2610,7 +1985,6 @@ static const struct tegra_function tegra20_functions[] = { TEGRA_MUX_ ## f2, \ TEGRA_MUX_ ## f3, \ }, \ - .func_safe = TEGRA_MUX_ ## f_safe, \ .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \ .mux_bank = 1, \ .mux_bit = mux_b, \ @@ -2620,13 +1994,12 @@ static const struct tegra_function tegra20_functions[] = { .tri_reg = ((tri_r) - TRISTATE_REG_A), \ .tri_bank = 0, \ .tri_bit = tri_b, \ - .einput_reg = -1, \ - .odrain_reg = -1, \ - .lock_reg = -1, \ - .ioreset_reg = -1, \ - .rcv_sel_reg = -1, \ + .einput_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .ioreset_bit = -1, \ + .rcv_sel_bit = -1, \ .drv_reg = -1, \ - .drvtype_reg = -1, \ } /* Pin groups with only pull up and pull down control */ @@ -2639,14 +2012,7 @@ static const struct tegra_function tegra20_functions[] = { .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ .pupd_bank = 2, \ .pupd_bit = pupd_b, \ - .tri_reg = -1, \ - .einput_reg = -1, \ - .odrain_reg = -1, \ - .lock_reg = -1, \ - .ioreset_reg = -1, \ - .rcv_sel_reg = -1, \ .drv_reg = -1, \ - .drvtype_reg = -1, \ } /* Pin groups for drive strength registers (configurable version) */ @@ -2660,11 +2026,6 @@ static const struct tegra_function tegra20_functions[] = { .mux_reg = -1, \ .pupd_reg = -1, \ .tri_reg = -1, \ - .einput_reg = -1, \ - .odrain_reg = -1, \ - .lock_reg = -1, \ - .ioreset_reg = -1, \ - .rcv_sel_reg = -1, \ .drv_reg = ((r) - PINGROUP_REG_A), \ .drv_bank = 3, \ .hsm_bit = hsm_b, \ @@ -2678,7 +2039,7 @@ static const struct tegra_function tegra20_functions[] = { .slwr_width = slwr_w, \ .slwf_bit = slwf_b, \ .slwf_width = slwf_w, \ - .drvtype_reg = -1, \ + .drvtype_bit = -1, \ } /* Pin groups for drive strength registers (simple version) */ @@ -2686,114 +2047,114 @@ static const struct tegra_function tegra20_functions[] = { DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2) static const struct tegra_pingroup tegra20_groups[] = { - /* name, f0, f1, f2, f3, f_safe, tri r/b, mux r/b, pupd r/b */ - MUX_PG(ata, IDE, NAND, GMI, RSVD4, IDE, 0x14, 0, 0x80, 24, 0xa0, 0), - MUX_PG(atb, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xa0, 2), - MUX_PG(atc, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xa0, 4), - MUX_PG(atd, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xa0, 6), - MUX_PG(ate, IDE, NAND, GMI, RSVD4, IDE, 0x18, 25, 0x80, 12, 0xa0, 8), - MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xa8, 0), - MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xa8, 2), - MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, RSVD2, 0x20, 14, 0x98, 20, 0xa4, 24), - MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xac, 24), - MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xa0, 10), - MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, DAP2, 0x14, 8, 0x88, 22, 0xa0, 12), - MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, DAP3, 0x14, 9, 0x88, 24, 0xa0, 14), - MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, DAP4, 0x14, 10, 0x88, 26, 0xa0, 16), - MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28), - MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18), - MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xa0, 20), - MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, RSVD1, 0x14, 13, 0x84, 26, 0xa0, 22), - MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, RSVD1, 0x14, 14, 0x84, 28, 0xa0, 24), - MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xa0, 26), - MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28), - MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xb0, 20), - MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xb0, 22), - MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xb0, 24), - MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xb0, 26), - MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8c, 0, 0xa8, 24), - MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20), - MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, RTCK, 0x20, 11, 0x98, 28, 0xa4, 6), - MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, PCIE, 0x14, 17, 0x8c, 2, 0xa0, 30), - MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, HDMI, 0x1c, 23, 0x84, 4, -1, -1), - MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2), - MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xa8, 22), - MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xa8, 20), - MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xa4, 8), - MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xa4, 10), - MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xa4, 12), - MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xa4, 14), - MUX_PG(kbce, KBC, NAND, OWR, RSVD4, KBC, 0x14, 26, 0x80, 28, 0xb0, 2), - MUX_PG(kbcf, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xb0, 0), - MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, RSVD4, 0x1c, 31, 0x90, 12, -1, -1), - MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 0, 0x94, 0, -1, -1), - MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 1, 0x94, 2, -1, -1), - MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 2, 0x94, 4, -1, -1), - MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 3, 0x94, 6, -1, -1), - MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 4, 0x94, 8, -1, -1), - MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 5, 0x94, 10, -1, -1), - MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 6, 0x94, 12, -1, -1), - MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 7, 0x94, 14, -1, -1), - MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 8, 0x94, 16, -1, -1), - MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 9, 0x94, 18, -1, -1), - MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 10, 0x94, 20, -1, -1), - MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 11, 0x94, 22, -1, -1), - MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 12, 0x94, 24, -1, -1), - MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 13, 0x94, 26, -1, -1), - MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 14, 0x94, 28, -1, -1), - MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 15, 0x94, 30, -1, -1), - MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 16, 0x98, 0, -1, -1), - MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 17, 0x98, 2, -1, -1), - MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 30, 0x90, 14, -1, -1), - MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 6, 0x98, 16, -1, -1), - MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 18, 0x98, 10, -1, -1), - MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 19, 0x98, 4, -1, -1), - MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 20, 0x98, 6, -1, -1), - MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x20, 7, 0x90, 22, -1, -1), - MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, RSVD4, 0x1c, 24, 0x90, 26, -1, -1), - MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, RSVD3, 0x1c, 25, 0x90, 28, -1, -1), - MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 8, 0x98, 14, -1, -1), - MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, -1, -1), - MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 4, 0x90, 2, -1, -1), - MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, -1, -1), - MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 27, 0x90, 18, -1, -1), - MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1c, 28, 0x90, 20, -1, -1), - MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1c, 29, 0x90, 16, -1, -1), - MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, -1, -1), - MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, DISPLAYA, 0x20, 2, 0x90, 6, -1, -1), - MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, -1, -1), - MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 21, 0x90, 30, -1, -1), - MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 22, 0x98, 8, -1, -1), - MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 26, 0x90, 24, -1, -1), - MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, OWR, 0x14, 31, 0x84, 8, 0xb0, 30), - MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, PWR_ON, 0x14, 23, 0x98, 18, -1, -1), - MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4), - MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0), - MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8c, 10, -1, -1), - MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8c, 12, 0xac, 28), - MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8c, 14, 0xac, 30), - MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xb0, 18), - MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xa4, 22), - MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xa4, 26), - MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xa4, 28), - MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xa4, 30), - MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, RSVD2, 0x18, 8, 0x8c, 8, 0xa4, 16), - MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, RSVD2, 0x18, 9, 0x8c, 6, 0xa4, 18), - MUX_PG(spia, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4), - MUX_PG(spib, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6), - MUX_PG(spic, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8), - MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10), - MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12), - MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14), - MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, SPI2_ALT, 0x18, 16, 0x8c, 18, 0xa8, 16), - MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, SPI2_ALT, 0x18, 17, 0x8c, 16, 0xa8, 18), - MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xac, 0), - MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xac, 2), - MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4), - MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xac, 6), - MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8), - MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10), - MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xb0, 16), + /* name, f0, f1, f2, f3, tri r/b, mux r/b, pupd r/b */ + MUX_PG(ata, IDE, NAND, GMI, RSVD4, 0x14, 0, 0x80, 24, 0xa0, 0), + MUX_PG(atb, IDE, NAND, GMI, SDIO4, 0x14, 1, 0x80, 16, 0xa0, 2), + MUX_PG(atc, IDE, NAND, GMI, SDIO4, 0x14, 2, 0x80, 22, 0xa0, 4), + MUX_PG(atd, IDE, NAND, GMI, SDIO4, 0x14, 3, 0x80, 20, 0xa0, 6), + MUX_PG(ate, IDE, NAND, GMI, RSVD4, 0x18, 25, 0x80, 12, 0xa0, 8), + MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0), + MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2), + MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, 0x20, 14, 0x98, 20, 0xa4, 24), + MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6, 0x88, 6, 0xac, 24), + MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, 0x14, 7, 0x88, 20, 0xa0, 10), + MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, 0x14, 8, 0x88, 22, 0xa0, 12), + MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, 0x14, 9, 0x88, 24, 0xa0, 14), + MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, 0x14, 10, 0x88, 26, 0xa0, 16), + MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28), + MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18), + MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, 0x14, 12, 0x84, 22, 0xa0, 20), + MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, 0x14, 13, 0x84, 26, 0xa0, 22), + MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24), + MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, 0x14, 15, 0x84, 30, 0xa0, 26), + MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28), + MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, 0x14, 28, 0x84, 0, 0xb0, 20), + MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, 0x18, 29, 0x88, 28, 0xb0, 22), + MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, 0x14, 29, 0x84, 2, 0xb0, 24), + MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, 0x18, 30, 0x88, 30, 0xb0, 26), + MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, 0x18, 0, 0x8c, 0, 0xa8, 24), + MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20), + MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, 0x20, 11, 0x98, 28, 0xa4, 6), + MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, 0x14, 17, 0x8c, 2, 0xa0, 30), + MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, 0x1c, 23, 0x84, 4, -1, -1), + MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2), + MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, 0x14, 20, 0x88, 18, 0xa8, 22), + MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, 0x14, 19, 0x88, 16, 0xa8, 20), + MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, 0x14, 22, 0x88, 10, 0xa4, 8), + MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, 0x14, 21, 0x88, 12, 0xa4, 10), + MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, 0x18, 26, 0x88, 14, 0xa4, 12), + MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, 0x20, 10, 0x98, 26, 0xa4, 14), + MUX_PG(kbce, KBC, NAND, OWR, RSVD4, 0x14, 26, 0x80, 28, 0xb0, 2), + MUX_PG(kbcf, KBC, NAND, TRACE, MIO, 0x14, 27, 0x80, 26, 0xb0, 0), + MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 31, 0x90, 12, -1, -1), + MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 0, 0x94, 0, -1, -1), + MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 1, 0x94, 2, -1, -1), + MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 2, 0x94, 4, -1, -1), + MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 3, 0x94, 6, -1, -1), + MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 4, 0x94, 8, -1, -1), + MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 5, 0x94, 10, -1, -1), + MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 6, 0x94, 12, -1, -1), + MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 7, 0x94, 14, -1, -1), + MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 8, 0x94, 16, -1, -1), + MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 9, 0x94, 18, -1, -1), + MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 10, 0x94, 20, -1, -1), + MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 11, 0x94, 22, -1, -1), + MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 12, 0x94, 24, -1, -1), + MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 13, 0x94, 26, -1, -1), + MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 14, 0x94, 28, -1, -1), + MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 15, 0x94, 30, -1, -1), + MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 16, 0x98, 0, -1, -1), + MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 17, 0x98, 2, -1, -1), + MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 30, 0x90, 14, -1, -1), + MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 6, 0x98, 16, -1, -1), + MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 18, 0x98, 10, -1, -1), + MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 19, 0x98, 4, -1, -1), + MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 20, 0x98, 6, -1, -1), + MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x20, 7, 0x90, 22, -1, -1), + MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 24, 0x90, 26, -1, -1), + MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, 0x1c, 25, 0x90, 28, -1, -1), + MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 8, 0x98, 14, -1, -1), + MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 3, 0x90, 0, -1, -1), + MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 4, 0x90, 2, -1, -1), + MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 5, 0x90, 4, -1, -1), + MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 27, 0x90, 18, -1, -1), + MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 28, 0x90, 20, -1, -1), + MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 29, 0x90, 16, -1, -1), + MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 1, 0x90, 8, -1, -1), + MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x20, 2, 0x90, 6, -1, -1), + MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, 0x20, 0, 0x90, 10, -1, -1), + MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 21, 0x90, 30, -1, -1), + MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 22, 0x98, 8, -1, -1), + MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 26, 0x90, 24, -1, -1), + MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, 0x14, 31, 0x84, 8, 0xb0, 30), + MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, 0x14, 23, 0x98, 18, -1, -1), + MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4), + MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0), + MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1), + MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28), + MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30), + MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, 0x14, 30, 0x80, 30, 0xb0, 18), + MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, 0x18, 3, 0x84, 6, 0xa4, 22), + MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, 0x18, 5, 0x84, 10, 0xa4, 26), + MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, 0x18, 6, 0x84, 12, 0xa4, 28), + MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, 0x18, 7, 0x84, 14, 0xa4, 30), + MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 8, 0x8c, 8, 0xa4, 16), + MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 9, 0x8c, 6, 0xa4, 18), + MUX_PG(spia, SPI1, SPI2, SPI3, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4), + MUX_PG(spib, SPI1, SPI2, SPI3, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6), + MUX_PG(spic, SPI1, SPI2, SPI3, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8), + MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10), + MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12), + MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14), + MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 16, 0x8c, 18, 0xa8, 16), + MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 17, 0x8c, 16, 0xa8, 18), + MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, 0x18, 18, 0x80, 0, 0xac, 0), + MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, 0x18, 19, 0x80, 2, 0xac, 2), + MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4), + MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, 0x18, 21, 0x80, 6, 0xac, 6), + MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8), + MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10), + MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, 0x20, 13, 0x80, 8, 0xb0, 16), /* pg_name, pupd_r/b */ PULL_PG(ck32, 0xb0, 14), PULL_PG(ddrc, 0xac, 26), @@ -2881,18 +2242,7 @@ static struct platform_driver tegra20_pinctrl_driver = { .probe = tegra20_pinctrl_probe, .remove = tegra_pinctrl_remove, }; - -static int __init tegra20_pinctrl_init(void) -{ - return platform_driver_register(&tegra20_pinctrl_driver); -} -arch_initcall(tegra20_pinctrl_init); - -static void __exit tegra20_pinctrl_exit(void) -{ - platform_driver_unregister(&tegra20_pinctrl_driver); -} -module_exit(tegra20_pinctrl_exit); +module_platform_driver(tegra20_pinctrl_driver); MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver"); diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c index 2300deba25b..fe2d2cf78ad 100644 --- a/drivers/pinctrl/pinctrl-tegra30.c +++ b/drivers/pinctrl/pinctrl-tegra30.c @@ -25,7 +25,7 @@ * Most pins affected by the pinmux can also be GPIOs. Define these first. * These must match how the GPIO driver names/numbers its pins. */ -#define _GPIO(offset) (offset) +#define _GPIO(offset) (offset) #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0) #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1) @@ -277,8 +277,8 @@ #define TEGRA_PIN_PEE7 _GPIO(247) /* All non-GPIO pins follow */ -#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1) -#define _PIN(offset) (NUM_GPIOS + (offset)) +#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1) +#define _PIN(offset) (NUM_GPIOS + (offset)) /* Non-GPIO pins */ #define TEGRA_PIN_CLK_32K_IN _PIN(0) @@ -2015,1253 +2015,13 @@ enum tegra_mux { TEGRA_MUX_VI_ALT2, TEGRA_MUX_VI_ALT3, }; -static const char * const blink_groups[] = { - "clk_32k_out_pa0", -}; - -static const char * const cec_groups[] = { - "hdmi_cec_pee3", - "owr", -}; - -static const char * const clk_12m_out_groups[] = { - "pv3", -}; - -static const char * const clk_32k_in_groups[] = { - "clk_32k_in", -}; - -static const char * const core_pwr_req_groups[] = { - "core_pwr_req", -}; - -static const char * const cpu_pwr_req_groups[] = { - "cpu_pwr_req", -}; - -static const char * const crt_groups[] = { - "crt_hsync_pv6", - "crt_vsync_pv7", -}; - -static const char * const dap_groups[] = { - "clk1_req_pee2", - "clk2_req_pcc5", -}; - -static const char * const ddr_groups[] = { - "vi_d0_pt4", - "vi_d1_pd5", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_hsync_pd7", - "vi_vsync_pd6", -}; - -static const char * const dev3_groups[] = { - "clk3_req_pee1", -}; - -static const char * const displaya_groups[] = { - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_fs_pp0", - "dap3_sclk_pp3", - "pbb3", - "pbb4", - "pbb5", - "pbb6", - "lcd_cs0_n_pn4", - "lcd_cs1_n_pw0", - "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d2_pe2", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_dc0_pn6", - "lcd_dc1_pd2", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_m1_pw1", - "lcd_pclk_pb3", - "lcd_pwr0_pb2", - "lcd_pwr1_pc1", - "lcd_pwr2_pc6", - "lcd_sck_pz4", - "lcd_sdin_pz2", - "lcd_sdout_pn5", - "lcd_vsync_pj4", - "lcd_wr_n_pz3", -}; - -static const char * const displayb_groups[] = { - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_fs_pp0", - "dap3_sclk_pp3", - "pbb3", - "pbb4", - "pbb5", - "pbb6", - "lcd_cs0_n_pn4", - "lcd_cs1_n_pw0", - "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d2_pe2", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_dc0_pn6", - "lcd_dc1_pd2", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_m1_pw1", - "lcd_pclk_pb3", - "lcd_pwr0_pb2", - "lcd_pwr1_pc1", - "lcd_pwr2_pc6", - "lcd_sck_pz4", - "lcd_sdin_pz2", - "lcd_sdout_pn5", - "lcd_vsync_pj4", - "lcd_wr_n_pz3", -}; - -static const char * const dtv_groups[] = { - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", -}; - -static const char * const extperiph1_groups[] = { - "clk1_out_pw4", -}; - -static const char * const extperiph2_groups[] = { - "clk2_out_pw5", -}; - -static const char * const extperiph3_groups[] = { - "clk3_out_pee0", -}; - -static const char * const gmi_groups[] = { - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3", - "dap2_din_pa4", - "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7", - "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6", - "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7", - "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs2_n_pk3", - "gmi_cs3_n_pk4", - "gmi_cs4_n_pk2", - "gmi_cs6_n_pi3", - "gmi_cs7_n_pi6", - "gmi_dqs_pi2", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_rst_n_pi4", - "gmi_wait_pi7", - "gmi_wp_n_pc7", - "gmi_wr_n_pi0", - "pu0", - "pu1", - "pu2", - "pu3", - "pu4", - "pu5", - "pu6", - "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7", - "spi1_cs0_n_px6", - "spi1_mosi_px4", - "spi1_sck_px5", - "spi2_cs0_n_px3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2", - "uart2_cts_n_pj5", - "uart2_rts_n_pj6", - "uart3_cts_n_pa1", - "uart3_rts_n_pc0", - "uart3_rxd_pw7", - "uart3_txd_pw6", -}; - -static const char * const gmi_alt_groups[] = { - "gmi_a16_pj7", - "gmi_cs3_n_pk4", - "gmi_cs7_n_pi6", - "gmi_wp_n_pc7", -}; - -static const char * const hda_groups[] = { - "clk1_req_pee2", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3", - "dap2_din_pa4", - "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3", - "pex_l0_clkreq_n_pdd2", - "pex_l0_prsnt_n_pdd0", - "pex_l0_rst_n_pdd1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_prsnt_n_pdd4", - "pex_l1_rst_n_pdd5", - "pex_l2_clkreq_n_pcc7", - "pex_l2_prsnt_n_pdd7", - "pex_l2_rst_n_pcc6", - "pex_wake_n_pdd3", - "spdif_in_pk6", -}; - -static const char * const hdcp_groups[] = { - "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6", - "lcd_pwr0_pb2", - "lcd_pwr2_pc6", - "lcd_sck_pz4", - "lcd_sdout_pn5", - "lcd_wr_n_pz3", -}; - -static const char * const hdmi_groups[] = { - "hdmi_int_pn7", -}; - -static const char * const hsi_groups[] = { - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0", -}; - -static const char * const i2c1_groups[] = { - "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5", - "spdif_in_pk6", - "spdif_out_pk5", - "spi2_cs1_n_pw2", - "spi2_cs2_n_pw3", -}; - -static const char * const i2c2_groups[] = { - "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6", -}; - -static const char * const i2c3_groups[] = { - "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2", - "sdmmc4_cmd_pt7", - "sdmmc4_dat4_paa4", -}; - -static const char * const i2c4_groups[] = { - "ddc_scl_pv4", - "ddc_sda_pv5", -}; - -static const char * const i2cpwr_groups[] = { - "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7", -}; - -static const char * const i2s0_groups[] = { - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3", -}; - -static const char * const i2s1_groups[] = { - "dap2_din_pa4", - "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3", -}; - -static const char * const i2s2_groups[] = { - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_fs_pp0", - "dap3_sclk_pp3", -}; - -static const char * const i2s3_groups[] = { - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7", -}; - -static const char * const i2s4_groups[] = { - "pbb0", - "pbb7", - "pcc1", - "pcc2", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7", -}; - -static const char * const invalid_groups[] = { - "kb_row3_pr3", - "sdmmc4_clk_pcc4", -}; - -static const char * const kbc_groups[] = { - "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_col5_pq5", - "kb_col6_pq6", - "kb_col7_pq7", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row10_ps2", - "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7", - "kb_row2_pr2", - "kb_row3_pr3", - "kb_row4_pr4", - "kb_row5_pr5", - "kb_row6_pr6", - "kb_row7_pr7", - "kb_row8_ps0", - "kb_row9_ps1", -}; - -static const char * const mio_groups[] = { - "kb_col6_pq6", - "kb_col7_pq7", - "kb_row10_ps2", - "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7", - "kb_row6_pr6", - "kb_row7_pr7", - "kb_row8_ps0", - "kb_row9_ps1", -}; - -static const char * const nand_groups[] = { - "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs2_n_pk3", - "gmi_cs3_n_pk4", - "gmi_cs4_n_pk2", - "gmi_cs6_n_pi3", - "gmi_cs7_n_pi6", - "gmi_dqs_pi2", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_rst_n_pi4", - "gmi_wait_pi7", - "gmi_wp_n_pc7", - "gmi_wr_n_pi0", - "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_col5_pq5", - "kb_col6_pq6", - "kb_col7_pq7", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row10_ps2", - "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7", - "kb_row2_pr2", - "kb_row3_pr3", - "kb_row4_pr4", - "kb_row5_pr5", - "kb_row6_pr6", - "kb_row7_pr7", - "kb_row8_ps0", - "kb_row9_ps1", - "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", -}; - -static const char * const nand_alt_groups[] = { - "gmi_cs6_n_pi3", - "gmi_cs7_n_pi6", - "gmi_rst_n_pi4", -}; - -static const char * const owr_groups[] = { - "pu0", - "pv2", - "kb_row5_pr5", - "owr", -}; - -static const char * const pcie_groups[] = { - "pex_l0_clkreq_n_pdd2", - "pex_l0_prsnt_n_pdd0", - "pex_l0_rst_n_pdd1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_prsnt_n_pdd4", - "pex_l1_rst_n_pdd5", - "pex_l2_clkreq_n_pcc7", - "pex_l2_prsnt_n_pdd7", - "pex_l2_rst_n_pcc6", - "pex_wake_n_pdd3", -}; - -static const char * const pwm0_groups[] = { - "gmi_ad8_ph0", - "pu3", - "sdmmc3_dat3_pb4", - "sdmmc3_dat5_pd0", - "uart3_rts_n_pc0", -}; - -static const char * const pwm1_groups[] = { - "gmi_ad9_ph1", - "pu4", - "sdmmc3_dat2_pb5", - "sdmmc3_dat4_pd1", -}; - -static const char * const pwm2_groups[] = { - "gmi_ad10_ph2", - "pu5", - "sdmmc3_clk_pa6", -}; - -static const char * const pwm3_groups[] = { - "gmi_ad11_ph3", - "pu6", - "sdmmc3_cmd_pa7", -}; - -static const char * const pwr_int_n_groups[] = { - "pwr_int_n", -}; - -static const char * const rsvd1_groups[] = { - "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs2_n_pk3", - "gmi_cs3_n_pk4", - "gmi_cs4_n_pk2", - "gmi_dqs_pi2", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_wait_pi7", - "gmi_wp_n_pc7", - "gmi_wr_n_pi0", - "pu1", - "pu2", - "pv0", - "pv1", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "vi_pclk_pt0", -}; - -static const char * const rsvd2_groups[] = { - "clk1_out_pw4", - "clk2_out_pw5", - "clk2_req_pcc5", - "clk3_out_pee0", - "clk3_req_pee1", - "clk_32k_in", - "clk_32k_out_pa0", - "core_pwr_req", - "cpu_pwr_req", - "crt_hsync_pv6", - "crt_vsync_pv7", - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_fs_pp0", - "dap3_sclk_pp3", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7", - "ddc_scl_pv4", - "ddc_sda_pv5", - "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5", - "pbb0", - "pbb7", - "pcc1", - "pcc2", - "pv0", - "pv1", - "pv2", - "pv3", - "hdmi_cec_pee3", - "hdmi_int_pn7", - "jtag_rtck_pu7", - "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7", - "pwr_int_n", - "sdmmc1_clk_pz0", - "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc4_rst_n_pcc3", - "spdif_out_pk5", - "sys_clk_req_pz5", - "uart3_cts_n_pa1", - "uart3_rxd_pw7", - "uart3_txd_pw6", - "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3", - "vi_d0_pt4", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_hsync_pd7", - "vi_vsync_pd6", -}; - -static const char * const rsvd3_groups[] = { - "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2", - "clk1_out_pw4", - "clk1_req_pee2", - "clk2_out_pw5", - "clk2_req_pcc5", - "clk3_out_pee0", - "clk3_req_pee1", - "clk_32k_in", - "clk_32k_out_pa0", - "core_pwr_req", - "cpu_pwr_req", - "crt_hsync_pv6", - "crt_vsync_pv7", - "dap2_din_pa4", - "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3", - "ddc_scl_pv4", - "ddc_sda_pv5", - "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5", - "pbb0", - "pbb7", - "pcc1", - "pcc2", - "pv0", - "pv1", - "pv2", - "pv3", - "hdmi_cec_pee3", - "hdmi_int_pn7", - "jtag_rtck_pu7", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3", - "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d2_pe2", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_dc0_pn6", - "lcd_dc1_pd2", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_m1_pw1", - "lcd_pclk_pb3", - "lcd_pwr1_pc1", - "lcd_vsync_pj4", - "owr", - "pex_l0_clkreq_n_pdd2", - "pex_l0_prsnt_n_pdd0", - "pex_l0_rst_n_pdd1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_prsnt_n_pdd4", - "pex_l1_rst_n_pdd5", - "pex_l2_clkreq_n_pcc7", - "pex_l2_prsnt_n_pdd7", - "pex_l2_rst_n_pcc6", - "pex_wake_n_pdd3", - "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7", - "pwr_int_n", - "sdmmc1_clk_pz0", - "sdmmc1_cmd_pz1", - "sdmmc4_rst_n_pcc3", - "sys_clk_req_pz5", -}; - -static const char * const rsvd4_groups[] = { - "clk1_out_pw4", - "clk1_req_pee2", - "clk2_out_pw5", - "clk2_req_pcc5", - "clk3_out_pee0", - "clk3_req_pee1", - "clk_32k_in", - "clk_32k_out_pa0", - "core_pwr_req", - "cpu_pwr_req", - "crt_hsync_pv6", - "crt_vsync_pv7", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7", - "ddc_scl_pv4", - "ddc_sda_pv5", - "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5", - "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6", - "gmi_a19_pk7", - "gmi_ad0_pg0", - "gmi_ad1_pg1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs2_n_pk3", - "gmi_cs4_n_pk2", - "gmi_dqs_pi2", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_rst_n_pi4", - "gmi_wait_pi7", - "gmi_wr_n_pi0", - "pcc2", - "pu0", - "pu1", - "pu2", - "pu3", - "pu4", - "pu5", - "pu6", - "pv0", - "pv1", - "pv2", - "pv3", - "hdmi_cec_pee3", - "hdmi_int_pn7", - "jtag_rtck_pu7", - "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_col5_pq5", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row4_pr4", - "lcd_cs0_n_pn4", - "lcd_cs1_n_pw0", - "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d2_pe2", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_dc0_pn6", - "lcd_dc1_pd2", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_m1_pw1", - "lcd_pclk_pb3", - "lcd_pwr1_pc1", - "lcd_sdin_pz2", - "lcd_vsync_pj4", - "owr", - "pex_l0_clkreq_n_pdd2", - "pex_l0_prsnt_n_pdd0", - "pex_l0_rst_n_pdd1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_prsnt_n_pdd4", - "pex_l1_rst_n_pdd5", - "pex_l2_clkreq_n_pcc7", - "pex_l2_prsnt_n_pdd7", - "pex_l2_rst_n_pcc6", - "pex_wake_n_pdd3", - "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7", - "pwr_int_n", - "spi1_miso_px7", - "sys_clk_req_pz5", - "uart3_cts_n_pa1", - "uart3_rts_n_pc0", - "uart3_rxd_pw7", - "uart3_txd_pw6", - "vi_d0_pt4", - "vi_d1_pd5", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_hsync_pd7", - "vi_pclk_pt0", - "vi_vsync_pd6", -}; - -static const char * const rtck_groups[] = { - "jtag_rtck_pu7", -}; - -static const char * const sata_groups[] = { - "gmi_cs6_n_pi3", -}; - -static const char * const sdmmc1_groups[] = { - "sdmmc1_clk_pz0", - "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4", -}; - -static const char * const sdmmc2_groups[] = { - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3", - "kb_row10_ps2", - "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7", - "kb_row6_pr6", - "kb_row7_pr7", - "kb_row8_ps0", - "kb_row9_ps1", - "spdif_in_pk6", - "spdif_out_pk5", - "vi_d1_pd5", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_pclk_pt0", -}; - -static const char * const sdmmc3_groups[] = { - "sdmmc3_clk_pa6", - "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4", -}; - -static const char * const sdmmc4_groups[] = { - "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2", - "cam_mclk_pcc0", - "pbb0", - "pbb3", - "pbb4", - "pbb5", - "pbb6", - "pbb7", - "pcc1", - "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7", - "sdmmc4_rst_n_pcc3", -}; - -static const char * const spdif_groups[] = { - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4", - "spdif_in_pk6", - "spdif_out_pk5", - "uart2_rxd_pc3", - "uart2_txd_pc2", -}; - -static const char * const spi1_groups[] = { - "spi1_cs0_n_px6", - "spi1_miso_px7", - "spi1_mosi_px4", - "spi1_sck_px5", - "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3", -}; - -static const char * const spi2_groups[] = { - "sdmmc3_cmd_pa7", - "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4", - "spi1_cs0_n_px6", - "spi1_mosi_px4", - "spi1_sck_px5", - "spi2_cs0_n_px3", - "spi2_cs1_n_pw2", - "spi2_cs2_n_pw3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0", -}; - -static const char * const spi2_alt_groups[] = { - "spi1_cs0_n_px6", - "spi1_miso_px7", - "spi1_mosi_px4", - "spi1_sck_px5", - "spi2_cs1_n_pw2", - "spi2_cs2_n_pw3", -}; - -static const char * const spi3_groups[] = { - "sdmmc3_clk_pa6", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "spi1_miso_px7", - "spi2_cs0_n_px3", - "spi2_cs1_n_pw2", - "spi2_cs2_n_pw3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", -}; - -static const char * const spi4_groups[] = { - "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7", - "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4", - "uart2_cts_n_pj5", - "uart2_rts_n_pj6", - "uart2_rxd_pc3", - "uart2_txd_pc2", -}; - -static const char * const spi5_groups[] = { - "lcd_cs0_n_pn4", - "lcd_cs1_n_pw0", - "lcd_pwr0_pb2", - "lcd_pwr2_pc6", - "lcd_sck_pz4", - "lcd_sdin_pz2", - "lcd_sdout_pn5", - "lcd_wr_n_pz3", -}; - -static const char * const spi6_groups[] = { - "spi2_cs0_n_px3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2", -}; - -static const char * const sysclk_groups[] = { - "sys_clk_req_pz5", -}; - -static const char * const test_groups[] = { - "kb_col0_pq0", - "kb_col1_pq1", -}; - -static const char * const trace_groups[] = { - "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_col5_pq5", - "kb_col6_pq6", - "kb_col7_pq7", - "kb_row4_pr4", - "kb_row5_pr5", -}; - -static const char * const uarta_groups[] = { - "pu0", - "pu1", - "pu2", - "pu3", - "pu4", - "pu5", - "pu6", - "sdmmc1_clk_pz0", - "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4", - "sdmmc3_clk_pa6", - "sdmmc3_cmd_pa7", - "uart2_cts_n_pj5", - "uart2_rts_n_pj6", - "uart2_rxd_pc3", - "uart2_txd_pc2", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0", -}; - -static const char * const uartb_groups[] = { - "uart2_cts_n_pj5", - "uart2_rts_n_pj6", - "uart2_rxd_pc3", - "uart2_txd_pc2", -}; - -static const char * const uartc_groups[] = { - "uart3_cts_n_pa1", - "uart3_rts_n_pc0", - "uart3_rxd_pw7", - "uart3_txd_pw6", -}; - -static const char * const uartd_groups[] = { - "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7", - "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3", -}; - -static const char * const uarte_groups[] = { - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", -}; - -static const char * const ulpi_groups[] = { - "ulpi_clk_py0", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3", -}; - -static const char * const vgp1_groups[] = { - "cam_i2c_scl_pbb1", -}; - -static const char * const vgp2_groups[] = { - "cam_i2c_sda_pbb2", -}; - -static const char * const vgp3_groups[] = { - "pbb3", - "sdmmc4_dat5_paa5", -}; - -static const char * const vgp4_groups[] = { - "pbb4", - "sdmmc4_dat6_paa6", -}; - -static const char * const vgp5_groups[] = { - "pbb5", - "sdmmc4_dat7_paa7", -}; - -static const char * const vgp6_groups[] = { - "pbb6", - "sdmmc4_rst_n_pcc3", -}; - -static const char * const vi_groups[] = { - "cam_mclk_pcc0", - "vi_d0_pt4", - "vi_d1_pd5", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_hsync_pd7", - "vi_mclk_pt1", - "vi_pclk_pt0", - "vi_vsync_pd6", -}; - -static const char * const vi_alt1_groups[] = { - "cam_mclk_pcc0", - "vi_mclk_pt1", -}; - -static const char * const vi_alt2_groups[] = { - "vi_mclk_pt1", -}; - -static const char * const vi_alt3_groups[] = { - "cam_mclk_pcc0", - "vi_mclk_pt1", -}; #define FUNCTION(fname) \ { \ .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ } -static const struct tegra_function tegra30_functions[] = { +static struct tegra_function tegra30_functions[] = { FUNCTION(blink), FUNCTION(cec), FUNCTION(clk_12m_out), @@ -3345,50 +2105,44 @@ static const struct tegra_function tegra30_functions[] = { FUNCTION(vi_alt3), }; -#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ -#define PINGROUP_REG_A 0x3000 /* bank 1 */ +#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ +#define PINGROUP_REG_A 0x3000 /* bank 1 */ -#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) -#define PINGROUP_REG_N(r) -1 +#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) -#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \ +#define PINGROUP_BIT_Y(b) (b) +#define PINGROUP_BIT_N(b) (-1) + +#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \ { \ .name = #pg_name, \ .pins = pg_name##_pins, \ .npins = ARRAY_SIZE(pg_name##_pins), \ .funcs = { \ - TEGRA_MUX_ ## f0, \ - TEGRA_MUX_ ## f1, \ - TEGRA_MUX_ ## f2, \ - TEGRA_MUX_ ## f3, \ + TEGRA_MUX_##f0, \ + TEGRA_MUX_##f1, \ + TEGRA_MUX_##f2, \ + TEGRA_MUX_##f3, \ }, \ - .func_safe = TEGRA_MUX_ ## f_safe, \ - .mux_reg = PINGROUP_REG_Y(r), \ + .mux_reg = PINGROUP_REG(r), \ .mux_bank = 1, \ .mux_bit = 0, \ - .pupd_reg = PINGROUP_REG_Y(r), \ + .pupd_reg = PINGROUP_REG(r), \ .pupd_bank = 1, \ .pupd_bit = 2, \ - .tri_reg = PINGROUP_REG_Y(r), \ + .tri_reg = PINGROUP_REG(r), \ .tri_bank = 1, \ .tri_bit = 4, \ - .einput_reg = PINGROUP_REG_Y(r), \ - .einput_bank = 1, \ - .einput_bit = 5, \ - .odrain_reg = PINGROUP_REG_##od(r), \ - .odrain_bank = 1, \ - .odrain_bit = 6, \ - .lock_reg = PINGROUP_REG_Y(r), \ - .lock_bank = 1, \ - .lock_bit = 7, \ - .ioreset_reg = PINGROUP_REG_##ior(r), \ - .ioreset_bank = 1, \ - .ioreset_bit = 8, \ - .rcv_sel_reg = -1, \ + .einput_bit = PINGROUP_BIT_Y(5), \ + .odrain_bit = PINGROUP_BIT_##od(6), \ + .lock_bit = PINGROUP_BIT_Y(7), \ + .ioreset_bit = PINGROUP_BIT_##ior(8), \ + .rcv_sel_bit = -1, \ .drv_reg = -1, \ - .drvtype_reg = -1, \ } +#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) + #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ drvdn_b, drvdn_w, drvup_b, drvup_w, \ slwr_b, slwr_w, slwf_b, slwf_w) \ @@ -3399,12 +2153,12 @@ static const struct tegra_function tegra30_functions[] = { .mux_reg = -1, \ .pupd_reg = -1, \ .tri_reg = -1, \ - .einput_reg = -1, \ - .odrain_reg = -1, \ - .lock_reg = -1, \ - .ioreset_reg = -1, \ - .rcv_sel_reg = -1, \ - .drv_reg = ((r) - DRV_PINGROUP_REG_A), \ + .einput_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .ioreset_bit = -1, \ + .rcv_sel_bit = -1, \ + .drv_reg = DRV_PINGROUP_REG(r), \ .drv_bank = 0, \ .hsm_bit = hsm_b, \ .schmitt_bit = schmitt_b, \ @@ -3417,261 +2171,260 @@ static const struct tegra_function tegra30_functions[] = { .slwr_width = slwr_w, \ .slwf_bit = slwf_b, \ .slwf_width = slwf_w, \ - .drvtype_reg = -1, \ + .drvtype_bit = -1, \ } static const struct tegra_pingroup tegra30_groups[] = { - /* pg_name, f0, f1, f2, f3, safe, r, od, ior */ - /* FIXME: Fill in correct data in safe column */ - PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, RSVD4, 0x331c, N, N), - PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x317c, N, N), - PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3358, N, N), - PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3364, N, N), - PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, GMI, RSVD3, 0x335c, N, N), - PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3360, N, N), - PINGROUP(sdmmc3_clk_pa6, UARTA, PWM2, SDMMC3, SPI3, SPI3, 0x3390, N, N), - PINGROUP(sdmmc3_cmd_pa7, UARTA, PWM3, SDMMC3, SPI2, SPI2, 0x3394, N, N), - PINGROUP(gmi_a17_pb0, UARTD, SPI4, GMI, DTV, DTV, 0x3234, N, N), - PINGROUP(gmi_a18_pb1, UARTD, SPI4, GMI, DTV, DTV, 0x3238, N, N), - PINGROUP(lcd_pwr0_pb2, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x3090, N, N), - PINGROUP(lcd_pclk_pb3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3094, N, N), - PINGROUP(sdmmc3_dat3_pb4, RSVD1, PWM0, SDMMC3, SPI3, RSVD1, 0x33a4, N, N), - PINGROUP(sdmmc3_dat2_pb5, RSVD1, PWM1, SDMMC3, SPI3, RSVD1, 0x33a0, N, N), - PINGROUP(sdmmc3_dat1_pb6, RSVD1, RSVD2, SDMMC3, SPI3, RSVD2, 0x339c, N, N), - PINGROUP(sdmmc3_dat0_pb7, RSVD1, RSVD2, SDMMC3, SPI3, RSVD2, 0x3398, N, N), - PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, GMI, RSVD4, RSVD4, 0x3180, N, N), - PINGROUP(lcd_pwr1_pc1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3070, N, N), - PINGROUP(uart2_txd_pc2, UARTB, SPDIF, UARTA, SPI4, SPI4, 0x3168, N, N), - PINGROUP(uart2_rxd_pc3, UARTB, SPDIF, UARTA, SPI4, SPI4, 0x3164, N, N), - PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a4, Y, N), - PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a0, Y, N), - PINGROUP(lcd_pwr2_pc6, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x3074, N, N), - PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, RSVD1, 0x31c0, N, N), - PINGROUP(sdmmc3_dat5_pd0, PWM0, SPI4, SDMMC3, SPI2, SPI2, 0x33ac, N, N), - PINGROUP(sdmmc3_dat4_pd1, PWM1, SPI4, SDMMC3, SPI2, SPI2, 0x33a8, N, N), - PINGROUP(lcd_dc1_pd2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x310c, N, N), - PINGROUP(sdmmc3_dat6_pd3, SPDIF, SPI4, SDMMC3, SPI2, SPI2, 0x33b0, N, N), - PINGROUP(sdmmc3_dat7_pd4, SPDIF, SPI4, SDMMC3, SPI2, SPI2, 0x33b4, N, N), - PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3128, N, Y), - PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, RSVD4, 0x315c, N, Y), - PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, RSVD4, 0x3160, N, Y), - PINGROUP(lcd_d0_pe0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30a4, N, N), - PINGROUP(lcd_d1_pe1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30a8, N, N), - PINGROUP(lcd_d2_pe2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30ac, N, N), - PINGROUP(lcd_d3_pe3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30b0, N, N), - PINGROUP(lcd_d4_pe4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30b4, N, N), - PINGROUP(lcd_d5_pe5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30b8, N, N), - PINGROUP(lcd_d6_pe6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30bc, N, N), - PINGROUP(lcd_d7_pe7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30c0, N, N), - PINGROUP(lcd_d8_pf0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30c4, N, N), - PINGROUP(lcd_d9_pf1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30c8, N, N), - PINGROUP(lcd_d10_pf2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30cc, N, N), - PINGROUP(lcd_d11_pf3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30d0, N, N), - PINGROUP(lcd_d12_pf4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30d4, N, N), - PINGROUP(lcd_d13_pf5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30d8, N, N), - PINGROUP(lcd_d14_pf6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30dc, N, N), - PINGROUP(lcd_d15_pf7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30e0, N, N), - PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f0, N, N), - PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f4, N, N), - PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f8, N, N), - PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31fc, N, N), - PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3200, N, N), - PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3204, N, N), - PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3208, N, N), - PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x320c, N, N), - PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, RSVD4, 0x3210, N, N), - PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, RSVD4, RSVD4, 0x3214, N, N), - PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, RSVD4, RSVD4, 0x3218, N, N), - PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, RSVD4, RSVD4, 0x321c, N, N), - PINGROUP(gmi_ad12_ph4, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3220, N, N), - PINGROUP(gmi_ad13_ph5, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3224, N, N), - PINGROUP(gmi_ad14_ph6, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3228, N, N), - PINGROUP(gmi_ad15_ph7, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x322c, N, N), - PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3240, N, N), - PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3244, N, N), - PINGROUP(gmi_dqs_pi2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3248, N, N), - PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SATA, SATA, 0x31e8, N, N), - PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, RSVD4, 0x324c, N, N), - PINGROUP(gmi_iordy_pi5, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31c4, N, N), - PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, GMI_ALT, GMI_ALT, 0x31ec, N, N), - PINGROUP(gmi_wait_pi7, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31c8, N, N), - PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, DTV, RSVD1, 0x31d4, N, N), - PINGROUP(lcd_de_pj1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3098, N, N), - PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, DTV, RSVD1, 0x31d8, N, N), - PINGROUP(lcd_hsync_pj3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x309c, N, N), - PINGROUP(lcd_vsync_pj4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30a0, N, N), - PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, SPI4, 0x3170, N, N), - PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, SPI4, 0x316c, N, N), - PINGROUP(gmi_a16_pj7, UARTD, SPI4, GMI, GMI_ALT, GMI_ALT, 0x3230, N, N), - PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31cc, N, N), - PINGROUP(gmi_clk_pk1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31d0, N, N), - PINGROUP(gmi_cs4_n_pk2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31e4, N, N), - PINGROUP(gmi_cs2_n_pk3, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31dc, N, N), - PINGROUP(gmi_cs3_n_pk4, RSVD1, NAND, GMI, GMI_ALT, RSVD1, 0x31e0, N, N), - PINGROUP(spdif_out_pk5, SPDIF, RSVD2, I2C1, SDMMC2, RSVD2, 0x3354, N, N), - PINGROUP(spdif_in_pk6, SPDIF, HDA, I2C1, SDMMC2, SDMMC2, 0x3350, N, N), - PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, RSVD4, RSVD4, 0x323c, N, N), - PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x312c, N, Y), - PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3130, N, Y), - PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3134, N, Y), - PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3138, N, Y), - PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x313c, N, Y), - PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3140, N, Y), - PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3144, N, Y), - PINGROUP(vi_d9_pl7, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3148, N, Y), - PINGROUP(lcd_d16_pm0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30e4, N, N), - PINGROUP(lcd_d17_pm1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30e8, N, N), - PINGROUP(lcd_d18_pm2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30ec, N, N), - PINGROUP(lcd_d19_pm3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30f0, N, N), - PINGROUP(lcd_d20_pm4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30f4, N, N), - PINGROUP(lcd_d21_pm5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30f8, N, N), - PINGROUP(lcd_d22_pm6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30fc, N, N), - PINGROUP(lcd_d23_pm7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3100, N, N), - PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, SDMMC2, SDMMC2, 0x3338, N, N), - PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, SDMMC2, SDMMC2, 0x333c, N, N), - PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SDMMC2, SDMMC2, 0x3340, N, N), - PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, SDMMC2, SDMMC2, 0x3344, N, N), - PINGROUP(lcd_cs0_n_pn4, DISPLAYA, DISPLAYB, SPI5, RSVD4, RSVD4, 0x3084, N, N), - PINGROUP(lcd_sdout_pn5, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x307c, N, N), - PINGROUP(lcd_dc0_pn6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3088, N, N), - PINGROUP(hdmi_int_pn7, HDMI, RSVD2, RSVD3, RSVD4, RSVD4, 0x3110, N, N), - PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, ULPI, 0x301c, N, N), - PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N), - PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N), - PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N), - PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, ULPI, 0x300c, N, N), - PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, ULPI, 0x3010, N, N), - PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, ULPI, 0x3014, N, N), - PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, ULPI, 0x3018, N, N), - PINGROUP(dap3_fs_pp0, I2S2, RSVD2, DISPLAYA, DISPLAYB, RSVD2, 0x3030, N, N), - PINGROUP(dap3_din_pp1, I2S2, RSVD2, DISPLAYA, DISPLAYB, RSVD2, 0x3034, N, N), - PINGROUP(dap3_dout_pp2, I2S2, RSVD2, DISPLAYA, DISPLAYB, RSVD2, 0x3038, N, N), - PINGROUP(dap3_sclk_pp3, I2S2, RSVD2, DISPLAYA, DISPLAYB, RSVD2, 0x303c, N, N), - PINGROUP(dap4_fs_pp4, I2S3, RSVD2, GMI, RSVD4, RSVD4, 0x31a8, N, N), - PINGROUP(dap4_din_pp5, I2S3, RSVD2, GMI, RSVD4, RSVD4, 0x31ac, N, N), - PINGROUP(dap4_dout_pp6, I2S3, RSVD2, GMI, RSVD4, RSVD4, 0x31b0, N, N), - PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, GMI, RSVD4, RSVD4, 0x31b4, N, N), - PINGROUP(kb_col0_pq0, KBC, NAND, TRACE, TEST, TEST, 0x32fc, N, N), - PINGROUP(kb_col1_pq1, KBC, NAND, TRACE, TEST, TEST, 0x3300, N, N), - PINGROUP(kb_col2_pq2, KBC, NAND, TRACE, RSVD4, RSVD4, 0x3304, N, N), - PINGROUP(kb_col3_pq3, KBC, NAND, TRACE, RSVD4, RSVD4, 0x3308, N, N), - PINGROUP(kb_col4_pq4, KBC, NAND, TRACE, RSVD4, RSVD4, 0x330c, N, N), - PINGROUP(kb_col5_pq5, KBC, NAND, TRACE, RSVD4, RSVD4, 0x3310, N, N), - PINGROUP(kb_col6_pq6, KBC, NAND, TRACE, MIO, MIO, 0x3314, N, N), - PINGROUP(kb_col7_pq7, KBC, NAND, TRACE, MIO, MIO, 0x3318, N, N), - PINGROUP(kb_row0_pr0, KBC, NAND, RSVD3, RSVD4, RSVD4, 0x32bc, N, N), - PINGROUP(kb_row1_pr1, KBC, NAND, RSVD3, RSVD4, RSVD4, 0x32c0, N, N), - PINGROUP(kb_row2_pr2, KBC, NAND, RSVD3, RSVD4, RSVD4, 0x32c4, N, N), - PINGROUP(kb_row3_pr3, KBC, NAND, RSVD3, INVALID, RSVD3, 0x32c8, N, N), - PINGROUP(kb_row4_pr4, KBC, NAND, TRACE, RSVD4, RSVD4, 0x32cc, N, N), - PINGROUP(kb_row5_pr5, KBC, NAND, TRACE, OWR, OWR, 0x32d0, N, N), - PINGROUP(kb_row6_pr6, KBC, NAND, SDMMC2, MIO, MIO, 0x32d4, N, N), - PINGROUP(kb_row7_pr7, KBC, NAND, SDMMC2, MIO, MIO, 0x32d8, N, N), - PINGROUP(kb_row8_ps0, KBC, NAND, SDMMC2, MIO, MIO, 0x32dc, N, N), - PINGROUP(kb_row9_ps1, KBC, NAND, SDMMC2, MIO, MIO, 0x32e0, N, N), - PINGROUP(kb_row10_ps2, KBC, NAND, SDMMC2, MIO, MIO, 0x32e4, N, N), - PINGROUP(kb_row11_ps3, KBC, NAND, SDMMC2, MIO, MIO, 0x32e8, N, N), - PINGROUP(kb_row12_ps4, KBC, NAND, SDMMC2, MIO, MIO, 0x32ec, N, N), - PINGROUP(kb_row13_ps5, KBC, NAND, SDMMC2, MIO, MIO, 0x32f0, N, N), - PINGROUP(kb_row14_ps6, KBC, NAND, SDMMC2, MIO, MIO, 0x32f4, N, N), - PINGROUP(kb_row15_ps7, KBC, NAND, SDMMC2, MIO, MIO, 0x32f8, N, N), - PINGROUP(vi_pclk_pt0, RSVD1, SDMMC2, VI, RSVD4, RSVD4, 0x3154, N, Y), - PINGROUP(vi_mclk_pt1, VI, VI_ALT1, VI_ALT2, VI_ALT3, VI_ALT3, 0x3158, N, Y), - PINGROUP(vi_d10_pt2, DDR, RSVD2, VI, RSVD4, RSVD4, 0x314c, N, Y), - PINGROUP(vi_d11_pt3, DDR, RSVD2, VI, RSVD4, RSVD4, 0x3150, N, Y), - PINGROUP(vi_d0_pt4, DDR, RSVD2, VI, RSVD4, RSVD4, 0x3124, N, Y), - PINGROUP(gen2_i2c_scl_pt5, I2C2, HDCP, GMI, RSVD4, RSVD4, 0x3250, Y, N), - PINGROUP(gen2_i2c_sda_pt6, I2C2, HDCP, GMI, RSVD4, RSVD4, 0x3254, Y, N), - PINGROUP(sdmmc4_cmd_pt7, I2C3, NAND, GMI, SDMMC4, SDMMC4, 0x325c, N, Y), - PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, RSVD4, 0x3184, N, N), - PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x3188, N, N), - PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x318c, N, N), - PINGROUP(pu3, PWM0, UARTA, GMI, RSVD4, RSVD4, 0x3190, N, N), - PINGROUP(pu4, PWM1, UARTA, GMI, RSVD4, RSVD4, 0x3194, N, N), - PINGROUP(pu5, PWM2, UARTA, GMI, RSVD4, RSVD4, 0x3198, N, N), - PINGROUP(pu6, PWM3, UARTA, GMI, RSVD4, RSVD4, 0x319c, N, N), - PINGROUP(jtag_rtck_pu7, RTCK, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b0, N, N), - PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3040, N, N), - PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3044, N, N), - PINGROUP(pv2, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x3060, N, N), - PINGROUP(pv3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4, RSVD4, 0x3064, N, N), - PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3114, N, N), - PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3118, N, N), - PINGROUP(crt_hsync_pv6, CRT, RSVD2, RSVD3, RSVD4, RSVD4, 0x311c, N, N), - PINGROUP(crt_vsync_pv7, CRT, RSVD2, RSVD3, RSVD4, RSVD4, 0x3120, N, N), - PINGROUP(lcd_cs1_n_pw0, DISPLAYA, DISPLAYB, SPI5, RSVD4, RSVD4, 0x3104, N, N), - PINGROUP(lcd_m1_pw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3108, N, N), - PINGROUP(spi2_cs1_n_pw2, SPI3, SPI2, SPI2_ALT, I2C1, I2C1, 0x3388, N, N), - PINGROUP(spi2_cs2_n_pw3, SPI3, SPI2, SPI2_ALT, I2C1, I2C1, 0x338c, N, N), - PINGROUP(clk1_out_pw4, EXTPERIPH1, RSVD2, RSVD3, RSVD4, RSVD4, 0x334c, N, N), - PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, RSVD4, 0x3068, N, N), - PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x3174, N, N), - PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x3178, N, N), - PINGROUP(spi2_mosi_px0, SPI6, SPI2, SPI3, GMI, GMI, 0x3368, N, N), - PINGROUP(spi2_miso_px1, SPI6, SPI2, SPI3, GMI, GMI, 0x336c, N, N), - PINGROUP(spi2_sck_px2, SPI6, SPI2, SPI3, GMI, GMI, 0x3374, N, N), - PINGROUP(spi2_cs0_n_px3, SPI6, SPI2, SPI3, GMI, GMI, 0x3370, N, N), - PINGROUP(spi1_mosi_px4, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x3378, N, N), - PINGROUP(spi1_sck_px5, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x337c, N, N), - PINGROUP(spi1_cs0_n_px6, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x3380, N, N), - PINGROUP(spi1_miso_px7, SPI3, SPI1, SPI2_ALT, RSVD4, RSVD4, 0x3384, N, N), - PINGROUP(ulpi_clk_py0, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x3020, N, N), - PINGROUP(ulpi_dir_py1, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x3024, N, N), - PINGROUP(ulpi_nxt_py2, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x3028, N, N), - PINGROUP(ulpi_stp_py3, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x302c, N, N), - PINGROUP(sdmmc1_dat3_py4, SDMMC1, RSVD2, UARTE, UARTA, RSVD2, 0x3050, N, N), - PINGROUP(sdmmc1_dat2_py5, SDMMC1, RSVD2, UARTE, UARTA, RSVD2, 0x3054, N, N), - PINGROUP(sdmmc1_dat1_py6, SDMMC1, RSVD2, UARTE, UARTA, RSVD2, 0x3058, N, N), - PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, UARTE, UARTA, RSVD2, 0x305c, N, N), - PINGROUP(sdmmc1_clk_pz0, SDMMC1, RSVD2, RSVD3, UARTA, RSVD3, 0x3048, N, N), - PINGROUP(sdmmc1_cmd_pz1, SDMMC1, RSVD2, RSVD3, UARTA, RSVD3, 0x304c, N, N), - PINGROUP(lcd_sdin_pz2, DISPLAYA, DISPLAYB, SPI5, RSVD4, RSVD4, 0x3078, N, N), - PINGROUP(lcd_wr_n_pz3, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x3080, N, N), - PINGROUP(lcd_sck_pz4, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x308c, N, N), - PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, RSVD4, 0x3320, N, N), - PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b4, Y, N), - PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b8, Y, N), - PINGROUP(sdmmc4_dat0_paa0, UARTE, SPI3, GMI, SDMMC4, SDMMC4, 0x3260, N, Y), - PINGROUP(sdmmc4_dat1_paa1, UARTE, SPI3, GMI, SDMMC4, SDMMC4, 0x3264, N, Y), - PINGROUP(sdmmc4_dat2_paa2, UARTE, SPI3, GMI, SDMMC4, SDMMC4, 0x3268, N, Y), - PINGROUP(sdmmc4_dat3_paa3, UARTE, SPI3, GMI, SDMMC4, SDMMC4, 0x326c, N, Y), - PINGROUP(sdmmc4_dat4_paa4, I2C3, I2S4, GMI, SDMMC4, SDMMC4, 0x3270, N, Y), - PINGROUP(sdmmc4_dat5_paa5, VGP3, I2S4, GMI, SDMMC4, SDMMC4, 0x3274, N, Y), - PINGROUP(sdmmc4_dat6_paa6, VGP4, I2S4, GMI, SDMMC4, SDMMC4, 0x3278, N, Y), - PINGROUP(sdmmc4_dat7_paa7, VGP5, I2S4, GMI, SDMMC4, SDMMC4, 0x327c, N, Y), - PINGROUP(pbb0, I2S4, RSVD2, RSVD3, SDMMC4, RSVD3, 0x328c, N, N), - PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC4, RSVD3, 0x3290, Y, N), - PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC4, RSVD3, 0x3294, Y, N), - PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC4, SDMMC4, 0x3298, N, N), - PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC4, SDMMC4, 0x329c, N, N), - PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, SDMMC4, SDMMC4, 0x32a0, N, N), - PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, SDMMC4, SDMMC4, 0x32a4, N, N), - PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC4, RSVD3, 0x32a8, N, N), - PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC4, SDMMC4, 0x3284, N, N), - PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC4, RSVD3, 0x3288, N, N), - PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32ac, N, N), - PINGROUP(sdmmc4_rst_n_pcc3, VGP6, RSVD2, RSVD3, SDMMC4, RSVD3, 0x3280, N, Y), - PINGROUP(sdmmc4_clk_pcc4, INVALID, NAND, GMI, SDMMC4, SDMMC4, 0x3258, N, Y), - PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, RSVD4, 0x306c, N, N), - PINGROUP(pex_l2_rst_n_pcc6, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33d8, N, N), - PINGROUP(pex_l2_clkreq_n_pcc7, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33dc, N, N), - PINGROUP(pex_l0_prsnt_n_pdd0, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33b8, N, N), - PINGROUP(pex_l0_rst_n_pdd1, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33bc, N, N), - PINGROUP(pex_l0_clkreq_n_pdd2, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33c0, N, N), - PINGROUP(pex_wake_n_pdd3, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33c4, N, N), - PINGROUP(pex_l1_prsnt_n_pdd4, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33c8, N, N), - PINGROUP(pex_l1_rst_n_pdd5, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33cc, N, N), - PINGROUP(pex_l1_clkreq_n_pdd6, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33d0, N, N), - PINGROUP(pex_l2_prsnt_n_pdd7, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33d4, N, N), - PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b8, N, N), - PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31bc, N, N), - PINGROUP(clk1_req_pee2, DAP, HDA, RSVD3, RSVD4, RSVD4, 0x3348, N, N), - PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, RSVD4, 0x33e0, Y, N), - PINGROUP(clk_32k_in, CLK_32K_IN, RSVD2, RSVD3, RSVD4, RSVD4, 0x3330, N, N), - PINGROUP(core_pwr_req, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4, RSVD4, 0x3324, N, N), - PINGROUP(cpu_pwr_req, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4, RSVD4, 0x3328, N, N), - PINGROUP(owr, OWR, CEC, RSVD3, RSVD4, RSVD4, 0x3334, N, N), - PINGROUP(pwr_int_n, PWR_INT_N, RSVD2, RSVD3, RSVD4, RSVD4, 0x332c, N, N), + /* pg_name, f0, f1, f2, f3, r, od, ior */ + PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, 0x331c, N, N), + PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, 0x317c, N, N), + PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, 0x3358, N, N), + PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, GMI, 0x3364, N, N), + PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, GMI, 0x335c, N, N), + PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, GMI, 0x3360, N, N), + PINGROUP(sdmmc3_clk_pa6, UARTA, PWM2, SDMMC3, SPI3, 0x3390, N, N), + PINGROUP(sdmmc3_cmd_pa7, UARTA, PWM3, SDMMC3, SPI2, 0x3394, N, N), + PINGROUP(gmi_a17_pb0, UARTD, SPI4, GMI, DTV, 0x3234, N, N), + PINGROUP(gmi_a18_pb1, UARTD, SPI4, GMI, DTV, 0x3238, N, N), + PINGROUP(lcd_pwr0_pb2, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3090, N, N), + PINGROUP(lcd_pclk_pb3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3094, N, N), + PINGROUP(sdmmc3_dat3_pb4, RSVD1, PWM0, SDMMC3, SPI3, 0x33a4, N, N), + PINGROUP(sdmmc3_dat2_pb5, RSVD1, PWM1, SDMMC3, SPI3, 0x33a0, N, N), + PINGROUP(sdmmc3_dat1_pb6, RSVD1, RSVD2, SDMMC3, SPI3, 0x339c, N, N), + PINGROUP(sdmmc3_dat0_pb7, RSVD1, RSVD2, SDMMC3, SPI3, 0x3398, N, N), + PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, GMI, RSVD4, 0x3180, N, N), + PINGROUP(lcd_pwr1_pc1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3070, N, N), + PINGROUP(uart2_txd_pc2, UARTB, SPDIF, UARTA, SPI4, 0x3168, N, N), + PINGROUP(uart2_rxd_pc3, UARTB, SPDIF, UARTA, SPI4, 0x3164, N, N), + PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N), + PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N), + PINGROUP(lcd_pwr2_pc6, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3074, N, N), + PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N), + PINGROUP(sdmmc3_dat5_pd0, PWM0, SPI4, SDMMC3, SPI2, 0x33ac, N, N), + PINGROUP(sdmmc3_dat4_pd1, PWM1, SPI4, SDMMC3, SPI2, 0x33a8, N, N), + PINGROUP(lcd_dc1_pd2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x310c, N, N), + PINGROUP(sdmmc3_dat6_pd3, SPDIF, SPI4, SDMMC3, SPI2, 0x33b0, N, N), + PINGROUP(sdmmc3_dat7_pd4, SPDIF, SPI4, SDMMC3, SPI2, 0x33b4, N, N), + PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, Y), + PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, Y), + PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, Y), + PINGROUP(lcd_d0_pe0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a4, N, N), + PINGROUP(lcd_d1_pe1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a8, N, N), + PINGROUP(lcd_d2_pe2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ac, N, N), + PINGROUP(lcd_d3_pe3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b0, N, N), + PINGROUP(lcd_d4_pe4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b4, N, N), + PINGROUP(lcd_d5_pe5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b8, N, N), + PINGROUP(lcd_d6_pe6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30bc, N, N), + PINGROUP(lcd_d7_pe7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c0, N, N), + PINGROUP(lcd_d8_pf0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c4, N, N), + PINGROUP(lcd_d9_pf1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c8, N, N), + PINGROUP(lcd_d10_pf2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30cc, N, N), + PINGROUP(lcd_d11_pf3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d0, N, N), + PINGROUP(lcd_d12_pf4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d4, N, N), + PINGROUP(lcd_d13_pf5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d8, N, N), + PINGROUP(lcd_d14_pf6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30dc, N, N), + PINGROUP(lcd_d15_pf7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e0, N, N), + PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N), + PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N), + PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N), + PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N), + PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N), + PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, N), + PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, N), + PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, N), + PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, N), + PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, RSVD4, 0x3214, N, N), + PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, RSVD4, 0x3218, N, N), + PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, RSVD4, 0x321c, N, N), + PINGROUP(gmi_ad12_ph4, RSVD1, NAND, GMI, RSVD4, 0x3220, N, N), + PINGROUP(gmi_ad13_ph5, RSVD1, NAND, GMI, RSVD4, 0x3224, N, N), + PINGROUP(gmi_ad14_ph6, RSVD1, NAND, GMI, RSVD4, 0x3228, N, N), + PINGROUP(gmi_ad15_ph7, RSVD1, NAND, GMI, RSVD4, 0x322c, N, N), + PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, RSVD4, 0x3240, N, N), + PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, RSVD4, 0x3244, N, N), + PINGROUP(gmi_dqs_pi2, RSVD1, NAND, GMI, RSVD4, 0x3248, N, N), + PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SATA, 0x31e8, N, N), + PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N), + PINGROUP(gmi_iordy_pi5, RSVD1, NAND, GMI, RSVD4, 0x31c4, N, N), + PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, GMI_ALT, 0x31ec, N, N), + PINGROUP(gmi_wait_pi7, RSVD1, NAND, GMI, RSVD4, 0x31c8, N, N), + PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, DTV, 0x31d4, N, N), + PINGROUP(lcd_de_pj1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3098, N, N), + PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, DTV, 0x31d8, N, N), + PINGROUP(lcd_hsync_pj3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x309c, N, N), + PINGROUP(lcd_vsync_pj4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a0, N, N), + PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N), + PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N), + PINGROUP(gmi_a16_pj7, UARTD, SPI4, GMI, GMI_ALT, 0x3230, N, N), + PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, RSVD4, 0x31cc, N, N), + PINGROUP(gmi_clk_pk1, RSVD1, NAND, GMI, RSVD4, 0x31d0, N, N), + PINGROUP(gmi_cs4_n_pk2, RSVD1, NAND, GMI, RSVD4, 0x31e4, N, N), + PINGROUP(gmi_cs2_n_pk3, RSVD1, NAND, GMI, RSVD4, 0x31dc, N, N), + PINGROUP(gmi_cs3_n_pk4, RSVD1, NAND, GMI, GMI_ALT, 0x31e0, N, N), + PINGROUP(spdif_out_pk5, SPDIF, RSVD2, I2C1, SDMMC2, 0x3354, N, N), + PINGROUP(spdif_in_pk6, SPDIF, HDA, I2C1, SDMMC2, 0x3350, N, N), + PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, RSVD4, 0x323c, N, N), + PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, Y), + PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, Y), + PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, Y), + PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, Y), + PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, Y), + PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, Y), + PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, Y), + PINGROUP(vi_d9_pl7, DDR, SDMMC2, VI, RSVD4, 0x3148, N, Y), + PINGROUP(lcd_d16_pm0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e4, N, N), + PINGROUP(lcd_d17_pm1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e8, N, N), + PINGROUP(lcd_d18_pm2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ec, N, N), + PINGROUP(lcd_d19_pm3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f0, N, N), + PINGROUP(lcd_d20_pm4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f4, N, N), + PINGROUP(lcd_d21_pm5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f8, N, N), + PINGROUP(lcd_d22_pm6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30fc, N, N), + PINGROUP(lcd_d23_pm7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3100, N, N), + PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, SDMMC2, 0x3338, N, N), + PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, SDMMC2, 0x333c, N, N), + PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SDMMC2, 0x3340, N, N), + PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, SDMMC2, 0x3344, N, N), + PINGROUP(lcd_cs0_n_pn4, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3084, N, N), + PINGROUP(lcd_sdout_pn5, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x307c, N, N), + PINGROUP(lcd_dc0_pn6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3088, N, N), + PINGROUP(hdmi_int_pn7, HDMI, RSVD2, RSVD3, RSVD4, 0x3110, N, N), + PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N), + PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N), + PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N), + PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N), + PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N), + PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N), + PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N), + PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N), + PINGROUP(dap3_fs_pp0, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3030, N, N), + PINGROUP(dap3_din_pp1, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3034, N, N), + PINGROUP(dap3_dout_pp2, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3038, N, N), + PINGROUP(dap3_sclk_pp3, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x303c, N, N), + PINGROUP(dap4_fs_pp4, I2S3, RSVD2, GMI, RSVD4, 0x31a8, N, N), + PINGROUP(dap4_din_pp5, I2S3, RSVD2, GMI, RSVD4, 0x31ac, N, N), + PINGROUP(dap4_dout_pp6, I2S3, RSVD2, GMI, RSVD4, 0x31b0, N, N), + PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, GMI, RSVD4, 0x31b4, N, N), + PINGROUP(kb_col0_pq0, KBC, NAND, TRACE, TEST, 0x32fc, N, N), + PINGROUP(kb_col1_pq1, KBC, NAND, TRACE, TEST, 0x3300, N, N), + PINGROUP(kb_col2_pq2, KBC, NAND, TRACE, RSVD4, 0x3304, N, N), + PINGROUP(kb_col3_pq3, KBC, NAND, TRACE, RSVD4, 0x3308, N, N), + PINGROUP(kb_col4_pq4, KBC, NAND, TRACE, RSVD4, 0x330c, N, N), + PINGROUP(kb_col5_pq5, KBC, NAND, TRACE, RSVD4, 0x3310, N, N), + PINGROUP(kb_col6_pq6, KBC, NAND, TRACE, MIO, 0x3314, N, N), + PINGROUP(kb_col7_pq7, KBC, NAND, TRACE, MIO, 0x3318, N, N), + PINGROUP(kb_row0_pr0, KBC, NAND, RSVD3, RSVD4, 0x32bc, N, N), + PINGROUP(kb_row1_pr1, KBC, NAND, RSVD3, RSVD4, 0x32c0, N, N), + PINGROUP(kb_row2_pr2, KBC, NAND, RSVD3, RSVD4, 0x32c4, N, N), + PINGROUP(kb_row3_pr3, KBC, NAND, RSVD3, INVALID, 0x32c8, N, N), + PINGROUP(kb_row4_pr4, KBC, NAND, TRACE, RSVD4, 0x32cc, N, N), + PINGROUP(kb_row5_pr5, KBC, NAND, TRACE, OWR, 0x32d0, N, N), + PINGROUP(kb_row6_pr6, KBC, NAND, SDMMC2, MIO, 0x32d4, N, N), + PINGROUP(kb_row7_pr7, KBC, NAND, SDMMC2, MIO, 0x32d8, N, N), + PINGROUP(kb_row8_ps0, KBC, NAND, SDMMC2, MIO, 0x32dc, N, N), + PINGROUP(kb_row9_ps1, KBC, NAND, SDMMC2, MIO, 0x32e0, N, N), + PINGROUP(kb_row10_ps2, KBC, NAND, SDMMC2, MIO, 0x32e4, N, N), + PINGROUP(kb_row11_ps3, KBC, NAND, SDMMC2, MIO, 0x32e8, N, N), + PINGROUP(kb_row12_ps4, KBC, NAND, SDMMC2, MIO, 0x32ec, N, N), + PINGROUP(kb_row13_ps5, KBC, NAND, SDMMC2, MIO, 0x32f0, N, N), + PINGROUP(kb_row14_ps6, KBC, NAND, SDMMC2, MIO, 0x32f4, N, N), + PINGROUP(kb_row15_ps7, KBC, NAND, SDMMC2, MIO, 0x32f8, N, N), + PINGROUP(vi_pclk_pt0, RSVD1, SDMMC2, VI, RSVD4, 0x3154, N, Y), + PINGROUP(vi_mclk_pt1, VI, VI_ALT1, VI_ALT2, VI_ALT3, 0x3158, N, Y), + PINGROUP(vi_d10_pt2, DDR, RSVD2, VI, RSVD4, 0x314c, N, Y), + PINGROUP(vi_d11_pt3, DDR, RSVD2, VI, RSVD4, 0x3150, N, Y), + PINGROUP(vi_d0_pt4, DDR, RSVD2, VI, RSVD4, 0x3124, N, Y), + PINGROUP(gen2_i2c_scl_pt5, I2C2, HDCP, GMI, RSVD4, 0x3250, Y, N), + PINGROUP(gen2_i2c_sda_pt6, I2C2, HDCP, GMI, RSVD4, 0x3254, Y, N), + PINGROUP(sdmmc4_cmd_pt7, I2C3, NAND, GMI, SDMMC4, 0x325c, N, Y), + PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N), + PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N), + PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N), + PINGROUP(pu3, PWM0, UARTA, GMI, RSVD4, 0x3190, N, N), + PINGROUP(pu4, PWM1, UARTA, GMI, RSVD4, 0x3194, N, N), + PINGROUP(pu5, PWM2, UARTA, GMI, RSVD4, 0x3198, N, N), + PINGROUP(pu6, PWM3, UARTA, GMI, RSVD4, 0x319c, N, N), + PINGROUP(jtag_rtck_pu7, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N), + PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N), + PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N), + PINGROUP(pv2, OWR, RSVD2, RSVD3, RSVD4, 0x3060, N, N), + PINGROUP(pv3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4, 0x3064, N, N), + PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N), + PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N), + PINGROUP(crt_hsync_pv6, CRT, RSVD2, RSVD3, RSVD4, 0x311c, N, N), + PINGROUP(crt_vsync_pv7, CRT, RSVD2, RSVD3, RSVD4, 0x3120, N, N), + PINGROUP(lcd_cs1_n_pw0, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3104, N, N), + PINGROUP(lcd_m1_pw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3108, N, N), + PINGROUP(spi2_cs1_n_pw2, SPI3, SPI2, SPI2_ALT, I2C1, 0x3388, N, N), + PINGROUP(spi2_cs2_n_pw3, SPI3, SPI2, SPI2_ALT, I2C1, 0x338c, N, N), + PINGROUP(clk1_out_pw4, EXTPERIPH1, RSVD2, RSVD3, RSVD4, 0x334c, N, N), + PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N), + PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, RSVD4, 0x3174, N, N), + PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, RSVD4, 0x3178, N, N), + PINGROUP(spi2_mosi_px0, SPI6, SPI2, SPI3, GMI, 0x3368, N, N), + PINGROUP(spi2_miso_px1, SPI6, SPI2, SPI3, GMI, 0x336c, N, N), + PINGROUP(spi2_sck_px2, SPI6, SPI2, SPI3, GMI, 0x3374, N, N), + PINGROUP(spi2_cs0_n_px3, SPI6, SPI2, SPI3, GMI, 0x3370, N, N), + PINGROUP(spi1_mosi_px4, SPI2, SPI1, SPI2_ALT, GMI, 0x3378, N, N), + PINGROUP(spi1_sck_px5, SPI2, SPI1, SPI2_ALT, GMI, 0x337c, N, N), + PINGROUP(spi1_cs0_n_px6, SPI2, SPI1, SPI2_ALT, GMI, 0x3380, N, N), + PINGROUP(spi1_miso_px7, SPI3, SPI1, SPI2_ALT, RSVD4, 0x3384, N, N), + PINGROUP(ulpi_clk_py0, SPI1, RSVD2, UARTD, ULPI, 0x3020, N, N), + PINGROUP(ulpi_dir_py1, SPI1, RSVD2, UARTD, ULPI, 0x3024, N, N), + PINGROUP(ulpi_nxt_py2, SPI1, RSVD2, UARTD, ULPI, 0x3028, N, N), + PINGROUP(ulpi_stp_py3, SPI1, RSVD2, UARTD, ULPI, 0x302c, N, N), + PINGROUP(sdmmc1_dat3_py4, SDMMC1, RSVD2, UARTE, UARTA, 0x3050, N, N), + PINGROUP(sdmmc1_dat2_py5, SDMMC1, RSVD2, UARTE, UARTA, 0x3054, N, N), + PINGROUP(sdmmc1_dat1_py6, SDMMC1, RSVD2, UARTE, UARTA, 0x3058, N, N), + PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, UARTE, UARTA, 0x305c, N, N), + PINGROUP(sdmmc1_clk_pz0, SDMMC1, RSVD2, RSVD3, UARTA, 0x3048, N, N), + PINGROUP(sdmmc1_cmd_pz1, SDMMC1, RSVD2, RSVD3, UARTA, 0x304c, N, N), + PINGROUP(lcd_sdin_pz2, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3078, N, N), + PINGROUP(lcd_wr_n_pz3, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3080, N, N), + PINGROUP(lcd_sck_pz4, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x308c, N, N), + PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N), + PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N), + PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N), + PINGROUP(sdmmc4_dat0_paa0, UARTE, SPI3, GMI, SDMMC4, 0x3260, N, Y), + PINGROUP(sdmmc4_dat1_paa1, UARTE, SPI3, GMI, SDMMC4, 0x3264, N, Y), + PINGROUP(sdmmc4_dat2_paa2, UARTE, SPI3, GMI, SDMMC4, 0x3268, N, Y), + PINGROUP(sdmmc4_dat3_paa3, UARTE, SPI3, GMI, SDMMC4, 0x326c, N, Y), + PINGROUP(sdmmc4_dat4_paa4, I2C3, I2S4, GMI, SDMMC4, 0x3270, N, Y), + PINGROUP(sdmmc4_dat5_paa5, VGP3, I2S4, GMI, SDMMC4, 0x3274, N, Y), + PINGROUP(sdmmc4_dat6_paa6, VGP4, I2S4, GMI, SDMMC4, 0x3278, N, Y), + PINGROUP(sdmmc4_dat7_paa7, VGP5, I2S4, GMI, SDMMC4, 0x327c, N, Y), + PINGROUP(pbb0, I2S4, RSVD2, RSVD3, SDMMC4, 0x328c, N, N), + PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC4, 0x3290, Y, N), + PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC4, 0x3294, Y, N), + PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC4, 0x3298, N, N), + PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC4, 0x329c, N, N), + PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, SDMMC4, 0x32a0, N, N), + PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, SDMMC4, 0x32a4, N, N), + PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC4, 0x32a8, N, N), + PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC4, 0x3284, N, N), + PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC4, 0x3288, N, N), + PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N), + PINGROUP(sdmmc4_rst_n_pcc3, VGP6, RSVD2, RSVD3, SDMMC4, 0x3280, N, Y), + PINGROUP(sdmmc4_clk_pcc4, INVALID, NAND, GMI, SDMMC4, 0x3258, N, Y), + PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N), + PINGROUP(pex_l2_rst_n_pcc6, PCIE, HDA, RSVD3, RSVD4, 0x33d8, N, N), + PINGROUP(pex_l2_clkreq_n_pcc7, PCIE, HDA, RSVD3, RSVD4, 0x33dc, N, N), + PINGROUP(pex_l0_prsnt_n_pdd0, PCIE, HDA, RSVD3, RSVD4, 0x33b8, N, N), + PINGROUP(pex_l0_rst_n_pdd1, PCIE, HDA, RSVD3, RSVD4, 0x33bc, N, N), + PINGROUP(pex_l0_clkreq_n_pdd2, PCIE, HDA, RSVD3, RSVD4, 0x33c0, N, N), + PINGROUP(pex_wake_n_pdd3, PCIE, HDA, RSVD3, RSVD4, 0x33c4, N, N), + PINGROUP(pex_l1_prsnt_n_pdd4, PCIE, HDA, RSVD3, RSVD4, 0x33c8, N, N), + PINGROUP(pex_l1_rst_n_pdd5, PCIE, HDA, RSVD3, RSVD4, 0x33cc, N, N), + PINGROUP(pex_l1_clkreq_n_pdd6, PCIE, HDA, RSVD3, RSVD4, 0x33d0, N, N), + PINGROUP(pex_l2_prsnt_n_pdd7, PCIE, HDA, RSVD3, RSVD4, 0x33d4, N, N), + PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N), + PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N), + PINGROUP(clk1_req_pee2, DAP, HDA, RSVD3, RSVD4, 0x3348, N, N), + PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N), + PINGROUP(clk_32k_in, CLK_32K_IN, RSVD2, RSVD3, RSVD4, 0x3330, N, N), + PINGROUP(core_pwr_req, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3324, N, N), + PINGROUP(cpu_pwr_req, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3328, N, N), + PINGROUP(owr, OWR, CEC, RSVD3, RSVD4, 0x3334, N, N), + PINGROUP(pwr_int_n, PWR_INT_N, RSVD2, RSVD3, RSVD4, 0x332c, N, N), /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */ DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2), DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2), @@ -3735,6 +2488,7 @@ static struct of_device_id tegra30_pinctrl_of_match[] = { { .compatible = "nvidia,tegra30-pinmux", }, { }, }; +MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match); static struct platform_driver tegra30_pinctrl_driver = { .driver = { @@ -3745,20 +2499,8 @@ static struct platform_driver tegra30_pinctrl_driver = { .probe = tegra30_pinctrl_probe, .remove = tegra_pinctrl_remove, }; - -static int __init tegra30_pinctrl_init(void) -{ - return platform_driver_register(&tegra30_pinctrl_driver); -} -arch_initcall(tegra30_pinctrl_init); - -static void __exit tegra30_pinctrl_exit(void) -{ - platform_driver_unregister(&tegra30_pinctrl_driver); -} -module_exit(tegra30_pinctrl_exit); +module_platform_driver(tegra30_pinctrl_driver); MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c new file mode 100644 index 00000000000..5bf01c28925 --- /dev/null +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -0,0 +1,1029 @@ +/* + * Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins + * + * Copyright (c) 2013, Imagination Technologies Ltd. + * + * Derived from Tegra code: + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * + * Derived from code: + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010 NVIDIA Corporation + * Copyright (C) 2009-2011 ST-Ericsson AB + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/slab.h> + +/* + * The registers may be shared with other threads/cores, so we need to use the + * metag global lock2 for atomicity. + */ +#include <asm/global_lock.h> + +#include "core.h" +#include "pinconf.h" + +/* Register offsets from bank base address */ +#define REG_GPIO_CONTROL0 0x00 +#define REG_GPIO_CONTROL2 0x08 + +/* Register field information */ +#define REG_GPIO_CONTROL2_PU_PD_S 16 +#define REG_GPIO_CONTROL2_PDC_POS_S 4 +#define REG_GPIO_CONTROL2_PDC_DR_S 2 +#define REG_GPIO_CONTROL2_PDC_SR_S 1 +#define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0 + +/* PU_PD field values */ +#define REG_PU_PD_TRISTATE 0 +#define REG_PU_PD_UP 1 +#define REG_PU_PD_DOWN 2 +#define REG_PU_PD_REPEATER 3 + +/* DR field values */ +#define REG_DR_2mA 0 +#define REG_DR_4mA 1 +#define REG_DR_8mA 2 +#define REG_DR_12mA 3 + +/** + * struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function + * @name: The name of the function, exported to pinctrl core. + * @groups: An array of pin groups that may select this function. + * @ngroups: The number of entries in @groups. + */ +struct tz1090_pdc_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +/** + * struct tz1090_pdc_pingroup - TZ1090 PDC pin group + * @name: Name of pin group. + * @pins: Array of pin numbers in this pin group. + * @npins: Number of pins in this pin group. + * @func: Function enabled by the mux. + * @reg: Mux register offset. + * @bit: Mux register bit. + * @drv: Drive control supported, otherwise it's a mux. + * This means Schmitt, Slew, and Drive strength. + * + * A representation of a group of pins (possibly just one pin) in the TZ1090 + * PDC pin controller. Each group allows some parameter or parameters to be + * configured. The most common is mux function selection. + */ +struct tz1090_pdc_pingroup { + const char *name; + const unsigned int *pins; + unsigned int npins; + int func; + u16 reg; + u8 bit; + bool drv; +}; + +/* + * All PDC pins can be GPIOs. Define these first to match how the GPIO driver + * names/numbers its pins. + */ + +enum tz1090_pdc_pin { + TZ1090_PDC_PIN_GPIO0, + TZ1090_PDC_PIN_GPIO1, + TZ1090_PDC_PIN_SYS_WAKE0, + TZ1090_PDC_PIN_SYS_WAKE1, + TZ1090_PDC_PIN_SYS_WAKE2, + TZ1090_PDC_PIN_IR_DATA, + TZ1090_PDC_PIN_EXT_POWER, +}; + +/* Pin names */ + +static const struct pinctrl_pin_desc tz1090_pdc_pins[] = { + /* PDC GPIOs */ + PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"), + PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"), + PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"), + PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"), + PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"), + PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"), + PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"), +}; + +/* Pin group pins */ + +static const unsigned int gpio0_pins[] = { + TZ1090_PDC_PIN_GPIO0, +}; + +static const unsigned int gpio1_pins[] = { + TZ1090_PDC_PIN_GPIO1, +}; + +static const unsigned int pdc_pins[] = { + TZ1090_PDC_PIN_GPIO0, + TZ1090_PDC_PIN_GPIO1, + TZ1090_PDC_PIN_SYS_WAKE0, + TZ1090_PDC_PIN_SYS_WAKE1, + TZ1090_PDC_PIN_SYS_WAKE2, + TZ1090_PDC_PIN_IR_DATA, + TZ1090_PDC_PIN_EXT_POWER, +}; + +/* Mux functions */ + +enum tz1090_pdc_mux { + /* PDC_GPIO0 mux */ + TZ1090_PDC_MUX_IR_MOD_STABLE_OUT, + /* PDC_GPIO1 mux */ + TZ1090_PDC_MUX_IR_MOD_POWER_OUT, +}; + +/* Pin groups a function can be muxed to */ + +static const char * const gpio0_groups[] = { + "gpio0", +}; + +static const char * const gpio1_groups[] = { + "gpio1", +}; + +#define FUNCTION(mux, fname, group) \ + [(TZ1090_PDC_MUX_ ## mux)] = { \ + .name = #fname, \ + .groups = group##_groups, \ + .ngroups = ARRAY_SIZE(group##_groups), \ + } + +/* Must correlate with enum tz1090_pdc_mux */ +static const struct tz1090_pdc_function tz1090_pdc_functions[] = { + /* MUX fn pingroups */ + FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0), + FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1), +}; + +/** + * MUX_PG() - Initialise a pin group with mux control + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + * @f0: Function 0 (TZ1090_PDC_MUX_ is prepended) + * @mux_r: Mux register (REG_PINCTRL_ is prepended) + * @mux_b: Bit number in register of mux field + */ +#define MUX_PG(pg_name, f0, mux_r, mux_b) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .func = TZ1090_PDC_MUX_ ## f0, \ + .reg = (REG_ ## mux_r), \ + .bit = (mux_b), \ + } + +/** + * DRV_PG() - Initialise a pin group with drive control + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + */ +#define DRV_PG(pg_name) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .drv = true, \ + } + +static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = { + /* Muxing pin groups */ + /* pg_name, f0, mux register, mux bit */ + MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7), + MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6), + + /* Drive pin groups */ + /* pg_name */ + DRV_PG(pdc), +}; + +/** + * struct tz1090_pdc_pmx - Private pinctrl data + * @dev: Platform device + * @pctl: Pin control device + * @regs: Register region + * @lock: Lock protecting coherency of mux_en and gpio_en + * @mux_en: Muxes that have been enabled + * @gpio_en: Muxable GPIOs that have been enabled + */ +struct tz1090_pdc_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *regs; + spinlock_t lock; + u32 mux_en; + u32 gpio_en; +}; + +static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg) +{ + return ioread32(pmx->regs + reg); +} + +static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg) +{ + iowrite32(val, pmx->regs + reg); +} + +/* + * Pin control operations + */ + +static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(tz1090_pdc_groups); +} + +static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl, + unsigned int group) +{ + return tz1090_pdc_groups[group].name; +} + +static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + *pins = tz1090_pdc_groups[group].pins; + *num_pins = tz1090_pdc_groups[group].npins; + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} +#endif + +static int reserve_map(struct device *dev, struct pinctrl_map **map, + unsigned int *reserved_maps, unsigned int *num_maps, + unsigned int reserve) +{ + unsigned int old_num = *reserved_maps; + unsigned int new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) { + dev_err(dev, "krealloc(map) failed\n"); + return -ENOMEM; + } + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps, + unsigned int *num_maps, const char *group, + const char *function) +{ + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +/** + * get_group_selector() - returns the group selector for a group + * @pin_group: the pin group to look up + * + * This is the same as pinctrl_get_group_selector except it doesn't produce an + * error message if the group isn't found or debug messages. + */ +static int get_group_selector(const char *pin_group) +{ + unsigned int group; + + for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group) + if (!strcmp(tz1090_pdc_groups[group].name, pin_group)) + return group; + + return -EINVAL; +} + +static int add_map_configs(struct device *dev, + struct pinctrl_map **map, + unsigned int *reserved_maps, unsigned int *num_maps, + const char *group, unsigned long *configs, + unsigned int num_configs) +{ + unsigned long *dup_configs; + enum pinctrl_map_type type; + + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) { + dev_err(dev, "kmemdup(configs) failed\n"); + return -ENOMEM; + } + + /* + * We support both pins and pin groups, but we need to figure out which + * one we have. + */ + if (get_group_selector(group) >= 0) + type = PIN_MAP_TYPE_CONFIGS_GROUP; + else + type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[*num_maps].type = type; + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + + kfree(map); +} + +static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps) +{ + int ret; + const char *function; + unsigned long *configs = NULL; + unsigned int num_configs = 0; + unsigned int reserve; + struct property *prop; + const char *group; + + ret = of_property_read_string(np, "tz1090,function", &function); + if (ret < 0) { + /* EINVAL=missing, which is fine since it's optional */ + if (ret != -EINVAL) + dev_err(dev, + "could not parse property function\n"); + function = NULL; + } + + ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + if (ret) + return ret; + + reserve = 0; + if (function != NULL) + reserve++; + if (num_configs) + reserve++; + ret = of_property_count_strings(np, "tz1090,pins"); + if (ret < 0) { + dev_err(dev, "could not parse property pins\n"); + goto exit; + } + reserve *= ret; + + ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "tz1090,pins", prop, group) { + if (function) { + ret = add_map_mux(map, reserved_maps, num_maps, + group, function); + if (ret < 0) + goto exit; + } + + if (num_configs) { + ret = add_map_configs(dev, map, reserved_maps, + num_maps, group, configs, + num_configs); + if (ret < 0) + goto exit; + } + } + + ret = 0; + +exit: + kfree(configs); + return ret; +} + +static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + unsigned int reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np, + map, &reserved_maps, + num_maps); + if (ret < 0) { + tz1090_pdc_pinctrl_dt_free_map(pctldev, *map, + *num_maps); + return ret; + } + } + + return 0; +} + +static struct pinctrl_ops tz1090_pdc_pinctrl_ops = { + .get_groups_count = tz1090_pdc_pinctrl_get_groups_count, + .get_group_name = tz1090_pdc_pinctrl_get_group_name, + .get_group_pins = tz1090_pdc_pinctrl_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show, +#endif + .dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map, + .dt_free_map = tz1090_pdc_pinctrl_dt_free_map, +}; + +/* + * Pin mux operations + */ + +static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(tz1090_pdc_functions); +} + +static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return tz1090_pdc_functions[function].name; +} + +static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = tz1090_pdc_functions[function].groups; + *num_groups = tz1090_pdc_functions[function].ngroups; + + return 0; +} + +/** + * tz1090_pdc_pinctrl_mux() - update mux bit + * @pmx: Pinmux data + * @grp: Pin mux group + */ +static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx, + const struct tz1090_pdc_pingroup *grp) +{ + u32 reg, select; + unsigned int pin_shift = grp->pins[0]; + unsigned long flags; + + /* select = mux && !gpio */ + select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1; + + /* set up the mux */ + __global_lock2(flags); + reg = pmx_read(pmx, grp->reg); + reg &= ~BIT(grp->bit); + reg |= select << grp->bit; + pmx_write(pmx, reg, grp->reg); + __global_unlock2(flags); +} + +static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; + + dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n", + __func__, + function, tz1090_pdc_functions[function].name, + group, tz1090_pdc_groups[group].name); + + /* is it even a mux? */ + if (grp->drv) + return -EINVAL; + + /* does this group even control the function? */ + if (function != grp->func) + return -EINVAL; + + /* record the pin being muxed and update mux bit */ + spin_lock(&pmx->lock); + pmx->mux_en |= BIT(grp->pins[0]); + tz1090_pdc_pinctrl_mux(pmx, grp); + spin_unlock(&pmx->lock); + return 0; +} + +static void tz1090_pdc_pinctrl_disable(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; + + dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n", + __func__, + function, tz1090_pdc_functions[function].name, + group, tz1090_pdc_groups[group].name); + + /* is it even a mux? */ + if (grp->drv) + return; + + /* does this group even control the function? */ + if (function != grp->func) + return; + + /* record the pin being unmuxed and update mux bit */ + spin_lock(&pmx->lock); + pmx->mux_en &= ~BIT(grp->pins[0]); + tz1090_pdc_pinctrl_mux(pmx, grp); + spin_unlock(&pmx->lock); +} + +static const struct tz1090_pdc_pingroup *find_mux_group( + struct tz1090_pdc_pmx *pmx, + unsigned int pin) +{ + const struct tz1090_pdc_pingroup *grp; + unsigned int group; + + grp = tz1090_pdc_groups; + for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) { + /* only match muxes */ + if (grp->drv) + continue; + + /* with a matching pin */ + if (grp->pins[0] == pin) + return grp; + } + + return NULL; +} + +static int tz1090_pdc_pinctrl_gpio_request_enable( + struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); + + if (grp) { + /* record the pin in GPIO use and update mux bit */ + spin_lock(&pmx->lock); + pmx->gpio_en |= BIT(pin); + tz1090_pdc_pinctrl_mux(pmx, grp); + spin_unlock(&pmx->lock); + } + return 0; +} + +static void tz1090_pdc_pinctrl_gpio_disable_free( + struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); + + if (grp) { + /* record the pin not in GPIO use and update mux bit */ + spin_lock(&pmx->lock); + pmx->gpio_en &= ~BIT(pin); + tz1090_pdc_pinctrl_mux(pmx, grp); + spin_unlock(&pmx->lock); + } +} + +static struct pinmux_ops tz1090_pdc_pinmux_ops = { + .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count, + .get_function_name = tz1090_pdc_pinctrl_get_func_name, + .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, + .enable = tz1090_pdc_pinctrl_enable, + .disable = tz1090_pdc_pinctrl_disable, + .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, + .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, +}; + +/* + * Pin config operations + */ + +static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev, + unsigned int pin, + enum pin_config_param param, + bool report_err, + u32 *reg, u32 *width, u32 *mask, u32 *shift, + u32 *val) +{ + /* Find information about parameter's register */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + *val = REG_PU_PD_TRISTATE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *val = REG_PU_PD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + *val = REG_PU_PD_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + *val = REG_PU_PD_REPEATER; + break; + default: + return -ENOTSUPP; + }; + + /* Only input bias parameters supported */ + *reg = REG_GPIO_CONTROL2; + *shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2; + *width = 2; + + /* Calculate field information */ + *mask = (BIT(*width) - 1) << *shift; + + return 0; +} + +static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + int ret; + u32 reg, width, mask, shift, val, tmp, arg; + + /* Get register information */ + ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; + + /* Extract field from register */ + tmp = pmx_read(pmx, reg); + arg = ((tmp & mask) >> shift) == val; + + /* Config not active */ + if (!arg) + return -EINVAL; + + /* And pack config */ + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *configs, + unsigned num_configs) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + unsigned int arg; + int ret; + u32 reg, width, mask, shift, val, tmp; + unsigned long flags; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", + __func__, tz1090_pdc_pins[pin].name, configs[i]); + + /* Get register information */ + ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; + + /* Unpack argument and range check it */ + if (arg > 1) { + dev_dbg(pctldev->dev, "%s: arg %u out of range\n", + __func__, arg); + return -EINVAL; + } + + /* Write register field */ + __global_lock2(flags); + tmp = pmx_read(pmx, reg); + tmp &= ~mask; + if (arg) + tmp |= val << shift; + pmx_write(pmx, tmp, reg); + __global_unlock2(flags); + } /* for each config */ + + return 0; +} + +static const int tz1090_pdc_boolean_map[] = { + [0] = -EINVAL, + [1] = 1, +}; + +static const int tz1090_pdc_dr_map[] = { + [REG_DR_2mA] = 2, + [REG_DR_4mA] = 4, + [REG_DR_8mA] = 8, + [REG_DR_12mA] = 12, +}; + +static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev, + const struct tz1090_pdc_pingroup *g, + enum pin_config_param param, + bool report_err, u32 *reg, u32 *width, + u32 *mask, u32 *shift, const int **map) +{ + /* Drive configuration applies in groups, but not to all groups. */ + if (!g->drv) { + if (report_err) + dev_dbg(pctldev->dev, + "%s: group %s has no drive control\n", + __func__, g->name); + return -ENOTSUPP; + } + + /* Find information about drive parameter's register */ + *reg = REG_GPIO_CONTROL2; + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S; + *width = 1; + *map = tz1090_pdc_boolean_map; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + *shift = REG_GPIO_CONTROL2_PDC_DR_S; + *width = 2; + *map = tz1090_pdc_dr_map; + break; + case PIN_CONFIG_LOW_POWER_MODE: + *shift = REG_GPIO_CONTROL2_PDC_POS_S; + *width = 1; + *map = tz1090_pdc_boolean_map; + break; + default: + return -ENOTSUPP; + }; + + /* Calculate field information */ + *mask = (BIT(*width) - 1) << *shift; + + return 0; +} + +static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; + enum pin_config_param param = pinconf_to_config_param(*config); + int ret, arg; + u32 reg, width, mask, shift, val; + const int *map; + + /* Get register information */ + ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, + ®, &width, &mask, &shift, &map); + if (ret < 0) + return ret; + + /* Extract field from register */ + val = pmx_read(pmx, reg); + arg = map[(val & mask) >> shift]; + if (arg < 0) + return arg; + + /* And pack config */ + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *configs, + unsigned num_configs) +{ + struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; + enum pin_config_param param; + const unsigned int *pit; + unsigned int i; + int ret, arg; + u32 reg, width, mask, shift, val; + unsigned long flags; + const int *map; + int j; + + for (j = 0; j < num_configs; j++) { + param = pinconf_to_config_param(configs[j]); + + dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", + __func__, g->name, configs[j]); + + /* Get register information */ + ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, + ®, &width, &mask, &shift, + &map); + if (ret < 0) { + /* + * Maybe we're trying to set a per-pin configuration + * of a group, so do the pins one by one. This is + * mainly as a convenience. + */ + for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { + ret = tz1090_pdc_pinconf_set(pctldev, *pit, + configs, num_configs); + if (ret) + return ret; + } + return 0; + } + + /* Unpack argument and map it to register value */ + arg = pinconf_to_config_argument(configs[j]); + for (i = 0; i < BIT(width); ++i) { + if (map[i] == arg || (map[i] == -EINVAL && !arg)) { + /* Write register field */ + __global_lock2(flags); + val = pmx_read(pmx, reg); + val &= ~mask; + val |= i << shift; + pmx_write(pmx, val, reg); + __global_unlock2(flags); + goto next_config; + } + } + + dev_dbg(pctldev->dev, "%s: arg %u not supported\n", + __func__, arg); + return 0; + +next_config: + ; + } /* for each config */ + + return 0; +} + +static struct pinconf_ops tz1090_pdc_pinconf_ops = { + .is_generic = true, + .pin_config_get = tz1090_pdc_pinconf_get, + .pin_config_set = tz1090_pdc_pinconf_set, + .pin_config_group_get = tz1090_pdc_pinconf_group_get, + .pin_config_group_set = tz1090_pdc_pinconf_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +/* + * Pin control driver setup + */ + +static struct pinctrl_desc tz1090_pdc_pinctrl_desc = { + .pctlops = &tz1090_pdc_pinctrl_ops, + .pmxops = &tz1090_pdc_pinmux_ops, + .confops = &tz1090_pdc_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev) +{ + struct tz1090_pdc_pmx *pmx; + struct resource *res; + + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) { + dev_err(&pdev->dev, "Can't alloc tz1090_pdc_pmx\n"); + return -ENOMEM; + } + pmx->dev = &pdev->dev; + spin_lock_init(&pmx->lock); + + tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev); + tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins; + tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pmx->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmx->regs)) + return PTR_ERR(pmx->regs); + + pmx->pctl = pinctrl_register(&tz1090_pdc_pinctrl_desc, &pdev->dev, pmx); + if (!pmx->pctl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, pmx); + + dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n"); + + return 0; +} + +static int tz1090_pdc_pinctrl_remove(struct platform_device *pdev) +{ + struct tz1090_pdc_pmx *pmx = platform_get_drvdata(pdev); + + pinctrl_unregister(pmx->pctl); + + return 0; +} + +static struct of_device_id tz1090_pdc_pinctrl_of_match[] = { + { .compatible = "img,tz1090-pdc-pinctrl", }, + { }, +}; + +static struct platform_driver tz1090_pdc_pinctrl_driver = { + .driver = { + .name = "tz1090-pdc-pinctrl", + .owner = THIS_MODULE, + .of_match_table = tz1090_pdc_pinctrl_of_match, + }, + .probe = tz1090_pdc_pinctrl_probe, + .remove = tz1090_pdc_pinctrl_remove, +}; + +static int __init tz1090_pdc_pinctrl_init(void) +{ + return platform_driver_register(&tz1090_pdc_pinctrl_driver); +} +arch_initcall(tz1090_pdc_pinctrl_init); + +static void __exit tz1090_pdc_pinctrl_exit(void) +{ + platform_driver_unregister(&tz1090_pdc_pinctrl_driver); +} +module_exit(tz1090_pdc_pinctrl_exit); + +MODULE_AUTHOR("Imagination Technologies Ltd."); +MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c new file mode 100644 index 00000000000..bc9cd7a7602 --- /dev/null +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -0,0 +1,2076 @@ +/* + * Pinctrl driver for the Toumaz Xenif TZ1090 SoC + * + * Copyright (c) 2013, Imagination Technologies Ltd. + * + * Derived from Tegra code: + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. + * + * Derived from code: + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010 NVIDIA Corporation + * Copyright (C) 2009-2011 ST-Ericsson AB + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +/* + * The registers may be shared with other threads/cores, so we need to use the + * metag global lock2 for atomicity. + */ +#include <asm/global_lock.h> + +#include "core.h" +#include "pinconf.h" + +/* Register offsets from bank base address */ +#define REG_PINCTRL_SELECT 0x10 +#define REG_PINCTRL_SCHMITT 0x90 +#define REG_PINCTRL_PU_PD 0xa0 +#define REG_PINCTRL_SR 0xc0 +#define REG_PINCTRL_DR 0xd0 +#define REG_PINCTRL_IF_CTL 0xe0 + +/* REG_PINCTRL_PU_PD field values */ +#define REG_PU_PD_TRISTATE 0 +#define REG_PU_PD_UP 1 +#define REG_PU_PD_DOWN 2 +#define REG_PU_PD_REPEATER 3 + +/* REG_PINCTRL_DR field values */ +#define REG_DR_2mA 0 +#define REG_DR_4mA 1 +#define REG_DR_8mA 2 +#define REG_DR_12mA 3 + +/** + * struct tz1090_function - TZ1090 pinctrl mux function + * @name: The name of the function, exported to pinctrl core. + * @groups: An array of pin groups that may select this function. + * @ngroups: The number of entries in @groups. + */ +struct tz1090_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +/** + * struct tz1090_muxdesc - TZ1090 individual mux description + * @funcs: Function for each mux value. + * @reg: Mux register offset. 0 if unsupported. + * @bit: Mux register bit. 0 if unsupported. + * @width: Mux field width. 0 if unsupported. + * + * A representation of a group of signals (possibly just one signal) in the + * TZ1090 which can be muxed to a set of functions or sub muxes. + */ +struct tz1090_muxdesc { + int funcs[5]; + u16 reg; + u8 bit; + u8 width; +}; + +/** + * struct tz1090_pingroup - TZ1090 pin group + * @name: Name of pin group. + * @pins: Array of pin numbers in this pin group. + * @npins: Number of pins in this pin group. + * @mux: Top level mux. + * @drv: Drive control supported, 0 if unsupported. + * This means Schmitt, Slew, and Drive strength. + * @slw_bit: Slew register bit. 0 if unsupported. + * The same bit is used for Schmitt, and Drive (*2). + * @func: Currently muxed function. + * @func_count: Number of pins using current mux function. + * + * A representation of a group of pins (possibly just one pin) in the TZ1090 + * pin controller. Each group allows some parameter or parameters to be + * configured. The most common is mux function selection. + */ +struct tz1090_pingroup { + const char *name; + const unsigned int *pins; + unsigned int npins; + struct tz1090_muxdesc mux; + + bool drv; + u8 slw_bit; + + int func; + unsigned int func_count; +}; + +/* + * Most pins affected by the pinmux can also be GPIOs. Define these first. + * These must match how the GPIO driver names/numbers its pins. + */ + +enum tz1090_pin { + /* GPIO pins */ + TZ1090_PIN_SDIO_CLK, + TZ1090_PIN_SDIO_CMD, + TZ1090_PIN_SDIO_D0, + TZ1090_PIN_SDIO_D1, + TZ1090_PIN_SDIO_D2, + TZ1090_PIN_SDIO_D3, + TZ1090_PIN_SDH_CD, + TZ1090_PIN_SDH_WP, + TZ1090_PIN_SPI0_MCLK, + TZ1090_PIN_SPI0_CS0, + TZ1090_PIN_SPI0_CS1, + TZ1090_PIN_SPI0_CS2, + TZ1090_PIN_SPI0_DOUT, + TZ1090_PIN_SPI0_DIN, + TZ1090_PIN_SPI1_MCLK, + TZ1090_PIN_SPI1_CS0, + TZ1090_PIN_SPI1_CS1, + TZ1090_PIN_SPI1_CS2, + TZ1090_PIN_SPI1_DOUT, + TZ1090_PIN_SPI1_DIN, + TZ1090_PIN_UART0_RXD, + TZ1090_PIN_UART0_TXD, + TZ1090_PIN_UART0_CTS, + TZ1090_PIN_UART0_RTS, + TZ1090_PIN_UART1_RXD, + TZ1090_PIN_UART1_TXD, + TZ1090_PIN_SCB0_SDAT, + TZ1090_PIN_SCB0_SCLK, + TZ1090_PIN_SCB1_SDAT, + TZ1090_PIN_SCB1_SCLK, + TZ1090_PIN_SCB2_SDAT, + TZ1090_PIN_SCB2_SCLK, + TZ1090_PIN_I2S_MCLK, + TZ1090_PIN_I2S_BCLK_OUT, + TZ1090_PIN_I2S_LRCLK_OUT, + TZ1090_PIN_I2S_DOUT0, + TZ1090_PIN_I2S_DOUT1, + TZ1090_PIN_I2S_DOUT2, + TZ1090_PIN_I2S_DIN, + TZ1090_PIN_PDM_A, + TZ1090_PIN_PDM_B, + TZ1090_PIN_PDM_C, + TZ1090_PIN_PDM_D, + TZ1090_PIN_TFT_RED0, + TZ1090_PIN_TFT_RED1, + TZ1090_PIN_TFT_RED2, + TZ1090_PIN_TFT_RED3, + TZ1090_PIN_TFT_RED4, + TZ1090_PIN_TFT_RED5, + TZ1090_PIN_TFT_RED6, + TZ1090_PIN_TFT_RED7, + TZ1090_PIN_TFT_GREEN0, + TZ1090_PIN_TFT_GREEN1, + TZ1090_PIN_TFT_GREEN2, + TZ1090_PIN_TFT_GREEN3, + TZ1090_PIN_TFT_GREEN4, + TZ1090_PIN_TFT_GREEN5, + TZ1090_PIN_TFT_GREEN6, + TZ1090_PIN_TFT_GREEN7, + TZ1090_PIN_TFT_BLUE0, + TZ1090_PIN_TFT_BLUE1, + TZ1090_PIN_TFT_BLUE2, + TZ1090_PIN_TFT_BLUE3, + TZ1090_PIN_TFT_BLUE4, + TZ1090_PIN_TFT_BLUE5, + TZ1090_PIN_TFT_BLUE6, + TZ1090_PIN_TFT_BLUE7, + TZ1090_PIN_TFT_VDDEN_GD, + TZ1090_PIN_TFT_PANELCLK, + TZ1090_PIN_TFT_BLANK_LS, + TZ1090_PIN_TFT_VSYNC_NS, + TZ1090_PIN_TFT_HSYNC_NR, + TZ1090_PIN_TFT_VD12ACB, + TZ1090_PIN_TFT_PWRSAVE, + TZ1090_PIN_TX_ON, + TZ1090_PIN_RX_ON, + TZ1090_PIN_PLL_ON, + TZ1090_PIN_PA_ON, + TZ1090_PIN_RX_HP, + TZ1090_PIN_GAIN0, + TZ1090_PIN_GAIN1, + TZ1090_PIN_GAIN2, + TZ1090_PIN_GAIN3, + TZ1090_PIN_GAIN4, + TZ1090_PIN_GAIN5, + TZ1090_PIN_GAIN6, + TZ1090_PIN_GAIN7, + TZ1090_PIN_ANT_SEL0, + TZ1090_PIN_ANT_SEL1, + TZ1090_PIN_SDH_CLK_IN, + + /* Non-GPIO pins */ + TZ1090_PIN_TCK, + TZ1090_PIN_TRST, + TZ1090_PIN_TDI, + TZ1090_PIN_TDO, + TZ1090_PIN_TMS, + TZ1090_PIN_CLK_OUT0, + TZ1090_PIN_CLK_OUT1, + + NUM_GPIOS = TZ1090_PIN_TCK, +}; + +/* Pin names */ + +static const struct pinctrl_pin_desc tz1090_pins[] = { + /* GPIO pins */ + PINCTRL_PIN(TZ1090_PIN_SDIO_CLK, "sdio_clk"), + PINCTRL_PIN(TZ1090_PIN_SDIO_CMD, "sdio_cmd"), + PINCTRL_PIN(TZ1090_PIN_SDIO_D0, "sdio_d0"), + PINCTRL_PIN(TZ1090_PIN_SDIO_D1, "sdio_d1"), + PINCTRL_PIN(TZ1090_PIN_SDIO_D2, "sdio_d2"), + PINCTRL_PIN(TZ1090_PIN_SDIO_D3, "sdio_d3"), + PINCTRL_PIN(TZ1090_PIN_SDH_CD, "sdh_cd"), + PINCTRL_PIN(TZ1090_PIN_SDH_WP, "sdh_wp"), + PINCTRL_PIN(TZ1090_PIN_SPI0_MCLK, "spi0_mclk"), + PINCTRL_PIN(TZ1090_PIN_SPI0_CS0, "spi0_cs0"), + PINCTRL_PIN(TZ1090_PIN_SPI0_CS1, "spi0_cs1"), + PINCTRL_PIN(TZ1090_PIN_SPI0_CS2, "spi0_cs2"), + PINCTRL_PIN(TZ1090_PIN_SPI0_DOUT, "spi0_dout"), + PINCTRL_PIN(TZ1090_PIN_SPI0_DIN, "spi0_din"), + PINCTRL_PIN(TZ1090_PIN_SPI1_MCLK, "spi1_mclk"), + PINCTRL_PIN(TZ1090_PIN_SPI1_CS0, "spi1_cs0"), + PINCTRL_PIN(TZ1090_PIN_SPI1_CS1, "spi1_cs1"), + PINCTRL_PIN(TZ1090_PIN_SPI1_CS2, "spi1_cs2"), + PINCTRL_PIN(TZ1090_PIN_SPI1_DOUT, "spi1_dout"), + PINCTRL_PIN(TZ1090_PIN_SPI1_DIN, "spi1_din"), + PINCTRL_PIN(TZ1090_PIN_UART0_RXD, "uart0_rxd"), + PINCTRL_PIN(TZ1090_PIN_UART0_TXD, "uart0_txd"), + PINCTRL_PIN(TZ1090_PIN_UART0_CTS, "uart0_cts"), + PINCTRL_PIN(TZ1090_PIN_UART0_RTS, "uart0_rts"), + PINCTRL_PIN(TZ1090_PIN_UART1_RXD, "uart1_rxd"), + PINCTRL_PIN(TZ1090_PIN_UART1_TXD, "uart1_txd"), + PINCTRL_PIN(TZ1090_PIN_SCB0_SDAT, "scb0_sdat"), + PINCTRL_PIN(TZ1090_PIN_SCB0_SCLK, "scb0_sclk"), + PINCTRL_PIN(TZ1090_PIN_SCB1_SDAT, "scb1_sdat"), + PINCTRL_PIN(TZ1090_PIN_SCB1_SCLK, "scb1_sclk"), + PINCTRL_PIN(TZ1090_PIN_SCB2_SDAT, "scb2_sdat"), + PINCTRL_PIN(TZ1090_PIN_SCB2_SCLK, "scb2_sclk"), + PINCTRL_PIN(TZ1090_PIN_I2S_MCLK, "i2s_mclk"), + PINCTRL_PIN(TZ1090_PIN_I2S_BCLK_OUT, "i2s_bclk_out"), + PINCTRL_PIN(TZ1090_PIN_I2S_LRCLK_OUT, "i2s_lrclk_out"), + PINCTRL_PIN(TZ1090_PIN_I2S_DOUT0, "i2s_dout0"), + PINCTRL_PIN(TZ1090_PIN_I2S_DOUT1, "i2s_dout1"), + PINCTRL_PIN(TZ1090_PIN_I2S_DOUT2, "i2s_dout2"), + PINCTRL_PIN(TZ1090_PIN_I2S_DIN, "i2s_din"), + PINCTRL_PIN(TZ1090_PIN_PDM_A, "pdm_a"), + PINCTRL_PIN(TZ1090_PIN_PDM_B, "pdm_b"), + PINCTRL_PIN(TZ1090_PIN_PDM_C, "pdm_c"), + PINCTRL_PIN(TZ1090_PIN_PDM_D, "pdm_d"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED0, "tft_red0"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED1, "tft_red1"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED2, "tft_red2"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED3, "tft_red3"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED4, "tft_red4"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED5, "tft_red5"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED6, "tft_red6"), + PINCTRL_PIN(TZ1090_PIN_TFT_RED7, "tft_red7"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN0, "tft_green0"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN1, "tft_green1"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN2, "tft_green2"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN3, "tft_green3"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN4, "tft_green4"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN5, "tft_green5"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN6, "tft_green6"), + PINCTRL_PIN(TZ1090_PIN_TFT_GREEN7, "tft_green7"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE0, "tft_blue0"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE1, "tft_blue1"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE2, "tft_blue2"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE3, "tft_blue3"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE4, "tft_blue4"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE5, "tft_blue5"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE6, "tft_blue6"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLUE7, "tft_blue7"), + PINCTRL_PIN(TZ1090_PIN_TFT_VDDEN_GD, "tft_vdden_gd"), + PINCTRL_PIN(TZ1090_PIN_TFT_PANELCLK, "tft_panelclk"), + PINCTRL_PIN(TZ1090_PIN_TFT_BLANK_LS, "tft_blank_ls"), + PINCTRL_PIN(TZ1090_PIN_TFT_VSYNC_NS, "tft_vsync_ns"), + PINCTRL_PIN(TZ1090_PIN_TFT_HSYNC_NR, "tft_hsync_nr"), + PINCTRL_PIN(TZ1090_PIN_TFT_VD12ACB, "tft_vd12acb"), + PINCTRL_PIN(TZ1090_PIN_TFT_PWRSAVE, "tft_pwrsave"), + PINCTRL_PIN(TZ1090_PIN_TX_ON, "tx_on"), + PINCTRL_PIN(TZ1090_PIN_RX_ON, "rx_on"), + PINCTRL_PIN(TZ1090_PIN_PLL_ON, "pll_on"), + PINCTRL_PIN(TZ1090_PIN_PA_ON, "pa_on"), + PINCTRL_PIN(TZ1090_PIN_RX_HP, "rx_hp"), + PINCTRL_PIN(TZ1090_PIN_GAIN0, "gain0"), + PINCTRL_PIN(TZ1090_PIN_GAIN1, "gain1"), + PINCTRL_PIN(TZ1090_PIN_GAIN2, "gain2"), + PINCTRL_PIN(TZ1090_PIN_GAIN3, "gain3"), + PINCTRL_PIN(TZ1090_PIN_GAIN4, "gain4"), + PINCTRL_PIN(TZ1090_PIN_GAIN5, "gain5"), + PINCTRL_PIN(TZ1090_PIN_GAIN6, "gain6"), + PINCTRL_PIN(TZ1090_PIN_GAIN7, "gain7"), + PINCTRL_PIN(TZ1090_PIN_ANT_SEL0, "ant_sel0"), + PINCTRL_PIN(TZ1090_PIN_ANT_SEL1, "ant_sel1"), + PINCTRL_PIN(TZ1090_PIN_SDH_CLK_IN, "sdh_clk_in"), + + /* Non-GPIO pins */ + PINCTRL_PIN(TZ1090_PIN_TCK, "tck"), + PINCTRL_PIN(TZ1090_PIN_TRST, "trst"), + PINCTRL_PIN(TZ1090_PIN_TDI, "tdi"), + PINCTRL_PIN(TZ1090_PIN_TDO, "tdo"), + PINCTRL_PIN(TZ1090_PIN_TMS, "tms"), + PINCTRL_PIN(TZ1090_PIN_CLK_OUT0, "clk_out0"), + PINCTRL_PIN(TZ1090_PIN_CLK_OUT1, "clk_out1"), +}; + +/* Pins in each pin group */ + +static const unsigned int spi1_cs2_pins[] = { + TZ1090_PIN_SPI1_CS2, +}; + +static const unsigned int pdm_d_pins[] = { + TZ1090_PIN_PDM_D, +}; + +static const unsigned int tft_pins[] = { + TZ1090_PIN_TFT_RED0, + TZ1090_PIN_TFT_RED1, + TZ1090_PIN_TFT_RED2, + TZ1090_PIN_TFT_RED3, + TZ1090_PIN_TFT_RED4, + TZ1090_PIN_TFT_RED5, + TZ1090_PIN_TFT_RED6, + TZ1090_PIN_TFT_RED7, + TZ1090_PIN_TFT_GREEN0, + TZ1090_PIN_TFT_GREEN1, + TZ1090_PIN_TFT_GREEN2, + TZ1090_PIN_TFT_GREEN3, + TZ1090_PIN_TFT_GREEN4, + TZ1090_PIN_TFT_GREEN5, + TZ1090_PIN_TFT_GREEN6, + TZ1090_PIN_TFT_GREEN7, + TZ1090_PIN_TFT_BLUE0, + TZ1090_PIN_TFT_BLUE1, + TZ1090_PIN_TFT_BLUE2, + TZ1090_PIN_TFT_BLUE3, + TZ1090_PIN_TFT_BLUE4, + TZ1090_PIN_TFT_BLUE5, + TZ1090_PIN_TFT_BLUE6, + TZ1090_PIN_TFT_BLUE7, + TZ1090_PIN_TFT_VDDEN_GD, + TZ1090_PIN_TFT_PANELCLK, + TZ1090_PIN_TFT_BLANK_LS, + TZ1090_PIN_TFT_VSYNC_NS, + TZ1090_PIN_TFT_HSYNC_NR, + TZ1090_PIN_TFT_VD12ACB, + TZ1090_PIN_TFT_PWRSAVE, +}; + +static const unsigned int afe_pins[] = { + TZ1090_PIN_TX_ON, + TZ1090_PIN_RX_ON, + TZ1090_PIN_PLL_ON, + TZ1090_PIN_PA_ON, + TZ1090_PIN_RX_HP, + TZ1090_PIN_ANT_SEL0, + TZ1090_PIN_ANT_SEL1, + TZ1090_PIN_GAIN0, + TZ1090_PIN_GAIN1, + TZ1090_PIN_GAIN2, + TZ1090_PIN_GAIN3, + TZ1090_PIN_GAIN4, + TZ1090_PIN_GAIN5, + TZ1090_PIN_GAIN6, + TZ1090_PIN_GAIN7, +}; + +static const unsigned int sdio_pins[] = { + TZ1090_PIN_SDIO_CLK, + TZ1090_PIN_SDIO_CMD, + TZ1090_PIN_SDIO_D0, + TZ1090_PIN_SDIO_D1, + TZ1090_PIN_SDIO_D2, + TZ1090_PIN_SDIO_D3, +}; + +static const unsigned int sdh_pins[] = { + TZ1090_PIN_SDH_CD, + TZ1090_PIN_SDH_WP, + TZ1090_PIN_SDH_CLK_IN, +}; + +static const unsigned int spi0_pins[] = { + TZ1090_PIN_SPI0_MCLK, + TZ1090_PIN_SPI0_CS0, + TZ1090_PIN_SPI0_CS1, + TZ1090_PIN_SPI0_CS2, + TZ1090_PIN_SPI0_DOUT, + TZ1090_PIN_SPI0_DIN, +}; + +static const unsigned int spi1_pins[] = { + TZ1090_PIN_SPI1_MCLK, + TZ1090_PIN_SPI1_CS0, + TZ1090_PIN_SPI1_CS1, + TZ1090_PIN_SPI1_CS2, + TZ1090_PIN_SPI1_DOUT, + TZ1090_PIN_SPI1_DIN, +}; + +static const unsigned int uart0_pins[] = { + TZ1090_PIN_UART0_RTS, + TZ1090_PIN_UART0_CTS, + TZ1090_PIN_UART0_TXD, + TZ1090_PIN_UART0_RXD, +}; + +static const unsigned int uart1_pins[] = { + TZ1090_PIN_UART1_TXD, + TZ1090_PIN_UART1_RXD, +}; + +static const unsigned int uart_pins[] = { + TZ1090_PIN_UART1_TXD, + TZ1090_PIN_UART1_RXD, + TZ1090_PIN_UART0_RTS, + TZ1090_PIN_UART0_CTS, + TZ1090_PIN_UART0_TXD, + TZ1090_PIN_UART0_RXD, +}; + +static const unsigned int scb0_pins[] = { + TZ1090_PIN_SCB0_SDAT, + TZ1090_PIN_SCB0_SCLK, +}; + +static const unsigned int scb1_pins[] = { + TZ1090_PIN_SCB1_SDAT, + TZ1090_PIN_SCB1_SCLK, +}; + +static const unsigned int scb2_pins[] = { + TZ1090_PIN_SCB2_SDAT, + TZ1090_PIN_SCB2_SCLK, +}; + +static const unsigned int i2s_pins[] = { + TZ1090_PIN_I2S_MCLK, + TZ1090_PIN_I2S_BCLK_OUT, + TZ1090_PIN_I2S_LRCLK_OUT, + TZ1090_PIN_I2S_DOUT0, + TZ1090_PIN_I2S_DOUT1, + TZ1090_PIN_I2S_DOUT2, + TZ1090_PIN_I2S_DIN, +}; + +static const unsigned int jtag_pins[] = { + TZ1090_PIN_TCK, + TZ1090_PIN_TRST, + TZ1090_PIN_TDI, + TZ1090_PIN_TDO, + TZ1090_PIN_TMS, +}; + +/* Pins in each drive pin group */ + +static const unsigned int drive_sdio_pins[] = { + TZ1090_PIN_SDIO_CLK, + TZ1090_PIN_SDIO_CMD, + TZ1090_PIN_SDIO_D0, + TZ1090_PIN_SDIO_D1, + TZ1090_PIN_SDIO_D2, + TZ1090_PIN_SDIO_D3, + TZ1090_PIN_SDH_WP, + TZ1090_PIN_SDH_CD, + TZ1090_PIN_SDH_CLK_IN, +}; + +static const unsigned int drive_i2s_pins[] = { + TZ1090_PIN_CLK_OUT1, + TZ1090_PIN_I2S_DIN, + TZ1090_PIN_I2S_DOUT0, + TZ1090_PIN_I2S_DOUT1, + TZ1090_PIN_I2S_DOUT2, + TZ1090_PIN_I2S_LRCLK_OUT, + TZ1090_PIN_I2S_BCLK_OUT, + TZ1090_PIN_I2S_MCLK, +}; + +static const unsigned int drive_scb0_pins[] = { + TZ1090_PIN_SCB0_SCLK, + TZ1090_PIN_SCB0_SDAT, + TZ1090_PIN_PDM_D, + TZ1090_PIN_PDM_C, +}; + +static const unsigned int drive_pdm_pins[] = { + TZ1090_PIN_CLK_OUT0, + TZ1090_PIN_PDM_B, + TZ1090_PIN_PDM_A, +}; + +/* Pin groups each function can be muxed to */ + +/* + * The magic "perip" function allows otherwise non-muxing pins to be enabled in + * peripheral mode. + */ +static const char * const perip_groups[] = { + /* non-muxing convenient gpio pingroups */ + "uart", + "uart0", + "uart1", + "spi0", + "spi1", + "scb0", + "scb1", + "scb2", + "i2s", + /* individual pins not part of a pin mux group */ + "spi0_mclk", + "spi0_cs0", + "spi0_cs1", + "spi0_cs2", + "spi0_dout", + "spi0_din", + "spi1_mclk", + "spi1_cs0", + "spi1_cs1", + "spi1_dout", + "spi1_din", + "uart0_rxd", + "uart0_txd", + "uart0_cts", + "uart0_rts", + "uart1_rxd", + "uart1_txd", + "scb0_sdat", + "scb0_sclk", + "scb1_sdat", + "scb1_sclk", + "scb2_sdat", + "scb2_sclk", + "i2s_mclk", + "i2s_bclk_out", + "i2s_lrclk_out", + "i2s_dout0", + "i2s_dout1", + "i2s_dout2", + "i2s_din", + "pdm_a", + "pdm_b", + "pdm_c", +}; + +static const char * const sdh_sdio_groups[] = { + "sdh", + "sdio", + /* sdh pins */ + "sdh_cd", + "sdh_wp", + "sdh_clk_in", + /* sdio pins */ + "sdio_clk", + "sdio_cmd", + "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", +}; + +static const char * const spi1_cs2_groups[] = { + "spi1_cs2", +}; + +static const char * const pdm_dac_groups[] = { + "pdm_d", +}; + +static const char * const usb_vbus_groups[] = { + "spi1_cs2", + "pdm_d", +}; + +static const char * const afe_groups[] = { + "afe", + /* afe pins */ + "tx_on", + "rx_on", + "pll_on", + "pa_on", + "rx_hp", + "ant_sel0", + "ant_sel1", + "gain0", + "gain1", + "gain2", + "gain3", + "gain4", + "gain5", + "gain6", + "gain7", +}; + +static const char * const tft_groups[] = { + "tft", + /* tft pins */ + "tft_red0", + "tft_red1", + "tft_red2", + "tft_red3", + "tft_red4", + "tft_red5", + "tft_red6", + "tft_red7", + "tft_green0", + "tft_green1", + "tft_green2", + "tft_green3", + "tft_green4", + "tft_green5", + "tft_green6", + "tft_green7", + "tft_blue0", + "tft_blue1", + "tft_blue2", + "tft_blue3", + "tft_blue4", + "tft_blue5", + "tft_blue6", + "tft_blue7", + "tft_vdden_gd", + "tft_panelclk", + "tft_blank_ls", + "tft_vsync_ns", + "tft_hsync_nr", + "tft_vd12acb", + "tft_pwrsave", +}; + +/* Mux functions that can be used by a mux */ + +enum tz1090_mux { + /* internal placeholder */ + TZ1090_MUX_NA = -1, + /* magic per-non-muxing-GPIO-pin peripheral mode mux */ + TZ1090_MUX_PERIP, + /* SDH/SDIO mux */ + TZ1090_MUX_SDH, + TZ1090_MUX_SDIO, + /* USB_VBUS muxes */ + TZ1090_MUX_SPI1_CS2, + TZ1090_MUX_PDM_DAC, + TZ1090_MUX_USB_VBUS, + /* AFE mux */ + TZ1090_MUX_AFE, + TZ1090_MUX_TS_OUT_0, + /* EXT_DAC mux */ + TZ1090_MUX_DAC, + TZ1090_MUX_NOT_IQADC_STB, + TZ1090_MUX_IQDAC_STB, + /* TFT mux */ + TZ1090_MUX_TFT, + TZ1090_MUX_EXT_DAC, + TZ1090_MUX_TS_OUT_1, + TZ1090_MUX_LCD_TRACE, + TZ1090_MUX_PHY_RINGOSC, +}; + +#define FUNCTION(mux, fname, group) \ + [(TZ1090_MUX_ ## mux)] = { \ + .name = #fname, \ + .groups = group##_groups, \ + .ngroups = ARRAY_SIZE(group##_groups), \ + } +/* For intermediate functions with submuxes */ +#define NULL_FUNCTION(mux, fname) \ + [(TZ1090_MUX_ ## mux)] = { \ + .name = #fname, \ + } + +/* Must correlate with enum tz1090_mux */ +static const struct tz1090_function tz1090_functions[] = { + /* FUNCTION function name pingroups */ + FUNCTION(PERIP, perip, perip), + FUNCTION(SDH, sdh, sdh_sdio), + FUNCTION(SDIO, sdio, sdh_sdio), + FUNCTION(SPI1_CS2, spi1_cs2, spi1_cs2), + FUNCTION(PDM_DAC, pdm_dac, pdm_dac), + FUNCTION(USB_VBUS, usb_vbus, usb_vbus), + FUNCTION(AFE, afe, afe), + FUNCTION(TS_OUT_0, ts_out_0, afe), + FUNCTION(DAC, ext_dac, tft), + FUNCTION(NOT_IQADC_STB, not_iqadc_stb, tft), + FUNCTION(IQDAC_STB, iqdac_stb, tft), + FUNCTION(TFT, tft, tft), + NULL_FUNCTION(EXT_DAC, _ext_dac), + FUNCTION(TS_OUT_1, ts_out_1, tft), + FUNCTION(LCD_TRACE, lcd_trace, tft), + FUNCTION(PHY_RINGOSC, phy_ringosc, tft), +}; + +/* Sub muxes */ + +/** + * MUX() - Initialise a mux description. + * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) + * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) + * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) + * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) + * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) + * @mux_r: Mux register (REG_PINCTRL_ is prepended) + * @mux_b: Bit number in register that the mux field begins + * @mux_w: Width of mux field in register + */ +#define MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \ + { \ + .funcs = { \ + TZ1090_MUX_ ## f0, \ + TZ1090_MUX_ ## f1, \ + TZ1090_MUX_ ## f2, \ + TZ1090_MUX_ ## f3, \ + TZ1090_MUX_ ## f4, \ + }, \ + .reg = (REG_PINCTRL_ ## mux_r), \ + .bit = (mux_b), \ + .width = (mux_w), \ + } + +/** + * DEFINE_SUBMUX() - Defines a submux description separate from a pin group. + * @mux: Mux name (_submux is appended) + * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) + * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) + * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) + * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) + * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) + * @mux_r: Mux register (REG_PINCTRL_ is prepended) + * @mux_b: Bit number in register that the mux field begins + * @mux_w: Width of mux field in register + * + * A sub mux is a nested mux that can be bound to a magic function number used + * by another mux description. For example value 4 of the top level mux might + * correspond to a function which has a submux pointed to in tz1090_submux[]. + * The outer mux can then take on any function in the top level mux or the + * submux, and if a submux function is chosen both muxes are updated to route + * the signal from the submux. + * + * The submux can be defined with DEFINE_SUBMUX and pointed to from + * tz1090_submux[] using SUBMUX. + */ +#define DEFINE_SUBMUX(mux, f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \ + static struct tz1090_muxdesc mux ## _submux = \ + MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) + +/** + * SUBMUX() - Link a submux to a function number. + * @f: Function name (TZ1090_MUX_ is prepended) + * @submux: Submux name (_submux is appended) + * + * For use in tz1090_submux[] initialisation to link an intermediate function + * number to a particular submux description. It indicates that when the + * function is chosen the signal is connected to the submux. + */ +#define SUBMUX(f, submux) [(TZ1090_MUX_ ## f)] = &(submux ## _submux) + +/** + * MUX_PG() - Initialise a pin group with mux control + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) + * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) + * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) + * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) + * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) + * @mux_r: Mux register (REG_PINCTRL_ is prepended) + * @mux_b: Bit number in register that the mux field begins + * @mux_w: Width of mux field in register + */ +#define MUX_PG(pg_name, f0, f1, f2, f3, f4, \ + mux_r, mux_b, mux_w) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .mux = MUX(f0, f1, f2, f3, f4, \ + mux_r, mux_b, mux_w), \ + } + +/** + * SIMPLE_PG() - Initialise a simple convenience pin group + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + * + * A simple pin group is simply used for binding pins together so they can be + * referred to by a single name instead of having to list every pin + * individually. + */ +#define SIMPLE_PG(pg_name) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + } + +/** + * DRV_PG() - Initialise a pin group with drive control + * @pg_name: Pin group name (stringified, _pins appended to get pins array) + * @slw_b: Slew register bit. + * The same bit is used for Schmitt, and Drive (*2). + */ +#define DRV_PG(pg_name, slw_b) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .drv = true, \ + .slw_bit = (slw_b), \ + } + +/* + * Define main muxing pin groups + */ + +/* submuxes */ + +/* name f0, f1, f2, f3, f4, mux r/b/w */ +DEFINE_SUBMUX(ext_dac, DAC, NOT_IQADC_STB, IQDAC_STB, NA, NA, IF_CTL, 6, 2); + +/* bind submuxes to internal functions */ +static struct tz1090_muxdesc *tz1090_submux[] = { + SUBMUX(EXT_DAC, ext_dac), +}; + +/* + * These are the pin mux groups. Pin muxing can be enabled and disabled for each + * pin individually so these groups are internal. The mapping of pins to pin mux + * group is below (tz1090_mux_pins). + */ +static struct tz1090_pingroup tz1090_mux_groups[] = { + /* Muxing pin groups */ + /* pg_name, f0, f1, f2, f3, f4, mux r/b/w */ + MUX_PG(sdh, SDH, SDIO, NA, NA, NA, IF_CTL, 20, 2), + MUX_PG(sdio, SDIO, SDH, NA, NA, NA, IF_CTL, 16, 2), + MUX_PG(spi1_cs2, SPI1_CS2, USB_VBUS, NA, NA, NA, IF_CTL, 10, 2), + MUX_PG(pdm_d, PDM_DAC, USB_VBUS, NA, NA, NA, IF_CTL, 8, 2), + MUX_PG(afe, AFE, TS_OUT_0, NA, NA, NA, IF_CTL, 4, 2), + MUX_PG(tft, TFT, EXT_DAC, TS_OUT_1, LCD_TRACE, PHY_RINGOSC, IF_CTL, 0, 3), +}; + +/* + * This is the mapping from GPIO pins to pin mux groups in tz1090_mux_groups[]. + * Pins which aren't muxable to multiple peripherals are set to + * TZ1090_MUX_GROUP_MAX to enable the "perip" function to enable/disable + * peripheral control of the pin. + * + * This array is initialised in tz1090_init_mux_pins(). + */ +static u8 tz1090_mux_pins[NUM_GPIOS]; + +/* TZ1090_MUX_GROUP_MAX is used in tz1090_mux_pins[] for non-muxing pins */ +#define TZ1090_MUX_GROUP_MAX ARRAY_SIZE(tz1090_mux_groups) + +/** + * tz1090_init_mux_pins() - Initialise GPIO pin to mux group mapping. + * + * Initialises the tz1090_mux_pins[] array to be the inverse of the pin lists in + * each pin mux group in tz1090_mux_groups[]. + * + * It is assumed that no pin mux groups overlap (share pins). + */ +static void __init tz1090_init_mux_pins(void) +{ + unsigned int g, p; + const struct tz1090_pingroup *grp; + const unsigned int *pin; + + for (p = 0; p < NUM_GPIOS; ++p) + tz1090_mux_pins[p] = TZ1090_MUX_GROUP_MAX; + + grp = tz1090_mux_groups; + for (g = 0, grp = tz1090_mux_groups; + g < ARRAY_SIZE(tz1090_mux_groups); ++g, ++grp) + for (pin = grp->pins, p = 0; p < grp->npins; ++p, ++pin) + tz1090_mux_pins[*pin] = g; +} + +/* + * These are the externally visible pin groups. Some of them allow group control + * of drive configuration. Some are just simple convenience pingroups. All the + * internal pin mux groups in tz1090_mux_groups[] are mirrored here with the + * same pins. + * Pseudo pin groups follow in the group numbers after this array for each GPIO + * pin. Any group used for muxing must have all pins belonging to the same pin + * mux group. + */ +static struct tz1090_pingroup tz1090_groups[] = { + /* Pin groups with drive control (with no out of place pins) */ + /* pg_name, slw/schmitt/drv b */ + DRV_PG(jtag, 11 /* 11, 22 */), + DRV_PG(tft, 10 /* 10, 20 */), + DRV_PG(scb2, 9 /* 9, 18 */), + DRV_PG(spi0, 7 /* 7, 14 */), + DRV_PG(uart, 5 /* 5, 10 */), + DRV_PG(scb1, 4 /* 4, 8 */), + DRV_PG(spi1, 3 /* 3, 6 */), + DRV_PG(afe, 0 /* 0, 0 */), + + /* + * Drive specific pin groups (with odd combinations of pins which makes + * the pin group naming somewhat arbitrary) + */ + /* pg_name, slw/schmitt/drv b */ + DRV_PG(drive_sdio, 8 /* 8, 16 */), /* sdio_* + sdh_* */ + DRV_PG(drive_i2s, 6 /* 6, 12 */), /* i2s_* + clk_out1 */ + DRV_PG(drive_scb0, 2 /* 2, 4 */), /* scb0_* + pdm_{c,d} */ + DRV_PG(drive_pdm, 1 /* 1, 2 */), /* pdm_{a,b} + clk_out0 */ + + /* Convenience pin groups */ + /* pg_name */ + SIMPLE_PG(uart0), + SIMPLE_PG(uart1), + SIMPLE_PG(scb0), + SIMPLE_PG(i2s), + SIMPLE_PG(sdh), + SIMPLE_PG(sdio), + + /* pseudo-pingroups for each GPIO pin follow */ +}; + +/** + * struct tz1090_pmx - Private pinctrl data + * @dev: Platform device + * @pctl: Pin control device + * @regs: Register region + * @lock: Lock protecting coherency of pin_en, gpio_en, and SELECT regs + * @pin_en: Pins that have been enabled (32 pins packed into each element) + * @gpio_en: GPIOs that have been enabled (32 pins packed into each element) + */ +struct tz1090_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *regs; + spinlock_t lock; + u32 pin_en[3]; + u32 gpio_en[3]; +}; + +static inline u32 pmx_read(struct tz1090_pmx *pmx, u32 reg) +{ + return ioread32(pmx->regs + reg); +} + +static inline void pmx_write(struct tz1090_pmx *pmx, u32 val, u32 reg) +{ + iowrite32(val, pmx->regs + reg); +} + +/* + * Pin control operations + */ + +/* each GPIO pin has it's own pseudo pingroup containing only itself */ + +static int tz1090_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(tz1090_groups) + NUM_GPIOS; +} + +static const char *tz1090_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + if (group < ARRAY_SIZE(tz1090_groups)) { + /* normal pingroup */ + return tz1090_groups[group].name; + } else { + /* individual gpio pin pseudo-pingroup */ + unsigned int pin = group - ARRAY_SIZE(tz1090_groups); + return tz1090_pins[pin].name; + } +} + +static int tz1090_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + if (group < ARRAY_SIZE(tz1090_groups)) { + /* normal pingroup */ + *pins = tz1090_groups[group].pins; + *num_pins = tz1090_groups[group].npins; + } else { + /* individual gpio pin pseudo-pingroup */ + unsigned int pin = group - ARRAY_SIZE(tz1090_groups); + *pins = &tz1090_pins[pin].number; + *num_pins = 1; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void tz1090_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} +#endif + +static int reserve_map(struct device *dev, struct pinctrl_map **map, + unsigned int *reserved_maps, unsigned int *num_maps, + unsigned int reserve) +{ + unsigned int old_num = *reserved_maps; + unsigned int new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) { + dev_err(dev, "krealloc(map) failed\n"); + return -ENOMEM; + } + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps, + unsigned int *num_maps, const char *group, + const char *function) +{ + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +static int add_map_configs(struct device *dev, + struct pinctrl_map **map, + unsigned int *reserved_maps, unsigned int *num_maps, + const char *group, unsigned long *configs, + unsigned int num_configs) +{ + unsigned long *dup_configs; + + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) { + dev_err(dev, "kmemdup(configs) failed\n"); + return -ENOMEM; + } + + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static void tz1090_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + + kfree(map); +} + +static int tz1090_pinctrl_dt_subnode_to_map(struct device *dev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps) +{ + int ret; + const char *function; + unsigned long *configs = NULL; + unsigned int num_configs = 0; + unsigned int reserve; + struct property *prop; + const char *group; + + ret = of_property_read_string(np, "tz1090,function", &function); + if (ret < 0) { + /* EINVAL=missing, which is fine since it's optional */ + if (ret != -EINVAL) + dev_err(dev, "could not parse property function\n"); + function = NULL; + } + + ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + if (ret) + return ret; + + reserve = 0; + if (function != NULL) + reserve++; + if (num_configs) + reserve++; + ret = of_property_count_strings(np, "tz1090,pins"); + if (ret < 0) { + dev_err(dev, "could not parse property pins\n"); + goto exit; + } + reserve *= ret; + + ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "tz1090,pins", prop, group) { + if (function) { + ret = add_map_mux(map, reserved_maps, num_maps, + group, function); + if (ret < 0) + goto exit; + } + + if (num_configs) { + ret = add_map_configs(dev, map, reserved_maps, + num_maps, group, configs, + num_configs); + if (ret < 0) + goto exit; + } + } + + ret = 0; + +exit: + kfree(configs); + return ret; +} + +static int tz1090_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + unsigned int reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = tz1090_pinctrl_dt_subnode_to_map(pctldev->dev, np, map, + &reserved_maps, + num_maps); + if (ret < 0) { + tz1090_pinctrl_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static struct pinctrl_ops tz1090_pinctrl_ops = { + .get_groups_count = tz1090_pinctrl_get_groups_count, + .get_group_name = tz1090_pinctrl_get_group_name, + .get_group_pins = tz1090_pinctrl_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = tz1090_pinctrl_pin_dbg_show, +#endif + .dt_node_to_map = tz1090_pinctrl_dt_node_to_map, + .dt_free_map = tz1090_pinctrl_dt_free_map, +}; + +/* + * Pin mux operations + */ + +static int tz1090_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(tz1090_functions); +} + +static const char *tz1090_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return tz1090_functions[function].name; +} + +static int tz1090_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const num_groups) +{ + /* pingroup functions */ + *groups = tz1090_functions[function].groups; + *num_groups = tz1090_functions[function].ngroups; + return 0; +} + +/** + * tz1090_pinctrl_select() - update bit in SELECT register + * @pmx: Pinmux data + * @pin: Pin number (must be within GPIO range) + */ +static void tz1090_pinctrl_select(struct tz1090_pmx *pmx, + unsigned int pin) +{ + u32 reg, reg_shift, select, val; + unsigned int pmx_index, pmx_shift; + unsigned long flags; + + /* uses base 32 instead of base 30 */ + pmx_index = pin >> 5; + pmx_shift = pin & 0x1f; + + /* select = !perip || gpio */ + select = ((~pmx->pin_en[pmx_index] | + pmx->gpio_en[pmx_index]) >> pmx_shift) & 1; + + /* find register and bit offset (base 30) */ + reg = REG_PINCTRL_SELECT + 4*(pin / 30); + reg_shift = pin % 30; + + /* modify gpio select bit */ + __global_lock2(flags); + val = pmx_read(pmx, reg); + val &= ~BIT(reg_shift); + val |= select << reg_shift; + pmx_write(pmx, val, reg); + __global_unlock2(flags); +} + +/** + * tz1090_pinctrl_gpio_select() - enable/disable GPIO usage for a pin + * @pmx: Pinmux data + * @pin: Pin number + * @gpio_select: true to enable pin as GPIO, + * false to leave control to whatever function is enabled + * + * Records that GPIO usage is enabled/disabled so that enabling a function + * doesn't override the SELECT register bit. + */ +static void tz1090_pinctrl_gpio_select(struct tz1090_pmx *pmx, + unsigned int pin, + bool gpio_select) +{ + unsigned int index, shift; + u32 gpio_en; + + if (pin >= NUM_GPIOS) + return; + + /* uses base 32 instead of base 30 */ + index = pin >> 5; + shift = pin & 0x1f; + + spin_lock(&pmx->lock); + + /* keep a record whether gpio is selected */ + gpio_en = pmx->gpio_en[index]; + gpio_en &= ~BIT(shift); + if (gpio_select) + gpio_en |= BIT(shift); + pmx->gpio_en[index] = gpio_en; + + /* update the select bit */ + tz1090_pinctrl_select(pmx, pin); + + spin_unlock(&pmx->lock); +} + +/** + * tz1090_pinctrl_perip_select() - enable/disable peripheral interface for a pin + * @pmx: Pinmux data + * @pin: Pin number + * @perip_select: true to enable peripheral interface when not GPIO, + * false to leave pin in GPIO mode + * + * Records that peripheral usage is enabled/disabled so that SELECT register can + * be set appropriately when GPIO is disabled. + */ +static void tz1090_pinctrl_perip_select(struct tz1090_pmx *pmx, + unsigned int pin, + bool perip_select) +{ + unsigned int index, shift; + u32 pin_en; + + if (pin >= NUM_GPIOS) + return; + + /* uses base 32 instead of base 30 */ + index = pin >> 5; + shift = pin & 0x1f; + + spin_lock(&pmx->lock); + + /* keep a record whether peripheral is selected */ + pin_en = pmx->pin_en[index]; + pin_en &= ~BIT(shift); + if (perip_select) + pin_en |= BIT(shift); + pmx->pin_en[index] = pin_en; + + /* update the select bit */ + tz1090_pinctrl_select(pmx, pin); + + spin_unlock(&pmx->lock); +} + +/** + * tz1090_pinctrl_enable_mux() - Switch a pin mux group to a function. + * @pmx: Pinmux data + * @desc: Pinmux description + * @function: Function to switch to + * + * Enable a particular function on a pin mux group. Since pin mux descriptions + * are nested this function is recursive. + */ +static int tz1090_pinctrl_enable_mux(struct tz1090_pmx *pmx, + const struct tz1090_muxdesc *desc, + unsigned int function) +{ + const int *fit; + unsigned long flags; + int mux; + unsigned int func, ret; + u32 reg, mask; + + /* find the mux value for this function, searching recursively */ + for (mux = 0, fit = desc->funcs; + mux < ARRAY_SIZE(desc->funcs); ++mux, ++fit) { + func = *fit; + if (func == function) + goto found_mux; + + /* maybe it's a sub-mux */ + if (func < ARRAY_SIZE(tz1090_submux) && tz1090_submux[func]) { + ret = tz1090_pinctrl_enable_mux(pmx, + tz1090_submux[func], + function); + if (!ret) + goto found_mux; + } + } + + return -EINVAL; +found_mux: + + /* Set up the mux */ + if (desc->width) { + mask = (BIT(desc->width) - 1) << desc->bit; + __global_lock2(flags); + reg = pmx_read(pmx, desc->reg); + reg &= ~mask; + reg |= (mux << desc->bit) & mask; + pmx_write(pmx, reg, desc->reg); + __global_unlock2(flags); + } + + return 0; +} + +/** + * tz1090_pinctrl_enable() - Enable a function on a pin group. + * @pctldev: Pin control data + * @function: Function index to enable + * @group: Group index to enable + * + * Enable a particular function on a group of pins. The per GPIO pin pseudo pin + * groups can be used (in which case the pin will be enabled in peripheral mode + * and if it belongs to a pin mux group the mux will be switched if it isn't + * already in use. Some convenience pin groups can also be used in which case + * the effect is the same as enabling the function on each individual pin in the + * group. + */ +static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct tz1090_pingroup *grp; + int ret; + unsigned int pin_num, mux_group, i, npins; + const unsigned int *pins; + + /* group of pins? */ + if (group < ARRAY_SIZE(tz1090_groups)) { + grp = &tz1090_groups[group]; + npins = grp->npins; + pins = grp->pins; + /* + * All pins in the group must belong to the same mux group, + * which allows us to just use the mux group of the first pin. + * By explicitly listing permitted pingroups for each function + * the pinmux core should ensure this is always the case. + */ + } else { + pin_num = group - ARRAY_SIZE(tz1090_groups); + npins = 1; + pins = &pin_num; + } + mux_group = tz1090_mux_pins[*pins]; + + /* no mux group, but can still be individually muxed to peripheral */ + if (mux_group >= TZ1090_MUX_GROUP_MAX) { + if (function == TZ1090_MUX_PERIP) + goto mux_pins; + return -EINVAL; + } + + /* mux group already set to a different function? */ + grp = &tz1090_mux_groups[mux_group]; + if (grp->func_count && grp->func != function) { + dev_err(pctldev->dev, + "%s: can't mux pin(s) to '%s', group already muxed to '%s'\n", + __func__, tz1090_functions[function].name, + tz1090_functions[grp->func].name); + return -EBUSY; + } + + dev_dbg(pctldev->dev, "%s: muxing %u pin(s) in '%s' to '%s'\n", + __func__, npins, grp->name, tz1090_functions[function].name); + + /* if first pin in mux group to be enabled, enable the group mux */ + if (!grp->func_count) { + grp->func = function; + ret = tz1090_pinctrl_enable_mux(pmx, &grp->mux, function); + if (ret) + return ret; + } + /* add pins to ref count and mux individually to peripheral */ + grp->func_count += npins; +mux_pins: + for (i = 0; i < npins; ++i) + tz1090_pinctrl_perip_select(pmx, pins[i], true); + + return 0; +} + +/** + * tz1090_pinctrl_disable() - Disable a function on a pin group. + * @pctldev: Pin control data + * @function: Function index to disable + * @group: Group index to disable + * + * Disable a particular function on a group of pins. The per GPIO pin pseudo pin + * groups can be used (in which case the pin will be taken out of peripheral + * mode. Some convenience pin groups can also be used in which case the effect + * is the same as enabling the function on each individual pin in the group. + */ +static void tz1090_pinctrl_disable(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct tz1090_pingroup *grp; + unsigned int pin_num, mux_group, i, npins; + const unsigned int *pins; + + /* group of pins? */ + if (group < ARRAY_SIZE(tz1090_groups)) { + grp = &tz1090_groups[group]; + npins = grp->npins; + pins = grp->pins; + /* + * All pins in the group must belong to the same mux group, + * which allows us to just use the mux group of the first pin. + * By explicitly listing permitted pingroups for each function + * the pinmux core should ensure this is always the case. + */ + } else { + pin_num = group - ARRAY_SIZE(tz1090_groups); + npins = 1; + pins = &pin_num; + } + mux_group = tz1090_mux_pins[*pins]; + + /* no mux group, but can still be individually muxed to peripheral */ + if (mux_group >= TZ1090_MUX_GROUP_MAX) { + if (function == TZ1090_MUX_PERIP) + goto unmux_pins; + return; + } + + /* mux group already set to a different function? */ + grp = &tz1090_mux_groups[mux_group]; + dev_dbg(pctldev->dev, "%s: unmuxing %u pin(s) in '%s' from '%s'\n", + __func__, npins, grp->name, tz1090_functions[function].name); + + /* subtract pins from ref count and unmux individually */ + WARN_ON(grp->func_count < npins); + grp->func_count -= npins; +unmux_pins: + for (i = 0; i < npins; ++i) + tz1090_pinctrl_perip_select(pmx, pins[i], false); +} + +/** + * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode. + * @pctldev: Pin control data + * @range: GPIO range + * @pin: Pin number + * + * Puts a particular pin into GPIO mode, disabling peripheral control until it's + * disabled again. + */ +static int tz1090_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + tz1090_pinctrl_gpio_select(pmx, pin, true); + return 0; +} + +/** + * tz1090_pinctrl_gpio_disable_free() - Take pin out of GPIO mode. + * @pctldev: Pin control data + * @range: GPIO range + * @pin: Pin number + * + * Take a particular pin out of GPIO mode. If the pin is enabled for a + * peripheral it will return to peripheral mode. + */ +static void tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + tz1090_pinctrl_gpio_select(pmx, pin, false); +} + +static struct pinmux_ops tz1090_pinmux_ops = { + .get_functions_count = tz1090_pinctrl_get_funcs_count, + .get_function_name = tz1090_pinctrl_get_func_name, + .get_function_groups = tz1090_pinctrl_get_func_groups, + .enable = tz1090_pinctrl_enable, + .disable = tz1090_pinctrl_disable, + .gpio_request_enable = tz1090_pinctrl_gpio_request_enable, + .gpio_disable_free = tz1090_pinctrl_gpio_disable_free, +}; + +/* + * Pin config operations + */ + +struct tz1090_pinconf_pullup { + unsigned char index; + unsigned char shift; +}; + +/* The mapping of pin to pull up/down register index and shift */ +static struct tz1090_pinconf_pullup tz1090_pinconf_pullup[] = { + {5, 22}, /* 0 - TZ1090_PIN_SDIO_CLK */ + {0, 14}, /* 1 - TZ1090_PIN_SDIO_CMD */ + {0, 6}, /* 2 - TZ1090_PIN_SDIO_D0 */ + {0, 8}, /* 3 - TZ1090_PIN_SDIO_D1 */ + {0, 10}, /* 4 - TZ1090_PIN_SDIO_D2 */ + {0, 12}, /* 5 - TZ1090_PIN_SDIO_D3 */ + {0, 2}, /* 6 - TZ1090_PIN_SDH_CD */ + {0, 4}, /* 7 - TZ1090_PIN_SDH_WP */ + {0, 16}, /* 8 - TZ1090_PIN_SPI0_MCLK */ + {0, 18}, /* 9 - TZ1090_PIN_SPI0_CS0 */ + {0, 20}, /* 10 - TZ1090_PIN_SPI0_CS1 */ + {0, 22}, /* 11 - TZ1090_PIN_SPI0_CS2 */ + {0, 24}, /* 12 - TZ1090_PIN_SPI0_DOUT */ + {0, 26}, /* 13 - TZ1090_PIN_SPI0_DIN */ + {0, 28}, /* 14 - TZ1090_PIN_SPI1_MCLK */ + {0, 30}, /* 15 - TZ1090_PIN_SPI1_CS0 */ + {1, 0}, /* 16 - TZ1090_PIN_SPI1_CS1 */ + {1, 2}, /* 17 - TZ1090_PIN_SPI1_CS2 */ + {1, 4}, /* 18 - TZ1090_PIN_SPI1_DOUT */ + {1, 6}, /* 19 - TZ1090_PIN_SPI1_DIN */ + {1, 8}, /* 20 - TZ1090_PIN_UART0_RXD */ + {1, 10}, /* 21 - TZ1090_PIN_UART0_TXD */ + {1, 12}, /* 22 - TZ1090_PIN_UART0_CTS */ + {1, 14}, /* 23 - TZ1090_PIN_UART0_RTS */ + {1, 16}, /* 24 - TZ1090_PIN_UART1_RXD */ + {1, 18}, /* 25 - TZ1090_PIN_UART1_TXD */ + {1, 20}, /* 26 - TZ1090_PIN_SCB0_SDAT */ + {1, 22}, /* 27 - TZ1090_PIN_SCB0_SCLK */ + {1, 24}, /* 28 - TZ1090_PIN_SCB1_SDAT */ + {1, 26}, /* 29 - TZ1090_PIN_SCB1_SCLK */ + + {1, 28}, /* 30 - TZ1090_PIN_SCB2_SDAT */ + {1, 30}, /* 31 - TZ1090_PIN_SCB2_SCLK */ + {2, 0}, /* 32 - TZ1090_PIN_I2S_MCLK */ + {2, 2}, /* 33 - TZ1090_PIN_I2S_BCLK_OUT */ + {2, 4}, /* 34 - TZ1090_PIN_I2S_LRCLK_OUT */ + {2, 6}, /* 35 - TZ1090_PIN_I2S_DOUT0 */ + {2, 8}, /* 36 - TZ1090_PIN_I2S_DOUT1 */ + {2, 10}, /* 37 - TZ1090_PIN_I2S_DOUT2 */ + {2, 12}, /* 38 - TZ1090_PIN_I2S_DIN */ + {4, 12}, /* 39 - TZ1090_PIN_PDM_A */ + {4, 14}, /* 40 - TZ1090_PIN_PDM_B */ + {4, 18}, /* 41 - TZ1090_PIN_PDM_C */ + {4, 20}, /* 42 - TZ1090_PIN_PDM_D */ + {2, 14}, /* 43 - TZ1090_PIN_TFT_RED0 */ + {2, 16}, /* 44 - TZ1090_PIN_TFT_RED1 */ + {2, 18}, /* 45 - TZ1090_PIN_TFT_RED2 */ + {2, 20}, /* 46 - TZ1090_PIN_TFT_RED3 */ + {2, 22}, /* 47 - TZ1090_PIN_TFT_RED4 */ + {2, 24}, /* 48 - TZ1090_PIN_TFT_RED5 */ + {2, 26}, /* 49 - TZ1090_PIN_TFT_RED6 */ + {2, 28}, /* 50 - TZ1090_PIN_TFT_RED7 */ + {2, 30}, /* 51 - TZ1090_PIN_TFT_GREEN0 */ + {3, 0}, /* 52 - TZ1090_PIN_TFT_GREEN1 */ + {3, 2}, /* 53 - TZ1090_PIN_TFT_GREEN2 */ + {3, 4}, /* 54 - TZ1090_PIN_TFT_GREEN3 */ + {3, 6}, /* 55 - TZ1090_PIN_TFT_GREEN4 */ + {3, 8}, /* 56 - TZ1090_PIN_TFT_GREEN5 */ + {3, 10}, /* 57 - TZ1090_PIN_TFT_GREEN6 */ + {3, 12}, /* 58 - TZ1090_PIN_TFT_GREEN7 */ + {3, 14}, /* 59 - TZ1090_PIN_TFT_BLUE0 */ + + {3, 16}, /* 60 - TZ1090_PIN_TFT_BLUE1 */ + {3, 18}, /* 61 - TZ1090_PIN_TFT_BLUE2 */ + {3, 20}, /* 62 - TZ1090_PIN_TFT_BLUE3 */ + {3, 22}, /* 63 - TZ1090_PIN_TFT_BLUE4 */ + {3, 24}, /* 64 - TZ1090_PIN_TFT_BLUE5 */ + {3, 26}, /* 65 - TZ1090_PIN_TFT_BLUE6 */ + {3, 28}, /* 66 - TZ1090_PIN_TFT_BLUE7 */ + {3, 30}, /* 67 - TZ1090_PIN_TFT_VDDEN_GD */ + {4, 0}, /* 68 - TZ1090_PIN_TFT_PANELCLK */ + {4, 2}, /* 69 - TZ1090_PIN_TFT_BLANK_LS */ + {4, 4}, /* 70 - TZ1090_PIN_TFT_VSYNC_NS */ + {4, 6}, /* 71 - TZ1090_PIN_TFT_HSYNC_NR */ + {4, 8}, /* 72 - TZ1090_PIN_TFT_VD12ACB */ + {4, 10}, /* 73 - TZ1090_PIN_TFT_PWRSAVE */ + {4, 24}, /* 74 - TZ1090_PIN_TX_ON */ + {4, 26}, /* 75 - TZ1090_PIN_RX_ON */ + {4, 28}, /* 76 - TZ1090_PIN_PLL_ON */ + {4, 30}, /* 77 - TZ1090_PIN_PA_ON */ + {5, 0}, /* 78 - TZ1090_PIN_RX_HP */ + {5, 6}, /* 79 - TZ1090_PIN_GAIN0 */ + {5, 8}, /* 80 - TZ1090_PIN_GAIN1 */ + {5, 10}, /* 81 - TZ1090_PIN_GAIN2 */ + {5, 12}, /* 82 - TZ1090_PIN_GAIN3 */ + {5, 14}, /* 83 - TZ1090_PIN_GAIN4 */ + {5, 16}, /* 84 - TZ1090_PIN_GAIN5 */ + {5, 18}, /* 85 - TZ1090_PIN_GAIN6 */ + {5, 20}, /* 86 - TZ1090_PIN_GAIN7 */ + {5, 2}, /* 87 - TZ1090_PIN_ANT_SEL0 */ + {5, 4}, /* 88 - TZ1090_PIN_ANT_SEL1 */ + {0, 0}, /* 89 - TZ1090_PIN_SDH_CLK_IN */ + + {5, 24}, /* 90 - TZ1090_PIN_TCK */ + {5, 26}, /* 91 - TZ1090_PIN_TRST */ + {5, 28}, /* 92 - TZ1090_PIN_TDI */ + {5, 30}, /* 93 - TZ1090_PIN_TDO */ + {6, 0}, /* 94 - TZ1090_PIN_TMS */ + {4, 16}, /* 95 - TZ1090_PIN_CLK_OUT0 */ + {4, 22}, /* 96 - TZ1090_PIN_CLK_OUT1 */ +}; + +static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev, + unsigned int pin, + enum pin_config_param param, + bool report_err, + u32 *reg, u32 *width, u32 *mask, u32 *shift, + u32 *val) +{ + struct tz1090_pinconf_pullup *pu; + + /* All supported pins have controllable input bias */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + *val = REG_PU_PD_TRISTATE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *val = REG_PU_PD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + *val = REG_PU_PD_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + *val = REG_PU_PD_REPEATER; + break; + default: + return -ENOTSUPP; + }; + + /* Only input bias parameters supported */ + pu = &tz1090_pinconf_pullup[pin]; + *reg = REG_PINCTRL_PU_PD + 4*pu->index; + *shift = pu->shift; + *width = 2; + + /* Calculate field information */ + *mask = (BIT(*width) - 1) << *shift; + + return 0; +} + +static int tz1090_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + int ret; + u32 reg, width, mask, shift, val, tmp, arg; + + /* Get register information */ + ret = tz1090_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; + + /* Extract field from register */ + tmp = pmx_read(pmx, reg); + arg = ((tmp & mask) >> shift) == val; + + /* Config not active */ + if (!arg) + return -EINVAL; + + /* And pack config */ + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int tz1090_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *configs, + unsigned num_configs) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + unsigned int arg; + int ret; + u32 reg, width, mask, shift, val, tmp; + unsigned long flags; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", + __func__, tz1090_pins[pin].name, configs[i]); + + /* Get register information */ + ret = tz1090_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; + + /* Unpack argument and range check it */ + if (arg > 1) { + dev_dbg(pctldev->dev, "%s: arg %u out of range\n", + __func__, arg); + return -EINVAL; + } + + /* Write register field */ + __global_lock2(flags); + tmp = pmx_read(pmx, reg); + tmp &= ~mask; + if (arg) + tmp |= val << shift; + pmx_write(pmx, tmp, reg); + __global_unlock2(flags); + } /* for each config */ + + return 0; +} + +static const int tz1090_boolean_map[] = { + [0] = -EINVAL, + [1] = 1, +}; + +static const int tz1090_dr_map[] = { + [REG_DR_2mA] = 2, + [REG_DR_4mA] = 4, + [REG_DR_8mA] = 8, + [REG_DR_12mA] = 12, +}; + +static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev, + const struct tz1090_pingroup *g, + enum pin_config_param param, + bool report_err, + u32 *reg, u32 *width, u32 *mask, u32 *shift, + const int **map) +{ + /* Drive configuration applies in groups, but not to all groups. */ + if (!g->drv) { + if (report_err) + dev_dbg(pctldev->dev, + "%s: group %s has no drive control\n", + __func__, g->name); + return -ENOTSUPP; + } + + /* Find information about drive parameter's register */ + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *reg = REG_PINCTRL_SCHMITT; + *width = 1; + *map = tz1090_boolean_map; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + *reg = REG_PINCTRL_DR; + *width = 2; + *map = tz1090_dr_map; + break; + default: + return -ENOTSUPP; + }; + + /* Calculate field information */ + *shift = g->slw_bit * *width; + *mask = (BIT(*width) - 1) << *shift; + + return 0; +} + +static int tz1090_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pingroup *g; + enum pin_config_param param = pinconf_to_config_param(*config); + int ret, arg; + unsigned int pin; + u32 reg, width, mask, shift, val; + const int *map; + + if (group >= ARRAY_SIZE(tz1090_groups)) { + pin = group - ARRAY_SIZE(tz1090_groups); + return tz1090_pinconf_get(pctldev, pin, config); + } + + g = &tz1090_groups[group]; + if (g->npins == 1) { + pin = g->pins[0]; + ret = tz1090_pinconf_get(pctldev, pin, config); + if (ret != -ENOTSUPP) + return ret; + } + + /* Get register information */ + ret = tz1090_pinconf_group_reg(pctldev, g, param, true, + ®, &width, &mask, &shift, &map); + if (ret < 0) + return ret; + + /* Extract field from register */ + val = pmx_read(pmx, reg); + arg = map[(val & mask) >> shift]; + if (arg < 0) + return arg; + + /* And pack config */ + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int tz1090_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *configs, + unsigned num_configs) +{ + struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tz1090_pingroup *g; + enum pin_config_param param; + unsigned int arg, pin, i; + const unsigned int *pit; + int ret; + u32 reg, width, mask, shift, val; + unsigned long flags; + const int *map; + int j; + + if (group >= ARRAY_SIZE(tz1090_groups)) { + pin = group - ARRAY_SIZE(tz1090_groups); + return tz1090_pinconf_set(pctldev, pin, configs, num_configs); + } + + g = &tz1090_groups[group]; + if (g->npins == 1) { + pin = g->pins[0]; + ret = tz1090_pinconf_set(pctldev, pin, configs, num_configs); + if (ret != -ENOTSUPP) + return ret; + } + + for (j = 0; j < num_configs; j++) { + param = pinconf_to_config_param(configs[j]); + + dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", + __func__, g->name, configs[j]); + + /* Get register information */ + ret = tz1090_pinconf_group_reg(pctldev, g, param, true, ®, + &width, &mask, &shift, &map); + if (ret < 0) { + /* + * Maybe we're trying to set a per-pin configuration + * of a group, so do the pins one by one. This is + * mainly as a convenience. + */ + for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { + ret = tz1090_pinconf_set(pctldev, *pit, configs, + num_configs); + if (ret) + return ret; + } + return 0; + } + + /* Unpack argument and map it to register value */ + arg = pinconf_to_config_argument(configs[j]); + for (i = 0; i < BIT(width); ++i) { + if (map[i] == arg || (map[i] == -EINVAL && !arg)) { + /* Write register field */ + __global_lock2(flags); + val = pmx_read(pmx, reg); + val &= ~mask; + val |= i << shift; + pmx_write(pmx, val, reg); + __global_unlock2(flags); + goto next_config; + } + } + + dev_dbg(pctldev->dev, "%s: arg %u not supported\n", + __func__, arg); + return -EINVAL; + +next_config: + ; + } /* for each config */ + + return 0; +} + +static struct pinconf_ops tz1090_pinconf_ops = { + .is_generic = true, + .pin_config_get = tz1090_pinconf_get, + .pin_config_set = tz1090_pinconf_set, + .pin_config_group_get = tz1090_pinconf_group_get, + .pin_config_group_set = tz1090_pinconf_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +/* + * Pin control driver setup + */ + +static struct pinctrl_desc tz1090_pinctrl_desc = { + .pctlops = &tz1090_pinctrl_ops, + .pmxops = &tz1090_pinmux_ops, + .confops = &tz1090_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int tz1090_pinctrl_probe(struct platform_device *pdev) +{ + struct tz1090_pmx *pmx; + struct resource *res; + + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) { + dev_err(&pdev->dev, "Can't alloc tz1090_pmx\n"); + return -ENOMEM; + } + pmx->dev = &pdev->dev; + spin_lock_init(&pmx->lock); + + tz1090_pinctrl_desc.name = dev_name(&pdev->dev); + tz1090_pinctrl_desc.pins = tz1090_pins; + tz1090_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pins); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pmx->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmx->regs)) + return PTR_ERR(pmx->regs); + + pmx->pctl = pinctrl_register(&tz1090_pinctrl_desc, &pdev->dev, pmx); + if (!pmx->pctl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + + platform_set_drvdata(pdev, pmx); + + dev_info(&pdev->dev, "TZ1090 pinctrl driver initialised\n"); + + return 0; +} + +static int tz1090_pinctrl_remove(struct platform_device *pdev) +{ + struct tz1090_pmx *pmx = platform_get_drvdata(pdev); + + pinctrl_unregister(pmx->pctl); + + return 0; +} + +static struct of_device_id tz1090_pinctrl_of_match[] = { + { .compatible = "img,tz1090-pinctrl", }, + { }, +}; + +static struct platform_driver tz1090_pinctrl_driver = { + .driver = { + .name = "tz1090-pinctrl", + .owner = THIS_MODULE, + .of_match_table = tz1090_pinctrl_of_match, + }, + .probe = tz1090_pinctrl_probe, + .remove = tz1090_pinctrl_remove, +}; + +static int __init tz1090_pinctrl_init(void) +{ + tz1090_init_mux_pins(); + return platform_driver_register(&tz1090_pinctrl_driver); +} +arch_initcall(tz1090_pinctrl_init); + +static void __exit tz1090_pinctrl_exit(void) +{ + platform_driver_unregister(&tz1090_pinctrl_driver); +} +module_exit(tz1090_pinctrl_exit); + +MODULE_AUTHOR("Imagination Technologies Ltd."); +MODULE_DESCRIPTION("Toumaz Xenif TZ1090 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, tz1090_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index 6a3a7503e6a..209a01b8bd3 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -1027,21 +1027,23 @@ static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, } static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) + unsigned long *configs, unsigned num_configs) { struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pctldev, pin); - int ret; + int ret, i; if (!range) return -EINVAL; - /* Note: none of these configurations take any argument */ - ret = u300_gpio_config_set(range->gc, - (pin - range->pin_base + range->base), - pinconf_to_config_param(config)); - if (ret) - return ret; + for (i = 0; i < num_configs; i++) { + /* Note: none of these configurations take any argument */ + ret = u300_gpio_config_set(range->gc, + (pin - range->pin_base + range->base), + pinconf_to_config_param(configs[i])); + if (ret) + return ret; + } /* for each config */ return 0; } @@ -1075,9 +1077,6 @@ static int u300_pmx_probe(struct platform_device *pdev) upmx->dev = &pdev->dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENOENT; - upmx->virtbase = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(upmx->virtbase)) return PTR_ERR(upmx->virtbase); @@ -1100,15 +1099,21 @@ static int u300_pmx_remove(struct platform_device *pdev) struct u300_pmx *upmx = platform_get_drvdata(pdev); pinctrl_unregister(upmx->pctl); - platform_set_drvdata(pdev, NULL); return 0; } +static const struct of_device_id u300_pinctrl_match[] = { + { .compatible = "stericsson,pinctrl-u300" }, + {}, +}; + + static struct platform_driver u300_pmx_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, + .of_match_table = u300_pinctrl_match, }, .probe = u300_pmx_probe, .remove = u300_pmx_remove, diff --git a/drivers/pinctrl/pinctrl-utils.c b/drivers/pinctrl/pinctrl-utils.c new file mode 100644 index 00000000000..d77693f2cc1 --- /dev/null +++ b/drivers/pinctrl/pinctrl-utils.c @@ -0,0 +1,142 @@ +/* + * Utils functions to implement the pincontrol driver. + * + * Copyright (c) 2013, NVIDIA Corporation. + * + * Author: Laxman Dewangan <ldewangan@nvidia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ +#include <linux/device.h> +#include <linux/export.h> +#include <linux/kernel.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/of.h> +#include <linux/slab.h> +#include "core.h" +#include "pinctrl-utils.h" + +int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, unsigned reserve) +{ + unsigned old_num = *reserved_maps; + unsigned new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) { + dev_err(pctldev->dev, "krealloc(map) failed\n"); + return -ENOMEM; + } + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_utils_reserve_map); + +int pinctrl_utils_add_map_mux(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, const char *group, + const char *function) +{ + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_utils_add_map_mux); + +int pinctrl_utils_add_map_configs(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, const char *group, + unsigned long *configs, unsigned num_configs, + enum pinctrl_map_type type) +{ + unsigned long *dup_configs; + + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) { + dev_err(pctldev->dev, "kmemdup(configs) failed\n"); + return -ENOMEM; + } + + (*map)[*num_maps].type = type; + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_utils_add_map_configs); + +int pinctrl_utils_add_config(struct pinctrl_dev *pctldev, + unsigned long **configs, unsigned *num_configs, + unsigned long config) +{ + unsigned old_num = *num_configs; + unsigned new_num = old_num + 1; + unsigned long *new_configs; + + new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, + GFP_KERNEL); + if (!new_configs) { + dev_err(pctldev->dev, "krealloc(configs) failed\n"); + return -ENOMEM; + } + + new_configs[old_num] = config; + + *configs = new_configs; + *num_configs = new_num; + + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_utils_add_config); + +void pinctrl_utils_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) { + switch (map[i].type) { + case PIN_MAP_TYPE_CONFIGS_GROUP: + case PIN_MAP_TYPE_CONFIGS_PIN: + kfree(map[i].data.configs.configs); + break; + default: + break; + } + } + kfree(map); +} +EXPORT_SYMBOL_GPL(pinctrl_utils_dt_free_map); diff --git a/drivers/pinctrl/pinctrl-utils.h b/drivers/pinctrl/pinctrl-utils.h new file mode 100644 index 00000000000..d0ffe1ce200 --- /dev/null +++ b/drivers/pinctrl/pinctrl-utils.h @@ -0,0 +1,43 @@ +/* + * Utils functions to implement the pincontrol driver. + * + * Copyright (c) 2013, NVIDIA Corporation. + * + * Author: Laxman Dewangan <ldewangan@nvidia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ +#ifndef __PINCTRL_UTILS_H__ +#define __PINCTRL_UTILS_H__ + +int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, unsigned reserve); +int pinctrl_utils_add_map_mux(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, const char *group, + const char *function); +int pinctrl_utils_add_map_configs(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, const char *group, + unsigned long *configs, unsigned num_configs, + enum pinctrl_map_type type); +int pinctrl_utils_add_config(struct pinctrl_dev *pctldev, + unsigned long **configs, unsigned *num_configs, + unsigned long config); +void pinctrl_utils_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps); + +#endif /* __PINCTRL_UTILS_H__ */ diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/pinctrl-vf610.c new file mode 100644 index 00000000000..bddd913d28b --- /dev/null +++ b/drivers/pinctrl/pinctrl-vf610.c @@ -0,0 +1,338 @@ +/* + * VF610 pinctrl driver based on imx pinmux and pinconf core + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum vf610_pads { + VF610_PAD_PTA6 = 0, + VF610_PAD_PTA8 = 1, + VF610_PAD_PTA9 = 2, + VF610_PAD_PTA10 = 3, + VF610_PAD_PTA11 = 4, + VF610_PAD_PTA12 = 5, + VF610_PAD_PTA16 = 6, + VF610_PAD_PTA17 = 7, + VF610_PAD_PTA18 = 8, + VF610_PAD_PTA19 = 9, + VF610_PAD_PTA20 = 10, + VF610_PAD_PTA21 = 11, + VF610_PAD_PTA22 = 12, + VF610_PAD_PTA23 = 13, + VF610_PAD_PTA24 = 14, + VF610_PAD_PTA25 = 15, + VF610_PAD_PTA26 = 16, + VF610_PAD_PTA27 = 17, + VF610_PAD_PTA28 = 18, + VF610_PAD_PTA29 = 19, + VF610_PAD_PTA30 = 20, + VF610_PAD_PTA31 = 21, + VF610_PAD_PTB0 = 22, + VF610_PAD_PTB1 = 23, + VF610_PAD_PTB2 = 24, + VF610_PAD_PTB3 = 25, + VF610_PAD_PTB4 = 26, + VF610_PAD_PTB5 = 27, + VF610_PAD_PTB6 = 28, + VF610_PAD_PTB7 = 29, + VF610_PAD_PTB8 = 30, + VF610_PAD_PTB9 = 31, + VF610_PAD_PTB10 = 32, + VF610_PAD_PTB11 = 33, + VF610_PAD_PTB12 = 34, + VF610_PAD_PTB13 = 35, + VF610_PAD_PTB14 = 36, + VF610_PAD_PTB15 = 37, + VF610_PAD_PTB16 = 38, + VF610_PAD_PTB17 = 39, + VF610_PAD_PTB18 = 40, + VF610_PAD_PTB19 = 41, + VF610_PAD_PTB20 = 42, + VF610_PAD_PTB21 = 43, + VF610_PAD_PTB22 = 44, + VF610_PAD_PTC0 = 45, + VF610_PAD_PTC1 = 46, + VF610_PAD_PTC2 = 47, + VF610_PAD_PTC3 = 48, + VF610_PAD_PTC4 = 49, + VF610_PAD_PTC5 = 50, + VF610_PAD_PTC6 = 51, + VF610_PAD_PTC7 = 52, + VF610_PAD_PTC8 = 53, + VF610_PAD_PTC9 = 54, + VF610_PAD_PTC10 = 55, + VF610_PAD_PTC11 = 56, + VF610_PAD_PTC12 = 57, + VF610_PAD_PTC13 = 58, + VF610_PAD_PTC14 = 59, + VF610_PAD_PTC15 = 60, + VF610_PAD_PTC16 = 61, + VF610_PAD_PTC17 = 62, + VF610_PAD_PTD31 = 63, + VF610_PAD_PTD30 = 64, + VF610_PAD_PTD29 = 65, + VF610_PAD_PTD28 = 66, + VF610_PAD_PTD27 = 67, + VF610_PAD_PTD26 = 68, + VF610_PAD_PTD25 = 69, + VF610_PAD_PTD24 = 70, + VF610_PAD_PTD23 = 71, + VF610_PAD_PTD22 = 72, + VF610_PAD_PTD21 = 73, + VF610_PAD_PTD20 = 74, + VF610_PAD_PTD19 = 75, + VF610_PAD_PTD18 = 76, + VF610_PAD_PTD17 = 77, + VF610_PAD_PTD16 = 78, + VF610_PAD_PTD0 = 79, + VF610_PAD_PTD1 = 80, + VF610_PAD_PTD2 = 81, + VF610_PAD_PTD3 = 82, + VF610_PAD_PTD4 = 83, + VF610_PAD_PTD5 = 84, + VF610_PAD_PTD6 = 85, + VF610_PAD_PTD7 = 86, + VF610_PAD_PTD8 = 87, + VF610_PAD_PTD9 = 88, + VF610_PAD_PTD10 = 89, + VF610_PAD_PTD11 = 90, + VF610_PAD_PTD12 = 91, + VF610_PAD_PTD13 = 92, + VF610_PAD_PTB23 = 93, + VF610_PAD_PTB24 = 94, + VF610_PAD_PTB25 = 95, + VF610_PAD_PTB26 = 96, + VF610_PAD_PTB27 = 97, + VF610_PAD_PTB28 = 98, + VF610_PAD_PTC26 = 99, + VF610_PAD_PTC27 = 100, + VF610_PAD_PTC28 = 101, + VF610_PAD_PTC29 = 102, + VF610_PAD_PTC30 = 103, + VF610_PAD_PTC31 = 104, + VF610_PAD_PTE0 = 105, + VF610_PAD_PTE1 = 106, + VF610_PAD_PTE2 = 107, + VF610_PAD_PTE3 = 108, + VF610_PAD_PTE4 = 109, + VF610_PAD_PTE5 = 110, + VF610_PAD_PTE6 = 111, + VF610_PAD_PTE7 = 112, + VF610_PAD_PTE8 = 113, + VF610_PAD_PTE9 = 114, + VF610_PAD_PTE10 = 115, + VF610_PAD_PTE11 = 116, + VF610_PAD_PTE12 = 117, + VF610_PAD_PTE13 = 118, + VF610_PAD_PTE14 = 119, + VF610_PAD_PTE15 = 120, + VF610_PAD_PTE16 = 121, + VF610_PAD_PTE17 = 122, + VF610_PAD_PTE18 = 123, + VF610_PAD_PTE19 = 124, + VF610_PAD_PTE20 = 125, + VF610_PAD_PTE21 = 126, + VF610_PAD_PTE22 = 127, + VF610_PAD_PTE23 = 128, + VF610_PAD_PTE24 = 129, + VF610_PAD_PTE25 = 130, + VF610_PAD_PTE26 = 131, + VF610_PAD_PTE27 = 132, + VF610_PAD_PTE28 = 133, + VF610_PAD_PTA7 = 134, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = { + IMX_PINCTRL_PIN(VF610_PAD_PTA6), + IMX_PINCTRL_PIN(VF610_PAD_PTA8), + IMX_PINCTRL_PIN(VF610_PAD_PTA9), + IMX_PINCTRL_PIN(VF610_PAD_PTA10), + IMX_PINCTRL_PIN(VF610_PAD_PTA11), + IMX_PINCTRL_PIN(VF610_PAD_PTA12), + IMX_PINCTRL_PIN(VF610_PAD_PTA16), + IMX_PINCTRL_PIN(VF610_PAD_PTA17), + IMX_PINCTRL_PIN(VF610_PAD_PTA18), + IMX_PINCTRL_PIN(VF610_PAD_PTA19), + IMX_PINCTRL_PIN(VF610_PAD_PTA20), + IMX_PINCTRL_PIN(VF610_PAD_PTA21), + IMX_PINCTRL_PIN(VF610_PAD_PTA22), + IMX_PINCTRL_PIN(VF610_PAD_PTA23), + IMX_PINCTRL_PIN(VF610_PAD_PTA24), + IMX_PINCTRL_PIN(VF610_PAD_PTA25), + IMX_PINCTRL_PIN(VF610_PAD_PTA26), + IMX_PINCTRL_PIN(VF610_PAD_PTA27), + IMX_PINCTRL_PIN(VF610_PAD_PTA28), + IMX_PINCTRL_PIN(VF610_PAD_PTA29), + IMX_PINCTRL_PIN(VF610_PAD_PTA30), + IMX_PINCTRL_PIN(VF610_PAD_PTA31), + IMX_PINCTRL_PIN(VF610_PAD_PTB0), + IMX_PINCTRL_PIN(VF610_PAD_PTB1), + IMX_PINCTRL_PIN(VF610_PAD_PTB2), + IMX_PINCTRL_PIN(VF610_PAD_PTB3), + IMX_PINCTRL_PIN(VF610_PAD_PTB4), + IMX_PINCTRL_PIN(VF610_PAD_PTB5), + IMX_PINCTRL_PIN(VF610_PAD_PTB6), + IMX_PINCTRL_PIN(VF610_PAD_PTB7), + IMX_PINCTRL_PIN(VF610_PAD_PTB8), + IMX_PINCTRL_PIN(VF610_PAD_PTB9), + IMX_PINCTRL_PIN(VF610_PAD_PTB10), + IMX_PINCTRL_PIN(VF610_PAD_PTB11), + IMX_PINCTRL_PIN(VF610_PAD_PTB12), + IMX_PINCTRL_PIN(VF610_PAD_PTB13), + IMX_PINCTRL_PIN(VF610_PAD_PTB14), + IMX_PINCTRL_PIN(VF610_PAD_PTB15), + IMX_PINCTRL_PIN(VF610_PAD_PTB16), + IMX_PINCTRL_PIN(VF610_PAD_PTB17), + IMX_PINCTRL_PIN(VF610_PAD_PTB18), + IMX_PINCTRL_PIN(VF610_PAD_PTB19), + IMX_PINCTRL_PIN(VF610_PAD_PTB20), + IMX_PINCTRL_PIN(VF610_PAD_PTB21), + IMX_PINCTRL_PIN(VF610_PAD_PTB22), + IMX_PINCTRL_PIN(VF610_PAD_PTC0), + IMX_PINCTRL_PIN(VF610_PAD_PTC1), + IMX_PINCTRL_PIN(VF610_PAD_PTC2), + IMX_PINCTRL_PIN(VF610_PAD_PTC3), + IMX_PINCTRL_PIN(VF610_PAD_PTC4), + IMX_PINCTRL_PIN(VF610_PAD_PTC5), + IMX_PINCTRL_PIN(VF610_PAD_PTC6), + IMX_PINCTRL_PIN(VF610_PAD_PTC7), + IMX_PINCTRL_PIN(VF610_PAD_PTC8), + IMX_PINCTRL_PIN(VF610_PAD_PTC9), + IMX_PINCTRL_PIN(VF610_PAD_PTC10), + IMX_PINCTRL_PIN(VF610_PAD_PTC11), + IMX_PINCTRL_PIN(VF610_PAD_PTC12), + IMX_PINCTRL_PIN(VF610_PAD_PTC13), + IMX_PINCTRL_PIN(VF610_PAD_PTC14), + IMX_PINCTRL_PIN(VF610_PAD_PTC15), + IMX_PINCTRL_PIN(VF610_PAD_PTC16), + IMX_PINCTRL_PIN(VF610_PAD_PTC17), + IMX_PINCTRL_PIN(VF610_PAD_PTD31), + IMX_PINCTRL_PIN(VF610_PAD_PTD30), + IMX_PINCTRL_PIN(VF610_PAD_PTD29), + IMX_PINCTRL_PIN(VF610_PAD_PTD28), + IMX_PINCTRL_PIN(VF610_PAD_PTD27), + IMX_PINCTRL_PIN(VF610_PAD_PTD26), + IMX_PINCTRL_PIN(VF610_PAD_PTD25), + IMX_PINCTRL_PIN(VF610_PAD_PTD24), + IMX_PINCTRL_PIN(VF610_PAD_PTD23), + IMX_PINCTRL_PIN(VF610_PAD_PTD22), + IMX_PINCTRL_PIN(VF610_PAD_PTD21), + IMX_PINCTRL_PIN(VF610_PAD_PTD20), + IMX_PINCTRL_PIN(VF610_PAD_PTD19), + IMX_PINCTRL_PIN(VF610_PAD_PTD18), + IMX_PINCTRL_PIN(VF610_PAD_PTD17), + IMX_PINCTRL_PIN(VF610_PAD_PTD16), + IMX_PINCTRL_PIN(VF610_PAD_PTD0), + IMX_PINCTRL_PIN(VF610_PAD_PTD1), + IMX_PINCTRL_PIN(VF610_PAD_PTD2), + IMX_PINCTRL_PIN(VF610_PAD_PTD3), + IMX_PINCTRL_PIN(VF610_PAD_PTD4), + IMX_PINCTRL_PIN(VF610_PAD_PTD5), + IMX_PINCTRL_PIN(VF610_PAD_PTD6), + IMX_PINCTRL_PIN(VF610_PAD_PTD7), + IMX_PINCTRL_PIN(VF610_PAD_PTD8), + IMX_PINCTRL_PIN(VF610_PAD_PTD9), + IMX_PINCTRL_PIN(VF610_PAD_PTD10), + IMX_PINCTRL_PIN(VF610_PAD_PTD11), + IMX_PINCTRL_PIN(VF610_PAD_PTD12), + IMX_PINCTRL_PIN(VF610_PAD_PTD13), + IMX_PINCTRL_PIN(VF610_PAD_PTB23), + IMX_PINCTRL_PIN(VF610_PAD_PTB24), + IMX_PINCTRL_PIN(VF610_PAD_PTB25), + IMX_PINCTRL_PIN(VF610_PAD_PTB26), + IMX_PINCTRL_PIN(VF610_PAD_PTB27), + IMX_PINCTRL_PIN(VF610_PAD_PTB28), + IMX_PINCTRL_PIN(VF610_PAD_PTC26), + IMX_PINCTRL_PIN(VF610_PAD_PTC27), + IMX_PINCTRL_PIN(VF610_PAD_PTC28), + IMX_PINCTRL_PIN(VF610_PAD_PTC29), + IMX_PINCTRL_PIN(VF610_PAD_PTC30), + IMX_PINCTRL_PIN(VF610_PAD_PTC31), + IMX_PINCTRL_PIN(VF610_PAD_PTE0), + IMX_PINCTRL_PIN(VF610_PAD_PTE1), + IMX_PINCTRL_PIN(VF610_PAD_PTE2), + IMX_PINCTRL_PIN(VF610_PAD_PTE3), + IMX_PINCTRL_PIN(VF610_PAD_PTE4), + IMX_PINCTRL_PIN(VF610_PAD_PTE5), + IMX_PINCTRL_PIN(VF610_PAD_PTE6), + IMX_PINCTRL_PIN(VF610_PAD_PTE7), + IMX_PINCTRL_PIN(VF610_PAD_PTE8), + IMX_PINCTRL_PIN(VF610_PAD_PTE9), + IMX_PINCTRL_PIN(VF610_PAD_PTE10), + IMX_PINCTRL_PIN(VF610_PAD_PTE11), + IMX_PINCTRL_PIN(VF610_PAD_PTE12), + IMX_PINCTRL_PIN(VF610_PAD_PTE13), + IMX_PINCTRL_PIN(VF610_PAD_PTE14), + IMX_PINCTRL_PIN(VF610_PAD_PTE15), + IMX_PINCTRL_PIN(VF610_PAD_PTE16), + IMX_PINCTRL_PIN(VF610_PAD_PTE17), + IMX_PINCTRL_PIN(VF610_PAD_PTE18), + IMX_PINCTRL_PIN(VF610_PAD_PTE19), + IMX_PINCTRL_PIN(VF610_PAD_PTE20), + IMX_PINCTRL_PIN(VF610_PAD_PTE21), + IMX_PINCTRL_PIN(VF610_PAD_PTE22), + IMX_PINCTRL_PIN(VF610_PAD_PTE23), + IMX_PINCTRL_PIN(VF610_PAD_PTE24), + IMX_PINCTRL_PIN(VF610_PAD_PTE25), + IMX_PINCTRL_PIN(VF610_PAD_PTE26), + IMX_PINCTRL_PIN(VF610_PAD_PTE27), + IMX_PINCTRL_PIN(VF610_PAD_PTE28), + IMX_PINCTRL_PIN(VF610_PAD_PTA7), +}; + +static struct imx_pinctrl_soc_info vf610_pinctrl_info = { + .pins = vf610_pinctrl_pads, + .npins = ARRAY_SIZE(vf610_pinctrl_pads), + .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, +}; + +static struct of_device_id vf610_pinctrl_of_match[] = { + { .compatible = "fsl,vf610-iomuxc", }, + { /* sentinel */ } +}; + +static int vf610_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &vf610_pinctrl_info); +} + +static struct platform_driver vf610_pinctrl_driver = { + .driver = { + .name = "vf610-pinctrl", + .owner = THIS_MODULE, + .of_match_table = vf610_pinctrl_of_match, + }, + .probe = vf610_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init vf610_pinctrl_init(void) +{ + return platform_driver_register(&vf610_pinctrl_driver); +} +arch_initcall(vf610_pinctrl_init); + +static void __exit vf610_pinctrl_exit(void) +{ + platform_driver_unregister(&vf610_pinctrl_driver); +} +module_exit(vf610_pinctrl_exit); + +MODULE_DESCRIPTION("Freescale VF610 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index f2977cff836..e66f4cae763 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -102,6 +102,7 @@ enum xway_mux { XWAY_MUX_EPHY, XWAY_MUX_DFE, XWAY_MUX_SDIO, + XWAY_MUX_GPHY, XWAY_MUX_NONE = 0xffff, }; @@ -109,12 +110,12 @@ static const struct ltq_mfp_pin xway_mfp[] = { /* pin f0 f1 f2 f3 */ MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM), MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE), - MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE), + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY), MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI), MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC), - MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE), + MFP_XWAY(GPIO5, GPIO, STP, NONE, GPHY), MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), - MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE), + MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY), MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN), MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE), @@ -151,10 +152,10 @@ static const struct ltq_mfp_pin xway_mfp[] = { MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), - MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN), - MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN), + MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN), MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), - MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN), + MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN), MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), @@ -208,6 +209,13 @@ static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6}; static const unsigned pins_nmi[] = {GPIO8}; static const unsigned pins_mdio[] = {GPIO42, GPIO43}; +static const unsigned pins_gphy0_led0[] = {GPIO5}; +static const unsigned pins_gphy0_led1[] = {GPIO7}; +static const unsigned pins_gphy0_led2[] = {GPIO2}; +static const unsigned pins_gphy1_led0[] = {GPIO44}; +static const unsigned pins_gphy1_led1[] = {GPIO45}; +static const unsigned pins_gphy1_led2[] = {GPIO47}; + static const unsigned pins_ebu_a24[] = {GPIO13}; static const unsigned pins_ebu_clk[] = {GPIO21}; static const unsigned pins_ebu_cs1[] = {GPIO23}; @@ -322,6 +330,12 @@ static const struct ltq_pin_group xway_grps[] = { GRP_MUX("gnt4", PCI, pins_pci_gnt4), GRP_MUX("req4", PCI, pins_pci_gnt4), GRP_MUX("mdio", MDIO, pins_mdio), + GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0), + GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1), + GRP_MUX("gphy0 led2", GPHY, pins_gphy0_led2), + GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0), + GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1), + GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2), }; static const struct ltq_pin_group ase_grps[] = { @@ -365,6 +379,9 @@ static const char * const xway_nmi_grps[] = {"nmi"}; /* ar9/vr9/gr9 */ static const char * const xrx_mdio_grps[] = {"mdio"}; +static const char * const xrx_gphy_grps[] = {"gphy0 led0", "gphy0 led1", + "gphy0 led2", "gphy1 led0", + "gphy1 led1", "gphy1 led2"}; static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24", "ebu a25", "ebu cs1", "ebu wait", "ebu clk", @@ -414,6 +431,7 @@ static const struct ltq_pmx_func xrx_funcs[] = { {"pci", ARRAY_AND_SIZE(xrx_pci_grps)}, {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)}, {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)}, + {"gphy", ARRAY_AND_SIZE(xrx_gphy_grps)}, }; static const struct ltq_pmx_func ase_funcs[] = { @@ -481,74 +499,101 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev, static int xway_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); - enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); - int arg = LTQ_PINCONF_UNPACK_ARG(config); + enum ltq_pinconf_param param; + int arg; int port = PORT(pin); u32 reg; + int i; + + for (i = 0; i < num_configs; i++) { + param = LTQ_PINCONF_UNPACK_PARAM(configs[i]); + arg = LTQ_PINCONF_UNPACK_ARG(configs[i]); + + switch (param) { + case LTQ_PINCONF_PARAM_OPEN_DRAIN: + if (port == PORT3) + reg = GPIO3_OD; + else + reg = GPIO_OD(pin); + if (arg == 0) + gpio_setbit(info->membase[0], + reg, + PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], + reg, + PORT_PIN(pin)); + break; - switch (param) { - case LTQ_PINCONF_PARAM_OPEN_DRAIN: - if (port == PORT3) - reg = GPIO3_OD; - else - reg = GPIO_OD(pin); - if (arg == 0) + case LTQ_PINCONF_PARAM_PULL: + if (port == PORT3) + reg = GPIO3_PUDEN; + else + reg = GPIO_PUDEN(pin); + if (arg == 0) { + gpio_clearbit(info->membase[0], + reg, + PORT_PIN(pin)); + break; + } gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); - else - gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); - break; - case LTQ_PINCONF_PARAM_PULL: - if (port == PORT3) - reg = GPIO3_PUDEN; - else - reg = GPIO_PUDEN(pin); - if (arg == 0) { - gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); + if (port == PORT3) + reg = GPIO3_PUDSEL; + else + reg = GPIO_PUDSEL(pin); + if (arg == 1) + gpio_clearbit(info->membase[0], + reg, + PORT_PIN(pin)); + else if (arg == 2) + gpio_setbit(info->membase[0], + reg, + PORT_PIN(pin)); + else + dev_err(pctldev->dev, + "Invalid pull value %d\n", arg); break; - } - gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); - if (port == PORT3) - reg = GPIO3_PUDSEL; - else - reg = GPIO_PUDSEL(pin); - if (arg == 1) - gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); - else if (arg == 2) - gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); - else - dev_err(pctldev->dev, "Invalid pull value %d\n", arg); - break; + case LTQ_PINCONF_PARAM_OUTPUT: + reg = GPIO_DIR(pin); + if (arg == 0) + gpio_clearbit(info->membase[0], + reg, + PORT_PIN(pin)); + else + gpio_setbit(info->membase[0], + reg, + PORT_PIN(pin)); + break; - case LTQ_PINCONF_PARAM_OUTPUT: - reg = GPIO_DIR(pin); - if (arg == 0) - gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); - else - gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); - break; + default: + dev_err(pctldev->dev, + "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + } /* for each config */ - default: - dev_err(pctldev->dev, "Invalid config param %04x\n", param); - return -ENOTSUPP; - } return 0; } int xway_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned selector, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); int i, ret = 0; for (i = 0; i < info->grps[selector].npins && !ret; i++) ret = xway_pinconf_set(pctldev, - info->grps[selector].pins[i], config); + info->grps[selector].pins[i], + configs, + num_configs); return ret; } @@ -716,10 +761,6 @@ static int pinmux_xway_probe(struct platform_device *pdev) /* get and remap our register range */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "Failed to get resource\n"); - return -ENOENT; - } xway_info.membase[0] = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(xway_info.membase[0])) return PTR_ERR(xway_info.membase[0]); diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 88cc5095d0c..051e8592990 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -391,19 +391,25 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting) struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; const struct pinmux_ops *ops = pctldev->desc->pmxops; - int ret; - const unsigned *pins; - unsigned num_pins; + int ret = 0; + const unsigned *pins = NULL; + unsigned num_pins = 0; int i; struct pin_desc *desc; - ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, - &pins, &num_pins); + if (pctlops->get_group_pins) + ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, + &pins, &num_pins); + if (ret) { + const char *gname; + /* errors only affect debug data, so just warn */ + gname = pctlops->get_group_name(pctldev, + setting->data.mux.group); dev_warn(pctldev->dev, - "could not get pins for group selector %d\n", - setting->data.mux.group); + "could not get pins for group %s\n", + gname); num_pins = 0; } @@ -411,9 +417,18 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting) for (i = 0; i < num_pins; i++) { ret = pin_request(pctldev, pins[i], setting->dev_name, NULL); if (ret) { + const char *gname; + const char *pname; + + desc = pin_desc_get(pctldev, pins[i]); + pname = desc ? desc->name : "non-existing"; + gname = pctlops->get_group_name(pctldev, + setting->data.mux.group); dev_err(pctldev->dev, - "could not request pin %d on device %s\n", - pins[i], pinctrl_dev_get_name(pctldev)); + "could not request pin %d (%s) from group %s " + " on device %s\n", + pins[i], pname, gname, + pinctrl_dev_get_name(pctldev)); goto err_pin_request; } } @@ -457,19 +472,24 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting) struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; const struct pinmux_ops *ops = pctldev->desc->pmxops; - int ret; - const unsigned *pins; - unsigned num_pins; + int ret = 0; + const unsigned *pins = NULL; + unsigned num_pins = 0; int i; struct pin_desc *desc; - ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, - &pins, &num_pins); + if (pctlops->get_group_pins) + ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, + &pins, &num_pins); if (ret) { + const char *gname; + /* errors only affect debug data, so just warn */ + gname = pctlops->get_group_name(pctldev, + setting->data.mux.group); dev_warn(pctldev->dev, - "could not get pins for group selector %d\n", - setting->data.mux.group); + "could not get pins for group %s\n", + gname); num_pins = 0; } @@ -482,12 +502,22 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting) pins[i]); continue; } - desc->mux_setting = NULL; - } + if (desc->mux_setting == &(setting->data.mux)) { + desc->mux_setting = NULL; + /* And release the pin */ + pin_free(pctldev, pins[i], NULL); + } else { + const char *gname; - /* And release the pins */ - for (i = 0; i < num_pins; i++) - pin_free(pctldev, pins[i], NULL); + gname = pctlops->get_group_name(pctldev, + setting->data.mux.group); + dev_warn(pctldev->dev, + "not freeing pin %d (%s) as part of " + "deactivating group %s - it is already " + "used for some other setting", + pins[i], desc->name, gname); + } + } if (ops->disable) ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group); diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index c3340f54d2a..26187aa5cf5 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -5,11 +5,10 @@ if ARCH_SHMOBILE || SUPERH config PINCTRL_SH_PFC - # XXX move off the gpio dependency - depends on GENERIC_GPIO select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB select PINMUX select PINCONF + select GENERIC_PINCONF def_bool y help This enables pin control drivers for SH and SH Mobile platforms @@ -21,32 +20,52 @@ config GPIO_SH_PFC This enables support for GPIOs within the SoC's pin function controller. +config PINCTRL_PFC_R8A73A4 + def_bool y + depends on ARCH_R8A73A4 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7740 def_bool y depends on ARCH_R8A7740 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7778 + def_bool y + depends on ARCH_R8A7778 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7779 def_bool y depends on ARCH_R8A7779 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7790 + def_bool y + depends on ARCH_R8A7790 + select PINCTRL_SH_PFC + +config PINCTRL_PFC_R8A7791 + def_bool y + depends on ARCH_R8A7791 + select PINCTRL_SH_PFC + config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7264 def_bool y depends on CPU_SUBTYPE_SH7264 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7269 def_bool y depends on CPU_SUBTYPE_SH7269 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7372 @@ -58,59 +77,60 @@ config PINCTRL_PFC_SH73A0 def_bool y depends on ARCH_SH73A0 select PINCTRL_SH_PFC + select REGULATOR config PINCTRL_PFC_SH7720 def_bool y depends on CPU_SUBTYPE_SH7720 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7722 def_bool y depends on CPU_SUBTYPE_SH7722 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7723 def_bool y depends on CPU_SUBTYPE_SH7723 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7724 def_bool y depends on CPU_SUBTYPE_SH7724 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7734 def_bool y depends on CPU_SUBTYPE_SH7734 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7757 def_bool y depends on CPU_SUBTYPE_SH7757 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7785 def_bool y depends on CPU_SUBTYPE_SH7785 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SH7786 def_bool y depends on CPU_SUBTYPE_SH7786 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC config PINCTRL_PFC_SHX3 def_bool y depends on CPU_SUBTYPE_SHX3 - depends on GENERIC_GPIO + depends on GPIOLIB select PINCTRL_SH_PFC endif diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index e8b9562c47e..ad8f4cf9faa 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -3,8 +3,12 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y) sh-pfc-objs += gpio.o endif obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o +obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o +obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o +obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o +obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 970ddff2b0b..b9b464d0578 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -10,7 +10,6 @@ */ #define DRV_NAME "sh-pfc" -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include <linux/bitops.h> #include <linux/err.h> @@ -19,37 +18,75 @@ #include <linux/ioport.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> #include <linux/pinctrl/machine.h> #include <linux/platform_device.h> #include <linux/slab.h> #include "core.h" -static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) +static int sh_pfc_map_resources(struct sh_pfc *pfc, + struct platform_device *pdev) { + unsigned int num_windows = 0; + unsigned int num_irqs = 0; + struct sh_pfc_window *windows; + unsigned int *irqs = NULL; struct resource *res; - int k; + unsigned int i; - if (pdev->num_resources == 0) { - pfc->num_windows = 0; - return 0; + /* Count the MEM and IRQ resources. */ + for (i = 0; i < pdev->num_resources; ++i) { + switch (resource_type(&pdev->resource[i])) { + case IORESOURCE_MEM: + num_windows++; + break; + + case IORESOURCE_IRQ: + num_irqs++; + break; + } } - pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * - sizeof(*pfc->window), GFP_NOWAIT); - if (!pfc->window) + if (num_windows == 0) + return -EINVAL; + + /* Allocate memory windows and IRQs arrays. */ + windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows), + GFP_KERNEL); + if (windows == NULL) return -ENOMEM; - pfc->num_windows = pdev->num_resources; + pfc->num_windows = num_windows; + pfc->windows = windows; - for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) { - WARN_ON(resource_type(res) != IORESOURCE_MEM); - pfc->window[k].phys = res->start; - pfc->window[k].size = resource_size(res); - pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start, - resource_size(res)); - if (!pfc->window[k].virt) + if (num_irqs) { + irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs), + GFP_KERNEL); + if (irqs == NULL) return -ENOMEM; + + pfc->num_irqs = num_irqs; + pfc->irqs = irqs; + } + + /* Fill them. */ + for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) { + switch (resource_type(res)) { + case IORESOURCE_MEM: + windows->phys = res->start; + windows->size = resource_size(res); + windows->virt = devm_ioremap_resource(pfc->dev, res); + if (IS_ERR(windows->virt)) + return -ENOMEM; + windows++; + break; + + case IORESOURCE_IRQ: + *irqs++ = res->start; + break; + } } return 0; @@ -59,11 +96,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address) { struct sh_pfc_window *window; - int k; + unsigned int i; /* scan through physical windows and convert address */ - for (k = 0; k < pfc->num_windows; k++) { - window = pfc->window + k; + for (i = 0; i < pfc->num_windows; i++) { + window = pfc->windows + i; if (address < window->phys) continue; @@ -74,11 +111,29 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, return window->virt + (address - window->phys); } - /* no windows defined, register must be 1:1 mapped virt:phys */ - return (void __iomem *)address; + BUG(); + return NULL; +} + +int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) +{ + unsigned int offset; + unsigned int i; + + for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { + const struct sh_pfc_pin_range *range = &pfc->ranges[i]; + + if (pin <= range->end) + return pin >= range->start + ? offset + pin - range->start : -1; + + offset += range->end - range->start + 1; + } + + return -EINVAL; } -static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) +static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) { if (enum_id < r->begin) return 0; @@ -89,8 +144,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) return 1; } -static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, - unsigned long reg_width) +unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, + unsigned long reg_width) { switch (reg_width) { case 8: @@ -105,8 +160,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, return 0; } -static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, - unsigned long reg_width, unsigned long data) +void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, + unsigned long data) { switch (reg_width) { case 8: @@ -123,45 +178,14 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, BUG(); } -int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos) -{ - unsigned long pos; - - pos = dr->reg_width - (in_pos + 1); - - pr_debug("read_bit: addr = %lx, pos = %ld, " - "r_width = %ld\n", dr->reg, pos, dr->reg_width); - - return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; -} - -void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, - unsigned long value) -{ - unsigned long pos; - - pos = dr->reg_width - (in_pos + 1); - - pr_debug("write_bit addr = %lx, value = %d, pos = %ld, " - "r_width = %ld\n", - dr->reg, !!value, pos, dr->reg_width); - - if (value) - set_bit(pos, &dr->reg_shadow); - else - clear_bit(pos, &dr->reg_shadow); - - sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); -} - static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, - struct pinmux_cfg_reg *crp, + const struct pinmux_cfg_reg *crp, unsigned long in_pos, void __iomem **mapped_regp, unsigned long *maskp, unsigned long *posp) { - int k; + unsigned int k; *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); @@ -176,24 +200,8 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, } } -static int sh_pfc_read_config_reg(struct sh_pfc *pfc, - struct pinmux_cfg_reg *crp, - unsigned long field) -{ - void __iomem *mapped_reg; - unsigned long mask, pos; - - sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); - - pr_debug("read_reg: addr = %lx, field = %ld, " - "r_width = %ld, f_width = %ld\n", - crp->reg, field, crp->reg_width, crp->field_width); - - return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask; -} - static void sh_pfc_write_config_reg(struct sh_pfc *pfc, - struct pinmux_cfg_reg *crp, + const struct pinmux_cfg_reg *crp, unsigned long field, unsigned long value) { void __iomem *mapped_reg; @@ -201,9 +209,9 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); - pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " - "r_width = %ld, f_width = %ld\n", - crp->reg, value, field, crp->reg_width, crp->field_width); + dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, " + "r_width = %ld, f_width = %ld\n", + crp->reg, value, field, crp->reg_width, crp->field_width); mask = ~(mask << pos); value = value << pos; @@ -220,85 +228,13 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); } -static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) -{ - struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio]; - struct pinmux_data_reg *data_reg; - int k, n; - - if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data)) - return -1; - - k = 0; - while (1) { - data_reg = pfc->info->data_regs + k; - - if (!data_reg->reg_width) - break; - - data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg); - - for (n = 0; n < data_reg->reg_width; n++) { - if (data_reg->enum_ids[n] == gpiop->enum_id) { - gpiop->flags &= ~PINMUX_FLAG_DREG; - gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); - gpiop->flags &= ~PINMUX_FLAG_DBIT; - gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); - return 0; - } - } - k++; - } - - BUG(); - - return -1; -} - -static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) -{ - struct pinmux_data_reg *drp; - int k; - - for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++) - sh_pfc_setup_data_reg(pfc, k); - - k = 0; - while (1) { - drp = pfc->info->data_regs + k; - - if (!drp->reg_width) - break; - - drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg, - drp->reg_width); - k++; - } -} - -int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, - struct pinmux_data_reg **drp, int *bitp) -{ - struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio]; - int k, n; - - if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data)) - return -1; - - k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; - n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; - *drp = pfc->info->data_regs + k; - *bitp = n; - return 0; -} - -static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, - struct pinmux_cfg_reg **crp, int *fieldp, - int *valuep, unsigned long **cntp) +static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, + const struct pinmux_cfg_reg **crp, int *fieldp, + int *valuep) { - struct pinmux_cfg_reg *config_reg; + const struct pinmux_cfg_reg *config_reg; unsigned long r_width, f_width, curr_width, ncomb; - int k, m, n, pos, bit_pos; + unsigned int k, m, n, pos, bit_pos; k = 0; while (1) { @@ -324,7 +260,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, *crp = config_reg; *fieldp = m; *valuep = n; - *cntp = &config_reg->cnt[m]; return 0; } } @@ -334,22 +269,14 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, k++; } - return -1; + return -EINVAL; } -int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, - pinmux_enum_t *enum_idp) +static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, + u16 *enum_idp) { - pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id; - pinmux_enum_t *data = pfc->info->gpio_data; - int k; - - if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) { - if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) { - pr_err("non data/mark enum_id for gpio %d\n", gpio); - return -1; - } - } + const u16 *data = pfc->info->gpio_data; + unsigned int k; if (pos) { *enum_idp = data[pos + 1]; @@ -357,27 +284,27 @@ int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, } for (k = 0; k < pfc->info->gpio_data_size; k++) { - if (data[k] == enum_id) { + if (data[k] == mark) { *enum_idp = data[k + 1]; return k + 1; } } - pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio); - return -1; + dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", + mark); + return -EINVAL; } -int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, - int cfg_mode) +int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) { - struct pinmux_cfg_reg *cr = NULL; - pinmux_enum_t enum_id; - struct pinmux_range *range; + const struct pinmux_cfg_reg *cr = NULL; + u16 enum_id; + const struct pinmux_range *range; int in_range, pos, field, value; - unsigned long *cntp; + int ret; switch (pinmux_type) { - + case PINMUX_TYPE_GPIO: case PINMUX_TYPE_FUNCTION: range = NULL; break; @@ -390,42 +317,38 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, range = &pfc->info->input; break; - case PINMUX_TYPE_INPUT_PULLUP: - range = &pfc->info->input_pu; - break; - - case PINMUX_TYPE_INPUT_PULLDOWN: - range = &pfc->info->input_pd; - break; - default: - goto out_err; + return -EINVAL; } pos = 0; enum_id = 0; field = 0; value = 0; + + /* Iterate over all the configuration fields we need to update. */ while (1) { - pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id); - if (pos <= 0) - goto out_err; + pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); + if (pos < 0) + return pos; if (!enum_id) break; - /* first check if this is a function enum */ + /* Check if the configuration field selects a function. If it + * doesn't, skip the field if it's not applicable to the + * requested pinmux type. + */ in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); if (!in_range) { - /* not a function enum */ - if (range) { - /* - * other range exists, so this pin is - * a regular GPIO pin that now is being - * bound to a specific direction. - * - * for this case we only allow function enums - * and the enums that match the other range. + if (pinmux_type == PINMUX_TYPE_FUNCTION) { + /* Functions are allowed to modify all + * fields. + */ + in_range = 1; + } else if (pinmux_type != PINMUX_TYPE_GPIO) { + /* Input/output types can only modify fields + * that correspond to their respective ranges. */ in_range = sh_pfc_enum_in_range(enum_id, range); @@ -436,62 +359,156 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, */ if (in_range && enum_id == range->force) continue; - } else { - /* - * no other range exists, so this pin - * must then be of the function type. - * - * allow function type pins to select - * any combination of function/in/out - * in their MARK lists. - */ - in_range = 1; } + /* GPIOs are only allowed to modify function fields. */ } if (!in_range) continue; - if (sh_pfc_get_config_reg(pfc, enum_id, &cr, - &field, &value, &cntp) != 0) - goto out_err; + ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); + if (ret < 0) + return ret; - switch (cfg_mode) { - case GPIO_CFG_DRYRUN: - if (!*cntp || - (sh_pfc_read_config_reg(pfc, cr, field) != value)) - continue; - break; + sh_pfc_write_config_reg(pfc, cr, field, value); + } - case GPIO_CFG_REQ: - sh_pfc_write_config_reg(pfc, cr, field, value); - *cntp = *cntp + 1; - break; + return 0; +} - case GPIO_CFG_FREE: - *cntp = *cntp - 1; - break; - } +static int sh_pfc_init_ranges(struct sh_pfc *pfc) +{ + struct sh_pfc_pin_range *range; + unsigned int nr_ranges; + unsigned int i; + + if (pfc->info->pins[0].pin == (u16)-1) { + /* Pin number -1 denotes that the SoC doesn't report pin numbers + * in its pin arrays yet. Consider the pin numbers range as + * continuous and allocate a single range. + */ + pfc->nr_ranges = 1; + pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges), + GFP_KERNEL); + if (pfc->ranges == NULL) + return -ENOMEM; + + pfc->ranges->start = 0; + pfc->ranges->end = pfc->info->nr_pins - 1; + pfc->nr_gpio_pins = pfc->info->nr_pins; + + return 0; + } + + /* Count, allocate and fill the ranges. The PFC SoC data pins array must + * be sorted by pin numbers, and pins without a GPIO port must come + * last. + */ + for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { + if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) + nr_ranges++; + } + + pfc->nr_ranges = nr_ranges; + pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges, + GFP_KERNEL); + if (pfc->ranges == NULL) + return -ENOMEM; + + range = pfc->ranges; + range->start = pfc->info->pins[0].pin; + + for (i = 1; i < pfc->info->nr_pins; ++i) { + if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) + continue; + + range->end = pfc->info->pins[i-1].pin; + if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) + pfc->nr_gpio_pins = range->end + 1; + + range++; + range->start = pfc->info->pins[i].pin; } + range->end = pfc->info->pins[i-1].pin; + if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) + pfc->nr_gpio_pins = range->end + 1; + return 0; - out_err: - return -1; } +#ifdef CONFIG_OF +static const struct of_device_id sh_pfc_of_table[] = { +#ifdef CONFIG_PINCTRL_PFC_R8A73A4 + { + .compatible = "renesas,pfc-r8a73a4", + .data = &r8a73a4_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7740 + { + .compatible = "renesas,pfc-r8a7740", + .data = &r8a7740_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7778 + { + .compatible = "renesas,pfc-r8a7778", + .data = &r8a7778_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7779 + { + .compatible = "renesas,pfc-r8a7779", + .data = &r8a7779_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7790 + { + .compatible = "renesas,pfc-r8a7790", + .data = &r8a7790_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7791 + { + .compatible = "renesas,pfc-r8a7791", + .data = &r8a7791_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_SH7372 + { + .compatible = "renesas,pfc-sh7372", + .data = &sh7372_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_SH73A0 + { + .compatible = "renesas,pfc-sh73a0", + .data = &sh73a0_pinmux_info, + }, +#endif + { }, +}; +MODULE_DEVICE_TABLE(of, sh_pfc_of_table); +#endif + static int sh_pfc_probe(struct platform_device *pdev) { - struct sh_pfc_soc_info *info; + const struct platform_device_id *platid = platform_get_device_id(pdev); +#ifdef CONFIG_OF + struct device_node *np = pdev->dev.of_node; +#endif + const struct sh_pfc_soc_info *info; struct sh_pfc *pfc; int ret; - /* - * Ensure that the type encoding fits - */ - BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1)); +#ifdef CONFIG_OF + if (np) + info = of_match_device(sh_pfc_of_table, &pdev->dev)->data; + else +#endif + info = platid ? (const void *)platid->driver_data : NULL; - info = pdev->id_entry->driver_data - ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; if (info == NULL) return -ENODEV; @@ -502,21 +519,30 @@ static int sh_pfc_probe(struct platform_device *pdev) pfc->info = info; pfc->dev = &pdev->dev; - ret = sh_pfc_ioremap(pfc, pdev); + ret = sh_pfc_map_resources(pfc, pdev); if (unlikely(ret < 0)) return ret; spin_lock_init(&pfc->lock); + if (info->ops && info->ops->init) { + ret = info->ops->init(pfc); + if (ret < 0) + return ret; + } + pinctrl_provide_dummies(); - sh_pfc_setup_data_regs(pfc); + + ret = sh_pfc_init_ranges(pfc); + if (ret < 0) + return ret; /* * Initialize pinctrl bindings first */ ret = sh_pfc_register_pinctrl(pfc); if (unlikely(ret != 0)) - return ret; + goto error; #ifdef CONFIG_GPIO_SH_PFC /* @@ -529,15 +555,20 @@ static int sh_pfc_probe(struct platform_device *pdev) * PFC state as it is, given that there are already * extant users of it that have succeeded by this point. */ - pr_notice("failed to init GPIO chip, ignoring...\n"); + dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); } #endif platform_set_drvdata(pdev, pfc); - pr_info("%s support registered\n", info->name); + dev_info(pfc->dev, "%s support registered\n", info->name); return 0; + +error: + if (info->ops && info->ops->exit) + info->ops->exit(pfc); + return ret; } static int sh_pfc_remove(struct platform_device *pdev) @@ -549,18 +580,31 @@ static int sh_pfc_remove(struct platform_device *pdev) #endif sh_pfc_unregister_pinctrl(pfc); - platform_set_drvdata(pdev, NULL); + if (pfc->info->ops && pfc->info->ops->exit) + pfc->info->ops->exit(pfc); return 0; } static const struct platform_device_id sh_pfc_id_table[] = { +#ifdef CONFIG_PINCTRL_PFC_R8A73A4 + { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7740 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7778 + { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7779 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7790 + { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7791 + { "pfc-r8a7791", (kernel_ulong_t)&r8a7791_pinmux_info }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH7203 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, #endif @@ -615,6 +659,7 @@ static struct platform_driver sh_pfc_driver = { .driver = { .name = DRV_NAME, .owner = THIS_MODULE, + .of_match_table = of_match_ptr(sh_pfc_of_table), }, }; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index ba7c33c3359..b7b0e6ccf30 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -11,6 +11,7 @@ #define __SH_PFC_CORE_H__ #include <linux/compiler.h> +#include <linux/spinlock.h> #include <linux/types.h> #include "sh_pfc.h" @@ -24,15 +25,30 @@ struct sh_pfc_window { struct sh_pfc_chip; struct sh_pfc_pinctrl; +struct sh_pfc_pin_range { + u16 start; + u16 end; +}; + struct sh_pfc { struct device *dev; - struct sh_pfc_soc_info *info; + const struct sh_pfc_soc_info *info; + void *soc_data; spinlock_t lock; unsigned int num_windows; - struct sh_pfc_window *window; + struct sh_pfc_window *windows; + unsigned int num_irqs; + unsigned int *irqs; + + struct sh_pfc_pin_range *ranges; + unsigned int nr_ranges; + + unsigned int nr_gpio_pins; struct sh_pfc_chip *gpio; + struct sh_pfc_chip *func; + struct sh_pfc_pinctrl *pinctrl; }; @@ -42,31 +58,33 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc); int sh_pfc_register_pinctrl(struct sh_pfc *pfc); int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); -int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos); -void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, - unsigned long value); -int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, - struct pinmux_data_reg **drp, int *bitp); -int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, - pinmux_enum_t *enum_idp); -int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, - int cfg_mode); - -extern struct sh_pfc_soc_info r8a7740_pinmux_info; -extern struct sh_pfc_soc_info r8a7779_pinmux_info; -extern struct sh_pfc_soc_info sh7203_pinmux_info; -extern struct sh_pfc_soc_info sh7264_pinmux_info; -extern struct sh_pfc_soc_info sh7269_pinmux_info; -extern struct sh_pfc_soc_info sh7372_pinmux_info; -extern struct sh_pfc_soc_info sh73a0_pinmux_info; -extern struct sh_pfc_soc_info sh7720_pinmux_info; -extern struct sh_pfc_soc_info sh7722_pinmux_info; -extern struct sh_pfc_soc_info sh7723_pinmux_info; -extern struct sh_pfc_soc_info sh7724_pinmux_info; -extern struct sh_pfc_soc_info sh7734_pinmux_info; -extern struct sh_pfc_soc_info sh7757_pinmux_info; -extern struct sh_pfc_soc_info sh7785_pinmux_info; -extern struct sh_pfc_soc_info sh7786_pinmux_info; -extern struct sh_pfc_soc_info shx3_pinmux_info; +unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, + unsigned long reg_width); +void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, + unsigned long data); + +int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); +int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); + +extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; +extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7778_pinmux_info; +extern const struct sh_pfc_soc_info r8a7779_pinmux_info; +extern const struct sh_pfc_soc_info r8a7790_pinmux_info; +extern const struct sh_pfc_soc_info r8a7791_pinmux_info; +extern const struct sh_pfc_soc_info sh7203_pinmux_info; +extern const struct sh_pfc_soc_info sh7264_pinmux_info; +extern const struct sh_pfc_soc_info sh7269_pinmux_info; +extern const struct sh_pfc_soc_info sh7372_pinmux_info; +extern const struct sh_pfc_soc_info sh73a0_pinmux_info; +extern const struct sh_pfc_soc_info sh7720_pinmux_info; +extern const struct sh_pfc_soc_info sh7722_pinmux_info; +extern const struct sh_pfc_soc_info sh7723_pinmux_info; +extern const struct sh_pfc_soc_info sh7724_pinmux_info; +extern const struct sh_pfc_soc_info sh7734_pinmux_info; +extern const struct sh_pfc_soc_info sh7757_pinmux_info; +extern const struct sh_pfc_soc_info sh7785_pinmux_info; +extern const struct sh_pfc_soc_info sh7786_pinmux_info; +extern const struct sh_pfc_soc_info shx3_pinmux_info; #endif /* __SH_PFC_CORE_H__ */ diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index a535075c8b6..a9288ab01f7 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -9,8 +9,6 @@ * for more details. */ -#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt - #include <linux/device.h> #include <linux/gpio.h> #include <linux/init.h> @@ -21,9 +19,23 @@ #include "core.h" +struct sh_pfc_gpio_data_reg { + const struct pinmux_data_reg *info; + unsigned long shadow; +}; + +struct sh_pfc_gpio_pin { + u8 dbit; + u8 dreg; +}; + struct sh_pfc_chip { - struct sh_pfc *pfc; - struct gpio_chip gpio_chip; + struct sh_pfc *pfc; + struct gpio_chip gpio_chip; + + struct sh_pfc_window *mem; + struct sh_pfc_gpio_data_reg *regs; + struct sh_pfc_gpio_pin *pins; }; static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) @@ -36,143 +48,372 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) return gpio_to_pfc_chip(gc)->pfc; } -static int sh_gpio_request(struct gpio_chip *gc, unsigned offset) +static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset, + struct sh_pfc_gpio_data_reg **reg, + unsigned int *bit) { - return pinctrl_request_gpio(offset); + int idx = sh_pfc_get_pin_index(chip->pfc, offset); + struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; + + *reg = &chip->regs[gpio_pin->dreg]; + *bit = gpio_pin->dbit; } -static void sh_gpio_free(struct gpio_chip *gc, unsigned offset) +static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip, + const struct pinmux_data_reg *dreg) { - pinctrl_free_gpio(offset); + void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; + + return sh_pfc_read_raw_reg(mem, dreg->reg_width); } -static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value) +static void gpio_write_data_reg(struct sh_pfc_chip *chip, + const struct pinmux_data_reg *dreg, + unsigned long value) { - struct pinmux_data_reg *dr = NULL; - int bit = 0; + void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; - if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) - BUG(); - else - sh_pfc_write_bit(dr, bit, value); + sh_pfc_write_raw_reg(mem, dreg->reg_width, value); +} + +static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx) +{ + struct sh_pfc *pfc = chip->pfc; + struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + const struct pinmux_data_reg *dreg; + unsigned int bit; + unsigned int i; + + for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) { + for (bit = 0; bit < dreg->reg_width; bit++) { + if (dreg->enum_ids[bit] == pin->enum_id) { + gpio_pin->dreg = i; + gpio_pin->dbit = bit; + return; + } + } + } + + BUG(); +} + +static int gpio_setup_data_regs(struct sh_pfc_chip *chip) +{ + struct sh_pfc *pfc = chip->pfc; + const struct pinmux_data_reg *dreg; + unsigned int i; + + /* Count the number of data registers, allocate memory and initialize + * them. + */ + for (i = 0; pfc->info->data_regs[i].reg_width; ++i) + ; + + chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs), + GFP_KERNEL); + if (chip->regs == NULL) + return -ENOMEM; + + for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { + chip->regs[i].info = dreg; + chip->regs[i].shadow = gpio_read_data_reg(chip, dreg); + } + + for (i = 0; i < pfc->info->nr_pins; i++) { + if (pfc->info->pins[i].enum_id == 0) + continue; + + gpio_setup_data_reg(chip, i); + } + + return 0; } -static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio) +/* ----------------------------------------------------------------------------- + * Pin GPIOs + */ + +static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) { - struct pinmux_data_reg *dr = NULL; - int bit = 0; + struct sh_pfc *pfc = gpio_to_pfc(gc); + int idx = sh_pfc_get_pin_index(pfc, offset); - if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) + if (idx < 0 || pfc->info->pins[idx].enum_id == 0) return -EINVAL; - return sh_pfc_read_bit(dr, bit); + return pinctrl_request_gpio(offset); +} + +static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) +{ + return pinctrl_free_gpio(offset); +} + +static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, + int value) +{ + struct sh_pfc_gpio_data_reg *reg; + unsigned long pos; + unsigned int bit; + + gpio_get_data_reg(chip, offset, ®, &bit); + + pos = reg->info->reg_width - (bit + 1); + + if (value) + set_bit(pos, ®->shadow); + else + clear_bit(pos, ®->shadow); + + gpio_write_data_reg(chip, reg->info, reg->shadow); } -static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset) +static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) { return pinctrl_gpio_direction_input(offset); } -static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset, +static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, int value) { - sh_gpio_set_value(gpio_to_pfc(gc), offset, value); + gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); return pinctrl_gpio_direction_output(offset); } -static int sh_gpio_get(struct gpio_chip *gc, unsigned offset) +static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) { - return sh_gpio_get_value(gpio_to_pfc(gc), offset); + struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc); + struct sh_pfc_gpio_data_reg *reg; + unsigned long pos; + unsigned int bit; + + gpio_get_data_reg(chip, offset, ®, &bit); + + pos = reg->info->reg_width - (bit + 1); + + return (gpio_read_data_reg(chip, reg->info) >> pos) & 1; } -static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value) +static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) { - sh_gpio_set_value(gpio_to_pfc(gc), offset, value); + gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); } -static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); - pinmux_enum_t enum_id; - pinmux_enum_t *enum_ids; - int i, k, pos; - - pos = 0; - enum_id = 0; - while (1) { - pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id); - if (pos <= 0 || !enum_id) - break; + unsigned int i, k; - for (i = 0; i < pfc->info->gpio_irq_size; i++) { - enum_ids = pfc->info->gpio_irq[i].enum_ids; - for (k = 0; enum_ids[k]; k++) { - if (enum_ids[k] == enum_id) - return pfc->info->gpio_irq[i].irq; - } + for (i = 0; i < pfc->info->gpio_irq_size; i++) { + const short *gpios = pfc->info->gpio_irq[i].gpios; + + for (k = 0; gpios[k] >= 0; k++) { + if (gpios[k] == offset) + goto found; } } return -ENOSYS; + +found: + if (pfc->num_irqs) + return pfc->irqs[i]; + else + return pfc->info->gpio_irq[i].irq; } -static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip) +static int gpio_pin_setup(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; struct gpio_chip *gc = &chip->gpio_chip; + int ret; + + chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins * + sizeof(*chip->pins), GFP_KERNEL); + if (chip->pins == NULL) + return -ENOMEM; - gc->request = sh_gpio_request; - gc->free = sh_gpio_free; - gc->direction_input = sh_gpio_direction_input; - gc->get = sh_gpio_get; - gc->direction_output = sh_gpio_direction_output; - gc->set = sh_gpio_set; - gc->to_irq = sh_gpio_to_irq; + ret = gpio_setup_data_regs(chip); + if (ret < 0) + return ret; - WARN_ON(pfc->info->first_gpio != 0); /* needs testing */ + gc->request = gpio_pin_request; + gc->free = gpio_pin_free; + gc->direction_input = gpio_pin_direction_input; + gc->get = gpio_pin_get; + gc->direction_output = gpio_pin_direction_output; + gc->set = gpio_pin_set; + gc->to_irq = gpio_pin_to_irq; gc->label = pfc->info->name; + gc->dev = pfc->dev; gc->owner = THIS_MODULE; - gc->base = pfc->info->first_gpio; - gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1; + gc->base = 0; + gc->ngpio = pfc->nr_gpio_pins; + + return 0; } -int sh_pfc_register_gpiochip(struct sh_pfc *pfc) +/* ----------------------------------------------------------------------------- + * Function GPIOs + */ + +static int gpio_function_request(struct gpio_chip *gc, unsigned offset) +{ + static bool __print_once; + struct sh_pfc *pfc = gpio_to_pfc(gc); + unsigned int mark = pfc->info->func_gpios[offset].enum_id; + unsigned long flags; + int ret; + + if (!__print_once) { + dev_notice(pfc->dev, + "Use of GPIO API for function requests is deprecated." + " Convert to pinctrl\n"); + __print_once = true; + } + + if (mark == 0) + return -EINVAL; + + spin_lock_irqsave(&pfc->lock, flags); + ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION); + spin_unlock_irqrestore(&pfc->lock, flags); + + return ret; +} + +static void gpio_function_free(struct gpio_chip *gc, unsigned offset) +{ +} + +static int gpio_function_setup(struct sh_pfc_chip *chip) +{ + struct sh_pfc *pfc = chip->pfc; + struct gpio_chip *gc = &chip->gpio_chip; + + gc->request = gpio_function_request; + gc->free = gpio_function_free; + + gc->label = pfc->info->name; + gc->owner = THIS_MODULE; + gc->base = pfc->nr_gpio_pins; + gc->ngpio = pfc->info->nr_func_gpios; + + return 0; +} + +/* ----------------------------------------------------------------------------- + * Register/unregister + */ + +static struct sh_pfc_chip * +sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *), + struct sh_pfc_window *mem) { struct sh_pfc_chip *chip; int ret; chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); if (unlikely(!chip)) - return -ENOMEM; + return ERR_PTR(-ENOMEM); + chip->mem = mem; chip->pfc = pfc; - sh_pfc_gpio_setup(chip); + ret = setup(chip); + if (ret < 0) + return ERR_PTR(ret); ret = gpiochip_add(&chip->gpio_chip); if (unlikely(ret < 0)) - return ret; + return ERR_PTR(ret); + + dev_info(pfc->dev, "%s handling gpio %u -> %u\n", + chip->gpio_chip.label, chip->gpio_chip.base, + chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); + + return chip; +} + +int sh_pfc_register_gpiochip(struct sh_pfc *pfc) +{ + struct sh_pfc_chip *chip; + unsigned int i; + int ret; + + if (pfc->info->data_regs == NULL) + return 0; + + /* Find the memory window that contain the GPIO registers. Boards that + * register a separate GPIO device will not supply a memory resource + * that covers the data registers. In that case don't try to handle + * GPIOs. + */ + for (i = 0; i < pfc->num_windows; ++i) { + struct sh_pfc_window *window = &pfc->windows[i]; + + if (pfc->info->data_regs[0].reg >= window->phys && + pfc->info->data_regs[0].reg < window->phys + window->size) + break; + } + + if (i == pfc->num_windows) + return 0; + + /* If we have IRQ resources make sure their number is correct. */ + if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) { + dev_err(pfc->dev, "invalid number of IRQ resources\n"); + return -EINVAL; + } + + /* Register the real GPIOs chip. */ + chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]); + if (IS_ERR(chip)) + return PTR_ERR(chip); pfc->gpio = chip; - pr_info("%s handling gpio %d -> %d\n", - pfc->info->name, pfc->info->first_gpio, - pfc->info->last_gpio); + /* Register the GPIO to pin mappings. As pins with GPIO ports must come + * first in the ranges, skip the pins without GPIO ports by stopping at + * the first range that contains such a pin. + */ + for (i = 0; i < pfc->nr_ranges; ++i) { + const struct sh_pfc_pin_range *range = &pfc->ranges[i]; + + if (range->start >= pfc->nr_gpio_pins) + break; + + ret = gpiochip_add_pin_range(&chip->gpio_chip, + dev_name(pfc->dev), + range->start, range->start, + range->end - range->start + 1); + if (ret < 0) + return ret; + } + + /* Register the function GPIOs chip. */ + if (pfc->info->nr_func_gpios == 0) + return 0; + + chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + pfc->func = chip; return 0; } int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) { - struct sh_pfc_chip *chip = pfc->gpio; + int err; int ret; - ret = gpiochip_remove(&chip->gpio_chip); - if (unlikely(ret < 0)) - return ret; + ret = gpiochip_remove(&pfc->gpio->gpio_chip); + err = gpiochip_remove(&pfc->func->gpio_chip); - pfc->gpio = NULL; - return 0; + return ret < 0 ? ret : err; } diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c new file mode 100644 index 00000000000..ce9fb7aa8ba --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -0,0 +1,2749 @@ +/* + * Copyright (C) 2012-2013 Renesas Solutions Corp. + * Copyright (C) 2013 Magnus Damm + * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/pinctrl/pinconf-generic.h> + +#ifndef CONFIG_ARCH_MULTIPLATFORM +#include <mach/irqs.h> +#endif + +#include "core.h" +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + /* Port0 - Port30 */ \ + PORT_10(0, fn, pfx, sfx), \ + PORT_10(10, fn, pfx##1, sfx), \ + PORT_10(20, fn, pfx##2, sfx), \ + PORT_1(30, fn, pfx##30, sfx), \ + /* Port32 - Port40 */ \ + PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \ + PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \ + PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \ + PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \ + PORT_1(40, fn, pfx##40, sfx), \ + /* Port64 - Port85 */ \ + PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \ + PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \ + PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \ + PORT_10(70, fn, pfx##7, sfx), \ + PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \ + PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \ + PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \ + /* Port96 - Port126 */ \ + PORT_1(96, fn, pfx##96, sfx), PORT_1(97, fn, pfx##97, sfx), \ + PORT_1(98, fn, pfx##98, sfx), PORT_1(99, fn, pfx##99, sfx), \ + PORT_10(100, fn, pfx##10, sfx), \ + PORT_10(110, fn, pfx##11, sfx), \ + PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \ + PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \ + PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \ + PORT_1(126, fn, pfx##126, sfx), \ + /* Port128 - Port134 */ \ + PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \ + PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \ + PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \ + PORT_1(134, fn, pfx##134, sfx), \ + /* Port160 - Port178 */ \ + PORT_10(160, fn, pfx##16, sfx), \ + PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \ + PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \ + PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \ + PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \ + PORT_1(178, fn, pfx##178, sfx), \ + /* Port192 - Port222 */ \ + PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \ + PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \ + PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \ + PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \ + PORT_10(200, fn, pfx##20, sfx), \ + PORT_10(210, fn, pfx##21, sfx), \ + PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \ + PORT_1(222, fn, pfx##222, sfx), \ + /* Port224 - Port250 */ \ + PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \ + PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \ + PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \ + PORT_10(230, fn, pfx##23, sfx), \ + PORT_10(240, fn, pfx##24, sfx), \ + PORT_1(250, fn, pfx##250, sfx), \ + /* Port256 - Port283 */ \ + PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \ + PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \ + PORT_10(260, fn, pfx##26, sfx), \ + PORT_10(270, fn, pfx##27, sfx), \ + PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \ + PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \ + /* Port288 - Port308 */ \ + PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \ + PORT_10(290, fn, pfx##29, sfx), \ + PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \ + PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \ + PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \ + PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \ + PORT_1(308, fn, pfx##308, sfx), \ + /* Port320 - Port329 */ \ + PORT_10(320, fn, pfx##32, sfx) + + +enum { + PINMUX_RESERVED = 0, + + /* PORT0_DATA -> PORT329_DATA */ + PINMUX_DATA_BEGIN, + PORT_ALL(DATA), + PINMUX_DATA_END, + + /* PORT0_IN -> PORT329_IN */ + PINMUX_INPUT_BEGIN, + PORT_ALL(IN), + PINMUX_INPUT_END, + + /* PORT0_OUT -> PORT329_OUT */ + PINMUX_OUTPUT_BEGIN, + PORT_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */ + PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */ + PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */ + PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */ + PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */ + PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */ + PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */ + PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */ + PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */ + PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */ + + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_25_0, MSEL1CR_25_1, + MSEL1CR_24_0, MSEL1CR_24_1, + MSEL1CR_22_0, MSEL1CR_22_1, + MSEL1CR_21_0, MSEL1CR_21_1, + MSEL1CR_20_0, MSEL1CR_20_1, + MSEL1CR_19_0, MSEL1CR_19_1, + MSEL1CR_18_0, MSEL1CR_18_1, + MSEL1CR_17_0, MSEL1CR_17_1, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + MSEL1CR_11_0, MSEL1CR_11_1, + MSEL1CR_10_0, MSEL1CR_10_1, + MSEL1CR_09_0, MSEL1CR_09_1, + MSEL1CR_08_0, MSEL1CR_08_1, + MSEL1CR_07_0, MSEL1CR_07_1, + MSEL1CR_06_0, MSEL1CR_06_1, + MSEL1CR_05_0, MSEL1CR_05_1, + MSEL1CR_04_0, MSEL1CR_04_1, + MSEL1CR_03_0, MSEL1CR_03_1, + MSEL1CR_02_0, MSEL1CR_02_1, + MSEL1CR_01_0, MSEL1CR_01_1, + MSEL1CR_00_0, MSEL1CR_00_1, + + MSEL3CR_31_0, MSEL3CR_31_1, + MSEL3CR_28_0, MSEL3CR_28_1, + MSEL3CR_27_0, MSEL3CR_27_1, + MSEL3CR_26_0, MSEL3CR_26_1, + MSEL3CR_23_0, MSEL3CR_23_1, + MSEL3CR_22_0, MSEL3CR_22_1, + MSEL3CR_21_0, MSEL3CR_21_1, + MSEL3CR_20_0, MSEL3CR_20_1, + MSEL3CR_19_0, MSEL3CR_19_1, + MSEL3CR_18_0, MSEL3CR_18_1, + MSEL3CR_17_0, MSEL3CR_17_1, + MSEL3CR_16_0, MSEL3CR_16_1, + MSEL3CR_15_0, MSEL3CR_15_1, + MSEL3CR_12_0, MSEL3CR_12_1, + MSEL3CR_11_0, MSEL3CR_11_1, + MSEL3CR_10_0, MSEL3CR_10_1, + MSEL3CR_09_0, MSEL3CR_09_1, + MSEL3CR_06_0, MSEL3CR_06_1, + MSEL3CR_03_0, MSEL3CR_03_1, + MSEL3CR_01_0, MSEL3CR_01_1, + MSEL3CR_00_0, MSEL3CR_00_1, + + MSEL4CR_30_0, MSEL4CR_30_1, + MSEL4CR_29_0, MSEL4CR_29_1, + MSEL4CR_28_0, MSEL4CR_28_1, + MSEL4CR_27_0, MSEL4CR_27_1, + MSEL4CR_26_0, MSEL4CR_26_1, + MSEL4CR_25_0, MSEL4CR_25_1, + MSEL4CR_24_0, MSEL4CR_24_1, + MSEL4CR_23_0, MSEL4CR_23_1, + MSEL4CR_22_0, MSEL4CR_22_1, + MSEL4CR_21_0, MSEL4CR_21_1, + MSEL4CR_20_0, MSEL4CR_20_1, + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_17_0, MSEL4CR_17_1, + MSEL4CR_16_0, MSEL4CR_16_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_14_0, MSEL4CR_14_1, + MSEL4CR_13_0, MSEL4CR_13_1, + MSEL4CR_12_0, MSEL4CR_12_1, + MSEL4CR_11_0, MSEL4CR_11_1, + MSEL4CR_10_0, MSEL4CR_10_1, + MSEL4CR_09_0, MSEL4CR_09_1, + MSEL4CR_07_0, MSEL4CR_07_1, + MSEL4CR_04_0, MSEL4CR_04_1, + MSEL4CR_01_0, MSEL4CR_01_1, + + MSEL5CR_31_0, MSEL5CR_31_1, + MSEL5CR_30_0, MSEL5CR_30_1, + MSEL5CR_29_0, MSEL5CR_29_1, + MSEL5CR_28_0, MSEL5CR_28_1, + MSEL5CR_27_0, MSEL5CR_27_1, + MSEL5CR_26_0, MSEL5CR_26_1, + MSEL5CR_25_0, MSEL5CR_25_1, + MSEL5CR_24_0, MSEL5CR_24_1, + MSEL5CR_23_0, MSEL5CR_23_1, + MSEL5CR_22_0, MSEL5CR_22_1, + MSEL5CR_21_0, MSEL5CR_21_1, + MSEL5CR_20_0, MSEL5CR_20_1, + MSEL5CR_19_0, MSEL5CR_19_1, + MSEL5CR_18_0, MSEL5CR_18_1, + MSEL5CR_17_0, MSEL5CR_17_1, + MSEL5CR_16_0, MSEL5CR_16_1, + MSEL5CR_15_0, MSEL5CR_15_1, + MSEL5CR_14_0, MSEL5CR_14_1, + MSEL5CR_13_0, MSEL5CR_13_1, + MSEL5CR_12_0, MSEL5CR_12_1, + MSEL5CR_11_0, MSEL5CR_11_1, + MSEL5CR_10_0, MSEL5CR_10_1, + MSEL5CR_09_0, MSEL5CR_09_1, + MSEL5CR_08_0, MSEL5CR_08_1, + MSEL5CR_07_0, MSEL5CR_07_1, + MSEL5CR_06_0, MSEL5CR_06_1, + + MSEL8CR_16_0, MSEL8CR_16_1, + MSEL8CR_01_0, MSEL8CR_01_1, + MSEL8CR_00_0, MSEL8CR_00_1, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + +#define F1(a) a##_MARK +#define F2(a) a##_MARK +#define F3(a) a##_MARK +#define F4(a) a##_MARK +#define F5(a) a##_MARK +#define F6(a) a##_MARK +#define F7(a) a##_MARK +#define IRQ(a) IRQ##a##_MARK + + F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */ + F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1), + F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2), + F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3), + F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4), + F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5), + F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6), + F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7), + F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8), + F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9), + F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */ + F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11), + F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12), + F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13), + F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14), + F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15), + F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0), + F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1), + F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2), + F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3), + F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */ + F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5), + F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6), + F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7), + F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24), + F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N), + F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N), + F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN), + F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT), + F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB), + F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE), + F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */ + + F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */ + F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS), + F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK), + F1(SCIFA1_RTS), F7(CSCIF1_RTS), + F1(SCIFA1_CTS), F7(CSCIF1_CTS), + F1(SCIFA1_SCK), F7(CSCIF1_SCK), + F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS), + F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS), + F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40), + F7(CHSCIF0_HSCK), /* Port40 */ + + F1(PDM0_DATA), /* Port64 */ + F1(PDM1_DATA), + F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4), + IRQ(40), + F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX), + F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68), + F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69), + F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0), + F7(CHSCIF1_HRTS), /* Port70 */ + F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1), + F7(CHSCIF1_HCTS), + F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX), + F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73), + F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0), + F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */ + F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */ + + F1(KEYIN0), /* Port96 */ + F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */ + F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42), + F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3), + F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */ + F2(KEYOUT7), F5(RFANAEN), IRQ(45), + F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46), + F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47), + F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48), + F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49), + F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX), + F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX), + F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */ + F3(SF_PORT_0_121), F4(SCIFB3_TXD_121), + F1(SCIFB0_TXD), F7(CHSCIF0_HTX), + F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124), + F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0), + F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1), + F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC), + F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1), + F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD), + F5(SIM0_VOLTSEL1), /* Port130 */ + F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK), + F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK), + F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1), + IRQ(20), /* Port160 */ + IRQ(21), IRQ(22), IRQ(23), + F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3), + F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */ + F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST), + IRQ(24), IRQ(25), IRQ(26), IRQ(27), + F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */ + F1(A9), F2(MMCD1_6), IRQ(32), + F1(A8), F2(MMCD1_5), IRQ(33), + F1(A7), F2(MMCD1_4), IRQ(34), + F1(A6), F2(MMCD1_3), IRQ(35), + F1(A5), F2(MMCD1_2), IRQ(36), + F1(A4), F2(MMCD1_1), IRQ(37), + F1(A3), F2(MMCD1_0), IRQ(38), + F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */ + F1(A1), + F1(A0), F2(BS), + F1(CKO), F2(MMCCLK1), + F1(CS0_N), F5(SIM0_GPO1), + F1(CS2_N), F5(SIM0_GPO2), + F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0), + F1(D15), F5(GIO_OUT15), + F1(D14), F5(GIO_OUT14), + F1(D13), F5(GIO_OUT13), + F1(D12), F5(GIO_OUT12), /* Port210 */ + F1(D11), F5(WGM_TXP2), + F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK), + F1(D9), F2(VIO_D9), F5(GIO_OUT9), + F1(D8), F2(VIO_D8), F5(GIO_OUT8), + F1(D7), F2(VIO_D7), F5(GIO_OUT7), + F1(D6), F2(VIO_D6), F5(GIO_OUT6), + F1(D5), F2(VIO_D5), F5(GIO_OUT5_217), + F1(D4), F2(VIO_D4), F5(GIO_OUT4_218), + F1(D3), F2(VIO_D3), F5(GIO_OUT3_219), + F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */ + F1(D1), F2(VIO_D1), F5(GIO_OUT1_221), + F1(D0), F2(VIO_D0), F5(GIO_OUT0_222), + F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2), + F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1), + F1(WE0_N), F2(RDWR_227), + F1(WE1_N), F5(SIM0_GPO0), + F1(PWMO), F2(VIO_CKO1_229), + F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */ + F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232), + F2(VIO_CKO3_233), F4(SF_PORT_1_233), + F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234), + F1(FSIAISLD), F2(PDM3_DATA_235), + F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236), + F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT), + F1(FSIAOSLD), F2(PDM0_OUTDATA_239), + F1(FSIBISLD), /* Port240 */ + F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242), + F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF), + F1(FSIBCK), F3(ISP_SHUTTER0_245), + F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248), + F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */ + F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2), + F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */ + F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262), + F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD), + F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1), + F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK), + F1(MSIOF1_SYNC), F4(MSIOF5_SYNC), + F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */ + F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272), + F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0), + F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP), + F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */ + F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282), + F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2), + F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */ + F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2), + F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2), + F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD), + F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52), + F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD), + F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC), + F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK), + F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300), + F4(MSIOF6_SS1), /* Port300 */ + F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1), + F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1), + F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1), + F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */ + IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54), + IRQ(55), IRQ(56), IRQ(57), + PINMUX_MARK_END, +}; + +static const u16 pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + PINMUX_DATA_ALL(), + + /* Port0 */ + PINMUX_DATA(LCDD0_MARK, PORT0_FN1), + PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3), + PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7), + PINMUX_DATA(IRQ0_MARK, PORT0_FN0), + + /* Port1 */ + PINMUX_DATA(LCDD1_MARK, PORT1_FN1), + PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0), + PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7), + PINMUX_DATA(IRQ1_MARK, PORT1_FN0), + + /* Port2 */ + PINMUX_DATA(LCDD2_MARK, PORT2_FN1), + PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3), + PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7), + PINMUX_DATA(IRQ2_MARK, PORT2_FN0), + + /* Port3 */ + PINMUX_DATA(LCDD3_MARK, PORT3_FN1), + PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0), + PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7), + PINMUX_DATA(IRQ3_MARK, PORT3_FN0), + + /* Port4 */ + PINMUX_DATA(LCDD4_MARK, PORT4_FN1), + PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3), + PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7), + PINMUX_DATA(IRQ4_MARK, PORT4_FN0), + + /* Port5 */ + PINMUX_DATA(LCDD5_MARK, PORT5_FN1), + PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0), + PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7), + PINMUX_DATA(IRQ5_MARK, PORT5_FN0), + + /* Port6 */ + PINMUX_DATA(LCDD6_MARK, PORT6_FN1), + PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3), + PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7), + PINMUX_DATA(IRQ6_MARK, PORT6_FN0), + + /* Port7 */ + PINMUX_DATA(LCDD7_MARK, PORT7_FN1), + PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3), + PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7), + PINMUX_DATA(IRQ7_MARK, PORT7_FN0), + + /* Port8 */ + PINMUX_DATA(LCDD8_MARK, PORT8_FN1), + PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3), + PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7), + PINMUX_DATA(IRQ8_MARK, PORT8_FN0), + + /* Port9 */ + PINMUX_DATA(LCDD9_MARK, PORT9_FN1), + PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3), + PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7), + PINMUX_DATA(IRQ9_MARK, PORT9_FN0), + + /* Port10 */ + PINMUX_DATA(LCDD10_MARK, PORT10_FN1), + PINMUX_DATA(FSICCK_MARK, PORT10_FN3), + PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7), + PINMUX_DATA(IRQ10_MARK, PORT10_FN0), + + /* Port11 */ + PINMUX_DATA(LCDD11_MARK, PORT11_FN1), + PINMUX_DATA(FSICISLD_MARK, PORT11_FN3), + PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7), + PINMUX_DATA(IRQ11_MARK, PORT11_FN0), + + /* Port12 */ + PINMUX_DATA(LCDD12_MARK, PORT12_FN1), + PINMUX_DATA(FSICOMC_MARK, PORT12_FN3), + PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7), + PINMUX_DATA(IRQ12_MARK, PORT12_FN0), + + /* Port13 */ + PINMUX_DATA(LCDD13_MARK, PORT13_FN1), + PINMUX_DATA(FSICOLR_MARK, PORT13_FN3), + PINMUX_DATA(FSICILR_MARK, PORT13_FN4), + PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7), + PINMUX_DATA(IRQ13_MARK, PORT13_FN0), + + /* Port14 */ + PINMUX_DATA(LCDD14_MARK, PORT14_FN1), + PINMUX_DATA(FSICOBT_MARK, PORT14_FN3), + PINMUX_DATA(FSICIBT_MARK, PORT14_FN4), + PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7), + PINMUX_DATA(IRQ14_MARK, PORT14_FN0), + + /* Port15 */ + PINMUX_DATA(LCDD15_MARK, PORT15_FN1), + PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3), + PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7), + PINMUX_DATA(IRQ15_MARK, PORT15_FN0), + + /* Port16 */ + PINMUX_DATA(LCDD16_MARK, PORT16_FN1), + PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4), + PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7), + + /* Port17 */ + PINMUX_DATA(LCDD17_MARK, PORT17_FN1), + PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4), + PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7), + + /* Port18 */ + PINMUX_DATA(LCDD18_MARK, PORT18_FN1), + PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4), + PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7), + + /* Port19 */ + PINMUX_DATA(LCDD19_MARK, PORT19_FN1), + PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3), + PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7), + + /* Port20 */ + PINMUX_DATA(LCDD20_MARK, PORT20_FN1), + PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0), + PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7), + + /* Port21 */ + PINMUX_DATA(LCDD21_MARK, PORT21_FN1), + PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0), + PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7), + + /* Port22 */ + PINMUX_DATA(LCDD22_MARK, PORT22_FN1), + PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0), + PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7), + + /* Port23 */ + PINMUX_DATA(LCDD23_MARK, PORT23_FN1), + PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3), + PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7), + + /* Port24 */ + PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1), + PINMUX_DATA(LCDCS_MARK, PORT24_FN2), + PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3), + PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7), + + /* Port25 */ + PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1), + PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0), + PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7), + + /* Port26 */ + PINMUX_DATA(LCDDCK_MARK, PORT26_FN1), + PINMUX_DATA(LCDWR_MARK, PORT26_FN2), + PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0), + PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7), + + /* Port27 */ + PINMUX_DATA(LCDDISP_MARK, PORT27_FN1), + PINMUX_DATA(LCDRS_MARK, PORT27_FN2), + PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0), + PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7), + + /* Port28 */ + PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1), + PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3), + PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7), + + /* Port29 */ + PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1), + PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4), + PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7), + + /* Port30 */ + PINMUX_DATA(LCDDON_MARK, PORT30_FN1), + PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4), + PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7), + + /* Port32 */ + PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1), + PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5), + PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7), + + /* Port33 */ + PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1), + PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5), + PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7), + + /* Port34 */ + PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1), + PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5), + PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7), + + /* Port35 */ + PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1), + PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7), + + /* Port36 */ + PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1), + PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7), + + /* Port37 */ + PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1), + PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7), + + /* Port38 */ + PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1), + PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3), + PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4), + PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7), + + /* Port39 */ + PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1), + PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3), + PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1), + PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7), + + /* Port40 */ + PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1), + PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3), + PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4), + PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7), + + /* Port64 */ + PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1), + + /* Port65 */ + PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1), + + /* Port66 */ + PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1), + PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0), + PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3), + PINMUX_DATA(GenIO4_MARK, PORT66_FN5), + PINMUX_DATA(IRQ40_MARK, PORT66_FN0), + + /* Port67 */ + PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1), + PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1), + PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5), + PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7), + + /* Port68 */ + PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1), + PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0), + PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3), + PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5), + + /* Port69 */ + PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1), + PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0), + PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3), + PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5), + + /* Port70 */ + PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1), + PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2), + PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5), + PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6), + PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7), + + /* Port71 */ + PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1), + PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1), + PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5), + PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6), + PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7), + + /* Port72 */ + PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1), + PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1), + PINMUX_DATA(GenIO8_MARK, PORT72_FN5), + PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7), + + /* Port73 */ + PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1), + PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2), + PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3), + PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5), + + /* Port74 - Port85 */ + PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1), + PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1), + PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1), + PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1), + PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1), + PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1), + PINMUX_DATA(TXP_MARK, PORT80_FN1), + PINMUX_DATA(TXP2_MARK, PORT81_FN1), + PINMUX_DATA(COEX_0_MARK, PORT82_FN1), + PINMUX_DATA(COEX_1_MARK, PORT83_FN1), + PINMUX_DATA(IRQ19_MARK, PORT84_FN0), + PINMUX_DATA(IRQ18_MARK, PORT85_FN0), + + /* Port96 - Port101 */ + PINMUX_DATA(KEYIN0_MARK, PORT96_FN1), + PINMUX_DATA(KEYIN1_MARK, PORT97_FN1), + PINMUX_DATA(KEYIN2_MARK, PORT98_FN1), + PINMUX_DATA(KEYIN3_MARK, PORT99_FN1), + PINMUX_DATA(KEYIN4_MARK, PORT100_FN1), + PINMUX_DATA(KEYIN5_MARK, PORT101_FN1), + + /* Port102 */ + PINMUX_DATA(KEYIN6_MARK, PORT102_FN1), + PINMUX_DATA(IRQ41_MARK, PORT102_FN0), + + /* Port103 */ + PINMUX_DATA(KEYIN7_MARK, PORT103_FN1), + PINMUX_DATA(IRQ42_MARK, PORT103_FN0), + + /* Port104 - Port108 */ + PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2), + PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2), + PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2), + PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2), + PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2), + + /* Port109 */ + PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2), + PINMUX_DATA(IRQ43_MARK, PORT109_FN0), + + /* Port110 */ + PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2), + PINMUX_DATA(IRQ44_MARK, PORT110_FN0), + + /* Port111 */ + PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2), + PINMUX_DATA(RFANAEN_MARK, PORT111_FN5), + PINMUX_DATA(IRQ45_MARK, PORT111_FN0), + + /* Port112 */ + PINMUX_DATA(KEYIN8_MARK, PORT112_FN1), + PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2), + PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4), + PINMUX_DATA(IRQ46_MARK, PORT112_FN0), + + /* Port113 */ + PINMUX_DATA(KEYIN9_MARK, PORT113_FN1), + PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2), + PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4), + PINMUX_DATA(IRQ47_MARK, PORT113_FN0), + + /* Port114 */ + PINMUX_DATA(KEYIN10_MARK, PORT114_FN1), + PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2), + PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4), + PINMUX_DATA(IRQ48_MARK, PORT114_FN0), + + /* Port115 */ + PINMUX_DATA(KEYIN11_MARK, PORT115_FN1), + PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2), + PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4), + PINMUX_DATA(IRQ49_MARK, PORT115_FN0), + + /* Port116 */ + PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1), + PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7), + + /* Port117 */ + PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1), + PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7), + + /* Port118 */ + PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1), + PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7), + + /* Port119 */ + PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1), + PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7), + + /* Port120 */ + PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3), + PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1), + PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7), + + /* Port121 */ + PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3), + PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1), + + /* Port122 */ + PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1), + PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7), + + /* Port123 */ + PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1), + PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7), + + /* Port124 */ + PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3), + + /* Port125 */ + PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1), + PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2), + PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3), + PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5), + + /* Port126 */ + PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1), + PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2), + PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3), + + /* Port128 */ + PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1), + PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2), + PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3), + PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5), + + /* Port129 */ + PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1), + PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2), + PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3), + + /* Port130 */ + PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1), + PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1), + PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3), + PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5), + + /* Port131 */ + PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1), + PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5), + + /* Port132 */ + PINMUX_DATA(TS_SCK_MARK, PORT132_FN1), + PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2), + PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3), + + /* Port133 */ + PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1), + PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2), + PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3), + PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5), + + /* Port134 */ + PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1), + PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2), + PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3), + + /* Port160 - Port178 */ + PINMUX_DATA(IRQ20_MARK, PORT160_FN0), + PINMUX_DATA(IRQ21_MARK, PORT161_FN0), + PINMUX_DATA(IRQ22_MARK, PORT162_FN0), + PINMUX_DATA(IRQ23_MARK, PORT163_FN0), + PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1), + PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1), + PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1), + PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1), + PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1), + PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1), + PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1), + PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1), + PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1), + PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1), + PINMUX_DATA(MMCRST_MARK, PORT174_FN1), + PINMUX_DATA(IRQ24_MARK, PORT175_FN0), + PINMUX_DATA(IRQ25_MARK, PORT176_FN0), + PINMUX_DATA(IRQ26_MARK, PORT177_FN0), + PINMUX_DATA(IRQ27_MARK, PORT178_FN0), + + /* Port192 - Port200 FN1 */ + PINMUX_DATA(A10_MARK, PORT192_FN1), + PINMUX_DATA(A9_MARK, PORT193_FN1), + PINMUX_DATA(A8_MARK, PORT194_FN1), + PINMUX_DATA(A7_MARK, PORT195_FN1), + PINMUX_DATA(A6_MARK, PORT196_FN1), + PINMUX_DATA(A5_MARK, PORT197_FN1), + PINMUX_DATA(A4_MARK, PORT198_FN1), + PINMUX_DATA(A3_MARK, PORT199_FN1), + PINMUX_DATA(A2_MARK, PORT200_FN1), + + /* Port192 - Port200 FN2 */ + PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2), + PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2), + PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2), + PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2), + PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2), + PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2), + PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2), + PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2), + PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2), + + /* Port192 - Port200 IRQ */ + PINMUX_DATA(IRQ31_MARK, PORT192_FN0), + PINMUX_DATA(IRQ32_MARK, PORT193_FN0), + PINMUX_DATA(IRQ33_MARK, PORT194_FN0), + PINMUX_DATA(IRQ34_MARK, PORT195_FN0), + PINMUX_DATA(IRQ35_MARK, PORT196_FN0), + PINMUX_DATA(IRQ36_MARK, PORT197_FN0), + PINMUX_DATA(IRQ37_MARK, PORT198_FN0), + PINMUX_DATA(IRQ38_MARK, PORT199_FN0), + PINMUX_DATA(IRQ39_MARK, PORT200_FN0), + + /* Port201 */ + PINMUX_DATA(A1_MARK, PORT201_FN1), + + /* Port202 */ + PINMUX_DATA(A0_MARK, PORT202_FN1), + PINMUX_DATA(BS_MARK, PORT202_FN2), + + /* Port203 */ + PINMUX_DATA(CKO_MARK, PORT203_FN1), + PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2), + + /* Port204 */ + PINMUX_DATA(CS0_N_MARK, PORT204_FN1), + PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5), + + /* Port205 */ + PINMUX_DATA(CS2_N_MARK, PORT205_FN1), + PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5), + + /* Port206 */ + PINMUX_DATA(CS4_N_MARK, PORT206_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT206_FN2), + PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5), + + /* Port207 - Port212 FN1 */ + PINMUX_DATA(D15_MARK, PORT207_FN1), + PINMUX_DATA(D14_MARK, PORT208_FN1), + PINMUX_DATA(D13_MARK, PORT209_FN1), + PINMUX_DATA(D12_MARK, PORT210_FN1), + PINMUX_DATA(D11_MARK, PORT211_FN1), + PINMUX_DATA(D10_MARK, PORT212_FN1), + + /* Port207 - Port212 FN5 */ + PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5), + PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5), + PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5), + PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5), + PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5), + PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5), + + /* Port213 - Port222 FN1 */ + PINMUX_DATA(D9_MARK, PORT213_FN1), + PINMUX_DATA(D8_MARK, PORT214_FN1), + PINMUX_DATA(D7_MARK, PORT215_FN1), + PINMUX_DATA(D6_MARK, PORT216_FN1), + PINMUX_DATA(D5_MARK, PORT217_FN1), + PINMUX_DATA(D4_MARK, PORT218_FN1), + PINMUX_DATA(D3_MARK, PORT219_FN1), + PINMUX_DATA(D2_MARK, PORT220_FN1), + PINMUX_DATA(D1_MARK, PORT221_FN1), + PINMUX_DATA(D0_MARK, PORT222_FN1), + + /* Port213 - Port222 FN2 */ + PINMUX_DATA(VIO_D9_MARK, PORT213_FN2), + PINMUX_DATA(VIO_D8_MARK, PORT214_FN2), + PINMUX_DATA(VIO_D7_MARK, PORT215_FN2), + PINMUX_DATA(VIO_D6_MARK, PORT216_FN2), + PINMUX_DATA(VIO_D5_MARK, PORT217_FN2), + PINMUX_DATA(VIO_D4_MARK, PORT218_FN2), + PINMUX_DATA(VIO_D3_MARK, PORT219_FN2), + PINMUX_DATA(VIO_D2_MARK, PORT220_FN2), + PINMUX_DATA(VIO_D1_MARK, PORT221_FN2), + PINMUX_DATA(VIO_D0_MARK, PORT222_FN2), + + /* Port213 - Port222 FN5 */ + PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5), + PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5), + PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5), + PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5), + PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5), + PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5), + PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5), + PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5), + PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5), + PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5), + + /* Port224 */ + PINMUX_DATA(RDWR_224_MARK, PORT224_FN1), + PINMUX_DATA(VIO_HD_MARK, PORT224_FN2), + PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5), + + /* Port225 */ + PINMUX_DATA(RD_N_MARK, PORT225_FN1), + + /* Port226 */ + PINMUX_DATA(WAIT_N_MARK, PORT226_FN1), + PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2), + PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5), + + /* Port227 */ + PINMUX_DATA(WE0_N_MARK, PORT227_FN1), + PINMUX_DATA(RDWR_227_MARK, PORT227_FN2), + + /* Port228 */ + PINMUX_DATA(WE1_N_MARK, PORT228_FN1), + PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5), + + /* Port229 */ + PINMUX_DATA(PWMO_MARK, PORT229_FN1), + PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2), + + /* Port230 */ + PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1), + PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2), + + /* Port231 */ + PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1), + PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2), + + /* Port232 */ + PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2), + PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4), + + /* Port233 */ + PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2), + PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4), + + /* Port234 */ + PINMUX_DATA(FSIACK_MARK, PORT234_FN1), + PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2), + PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3), + + /* Port235 */ + PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1), + PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1), + + /* Port236 */ + PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1), + PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2), + PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3), + + /* Port237 */ + PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1), + PINMUX_DATA(FSIAILR_MARK, PORT237_FN2), + + /* Port238 */ + PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1), + PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2), + + /* Port239 */ + PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1), + PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2), + + /* Port240 */ + PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1), + + /* Port241 */ + PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1), + PINMUX_DATA(FSIBILR_MARK, PORT241_FN2), + + /* Port242 */ + PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1), + PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3), + + /* Port243 */ + PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1), + PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2), + + /* Port244 */ + PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1), + PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2), + + /* Port245 */ + PINMUX_DATA(FSIBCK_MARK, PORT245_FN1), + PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3), + + /* Port246 - Port250 FN1 */ + PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1), + PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1), + PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1), + PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1), + PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1), + + /* Port256 - Port258 */ + PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1), + PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1), + + /* Port259 */ + PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1), + PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3), + + /* Port260 */ + PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1), + + /* Port261 */ + PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2), + PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7), + + /* Port262 */ + PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2), + + /* Port263 - Port266 FN1 */ + PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1), + PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1), + PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1), + PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1), + + /* Port263 - Port266 FN4 */ + PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4), + PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4), + PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4), + PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4), + + /* Port267 */ + PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1), + + /* Port268 */ + PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1), + PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4), + + /* Port269 */ + PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1), + PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4), + + /* Port270 - Port273 FN1 */ + PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1), + PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1), + PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1), + PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1), + + /* Port270 - Port273 FN3 */ + PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3), + PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3), + PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3), + PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3), + + /* Port274 */ + PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1), + PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4), + + /* Port275 - Port280 */ + PINMUX_DATA(IC_DP_MARK, PORT275_FN1), + PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1), + PINMUX_DATA(IC_DM_MARK, PORT277_FN1), + PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1), + PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1), + PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1), + + /* Port281 */ + PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1), + PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1), + + /* Port282 */ + PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1), + PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2), + + /* Port283 */ + PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1), + + /* Port289 */ + PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1), + PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3), + + /* Port290 */ + PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1), + PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3), + PINMUX_DATA(IRQ51_MARK, PORT290_FN0), + + /* Port291 - Port294 FN1 */ + PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1), + PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1), + PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1), + PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1), + + /* Port291 - Port294 FN3 */ + PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3), + PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3), + PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3), + PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3), + + /* Port295 */ + PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1), + PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2), + PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1), + PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4), + + /* Port296 */ + PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1), + PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4), + PINMUX_DATA(IRQ52_MARK, PORT296_FN0), + + /* Port297 - Port300 FN1 */ + PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1), + PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1), + PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1), + PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1), + + /* Port297 - Port300 FN2 */ + PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2), + PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2), + PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2), + PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2), + + /* Port297 - Port300 FN3 */ + PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1), + PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1), + PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3), + PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3), + + /* Port297 - Port300 FN4 */ + PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4), + PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4), + PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4), + PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4), + + /* Port301 */ + PINMUX_DATA(SDHICD0_MARK, PORT301_FN1), + PINMUX_DATA(IRQ50_MARK, PORT301_FN0), + + /* Port302 - Port306 FN1 */ + PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1), + PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1), + PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1), + PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1), + PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1), + + /* Port302 - Port306 FN3 */ + PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3), + PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3), + PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3), + PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3), + PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3), + + /* Port307 */ + PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1), + + /* Port308 */ + PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1), + PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3), + + /* Port320 - Port329 */ + PINMUX_DATA(IRQ16_MARK, PORT320_FN0), + PINMUX_DATA(IRQ17_MARK, PORT321_FN0), + PINMUX_DATA(IRQ28_MARK, PORT322_FN0), + PINMUX_DATA(IRQ29_MARK, PORT323_FN0), + PINMUX_DATA(IRQ30_MARK, PORT324_FN0), + PINMUX_DATA(IRQ53_MARK, PORT325_FN0), + PINMUX_DATA(IRQ54_MARK, PORT326_FN0), + PINMUX_DATA(IRQ55_MARK, PORT327_FN0), + PINMUX_DATA(IRQ56_MARK, PORT328_FN0), + PINMUX_DATA(IRQ57_MARK, PORT329_FN0), +}; + +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) +#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) + +static const struct sh_pfc_pin pinmux_pins[] = { + R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1), + R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3), + R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5), + R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7), + R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9), + R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11), + R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13), + R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15), + R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17), + R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19), + R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21), + R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23), + R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25), + R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27), + R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29), + R8A73A4_PIN_IO_PU_PD(30), + R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33), + R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35), + R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37), + R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39), + R8A73A4_PIN_IO_PU_PD(40), + R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65), + R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67), + R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69), + R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71), + R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73), + R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75), + R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77), + R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79), + R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81), + R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83), + R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85), + R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97), + R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99), + R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101), + R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103), + R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105), + R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107), + R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109), + R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111), + R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113), + R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115), + R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117), + R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119), + R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121), + R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123), + R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125), + R8A73A4_PIN_IO_PU_PD(126), + R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129), + R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131), + R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133), + R8A73A4_PIN_IO_PU_PD(134), + R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161), + R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163), + R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165), + R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167), + R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169), + R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171), + R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173), + R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175), + R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177), + R8A73A4_PIN_IO_PU_PD(178), + R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193), + R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195), + R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197), + R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199), + R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201), + R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203), + R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205), + R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207), + R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209), + R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211), + R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213), + R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215), + R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217), + R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219), + R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221), + R8A73A4_PIN_IO_PU_PD(222), + R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225), + R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227), + R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229), + R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231), + R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233), + R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235), + R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237), + R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239), + R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241), + R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243), + R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245), + R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247), + R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249), + R8A73A4_PIN_IO_PU_PD(250), + R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257), + R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259), + R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261), + R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263), + R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265), + R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267), + R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269), + R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271), + R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273), + R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275), + R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277), + R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279), + R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281), + R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283), + R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289), + R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291), + R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293), + R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295), + R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297), + R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299), + R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301), + R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303), + R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305), + R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307), + R8A73A4_PIN_IO_PU_PD(308), + R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321), + R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323), + R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325), + R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327), + R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329), +}; + +/* - IRQC ------------------------------------------------------------------- */ +#define IRQC_PINS_MUX(pin, irq_mark) \ +static const unsigned int irqc_irq##irq_mark##_pins[] = { \ + pin, \ +}; \ +static const unsigned int irqc_irq##irq_mark##_mux[] = { \ + IRQ##irq_mark##_MARK, \ +} +IRQC_PINS_MUX(0, 0); +IRQC_PINS_MUX(1, 1); +IRQC_PINS_MUX(2, 2); +IRQC_PINS_MUX(3, 3); +IRQC_PINS_MUX(4, 4); +IRQC_PINS_MUX(5, 5); +IRQC_PINS_MUX(6, 6); +IRQC_PINS_MUX(7, 7); +IRQC_PINS_MUX(8, 8); +IRQC_PINS_MUX(9, 9); +IRQC_PINS_MUX(10, 10); +IRQC_PINS_MUX(11, 11); +IRQC_PINS_MUX(12, 12); +IRQC_PINS_MUX(13, 13); +IRQC_PINS_MUX(14, 14); +IRQC_PINS_MUX(15, 15); +IRQC_PINS_MUX(66, 40); +IRQC_PINS_MUX(84, 19); +IRQC_PINS_MUX(85, 18); +IRQC_PINS_MUX(102, 41); +IRQC_PINS_MUX(103, 42); +IRQC_PINS_MUX(109, 43); +IRQC_PINS_MUX(110, 44); +IRQC_PINS_MUX(111, 45); +IRQC_PINS_MUX(112, 46); +IRQC_PINS_MUX(113, 47); +IRQC_PINS_MUX(114, 48); +IRQC_PINS_MUX(115, 49); +IRQC_PINS_MUX(160, 20); +IRQC_PINS_MUX(161, 21); +IRQC_PINS_MUX(162, 22); +IRQC_PINS_MUX(163, 23); +IRQC_PINS_MUX(175, 24); +IRQC_PINS_MUX(176, 25); +IRQC_PINS_MUX(177, 26); +IRQC_PINS_MUX(178, 27); +IRQC_PINS_MUX(192, 31); +IRQC_PINS_MUX(193, 32); +IRQC_PINS_MUX(194, 33); +IRQC_PINS_MUX(195, 34); +IRQC_PINS_MUX(196, 35); +IRQC_PINS_MUX(197, 36); +IRQC_PINS_MUX(198, 37); +IRQC_PINS_MUX(199, 38); +IRQC_PINS_MUX(200, 39); +IRQC_PINS_MUX(290, 51); +IRQC_PINS_MUX(296, 52); +IRQC_PINS_MUX(301, 50); +IRQC_PINS_MUX(320, 16); +IRQC_PINS_MUX(321, 17); +IRQC_PINS_MUX(322, 28); +IRQC_PINS_MUX(323, 29); +IRQC_PINS_MUX(324, 30); +IRQC_PINS_MUX(325, 53); +IRQC_PINS_MUX(326, 54); +IRQC_PINS_MUX(327, 55); +IRQC_PINS_MUX(328, 56); +IRQC_PINS_MUX(329, 57); +/* - MMCIF0 ----------------------------------------------------------------- */ +static const unsigned int mmc0_data1_pins[] = { + /* D[0] */ + 164, +}; +static const unsigned int mmc0_data1_mux[] = { + MMCD0_0_MARK, +}; +static const unsigned int mmc0_data4_pins[] = { + /* D[0:3] */ + 164, 165, 166, 167, +}; +static const unsigned int mmc0_data4_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, +}; +static const unsigned int mmc0_data8_pins[] = { + /* D[0:7] */ + 164, 165, 166, 167, 168, 169, 170, 171, +}; +static const unsigned int mmc0_data8_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, + MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, +}; +static const unsigned int mmc0_ctrl_pins[] = { + /* CMD, CLK */ + 172, 173, +}; +static const unsigned int mmc0_ctrl_mux[] = { + MMCCMD0_MARK, MMCCLK0_MARK, +}; +/* - MMCIF1 ----------------------------------------------------------------- */ +static const unsigned int mmc1_data1_pins[] = { + /* D[0] */ + 199, +}; +static const unsigned int mmc1_data1_mux[] = { + MMCD1_0_MARK, +}; +static const unsigned int mmc1_data4_pins[] = { + /* D[0:3] */ + 199, 198, 197, 196, +}; +static const unsigned int mmc1_data4_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, +}; +static const unsigned int mmc1_data8_pins[] = { + /* D[0:7] */ + 199, 198, 197, 196, 195, 194, 193, 192, +}; +static const unsigned int mmc1_data8_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, + MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, +}; +static const unsigned int mmc1_ctrl_pins[] = { + /* CMD, CLK */ + 200, 203, +}; +static const unsigned int mmc1_ctrl_mux[] = { + MMCCMD1_MARK, MMCCLK1_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* SCIFA0_RXD, SCIFA0_TXD */ + 117, 116, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCIFA0_SCK */ + 34, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* SCIFA0_RTS, SCIFA0_CTS */ + 32, 33, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* SCIFA1_RXD, SCIFA1_TXD */ + 119, 118, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCIFA1_SCK */ + 37, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* SCIFA1_RTS, SCIFA1_CTS */ + 35, 36, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, +}; +/* - SCIFB0 ----------------------------------------------------------------- */ +static const unsigned int scifb0_data_pins[] = { + /* SCIFB0_RXD, SCIFB0_TXD */ + 123, 122, +}; +static const unsigned int scifb0_data_mux[] = { + SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, +}; +static const unsigned int scifb0_clk_pins[] = { + /* SCIFB0_SCK */ + 40, +}; +static const unsigned int scifb0_clk_mux[] = { + SCIFB0_SCK_MARK, +}; +static const unsigned int scifb0_ctrl_pins[] = { + /* SCIFB0_RTS, SCIFB0_CTS */ + 38, 39, +}; +static const unsigned int scifb0_ctrl_mux[] = { + SCIFB0_RTS_MARK, SCIFB0_CTS_MARK, +}; +/* - SCIFB1 ----------------------------------------------------------------- */ +static const unsigned int scifb1_data_pins[] = { + /* SCIFB1_RXD, SCIFB1_TXD */ + 27, 26, +}; +static const unsigned int scifb1_data_mux[] = { + SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK, +}; +static const unsigned int scifb1_clk_pins[] = { + /* SCIFB1_SCK */ + 28, +}; +static const unsigned int scifb1_clk_mux[] = { + SCIFB1_SCK_28_MARK, +}; +static const unsigned int scifb1_ctrl_pins[] = { + /* SCIFB1_RTS, SCIFB1_CTS */ + 24, 25, +}; +static const unsigned int scifb1_ctrl_mux[] = { + SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK, +}; +static const unsigned int scifb1_data_b_pins[] = { + /* SCIFB1_RXD, SCIFB1_TXD */ + 72, 67, +}; +static const unsigned int scifb1_data_b_mux[] = { + SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK, +}; +static const unsigned int scifb1_clk_b_pins[] = { + /* SCIFB1_SCK */ + 261, +}; +static const unsigned int scifb1_clk_b_mux[] = { + SCIFB1_SCK_261_MARK, +}; +static const unsigned int scifb1_ctrl_b_pins[] = { + /* SCIFB1_RTS, SCIFB1_CTS */ + 70, 71, +}; +static const unsigned int scifb1_ctrl_b_mux[] = { + SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK, +}; +/* - SCIFB2 ----------------------------------------------------------------- */ +static const unsigned int scifb2_data_pins[] = { + /* SCIFB2_RXD, SCIFB2_TXD */ + 69, 68, +}; +static const unsigned int scifb2_data_mux[] = { + SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK, +}; +static const unsigned int scifb2_clk_pins[] = { + /* SCIFB2_SCK */ + 262, +}; +static const unsigned int scifb2_clk_mux[] = { + SCIFB2_SCK_262_MARK, +}; +static const unsigned int scifb2_ctrl_pins[] = { + /* SCIFB2_RTS, SCIFB2_CTS */ + 73, 66, +}; +static const unsigned int scifb2_ctrl_mux[] = { + SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK, +}; +static const unsigned int scifb2_data_b_pins[] = { + /* SCIFB2_RXD, SCIFB2_TXD */ + 297, 295, +}; +static const unsigned int scifb2_data_b_mux[] = { + SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK, +}; +static const unsigned int scifb2_clk_b_pins[] = { + /* SCIFB2_SCK */ + 299, +}; +static const unsigned int scifb2_clk_b_mux[] = { + SCIFB2_SCK_299_MARK, +}; +static const unsigned int scifb2_ctrl_b_pins[] = { + /* SCIFB2_RTS, SCIFB2_CTS */ + 300, 298, +}; +static const unsigned int scifb2_ctrl_b_mux[] = { + SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK, +}; +/* - SCIFB3 ----------------------------------------------------------------- */ +static const unsigned int scifb3_data_pins[] = { + /* SCIFB3_RXD, SCIFB3_TXD */ + 22, 21, +}; +static const unsigned int scifb3_data_mux[] = { + SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK, +}; +static const unsigned int scifb3_clk_pins[] = { + /* SCIFB3_SCK */ + 23, +}; +static const unsigned int scifb3_clk_mux[] = { + SCIFB3_SCK_23_MARK, +}; +static const unsigned int scifb3_ctrl_pins[] = { + /* SCIFB3_RTS, SCIFB3_CTS */ + 19, 20, +}; +static const unsigned int scifb3_ctrl_mux[] = { + SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK, +}; +static const unsigned int scifb3_data_b_pins[] = { + /* SCIFB3_RXD, SCIFB3_TXD */ + 120, 121, +}; +static const unsigned int scifb3_data_b_mux[] = { + SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK, +}; +static const unsigned int scifb3_clk_b_pins[] = { + /* SCIFB3_SCK */ + 40, +}; +static const unsigned int scifb3_clk_b_mux[] = { + SCIFB3_SCK_40_MARK, +}; +static const unsigned int scifb3_ctrl_b_pins[] = { + /* SCIFB3_RTS, SCIFB3_CTS */ + 38, 39, +}; +static const unsigned int scifb3_ctrl_b_mux[] = { + SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + 302, +}; +static const unsigned int sdhi0_data1_mux[] = { + SDHID0_0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + 302, 303, 304, 305, +}; +static const unsigned int sdhi0_data4_mux[] = { + SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + 308, 306, +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SDHICLK0_MARK, SDHICMD0_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + 301, +}; +static const unsigned int sdhi0_cd_mux[] = { + SDHICD0_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + 307, +}; +static const unsigned int sdhi0_wp_mux[] = { + SDHIWP0_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + 289, +}; +static const unsigned int sdhi1_data1_mux[] = { + SDHID1_0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + 289, 290, 291, 292, +}; +static const unsigned int sdhi1_data4_mux[] = { + SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + 293, 294, +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SDHICLK1_MARK, SDHICMD1_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + 295, +}; +static const unsigned int sdhi2_data1_mux[] = { + SDHID2_0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + 295, 296, 297, 298, +}; +static const unsigned int sdhi2_data4_mux[] = { + SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + 299, 300, +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SDHICLK2_MARK, SDHICMD2_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(irqc_irq0), + SH_PFC_PIN_GROUP(irqc_irq1), + SH_PFC_PIN_GROUP(irqc_irq2), + SH_PFC_PIN_GROUP(irqc_irq3), + SH_PFC_PIN_GROUP(irqc_irq4), + SH_PFC_PIN_GROUP(irqc_irq5), + SH_PFC_PIN_GROUP(irqc_irq6), + SH_PFC_PIN_GROUP(irqc_irq7), + SH_PFC_PIN_GROUP(irqc_irq8), + SH_PFC_PIN_GROUP(irqc_irq9), + SH_PFC_PIN_GROUP(irqc_irq10), + SH_PFC_PIN_GROUP(irqc_irq11), + SH_PFC_PIN_GROUP(irqc_irq12), + SH_PFC_PIN_GROUP(irqc_irq13), + SH_PFC_PIN_GROUP(irqc_irq14), + SH_PFC_PIN_GROUP(irqc_irq15), + SH_PFC_PIN_GROUP(irqc_irq16), + SH_PFC_PIN_GROUP(irqc_irq17), + SH_PFC_PIN_GROUP(irqc_irq18), + SH_PFC_PIN_GROUP(irqc_irq19), + SH_PFC_PIN_GROUP(irqc_irq20), + SH_PFC_PIN_GROUP(irqc_irq21), + SH_PFC_PIN_GROUP(irqc_irq22), + SH_PFC_PIN_GROUP(irqc_irq23), + SH_PFC_PIN_GROUP(irqc_irq24), + SH_PFC_PIN_GROUP(irqc_irq25), + SH_PFC_PIN_GROUP(irqc_irq26), + SH_PFC_PIN_GROUP(irqc_irq27), + SH_PFC_PIN_GROUP(irqc_irq28), + SH_PFC_PIN_GROUP(irqc_irq29), + SH_PFC_PIN_GROUP(irqc_irq30), + SH_PFC_PIN_GROUP(irqc_irq31), + SH_PFC_PIN_GROUP(irqc_irq32), + SH_PFC_PIN_GROUP(irqc_irq33), + SH_PFC_PIN_GROUP(irqc_irq34), + SH_PFC_PIN_GROUP(irqc_irq35), + SH_PFC_PIN_GROUP(irqc_irq36), + SH_PFC_PIN_GROUP(irqc_irq37), + SH_PFC_PIN_GROUP(irqc_irq38), + SH_PFC_PIN_GROUP(irqc_irq39), + SH_PFC_PIN_GROUP(irqc_irq40), + SH_PFC_PIN_GROUP(irqc_irq41), + SH_PFC_PIN_GROUP(irqc_irq42), + SH_PFC_PIN_GROUP(irqc_irq43), + SH_PFC_PIN_GROUP(irqc_irq44), + SH_PFC_PIN_GROUP(irqc_irq45), + SH_PFC_PIN_GROUP(irqc_irq46), + SH_PFC_PIN_GROUP(irqc_irq47), + SH_PFC_PIN_GROUP(irqc_irq48), + SH_PFC_PIN_GROUP(irqc_irq49), + SH_PFC_PIN_GROUP(irqc_irq50), + SH_PFC_PIN_GROUP(irqc_irq51), + SH_PFC_PIN_GROUP(irqc_irq52), + SH_PFC_PIN_GROUP(irqc_irq53), + SH_PFC_PIN_GROUP(irqc_irq54), + SH_PFC_PIN_GROUP(irqc_irq55), + SH_PFC_PIN_GROUP(irqc_irq56), + SH_PFC_PIN_GROUP(irqc_irq57), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb3_data), + SH_PFC_PIN_GROUP(scifb3_clk), + SH_PFC_PIN_GROUP(scifb3_ctrl), + SH_PFC_PIN_GROUP(scifb3_data_b), + SH_PFC_PIN_GROUP(scifb3_clk_b), + SH_PFC_PIN_GROUP(scifb3_ctrl_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), +}; + +static const char * const irqc_groups[] = { + "irqc_irq0", + "irqc_irq1", + "irqc_irq2", + "irqc_irq3", + "irqc_irq4", + "irqc_irq5", + "irqc_irq6", + "irqc_irq7", + "irqc_irq8", + "irqc_irq9", + "irqc_irq10", + "irqc_irq11", + "irqc_irq12", + "irqc_irq13", + "irqc_irq14", + "irqc_irq15", + "irqc_irq16", + "irqc_irq17", + "irqc_irq18", + "irqc_irq19", + "irqc_irq20", + "irqc_irq21", + "irqc_irq22", + "irqc_irq23", + "irqc_irq24", + "irqc_irq25", + "irqc_irq26", + "irqc_irq27", + "irqc_irq28", + "irqc_irq29", + "irqc_irq30", + "irqc_irq31", + "irqc_irq32", + "irqc_irq33", + "irqc_irq34", + "irqc_irq35", + "irqc_irq36", + "irqc_irq37", + "irqc_irq38", + "irqc_irq39", + "irqc_irq40", + "irqc_irq41", + "irqc_irq42", + "irqc_irq43", + "irqc_irq44", + "irqc_irq45", + "irqc_irq46", + "irqc_irq47", + "irqc_irq48", + "irqc_irq49", + "irqc_irq50", + "irqc_irq51", + "irqc_irq52", + "irqc_irq53", + "irqc_irq54", + "irqc_irq55", + "irqc_irq56", + "irqc_irq57", +}; + +static const char * const mmc0_groups[] = { + "mmc0_data1", + "mmc0_data4", + "mmc0_data8", + "mmc0_ctrl", +}; + +static const char * const mmc1_groups[] = { + "mmc1_data1", + "mmc1_data4", + "mmc1_data8", + "mmc1_ctrl", +}; + +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; + +static const char * const scifb0_groups[] = { + "scifb0_data", + "scifb0_clk", + "scifb0_ctrl", +}; + +static const char * const scifb1_groups[] = { + "scifb1_data", + "scifb1_clk", + "scifb1_ctrl", + "scifb1_data_b", + "scifb1_clk_b", + "scifb1_ctrl_b", +}; + +static const char * const scifb2_groups[] = { + "scifb2_data", + "scifb2_clk", + "scifb2_ctrl", + "scifb2_data_b", + "scifb2_clk_b", + "scifb2_ctrl_b", +}; + +static const char * const scifb3_groups[] = { + "scifb3_data", + "scifb3_clk", + "scifb3_ctrl", + "scifb3_data_b", + "scifb3_clk_b", + "scifb3_ctrl_b", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(irqc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scifb3), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), + PORTCR(1, 0xe6050001), + PORTCR(2, 0xe6050002), + PORTCR(3, 0xe6050003), + PORTCR(4, 0xe6050004), + PORTCR(5, 0xe6050005), + PORTCR(6, 0xe6050006), + PORTCR(7, 0xe6050007), + PORTCR(8, 0xe6050008), + PORTCR(9, 0xe6050009), + PORTCR(10, 0xe605000A), + PORTCR(11, 0xe605000B), + PORTCR(12, 0xe605000C), + PORTCR(13, 0xe605000D), + PORTCR(14, 0xe605000E), + PORTCR(15, 0xe605000F), + PORTCR(16, 0xe6050010), + PORTCR(17, 0xe6050011), + PORTCR(18, 0xe6050012), + PORTCR(19, 0xe6050013), + PORTCR(20, 0xe6050014), + PORTCR(21, 0xe6050015), + PORTCR(22, 0xe6050016), + PORTCR(23, 0xe6050017), + PORTCR(24, 0xe6050018), + PORTCR(25, 0xe6050019), + PORTCR(26, 0xe605001A), + PORTCR(27, 0xe605001B), + PORTCR(28, 0xe605001C), + PORTCR(29, 0xe605001D), + PORTCR(30, 0xe605001E), + PORTCR(32, 0xe6051020), + PORTCR(33, 0xe6051021), + PORTCR(34, 0xe6051022), + PORTCR(35, 0xe6051023), + PORTCR(36, 0xe6051024), + PORTCR(37, 0xe6051025), + PORTCR(38, 0xe6051026), + PORTCR(39, 0xe6051027), + PORTCR(40, 0xe6051028), + PORTCR(64, 0xe6050040), + PORTCR(65, 0xe6050041), + PORTCR(66, 0xe6050042), + PORTCR(67, 0xe6050043), + PORTCR(68, 0xe6050044), + PORTCR(69, 0xe6050045), + PORTCR(70, 0xe6050046), + PORTCR(71, 0xe6050047), + PORTCR(72, 0xe6050048), + PORTCR(73, 0xe6050049), + PORTCR(74, 0xe605004A), + PORTCR(75, 0xe605004B), + PORTCR(76, 0xe605004C), + PORTCR(77, 0xe605004D), + PORTCR(78, 0xe605004E), + PORTCR(79, 0xe605004F), + PORTCR(80, 0xe6050050), + PORTCR(81, 0xe6050051), + PORTCR(82, 0xe6050052), + PORTCR(83, 0xe6050053), + PORTCR(84, 0xe6050054), + PORTCR(85, 0xe6050055), + PORTCR(96, 0xe6051060), + PORTCR(97, 0xe6051061), + PORTCR(98, 0xe6051062), + PORTCR(99, 0xe6051063), + PORTCR(100, 0xe6051064), + PORTCR(101, 0xe6051065), + PORTCR(102, 0xe6051066), + PORTCR(103, 0xe6051067), + PORTCR(104, 0xe6051068), + PORTCR(105, 0xe6051069), + PORTCR(106, 0xe605106A), + PORTCR(107, 0xe605106B), + PORTCR(108, 0xe605106C), + PORTCR(109, 0xe605106D), + PORTCR(110, 0xe605106E), + PORTCR(111, 0xe605106F), + PORTCR(112, 0xe6051070), + PORTCR(113, 0xe6051071), + PORTCR(114, 0xe6051072), + PORTCR(115, 0xe6051073), + PORTCR(116, 0xe6051074), + PORTCR(117, 0xe6051075), + PORTCR(118, 0xe6051076), + PORTCR(119, 0xe6051077), + PORTCR(120, 0xe6051078), + PORTCR(121, 0xe6051079), + PORTCR(122, 0xe605107A), + PORTCR(123, 0xe605107B), + PORTCR(124, 0xe605107C), + PORTCR(125, 0xe605107D), + PORTCR(126, 0xe605107E), + PORTCR(128, 0xe6051080), + PORTCR(129, 0xe6051081), + PORTCR(130, 0xe6051082), + PORTCR(131, 0xe6051083), + PORTCR(132, 0xe6051084), + PORTCR(133, 0xe6051085), + PORTCR(134, 0xe6051086), + PORTCR(160, 0xe60520A0), + PORTCR(161, 0xe60520A1), + PORTCR(162, 0xe60520A2), + PORTCR(163, 0xe60520A3), + PORTCR(164, 0xe60520A4), + PORTCR(165, 0xe60520A5), + PORTCR(166, 0xe60520A6), + PORTCR(167, 0xe60520A7), + PORTCR(168, 0xe60520A8), + PORTCR(169, 0xe60520A9), + PORTCR(170, 0xe60520AA), + PORTCR(171, 0xe60520AB), + PORTCR(172, 0xe60520AC), + PORTCR(173, 0xe60520AD), + PORTCR(174, 0xe60520AE), + PORTCR(175, 0xe60520AF), + PORTCR(176, 0xe60520B0), + PORTCR(177, 0xe60520B1), + PORTCR(178, 0xe60520B2), + PORTCR(192, 0xe60520C0), + PORTCR(193, 0xe60520C1), + PORTCR(194, 0xe60520C2), + PORTCR(195, 0xe60520C3), + PORTCR(196, 0xe60520C4), + PORTCR(197, 0xe60520C5), + PORTCR(198, 0xe60520C6), + PORTCR(199, 0xe60520C7), + PORTCR(200, 0xe60520C8), + PORTCR(201, 0xe60520C9), + PORTCR(202, 0xe60520CA), + PORTCR(203, 0xe60520CB), + PORTCR(204, 0xe60520CC), + PORTCR(205, 0xe60520CD), + PORTCR(206, 0xe60520CE), + PORTCR(207, 0xe60520CF), + PORTCR(208, 0xe60520D0), + PORTCR(209, 0xe60520D1), + PORTCR(210, 0xe60520D2), + PORTCR(211, 0xe60520D3), + PORTCR(212, 0xe60520D4), + PORTCR(213, 0xe60520D5), + PORTCR(214, 0xe60520D6), + PORTCR(215, 0xe60520D7), + PORTCR(216, 0xe60520D8), + PORTCR(217, 0xe60520D9), + PORTCR(218, 0xe60520DA), + PORTCR(219, 0xe60520DB), + PORTCR(220, 0xe60520DC), + PORTCR(221, 0xe60520DD), + PORTCR(222, 0xe60520DE), + PORTCR(224, 0xe60520E0), + PORTCR(225, 0xe60520E1), + PORTCR(226, 0xe60520E2), + PORTCR(227, 0xe60520E3), + PORTCR(228, 0xe60520E4), + PORTCR(229, 0xe60520E5), + PORTCR(230, 0xe60520e6), + PORTCR(231, 0xe60520E7), + PORTCR(232, 0xe60520E8), + PORTCR(233, 0xe60520E9), + PORTCR(234, 0xe60520EA), + PORTCR(235, 0xe60520EB), + PORTCR(236, 0xe60520EC), + PORTCR(237, 0xe60520ED), + PORTCR(238, 0xe60520EE), + PORTCR(239, 0xe60520EF), + PORTCR(240, 0xe60520F0), + PORTCR(241, 0xe60520F1), + PORTCR(242, 0xe60520F2), + PORTCR(243, 0xe60520F3), + PORTCR(244, 0xe60520F4), + PORTCR(245, 0xe60520F5), + PORTCR(246, 0xe60520F6), + PORTCR(247, 0xe60520F7), + PORTCR(248, 0xe60520F8), + PORTCR(249, 0xe60520F9), + PORTCR(250, 0xe60520FA), + PORTCR(256, 0xe6052100), + PORTCR(257, 0xe6052101), + PORTCR(258, 0xe6052102), + PORTCR(259, 0xe6052103), + PORTCR(260, 0xe6052104), + PORTCR(261, 0xe6052105), + PORTCR(262, 0xe6052106), + PORTCR(263, 0xe6052107), + PORTCR(264, 0xe6052108), + PORTCR(265, 0xe6052109), + PORTCR(266, 0xe605210A), + PORTCR(267, 0xe605210B), + PORTCR(268, 0xe605210C), + PORTCR(269, 0xe605210D), + PORTCR(270, 0xe605210E), + PORTCR(271, 0xe605210F), + PORTCR(272, 0xe6052110), + PORTCR(273, 0xe6052111), + PORTCR(274, 0xe6052112), + PORTCR(275, 0xe6052113), + PORTCR(276, 0xe6052114), + PORTCR(277, 0xe6052115), + PORTCR(278, 0xe6052116), + PORTCR(279, 0xe6052117), + PORTCR(280, 0xe6052118), + PORTCR(281, 0xe6052119), + PORTCR(282, 0xe605211A), + PORTCR(283, 0xe605211B), + PORTCR(288, 0xe6053120), + PORTCR(289, 0xe6053121), + PORTCR(290, 0xe6053122), + PORTCR(291, 0xe6053123), + PORTCR(292, 0xe6053124), + PORTCR(293, 0xe6053125), + PORTCR(294, 0xe6053126), + PORTCR(295, 0xe6053127), + PORTCR(296, 0xe6053128), + PORTCR(297, 0xe6053129), + PORTCR(298, 0xe605312A), + PORTCR(299, 0xe605312B), + PORTCR(300, 0xe605312C), + PORTCR(301, 0xe605312D), + PORTCR(302, 0xe605312E), + PORTCR(303, 0xe605312F), + PORTCR(304, 0xe6053130), + PORTCR(305, 0xe6053131), + PORTCR(306, 0xe6053132), + PORTCR(307, 0xe6053133), + PORTCR(308, 0xe6053134), + PORTCR(320, 0xe6053140), + PORTCR(321, 0xe6053141), + PORTCR(322, 0xe6053142), + PORTCR(323, 0xe6053143), + PORTCR(324, 0xe6053144), + PORTCR(325, 0xe6053145), + PORTCR(326, 0xe6053146), + PORTCR(327, 0xe6053147), + PORTCR(328, 0xe6053148), + PORTCR(329, 0xe6053149), + + { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { + MSEL1CR_31_0, MSEL1CR_31_1, + 0, 0, + 0, 0, + 0, 0, + MSEL1CR_27_0, MSEL1CR_27_1, + 0, 0, + MSEL1CR_25_0, MSEL1CR_25_1, + MSEL1CR_24_0, MSEL1CR_24_1, + 0, 0, + MSEL1CR_22_0, MSEL1CR_22_1, + MSEL1CR_21_0, MSEL1CR_21_1, + MSEL1CR_20_0, MSEL1CR_20_1, + MSEL1CR_19_0, MSEL1CR_19_1, + MSEL1CR_18_0, MSEL1CR_18_1, + MSEL1CR_17_0, MSEL1CR_17_1, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + MSEL1CR_11_0, MSEL1CR_11_1, + MSEL1CR_10_0, MSEL1CR_10_1, + MSEL1CR_09_0, MSEL1CR_09_1, + MSEL1CR_08_0, MSEL1CR_08_1, + MSEL1CR_07_0, MSEL1CR_07_1, + MSEL1CR_06_0, MSEL1CR_06_1, + MSEL1CR_05_0, MSEL1CR_05_1, + MSEL1CR_04_0, MSEL1CR_04_1, + MSEL1CR_03_0, MSEL1CR_03_1, + MSEL1CR_02_0, MSEL1CR_02_1, + MSEL1CR_01_0, MSEL1CR_01_1, + MSEL1CR_00_0, MSEL1CR_00_1, + } + }, + { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { + MSEL3CR_31_0, MSEL3CR_31_1, + 0, 0, + 0, 0, + MSEL3CR_28_0, MSEL3CR_28_1, + MSEL3CR_27_0, MSEL3CR_27_1, + MSEL3CR_26_0, MSEL3CR_26_1, + 0, 0, + 0, 0, + MSEL3CR_23_0, MSEL3CR_23_1, + MSEL3CR_22_0, MSEL3CR_22_1, + MSEL3CR_21_0, MSEL3CR_21_1, + MSEL3CR_20_0, MSEL3CR_20_1, + MSEL3CR_19_0, MSEL3CR_19_1, + MSEL3CR_18_0, MSEL3CR_18_1, + MSEL3CR_17_0, MSEL3CR_17_1, + MSEL3CR_16_0, MSEL3CR_16_1, + MSEL3CR_15_0, MSEL3CR_15_1, + 0, 0, + 0, 0, + MSEL3CR_12_0, MSEL3CR_12_1, + MSEL3CR_11_0, MSEL3CR_11_1, + MSEL3CR_10_0, MSEL3CR_10_1, + MSEL3CR_09_0, MSEL3CR_09_1, + 0, 0, + 0, 0, + MSEL3CR_06_0, MSEL3CR_06_1, + 0, 0, + 0, 0, + MSEL3CR_03_0, MSEL3CR_03_1, + 0, 0, + MSEL3CR_01_0, MSEL3CR_01_1, + MSEL3CR_00_0, MSEL3CR_00_1, + } + }, + { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { + 0, 0, + MSEL4CR_30_0, MSEL4CR_30_1, + MSEL4CR_29_0, MSEL4CR_29_1, + MSEL4CR_28_0, MSEL4CR_28_1, + MSEL4CR_27_0, MSEL4CR_27_1, + MSEL4CR_26_0, MSEL4CR_26_1, + MSEL4CR_25_0, MSEL4CR_25_1, + MSEL4CR_24_0, MSEL4CR_24_1, + MSEL4CR_23_0, MSEL4CR_23_1, + MSEL4CR_22_0, MSEL4CR_22_1, + MSEL4CR_21_0, MSEL4CR_21_1, + MSEL4CR_20_0, MSEL4CR_20_1, + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_17_0, MSEL4CR_17_1, + MSEL4CR_16_0, MSEL4CR_16_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_14_0, MSEL4CR_14_1, + MSEL4CR_13_0, MSEL4CR_13_1, + MSEL4CR_12_0, MSEL4CR_12_1, + MSEL4CR_11_0, MSEL4CR_11_1, + MSEL4CR_10_0, MSEL4CR_10_1, + MSEL4CR_09_0, MSEL4CR_09_1, + 0, 0, + MSEL4CR_07_0, MSEL4CR_07_1, + 0, 0, + 0, 0, + MSEL4CR_04_0, MSEL4CR_04_1, + 0, 0, + 0, 0, + MSEL4CR_01_0, MSEL4CR_01_1, + 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) { + MSEL5CR_31_0, MSEL5CR_31_1, + MSEL5CR_30_0, MSEL5CR_30_1, + MSEL5CR_29_0, MSEL5CR_29_1, + MSEL5CR_28_0, MSEL5CR_28_1, + MSEL5CR_27_0, MSEL5CR_27_1, + MSEL5CR_26_0, MSEL5CR_26_1, + MSEL5CR_25_0, MSEL5CR_25_1, + MSEL5CR_24_0, MSEL5CR_24_1, + MSEL5CR_23_0, MSEL5CR_23_1, + MSEL5CR_22_0, MSEL5CR_22_1, + MSEL5CR_21_0, MSEL5CR_21_1, + MSEL5CR_20_0, MSEL5CR_20_1, + MSEL5CR_19_0, MSEL5CR_19_1, + MSEL5CR_18_0, MSEL5CR_18_1, + MSEL5CR_17_0, MSEL5CR_17_1, + MSEL5CR_16_0, MSEL5CR_16_1, + MSEL5CR_15_0, MSEL5CR_15_1, + MSEL5CR_14_0, MSEL5CR_14_1, + MSEL5CR_13_0, MSEL5CR_13_1, + MSEL5CR_12_0, MSEL5CR_12_1, + MSEL5CR_11_0, MSEL5CR_11_1, + MSEL5CR_10_0, MSEL5CR_10_1, + MSEL5CR_09_0, MSEL5CR_09_1, + MSEL5CR_08_0, MSEL5CR_08_1, + MSEL5CR_07_0, MSEL5CR_07_1, + MSEL5CR_06_0, MSEL5CR_06_1, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSEL8CR_16_0, MSEL8CR_16_1, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSEL8CR_01_0, MSEL8CR_01_1, + MSEL8CR_00_0, MSEL8CR_00_1, + } + }, + { }, +}; + +static const struct pinmux_data_reg pinmux_data_regs[] = { + + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { + 0, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA, + } + }, + { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA, + } + }, + { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA, + } + }, + { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) { + 0, PORT126_DATA, PORT125_DATA, PORT124_DATA, + PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, + PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA, + } + }, + { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA, + } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT178_DATA, PORT177_DATA, PORT176_DATA, + PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, + PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, + PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA, + } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) { + 0, PORT222_DATA, PORT221_DATA, PORT220_DATA, + PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, + PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, + PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA, + } + }, + { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) { + 0, 0, 0, 0, + 0, PORT250_DATA, PORT249_DATA, PORT248_DATA, + PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, + PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, + PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, + PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, + PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, + PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA, + } + }, + { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) { + 0, 0, 0, 0, + PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA, + PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, + PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA, + PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, + PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, + PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, + PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA, + } + }, + { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT308_DATA, + PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA, + PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, + PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, + PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, + PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA, + } + }, + { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, PORT329_DATA, PORT328_DATA, + PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA, + PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA, + } + }, + { }, +}; + +static const struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(irq_pin(0), 0), + PINMUX_IRQ(irq_pin(1), 1), + PINMUX_IRQ(irq_pin(2), 2), + PINMUX_IRQ(irq_pin(3), 3), + PINMUX_IRQ(irq_pin(4), 4), + PINMUX_IRQ(irq_pin(5), 5), + PINMUX_IRQ(irq_pin(6), 6), + PINMUX_IRQ(irq_pin(7), 7), + PINMUX_IRQ(irq_pin(8), 8), + PINMUX_IRQ(irq_pin(9), 9), + PINMUX_IRQ(irq_pin(10), 10), + PINMUX_IRQ(irq_pin(11), 11), + PINMUX_IRQ(irq_pin(12), 12), + PINMUX_IRQ(irq_pin(13), 13), + PINMUX_IRQ(irq_pin(14), 14), + PINMUX_IRQ(irq_pin(15), 15), + PINMUX_IRQ(irq_pin(16), 320), + PINMUX_IRQ(irq_pin(17), 321), + PINMUX_IRQ(irq_pin(18), 85), + PINMUX_IRQ(irq_pin(19), 84), + PINMUX_IRQ(irq_pin(20), 160), + PINMUX_IRQ(irq_pin(21), 161), + PINMUX_IRQ(irq_pin(22), 162), + PINMUX_IRQ(irq_pin(23), 163), + PINMUX_IRQ(irq_pin(24), 175), + PINMUX_IRQ(irq_pin(25), 176), + PINMUX_IRQ(irq_pin(26), 177), + PINMUX_IRQ(irq_pin(27), 178), + PINMUX_IRQ(irq_pin(28), 322), + PINMUX_IRQ(irq_pin(29), 323), + PINMUX_IRQ(irq_pin(30), 324), + PINMUX_IRQ(irq_pin(31), 192), + PINMUX_IRQ(irq_pin(32), 193), + PINMUX_IRQ(irq_pin(33), 194), + PINMUX_IRQ(irq_pin(34), 195), + PINMUX_IRQ(irq_pin(35), 196), + PINMUX_IRQ(irq_pin(36), 197), + PINMUX_IRQ(irq_pin(37), 198), + PINMUX_IRQ(irq_pin(38), 199), + PINMUX_IRQ(irq_pin(39), 200), + PINMUX_IRQ(irq_pin(40), 66), + PINMUX_IRQ(irq_pin(41), 102), + PINMUX_IRQ(irq_pin(42), 103), + PINMUX_IRQ(irq_pin(43), 109), + PINMUX_IRQ(irq_pin(44), 110), + PINMUX_IRQ(irq_pin(45), 111), + PINMUX_IRQ(irq_pin(46), 112), + PINMUX_IRQ(irq_pin(47), 113), + PINMUX_IRQ(irq_pin(48), 114), + PINMUX_IRQ(irq_pin(49), 115), + PINMUX_IRQ(irq_pin(50), 301), + PINMUX_IRQ(irq_pin(51), 290), + PINMUX_IRQ(irq_pin(52), 296), + PINMUX_IRQ(irq_pin(53), 325), + PINMUX_IRQ(irq_pin(54), 326), + PINMUX_IRQ(irq_pin(55), 327), + PINMUX_IRQ(irq_pin(56), 328), + PINMUX_IRQ(irq_pin(57), 329), +}; + +#define PORTCR_PULMD_OFF (0 << 6) +#define PORTCR_PULMD_DOWN (2 << 6) +#define PORTCR_PULMD_UP (3 << 6) +#define PORTCR_PULMD_MASK (3 << 6) + +static const unsigned int r8a73a4_portcr_offsets[] = { + 0x00000000, 0x00001000, 0x00000000, 0x00001000, + 0x00001000, 0x00002000, 0x00002000, 0x00002000, + 0x00002000, 0x00003000, 0x00003000, +}; + +static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + void __iomem *addr; + + addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; + + switch (ioread8(addr) & PORTCR_PULMD_MASK) { + case PORTCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr; + u32 value; + + addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; + value = ioread8(addr) & ~PORTCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = { + .get_bias = r8a73a4_pinmux_get_bias, + .set_bias = r8a73a4_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info r8a73a4_pinmux_info = { + .name = "r8a73a4_pfc", + .ops = &r8a73a4_pinmux_ops, + + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), + + .gpio_irq = pinmux_irqs, + .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), +}; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 214788c4a60..e4c1ef47705 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -18,17 +18,38 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/io.h> #include <linux/kernel.h> -#include <mach/r8a7740.h> +#include <linux/pinctrl/pinconf-generic.h> + +#ifndef CONFIG_ARCH_MULTIPLATFORM #include <mach/irqs.h> +#endif +#include "core.h" #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ - PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) + PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ + PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \ + PORT_10(200, fn, pfx##20, sfx), \ + PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx) + +#define IRQC_PIN_MUX(irq, pin) \ +static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +}; \ +static const unsigned int intc_irq##irq##_mux[] = { \ + IRQ##irq##_MARK, \ +} + +#define IRQC_PINS_MUX(irq, idx, pin) \ +static const unsigned int intc_irq##irq##_##idx##_pins[] = { \ + pin, \ +}; \ +static const unsigned int intc_irq##irq##_##idx##_mux[] = { \ + IRQ##irq##_PORT##pin##_MARK, \ +} enum { PINMUX_RESERVED = 0, @@ -43,16 +64,6 @@ enum { PORT_ALL(IN), PINMUX_INPUT_END, - /* PORT0_IN_PU -> PORT211_IN_PU */ - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), - PINMUX_INPUT_PULLUP_END, - - /* PORT0_IN_PD -> PORT211_IN_PD */ - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), - PINMUX_INPUT_PULLDOWN_END, - /* PORT0_OUT -> PORT211_OUT */ PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), @@ -261,8 +272,6 @@ enum { SCIFB_CTS_PORT173_MARK, /* LCD0 */ - LCDC0_SELECT_MARK, - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, @@ -285,8 +294,6 @@ enum { LCD0_LCLK_PORT102_MARK, /* LCD1 */ - LCDC1_SELECT_MARK, - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, @@ -577,137 +584,8 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { - /* specify valid pin states for each pin in GPIO mode */ - - /* I/O and Pull U/D */ - PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), - PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3), - PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5), - PORT_DATA_IO_PD(6), PORT_DATA_IO(7), - PORT_DATA_IO(8), PORT_DATA_IO(9), - - PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11), - PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13), - PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15), - PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), - PORT_DATA_IO(18), PORT_DATA_IO_PU(19), - - PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21), - PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23), - PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25), - PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27), - PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29), - - PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31), - PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33), - PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35), - PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37), - PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39), - - PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41), - PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43), - PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45), - PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47), - PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49), - - PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51), - PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53), - PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55), - PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57), - PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59), - - PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61), - PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), - PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), - PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), - PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), - - PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), - PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), - PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75), - PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), - PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), - - PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), - PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83), - PORT_DATA_IO(84), PORT_DATA_IO_PD(85), - PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87), - PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89), - - PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91), - PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), - PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), - PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), - PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), - - PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101), - PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103), - PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105), - PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107), - PORT_DATA_IO(108), PORT_DATA_IO(109), - - PORT_DATA_IO(110), PORT_DATA_IO(111), - PORT_DATA_IO(112), PORT_DATA_IO(113), - PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115), - PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117), - PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119), - - PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121), - PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), - PORT_DATA_IO_PD(124), PORT_DATA_IO(125), - PORT_DATA_IO(126), PORT_DATA_IO(127), - PORT_DATA_IO(128), PORT_DATA_IO(129), - - PORT_DATA_IO(130), PORT_DATA_IO(131), - PORT_DATA_IO(132), PORT_DATA_IO(133), - PORT_DATA_IO(134), PORT_DATA_IO(135), - PORT_DATA_IO(136), PORT_DATA_IO(137), - PORT_DATA_IO(138), PORT_DATA_IO(139), - - PORT_DATA_IO(140), PORT_DATA_IO(141), - PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143), - PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145), - PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147), - PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149), - - PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151), - PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153), - PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155), - PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157), - PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159), - - PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161), - PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), - PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165), - PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167), - PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169), - - PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171), - PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), - PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175), - PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177), - PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179), - - PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181), - PORT_DATA_IO_PU(182), PORT_DATA_IO(183), - PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), - PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187), - PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), - - PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), - PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193), - PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195), - PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197), - PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), - - PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201), - PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203), - PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), - PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), - PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209), - - PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), +static const u16 pinmux_data[] = { + PINMUX_DATA_ALL(), /* Port0 */ PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), @@ -986,7 +864,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), /* Port58 */ - PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), + PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0), PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), PINMUX_DATA(DV_D0_MARK, PORT58_FN6), @@ -1633,10 +1511,6 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1), - /* LCDC select */ - PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), - PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), - /* SDENC */ PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), @@ -1654,479 +1528,1715 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), }; -static struct pinmux_gpio pinmux_gpios[] = { - - /* PORT */ - GPIO_PORT_ALL(), - - /* IRQ */ - GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), - GPIO_FN(IRQ1), - GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12), - GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14), - GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172), - GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1), - GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173), - GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209), - GPIO_FN(IRQ8), - GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210), - GPIO_FN(IRQ10), - GPIO_FN(IRQ11), - GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97), - GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98), - GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99), - GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100), - GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211), - GPIO_FN(IRQ17), - GPIO_FN(IRQ18), - GPIO_FN(IRQ19), - GPIO_FN(IRQ20), - GPIO_FN(IRQ21), - GPIO_FN(IRQ22), - GPIO_FN(IRQ23), - GPIO_FN(IRQ24), - GPIO_FN(IRQ25), - GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81), - GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168), - GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169), - GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170), - GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171), - GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167), - - /* Function */ - - /* DBGT */ - GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0), - GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20), - GPIO_FN(DBGMD21), - - /* FSI-A */ - GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */ - GPIO_FN(FSIAISLD_PORT5), - GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */ - GPIO_FN(FSIASPDIF_PORT18), - GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR), - GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC), - GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT), - - /* FSI-B */ - GPIO_FN(FSIBCK), - - /* FMSI */ - GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */ - GPIO_FN(FMSISLD_PORT6), - GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR), - GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR), - GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT), - GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK), - - /* SCIFA0 */ - GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS), - GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD), - - /* SCIFA1 */ - GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK), - GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS), - - /* SCIFA2 */ - GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */ - GPIO_FN(SCIFA2_SCK_PORT199), - GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD), - GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS), - - /* SCIFA3 */ - GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */ - GPIO_FN(SCIFA3_SCK_PORT116), - GPIO_FN(SCIFA3_CTS_PORT117), - GPIO_FN(SCIFA3_RXD_PORT174), - GPIO_FN(SCIFA3_TXD_PORT175), - - GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */ - GPIO_FN(SCIFA3_SCK_PORT158), - GPIO_FN(SCIFA3_CTS_PORT162), - GPIO_FN(SCIFA3_RXD_PORT159), - GPIO_FN(SCIFA3_TXD_PORT160), - - /* SCIFA4 */ - GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */ - GPIO_FN(SCIFA4_TXD_PORT13), - - GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */ - GPIO_FN(SCIFA4_TXD_PORT203), - - GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */ - GPIO_FN(SCIFA4_TXD_PORT93), - - GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */ - GPIO_FN(SCIFA4_SCK_PORT205), - - /* SCIFA5 */ - GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */ - GPIO_FN(SCIFA5_RXD_PORT10), - - GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */ - GPIO_FN(SCIFA5_TXD_PORT208), - - GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */ - GPIO_FN(SCIFA5_RXD_PORT92), - - GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */ - GPIO_FN(SCIFA5_SCK_PORT206), - - /* SCIFA6 */ - GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD), - - /* SCIFA7 */ - GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD), - - /* SCIFAB */ - GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */ - GPIO_FN(SCIFB_RXD_PORT191), - GPIO_FN(SCIFB_TXD_PORT192), - GPIO_FN(SCIFB_RTS_PORT186), - GPIO_FN(SCIFB_CTS_PORT187), - - GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */ - GPIO_FN(SCIFB_RXD_PORT3), - GPIO_FN(SCIFB_TXD_PORT4), - GPIO_FN(SCIFB_RTS_PORT172), - GPIO_FN(SCIFB_CTS_PORT173), - - /* LCD0 */ - GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2), - GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5), - GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8), - GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11), - GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14), - GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17), - GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC), - GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN), - GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP), - GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD), - GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS), - - GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162), - GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158), - GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159), - GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */ - - GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4), - GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2), - GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1), - GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */ - - /* LCD1 */ - GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2), - GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5), - GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8), - GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11), - GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14), - GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17), - GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20), - GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23), - GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS), - GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON), - GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN), - GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP), - - /* RSPI */ - GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), - GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), - GPIO_FN(RSPI_MISO_A), - - /* VIO CKO */ - GPIO_FN(VIO_CKO1), - GPIO_FN(VIO_CKO2), - GPIO_FN(VIO_CKO_1), - GPIO_FN(VIO_CKO), - - /* VIO0 */ - GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2), - GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5), - GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8), - GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11), - GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD), - GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD), - - GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */ - GPIO_FN(VIO0_D14_PORT25), - GPIO_FN(VIO0_D15_PORT24), - - GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */ - GPIO_FN(VIO0_D14_PORT95), - GPIO_FN(VIO0_D15_PORT96), - - /* VIO1 */ - GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2), - GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5), - GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD), - GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD), - - /* TPU0 */ - GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3), - GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */ - GPIO_FN(TPU0TO2_PORT202), - - /* SSP1 0 */ - GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2), - GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5), - GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN), - GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC), - - /* SSP1 1 */ - GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3), - GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6), - GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC), - - GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */ - GPIO_FN(STP1_IPEN_PORT187), - - GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */ - GPIO_FN(STP1_IPEN_PORT193), - - /* SIM */ - GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), - GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ - GPIO_FN(SIM_D_PORT199), - - /* SDHI0 */ - GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2), - GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP), - GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK), - - /* SDHI1 */ - GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2), - GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP), - GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK), - - /* SDHI2 */ - GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2), - GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD), - - GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */ - GPIO_FN(SDHI2_WP_PORT25), - - GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */ - GPIO_FN(SDHI2_CD_PORT202), - - /* MSIOF2 */ - GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), - GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), - GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC), - GPIO_FN(MSIOF2_RSCK), - - /* KEYSC */ - GPIO_FN(KEYIN4), GPIO_FN(KEYIN5), - GPIO_FN(KEYIN6), GPIO_FN(KEYIN7), - GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2), - GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5), - GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7), - - GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */ - GPIO_FN(KEYIN1_PORT44), - GPIO_FN(KEYIN2_PORT45), - GPIO_FN(KEYIN3_PORT46), - - GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */ - GPIO_FN(KEYIN1_PORT57), - GPIO_FN(KEYIN2_PORT56), - GPIO_FN(KEYIN3_PORT55), +#define __I (SH_PFC_PIN_CFG_INPUT) +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) +#define __PU (SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) +#define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) +#define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD) +#define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO) +#define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD) +#define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU) +#define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) +#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) +#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) + +static const struct sh_pfc_pin pinmux_pins[] = { + /* Table 56-1 (I/O and Pull U/D) */ + R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1), + R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3), + R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5), + R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7), + R8A7740_PIN_IO(8), R8A7740_PIN_IO(9), + R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11), + R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13), + R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15), + R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17), + R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19), + R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21), + R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23), + R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25), + R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27), + R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29), + R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31), + R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33), + R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35), + R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37), + R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39), + R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41), + R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43), + R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45), + R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47), + R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49), + R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51), + R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53), + R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55), + R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57), + R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59), + R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61), + R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63), + R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65), + R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67), + R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69), + R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71), + R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73), + R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75), + R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77), + R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79), + R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81), + R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83), + R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85), + R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87), + R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89), + R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91), + R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93), + R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95), + R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97), + R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99), + R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101), + R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103), + R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105), + R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107), + R8A7740_PIN_IO(108), R8A7740_PIN_IO(109), + R8A7740_PIN_IO(110), R8A7740_PIN_IO(111), + R8A7740_PIN_IO(112), R8A7740_PIN_IO(113), + R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115), + R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117), + R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119), + R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121), + R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123), + R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125), + R8A7740_PIN_IO(126), R8A7740_PIN_IO(127), + R8A7740_PIN_IO(128), R8A7740_PIN_IO(129), + R8A7740_PIN_IO(130), R8A7740_PIN_IO(131), + R8A7740_PIN_IO(132), R8A7740_PIN_IO(133), + R8A7740_PIN_IO(134), R8A7740_PIN_IO(135), + R8A7740_PIN_IO(136), R8A7740_PIN_IO(137), + R8A7740_PIN_IO(138), R8A7740_PIN_IO(139), + R8A7740_PIN_IO(140), R8A7740_PIN_IO(141), + R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143), + R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145), + R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147), + R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149), + R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151), + R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153), + R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155), + R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157), + R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159), + R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161), + R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163), + R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165), + R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167), + R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169), + R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171), + R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173), + R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175), + R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177), + R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179), + R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181), + R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183), + R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185), + R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187), + R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189), + R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191), + R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193), + R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195), + R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197), + R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199), + R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201), + R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203), + R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205), + R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207), + R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209), + R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211), +}; - /* VOU */ - GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2), - GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5), - GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8), - GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11), - GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14), - GPIO_FN(DV_D15), GPIO_FN(DV_CLK), - GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC), +/* - BSC -------------------------------------------------------------------- */ +static const unsigned int bsc_data8_pins[] = { + /* D[0:7] */ + 157, 156, 155, 154, 153, 152, 151, 150, +}; +static const unsigned int bsc_data8_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, +}; +static const unsigned int bsc_data16_pins[] = { + /* D[0:15] */ + 157, 156, 155, 154, 153, 152, 151, 150, + 149, 148, 147, 146, 145, 144, 143, 142, +}; +static const unsigned int bsc_data16_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int bsc_data32_pins[] = { + /* D[0:31] */ + 157, 156, 155, 154, 153, 152, 151, 150, + 149, 148, 147, 146, 145, 144, 143, 142, + 171, 170, 169, 168, 167, 166, 173, 172, + 165, 164, 163, 162, 161, 160, 159, 158, +}; +static const unsigned int bsc_data32_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, + D16_MARK, D17_MARK, D18_MARK, D19_MARK, + D20_MARK, D21_MARK, D22_MARK, D23_MARK, + D24_MARK, D25_MARK, D26_MARK, D27_MARK, + D28_MARK, D29_MARK, D30_MARK, D31_MARK, +}; +static const unsigned int bsc_cs0_pins[] = { + /* CS */ + 109, +}; +static const unsigned int bsc_cs0_mux[] = { + CS0_MARK, +}; +static const unsigned int bsc_cs2_pins[] = { + /* CS */ + 110, +}; +static const unsigned int bsc_cs2_mux[] = { + CS2_MARK, +}; +static const unsigned int bsc_cs4_pins[] = { + /* CS */ + 111, +}; +static const unsigned int bsc_cs4_mux[] = { + CS4_MARK, +}; +static const unsigned int bsc_cs5a_0_pins[] = { + /* CS */ + 105, +}; +static const unsigned int bsc_cs5a_0_mux[] = { + CS5A_PORT105_MARK, +}; +static const unsigned int bsc_cs5a_1_pins[] = { + /* CS */ + 19, +}; +static const unsigned int bsc_cs5a_1_mux[] = { + CS5A_PORT19_MARK, +}; +static const unsigned int bsc_cs5b_pins[] = { + /* CS */ + 103, +}; +static const unsigned int bsc_cs5b_mux[] = { + CS5B_MARK, +}; +static const unsigned int bsc_cs6a_pins[] = { + /* CS */ + 104, +}; +static const unsigned int bsc_cs6a_mux[] = { + CS6A_MARK, +}; +static const unsigned int bsc_rd_we8_pins[] = { + /* RD, WE[0] */ + 115, 113, +}; +static const unsigned int bsc_rd_we8_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, +}; +static const unsigned int bsc_rd_we16_pins[] = { + /* RD, WE[0:1] */ + 115, 113, 112, +}; +static const unsigned int bsc_rd_we16_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, +}; +static const unsigned int bsc_rd_we32_pins[] = { + /* RD, WE[0:3] */ + 115, 113, 112, 108, 107, +}; +static const unsigned int bsc_rd_we32_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK, +}; +static const unsigned int bsc_bs_pins[] = { + /* BS */ + 175, +}; +static const unsigned int bsc_bs_mux[] = { + BS_MARK, +}; +static const unsigned int bsc_rdwr_pins[] = { + /* RDWR */ + 114, +}; +static const unsigned int bsc_rdwr_mux[] = { + RDWR_MARK, +}; +/* - CEU0 ------------------------------------------------------------------- */ +static const unsigned int ceu0_data_0_7_pins[] = { + /* D[0:7] */ + 34, 33, 32, 31, 30, 29, 28, 27, +}; +static const unsigned int ceu0_data_0_7_mux[] = { + VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK, + VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK, +}; +static const unsigned int ceu0_data_8_15_0_pins[] = { + /* D[8:15] */ + 182, 181, 180, 179, 178, 26, 25, 24, +}; +static const unsigned int ceu0_data_8_15_0_mux[] = { + VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, + VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK, + VIO0_D15_PORT24_MARK, +}; +static const unsigned int ceu0_data_8_15_1_pins[] = { + /* D[8:15] */ + 182, 181, 180, 179, 178, 22, 95, 96, +}; +static const unsigned int ceu0_data_8_15_1_mux[] = { + VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, + VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK, + VIO0_D15_PORT96_MARK, +}; +static const unsigned int ceu0_clk_0_pins[] = { + /* CKO */ + 36, +}; +static const unsigned int ceu0_clk_0_mux[] = { + VIO_CKO_MARK, +}; +static const unsigned int ceu0_clk_1_pins[] = { + /* CKO */ + 14, +}; +static const unsigned int ceu0_clk_1_mux[] = { + VIO_CKO1_MARK, +}; +static const unsigned int ceu0_clk_2_pins[] = { + /* CKO */ + 15, +}; +static const unsigned int ceu0_clk_2_mux[] = { + VIO_CKO2_MARK, +}; +static const unsigned int ceu0_sync_pins[] = { + /* CLK, VD, HD */ + 35, 39, 37, +}; +static const unsigned int ceu0_sync_mux[] = { + VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK, +}; +static const unsigned int ceu0_field_pins[] = { + /* FIELD */ + 38, +}; +static const unsigned int ceu0_field_mux[] = { + VIO0_FIELD_MARK, +}; +/* - CEU1 ------------------------------------------------------------------- */ +static const unsigned int ceu1_data_pins[] = { + /* D[0:7] */ + 182, 181, 180, 179, 178, 26, 25, 24, +}; +static const unsigned int ceu1_data_mux[] = { + VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK, + VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK, +}; +static const unsigned int ceu1_clk_pins[] = { + /* CKO */ + 23, +}; +static const unsigned int ceu1_clk_mux[] = { + VIO_CKO_1_MARK, +}; +static const unsigned int ceu1_sync_pins[] = { + /* CLK, VD, HD */ + 197, 198, 160, +}; +static const unsigned int ceu1_sync_mux[] = { + VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK, +}; +static const unsigned int ceu1_field_pins[] = { + /* FIELD */ + 21, +}; +static const unsigned int ceu1_field_mux[] = { + VIO1_FIELD_MARK, +}; +/* - FSIA ------------------------------------------------------------------- */ +static const unsigned int fsia_mclk_in_pins[] = { + /* CK */ + 11, +}; +static const unsigned int fsia_mclk_in_mux[] = { + FSIACK_MARK, +}; +static const unsigned int fsia_mclk_out_pins[] = { + /* OMC */ + 10, +}; +static const unsigned int fsia_mclk_out_mux[] = { + FSIAOMC_MARK, +}; +static const unsigned int fsia_sclk_in_pins[] = { + /* ILR, IBT */ + 12, 13, +}; +static const unsigned int fsia_sclk_in_mux[] = { + FSIAILR_MARK, FSIAIBT_MARK, +}; +static const unsigned int fsia_sclk_out_pins[] = { + /* OLR, OBT */ + 7, 8, +}; +static const unsigned int fsia_sclk_out_mux[] = { + FSIAOLR_MARK, FSIAOBT_MARK, +}; +static const unsigned int fsia_data_in_0_pins[] = { + /* ISLD */ + 0, +}; +static const unsigned int fsia_data_in_0_mux[] = { + FSIAISLD_PORT0_MARK, +}; +static const unsigned int fsia_data_in_1_pins[] = { + /* ISLD */ + 5, +}; +static const unsigned int fsia_data_in_1_mux[] = { + FSIAISLD_PORT5_MARK, +}; +static const unsigned int fsia_data_out_0_pins[] = { + /* OSLD */ + 9, +}; +static const unsigned int fsia_data_out_0_mux[] = { + FSIAOSLD_MARK, +}; +static const unsigned int fsia_data_out_1_pins[] = { + /* OSLD */ + 0, +}; +static const unsigned int fsia_data_out_1_mux[] = { + FSIAOSLD1_MARK, +}; +static const unsigned int fsia_data_out_2_pins[] = { + /* OSLD */ + 1, +}; +static const unsigned int fsia_data_out_2_mux[] = { + FSIAOSLD2_MARK, +}; +static const unsigned int fsia_spdif_0_pins[] = { + /* SPDIF */ + 9, +}; +static const unsigned int fsia_spdif_0_mux[] = { + FSIASPDIF_PORT9_MARK, +}; +static const unsigned int fsia_spdif_1_pins[] = { + /* SPDIF */ + 18, +}; +static const unsigned int fsia_spdif_1_mux[] = { + FSIASPDIF_PORT18_MARK, +}; +/* - FSIB ------------------------------------------------------------------- */ +static const unsigned int fsib_mclk_in_pins[] = { + /* CK */ + 11, +}; +static const unsigned int fsib_mclk_in_mux[] = { + FSIBCK_MARK, +}; +/* - GETHER ----------------------------------------------------------------- */ +static const unsigned int gether_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */ + 195, 196, 194, 193, 200, 201, 199, 159, 202, 208, +}; +static const unsigned int gether_rmii_mux[] = { + RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK, + RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK, + RMII_MDC_MARK, RMII_MDIO_MARK, +}; +static const unsigned int gether_mii_pins[] = { + /* RXD[0:3], RX_CLK, RX_DV, RX_ER + * TXD[0:3], TX_CLK, TX_EN, TX_ER + * CRS, COL, MDC, MDIO, + */ + 185, 186, 187, 188, 174, 161, 204, + 171, 170, 169, 168, 184, 183, 203, + 205, 163, 206, 207, +}; +static const unsigned int gether_mii_mux[] = { + ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, + ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK, + ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK, + ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK, + ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK, +}; +static const unsigned int gether_gmii_pins[] = { + /* RXD[0:7], RX_CLK, RX_DV, RX_ER + * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER + * CRS, COL, MDC, MDIO, REF125CK_MARK, + */ + 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204, + 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203, + 205, 163, 206, 207, +}; +static const unsigned int gether_gmii_mux[] = { + ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, + ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK, + ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK, + ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK, + ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK, + ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK, + ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK, + RMII_REF125CK_MARK, +}; +static const unsigned int gether_int_pins[] = { + /* PHY_INT */ + 164, +}; +static const unsigned int gether_int_mux[] = { + ET_PHY_INT_MARK, +}; +static const unsigned int gether_link_pins[] = { + /* LINK */ + 177, +}; +static const unsigned int gether_link_mux[] = { + ET_LINK_MARK, +}; +static const unsigned int gether_wol_pins[] = { + /* WOL */ + 175, +}; +static const unsigned int gether_wol_mux[] = { + ET_WOL_MARK, +}; +/* - HDMI ------------------------------------------------------------------- */ +static const unsigned int hdmi_pins[] = { + /* HPD, CEC */ + 210, 211, +}; +static const unsigned int hdmi_mux[] = { + HDMI_HPD_MARK, HDMI_CEC_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +IRQC_PINS_MUX(0, 0, 2); +IRQC_PINS_MUX(0, 1, 13); +IRQC_PIN_MUX(1, 20); +IRQC_PINS_MUX(2, 0, 11); +IRQC_PINS_MUX(2, 1, 12); +IRQC_PINS_MUX(3, 0, 10); +IRQC_PINS_MUX(3, 1, 14); +IRQC_PINS_MUX(4, 0, 15); +IRQC_PINS_MUX(4, 1, 172); +IRQC_PINS_MUX(5, 0, 0); +IRQC_PINS_MUX(5, 1, 1); +IRQC_PINS_MUX(6, 0, 121); +IRQC_PINS_MUX(6, 1, 173); +IRQC_PINS_MUX(7, 0, 120); +IRQC_PINS_MUX(7, 1, 209); +IRQC_PIN_MUX(8, 119); +IRQC_PINS_MUX(9, 0, 118); +IRQC_PINS_MUX(9, 1, 210); +IRQC_PIN_MUX(10, 19); +IRQC_PIN_MUX(11, 104); +IRQC_PINS_MUX(12, 0, 42); +IRQC_PINS_MUX(12, 1, 97); +IRQC_PINS_MUX(13, 0, 64); +IRQC_PINS_MUX(13, 1, 98); +IRQC_PINS_MUX(14, 0, 63); +IRQC_PINS_MUX(14, 1, 99); +IRQC_PINS_MUX(15, 0, 62); +IRQC_PINS_MUX(15, 1, 100); +IRQC_PINS_MUX(16, 0, 68); +IRQC_PINS_MUX(16, 1, 211); +IRQC_PIN_MUX(17, 69); +IRQC_PIN_MUX(18, 70); +IRQC_PIN_MUX(19, 71); +IRQC_PIN_MUX(20, 67); +IRQC_PIN_MUX(21, 202); +IRQC_PIN_MUX(22, 95); +IRQC_PIN_MUX(23, 96); +IRQC_PIN_MUX(24, 180); +IRQC_PIN_MUX(25, 38); +IRQC_PINS_MUX(26, 0, 58); +IRQC_PINS_MUX(26, 1, 81); +IRQC_PINS_MUX(27, 0, 57); +IRQC_PINS_MUX(27, 1, 168); +IRQC_PINS_MUX(28, 0, 56); +IRQC_PINS_MUX(28, 1, 169); +IRQC_PINS_MUX(29, 0, 50); +IRQC_PINS_MUX(29, 1, 170); +IRQC_PINS_MUX(30, 0, 49); +IRQC_PINS_MUX(30, 1, 171); +IRQC_PINS_MUX(31, 0, 41); +IRQC_PINS_MUX(31, 1, 167); + +/* - LCD0 ------------------------------------------------------------------- */ +static const unsigned int lcd0_data8_pins[] = { + /* D[0:7] */ + 58, 57, 56, 55, 54, 53, 52, 51, +}; +static const unsigned int lcd0_data8_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, +}; +static const unsigned int lcd0_data9_pins[] = { + /* D[0:8] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, +}; +static const unsigned int lcd0_data9_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, +}; +static const unsigned int lcd0_data12_pins[] = { + /* D[0:11] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, +}; +static const unsigned int lcd0_data12_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, +}; +static const unsigned int lcd0_data16_pins[] = { + /* D[0:15] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, +}; +static const unsigned int lcd0_data16_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, +}; +static const unsigned int lcd0_data18_pins[] = { + /* D[0:17] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, +}; +static const unsigned int lcd0_data18_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, + LCD0_D16_MARK, LCD0_D17_MARK, +}; +static const unsigned int lcd0_data24_0_pins[] = { + /* D[0:23] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, 40, 4, 3, 2, 0, 1, +}; +static const unsigned int lcd0_data24_0_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, + LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK, + LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK, + LCD0_D23_PORT1_MARK, +}; +static const unsigned int lcd0_data24_1_pins[] = { + /* D[0:23] */ + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, 163, 162, 161, 158, 160, 159, +}; +static const unsigned int lcd0_data24_1_mux[] = { + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK, + LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK, + LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK, +}; +static const unsigned int lcd0_display_pins[] = { + /* DON, VCPWC, VEPWC */ + 61, 59, 60, +}; +static const unsigned int lcd0_display_mux[] = { + LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK, +}; +static const unsigned int lcd0_lclk_0_pins[] = { + /* LCLK */ + 102, +}; +static const unsigned int lcd0_lclk_0_mux[] = { + LCD0_LCLK_PORT102_MARK, +}; +static const unsigned int lcd0_lclk_1_pins[] = { + /* LCLK */ + 165, +}; +static const unsigned int lcd0_lclk_1_mux[] = { + LCD0_LCLK_PORT165_MARK, +}; +static const unsigned int lcd0_sync_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 63, 64, 62, 65, +}; +static const unsigned int lcd0_sync_mux[] = { + LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK, +}; +static const unsigned int lcd0_sys_pins[] = { + /* CS, WR, RD, RS */ + 64, 62, 164, 65, +}; +static const unsigned int lcd0_sys_mux[] = { + LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK, +}; +/* - LCD1 ------------------------------------------------------------------- */ +static const unsigned int lcd1_data8_pins[] = { + /* D[0:7] */ + 4, 3, 2, 1, 0, 91, 92, 23, +}; +static const unsigned int lcd1_data8_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, +}; +static const unsigned int lcd1_data9_pins[] = { + /* D[0:8] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, +}; +static const unsigned int lcd1_data9_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, +}; +static const unsigned int lcd1_data12_pins[] = { + /* D[0:12] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, 94, 21, 201, +}; +static const unsigned int lcd1_data12_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, +}; +static const unsigned int lcd1_data16_pins[] = { + /* D[0:15] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, 94, 21, 201, 200, 199, 196, 195, +}; +static const unsigned int lcd1_data16_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, + LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, +}; +static const unsigned int lcd1_data18_pins[] = { + /* D[0:17] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, 94, 21, 201, 200, 199, 196, 195, + 194, 193, +}; +static const unsigned int lcd1_data18_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, + LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, + LCD1_D16_MARK, LCD1_D17_MARK, +}; +static const unsigned int lcd1_data24_pins[] = { + /* D[0:23] */ + 4, 3, 2, 1, 0, 91, 92, 23, + 93, 94, 21, 201, 200, 199, 196, 195, + 194, 193, 198, 197, 75, 74, 15, 14, +}; +static const unsigned int lcd1_data24_mux[] = { + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, + LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, + LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK, + LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK, +}; +static const unsigned int lcd1_display_pins[] = { + /* DON, VCPWC, VEPWC */ + 100, 5, 6, +}; +static const unsigned int lcd1_display_mux[] = { + LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK, +}; +static const unsigned int lcd1_lclk_pins[] = { + /* LCLK */ + 40, +}; +static const unsigned int lcd1_lclk_mux[] = { + LCD1_LCLK_MARK, +}; +static const unsigned int lcd1_sync_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 98, 97, 99, 12, +}; +static const unsigned int lcd1_sync_mux[] = { + LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK, +}; +static const unsigned int lcd1_sys_pins[] = { + /* CS, WR, RD, RS */ + 97, 99, 13, 12, +}; +static const unsigned int lcd1_sys_mux[] = { + LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK, +}; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ + 68, +}; +static const unsigned int mmc0_data1_0_mux[] = { + MMC0_D0_PORT68_MARK, +}; +static const unsigned int mmc0_data4_0_pins[] = { + /* D[0:3] */ + 68, 69, 70, 71, +}; +static const unsigned int mmc0_data4_0_mux[] = { + MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, +}; +static const unsigned int mmc0_data8_0_pins[] = { + /* D[0:7] */ + 68, 69, 70, 71, 72, 73, 74, 75, +}; +static const unsigned int mmc0_data8_0_mux[] = { + MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, + MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, +}; +static const unsigned int mmc0_ctrl_0_pins[] = { + /* CMD, CLK */ + 67, 66, +}; +static const unsigned int mmc0_ctrl_0_mux[] = { + MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK, +}; - /* MEMC */ - GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), - GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), - GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), - GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), - GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), - GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT), - GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1), - GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0), - GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), - GPIO_FN(MEMC_A0), +static const unsigned int mmc0_data1_1_pins[] = { + /* D[0] */ + 149, +}; +static const unsigned int mmc0_data1_1_mux[] = { + MMC1_D0_PORT149_MARK, +}; +static const unsigned int mmc0_data4_1_pins[] = { + /* D[0:3] */ + 149, 148, 147, 146, +}; +static const unsigned int mmc0_data4_1_mux[] = { + MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, +}; +static const unsigned int mmc0_data8_1_pins[] = { + /* D[0:7] */ + 149, 148, 147, 146, 145, 144, 143, 142, +}; +static const unsigned int mmc0_data8_1_mux[] = { + MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, + MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, +}; +static const unsigned int mmc0_ctrl_1_pins[] = { + /* CMD, CLK */ + 104, 103, +}; +static const unsigned int mmc0_ctrl_1_mux[] = { + MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + 197, 198, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + 188, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + 194, 193, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + 195, 196, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + 185, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + 23, 21, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + 200, 201, +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, +}; +static const unsigned int scifa2_clk_0_pins[] = { + /* SCK */ + 22, +}; +static const unsigned int scifa2_clk_0_mux[] = { + SCIFA2_SCK_PORT22_MARK, +}; +static const unsigned int scifa2_clk_1_pins[] = { + /* SCK */ + 199, +}; +static const unsigned int scifa2_clk_1_mux[] = { + SCIFA2_SCK_PORT199_MARK, +}; +static const unsigned int scifa2_ctrl_pins[] = { + /* RTS, CTS */ + 96, 95, +}; +static const unsigned int scifa2_ctrl_mux[] = { + SCIFA2_RTS_MARK, SCIFA2_CTS_MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_0_pins[] = { + /* RXD, TXD */ + 174, 175, +}; +static const unsigned int scifa3_data_0_mux[] = { + SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK, +}; +static const unsigned int scifa3_clk_0_pins[] = { + /* SCK */ + 116, +}; +static const unsigned int scifa3_clk_0_mux[] = { + SCIFA3_SCK_PORT116_MARK, +}; +static const unsigned int scifa3_ctrl_0_pins[] = { + /* RTS, CTS */ + 105, 117, +}; +static const unsigned int scifa3_ctrl_0_mux[] = { + SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK, +}; +static const unsigned int scifa3_data_1_pins[] = { + /* RXD, TXD */ + 159, 160, +}; +static const unsigned int scifa3_data_1_mux[] = { + SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK, +}; +static const unsigned int scifa3_clk_1_pins[] = { + /* SCK */ + 158, +}; +static const unsigned int scifa3_clk_1_mux[] = { + SCIFA3_SCK_PORT158_MARK, +}; +static const unsigned int scifa3_ctrl_1_pins[] = { + /* RTS, CTS */ + 161, 162, +}; +static const unsigned int scifa3_ctrl_1_mux[] = { + SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_0_pins[] = { + /* RXD, TXD */ + 12, 13, +}; +static const unsigned int scifa4_data_0_mux[] = { + SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK, +}; +static const unsigned int scifa4_data_1_pins[] = { + /* RXD, TXD */ + 204, 203, +}; +static const unsigned int scifa4_data_1_mux[] = { + SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK, +}; +static const unsigned int scifa4_data_2_pins[] = { + /* RXD, TXD */ + 94, 93, +}; +static const unsigned int scifa4_data_2_mux[] = { + SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK, +}; +static const unsigned int scifa4_clk_0_pins[] = { + /* SCK */ + 21, +}; +static const unsigned int scifa4_clk_0_mux[] = { + SCIFA4_SCK_PORT21_MARK, +}; +static const unsigned int scifa4_clk_1_pins[] = { + /* SCK */ + 205, +}; +static const unsigned int scifa4_clk_1_mux[] = { + SCIFA4_SCK_PORT205_MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_0_pins[] = { + /* RXD, TXD */ + 10, 20, +}; +static const unsigned int scifa5_data_0_mux[] = { + SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK, +}; +static const unsigned int scifa5_data_1_pins[] = { + /* RXD, TXD */ + 207, 208, +}; +static const unsigned int scifa5_data_1_mux[] = { + SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK, +}; +static const unsigned int scifa5_data_2_pins[] = { + /* RXD, TXD */ + 92, 91, +}; +static const unsigned int scifa5_data_2_mux[] = { + SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK, +}; +static const unsigned int scifa5_clk_0_pins[] = { + /* SCK */ + 23, +}; +static const unsigned int scifa5_clk_0_mux[] = { + SCIFA5_SCK_PORT23_MARK, +}; +static const unsigned int scifa5_clk_1_pins[] = { + /* SCK */ + 206, +}; +static const unsigned int scifa5_clk_1_mux[] = { + SCIFA5_SCK_PORT206_MARK, +}; +/* - SCIFA6 ----------------------------------------------------------------- */ +static const unsigned int scifa6_data_pins[] = { + /* RXD, TXD */ + 25, 26, +}; +static const unsigned int scifa6_data_mux[] = { + SCIFA6_RXD_MARK, SCIFA6_TXD_MARK, +}; +static const unsigned int scifa6_clk_pins[] = { + /* SCK */ + 24, +}; +static const unsigned int scifa6_clk_mux[] = { + SCIFA6_SCK_MARK, +}; +/* - SCIFA7 ----------------------------------------------------------------- */ +static const unsigned int scifa7_data_pins[] = { + /* RXD, TXD */ + 0, 1, +}; +static const unsigned int scifa7_data_mux[] = { + SCIFA7_RXD_MARK, SCIFA7_TXD_MARK, +}; +/* - SCIFB ------------------------------------------------------------------ */ +static const unsigned int scifb_data_0_pins[] = { + /* RXD, TXD */ + 191, 192, +}; +static const unsigned int scifb_data_0_mux[] = { + SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK, +}; +static const unsigned int scifb_clk_0_pins[] = { + /* SCK */ + 190, +}; +static const unsigned int scifb_clk_0_mux[] = { + SCIFB_SCK_PORT190_MARK, +}; +static const unsigned int scifb_ctrl_0_pins[] = { + /* RTS, CTS */ + 186, 187, +}; +static const unsigned int scifb_ctrl_0_mux[] = { + SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK, +}; +static const unsigned int scifb_data_1_pins[] = { + /* RXD, TXD */ + 3, 4, +}; +static const unsigned int scifb_data_1_mux[] = { + SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK, +}; +static const unsigned int scifb_clk_1_pins[] = { + /* SCK */ + 2, +}; +static const unsigned int scifb_clk_1_mux[] = { + SCIFB_SCK_PORT2_MARK, +}; +static const unsigned int scifb_ctrl_1_pins[] = { + /* RTS, CTS */ + 172, 173, +}; +static const unsigned int scifb_ctrl_1_mux[] = { + SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + 77, +}; +static const unsigned int sdhi0_data1_mux[] = { + SDHI0_D0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + 77, 78, 79, 80, +}; +static const unsigned int sdhi0_data4_mux[] = { + SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CMD, CLK */ + 76, 82, +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SDHI0_CMD_MARK, SDHI0_CLK_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + 81, +}; +static const unsigned int sdhi0_cd_mux[] = { + SDHI0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + 83, +}; +static const unsigned int sdhi0_wp_mux[] = { + SDHI0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + 68, +}; +static const unsigned int sdhi1_data1_mux[] = { + SDHI1_D0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + 68, 69, 70, 71, +}; +static const unsigned int sdhi1_data4_mux[] = { + SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CMD, CLK */ + 67, 66, +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SDHI1_CMD_MARK, SDHI1_CLK_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + 72, +}; +static const unsigned int sdhi1_cd_mux[] = { + SDHI1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + 73, +}; +static const unsigned int sdhi1_wp_mux[] = { + SDHI1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + 205, +}; +static const unsigned int sdhi2_data1_mux[] = { + SDHI2_D0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + 205, 206, 207, 208, +}; +static const unsigned int sdhi2_data4_mux[] = { + SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CMD, CLK */ + 204, 203, +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SDHI2_CMD_MARK, SDHI2_CLK_MARK, +}; +static const unsigned int sdhi2_cd_0_pins[] = { + /* CD */ + 202, +}; +static const unsigned int sdhi2_cd_0_mux[] = { + SDHI2_CD_PORT202_MARK, +}; +static const unsigned int sdhi2_wp_0_pins[] = { + /* WP */ + 177, +}; +static const unsigned int sdhi2_wp_0_mux[] = { + SDHI2_WP_PORT177_MARK, +}; +static const unsigned int sdhi2_cd_1_pins[] = { + /* CD */ + 24, +}; +static const unsigned int sdhi2_cd_1_mux[] = { + SDHI2_CD_PORT24_MARK, +}; +static const unsigned int sdhi2_wp_1_pins[] = { + /* WP */ + 25, +}; +static const unsigned int sdhi2_wp_1_mux[] = { + SDHI2_WP_PORT25_MARK, +}; +/* - TPU0 ------------------------------------------------------------------- */ +static const unsigned int tpu0_to0_pins[] = { + /* TO */ + 23, +}; +static const unsigned int tpu0_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu0_to1_pins[] = { + /* TO */ + 21, +}; +static const unsigned int tpu0_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu0_to2_0_pins[] = { + /* TO */ + 66, +}; +static const unsigned int tpu0_to2_0_mux[] = { + TPU0TO2_PORT66_MARK, +}; +static const unsigned int tpu0_to2_1_pins[] = { + /* TO */ + 202, +}; +static const unsigned int tpu0_to2_1_mux[] = { + TPU0TO2_PORT202_MARK, +}; +static const unsigned int tpu0_to3_pins[] = { + /* TO */ + 180, +}; +static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, +}; - /* MMC */ - GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69), - GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71), - GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73), - GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75), - GPIO_FN(MMC0_CLK_PORT66), - GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */ - - GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148), - GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146), - GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144), - GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142), - GPIO_FN(MMC1_CLK_PORT103), - GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */ +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data8), + SH_PFC_PIN_GROUP(bsc_data16), + SH_PFC_PIN_GROUP(bsc_data32), + SH_PFC_PIN_GROUP(bsc_cs0), + SH_PFC_PIN_GROUP(bsc_cs2), + SH_PFC_PIN_GROUP(bsc_cs4), + SH_PFC_PIN_GROUP(bsc_cs5a_0), + SH_PFC_PIN_GROUP(bsc_cs5a_1), + SH_PFC_PIN_GROUP(bsc_cs5b), + SH_PFC_PIN_GROUP(bsc_cs6a), + SH_PFC_PIN_GROUP(bsc_rd_we8), + SH_PFC_PIN_GROUP(bsc_rd_we16), + SH_PFC_PIN_GROUP(bsc_rd_we32), + SH_PFC_PIN_GROUP(bsc_bs), + SH_PFC_PIN_GROUP(bsc_rdwr), + SH_PFC_PIN_GROUP(ceu0_data_0_7), + SH_PFC_PIN_GROUP(ceu0_data_8_15_0), + SH_PFC_PIN_GROUP(ceu0_data_8_15_1), + SH_PFC_PIN_GROUP(ceu0_clk_0), + SH_PFC_PIN_GROUP(ceu0_clk_1), + SH_PFC_PIN_GROUP(ceu0_clk_2), + SH_PFC_PIN_GROUP(ceu0_sync), + SH_PFC_PIN_GROUP(ceu0_field), + SH_PFC_PIN_GROUP(ceu1_data), + SH_PFC_PIN_GROUP(ceu1_clk), + SH_PFC_PIN_GROUP(ceu1_sync), + SH_PFC_PIN_GROUP(ceu1_field), + SH_PFC_PIN_GROUP(fsia_mclk_in), + SH_PFC_PIN_GROUP(fsia_mclk_out), + SH_PFC_PIN_GROUP(fsia_sclk_in), + SH_PFC_PIN_GROUP(fsia_sclk_out), + SH_PFC_PIN_GROUP(fsia_data_in_0), + SH_PFC_PIN_GROUP(fsia_data_in_1), + SH_PFC_PIN_GROUP(fsia_data_out_0), + SH_PFC_PIN_GROUP(fsia_data_out_1), + SH_PFC_PIN_GROUP(fsia_data_out_2), + SH_PFC_PIN_GROUP(fsia_spdif_0), + SH_PFC_PIN_GROUP(fsia_spdif_1), + SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(gether_rmii), + SH_PFC_PIN_GROUP(gether_mii), + SH_PFC_PIN_GROUP(gether_gmii), + SH_PFC_PIN_GROUP(gether_int), + SH_PFC_PIN_GROUP(gether_link), + SH_PFC_PIN_GROUP(gether_wol), + SH_PFC_PIN_GROUP(hdmi), + SH_PFC_PIN_GROUP(intc_irq0_0), + SH_PFC_PIN_GROUP(intc_irq0_1), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2_0), + SH_PFC_PIN_GROUP(intc_irq2_1), + SH_PFC_PIN_GROUP(intc_irq3_0), + SH_PFC_PIN_GROUP(intc_irq3_1), + SH_PFC_PIN_GROUP(intc_irq4_0), + SH_PFC_PIN_GROUP(intc_irq4_1), + SH_PFC_PIN_GROUP(intc_irq5_0), + SH_PFC_PIN_GROUP(intc_irq5_1), + SH_PFC_PIN_GROUP(intc_irq6_0), + SH_PFC_PIN_GROUP(intc_irq6_1), + SH_PFC_PIN_GROUP(intc_irq7_0), + SH_PFC_PIN_GROUP(intc_irq7_1), + SH_PFC_PIN_GROUP(intc_irq8), + SH_PFC_PIN_GROUP(intc_irq9_0), + SH_PFC_PIN_GROUP(intc_irq9_1), + SH_PFC_PIN_GROUP(intc_irq10), + SH_PFC_PIN_GROUP(intc_irq11), + SH_PFC_PIN_GROUP(intc_irq12_0), + SH_PFC_PIN_GROUP(intc_irq12_1), + SH_PFC_PIN_GROUP(intc_irq13_0), + SH_PFC_PIN_GROUP(intc_irq13_1), + SH_PFC_PIN_GROUP(intc_irq14_0), + SH_PFC_PIN_GROUP(intc_irq14_1), + SH_PFC_PIN_GROUP(intc_irq15_0), + SH_PFC_PIN_GROUP(intc_irq15_1), + SH_PFC_PIN_GROUP(intc_irq16_0), + SH_PFC_PIN_GROUP(intc_irq16_1), + SH_PFC_PIN_GROUP(intc_irq17), + SH_PFC_PIN_GROUP(intc_irq18), + SH_PFC_PIN_GROUP(intc_irq19), + SH_PFC_PIN_GROUP(intc_irq20), + SH_PFC_PIN_GROUP(intc_irq21), + SH_PFC_PIN_GROUP(intc_irq22), + SH_PFC_PIN_GROUP(intc_irq23), + SH_PFC_PIN_GROUP(intc_irq24), + SH_PFC_PIN_GROUP(intc_irq25), + SH_PFC_PIN_GROUP(intc_irq26_0), + SH_PFC_PIN_GROUP(intc_irq26_1), + SH_PFC_PIN_GROUP(intc_irq27_0), + SH_PFC_PIN_GROUP(intc_irq27_1), + SH_PFC_PIN_GROUP(intc_irq28_0), + SH_PFC_PIN_GROUP(intc_irq28_1), + SH_PFC_PIN_GROUP(intc_irq29_0), + SH_PFC_PIN_GROUP(intc_irq29_1), + SH_PFC_PIN_GROUP(intc_irq30_0), + SH_PFC_PIN_GROUP(intc_irq30_1), + SH_PFC_PIN_GROUP(intc_irq31_0), + SH_PFC_PIN_GROUP(intc_irq31_1), + SH_PFC_PIN_GROUP(lcd0_data8), + SH_PFC_PIN_GROUP(lcd0_data9), + SH_PFC_PIN_GROUP(lcd0_data12), + SH_PFC_PIN_GROUP(lcd0_data16), + SH_PFC_PIN_GROUP(lcd0_data18), + SH_PFC_PIN_GROUP(lcd0_data24_0), + SH_PFC_PIN_GROUP(lcd0_data24_1), + SH_PFC_PIN_GROUP(lcd0_display), + SH_PFC_PIN_GROUP(lcd0_lclk_0), + SH_PFC_PIN_GROUP(lcd0_lclk_1), + SH_PFC_PIN_GROUP(lcd0_sync), + SH_PFC_PIN_GROUP(lcd0_sys), + SH_PFC_PIN_GROUP(lcd1_data8), + SH_PFC_PIN_GROUP(lcd1_data9), + SH_PFC_PIN_GROUP(lcd1_data12), + SH_PFC_PIN_GROUP(lcd1_data16), + SH_PFC_PIN_GROUP(lcd1_data18), + SH_PFC_PIN_GROUP(lcd1_data24), + SH_PFC_PIN_GROUP(lcd1_display), + SH_PFC_PIN_GROUP(lcd1_lclk), + SH_PFC_PIN_GROUP(lcd1_sync), + SH_PFC_PIN_GROUP(lcd1_sys), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), + SH_PFC_PIN_GROUP(mmc0_ctrl_0), + SH_PFC_PIN_GROUP(mmc0_data1_1), + SH_PFC_PIN_GROUP(mmc0_data4_1), + SH_PFC_PIN_GROUP(mmc0_data8_1), + SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk_0), + SH_PFC_PIN_GROUP(scifa2_clk_1), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa3_data_0), + SH_PFC_PIN_GROUP(scifa3_clk_0), + SH_PFC_PIN_GROUP(scifa3_ctrl_0), + SH_PFC_PIN_GROUP(scifa3_data_1), + SH_PFC_PIN_GROUP(scifa3_clk_1), + SH_PFC_PIN_GROUP(scifa3_ctrl_1), + SH_PFC_PIN_GROUP(scifa4_data_0), + SH_PFC_PIN_GROUP(scifa4_data_1), + SH_PFC_PIN_GROUP(scifa4_data_2), + SH_PFC_PIN_GROUP(scifa4_clk_0), + SH_PFC_PIN_GROUP(scifa4_clk_1), + SH_PFC_PIN_GROUP(scifa5_data_0), + SH_PFC_PIN_GROUP(scifa5_data_1), + SH_PFC_PIN_GROUP(scifa5_data_2), + SH_PFC_PIN_GROUP(scifa5_clk_0), + SH_PFC_PIN_GROUP(scifa5_clk_1), + SH_PFC_PIN_GROUP(scifa6_data), + SH_PFC_PIN_GROUP(scifa6_clk), + SH_PFC_PIN_GROUP(scifa7_data), + SH_PFC_PIN_GROUP(scifb_data_0), + SH_PFC_PIN_GROUP(scifb_clk_0), + SH_PFC_PIN_GROUP(scifb_ctrl_0), + SH_PFC_PIN_GROUP(scifb_data_1), + SH_PFC_PIN_GROUP(scifb_clk_1), + SH_PFC_PIN_GROUP(scifb_ctrl_1), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd_0), + SH_PFC_PIN_GROUP(sdhi2_wp_0), + SH_PFC_PIN_GROUP(sdhi2_cd_1), + SH_PFC_PIN_GROUP(sdhi2_wp_1), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2_0), + SH_PFC_PIN_GROUP(tpu0_to2_1), + SH_PFC_PIN_GROUP(tpu0_to3), +}; - /* MSIOF0 */ - GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), - GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), - GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK), - GPIO_FN(MSIOF0_TSYNC), +static const char * const bsc_groups[] = { + "bsc_data8", + "bsc_data16", + "bsc_data32", + "bsc_cs0", + "bsc_cs2", + "bsc_cs4", + "bsc_cs5a_0", + "bsc_cs5a_1", + "bsc_cs5b", + "bsc_cs6a", + "bsc_rd_we8", + "bsc_rd_we16", + "bsc_rd_we32", + "bsc_bs", + "bsc_rdwr", +}; - /* MSIOF1 */ - GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), - GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), +static const char * const ceu0_groups[] = { + "ceu0_data_0_7", + "ceu0_data_8_15_0", + "ceu0_data_8_15_1", + "ceu0_clk_0", + "ceu0_clk_1", + "ceu0_clk_2", + "ceu0_sync", + "ceu0_field", +}; - GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117), - GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119), - GPIO_FN(MSIOF1_TSYNC_PORT120), - GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */ +static const char * const ceu1_groups[] = { + "ceu1_data", + "ceu1_clk", + "ceu1_sync", + "ceu1_field", +}; - GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72), - GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74), - GPIO_FN(MSIOF1_RXD_PORT75), - GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */ +static const char * const fsia_groups[] = { + "fsia_mclk_in", + "fsia_mclk_out", + "fsia_sclk_in", + "fsia_sclk_out", + "fsia_data_in_0", + "fsia_data_in_1", + "fsia_data_out_0", + "fsia_data_out_1", + "fsia_data_out_2", + "fsia_spdif_0", + "fsia_spdif_1", +}; - /* GPIO */ - GPIO_FN(GPO0), GPIO_FN(GPI0), - GPIO_FN(GPO1), GPIO_FN(GPI1), +static const char * const fsib_groups[] = { + "fsib_mclk_in", +}; - /* USB0 */ - GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS), +static const char * const gether_groups[] = { + "gether_rmii", + "gether_mii", + "gether_gmii", + "gether_int", + "gether_link", + "gether_wol", +}; - /* USB1 */ - GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON), +static const char * const hdmi_groups[] = { + "hdmi", +}; - /* BBIF1 */ - GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC), - GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), - GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N), +static const char * const intc_groups[] = { + "intc_irq0_0", + "intc_irq0_1", + "intc_irq1", + "intc_irq2_0", + "intc_irq2_1", + "intc_irq3_0", + "intc_irq3_1", + "intc_irq4_0", + "intc_irq4_1", + "intc_irq5_0", + "intc_irq5_1", + "intc_irq6_0", + "intc_irq6_1", + "intc_irq7_0", + "intc_irq7_1", + "intc_irq8", + "intc_irq9_0", + "intc_irq9_1", + "intc_irq10", + "intc_irq11", + "intc_irq12_0", + "intc_irq12_1", + "intc_irq13_0", + "intc_irq13_1", + "intc_irq14_0", + "intc_irq14_1", + "intc_irq15_0", + "intc_irq15_1", + "intc_irq16_0", + "intc_irq16_1", + "intc_irq17", + "intc_irq18", + "intc_irq19", + "intc_irq20", + "intc_irq21", + "intc_irq22", + "intc_irq23", + "intc_irq24", + "intc_irq25", + "intc_irq26_0", + "intc_irq26_1", + "intc_irq27_0", + "intc_irq27_1", + "intc_irq28_0", + "intc_irq28_1", + "intc_irq29_0", + "intc_irq29_1", + "intc_irq30_0", + "intc_irq30_1", + "intc_irq31_0", + "intc_irq31_1", +}; - /* BBIF2 */ - GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */ - GPIO_FN(BBIF2_RXD2_PORT60), - GPIO_FN(BBIF2_TSYNC2_PORT6), - GPIO_FN(BBIF2_TSCK2_PORT59), +static const char * const lcd0_groups[] = { + "lcd0_data8", + "lcd0_data9", + "lcd0_data12", + "lcd0_data16", + "lcd0_data18", + "lcd0_data24_0", + "lcd0_data24_1", + "lcd0_display", + "lcd0_lclk_0", + "lcd0_lclk_1", + "lcd0_sync", + "lcd0_sys", +}; - GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */ - GPIO_FN(BBIF2_TXD2_PORT183), - GPIO_FN(BBIF2_TSCK2_PORT89), - GPIO_FN(BBIF2_TSYNC2_PORT184), +static const char * const lcd1_groups[] = { + "lcd1_data8", + "lcd1_data9", + "lcd1_data12", + "lcd1_data16", + "lcd1_data18", + "lcd1_data24", + "lcd1_display", + "lcd1_lclk", + "lcd1_sync", + "lcd1_sys", +}; - /* BSC / FLCTL / PCMCIA */ - GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), - GPIO_FN(CS5B), GPIO_FN(CS6A), - GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */ - GPIO_FN(CS5A_PORT19), - GPIO_FN(IOIS16), /* ? */ - - GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3), - GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */ - GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9), - GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), - GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17), - GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21), - GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), - GPIO_FN(A26), - - GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */ - GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */ - GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */ - GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */ - GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */ - GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */ - GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */ - GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */ - GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19), - GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23), - GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27), - GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31), - - GPIO_FN(WE0_FWE), /* share with FLCTL */ - GPIO_FN(WE1), - GPIO_FN(WE2_ICIORD), /* share with PCMCIA */ - GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */ - GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR), - GPIO_FN(RD_FSC), /* share with FLCTL */ - GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */ - GPIO_FN(WAIT_PORT90), - - GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */ +static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", + "mmc0_data8_0", + "mmc0_ctrl_0", + "mmc0_data1_1", + "mmc0_data4_1", + "mmc0_data8_1", + "mmc0_ctrl_1", +}; - /* IRDA */ - GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT), +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; - /* ATAPI */ - GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2), - GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5), - GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8), - GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11), - GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14), - GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1), - GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1), - GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY), - GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION), - GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ), +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; - /* RMII */ - GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0), - GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0), - GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO), - GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */ +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk_0", + "scifa2_clk_1", + "scifa2_ctrl", +}; - /* GEther */ - GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0), - GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3), - GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */ - GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */ - GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK), - GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1), - GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3), - GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */ - GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */ - GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC), - GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT), - GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK), +static const char * const scifa3_groups[] = { + "scifa3_data_0", + "scifa3_clk_0", + "scifa3_ctrl_0", + "scifa3_data_1", + "scifa3_clk_1", + "scifa3_ctrl_1", +}; - /* DMA0 */ - GPIO_FN(DREQ0), GPIO_FN(DACK0), +static const char * const scifa4_groups[] = { + "scifa4_data_0", + "scifa4_data_1", + "scifa4_data_2", + "scifa4_clk_0", + "scifa4_clk_1", +}; - /* DMA1 */ - GPIO_FN(DREQ1), GPIO_FN(DACK1), +static const char * const scifa5_groups[] = { + "scifa5_data_0", + "scifa5_data_1", + "scifa5_data_2", + "scifa5_clk_0", + "scifa5_clk_1", +}; - /* SYSC */ - GPIO_FN(RESETOUTS), +static const char * const scifa6_groups[] = { + "scifa6_data", + "scifa6_clk", +}; - /* IRREM */ - GPIO_FN(IROUT), +static const char * const scifa7_groups[] = { + "scifa7_data", +}; - /* LCDC */ - GPIO_FN(LCDC0_SELECT), - GPIO_FN(LCDC1_SELECT), +static const char * const scifb_groups[] = { + "scifb_data_0", + "scifb_clk_0", + "scifb_ctrl_0", + "scifb_data_1", + "scifb_clk_1", + "scifb_ctrl_1", +}; - /* SDENC */ - GPIO_FN(SDENC_CPG), - GPIO_FN(SDENC_DV_CLKI), +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; - /* HDMI */ - GPIO_FN(HDMI_HPD), - GPIO_FN(HDMI_CEC), +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; - /* SYSC */ - GPIO_FN(RESETP_PULLUP), - GPIO_FN(RESETP_PLAIN), +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd_0", + "sdhi2_wp_0", + "sdhi2_cd_1", + "sdhi2_wp_1", +}; - /* DEBUG */ - GPIO_FN(EDEBGREQ_PULLDOWN), - GPIO_FN(EDEBGREQ_PULLUP), +static const char * const tpu0_groups[] = { + "tpu0_to0", + "tpu0_to1", + "tpu0_to2_0", + "tpu0_to2_1", + "tpu0_to3", +}; - GPIO_FN(TRACEAUD_FROM_VIO), - GPIO_FN(TRACEAUD_FROM_LCDC0), - GPIO_FN(TRACEAUD_FROM_MEMC), +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu0), + SH_PFC_FUNCTION(ceu1), + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(gether), + SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lcd0), + SH_PFC_FUNCTION(lcd1), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifa6), + SH_PFC_FUNCTION(scifa7), + SH_PFC_FUNCTION(scifb), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(tpu0), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ PORTCR(1, 0xe6050001), /* PORT1CR */ PORTCR(2, 0xe6050002), /* PORT2CR */ @@ -2440,7 +3550,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, @@ -2544,63 +3654,127 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */ - PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */ - PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */ - PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */ - PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */ - PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */ - PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */ - PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */ - PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */ - PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */ - PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */ - PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */ - PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */ - PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */ - PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */ - PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */ - PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */ - PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */ - PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */ - PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */ - PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */ - PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */ - PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */ - PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */ - PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */ - PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */ - PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */ - PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */ - PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */ - PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */ - PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */ - PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */ -}; - -struct sh_pfc_soc_info r8a7740_pinmux_info = { +static const struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */ + PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */ + PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */ + PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */ + PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */ + PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */ + PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */ + PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */ + PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */ + PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */ + PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */ + PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */ + PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */ + PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */ + PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */ + PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */ + PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */ + PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */ + PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */ + PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */ + PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */ + PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */ + PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */ + PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */ + PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */ + PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */ + PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */ + PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */ + PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */ + PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */ + PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */ + PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */ +}; + +#define PORTnCR_PULMD_OFF (0 << 6) +#define PORTnCR_PULMD_DOWN (2 << 6) +#define PORTnCR_PULMD_UP (3 << 6) +#define PORTnCR_PULMD_MASK (3 << 6) + +struct r8a7740_portcr_group { + unsigned int end_pin; + unsigned int offset; +}; + +static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = { + { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 }, +}; + +static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) { + const struct r8a7740_portcr_group *group = + &r8a7740_portcr_offsets[i]; + + if (pin <= group->end_pin) + return pfc->windows->virt + group->offset + pin; + } + + return NULL; +} + +static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; + + switch (value) { + case PORTnCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTnCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTnCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTnCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTnCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = { + .get_bias = r8a7740_pinmux_get_bias, + .set_bias = r8a7740_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info r8a7740_pinmux_info = { .name = "r8a7740_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, - PINMUX_DATA_END }, + .ops = &r8a7740_pinmux_ops, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, - PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, - PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, - PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PORT0, - .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c new file mode 100644 index 00000000000..c7d610d1f3e --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -0,0 +1,2928 @@ +/* + * r8a7778 processor support - PFC hardware block + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * Copyright (C) 2013 Cogent Embedded, Inc. + * + * based on + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/platform_data/gpio-rcar.h> +#include <linux/kernel.h> +#include "sh_pfc.h" + +#define PORT_GP_27(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_27(4, fn, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */ + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */ + + /* GPSR0 */ + FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2, + FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1, + FN_A2, FN_A3, FN_IP0_15, FN_IP0_16, + FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, + FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24, + FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28, + FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1, + FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11, + + /* GPSR1 */ + FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25, + FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, + FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17, + FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2, + FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13, + FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24, + FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30, + FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4, + + /* GPSR2 */ + FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11, + FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21, + FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0, + FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7, + FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13, + FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB, + FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29, + FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7, + + /* GPSR3 */ + FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10, + FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16, + FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22, + FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30, + FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6, + FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, + FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29, + FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9, + + /* GPSR4 */ + FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19, + FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0, + FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, + FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24, + FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6, + FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19, + FN_IP10_24_22, FN_AVS1, FN_AVS2, + + /* IPSR0 */ + FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0, + FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B, + FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, + FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A, + FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A, + FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0, + FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5, + FN_A6, FN_A7, FN_A8, FN_A9, + FN_A10, FN_A11, FN_A12, FN_A13, + FN_A14, FN_A15, FN_A16, FN_A17, + FN_A18, FN_A19, + + /* IPSR1 */ + FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B, + FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, + FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, + FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24, + FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A, + FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A, + FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT, + FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B, + FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, + FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR, + FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0, + FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1, + FN_MMC_D4, + + /* IPSR2 */ + FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2, + FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3, + FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4, + FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A, + FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A, + FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0, + FN_PWM0_C, FN_D0, FN_D1, FN_D2, + FN_D3, FN_D4, FN_D5, FN_D6, + FN_D7, FN_D8, FN_D9, FN_D10, + FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK, + FN_IRQ1_A, + + /* IPSR3 */ + FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, + FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, + FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, + FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A, + FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, + FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, + FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B, + FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0, + FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2, + FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4, + FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3, + FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, + FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3, + FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5, + FN_DU0_DR6, FN_LCDOUT6, + + /* IPSR4 */ + FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, + FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D, + FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9, + FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D, + FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10, + FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, + FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, + FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7, + FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B, + FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6, + FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B, + FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, + FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, + FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2, + FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, + FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, + + /* IPSR5 */ + FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B, + FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B, + FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, + FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK, + FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A, + FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, + FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, + FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP, + FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK, + FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, + FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D, + FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, + FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, + FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, + FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B, + FN_RX2_A, FN_CAN0_RX_B, + + /* IPSR6 */ + FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B, + FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B, + FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5, + FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5, + FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8, + FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9, + FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, + FN_SSI_SCK012, FN_ARM_TRACEDATA_11, + FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12, + FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13, + FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, + FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0, + FN_ARM_TRACEDATA_15, + FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST, + FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK, + FN_SD0_DAT2, FN_SUB_TDI, + + /* IPSR7 */ + FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A, + FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A, + FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A, + FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A, + FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC, + FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C, + FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C, + FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A, + FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, + FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B, + FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A, + FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, + FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B, + + /* IPSR8 */ + FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, + FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0, + FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1, + FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2, + FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3, + FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4, + FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5, + FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B, + FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A, + FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, + FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, + FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B, + FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B, + + /* IPSR9 */ + FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, + FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, + FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK, + FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A, + FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2, + FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, + FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV, + FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN, + FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER, + FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A, + FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C, + FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C, + FN_RX2_D, FN_SCL2_C, + + /* IPSR10 */ + FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1, + FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1, + FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP, + FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A, + FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, + FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A, + FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B, + FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, + FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A, + FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B, + FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, + FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C, + + /* SEL */ + FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, + FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C, + FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, + FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E, + FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, + FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, + FN_SEL_SSI2_A, FN_SEL_SSI2_B, + FN_SEL_SSI1_A, FN_SEL_SSI1_B, + FN_SEL_VI1_A, FN_SEL_VI1_B, + FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D, + FN_SEL_SD2_A, FN_SEL_SD2_B, + FN_SEL_SD1_A, FN_SEL_SD1_B, + FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, + FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C, + FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, + FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, + FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, + FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, + FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, + FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, + FN_SEL_CAN1_A, FN_SEL_CAN1_B, + FN_SEL_CAN0_A, FN_SEL_CAN0_B, + FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, + FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, + FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, + FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, + FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C, + FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D, + FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C, + FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, + FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, + FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, + FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, + FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C, + FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C, + FN_SEL_I2C1_A, FN_SEL_I2C1_B, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* GPSR0 */ + PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK, + + /* GPSR1 */ + WE0_MARK, + + /* GPSR2 */ + AUDIO_CLKA_MARK, + AUDIO_CLKB_MARK, + + /* GPSR3 */ + SSI_SCK34_MARK, + + /* GPSR4 */ + AVS1_MARK, + AVS2_MARK, + + VI0_R0_C_MARK, /* see sel_vi0 */ + VI0_R1_C_MARK, /* see sel_vi0 */ + VI0_R2_C_MARK, /* see sel_vi0 */ + /* VI0_R3_C_MARK, */ + VI0_R4_C_MARK, /* see sel_vi0 */ + VI0_R5_C_MARK, /* see sel_vi0 */ + + VI0_R0_D_MARK, /* see sel_vi0 */ + VI0_R1_D_MARK, /* see sel_vi0 */ + VI0_R2_D_MARK, /* see sel_vi0 */ + VI0_R3_D_MARK, /* see sel_vi0 */ + VI0_R4_D_MARK, /* see sel_vi0 */ + VI0_R5_D_MARK, /* see sel_vi0 */ + + /* IPSR0 */ + PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK, + ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK, + TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK, + GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK, + SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK, + ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK, + MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK, + A4_MARK, A5_MARK, A6_MARK, A7_MARK, + A8_MARK, A9_MARK, A10_MARK, A11_MARK, + A12_MARK, A13_MARK, A14_MARK, A15_MARK, + A16_MARK, A17_MARK, A18_MARK, A19_MARK, + + /* IPSR1 */ + A20_MARK, HSPI_CS1_B_MARK, A21_MARK, + HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK, + RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK, + TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK, + SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK, + HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK, + MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK, + RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK, + HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK, + HSPI_RX1_B_MARK, SSI_SCK1_B_MARK, + ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK, + MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK, + ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK, + TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK, + + /* IPSR2 */ + SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK, + SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK, + SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK, + EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK, + MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK, + DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK, + DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK, + D1_MARK, D2_MARK, D3_MARK, D4_MARK, + D5_MARK, D6_MARK, D7_MARK, D8_MARK, + D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK, + IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK, + + /* IPSR3 */ + MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK, + MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK, + SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK, + CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK, + TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK, + RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK, + SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK, + HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK, + HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK, + DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK, + SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK, + SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK, + ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK, + TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK, + DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, + DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, + + /* IPSR4 */ + DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, + AUDATA4_MARK, ARM_TRACEDATA_4_MARK, + TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK, + LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK, + RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK, + LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK, + LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK, + TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK, + DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK, + VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK, + ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK, + ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK, + VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK, + ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK, + TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK, + VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK, + DU0_DB4_MARK, LCDOUT20_MARK, + + /* IPSR5 */ + VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK, + DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK, + DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, + QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK, + QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK, + AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK, + DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, + QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK, + DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK, + BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK, + AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK, + SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK, + TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK, + RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK, + SSI_SCK2_A_MARK, HSPI_CS0_B_MARK, + TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK, + HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK, + + /* IPSR6 */ + SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK, + CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK, + BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK, + HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK, + RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK, + RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK, + SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK, + SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK, + SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK, + TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK, + SSI_SDATA2_MARK, HSPI_CS2_A_MARK, + ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK, + ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK, + SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK, + SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK, + SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK, + SD0_DAT2_MARK, SUB_TDI_MARK, + + /* IPSR7 */ + SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK, + SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK, + HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK, + HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK, + HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK, + VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK, + TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK, + IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK, + CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK, + VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK, + RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK, + VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK, + TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK, + DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK, + + /* IPSR8 */ + VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK, + HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK, + DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK, + DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK, + DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK, + DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK, + DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK, + DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK, + VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK, + PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK, + RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK, + DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK, + VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK, + + /* IPSR9 */ + VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK, + DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK, + VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK, + VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK, + VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK, + PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK, + DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK, + ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK, + VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK, + TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK, + IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK, + DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK, + BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK, + DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK, + RX2_D_MARK, SCL2_C_MARK, + + /* IPSR10 */ + SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK, + ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK, + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK, + ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK, + DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK, + CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK, + ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK, + PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK, + DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK, + GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK, + DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK, + GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK, + EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK, + REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK, + EX_WAIT2_B_MARK, DACK0_B_MARK, + HSPI_TX2_B_MARK, CAN_CLK_C_MARK, + + PINMUX_MARK_END, +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(PENC0_MARK, FN_PENC0), + PINMUX_DATA(PENC1_MARK, FN_PENC1), + PINMUX_DATA(A1_MARK, FN_A1), + PINMUX_DATA(A2_MARK, FN_A2), + PINMUX_DATA(A3_MARK, FN_A3), + PINMUX_DATA(WE0_MARK, FN_WE0), + PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), + PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB), + PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(AVS2_MARK, FN_AVS2), + + /* IPSR0 */ + PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT), + PINMUX_IPSR_DATA(IP0_1_0, PWM1), + + PINMUX_IPSR_DATA(IP0_4_2, AUDATA0), + PINMUX_IPSR_DATA(IP0_4_2, ARM_TRACEDATA_0), + PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C), + PINMUX_IPSR_DATA(IP0_4_2, USB_OVC0), + PINMUX_IPSR_DATA(IP0_4_2, TX2_E), + PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B), + + PINMUX_IPSR_DATA(IP0_7_5, AUDATA1), + PINMUX_IPSR_DATA(IP0_7_5, ARM_TRACEDATA_1), + PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C), + PINMUX_IPSR_DATA(IP0_7_5, USB_OVC1), + PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E), + PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B), + + PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP0_11_8, MMC_D2), + PINMUX_IPSR_DATA(IP0_11_8, BS), + PINMUX_IPSR_DATA(IP0_11_8, ATADIR0_A), + PINMUX_IPSR_DATA(IP0_11_8, SDSELF_A), + PINMUX_IPSR_DATA(IP0_11_8, PWM4_B), + + PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP0_14_12, MMC_D3), + PINMUX_IPSR_DATA(IP0_14_12, A0), + PINMUX_IPSR_DATA(IP0_14_12, ATAG0_A), + PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B), + + PINMUX_IPSR_DATA(IP0_15, A4), + PINMUX_IPSR_DATA(IP0_16, A5), + PINMUX_IPSR_DATA(IP0_17, A6), + PINMUX_IPSR_DATA(IP0_18, A7), + PINMUX_IPSR_DATA(IP0_19, A8), + PINMUX_IPSR_DATA(IP0_20, A9), + PINMUX_IPSR_DATA(IP0_21, A10), + PINMUX_IPSR_DATA(IP0_22, A11), + PINMUX_IPSR_DATA(IP0_23, A12), + PINMUX_IPSR_DATA(IP0_24, A13), + PINMUX_IPSR_DATA(IP0_25, A14), + PINMUX_IPSR_DATA(IP0_26, A15), + PINMUX_IPSR_DATA(IP0_27, A16), + PINMUX_IPSR_DATA(IP0_28, A17), + PINMUX_IPSR_DATA(IP0_29, A18), + PINMUX_IPSR_DATA(IP0_30, A19), + + /* IPSR1 */ + PINMUX_IPSR_DATA(IP1_0, A20), + PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B), + + PINMUX_IPSR_DATA(IP1_1, A21), + PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B), + + PINMUX_IPSR_DATA(IP1_4_2, A22), + PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B), + PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B), + PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A), + + PINMUX_IPSR_DATA(IP1_7_5, A23), + PINMUX_IPSR_DATA(IP1_7_5, HTX0_B), + PINMUX_IPSR_DATA(IP1_7_5, TX2_B), + PINMUX_IPSR_DATA(IP1_7_5, DACK2_A), + PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A), + + PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP1_10_8, MMC_D6), + PINMUX_IPSR_DATA(IP1_10_8, A24), + PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A), + PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B), + PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A), + + PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP1_14_11, MMC_D7), + PINMUX_IPSR_DATA(IP1_14_11, A25), + PINMUX_IPSR_DATA(IP1_14_11, DACK1_A), + PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B), + PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C), + PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A), + + PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT), + PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B), + PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B), + + PINMUX_IPSR_NOGP(IP1_17, CS0), + PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B), + + PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B), + PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B), + PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26), + PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A), + PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B), + + PINMUX_IPSR_DATA(IP1_23_21, MMC_D5), + PINMUX_IPSR_DATA(IP1_23_21, ATADIR0_B), + PINMUX_IPSR_DATA(IP1_23_21, RD_WR), + + PINMUX_IPSR_DATA(IP1_24, WE1), + PINMUX_IPSR_DATA(IP1_24, ATAWR0_B), + + PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B), + PINMUX_IPSR_DATA(IP1_27_25, EX_CS0), + PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A), + PINMUX_IPSR_DATA(IP1_27_25, TX3_C), + PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A), + + PINMUX_IPSR_DATA(IP1_29_28, EX_CS1), + PINMUX_IPSR_DATA(IP1_29_28, MMC_D4), + + /* IPSR2 */ + PINMUX_IPSR_DATA(IP2_2_0, SD1_CLK_A), + PINMUX_IPSR_DATA(IP2_2_0, MMC_CLK), + PINMUX_IPSR_DATA(IP2_2_0, ATACS00), + PINMUX_IPSR_DATA(IP2_2_0, EX_CS2), + + PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP2_5_3, MMC_CMD), + PINMUX_IPSR_DATA(IP2_5_3, ATACS10), + PINMUX_IPSR_DATA(IP2_5_3, EX_CS3), + + PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP2_8_6, MMC_D0), + PINMUX_IPSR_DATA(IP2_8_6, ATARD0), + PINMUX_IPSR_DATA(IP2_8_6, EX_CS4), + PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A), + + PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP2_11_9, MMC_D1), + PINMUX_IPSR_DATA(IP2_11_9, ATAWR0_A), + PINMUX_IPSR_DATA(IP2_11_9, EX_CS5), + PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A), + + PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A), + PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A), + + PINMUX_IPSR_DATA(IP2_16_14, DACK0), + PINMUX_IPSR_DATA(IP2_16_14, TX3_A), + PINMUX_IPSR_DATA(IP2_16_14, DRACK0), + + PINMUX_IPSR_DATA(IP2_17, EX_WAIT0), + PINMUX_IPSR_DATA(IP2_17, PWM0_C), + + PINMUX_IPSR_NOGP(IP2_18, D0), + PINMUX_IPSR_NOGP(IP2_19, D1), + PINMUX_IPSR_NOGP(IP2_20, D2), + PINMUX_IPSR_NOGP(IP2_21, D3), + PINMUX_IPSR_NOGP(IP2_22, D4), + PINMUX_IPSR_NOGP(IP2_23, D5), + PINMUX_IPSR_NOGP(IP2_24, D6), + PINMUX_IPSR_NOGP(IP2_25, D7), + PINMUX_IPSR_NOGP(IP2_26, D8), + PINMUX_IPSR_NOGP(IP2_27, D9), + PINMUX_IPSR_NOGP(IP2_28, D10), + PINMUX_IPSR_NOGP(IP2_29, D11), + + PINMUX_IPSR_DATA(IP2_30, RD_WR_B), + PINMUX_IPSR_DATA(IP2_30, IRQ0), + + PINMUX_IPSR_DATA(IP2_31, MLB_CLK), + PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A), + + /* IPSR3 */ + PINMUX_IPSR_DATA(IP3_1_0, MLB_SIG), + PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B), + PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A), + PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A), + + PINMUX_IPSR_DATA(IP3_4_2, MLB_DAT), + PINMUX_IPSR_DATA(IP3_4_2, TX5_B), + PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A), + PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A), + PINMUX_IPSR_DATA(IP3_4_2, SDSELF_B), + + PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B), + PINMUX_IPSR_DATA(IP3_7_5, SCIF_CLK), + PINMUX_IPSR_DATA(IP3_7_5, AUDIO_CLKOUT_B), + PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B), + PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B), + + PINMUX_IPSR_DATA(IP3_9_8, SD1_CLK_B), + PINMUX_IPSR_DATA(IP3_9_8, HTX0_A), + PINMUX_IPSR_DATA(IP3_9_8, TX0_A), + + PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A), + PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A), + + PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A), + PINMUX_IPSR_DATA(IP3_15_13, SCK0), + PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B), + + PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A), + PINMUX_IPSR_DATA(IP3_18_16, CTS0), + + PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A), + PINMUX_IPSR_DATA(IP3_20_19, RTS0), + + PINMUX_IPSR_DATA(IP3_23_21, SSI_SCK4), + PINMUX_IPSR_DATA(IP3_23_21, DU0_DR0), + PINMUX_IPSR_DATA(IP3_23_21, LCDOUT0), + PINMUX_IPSR_DATA(IP3_23_21, AUDATA2), + PINMUX_IPSR_DATA(IP3_23_21, ARM_TRACEDATA_2), + PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C), + PINMUX_IPSR_DATA(IP3_23_21, ADICHS1), + PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B), + + PINMUX_IPSR_DATA(IP3_26_24, SSI_WS4), + PINMUX_IPSR_DATA(IP3_26_24, DU0_DR1), + PINMUX_IPSR_DATA(IP3_26_24, LCDOUT1), + PINMUX_IPSR_DATA(IP3_26_24, AUDATA3), + PINMUX_IPSR_DATA(IP3_26_24, ARM_TRACEDATA_3), + PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C), + PINMUX_IPSR_DATA(IP3_26_24, ADICHS2), + PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B), + + PINMUX_IPSR_DATA(IP3_27, DU0_DR2), + PINMUX_IPSR_DATA(IP3_27, LCDOUT2), + + PINMUX_IPSR_DATA(IP3_28, DU0_DR3), + PINMUX_IPSR_DATA(IP3_28, LCDOUT3), + + PINMUX_IPSR_DATA(IP3_29, DU0_DR4), + PINMUX_IPSR_DATA(IP3_29, LCDOUT4), + + PINMUX_IPSR_DATA(IP3_30, DU0_DR5), + PINMUX_IPSR_DATA(IP3_30, LCDOUT5), + + PINMUX_IPSR_DATA(IP3_31, DU0_DR6), + PINMUX_IPSR_DATA(IP3_31, LCDOUT6), + + /* IPSR4 */ + PINMUX_IPSR_DATA(IP4_0, DU0_DR7), + PINMUX_IPSR_DATA(IP4_0, LCDOUT7), + + PINMUX_IPSR_DATA(IP4_3_1, DU0_DG0), + PINMUX_IPSR_DATA(IP4_3_1, LCDOUT8), + PINMUX_IPSR_DATA(IP4_3_1, AUDATA4), + PINMUX_IPSR_DATA(IP4_3_1, ARM_TRACEDATA_4), + PINMUX_IPSR_DATA(IP4_3_1, TX1_D), + PINMUX_IPSR_DATA(IP4_3_1, CAN0_TX_A), + PINMUX_IPSR_DATA(IP4_3_1, ADICHS0), + + PINMUX_IPSR_DATA(IP4_6_4, DU0_DG1), + PINMUX_IPSR_DATA(IP4_6_4, LCDOUT9), + PINMUX_IPSR_DATA(IP4_6_4, AUDATA5), + PINMUX_IPSR_DATA(IP4_6_4, ARM_TRACEDATA_5), + PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D), + PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A), + PINMUX_IPSR_DATA(IP4_6_4, ADIDATA), + + PINMUX_IPSR_DATA(IP4_7, DU0_DG2), + PINMUX_IPSR_DATA(IP4_7, LCDOUT10), + + PINMUX_IPSR_DATA(IP4_8, DU0_DG3), + PINMUX_IPSR_DATA(IP4_8, LCDOUT11), + + PINMUX_IPSR_DATA(IP4_10_9, DU0_DG4), + PINMUX_IPSR_DATA(IP4_10_9, LCDOUT12), + PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B), + + PINMUX_IPSR_DATA(IP4_12_11, DU0_DG5), + PINMUX_IPSR_DATA(IP4_12_11, LCDOUT13), + PINMUX_IPSR_DATA(IP4_12_11, TX0_B), + + PINMUX_IPSR_DATA(IP4_14_13, DU0_DG6), + PINMUX_IPSR_DATA(IP4_14_13, LCDOUT14), + PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A), + + PINMUX_IPSR_DATA(IP4_16_15, DU0_DG7), + PINMUX_IPSR_DATA(IP4_16_15, LCDOUT15), + PINMUX_IPSR_DATA(IP4_16_15, TX4_A), + + PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B), + PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_20_17, DU0_DB0), + PINMUX_IPSR_DATA(IP4_20_17, LCDOUT16), + PINMUX_IPSR_DATA(IP4_20_17, AUDATA6), + PINMUX_IPSR_DATA(IP4_20_17, ARM_TRACEDATA_6), + PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A), + PINMUX_IPSR_DATA(IP4_20_17, PWM0_A), + PINMUX_IPSR_DATA(IP4_20_17, ADICLK), + PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B), + + PINMUX_IPSR_DATA(IP4_24_21, AUDIO_CLKC), + PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_24_21, DU0_DB1), + PINMUX_IPSR_DATA(IP4_24_21, LCDOUT17), + PINMUX_IPSR_DATA(IP4_24_21, AUDATA7), + PINMUX_IPSR_DATA(IP4_24_21, ARM_TRACEDATA_7), + PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A), + PINMUX_IPSR_DATA(IP4_24_21, ADICS_SAMP), + PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B), + + PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_26_25, DU0_DB2), + PINMUX_IPSR_DATA(IP4_26_25, LCDOUT18), + + PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B), + PINMUX_IPSR_DATA(IP4_28_27, DU0_DB3), + PINMUX_IPSR_DATA(IP4_28_27, LCDOUT19), + + PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_30_29, DU0_DB4), + PINMUX_IPSR_DATA(IP4_30_29, LCDOUT20), + + /* IPSR5 */ + PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP5_1_0, DU0_DB5), + PINMUX_IPSR_DATA(IP5_1_0, LCDOUT21), + + PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B), + PINMUX_IPSR_DATA(IP5_3_2, DU0_DB6), + PINMUX_IPSR_DATA(IP5_3_2, LCDOUT22), + + PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B), + PINMUX_IPSR_DATA(IP5_5_4, DU0_DB7), + PINMUX_IPSR_DATA(IP5_5_4, LCDOUT23), + + PINMUX_IPSR_DATA(IP5_6, DU0_DOTCLKIN), + PINMUX_IPSR_DATA(IP5_6, QSTVA_QVS), + + PINMUX_IPSR_DATA(IP5_7, DU0_DOTCLKO_UT0), + PINMUX_IPSR_DATA(IP5_7, QCLK), + + PINMUX_IPSR_DATA(IP5_9_8, DU0_DOTCLKO_UT1), + PINMUX_IPSR_DATA(IP5_9_8, QSTVB_QVE), + PINMUX_IPSR_DATA(IP5_9_8, AUDIO_CLKOUT_A), + PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C), + + PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B), + PINMUX_IPSR_DATA(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC), + PINMUX_IPSR_DATA(IP5_11_10, QSTH_QHS), + + PINMUX_IPSR_DATA(IP5_12, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_DATA(IP5_12, QSTB_QHE), + + PINMUX_IPSR_DATA(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP5_14_13, QCPV_QDE), + PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D), + + PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A), + PINMUX_IPSR_DATA(IP5_17_15, DU0_DISP), + PINMUX_IPSR_DATA(IP5_17_15, QPOLA), + PINMUX_IPSR_DATA(IP5_17_15, AUDCK), + PINMUX_IPSR_DATA(IP5_17_15, ARM_TRACECLK), + PINMUX_IPSR_DATA(IP5_17_15, BPFCLK_D), + + PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A), + PINMUX_IPSR_DATA(IP5_20_18, DU0_CDE), + PINMUX_IPSR_DATA(IP5_20_18, QPOLB), + PINMUX_IPSR_DATA(IP5_20_18, AUDSYNC), + PINMUX_IPSR_DATA(IP5_20_18, ARM_TRACECTL), + PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D), + + PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B), + PINMUX_IPSR_DATA(IP5_22_21, SSI_SCK78), + PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B), + PINMUX_IPSR_DATA(IP5_22_21, TX1_B), + + PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B), + PINMUX_IPSR_DATA(IP5_25_23, SSI_WS78), + PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B), + PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B), + PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D), + + PINMUX_IPSR_DATA(IP5_28_26, SSI_SDATA8), + PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A), + PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B), + PINMUX_IPSR_DATA(IP5_28_26, TX2_A), + PINMUX_IPSR_DATA(IP5_28_26, CAN0_TX_B), + + PINMUX_IPSR_DATA(IP5_30_29, SSI_SDATA7), + PINMUX_IPSR_DATA(IP5_30_29, HSPI_TX0_B), + PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A), + PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B), + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK6), + PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A), + PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B), + PINMUX_IPSR_DATA(IP6_1_0, CAN1_TX_B), + + PINMUX_IPSR_DATA(IP6_4_2, SSI_WS6), + PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A), + PINMUX_IPSR_DATA(IP6_4_2, BPFCLK_B), + PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B), + + PINMUX_IPSR_DATA(IP6_6_5, SSI_SDATA6), + PINMUX_IPSR_DATA(IP6_6_5, HSPI_TX2_A), + PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B), + + PINMUX_IPSR_DATA(IP6_7, SSI_SCK5), + PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C), + + PINMUX_IPSR_DATA(IP6_8, SSI_WS5), + PINMUX_IPSR_DATA(IP6_8, TX4_C), + + PINMUX_IPSR_DATA(IP6_9, SSI_SDATA5), + PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D), + + PINMUX_IPSR_DATA(IP6_10, SSI_WS34), + PINMUX_IPSR_DATA(IP6_10, ARM_TRACEDATA_8), + + PINMUX_IPSR_DATA(IP6_12_11, SSI_SDATA4), + PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A), + PINMUX_IPSR_DATA(IP6_12_11, ARM_TRACEDATA_9), + + PINMUX_IPSR_DATA(IP6_13, SSI_SDATA3), + PINMUX_IPSR_DATA(IP6_13, ARM_TRACEDATA_10), + + PINMUX_IPSR_DATA(IP6_15_14, SSI_SCK012), + PINMUX_IPSR_DATA(IP6_15_14, ARM_TRACEDATA_11), + PINMUX_IPSR_DATA(IP6_15_14, TX0_D), + + PINMUX_IPSR_DATA(IP6_16, SSI_WS012), + PINMUX_IPSR_DATA(IP6_16, ARM_TRACEDATA_12), + + PINMUX_IPSR_DATA(IP6_18_17, SSI_SDATA2), + PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A), + PINMUX_IPSR_DATA(IP6_18_17, ARM_TRACEDATA_13), + PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A), + + PINMUX_IPSR_DATA(IP6_20_19, SSI_SDATA1), + PINMUX_IPSR_DATA(IP6_20_19, ARM_TRACEDATA_14), + PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A), + PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A), + + PINMUX_IPSR_DATA(IP6_21, SSI_SDATA0), + PINMUX_IPSR_DATA(IP6_21, ARM_TRACEDATA_15), + + PINMUX_IPSR_DATA(IP6_23_22, SD0_CLK), + PINMUX_IPSR_DATA(IP6_23_22, SUB_TDO), + + PINMUX_IPSR_DATA(IP6_25_24, SD0_CMD), + PINMUX_IPSR_DATA(IP6_25_24, SUB_TRST), + + PINMUX_IPSR_DATA(IP6_27_26, SD0_DAT0), + PINMUX_IPSR_DATA(IP6_27_26, SUB_TMS), + + PINMUX_IPSR_DATA(IP6_29_28, SD0_DAT1), + PINMUX_IPSR_DATA(IP6_29_28, SUB_TCK), + + PINMUX_IPSR_DATA(IP6_31_30, SD0_DAT2), + PINMUX_IPSR_DATA(IP6_31_30, SUB_TDI), + + /* IPSR7 */ + PINMUX_IPSR_DATA(IP7_1_0, SD0_DAT3), + PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B), + + PINMUX_IPSR_DATA(IP7_3_2, SD0_CD), + PINMUX_IPSR_DATA(IP7_3_2, TX5_A), + + PINMUX_IPSR_DATA(IP7_5_4, SD0_WP), + PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A), + + PINMUX_IPSR_DATA(IP7_8_6, VI1_CLKENB), + PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A), + PINMUX_IPSR_DATA(IP7_8_6, HTX1_A), + PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C), + + PINMUX_IPSR_DATA(IP7_11_9, VI1_FIELD), + PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A), + PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A), + PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C), + + PINMUX_IPSR_DATA(IP7_14_12, VI1_HSYNC), + PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A), + PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A), + PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A), + PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C), + + PINMUX_IPSR_DATA(IP7_17_15, VI1_VSYNC), + PINMUX_IPSR_DATA(IP7_17_15, HSPI_TX0), + PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A), + PINMUX_IPSR_DATA(IP7_17_15, BPFCLK_A), + PINMUX_IPSR_DATA(IP7_17_15, TX1_C), + + PINMUX_IPSR_DATA(IP7_20_18, TCLK0), + PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A), + PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A), + PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C), + PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C), + PINMUX_IPSR_DATA(IP7_20_18, SPEEDIN), + + PINMUX_IPSR_DATA(IP7_21, VI0_CLK), + PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A), + + PINMUX_IPSR_DATA(IP7_24_22, VI0_CLKENB), + PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP7_24_22, VI1_DATA0), + PINMUX_IPSR_DATA(IP7_24_22, DU1_DG6), + PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A), + PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B), + + PINMUX_IPSR_DATA(IP7_28_25, VI0_FIELD), + PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B), + PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP7_28_25, VI1_DATA1), + PINMUX_IPSR_DATA(IP7_28_25, DU1_DG7), + PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A), + PINMUX_IPSR_DATA(IP7_28_25, TX4_B), + + PINMUX_IPSR_DATA(IP7_31_29, VI0_HSYNC), + PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP7_31_29, VI1_DATA2), + PINMUX_IPSR_DATA(IP7_31_29, DU1_DR2), + PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A), + PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B), + + /* IPSR8 */ + PINMUX_IPSR_DATA(IP8_2_0, VI0_VSYNC), + PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP8_2_0, VI1_DATA3), + PINMUX_IPSR_DATA(IP8_2_0, DU1_DR3), + PINMUX_IPSR_DATA(IP8_2_0, HSPI_TX1_A), + PINMUX_IPSR_DATA(IP8_2_0, TX3_B), + + PINMUX_IPSR_DATA(IP8_5_3, VI0_DATA0_VI0_B0), + PINMUX_IPSR_DATA(IP8_5_3, DU1_DG2), + PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B), + PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D), + + PINMUX_IPSR_DATA(IP8_8_6, VI0_DATA1_VI0_B1), + PINMUX_IPSR_DATA(IP8_8_6, DU1_DG3), + PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B), + PINMUX_IPSR_DATA(IP8_8_6, TX3_D), + + PINMUX_IPSR_DATA(IP8_10_9, VI0_DATA2_VI0_B2), + PINMUX_IPSR_DATA(IP8_10_9, DU1_DG4), + PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C), + + PINMUX_IPSR_DATA(IP8_13_11, VI0_DATA3_VI0_B3), + PINMUX_IPSR_DATA(IP8_13_11, DU1_DG5), + PINMUX_IPSR_DATA(IP8_13_11, TX1_A), + PINMUX_IPSR_DATA(IP8_13_11, TX0_C), + + PINMUX_IPSR_DATA(IP8_15_14, VI0_DATA4_VI0_B4), + PINMUX_IPSR_DATA(IP8_15_14, DU1_DB2), + PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A), + + PINMUX_IPSR_DATA(IP8_18_16, VI0_DATA5_VI0_B5), + PINMUX_IPSR_DATA(IP8_18_16, DU1_DB3), + PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A), + PINMUX_IPSR_DATA(IP8_18_16, PWM4), + PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B), + + PINMUX_IPSR_DATA(IP8_21_19, VI0_DATA6_VI0_G0), + PINMUX_IPSR_DATA(IP8_21_19, DU1_DB4), + PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A), + PINMUX_IPSR_DATA(IP8_21_19, PWM5), + + PINMUX_IPSR_DATA(IP8_23_22, VI0_DATA7_VI0_G1), + PINMUX_IPSR_DATA(IP8_23_22, DU1_DB5), + PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A), + + PINMUX_IPSR_DATA(IP8_26_24, VI0_G2), + PINMUX_IPSR_DATA(IP8_26_24, SD2_CLK_B), + PINMUX_IPSR_DATA(IP8_26_24, VI1_DATA4), + PINMUX_IPSR_DATA(IP8_26_24, DU1_DR4), + PINMUX_IPSR_DATA(IP8_26_24, HTX1_B), + + PINMUX_IPSR_DATA(IP8_29_27, VI0_G3), + PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP8_29_27, VI1_DATA5), + PINMUX_IPSR_DATA(IP8_29_27, DU1_DR5), + PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B), + + /* IPSR9 */ + PINMUX_IPSR_DATA(IP9_2_0, VI0_G4), + PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP9_2_0, VI1_DATA6), + PINMUX_IPSR_DATA(IP9_2_0, DU1_DR6), + PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B), + + PINMUX_IPSR_DATA(IP9_5_3, VI0_G5), + PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP9_5_3, VI1_DATA7), + PINMUX_IPSR_DATA(IP9_5_3, DU1_DR7), + PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B), + + PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_8_6, VI1_CLK), + PINMUX_IPSR_DATA(IP9_8_6, ETH_REF_CLK), + PINMUX_IPSR_DATA(IP9_8_6, DU1_DOTCLKIN), + + PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_11_9, VI1_DATA8), + PINMUX_IPSR_DATA(IP9_11_9, DU1_DB6), + PINMUX_IPSR_DATA(IP9_11_9, ETH_TXD0), + PINMUX_IPSR_DATA(IP9_11_9, PWM2), + PINMUX_IPSR_DATA(IP9_11_9, TCLK1), + + PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_14_12, VI1_DATA9), + PINMUX_IPSR_DATA(IP9_14_12, DU1_DB7), + PINMUX_IPSR_DATA(IP9_14_12, ETH_TXD1), + PINMUX_IPSR_DATA(IP9_14_12, PWM3), + + PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A), + PINMUX_IPSR_DATA(IP9_17_15, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP9_17_15, IECLK), + PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C), + + PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_20_18, ETH_TX_EN), + PINMUX_IPSR_DATA(IP9_20_18, IETX), + PINMUX_IPSR_DATA(IP9_20_18, TX2_C), + + PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_23_21, ETH_RX_ER), + PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C), + PINMUX_IPSR_DATA(IP9_23_21, IERX), + PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C), + + PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A), + PINMUX_IPSR_DATA(IP9_26_24, DU1_DOTCLKOUT), + PINMUX_IPSR_DATA(IP9_26_24, ETH_RXD0), + PINMUX_IPSR_DATA(IP9_26_24, BPFCLK_C), + PINMUX_IPSR_DATA(IP9_26_24, TX2_D), + PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C), + + PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A), + PINMUX_IPSR_DATA(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP9_29_27, ETH_RXD1), + PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C), + PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D), + PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C), + + /* IPSR10 */ + PINMUX_IPSR_DATA(IP10_2_0, SD2_CLK_A), + PINMUX_IPSR_DATA(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP10_2_0, ATARD1), + PINMUX_IPSR_DATA(IP10_2_0, ETH_MDC), + PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B), + + PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP10_5_3, ATAWR1), + PINMUX_IPSR_DATA(IP10_5_3, ETH_MDIO), + PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B), + + PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_8_6, DU1_DISP), + PINMUX_IPSR_DATA(IP10_8_6, ATACS01), + PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B), + PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK), + PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A), + + PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_12_9, DU1_CDE), + PINMUX_IPSR_DATA(IP10_12_9, ATACS11), + PINMUX_IPSR_DATA(IP10_12_9, DACK1_B), + PINMUX_IPSR_DATA(IP10_12_9, ETH_MAGIC), + PINMUX_IPSR_DATA(IP10_12_9, CAN1_TX_A), + PINMUX_IPSR_DATA(IP10_12_9, PWM6), + + PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_15_13, VI1_DATA12), + PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B), + PINMUX_IPSR_DATA(IP10_15_13, ATADIR1), + PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B), + PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B), + + PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_18_16, VI1_DATA13), + PINMUX_IPSR_DATA(IP10_18_16, DACK2_B), + PINMUX_IPSR_DATA(IP10_18_16, ATAG1), + PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B), + PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B), + + PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_21_19, VI1_DATA14), + PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B), + PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B), + PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B), + PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A), + + PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_24_22, VI1_DATA15), + PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B), + PINMUX_IPSR_DATA(IP10_24_22, DACK0_B), + PINMUX_IPSR_DATA(IP10_24_22, HSPI_TX2_B), + PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C), +}; + +/* Pin numbers for pins without a corresponding GPIO port number are computed + * from the row and column numbers with a 1000 offset to avoid collisions with + * GPIO port numbers. + */ +#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), + + /* Pins not associated with a GPIO port */ + SH_PFC_PIN_NAMED(3, 20, C20), + SH_PFC_PIN_NAMED(20, 1, T1), + SH_PFC_PIN_NAMED(25, 2, Y2), +}; + +/* - macro */ +#define SH_PFC_PINS(name, args...) \ + static const unsigned int name ##_pins[] = { args } +#define SH_PFC_MUX1(name, arg1) \ + static const unsigned int name ##_mux[] = { arg1##_MARK } +#define SH_PFC_MUX2(name, arg1, arg2) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, } +#define SH_PFC_MUX3(name, arg1, arg2, arg3) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK } +#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK, arg4##_MARK } +#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK, arg4##_MARK, \ + arg5##_MARK, arg6##_MARK, \ + arg7##_MARK, arg8##_MARK, } + +/* - AUDIO macro -------------------------------------------------------------*/ +#define AUDIO_PFC_PIN(name, pin) SH_PFC_PINS(name, pin) +#define AUDIO_PFC_DAT(name, pin) SH_PFC_MUX1(name, pin) + +/* - AUDIO clock -------------------------------------------------------------*/ +AUDIO_PFC_PIN(audio_clk_a, RCAR_GP_PIN(2, 22)); +AUDIO_PFC_DAT(audio_clk_a, AUDIO_CLKA); +AUDIO_PFC_PIN(audio_clk_b, RCAR_GP_PIN(2, 23)); +AUDIO_PFC_DAT(audio_clk_b, AUDIO_CLKB); +AUDIO_PFC_PIN(audio_clk_c, RCAR_GP_PIN(2, 7)); +AUDIO_PFC_DAT(audio_clk_c, AUDIO_CLKC); +AUDIO_PFC_PIN(audio_clkout_a, RCAR_GP_PIN(2, 16)); +AUDIO_PFC_DAT(audio_clkout_a, AUDIO_CLKOUT_A); +AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16)); +AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B); + +/* - CAN macro --------_----------------------------------------------------- */ +#define CAN_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define CAN_PFC_DATA(name, tx, rx) SH_PFC_MUX2(name, tx, rx) +#define CAN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk) + +/* - CAN0 ------------------------------------------------------------------- */ +CAN_PFC_PINS(can0_data_a, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31)); +CAN_PFC_DATA(can0_data_a, CAN0_TX_A, CAN0_RX_A); +CAN_PFC_PINS(can0_data_b, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27)); +CAN_PFC_DATA(can0_data_b, CAN0_TX_B, CAN0_RX_B); + +/* - CAN1 ------------------------------------------------------------------- */ +CAN_PFC_PINS(can1_data_a, RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19)); +CAN_PFC_DATA(can1_data_a, CAN1_TX_A, CAN1_RX_A); +CAN_PFC_PINS(can1_data_b, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29)); +CAN_PFC_DATA(can1_data_b, CAN1_TX_B, CAN1_RX_B); + +/* - CAN_CLK --------------------------------------------------------------- */ +CAN_PFC_PINS(can_clk_a, RCAR_GP_PIN(3, 24)); +CAN_PFC_CLK(can_clk_a, CAN_CLK_A); +CAN_PFC_PINS(can_clk_b, RCAR_GP_PIN(1, 16)); +CAN_PFC_CLK(can_clk_b, CAN_CLK_B); +CAN_PFC_PINS(can_clk_c, RCAR_GP_PIN(4, 24)); +CAN_PFC_CLK(can_clk_c, CAN_CLK_C); +CAN_PFC_PINS(can_clk_d, RCAR_GP_PIN(2, 25)); +CAN_PFC_CLK(can_clk_d, CAN_CLK_D); + +/* - Ether ------------------------------------------------------------------ */ +SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17)); +static const unsigned int ether_rmii_mux[] = { + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, + ETH_MDIO_MARK, ETH_MDC_MARK, +}; +SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19)); +SH_PFC_MUX1(ether_link, ETH_LINK); +SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20)); +SH_PFC_MUX1(ether_magic, ETH_MAGIC); + +/* - SCIF macro ------------------------------------------------------------- */ +#define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +#define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx) +#define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts) +#define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck) + +/* - HSCIF0 ----------------------------------------------------------------- */ +SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); +SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A); +SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30)); +SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B); +SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A); +SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28)); +SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B); +SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19)); +SCIF_PFC_CLK(hscif0_clk, HSCK0); + +/* - HSCIF1 ----------------------------------------------------------------- */ +SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20)); +SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A); +SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); +SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B); +SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); +SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A); +SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7)); +SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B); +SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23)); +SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A); +SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2)); +SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B); + +/* - HSPI macro --------------------------------------------------------------*/ +#define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +#define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx) + +/* - HSPI0 -------------------------------------------------------------------*/ +HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); +HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A, + HSPI_RX0_A, HSPI_TX0); + +HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27)); +HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B, + HSPI_RX0_B, HSPI_TX0_B); + +/* - HSPI1 -------------------------------------------------------------------*/ +HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28)); +HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A, + HSPI_RX1_A, HSPI_TX1_A); + +HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26), + PIN_NUMBER(20, 1), PIN_NUMBER(25, 2)); +HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B, + HSPI_RX1_B, HSPI_TX1_B); + +/* - HSPI2 -------------------------------------------------------------------*/ +HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30)); +HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A, + HSPI_RX2_A, HSPI_TX2_A); + +HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24)); +HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B, + HSPI_RX2_B, HSPI_TX2_B); + +/* - I2C macro ------------------------------------------------------------- */ +#define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +#define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl) + +/* - I2C1 ------------------------------------------------------------------ */ +I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9)); +I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A); +I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); +I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B); + +/* - I2C2 ------------------------------------------------------------------ */ +I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); +I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A); +I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); +I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B); +I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); +I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C); + +/* - I2C3 ------------------------------------------------------------------ */ +I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15)); +I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A); +I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19)); +I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B); +I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); +I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); + +/* - MMC macro -------------------------------------------------------------- */ +#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) +#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) +#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) +#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ + SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) + +/* - MMC -------------------------------------------------------------------- */ +MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); +MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); +MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); +MMC_PFC_DAT1(mmc_data1, MMC_D0); +MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); +MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, + MMC_D2, MMC_D3); +MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), + RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); +MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1, + MMC_D2, MMC_D3, + MMC_D4, MMC_D5, + MMC_D6, MMC_D7); + +/* - SCIF CLOCK ------------------------------------------------------------- */ +SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16)); +SCIF_PFC_CLK(scif_clk, SCIF_CLK); + +/* - SCIF0 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); +SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A); +SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2)); +SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B); +SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31)); +SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C); +SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1)); +SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D); +SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0); +SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19)); +SCIF_PFC_CLK(scif0_clk, SCK0); + +/* - SCIF1 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1)); +SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A); +SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25)); +SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B); +SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); +SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C); +SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31)); +SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D); +SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); +SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A); +SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19)); +SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C); +SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2)); +SCIF_PFC_CLK(scif1_clk_a, SCK1_A); +SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20)); +SCIF_PFC_CLK(scif1_clk_c, SCK1_C); + +/* - SCIF2 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27)); +SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A); +SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28)); +SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B); +SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14)); +SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C); +SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); +SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D); +SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); +SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E); +SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9)); +SCIF_PFC_CLK(scif2_clk_a, SCK2_A); +SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20)); +SCIF_PFC_CLK(scif2_clk_b, SCK2_B); +SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12)); +SCIF_PFC_CLK(scif2_clk_c, SCK2_C); + +/* - SCIF3 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9)); +SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A); +SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27)); +SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B); +SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31)); +SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C); +SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29)); +SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D); + +/* - SCIF4 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4)); +SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A); +SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25)); +SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B); +SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31)); +SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C); + +/* - SCIF5 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18)); +SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A); +SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14)); +SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); + +/* - SDHI macro ------------------------------------------------------------- */ +#define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) +#define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) +#define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) +#define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd) +#define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp) + +/* - SDHI0 ------------------------------------------------------------------ */ +SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17)); +SDHI_PFC_CDPN(sdhi0_cd, SD0_CD); +SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12)); +SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD); +SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13)); +SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0); +SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16)); +SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1, + SD0_DAT2, SD0_DAT3); +SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18)); +SDHI_PFC_WPPN(sdhi0_wp, SD0_WP); + +/* - SDHI1 ------------------------------------------------------------------ */ +SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30)); +SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A); +SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24)); +SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B); +SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); +SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A); +SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); +SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B); +SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7)); +SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A); +SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18)); +SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B); +SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); +SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A, + SD1_DAT2_A, SD1_DAT3_A); +SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B, + SD1_DAT2_B, SD1_DAT3_B); +SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31)); +SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A); +SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25)); +SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B); + +/* - SDH2 ------------------------------------------------------------------- */ +SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23)); +SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A); +SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27)); +SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B); +SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); +SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A); +SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); +SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B); +SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19)); +SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A); +SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7)); +SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B); +SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22)); +SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A, + SD2_DAT2_A, SD2_DAT3_A); +SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26)); +SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B, + SD2_DAT2_B, SD2_DAT3_B); +SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24)); +SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A); +SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28)); +SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B); + +/* - SSI macro -------------------------------------------------------------- */ +#define SSI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define SSI_PFC_CTRL(name, sck, ws) SH_PFC_MUX2(name, sck, ws) +#define SSI_PFC_DATA(name, d) SH_PFC_MUX1(name, d) + +/* - SSI 0/1/2 -------------------------------------------------------------- */ +SSI_PFC_PINS(ssi012_ctrl, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7)); +SSI_PFC_CTRL(ssi012_ctrl, SSI_SCK012, SSI_WS012); +SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10)); +SSI_PFC_DATA(ssi0_data, SSI_SDATA0); +SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21)); +SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A); +SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); +SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B); +SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9)); +SSI_PFC_DATA(ssi1_data, SSI_SDATA1); +SSI_PFC_PINS(ssi2_a_ctrl, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(3, 4)); +SSI_PFC_CTRL(ssi2_a_ctrl, SSI_SCK2_A, SSI_WS2_A); +SSI_PFC_PINS(ssi2_b_ctrl, RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 17)); +SSI_PFC_CTRL(ssi2_b_ctrl, SSI_SCK2_B, SSI_WS2_B); +SSI_PFC_PINS(ssi2_data, RCAR_GP_PIN(3, 8)); +SSI_PFC_DATA(ssi2_data, SSI_SDATA2); + +/* - SSI 3/4 ---------------------------------------------------------------- */ +SSI_PFC_PINS(ssi34_ctrl, RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3)); +SSI_PFC_CTRL(ssi34_ctrl, SSI_SCK34, SSI_WS34); +SSI_PFC_PINS(ssi3_data, RCAR_GP_PIN(3, 5)); +SSI_PFC_DATA(ssi3_data, SSI_SDATA3); +SSI_PFC_PINS(ssi4_ctrl, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); +SSI_PFC_CTRL(ssi4_ctrl, SSI_SCK4, SSI_WS4); +SSI_PFC_PINS(ssi4_data, RCAR_GP_PIN(3, 4)); +SSI_PFC_DATA(ssi4_data, SSI_SDATA4); + +/* - SSI 5 ------------------------------------------------------------------ */ +SSI_PFC_PINS(ssi5_ctrl, RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0)); +SSI_PFC_CTRL(ssi5_ctrl, SSI_SCK5, SSI_WS5); +SSI_PFC_PINS(ssi5_data, RCAR_GP_PIN(3, 1)); +SSI_PFC_DATA(ssi5_data, SSI_SDATA5); + +/* - SSI 6 ------------------------------------------------------------------ */ +SSI_PFC_PINS(ssi6_ctrl, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29)); +SSI_PFC_CTRL(ssi6_ctrl, SSI_SCK6, SSI_WS6); +SSI_PFC_PINS(ssi6_data, RCAR_GP_PIN(2, 30)); +SSI_PFC_DATA(ssi6_data, SSI_SDATA6); + +/* - SSI 7/8 --------------------------------------------------------------- */ +SSI_PFC_PINS(ssi78_ctrl, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25)); +SSI_PFC_CTRL(ssi78_ctrl, SSI_SCK78, SSI_WS78); +SSI_PFC_PINS(ssi7_data, RCAR_GP_PIN(2, 27)); +SSI_PFC_DATA(ssi7_data, SSI_SDATA7); +SSI_PFC_PINS(ssi8_data, RCAR_GP_PIN(2, 26)); +SSI_PFC_DATA(ssi8_data, SSI_SDATA8); + +/* - USB0 ------------------------------------------------------------------- */ +SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1)); +SH_PFC_MUX1(usb0, PENC0); +SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3)); +SH_PFC_MUX1(usb0_ovc, USB_OVC0); + +/* - USB1 ------------------------------------------------------------------- */ +SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2)); +SH_PFC_MUX1(usb1, PENC1); +SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4)); +SH_PFC_MUX1(usb1_ovc, USB_OVC1); + +/* - VIN macros ------------------------------------------------------------- */ +#define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ + SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) +#define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk) +#define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync) + +/* - VIN0 ------------------------------------------------------------------- */ +VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30), + RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0), + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); +VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1, + VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3, + VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5, + VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1); +VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24)); +VIN_PFC_CLK(vin0_clk, VI0_CLK); +VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28)); +VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC); +/* - VIN1 ------------------------------------------------------------------- */ +VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8)); +VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1, + VI1_DATA2, VI1_DATA3, + VI1_DATA4, VI1_DATA5, + VI1_DATA6, VI1_DATA7); +VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9)); +VIN_PFC_CLK(vin1_clk, VI1_CLK); +VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); +VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC); + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(can0_data_a), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data_a), + SH_PFC_PIN_GROUP(can1_data_b), + SH_PFC_PIN_GROUP(can_clk_a), + SH_PFC_PIN_GROUP(can_clk_b), + SH_PFC_PIN_GROUP(can_clk_c), + SH_PFC_PIN_GROUP(can_clk_d), + SH_PFC_PIN_GROUP(ether_rmii), + SH_PFC_PIN_GROUP(ether_link), + SH_PFC_PIN_GROUP(ether_magic), + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_a), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hspi0_a), + SH_PFC_PIN_GROUP(hspi0_b), + SH_PFC_PIN_GROUP(hspi1_a), + SH_PFC_PIN_GROUP(hspi1_b), + SH_PFC_PIN_GROUP(hspi2_a), + SH_PFC_PIN_GROUP(hspi2_b), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c3_a), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif0_data_a), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_ctrl_a), + SH_PFC_PIN_GROUP(scif1_ctrl_c), + SH_PFC_PIN_GROUP(scif1_clk_a), + SH_PFC_PIN_GROUP(scif1_clk_c), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_data_d), + SH_PFC_PIN_GROUP(scif2_data_e), + SH_PFC_PIN_GROUP(scif2_clk_a), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_clk_c), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif3_data_d), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_cd_a), + SH_PFC_PIN_GROUP(sdhi1_cd_b), + SH_PFC_PIN_GROUP(sdhi1_ctrl_a), + SH_PFC_PIN_GROUP(sdhi1_ctrl_b), + SH_PFC_PIN_GROUP(sdhi1_data1_a), + SH_PFC_PIN_GROUP(sdhi1_data1_b), + SH_PFC_PIN_GROUP(sdhi1_data4_a), + SH_PFC_PIN_GROUP(sdhi1_data4_b), + SH_PFC_PIN_GROUP(sdhi1_wp_a), + SH_PFC_PIN_GROUP(sdhi1_wp_b), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_ctrl_a), + SH_PFC_PIN_GROUP(sdhi2_ctrl_b), + SH_PFC_PIN_GROUP(sdhi2_data1_a), + SH_PFC_PIN_GROUP(sdhi2_data1_b), + SH_PFC_PIN_GROUP(sdhi2_data4_a), + SH_PFC_PIN_GROUP(sdhi2_data4_b), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(ssi012_ctrl), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi1_a_ctrl), + SH_PFC_PIN_GROUP(ssi1_b_ctrl), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi2_a_ctrl), + SH_PFC_PIN_GROUP(ssi2_b_ctrl), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb1_ovc), + SH_PFC_PIN_GROUP(vin0_data8), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_clk), + SH_PFC_PIN_GROUP(vin1_sync), +}; + +static const char * const audio_clk_groups[] = { + "audio_clk_a", + "audio_clk_b", + "audio_clk_c", + "audio_clkout_a", + "audio_clkout_b", +}; + +static const char * const can0_groups[] = { + "can0_data_a", + "can0_data_b", + "can_clk_a", + "can_clk_b", + "can_clk_c", + "can_clk_d", +}; + +static const char * const can1_groups[] = { + "can1_data_a", + "can1_data_b", + "can_clk_a", + "can_clk_b", + "can_clk_c", + "can_clk_d", +}; + +static const char * const ether_groups[] = { + "ether_rmii", + "ether_link", + "ether_magic", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data_a", + "hscif0_data_b", + "hscif0_ctrl_a", + "hscif0_ctrl_b", + "hscif0_clk", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_data_b", + "hscif1_ctrl_a", + "hscif1_ctrl_b", + "hscif1_clk_a", + "hscif1_clk_b", +}; + +static const char * const hspi0_groups[] = { + "hspi0_a", + "hspi0_b", +}; + +static const char * const hspi1_groups[] = { + "hspi1_a", + "hspi1_b", +}; + +static const char * const hspi2_groups[] = { + "hspi2_a", + "hspi2_b", +}; + +static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", + "i2c2_c", +}; + +static const char * const i2c3_groups[] = { + "i2c3_a", + "i2c3_b", + "i2c3_c", +}; + +static const char * const mmc_groups[] = { + "mmc_ctrl", + "mmc_data1", + "mmc_data4", + "mmc_data8", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const char * const scif0_groups[] = { + "scif0_data_a", + "scif0_data_b", + "scif0_data_c", + "scif0_data_d", + "scif0_ctrl", + "scif0_clk", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_data_b", + "scif1_data_c", + "scif1_data_d", + "scif1_ctrl_a", + "scif1_ctrl_c", + "scif1_clk_a", + "scif1_clk_c", +}; + +static const char * const scif2_groups[] = { + "scif2_data_a", + "scif2_data_b", + "scif2_data_c", + "scif2_data_d", + "scif2_data_e", + "scif2_clk_a", + "scif2_clk_b", + "scif2_clk_c", +}; + +static const char * const scif3_groups[] = { + "scif3_data_a", + "scif3_data_b", + "scif3_data_c", + "scif3_data_d", +}; + +static const char * const scif4_groups[] = { + "scif4_data_a", + "scif4_data_b", + "scif4_data_c", +}; + +static const char * const scif5_groups[] = { + "scif5_data_a", + "scif5_data_b", +}; + + +static const char * const sdhi0_groups[] = { + "sdhi0_cd", + "sdhi0_ctrl", + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_cd_a", + "sdhi1_cd_b", + "sdhi1_ctrl_a", + "sdhi1_ctrl_b", + "sdhi1_data1_a", + "sdhi1_data1_b", + "sdhi1_data4_a", + "sdhi1_data4_b", + "sdhi1_wp_a", + "sdhi1_wp_b", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_cd_a", + "sdhi2_cd_b", + "sdhi2_ctrl_a", + "sdhi2_ctrl_b", + "sdhi2_data1_a", + "sdhi2_data1_b", + "sdhi2_data4_a", + "sdhi2_data4_b", + "sdhi2_wp_a", + "sdhi2_wp_b", +}; + +static const char * const ssi_groups[] = { + "ssi012_ctrl", + "ssi0_data", + "ssi1_a_ctrl", + "ssi1_b_ctrl", + "ssi1_data", + "ssi2_a_ctrl", + "ssi2_b_ctrl", + "ssi2_data", + "ssi34_ctrl", + "ssi3_data", + "ssi4_ctrl", + "ssi4_data", + "ssi5_ctrl", + "ssi5_data", + "ssi6_ctrl", + "ssi6_data", + "ssi78_ctrl", + "ssi7_data", + "ssi8_data", +}; + +static const char * const usb0_groups[] = { + "usb0", + "usb0_ovc", +}; + +static const char * const usb1_groups[] = { + "usb1", + "usb1_ovc", +}; + +static const char * const vin0_groups[] = { + "vin0_data8", + "vin0_clk", + "vin0_sync", +}; + +static const char * const vin1_groups[] = { + "vin1_data8", + "vin1_clk", + "vin1_sync", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(ether), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hspi0), + SH_PFC_FUNCTION(hspi1), + SH_PFC_FUNCTION(hspi2), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { + GP_0_31_FN, FN_IP1_14_11, + GP_0_30_FN, FN_IP1_10_8, + GP_0_29_FN, FN_IP1_7_5, + GP_0_28_FN, FN_IP1_4_2, + GP_0_27_FN, FN_IP1_1, + GP_0_26_FN, FN_IP1_0, + GP_0_25_FN, FN_IP0_30, + GP_0_24_FN, FN_IP0_29, + GP_0_23_FN, FN_IP0_28, + GP_0_22_FN, FN_IP0_27, + GP_0_21_FN, FN_IP0_26, + GP_0_20_FN, FN_IP0_25, + GP_0_19_FN, FN_IP0_24, + GP_0_18_FN, FN_IP0_23, + GP_0_17_FN, FN_IP0_22, + GP_0_16_FN, FN_IP0_21, + GP_0_15_FN, FN_IP0_20, + GP_0_14_FN, FN_IP0_19, + GP_0_13_FN, FN_IP0_18, + GP_0_12_FN, FN_IP0_17, + GP_0_11_FN, FN_IP0_16, + GP_0_10_FN, FN_IP0_15, + GP_0_9_FN, FN_A3, + GP_0_8_FN, FN_A2, + GP_0_7_FN, FN_A1, + GP_0_6_FN, FN_IP0_14_12, + GP_0_5_FN, FN_IP0_11_8, + GP_0_4_FN, FN_IP0_7_5, + GP_0_3_FN, FN_IP0_4_2, + GP_0_2_FN, FN_PENC1, + GP_0_1_FN, FN_PENC0, + GP_0_0_FN, FN_IP0_1_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { + GP_1_31_FN, FN_IP4_6_4, + GP_1_30_FN, FN_IP4_3_1, + GP_1_29_FN, FN_IP4_0, + GP_1_28_FN, FN_IP3_31, + GP_1_27_FN, FN_IP3_30, + GP_1_26_FN, FN_IP3_29, + GP_1_25_FN, FN_IP3_28, + GP_1_24_FN, FN_IP3_27, + GP_1_23_FN, FN_IP3_26_24, + GP_1_22_FN, FN_IP3_23_21, + GP_1_21_FN, FN_IP3_20_19, + GP_1_20_FN, FN_IP3_18_16, + GP_1_19_FN, FN_IP3_15_13, + GP_1_18_FN, FN_IP3_12_10, + GP_1_17_FN, FN_IP3_9_8, + GP_1_16_FN, FN_IP3_7_5, + GP_1_15_FN, FN_IP3_4_2, + GP_1_14_FN, FN_IP3_1_0, + GP_1_13_FN, FN_IP2_31, + GP_1_12_FN, FN_IP2_30, + GP_1_11_FN, FN_IP2_17, + GP_1_10_FN, FN_IP2_16_14, + GP_1_9_FN, FN_IP2_13_12, + GP_1_8_FN, FN_IP2_11_9, + GP_1_7_FN, FN_IP2_8_6, + GP_1_6_FN, FN_IP2_5_3, + GP_1_5_FN, FN_IP2_2_0, + GP_1_4_FN, FN_IP1_29_28, + GP_1_3_FN, FN_IP1_27_25, + GP_1_2_FN, FN_IP1_24, + GP_1_1_FN, FN_WE0, + GP_1_0_FN, FN_IP1_23_21 } + }, + { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { + GP_2_31_FN, FN_IP6_7, + GP_2_30_FN, FN_IP6_6_5, + GP_2_29_FN, FN_IP6_4_2, + GP_2_28_FN, FN_IP6_1_0, + GP_2_27_FN, FN_IP5_30_29, + GP_2_26_FN, FN_IP5_28_26, + GP_2_25_FN, FN_IP5_25_23, + GP_2_24_FN, FN_IP5_22_21, + GP_2_23_FN, FN_AUDIO_CLKB, + GP_2_22_FN, FN_AUDIO_CLKA, + GP_2_21_FN, FN_IP5_20_18, + GP_2_20_FN, FN_IP5_17_15, + GP_2_19_FN, FN_IP5_14_13, + GP_2_18_FN, FN_IP5_12, + GP_2_17_FN, FN_IP5_11_10, + GP_2_16_FN, FN_IP5_9_8, + GP_2_15_FN, FN_IP5_7, + GP_2_14_FN, FN_IP5_6, + GP_2_13_FN, FN_IP5_5_4, + GP_2_12_FN, FN_IP5_3_2, + GP_2_11_FN, FN_IP5_1_0, + GP_2_10_FN, FN_IP4_30_29, + GP_2_9_FN, FN_IP4_28_27, + GP_2_8_FN, FN_IP4_26_25, + GP_2_7_FN, FN_IP4_24_21, + GP_2_6_FN, FN_IP4_20_17, + GP_2_5_FN, FN_IP4_16_15, + GP_2_4_FN, FN_IP4_14_13, + GP_2_3_FN, FN_IP4_12_11, + GP_2_2_FN, FN_IP4_10_9, + GP_2_1_FN, FN_IP4_8, + GP_2_0_FN, FN_IP4_7 } + }, + { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { + GP_3_31_FN, FN_IP8_10_9, + GP_3_30_FN, FN_IP8_8_6, + GP_3_29_FN, FN_IP8_5_3, + GP_3_28_FN, FN_IP8_2_0, + GP_3_27_FN, FN_IP7_31_29, + GP_3_26_FN, FN_IP7_28_25, + GP_3_25_FN, FN_IP7_24_22, + GP_3_24_FN, FN_IP7_21, + GP_3_23_FN, FN_IP7_20_18, + GP_3_22_FN, FN_IP7_17_15, + GP_3_21_FN, FN_IP7_14_12, + GP_3_20_FN, FN_IP7_11_9, + GP_3_19_FN, FN_IP7_8_6, + GP_3_18_FN, FN_IP7_5_4, + GP_3_17_FN, FN_IP7_3_2, + GP_3_16_FN, FN_IP7_1_0, + GP_3_15_FN, FN_IP6_31_30, + GP_3_14_FN, FN_IP6_29_28, + GP_3_13_FN, FN_IP6_27_26, + GP_3_12_FN, FN_IP6_25_24, + GP_3_11_FN, FN_IP6_23_22, + GP_3_10_FN, FN_IP6_21, + GP_3_9_FN, FN_IP6_20_19, + GP_3_8_FN, FN_IP6_18_17, + GP_3_7_FN, FN_IP6_16, + GP_3_6_FN, FN_IP6_15_14, + GP_3_5_FN, FN_IP6_13, + GP_3_4_FN, FN_IP6_12_11, + GP_3_3_FN, FN_IP6_10, + GP_3_2_FN, FN_SSI_SCK34, + GP_3_1_FN, FN_IP6_9, + GP_3_0_FN, FN_IP6_8 } + }, + { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_26_FN, FN_AVS2, + GP_4_25_FN, FN_AVS1, + GP_4_24_FN, FN_IP10_24_22, + GP_4_23_FN, FN_IP10_21_19, + GP_4_22_FN, FN_IP10_18_16, + GP_4_21_FN, FN_IP10_15_13, + GP_4_20_FN, FN_IP10_12_9, + GP_4_19_FN, FN_IP10_8_6, + GP_4_18_FN, FN_IP10_5_3, + GP_4_17_FN, FN_IP10_2_0, + GP_4_16_FN, FN_IP9_29_27, + GP_4_15_FN, FN_IP9_26_24, + GP_4_14_FN, FN_IP9_23_21, + GP_4_13_FN, FN_IP9_20_18, + GP_4_12_FN, FN_IP9_17_15, + GP_4_11_FN, FN_IP9_14_12, + GP_4_10_FN, FN_IP9_11_9, + GP_4_9_FN, FN_IP9_8_6, + GP_4_8_FN, FN_IP9_5_3, + GP_4_7_FN, FN_IP9_2_0, + GP_4_6_FN, FN_IP8_29_27, + GP_4_5_FN, FN_IP8_26_24, + GP_4_4_FN, FN_IP8_23_22, + GP_4_3_FN, FN_IP8_21_19, + GP_4_2_FN, FN_IP8_18_16, + GP_4_1_FN, FN_IP8_15_14, + GP_4_0_FN, FN_IP8_13_11 } + }, + + { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) { + /* IP0_31 [1] */ + 0, 0, + /* IP0_30 [1] */ + FN_A19, 0, + /* IP0_29 [1] */ + FN_A18, 0, + /* IP0_28 [1] */ + FN_A17, 0, + /* IP0_27 [1] */ + FN_A16, 0, + /* IP0_26 [1] */ + FN_A15, 0, + /* IP0_25 [1] */ + FN_A14, 0, + /* IP0_24 [1] */ + FN_A13, 0, + /* IP0_23 [1] */ + FN_A12, 0, + /* IP0_22 [1] */ + FN_A11, 0, + /* IP0_21 [1] */ + FN_A10, 0, + /* IP0_20 [1] */ + FN_A9, 0, + /* IP0_19 [1] */ + FN_A8, 0, + /* IP0_18 [1] */ + FN_A7, 0, + /* IP0_17 [1] */ + FN_A6, 0, + /* IP0_16 [1] */ + FN_A5, 0, + /* IP0_15 [1] */ + FN_A4, 0, + /* IP0_14_12 [3] */ + FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0, + FN_ATAG0_A, 0, FN_REMOCON_B, 0, + /* IP0_11_8 [4] */ + FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS, + FN_ATADIR0_A, 0, FN_SDSELF_B, 0, + FN_PWM4_B, 0, 0, 0, + 0, 0, 0, 0, + /* IP0_7_5 [3] */ + FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1, + FN_RX2_E, FN_SCL2_B, 0, 0, + /* IP0_4_2 [3] */ + FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0, + FN_TX2_E, FN_SDA2_B, 0, 0, + /* IP0_1_0 [2] */ + FN_PRESETOUT, 0, FN_PWM1, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, + 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) { + /* IP1_31 [1] */ + 0, 0, + /* IP1_30 [1] */ + 0, 0, + /* IP1_29_28 [2] */ + FN_EX_CS1, FN_MMC_D4, 0, 0, + /* IP1_27_25 [3] */ + FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C, + FN_TS_SCK0_A, 0, 0, 0, + /* IP1_24 [1] */ + FN_WE1, FN_ATAWR0_B, + /* IP1_23_21 [3] */ + FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR, + 0, 0, 0, 0, + /* IP1_20_18 [3] */ + FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, + FN_SCK2_B, 0, 0, 0, + /* IP1_17 [1] */ + FN_CS0, FN_HSPI_RX1_B, + /* IP1_16_15 [2] */ + FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0, + /* IP1_14_11 [4] */ + FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25, + FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C, + FN_TS_SDAT0_A, 0, 0, 0, + 0, 0, 0, 0, + /* IP1_10_8 [3] */ + FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24, + FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A, + /* IP1_7_5 [3] */ + FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, + FN_TS_SDEN0_A, 0, 0, 0, + /* IP1_4_2 [3] */ + FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, + 0, 0, 0, 0, + /* IP1_1 [1] */ + FN_A21, FN_HSPI_CLK1_B, + /* IP1_0 [1] */ + FN_A20, FN_HSPI_CS1_B, + } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) { + /* IP2_31 [1] */ + FN_MLB_CLK, FN_IRQ1_A, + /* IP2_30 [1] */ + FN_RD_WR_B, FN_IRQ0, + /* IP2_29 [1] */ + FN_D11, 0, + /* IP2_28 [1] */ + FN_D10, 0, + /* IP2_27 [1] */ + FN_D9, 0, + /* IP2_26 [1] */ + FN_D8, 0, + /* IP2_25 [1] */ + FN_D7, 0, + /* IP2_24 [1] */ + FN_D6, 0, + /* IP2_23 [1] */ + FN_D5, 0, + /* IP2_22 [1] */ + FN_D4, 0, + /* IP2_21 [1] */ + FN_D3, 0, + /* IP2_20 [1] */ + FN_D2, 0, + /* IP2_19 [1] */ + FN_D1, 0, + /* IP2_18 [1] */ + FN_D0, 0, + /* IP2_17 [1] */ + FN_EX_WAIT0, FN_PWM0_C, + /* IP2_16_14 [3] */ + FN_DACK0, 0, 0, FN_TX3_A, + FN_DRACK0, 0, 0, 0, + /* IP2_13_12 [2] */ + FN_DREQ0_A, 0, 0, FN_RX3_A, + /* IP2_11_9 [3] */ + FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A, + FN_EX_CS5, FN_EX_WAIT2_A, 0, 0, + /* IP2_8_6 [3] */ + FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0, + FN_EX_CS4, FN_EX_WAIT1_A, 0, 0, + /* IP2_5_3 [3] */ + FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10, + FN_EX_CS3, 0, 0, 0, + /* IP2_2_0 [3] */ + FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00, + FN_EX_CS2, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, + 1, 1, 1, 1, 1, 3, 3, 2, + 3, 3, 3, 2, 3, 3, 2) { + /* IP3_31 [1] */ + FN_DU0_DR6, FN_LCDOUT6, + /* IP3_30 [1] */ + FN_DU0_DR5, FN_LCDOUT5, + /* IP3_29 [1] */ + FN_DU0_DR4, FN_LCDOUT4, + /* IP3_28 [1] */ + FN_DU0_DR3, FN_LCDOUT3, + /* IP3_27 [1] */ + FN_DU0_DR2, FN_LCDOUT2, + /* IP3_26_24 [3] */ + FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, + FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, + /* IP3_23_21 [3] */ + FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2, + FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, + /* IP3_20_19 [2] */ + FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0, + /* IP3_18_16 [3] */ + FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0, + 0, 0, 0, 0, + /* IP3_15_13 [3] */ + FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, + 0, 0, 0, 0, + /* IP3_12_10 [3] */ + FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0, + 0, 0, 0, 0, + /* IP3_9_8 [2] */ + FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0, + /* IP3_7_5 [3] */ + FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B, + FN_SDA3_B, 0, 0, 0, + /* IP3_4_2 [3] */ + FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, + FN_SDSELF_B, 0, 0, 0, + /* IP3_1_0 [2] */ + FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, + } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, + 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) { + /* IP4_31 [1] */ + 0, 0, + /* IP4_30_29 [2] */ + FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0, + /* IP4_28_27 [2] */ + FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0, + /* IP4_26_25 [2] */ + FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0, + /* IP4_24_21 [4] */ + FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, + FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0, + FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0, + 0, 0, 0, 0, + /* IP4_20_17 [4] */ + FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16, + FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A, + FN_ADICLK, FN_TS_SDAT0_B, 0, 0, + 0, 0, 0, 0, + /* IP4_16_15 [2] */ + FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0, + /* IP4_14_13 [2] */ + FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0, + /* IP4_12_11 [2] */ + FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0, + /* IP4_10_9 [2] */ + FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0, + /* IP4_8 [1] */ + FN_DU0_DG3, FN_LCDOUT11, + /* IP4_7 [1] */ + FN_DU0_DG2, FN_LCDOUT10, + /* IP4_6_4 [3] */ + FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5, + FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0, + /* IP4_3_1 [3] */ + FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4, + FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0, + /* IP4_0 [1] */ + FN_DU0_DR7, FN_LCDOUT7, + } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, + 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) { + + /* IP5_31 [1] */ + 0, 0, + /* IP5_30_29 [2] */ + FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B, + /* IP5_28_26 [3] */ + FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A, + FN_CAN0_TX_B, 0, 0, 0, + /* IP5_25_23 [3] */ + FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, + FN_CAN_CLK_D, 0, 0, 0, + /* IP5_22_21 [2] */ + FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, + /* IP5_20_18 [3] */ + FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC, + FN_ARM_TRACECTL, FN_FMIN_D, 0, 0, + /* IP5_17_15 [3] */ + FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK, + FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0, + /* IP5_14_13 [2] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_FMCLK_D, 0, + /* IP5_12 [1] */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + /* IP5_11_10 [2] */ + FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, + FN_QSTH_QHS, 0, + /* IP5_9_8 [2] */ + FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, + FN_AUDIO_CLKOUT_A, FN_REMOCON_C, + /* IP5_7 [1] */ + FN_DU0_DOTCLKO_UT0, FN_QCLK, + /* IP5_6 [1] */ + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, + /* IP5_5_4 [2] */ + FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0, + /* IP5_3_2 [2] */ + FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0, + /* IP5_1_0 [2] */ + FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, + 2, 2, 2, 2, 2, 1, 2, 2, 1, 2, + 1, 2, 1, 1, 1, 1, 2, 3, 2) { + /* IP6_31_30 [2] */ + FN_SD0_DAT2, 0, FN_SUB_TDI, 0, + /* IP6_29_28 [2] */ + FN_SD0_DAT1, 0, FN_SUB_TCK, 0, + /* IP6_27_26 [2] */ + FN_SD0_DAT0, 0, FN_SUB_TMS, 0, + /* IP6_25_24 [2] */ + FN_SD0_CMD, 0, FN_SUB_TRST, 0, + /* IP6_23_22 [2] */ + FN_SD0_CLK, 0, FN_SUB_TDO, 0, + /* IP6_21 [1] */ + FN_SSI_SDATA0, FN_ARM_TRACEDATA_15, + /* IP6_20_19 [2] */ + FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, + FN_SCL1_A, FN_SCK2_A, + /* IP6_18_17 [2] */ + FN_SSI_SDATA2, FN_HSPI_CS2_A, + FN_ARM_TRACEDATA_13, FN_SDA1_A, + /* IP6_16 [1] */ + FN_SSI_WS012, FN_ARM_TRACEDATA_12, + /* IP6_15_14 [2] */ + FN_SSI_SCK012, FN_ARM_TRACEDATA_11, + FN_TX0_D, 0, + /* IP6_13 [1] */ + FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, + /* IP6_12_11 [2] */ + FN_SSI_SDATA4, FN_SSI_WS2_A, + FN_ARM_TRACEDATA_9, 0, + /* IP6_10 [1] */ + FN_SSI_WS34, FN_ARM_TRACEDATA_8, + /* IP6_9 [1] */ + FN_SSI_SDATA5, FN_RX0_D, + /* IP6_8 [1] */ + FN_SSI_WS5, FN_TX4_C, + /* IP6_7 [1] */ + FN_SSI_SCK5, FN_RX4_C, + /* IP6_6_5 [2] */ + FN_SSI_SDATA6, FN_HSPI_TX2_A, + FN_FMIN_B, 0, + /* IP6_4_2 [3] */ + FN_SSI_WS6, FN_HSPI_CLK2_A, + FN_BPFCLK_B, FN_CAN1_RX_B, + 0, 0, 0, 0, + /* IP6_1_0 [2] */ + FN_SSI_SCK6, FN_HSPI_RX2_A, + FN_FMCLK_B, FN_CAN1_TX_B, + } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, + 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) { + + /* IP7_31_29 [3] */ + FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2, + 0, FN_HSPI_CS1_A, FN_RX3_B, 0, + /* IP7_28_25 [4] */ + FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1, + FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IP7_24_22 [3] */ + FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, + 0, FN_HSPI_RX1_A, FN_RX4_B, 0, + /* IP7_21 [1] */ + FN_VI0_CLK, FN_CAN_CLK_A, + /* IP7_20_18 [3] */ + FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0, + FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0, + /* IP7_17_15 [3] */ + FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, + 0, FN_TX1_C, 0, 0, + /* IP7_14_12 [3] */ + FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A, + 0, FN_RX1_C, 0, 0, + /* IP7_11_9 [3] */ + FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0, + FN_SCK1_C, 0, 0, 0, + /* IP7_8_6 [3] */ + FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0, + FN_RTS1_C, 0, 0, 0, + /* IP7_5_4 [2] */ + FN_SD0_WP, 0, FN_RX5_A, 0, + /* IP7_3_2 [2] */ + FN_SD0_CD, 0, FN_TX5_A, 0, + /* IP7_1_0 [2] */ + FN_SD0_DAT3, 0, FN_IRQ1_B, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, + 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) { + /* IP8_31 [1] */ + 0, 0, + /* IP8_30 [1] */ + 0, 0, + /* IP8_29_27 [3] */ + FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5, + 0, FN_HRX1_B, 0, 0, + /* IP8_26_24 [3] */ + FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4, + 0, FN_HTX1_B, 0, 0, + /* IP8_23_22 [2] */ + FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, + FN_RTS1_A, 0, + /* IP8_21_19 [3] */ + FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, + FN_CTS1_A, FN_PWM5, + 0, 0, 0, 0, + /* IP8_18_16 [3] */ + FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4, + 0, FN_HSCK1_B, 0, 0, + /* IP8_15_14 [2] */ + FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0, + /* IP8_13_11 [3] */ + FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C, + 0, 0, 0, 0, + /* IP8_10_9 [2] */ + FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0, + /* IP8_8_6 [3] */ + FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, + 0, 0, 0, 0, + /* IP8_5_3 [3] */ + FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, + 0, 0, 0, 0, + /* IP8_2_0 [3] */ + FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, + 0, FN_HSPI_TX1_A, FN_TX3_B, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, + 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP9_31 [1] */ + 0, 0, + /* IP9_30 [1] */ + 0, 0, + /* IP9_29_27 [3] */ + FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_ETH_RXD1, FN_FMIN_C, + 0, FN_RX2_D, + FN_SCL2_C, 0, + /* IP9_26_24 [3] */ + FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT, + FN_ETH_RXD0, FN_BPFCLK_C, + 0, FN_TX2_D, + FN_SDA2_C, 0, + /* IP9_23_21 [3] */ + FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C, + FN_IERX, FN_RX2_C, 0, 0, + /* IP9_20_18 [3] */ + FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0, + FN_IETX, FN_TX2_C, 0, 0, + /* IP9_17_15 [3] */ + FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK, + FN_SCK2_C, 0, 0, 0, + /* IP9_14_12 [3] */ + FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1, + 0, FN_PWM3, 0, 0, + /* IP9_11_9 [3] */ + FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, + 0, FN_PWM2, FN_TCLK1, 0, + /* IP9_8_6 [3] */ + FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, + 0, 0, 0, 0, + /* IP9_5_3 [3] */ + FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7, + 0, FN_HCTS1_B, 0, 0, + /* IP9_2_0 [3] */ + FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, + 0, FN_HRTS1_B, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, + 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) { + + /* IP10_31 [1] */ + 0, 0, + /* IP10_30 [1] */ + 0, 0, + /* IP10_29 [1] */ + 0, 0, + /* IP10_28 [1] */ + 0, 0, + /* IP10_27 [1] */ + 0, 0, + /* IP10_26 [1] */ + 0, 0, + /* IP10_25 [1] */ + 0, 0, + /* IP10_24_22 [3] */ + FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B, + FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0, + /* IP10_21_19 [3] */ + FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, + FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0, + /* IP10_18_16 [3] */ + FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1, + FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0, + /* IP10_15_13 [3] */ + FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, + FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0, + /* IP10_12_9 [4] */ + FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, + FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IP10_8_6 [3] */ + FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B, + FN_ETH_LINK, FN_CAN1_RX_A, 0, 0, + /* IP10_5_3 [3] */ + FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + FN_ATAWR1, FN_ETH_MDIO, + FN_SCL1_B, 0, + 0, 0, + /* IP10_2_0 [3] */ + FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_ATARD1, FN_ETH_MDC, + FN_SDA1_B, 0, + 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32, + 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2, + 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + + /* SEL 31 [1] */ + 0, 0, + /* SEL_30 (SCIF5) [1] */ + FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, + /* SEL_29_28 (SCIF4) [2] */ + FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, + FN_SEL_SCIF4_C, 0, + /* SEL_27_26 (SCIF3) [2] */ + FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, + FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, + /* SEL_25_23 (SCIF2) [3] */ + FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, + FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, + FN_SEL_SCIF2_E, 0, + 0, 0, + /* SEL_22_21 (SCIF1) [2] */ + FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, + FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, + /* SEL_20_19 (SCIF0) [2] */ + FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, + FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, + /* SEL_18 [1] */ + 0, 0, + /* SEL_17 (SSI2) [1] */ + FN_SEL_SSI2_A, FN_SEL_SSI2_B, + /* SEL_16 (SSI1) [1] */ + FN_SEL_SSI1_A, FN_SEL_SSI1_B, + /* SEL_15 (VI1) [1] */ + FN_SEL_VI1_A, FN_SEL_VI1_B, + /* SEL_14_13 (VI0) [2] */ + FN_SEL_VI0_A, FN_SEL_VI0_B, + FN_SEL_VI0_C, FN_SEL_VI0_D, + /* SEL_12 [1] */ + 0, 0, + /* SEL_11 (SD2) [1] */ + FN_SEL_SD2_A, FN_SEL_SD2_B, + /* SEL_10 (SD1) [1] */ + FN_SEL_SD1_A, FN_SEL_SD1_B, + /* SEL_9 (IRQ3) [1] */ + FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, + /* SEL_8_7 (IRQ2) [2] */ + FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, + FN_SEL_IRQ2_C, 0, + /* SEL_6 (IRQ1) [1] */ + FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, + /* SEL_5 [1] */ + 0, 0, + /* SEL_4 (DREQ2) [1] */ + FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, + /* SEL_3 (DREQ1) [1] */ + FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, + /* SEL_2 (DREQ0) [1] */ + FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, + /* SEL_1 (WAIT2) [1] */ + FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, + /* SEL_0 (WAIT1) [1] */ + FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, + } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32, + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) { + + /* SEL_31 [1] */ + 0, 0, + /* SEL_30 [1] */ + 0, 0, + /* SEL_29 [1] */ + 0, 0, + /* SEL_28 [1] */ + 0, 0, + /* SEL_27 (CAN1) [1] */ + FN_SEL_CAN1_A, FN_SEL_CAN1_B, + /* SEL_26 (CAN0) [1] */ + FN_SEL_CAN0_A, FN_SEL_CAN0_B, + /* SEL_25_24 (CANCLK) [2] */ + FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, + FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, + /* SEL_23 (HSCIF1) [1] */ + FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, + /* SEL_22 (HSCIF0) [1] */ + FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, + /* SEL_21 [1] */ + 0, 0, + /* SEL_20 [1] */ + 0, 0, + /* SEL_19 [1] */ + 0, 0, + /* SEL_18 [1] */ + 0, 0, + /* SEL_17 [1] */ + 0, 0, + /* SEL_16 [1] */ + 0, 0, + /* SEL_15 [1] */ + 0, 0, + /* SEL_14_13 (REMOCON) [2] */ + FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, + FN_SEL_REMOCON_C, 0, + /* SEL_12_11 (FM) [2] */ + FN_SEL_FM_A, FN_SEL_FM_B, + FN_SEL_FM_C, FN_SEL_FM_D, + /* SEL_10_9 (GPS) [2] */ + FN_SEL_GPS_A, FN_SEL_GPS_B, + FN_SEL_GPS_C, 0, + /* SEL_8 (TSIF0) [1] */ + FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, + /* SEL_7 (HSPI2) [1] */ + FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, + /* SEL_6 (HSPI1) [1] */ + FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, + /* SEL_5 (HSPI0) [1] */ + FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, + /* SEL_4_3 (I2C3) [2] */ + FN_SEL_I2C3_A, FN_SEL_I2C3_B, + FN_SEL_I2C3_C, 0, + /* SEL_2_1 (I2C2) [2] */ + FN_SEL_I2C2_A, FN_SEL_I2C2_B, + FN_SEL_I2C2_C, 0, + /* SEL_0 (I2C1) [1] */ + FN_SEL_I2C1_A, FN_SEL_I2C1_B, + } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7778_pinmux_info = { + .name = "r8a7778_pfc", + + .unlock_reg = 0xfffc0000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 13feaa0c0eb..f5c01e1e261 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1,8 +1,9 @@ /* * r8a7779 processor support - PFC hardware block * - * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011, 2013 Renesas Solutions Corp. * Copyright (C) 2011 Magnus Damm + * Copyright (C) 2013 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,61 +20,25 @@ */ #include <linux/kernel.h> -#include <mach/r8a7779.h> +#include <linux/platform_data/gpio-rcar.h> #include "sh_pfc.h" -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define CPU_32_PORT6(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ - PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ - PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ - PORT_1(fn, pfx##8, sfx) - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT(fn, pfx##_0_, sfx), \ - CPU_32_PORT(fn, pfx##_1_, sfx), \ - CPU_32_PORT(fn, pfx##_2_, sfx), \ - CPU_32_PORT(fn, pfx##_3_, sfx), \ - CPU_32_PORT(fn, pfx##_4_, sfx), \ - CPU_32_PORT(fn, pfx##_5_, sfx), \ - CPU_32_PORT6(fn, pfx##_6_, sfx) - -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) - -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA - -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) - -#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ - FN_##ipsr, FN_##fn) +#define PORT_GP_9(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx), \ + PORT_GP_9(6, fn, sfx) enum { PINMUX_RESERVED = 0, @@ -82,14 +47,6 @@ enum { GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */ PINMUX_DATA_END, - PINMUX_INPUT_BEGIN, - GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */ - PINMUX_INPUT_END, - - PINMUX_OUTPUT_BEGIN, - GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */ - PINMUX_OUTPUT_END, - PINMUX_FUNCTION_BEGIN, GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */ @@ -371,7 +328,7 @@ enum { FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0, - FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, + FN_TS_SCK1, FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, @@ -447,7 +404,8 @@ enum { A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, - USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, + USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK, + SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, SCIF_CLK_MARK, TCLK0_C_MARK, EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, @@ -632,7 +590,7 @@ enum { HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK, MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK, SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK, - VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK, + VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK, DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK, VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK, DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK, @@ -649,7 +607,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ PINMUX_DATA(AVS1_MARK, FN_AVS1), @@ -658,6 +616,9 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(A18_MARK, FN_A18), PINMUX_DATA(A19_MARK, FN_A19), + PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0), + PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1), + PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2), PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP0_2_0, PWM1), @@ -1399,7 +1360,6 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), PINMUX_IPSR_DATA(IP11_26_24, VI1_G0), PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0), - PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1), PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1), PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), PINMUX_IPSR_DATA(IP11_26_24, TX2), @@ -1450,280 +1410,1611 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18), - GPIO_FN(A19), +}; - /* IPSR0 */ - GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), - GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2), - GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), - GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3), - GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D), - GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D), - GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D), - GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), - GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD), - GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2), - GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5), - GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B), - GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT), - GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0), - GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2), - GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0), - GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C), +/* - DU0 -------------------------------------------------------------------- */ +static const unsigned int du0_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), + RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 3), +}; +static const unsigned int du0_rgb666_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, + DU0_DR3_MARK, DU0_DR2_MARK, + DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, + DU0_DG3_MARK, DU0_DG2_MARK, + DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, + DU0_DB3_MARK, DU0_DB2_MARK, +}; +static const unsigned int du0_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2), + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(5, 31), + RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26), + RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), + RCAR_GP_PIN(6, 3), RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27), +}; +static const unsigned int du0_rgb888_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, + DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK, + DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, + DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK, + DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, + DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, +}; +static const unsigned int du0_clk_in_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(0, 29), +}; +static const unsigned int du0_clk_in_mux[] = { + DU0_DOTCLKIN_MARK, +}; +static const unsigned int du0_clk_out_0_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int du0_clk_out_0_mux[] = { + DU0_DOTCLKOUT0_MARK, +}; +static const unsigned int du0_clk_out_1_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(0, 30), +}; +static const unsigned int du0_clk_out_1_mux[] = { + DU0_DOTCLKOUT1_MARK, +}; +static const unsigned int du0_sync_0_pins[] = { + /* VSYNC, HSYNC, DISP */ + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31), +}; +static const unsigned int du0_sync_0_mux[] = { + DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK +}; +static const unsigned int du0_sync_1_pins[] = { + /* VSYNC, HSYNC, DISP */ + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0), +}; +static const unsigned int du0_sync_1_mux[] = { + DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, + DU0_DISP_MARK +}; +static const unsigned int du0_oddf_pins[] = { + /* ODDF */ + RCAR_GP_PIN(0, 31), +}; +static const unsigned int du0_oddf_mux[] = { + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK +}; +static const unsigned int du0_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int du0_cde_mux[] = { + DU0_CDE_MARK +}; +/* - DU1 -------------------------------------------------------------------- */ +static const unsigned int du1_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20), +}; +static const unsigned int du1_rgb666_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, +}; +static const unsigned int du1_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 17), + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), +}; +static const unsigned int du1_rgb888_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, +}; +static const unsigned int du1_clk_in_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int du1_clk_in_mux[] = { + DU1_DOTCLKIN_MARK, +}; +static const unsigned int du1_clk_out_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int du1_clk_out_mux[] = { + DU1_DOTCLKOUT_MARK, +}; +static const unsigned int du1_sync_0_pins[] = { + /* VSYNC, HSYNC, DISP */ + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30), +}; +static const unsigned int du1_sync_0_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK +}; +static const unsigned int du1_sync_1_pins[] = { + /* VSYNC, HSYNC, DISP */ + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31), +}; +static const unsigned int du1_sync_1_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, + DU1_DISP_MARK +}; +static const unsigned int du1_oddf_pins[] = { + /* ODDF */ + RCAR_GP_PIN(1, 30), +}; +static const unsigned int du1_oddf_mux[] = { + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK +}; +static const unsigned int du1_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int du1_cde_mux[] = { + DU1_CDE_MARK +}; +/* - Ether ------------------------------------------------------------------ */ +static const unsigned int ether_rmii_pins[] = { + /* + * ETH_TXD0, ETH_TXD1, ETH_TX_EN, ETH_REFCLK, + * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER, + * ETH_MDIO, ETH_MDC + */ + RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17), + RCAR_GP_PIN(2, 19), + RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28), +}; +static const unsigned int ether_rmii_mux[] = { + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, + ETH_MDIO_MARK, ETH_MDC_MARK, +}; +static const unsigned int ether_link_pins[] = { + /* ETH_LINK */ + RCAR_GP_PIN(2, 24), +}; +static const unsigned int ether_link_mux[] = { + ETH_LINK_MARK, +}; +static const unsigned int ether_magic_pins[] = { + /* ETH_MAGIC */ + RCAR_GP_PIN(2, 25), +}; +static const unsigned int ether_magic_mux[] = { + ETH_MAGIC_MARK, +}; +/* - HSPI0 ------------------------------------------------------------------ */ +static const unsigned int hspi0_pins[] = { + /* CLK, CS, RX, TX */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25), + RCAR_GP_PIN(4, 24), +}; +static const unsigned int hspi0_mux[] = { + HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK, +}; +/* - HSPI1 ------------------------------------------------------------------ */ +static const unsigned int hspi1_pins[] = { + /* CLK, CS, RX, TX */ + RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0), + RCAR_GP_PIN(1, 30), +}; +static const unsigned int hspi1_mux[] = { + HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK, +}; +static const unsigned int hspi1_b_pins[] = { + /* CLK, CS, RX, TX */ + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29), + RCAR_GP_PIN(2, 28), +}; +static const unsigned int hspi1_b_mux[] = { + HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK, +}; +static const unsigned int hspi1_c_pins[] = { + /* CLK, CS, RX, TX */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 15), +}; +static const unsigned int hspi1_c_mux[] = { + HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK, +}; +static const unsigned int hspi1_d_pins[] = { + /* CLK, CS, RX, TX */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(3, 7), +}; +static const unsigned int hspi1_d_mux[] = { + HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK, +}; +/* - HSPI2 ------------------------------------------------------------------ */ +static const unsigned int hspi2_pins[] = { + /* CLK, CS, RX, TX */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 14), +}; +static const unsigned int hspi2_mux[] = { + HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK, +}; +static const unsigned int hspi2_b_pins[] = { + /* CLK, CS, RX, TX */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8), + RCAR_GP_PIN(0, 6), +}; +static const unsigned int hspi2_b_mux[] = { + HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, +}; +/* - I2C1 ------------------------------------------------------------------ */ +static const unsigned int i2c1_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), +}; +static const unsigned int i2c1_mux[] = { + SCL1_MARK, SDA1_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), +}; +static const unsigned int i2c1_b_mux[] = { + SCL1_B_MARK, SDA1_B_MARK, +}; +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; +static const unsigned int i2c1_c_mux[] = { + SCL1_C_MARK, SDA1_C_MARK, +}; +static const unsigned int i2c1_d_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), +}; +static const unsigned int i2c1_d_mux[] = { + SCL1_D_MARK, SDA1_D_MARK, +}; +/* - I2C2 ------------------------------------------------------------------ */ +static const unsigned int i2c2_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26), +}; +static const unsigned int i2c2_mux[] = { + SCL2_MARK, SDA2_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +}; +static const unsigned int i2c2_b_mux[] = { + SCL2_B_MARK, SDA2_B_MARK, +}; +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30), +}; +static const unsigned int i2c2_c_mux[] = { + SCL2_C_MARK, SDA2_C_MARK, +}; +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), +}; +static const unsigned int i2c2_d_mux[] = { + SCL2_D_MARK, SDA2_D_MARK, +}; +/* - I2C3 ------------------------------------------------------------------ */ +static const unsigned int i2c3_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30), +}; +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; +static const unsigned int i2c3_b_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30), +}; +static const unsigned int i2c3_b_mux[] = { + SCL3_B_MARK, SDA3_B_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +static const unsigned int intc_irq0_pins[] = { + /* IRQ */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_irq0_b_pins[] = { + /* IRQ */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int intc_irq0_b_mux[] = { + IRQ0_B_MARK, +}; +static const unsigned int intc_irq1_pins[] = { + /* IRQ */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_irq1_b_pins[] = { + /* IRQ */ + RCAR_GP_PIN(4, 14), +}; +static const unsigned int intc_irq1_b_mux[] = { + IRQ1_B_MARK, +}; +static const unsigned int intc_irq2_pins[] = { + /* IRQ */ + RCAR_GP_PIN(2, 24), +}; +static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_irq2_b_pins[] = { + /* IRQ */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int intc_irq2_b_mux[] = { + IRQ2_B_MARK, +}; +static const unsigned int intc_irq3_pins[] = { + /* IRQ */ + RCAR_GP_PIN(2, 25), +}; +static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_irq3_b_pins[] = { + /* IRQ */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int intc_irq3_b_mux[] = { + IRQ3_B_MARK, +}; +/* - LSBC ------------------------------------------------------------------- */ +static const unsigned int lbsc_cs0_pins[] = { + /* CS */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int lbsc_cs0_mux[] = { + CS0_MARK, +}; +static const unsigned int lbsc_cs1_pins[] = { + /* CS */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int lbsc_cs1_mux[] = { + CS1_A26_MARK, +}; +static const unsigned int lbsc_ex_cs0_pins[] = { + /* CS */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int lbsc_ex_cs0_mux[] = { + EX_CS0_MARK, +}; +static const unsigned int lbsc_ex_cs1_pins[] = { + /* CS */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int lbsc_ex_cs1_mux[] = { + EX_CS1_MARK, +}; +static const unsigned int lbsc_ex_cs2_pins[] = { + /* CS */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int lbsc_ex_cs2_mux[] = { + EX_CS2_MARK, +}; +static const unsigned int lbsc_ex_cs3_pins[] = { + /* CS */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int lbsc_ex_cs3_mux[] = { + EX_CS3_MARK, +}; +static const unsigned int lbsc_ex_cs4_pins[] = { + /* CS */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int lbsc_ex_cs4_mux[] = { + EX_CS4_MARK, +}; +static const unsigned int lbsc_ex_cs5_pins[] = { + /* CS */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int lbsc_ex_cs5_mux[] = { + EX_CS5_MARK, +}; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc0_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int mmc0_data1_mux[] = { + MMC0_D0_MARK, +}; +static const unsigned int mmc0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 2), +}; +static const unsigned int mmc0_data4_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, +}; +static const unsigned int mmc0_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), +}; +static const unsigned int mmc0_data8_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, + MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, +}; +static const unsigned int mmc0_ctrl_pins[] = { + /* CMD, CLK */ + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), +}; +static const unsigned int mmc0_ctrl_mux[] = { + MMC0_CMD_MARK, MMC0_CLK_MARK, +}; +static const unsigned int mmc1_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(2, 8), +}; +static const unsigned int mmc1_data1_mux[] = { + MMC1_D0_MARK, +}; +static const unsigned int mmc1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), +}; +static const unsigned int mmc1_data4_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, +}; +static const unsigned int mmc1_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), +}; +static const unsigned int mmc1_data8_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, + MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, +}; +static const unsigned int mmc1_ctrl_pins[] = { + /* CMD, CLK */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1), +}; +static const unsigned int mmc1_ctrl_mux[] = { + MMC1_CMD_MARK, MMC1_CLK_MARK, +}; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 28), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_TANS_MARK, CTS0_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), +}; +static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, +}; +static const unsigned int scif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int scif0_clk_b_mux[] = { + SCK0_B_MARK, +}; +static const unsigned int scif0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), +}; +static const unsigned int scif0_ctrl_b_mux[] = { + RTS0_B_TANS_B_MARK, CTS0_B_MARK, +}; +static const unsigned int scif0_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), +}; +static const unsigned int scif0_data_c_mux[] = { + RX0_C_MARK, TX0_C_MARK, +}; +static const unsigned int scif0_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int scif0_clk_c_mux[] = { + SCK0_C_MARK, +}; +static const unsigned int scif0_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), +}; +static const unsigned int scif0_ctrl_c_mux[] = { + RTS0_C_TANS_C_MARK, CTS0_C_MARK, +}; +static const unsigned int scif0_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), +}; +static const unsigned int scif0_data_d_mux[] = { + RX0_D_MARK, TX0_D_MARK, +}; +static const unsigned int scif0_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int scif0_clk_d_mux[] = { + SCK0_D_MARK, +}; +static const unsigned int scif0_ctrl_d_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3), +}; +static const unsigned int scif0_ctrl_d_mux[] = { + RTS0_D_TANS_D_MARK, CTS0_D_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), +}; +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_TANS_MARK, CTS1_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int scif1_clk_b_mux[] = { + SCK1_B_MARK, +}; +static const unsigned int scif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), +}; +static const unsigned int scif1_ctrl_b_mux[] = { + RTS1_B_TANS_B_MARK, CTS1_B_MARK, +}; +static const unsigned int scif1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), +}; +static const unsigned int scif1_data_c_mux[] = { + RX1_C_MARK, TX1_C_MARK, +}; +static const unsigned int scif1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 22), +}; +static const unsigned int scif1_clk_c_mux[] = { + SCK1_C_MARK, +}; +static const unsigned int scif1_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), +}; +static const unsigned int scif1_ctrl_c_mux[] = { + RTS1_C_TANS_C_MARK, CTS1_C_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9), +}; +static const unsigned int scif2_data_mux[] = { + RX2_MARK, TX2_MARK, +}; +static const unsigned int scif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 11), +}; +static const unsigned int scif2_clk_mux[] = { + SCK2_MARK, +}; +static const unsigned int scif2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23), +}; +static const unsigned int scif2_data_b_mux[] = { + RX2_B_MARK, TX2_B_MARK, +}; +static const unsigned int scif2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 22), +}; +static const unsigned int scif2_clk_b_mux[] = { + SCK2_B_MARK, +}; +static const unsigned int scif2_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31), +}; +static const unsigned int scif2_data_c_mux[] = { + RX2_C_MARK, TX2_C_MARK, +}; +static const unsigned int scif2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int scif2_clk_c_mux[] = { + SCK2_C_MARK, +}; +static const unsigned int scif2_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), +}; +static const unsigned int scif2_data_d_mux[] = { + RX2_D_MARK, TX2_D_MARK, +}; +static const unsigned int scif2_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 31), +}; +static const unsigned int scif2_clk_d_mux[] = { + SCK2_D_MARK, +}; +static const unsigned int scif2_data_e_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), +}; +static const unsigned int scif2_data_e_mux[] = { + RX2_E_MARK, TX2_E_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), +}; +static const unsigned int scif3_data_mux[] = { + RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 7), +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; - /* IPSR1 */ - GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6), - GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7), - GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE), - GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD), - GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B), - GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B), - GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0), - GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), - GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B), - GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1), - GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), - GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9), - GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG), - GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4), - GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA), - GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2), - GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26), - GPIO_FN(CC5_STATE34), +static const unsigned int scif3_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), +}; +static const unsigned int scif3_data_b_mux[] = { + RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK, +}; +static const unsigned int scif3_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12), +}; +static const unsigned int scif3_data_c_mux[] = { + RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK, +}; +static const unsigned int scif3_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29), +}; +static const unsigned int scif3_data_d_mux[] = { + RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK, +}; +static const unsigned int scif3_data_e_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), +}; +static const unsigned int scif3_data_e_mux[] = { + RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK, +}; +static const unsigned int scif3_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int scif3_clk_e_mux[] = { + SCK3_E_MARK, +}; +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26), +}; +static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, +}; +static const unsigned int scif4_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 25), +}; +static const unsigned int scif4_clk_mux[] = { + SCK4_MARK, +}; +static const unsigned int scif4_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), +}; +static const unsigned int scif4_data_b_mux[] = { + RX4_B_MARK, TX4_B_MARK, +}; +static const unsigned int scif4_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 16), +}; +static const unsigned int scif4_clk_b_mux[] = { + SCK4_B_MARK, +}; +static const unsigned int scif4_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21), +}; +static const unsigned int scif4_data_c_mux[] = { + RX4_C_MARK, TX4_C_MARK, +}; +static const unsigned int scif4_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), +}; +static const unsigned int scif4_data_d_mux[] = { + RX4_D_MARK, TX4_D_MARK, +}; +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), +}; +static const unsigned int scif5_data_mux[] = { + RX5_MARK, TX5_MARK, +}; +static const unsigned int scif5_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int scif5_clk_mux[] = { + SCK5_MARK, +}; +static const unsigned int scif5_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), +}; +static const unsigned int scif5_data_b_mux[] = { + RX5_B_MARK, TX5_B_MARK, +}; +static const unsigned int scif5_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int scif5_clk_b_mux[] = { + SCK5_B_MARK, +}; +static const unsigned int scif5_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), +}; +static const unsigned int scif5_data_c_mux[] = { + RX5_C_MARK, TX5_C_MARK, +}; +static const unsigned int scif5_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 28), +}; +static const unsigned int scif5_clk_c_mux[] = { + SCK5_C_MARK, +}; +static const unsigned int scif5_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), +}; +static const unsigned int scif5_data_d_mux[] = { + RX5_D_MARK, TX5_D_MARK, +}; +static const unsigned int scif5_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int scif5_clk_d_mux[] = { + SCK5_D_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 21), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), + RCAR_GP_PIN(3, 24), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CMD, CLK */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CMD_MARK, SD0_CLK_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 19), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 20), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 2), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CMD, CLK */ + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CMD_MARK, SD1_CLK_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CMD, CLK */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CMD_MARK, SD2_CLK_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 21), +}; +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, +}; +static const unsigned int sdhi3_ctrl_pins[] = { + /* CMD, CLK */ + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), +}; +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CMD_MARK, SD3_CLK_MARK, +}; +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(1, 30), +}; +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + /* PENC */ + RCAR_GP_PIN(4, 26), +}; +static const unsigned int usb0_mux[] = { + USB_PENC0_MARK, +}; +static const unsigned int usb0_ovc_pins[] = { + /* USB_OVC */ + RCAR_GP_PIN(4, 22), +}; +static const unsigned int usb0_ovc_mux[] = { + USB_OVC0_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_pins[] = { + /* PENC */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int usb1_mux[] = { + USB_PENC1_MARK, +}; +static const unsigned int usb1_ovc_pins[] = { + /* USB_OVC */ + RCAR_GP_PIN(4, 24), +}; +static const unsigned int usb1_ovc_mux[] = { + USB_OVC1_MARK, +}; +/* - USB2 ------------------------------------------------------------------- */ +static const unsigned int usb2_pins[] = { + /* PENC */ + RCAR_GP_PIN(4, 28), +}; +static const unsigned int usb2_mux[] = { + USB_PENC2_MARK, +}; +static const unsigned int usb2_ovc_pins[] = { + /* USB_OVC */ + RCAR_GP_PIN(3, 29), +}; +static const unsigned int usb2_ovc_mux[] = { + USB_OVC2_MARK, +}; +/* - VIN0 ------------------------------------------------------------------- */ +static const unsigned int vin0_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), +}; +static const unsigned int vin0_data8_mux[] = { + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, + VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_MARK, VI0_VSYNC_MARK, +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const unsigned int vin1_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), +}; +static const unsigned int vin1_data8_mux[] = { + VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, + VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, + VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 30), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; +static const unsigned int vin1_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0), +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_MARK, VI1_VSYNC_MARK, +}; +/* - VIN2 ------------------------------------------------------------------- */ +static const unsigned int vin2_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), + RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0), +}; +static const unsigned int vin2_data8_mux[] = { + VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK, + VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, +}; +static const unsigned int vin2_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 30), +}; +static const unsigned int vin2_clk_mux[] = { + VI2_CLK_MARK, +}; +static const unsigned int vin2_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), +}; +static const unsigned int vin2_sync_mux[] = { + VI2_HSYNC_MARK, VI2_VSYNC_MARK, +}; +/* - VIN3 ------------------------------------------------------------------- */ +static const unsigned int vin3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), +}; +static const unsigned int vin3_data8_mux[] = { + VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK, + VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK, + VI3_DATA6_MARK, VI3_DATA7_MARK, +}; +static const unsigned int vin3_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 31), +}; +static const unsigned int vin3_clk_mux[] = { + VI3_CLK_MARK, +}; +static const unsigned int vin3_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), +}; +static const unsigned int vin3_sync_mux[] = { + VI3_HSYNC_MARK, VI3_VSYNC_MARK, +}; - /* IPSR2 */ - GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C), - GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11), - GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35), - GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5), - GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO), - GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16), - GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0), - GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C), - GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B), - GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS), - GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1), - GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25), - GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0), - GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0), - GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0), - GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C), - GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3), - GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5), - GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7), - GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2), - GPIO_FN(AUDATA2), +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(du0_rgb666), + SH_PFC_PIN_GROUP(du0_rgb888), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du0_clk_out_0), + SH_PFC_PIN_GROUP(du0_clk_out_1), + SH_PFC_PIN_GROUP(du0_sync_0), + SH_PFC_PIN_GROUP(du0_sync_1), + SH_PFC_PIN_GROUP(du0_oddf), + SH_PFC_PIN_GROUP(du0_cde), + SH_PFC_PIN_GROUP(du1_rgb666), + SH_PFC_PIN_GROUP(du1_rgb888), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du1_clk_out), + SH_PFC_PIN_GROUP(du1_sync_0), + SH_PFC_PIN_GROUP(du1_sync_1), + SH_PFC_PIN_GROUP(du1_oddf), + SH_PFC_PIN_GROUP(du1_cde), + SH_PFC_PIN_GROUP(ether_rmii), + SH_PFC_PIN_GROUP(ether_link), + SH_PFC_PIN_GROUP(ether_magic), + SH_PFC_PIN_GROUP(hspi0), + SH_PFC_PIN_GROUP(hspi1), + SH_PFC_PIN_GROUP(hspi1_b), + SH_PFC_PIN_GROUP(hspi1_c), + SH_PFC_PIN_GROUP(hspi1_d), + SH_PFC_PIN_GROUP(hspi2), + SH_PFC_PIN_GROUP(hspi2_b), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq0_b), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq1_b), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq2_b), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(intc_irq3_b), + SH_PFC_PIN_GROUP(lbsc_cs0), + SH_PFC_PIN_GROUP(lbsc_cs1), + SH_PFC_PIN_GROUP(lbsc_ex_cs0), + SH_PFC_PIN_GROUP(lbsc_ex_cs1), + SH_PFC_PIN_GROUP(lbsc_ex_cs2), + SH_PFC_PIN_GROUP(lbsc_ex_cs3), + SH_PFC_PIN_GROUP(lbsc_ex_cs4), + SH_PFC_PIN_GROUP(lbsc_ex_cs5), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_clk_b), + SH_PFC_PIN_GROUP(scif0_ctrl_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_clk_c), + SH_PFC_PIN_GROUP(scif0_ctrl_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif0_clk_d), + SH_PFC_PIN_GROUP(scif0_ctrl_d), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_ctrl_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_clk_c), + SH_PFC_PIN_GROUP(scif1_ctrl_c), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_clk_c), + SH_PFC_PIN_GROUP(scif2_data_d), + SH_PFC_PIN_GROUP(scif2_clk_d), + SH_PFC_PIN_GROUP(scif2_data_e), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif3_data_d), + SH_PFC_PIN_GROUP(scif3_data_e), + SH_PFC_PIN_GROUP(scif3_clk_e), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_clk), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_clk_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_data_d), + SH_PFC_PIN_GROUP(scif5_data), + SH_PFC_PIN_GROUP(scif5_clk), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_clk_b), + SH_PFC_PIN_GROUP(scif5_data_c), + SH_PFC_PIN_GROUP(scif5_clk_c), + SH_PFC_PIN_GROUP(scif5_data_d), + SH_PFC_PIN_GROUP(scif5_clk_d), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb1_ovc), + SH_PFC_PIN_GROUP(usb2), + SH_PFC_PIN_GROUP(usb2_ovc), + SH_PFC_PIN_GROUP(vin0_data8), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_clk), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin2_data8), + SH_PFC_PIN_GROUP(vin2_clk), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin3_data8), + SH_PFC_PIN_GROUP(vin3_clk), + SH_PFC_PIN_GROUP(vin3_sync), +}; - /* IPSR3 */ - GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2), - GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10), - GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4), - GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13), - GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7), - GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16), - GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4), - GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1), - GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C), - GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3), - GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20), - GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6), - GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23), - GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D), - GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK), - GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D), - GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B), - GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS), - GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE), - GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE), - GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON), +static const char * const du0_groups[] = { + "du0_rgb666", + "du0_rgb888", + "du0_clk_in", + "du0_clk_out_0", + "du0_clk_out_1", + "du0_sync_0", + "du0_sync_1", + "du0_oddf", + "du0_cde", +}; - /* IPSR4 */ - GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C), - GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C), - GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B), - GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), - GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK), - GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1), - GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E), - GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0), - GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2), - GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4), - GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0), - GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2), - GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1), - GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3), - GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2), - GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4), - GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6), - GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0), - GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0), - GPIO_FN(TX5), GPIO_FN(SCK0_D), +static const char * const du1_groups[] = { + "du1_rgb666", + "du1_rgb888", + "du1_clk_in", + "du1_clk_out", + "du1_sync_0", + "du1_sync_1", + "du1_oddf", + "du1_cde", +}; - /* IPSR5 */ - GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), - GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D), - GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5), - GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7), - GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D), - GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1), - GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD), - GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC), - GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC), - GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), - GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD), - GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), - GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN), - GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6), - GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1), - GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), - GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B), - GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD), - GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D), - GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), - GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2), - GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0), +static const char * const ether_groups[] = { + "ether_rmii", + "ether_link", + "ether_magic", +}; - /* IPSR6 */ - GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1), - GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2), - GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5), - GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6), - GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34), - GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX), - GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7), - GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C), - GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8), - GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B), - GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9), - GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK), - GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D), - GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11), - GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA), - GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6), - GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B), +static const char * const hspi0_groups[] = { + "hspi0", +}; - /* IPSR7 */ - GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B), - GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK), - GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13), - GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C), - GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B), - GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7), - GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C), - GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), - GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK), - GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11), - GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1), - GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1), - GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1), - GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1), - GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2), - GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2), - GPIO_FN(CTS1_B), +static const char * const hspi1_groups[] = { + "hspi1", + "hspi1_b", + "hspi1_c", + "hspi1_d", +}; - /* IPSR8 */ - GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), - GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20), - GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0), - GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI), - GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21), - GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0), - GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), - GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22), - GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0), - GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7), - GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31), - GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE), - GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA), - GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB), - GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC), - GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B), - GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C), - GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B), - GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B), - GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C), +static const char * const hspi2_groups[] = { + "hspi2", + "hspi2_b", +}; - /* IPSR9 */ - GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO), - GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM), - GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3), - GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2), - GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6), - GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7), - GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0), - GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2), - GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1), - GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1), - GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0), - GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7), - GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4), - GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6), - GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B), - GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0), - GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7), - GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9), +static const char * const i2c1_groups[] = { + "i2c1", + "i2c1_b", + "i2c1_c", + "i2c1_d", +}; - /* IPSR10 */ - GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C), - GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C), - GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B), - GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C), - GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2), - GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC), - GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13), - GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B), - GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK), - GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0), - GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15), - GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC), - GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK), - GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7), - GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B), - GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN), - GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC), - GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C), - GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C), - GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C), - GPIO_FN(SPV_TRST), GPIO_FN(SCL3), +static const char * const i2c2_groups[] = { + "i2c2", + "i2c2_b", + "i2c2_c", + "i2c2_d", +}; - /* IPSR11 */ - GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST), - GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1), - GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS), - GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2), - GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B), - GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN), - GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4), - GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST), - GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5), - GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK), - GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6), - GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS), - GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP), - GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D), - GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1), - GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO), - GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1), - GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2), - GPIO_FN(HRTS0_B), +static const char * const i2c3_groups[] = { + "i2c3", + "i2c3_b", +}; - /* IPSR12 */ - GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1), - GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3), - GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1), - GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4), - GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B), - GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5), - GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B), - GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB), - GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7), - GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq0_b", + "intc_irq1", + "intc_irq1_b", + "intc_irq2", + "intc_irq2_b", + "intc_irq3", + "intc_irq3_b", +}; + +static const char * const lbsc_groups[] = { + "lbsc_cs0", + "lbsc_cs1", + "lbsc_ex_cs0", + "lbsc_ex_cs1", + "lbsc_ex_cs2", + "lbsc_ex_cs3", + "lbsc_ex_cs4", + "lbsc_ex_cs5", +}; + +static const char * const mmc0_groups[] = { + "mmc0_data1", + "mmc0_data4", + "mmc0_data8", + "mmc0_ctrl", +}; + +static const char * const mmc1_groups[] = { + "mmc1_data1", + "mmc1_data4", + "mmc1_data8", + "mmc1_ctrl", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", + "scif0_data_b", + "scif0_clk_b", + "scif0_ctrl_b", + "scif0_data_c", + "scif0_clk_c", + "scif0_ctrl_c", + "scif0_data_d", + "scif0_clk_d", + "scif0_ctrl_d", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_ctrl", + "scif1_data_b", + "scif1_clk_b", + "scif1_ctrl_b", + "scif1_data_c", + "scif1_clk_c", + "scif1_ctrl_c", +}; + +static const char * const scif2_groups[] = { + "scif2_data", + "scif2_clk", + "scif2_data_b", + "scif2_clk_b", + "scif2_data_c", + "scif2_clk_c", + "scif2_data_d", + "scif2_clk_d", + "scif2_data_e", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_data_b", + "scif3_data_c", + "scif3_data_d", + "scif3_data_e", + "scif3_clk_e", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_clk", + "scif4_data_b", + "scif4_clk_b", + "scif4_data_c", + "scif4_data_d", +}; + +static const char * const scif5_groups[] = { + "scif5_data", + "scif5_clk", + "scif5_data_b", + "scif5_clk_b", + "scif5_data_c", + "scif5_clk_c", + "scif5_data_d", + "scif5_clk_d", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", +}; + +static const char * const usb0_groups[] = { + "usb0", + "usb0_ovc", +}; + +static const char * const usb1_groups[] = { + "usb1", + "usb1_ovc", +}; + +static const char * const usb2_groups[] = { + "usb2", + "usb2_ovc", +}; + +static const char * const vin0_groups[] = { + "vin0_data8", + "vin0_clk", + "vin0_sync", +}; + +static const char * const vin1_groups[] = { + "vin1_data8", + "vin1_clk", + "vin1_sync", +}; + +static const char * const vin2_groups[] = { + "vin2_data8", + "vin2_clk", + "vin2_sync", +}; + +static const char * const vin3_groups[] = { + "vin3_data8", + "vin3_clk", + "vin3_sync", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(ether), + SH_PFC_FUNCTION(hspi0), + SH_PFC_FUNCTION(hspi1), + SH_PFC_FUNCTION(hspi2), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lbsc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { GP_0_31_FN, FN_IP3_31_29, GP_0_30_FN, FN_IP3_26_24, @@ -2412,7 +3703,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0, /* IP11_26_24 [3] */ - FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1, + FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, /* IP11_23_21 [3] */ FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, @@ -2525,7 +3816,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SCIF [2] */ FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, /* SEL_CANCLK [2] */ - FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0, /* SEL_CAN0 [1] */ FN_SEL_CAN0_0, FN_SEL_CAN0_1, /* SEL_HSCIF1 [1] */ @@ -2558,66 +3849,24 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_I2C1 [2] */ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 } }, - { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } }, - { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } }, - { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } }, - { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } }, - { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } }, - { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } }, - { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_6_8_IN, GP_6_8_OUT, - GP_6_7_IN, GP_6_7_OUT, - GP_6_6_IN, GP_6_6_OUT, - GP_6_5_IN, GP_6_5_OUT, - GP_6_4_IN, GP_6_4_OUT, - GP_6_3_IN, GP_6_3_OUT, - GP_6_2_IN, GP_6_2_OUT, - GP_6_1_IN, GP_6_1_OUT, - GP_6_0_IN, GP_6_0_OUT, } - }, - { }, -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } }, - { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } }, - { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } }, - { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } }, - { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } }, - { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } }, - { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA, - GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA, - GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA } - }, { }, }; -struct sh_pfc_soc_info r8a7779_pinmux_info = { +const struct sh_pfc_soc_info r8a7779_pinmux_info = { .name = "r8a7779_pfc", .unlock_reg = 0xfffc0000, /* PMMR */ - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_SCK4_B, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, .gpio_data = pinmux_data, .gpio_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c new file mode 100644 index 00000000000..9a179c94b4d --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -0,0 +1,5502 @@ +/* + * R8A7790 processor support + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Magnus Damm + * Copyright (C) 2012 Renesas Solutions Corp. + * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kernel.h> +#include <linux/platform_data/gpio-rcar.h> + +#include "core.h" +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, + FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, + FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, + FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, + FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, + FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, + FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, + FN_IP3_14_12, FN_IP3_17_15, + + /* GPSR1 */ + FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, + FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, + FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, + FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, + FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, + FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, + + /* GPSR2 */ + FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, + FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, + FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, + FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, + FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, + FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, + FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, + + /* GPSR3 */ + FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, + FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, + FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, + FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, + FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, + FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, + FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, + + /* GPSR4 */ + FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, + FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, + FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, + FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, + FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, + FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, + FN_IP14_15_12, FN_IP14_18_16, + + /* GPSR5 */ + FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, + FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, + FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, + FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, + FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, + FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, + FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, + + /* IPSR0 */ + FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, + FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, + FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, + FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, + FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, + FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, + FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, + FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, + FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, + FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, + FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1, + FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + + /* IPSR1 */ + FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, + FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, + FN_SCIFA1_TXD_C, FN_AVB_TXD2, + FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, + FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, + FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, + FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, + FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, + FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, + FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, + FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, + FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, + FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, + FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, + FN_A0, FN_PWM3, FN_A1, FN_PWM4, + + /* IPSR2 */ + FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, + FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, + FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, + FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, + FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, + FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, + FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, + FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, + FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, + FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, + FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, + + /* IPSR3 */ + FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, + FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, + FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, + FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, + FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, + FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, + FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, + FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, + FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, + FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, + FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, + FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, + FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, + + /* IPSR4 */ + FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, + FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, + FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, + FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, + FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, + FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, + FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, + FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, + FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, + FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, + FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, + FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, + FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, + FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, + FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, + + /* IPSR5 */ + FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, + FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, + FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, + FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, + FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, + FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, + FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, + FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, + FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, + FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, + FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, + FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, + FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, + FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, + FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, + FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, + FN_SSI_WS78_B, + + /* IPSR6 */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, + FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, + FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, + FN_I2C2_SCL_E, FN_ETH_RX_ER, + FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, + FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, + FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, + FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, + FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, + FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, + FN_ETH_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, + + /* IPSR7 */ + FN_ETH_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, + FN_HTX0_F, FN_BPFCLK_G, + FN_ETH_TX_EN, FN_SIM0_CLK_C, + FN_HRTS0_N_F, FN_ETH_MAGIC, + FN_SIM0_RST_C, FN_ETH_TXD0, + FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, + FN_ETH_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, + FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, + FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, + FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, + FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1, + FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, + FN_ATACS00_N, FN_AVB_RXD1, + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + + /* IPSR8 */ + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, + FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, + FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, + FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, + FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, + FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, + FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, + FN_VI1_CLK, FN_AVB_RX_DV, + FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, + FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, + FN_SCIFA1_RXD_D, FN_AVB_MDC, + FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, + FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, + FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, + FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, + FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, + FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, + FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, + + /* IPSR9 */ + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, + FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, + FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, + FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, + FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, + FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, + FN_AVB_TX_EN, FN_SD1_CMD, + FN_AVB_TX_ER, FN_SCIFB0_SCK_B, + FN_SD1_DAT0, FN_AVB_TX_CLK, + FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, + FN_SCIFB0_TXD_B, FN_SD1_DAT2, + FN_AVB_COL, FN_SCIFB0_CTS_N_B, + FN_SD1_DAT3, FN_AVB_RXD0, + FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, + FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, + FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, + FN_VI3_CLK_B, + + /* IPSR10 */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, + FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, + FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, + FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, + FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, + FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, + FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, + FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, + FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, + FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, + FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, + FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, + FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, + FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, + FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, + FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, + FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, + FN_GLO_I0_B, FN_VI3_DATA6_B, + + /* IPSR11 */ + FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, + FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, + FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, + FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, + FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, + FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, + FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, + FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + FN_FMIN_E, FN_FMIN_F, + FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, + FN_I2C2_SDA_B, FN_MLB_DAT, + FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_SSI_SCK0129, FN_CAN_CLK_B, + FN_MOUT0, + + /* IPSR12 */ + FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, + FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, + FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, + FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, + FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, + FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, + FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, + FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, + FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, + FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, + FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, + FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, + FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, + FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, + FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, + FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, + FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, + FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, + FN_CAN_DEBUGOUT4, + + /* IPSR13 */ + FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, + FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, + FN_SCIFB1_CTS_N, FN_BPFCLK_D, + FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, + FN_BPFCLK_F, FN_SSI_WS6, + FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, + FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, + FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5, + FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, + FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, + FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, + FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, + FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, + FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, + FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, + FN_BPFCLK_E, FN_SSI_SDATA7_B, + FN_FMIN_G, FN_SSI_SDATA8, + FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, + FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, + FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, + FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, + FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, + + /* IPSR14 */ + FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, + FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, + FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, + FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, + FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, + FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, + FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, + FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, + FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, + FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, + FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, + FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, + FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, + FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, + FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, + FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, + FN_HRTS0_N_C, + + /* IPSR15 */ + FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, + FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, + FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, + FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, + FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, + FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, + FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, + FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, + FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, + FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, + FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, + FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0, + FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, + FN_DU2_DG6, FN_LCDOUT14, + + /* IPSR16 */ + FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, + FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, + FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, + FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, + FN_TCLK1_B, + + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFB1_4, + FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, + FN_SEL_VI3_0, FN_SEL_VI3_1, + FN_SEL_VI2_0, FN_SEL_VI2_1, + FN_SEL_VI1_0, FN_SEL_VI1_1, + FN_SEL_VI0_0, FN_SEL_VI0_1, + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, + FN_SEL_LBS_0, FN_SEL_LBS_1, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, + + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, + FN_SEL_ADI_0, FN_SEL_ADI_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, + FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, + + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + VI1_DATA7_VI1_B7_MARK, + + USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, + USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, + DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, + + D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, + D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, + VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, + VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, + VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, + SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, + VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, + SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, + VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, + IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, + I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, + VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK, + D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, + VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, + + D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, + VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, + SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, + VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, + SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, + VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, + D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, + VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, + D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, + VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, + SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, + VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, + D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, + VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, + A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, + + A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, + PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, + TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, + A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, + SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, + A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, + VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, + A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, + VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, + A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, + VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, + + A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, + VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, + A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, + VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, + A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, + MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, + VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, + ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, + ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, + A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, + AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, + ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, + VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, + + A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, + A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, + VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, + VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, + VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, + VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, + VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, + VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, + CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, + VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, + VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, + MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, + HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, + VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, + VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, + + EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, + VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, + EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, + VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, + INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, + MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, + VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, + I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, + CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, + CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, + VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, + INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, + VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, + WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, + VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, + IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, + VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, + MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, + VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, + SSI_WS78_B_MARK, + + DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, + DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, + SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, + INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, + ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, + TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, + I2C2_SCL_E_MARK, ETH_RX_ER_MARK, + STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, + IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, + STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, + SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, + HRX0_E_MARK, STP_ISSYNC_0_B_MARK, + TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, + RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, + STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, + ETH_REF_CLK_MARK, HCTS0_N_E_MARK, + STP_IVCXO27_1_B_MARK, HRX0_F_MARK, + + ETH_MDIO_MARK, HRTS0_N_E_MARK, + SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, + HTX0_F_MARK, BPFCLK_G_MARK, + ETH_TX_EN_MARK, SIM0_CLK_C_MARK, + HRTS0_N_F_MARK, ETH_MAGIC_MARK, + SIM0_RST_C_MARK, ETH_TXD0_MARK, + STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, + ETH_MDC_MARK, STP_ISD_1_B_MARK, + TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, + SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, + GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, + STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, + PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, + PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK, + AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, + ATACS00_N_MARK, AVB_RXD1_MARK, + VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, + + VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, + VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, + AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, + AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, + AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, + AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, + VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, + VI1_CLK_MARK, AVB_RX_DV_MARK, + VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, + AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, + SCIFA1_RXD_D_MARK, AVB_MDC_MARK, + VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, + VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, + AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, + AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, + AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, + SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, + SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, + + SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, + SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, + SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, + GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, + I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, + MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, + GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, + I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, + AVB_TX_EN_MARK, SD1_CMD_MARK, + AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, + SD1_DAT0_MARK, AVB_TX_CLK_MARK, + SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, + SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, + AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, + SD1_DAT3_MARK, AVB_RXD0_MARK, + SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, + TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, + IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, + VI3_CLK_B_MARK, + + SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, + GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, + SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, + VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, + VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, + VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, + TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, + SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, + VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, + TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, + SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, + VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, + TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, + SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, + VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, + GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, + MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, + HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, + VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, + TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, + VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, + GLO_I0_B_MARK, VI3_DATA6_B_MARK, + + SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, + GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, + TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, + SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, + MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, + SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, + MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, + SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, + VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, + MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, + FMIN_E_MARK, FMIN_F_MARK, + MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, + MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, + I2C2_SDA_B_MARK, MLB_DAT_MARK, + SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, + SSI_SCK0129_MARK, CAN_CLK_B_MARK, + MOUT0_MARK, + + SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, + SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, + SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, + SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, + SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, + MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, + STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, + CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, + SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, + SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, + MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, + SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, + MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, + SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, + CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, + IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, + CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, + IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, + CAN_DEBUGOUT4_MARK, + + SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, + LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, + SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, + DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, + BPFCLK_F_MARK, SSI_WS6_MARK, + SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, + LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, + FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK, + CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, + SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, + CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, + SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, + LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, + STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, + TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, + BPFCLK_E_MARK, SSI_SDATA7_B_MARK, + FMIN_G_MARK, SSI_SDATA8_MARK, + STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, + CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, + STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, + SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, + SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, + + AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, + DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, + REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, + MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, + I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, + DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, + TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, + HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, + LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, + SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, + MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, + SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, + DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, + SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, + LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, + CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, + SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, + MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, + HRTS0_N_C_MARK, + + SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, + LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, + TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, + SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, + IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, + DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, + DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, + LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, + LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, + LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, + DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, + SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, + HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, + DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, + DU2_DG6_MARK, LCDOUT14_MARK, + + MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, + DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, + MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, + ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, + USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, + TCLK1_B_MARK, + + IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK, + IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK, + PINMUX_MARK_END, +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), + PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), + PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(AVS2_MARK, FN_AVS2), + PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), + PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), + + PINMUX_IPSR_DATA(IP0_2_0, D0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_5_3, D1), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_8_6, D2), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_11_9, D3), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_15_12, D4), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP0_19_16, D5), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP0_22_20, D6), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), + PINMUX_IPSR_DATA(IP0_26_23, D7), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_DATA(IP0_30_27, D8), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), + + PINMUX_IPSR_DATA(IP1_3_0, D9), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_7_4, D10), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_11_8, D11), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_14_12, D12), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_17_15, D13), + PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_21_18, D14), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_25_22, D15), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_27_26, A0), + PINMUX_IPSR_DATA(IP1_27_26, PWM3), + PINMUX_IPSR_DATA(IP1_29_28, A1), + PINMUX_IPSR_DATA(IP1_29_28, PWM4), + + PINMUX_IPSR_DATA(IP2_2_0, A2), + PINMUX_IPSR_DATA(IP2_2_0, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP2_5_3, A3), + PINMUX_IPSR_DATA(IP2_5_3, PWM6), + PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP2_8_6, A4), + PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), + PINMUX_IPSR_DATA(IP2_11_9, A5), + PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), + PINMUX_IPSR_DATA(IP2_14_12, A6), + PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), + PINMUX_IPSR_DATA(IP2_17_15, A7), + PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), + PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), + PINMUX_IPSR_DATA(IP2_21_18, A8), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP2_25_22, A9), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP2_28_26, A10), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), + + PINMUX_IPSR_DATA(IP3_3_0, A11), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP3_7_4, A12), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP3_11_8, A13), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), + PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP3_14_12, A14), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), + PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), + PINMUX_IPSR_DATA(IP3_17_15, A15), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), + PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), + PINMUX_IPSR_DATA(IP3_19_18, A16), + PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), + PINMUX_IPSR_DATA(IP3_22_20, A17), + PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), + PINMUX_IPSR_DATA(IP3_25_23, A18), + PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), + PINMUX_IPSR_DATA(IP3_28_26, A19), + PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), + PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), + PINMUX_IPSR_DATA(IP3_31_29, A20), + PINMUX_IPSR_DATA(IP3_31_29, SPCLK), + PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), + + PINMUX_IPSR_DATA(IP4_2_0, A21), + PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), + PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), + PINMUX_IPSR_DATA(IP4_5_3, A22), + PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), + PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), + PINMUX_IPSR_DATA(IP4_8_6, A23), + PINMUX_IPSR_DATA(IP4_8_6, IO2), + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), + PINMUX_IPSR_DATA(IP4_11_9, A24), + PINMUX_IPSR_DATA(IP4_11_9, IO3), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP4_14_12, A25), + PINMUX_IPSR_DATA(IP4_14_12, SSL), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP4_17_15, CS0_N), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), + PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), + PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), + PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), + PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), + PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), + PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), + + PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), + PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), + PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), + PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0), + PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0), + PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0), + PINMUX_IPSR_DATA(IP5_12_10, BS_N), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP5_12_10, DRACK0), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP5_14_13, RD_N), + PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), + PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), + PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), + PINMUX_IPSR_DATA(IP5_20_18, WE0_N), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP5_23_21, WE1_N), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0), + PINMUX_IPSR_DATA(IP5_26_24, IRQ3), + PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), + + PINMUX_IPSR_DATA(IP6_2_0, DACK0), + PINMUX_IPSR_DATA(IP6_2_0, IRQ0), + PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), + PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP6_8_6, DACK1), + PINMUX_IPSR_DATA(IP6_8_6, IRQ1), + PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), + PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_13_11, DACK2), + PINMUX_IPSR_DATA(IP6_13_11, IRQ2), + PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), + + PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6), + PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), + PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_18_16, PWM0), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), + PINMUX_IPSR_DATA(IP7_24_22, PWM2), + PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), + PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), + PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), + + PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), + PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), + PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), + PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), + PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), + PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), + PINMUX_IPSR_DATA(IP8_28, SD0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), + + PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), + PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), + PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), + PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), + PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), + PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), + PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), + PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), + PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), + PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), + PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), + + PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), + PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), + PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), + PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), + PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), + PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), + PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), + PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), + PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), + + PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), + PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP11_4, SD3_CLK), + PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), + PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), + PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD), + PINMUX_IPSR_DATA(IP11_6_5, MTS_N), + PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0), + PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0), + PINMUX_IPSR_DATA(IP11_8_7, STM_N), + PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1), + PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1), + PINMUX_IPSR_DATA(IP11_10_9, MDATA), + PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2), + PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2), + PINMUX_IPSR_DATA(IP11_12_11, SDATA), + PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3), + PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3), + PINMUX_IPSR_DATA(IP11_14_13, SCKZ), + PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), + PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP11_17_15, VSP), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), + PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), + PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP11_31_30, MOUT0), + + PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP12_1_0, MOUT1), + PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP12_3_2, MOUT2), + PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), + PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_DATA(IP12_5_4, MOUT5), + PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), + PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1), + PINMUX_IPSR_DATA(IP12_7_6, MOUT6), + PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), + PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), + PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), + PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), + PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), + PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), + PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), + PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), + PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), + PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), + PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), + PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), + PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), + PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), + PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), + PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), + PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), + PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), + PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), + PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), + PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), + + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), + PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), + PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), + PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), + PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), + PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), + PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), + PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), + PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), + PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), + PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), + PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), + PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), + PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), + PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), + PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), + PINMUX_IPSR_DATA(IP13_22_19, TCLK2), + PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), + PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), + PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), + PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), + PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), + PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), + PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), + + PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), + PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), + PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), + PINMUX_IPSR_DATA(IP14_2_0, REMOCON), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP14_5_3, SCK0), + PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), + PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), + PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), + PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), + PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), + PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP14_15_12, CTS0_N), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), + PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11), + PINMUX_IPSR_DATA(IP14_15_12, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP14_18_16, RTS0_N), + PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), + PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), + PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), + PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), + PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), + PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), + PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), + PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), + PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), + PINMUX_IPSR_DATA(IP14_27_25, QCLK), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_DATA(IP14_30_28, RTS1_N), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), + PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), + + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), + PINMUX_IPSR_DATA(IP15_2_0, SCK2), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), + PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0), + PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), + PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0), + PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), + PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0), + PINMUX_IPSR_DATA(IP15_11_9, HSCK0), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), + PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), + PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), + PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), + PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), + PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), + PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), + PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), + PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), + PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), + PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), + PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_22_20, ADICLK), + PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), + PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), + PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), + PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), + PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), + PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), + PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), + PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), + PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), + PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), + PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), + PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), + PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), + + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), + PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), + PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), + PINMUX_IPSR_DATA(IP16_2_0, QPOLA), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), + PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), + PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), + PINMUX_IPSR_DATA(IP16_5_3, QPOLB), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), + PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), + PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), + PINMUX_IPSR_DATA(IP16_7, USB1_OVC), + PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), + + PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0), + PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0), + PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1), + PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1), + + PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0), + PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0), + PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1), + PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), +}; + +/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */ +#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) +#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) +#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), + + /* Pins not associated with a GPIO port */ + SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15), + SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15), + SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), + SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15), +}; + +/* - AUDIO CLOCK ------------------------------------------------------------ */ +static const unsigned int audio_clk_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(4, 25), +}; +static const unsigned int audio_clk_a_mux[] = { + AUDIO_CLKA_MARK, +}; +static const unsigned int audio_clk_b_pins[] = { + /* CLK B */ + RCAR_GP_PIN(4, 26), +}; +static const unsigned int audio_clk_b_mux[] = { + AUDIO_CLKB_MARK, +}; +static const unsigned int audio_clk_c_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 27), +}; +static const unsigned int audio_clk_c_mux[] = { + AUDIO_CLKC_MARK, +}; +static const unsigned int audio_clkout_pins[] = { + /* CLK OUT */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int audio_clkout_mux[] = { + AUDIO_CLKOUT_MARK, +}; +static const unsigned int audio_clkout_b_pins[] = { + /* CLK OUT B */ + RCAR_GP_PIN(0, 23), +}; +static const unsigned int audio_clkout_b_mux[] = { + AUDIO_CLKOUT_B_MARK, +}; +static const unsigned int audio_clkout_c_pins[] = { + /* CLK OUT C */ + RCAR_GP_PIN(5, 27), +}; +static const unsigned int audio_clkout_c_mux[] = { + AUDIO_CLKOUT_C_MARK, +}; +static const unsigned int audio_clkout_d_pins[] = { + /* CLK OUT D */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int audio_clkout_d_mux[] = { + AUDIO_CLKOUT_D_MARK, +}; +/* - DU RGB ----------------------------------------------------------------- */ +static const unsigned int du_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), +}; +static const unsigned int du_rgb666_mux[] = { + DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, + DU2_DR3_MARK, DU2_DR2_MARK, + DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, + DU2_DG3_MARK, DU2_DG2_MARK, + DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, + DU2_DB3_MARK, DU2_DB2_MARK, +}; +static const unsigned int du_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1), + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), +}; +static const unsigned int du_rgb888_mux[] = { + DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, + DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK, + DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, + DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK, + DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, + DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK, +}; +static const unsigned int du_clk_out_0_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int du_clk_out_0_mux[] = { + DU0_DOTCLKOUT_MARK +}; +static const unsigned int du_clk_out_1_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int du_clk_out_1_mux[] = { + DU1_DOTCLKOUT_MARK +}; +static const unsigned int du_sync_0_pins[] = { + /* VSYNC, HSYNC, DISP */ + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0), +}; +static const unsigned int du_sync_0_mux[] = { + DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, + DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK +}; +static const unsigned int du_sync_1_pins[] = { + /* VSYNC, HSYNC, DISP */ + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16), +}; +static const unsigned int du_sync_1_mux[] = { + DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, + DU2_DISP_MARK +}; +static const unsigned int du_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int du_cde_mux[] = { + DU2_CDE_MARK, +}; +/* - DU0 -------------------------------------------------------------------- */ +static const unsigned int du0_clk_in_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(5, 26), +}; +static const unsigned int du0_clk_in_mux[] = { + DU_DOTCLKIN0_MARK +}; +/* - DU1 -------------------------------------------------------------------- */ +static const unsigned int du1_clk_in_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(5, 27), +}; +static const unsigned int du1_clk_in_mux[] = { + DU_DOTCLKIN1_MARK, +}; +/* - DU2 -------------------------------------------------------------------- */ +static const unsigned int du2_clk_in_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(5, 28), +}; +static const unsigned int du2_clk_in_mux[] = { + DU_DOTCLKIN2_MARK, +}; +/* - ETH -------------------------------------------------------------------- */ +static const unsigned int eth_link_pins[] = { + /* LINK */ + RCAR_GP_PIN(2, 22), +}; +static const unsigned int eth_link_mux[] = { + ETH_LINK_MARK, +}; +static const unsigned int eth_magic_pins[] = { + /* MAGIC */ + RCAR_GP_PIN(2, 27), +}; +static const unsigned int eth_magic_mux[] = { + ETH_MAGIC_MARK, +}; +static const unsigned int eth_mdio_pins[] = { + /* MDC, MDIO */ + RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), +}; +static const unsigned int eth_mdio_mux[] = { + ETH_MDC_MARK, ETH_MDIO_MARK, +}; +static const unsigned int eth_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), + RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), +}; +static const unsigned int eth_rmii_mux[] = { + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, +}; +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 7), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; +static const unsigned int hscif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), +}; +static const unsigned int hscif0_data_b_mux[] = { + HRX0_B_MARK, HTX0_B_MARK, +}; +static const unsigned int hscif0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), +}; +static const unsigned int hscif0_ctrl_b_mux[] = { + HRTS0_N_B_MARK, HCTS0_N_B_MARK, +}; +static const unsigned int hscif0_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), +}; +static const unsigned int hscif0_data_c_mux[] = { + HRX0_C_MARK, HTX0_C_MARK, +}; +static const unsigned int hscif0_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), +}; +static const unsigned int hscif0_ctrl_c_mux[] = { + HRTS0_N_C_MARK, HCTS0_N_C_MARK, +}; +static const unsigned int hscif0_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int hscif0_data_d_mux[] = { + HRX0_D_MARK, HTX0_D_MARK, +}; +static const unsigned int hscif0_ctrl_d_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), +}; +static const unsigned int hscif0_ctrl_d_mux[] = { + HRTS0_N_D_MARK, HCTS0_N_D_MARK, +}; +static const unsigned int hscif0_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +}; +static const unsigned int hscif0_data_e_mux[] = { + HRX0_E_MARK, HTX0_E_MARK, +}; +static const unsigned int hscif0_ctrl_e_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), +}; +static const unsigned int hscif0_ctrl_e_mux[] = { + HRTS0_N_E_MARK, HCTS0_N_E_MARK, +}; +static const unsigned int hscif0_data_f_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), +}; +static const unsigned int hscif0_data_f_mux[] = { + HRX0_F_MARK, HTX0_F_MARK, +}; +static const unsigned int hscif0_ctrl_f_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), +}; +static const unsigned int hscif0_ctrl_f_mux[] = { + HRTS0_N_F_MARK, HCTS0_N_F_MARK, +}; +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int hscif1_data_mux[] = { + HRX1_MARK, HTX1_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCK1_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HRTS1_N_MARK, HCTS1_N_MARK, +}; +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), +}; +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; +static const unsigned int hscif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 28), +}; +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), +}; +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), +}; +static const unsigned int i2c0_mux[] = { + I2C0_SCL_MARK, I2C0_SDA_MARK, +}; +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), +}; +static const unsigned int i2c1_mux[] = { + I2C1_SCL_MARK, I2C1_SDA_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int i2c1_b_mux[] = { + I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, +}; +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), +}; +static const unsigned int i2c1_c_mux[] = { + I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, +}; +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int i2c2_mux[] = { + I2C2_SCL_MARK, I2C2_SDA_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int i2c2_b_mux[] = { + I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, +}; +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int i2c2_c_mux[] = { + I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, +}; +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; +static const unsigned int i2c2_d_mux[] = { + I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, +}; +static const unsigned int i2c2_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), +}; +static const unsigned int i2c2_e_mux[] = { + I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, +}; +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), +}; +static const unsigned int i2c3_mux[] = { + I2C3_SCL_MARK, I2C3_SDA_MARK, +}; +/* - IIC0 (I2C4) ------------------------------------------------------------ */ +static const unsigned int iic0_pins[] = { + /* SCL, SDA */ + PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), +}; +static const unsigned int iic0_mux[] = { + IIC0_SCL_MARK, IIC0_SDA_MARK, +}; +/* - IIC1 (I2C5) ------------------------------------------------------------ */ +static const unsigned int iic1_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), +}; +static const unsigned int iic1_mux[] = { + IIC1_SCL_MARK, IIC1_SDA_MARK, +}; +static const unsigned int iic1_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int iic1_b_mux[] = { + IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, +}; +static const unsigned int iic1_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), +}; +static const unsigned int iic1_c_mux[] = { + IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, +}; +/* - IIC2 (I2C6) ------------------------------------------------------------ */ +static const unsigned int iic2_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int iic2_mux[] = { + IIC2_SCL_MARK, IIC2_SDA_MARK, +}; +static const unsigned int iic2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int iic2_b_mux[] = { + IIC2_SCL_B_MARK, IIC2_SDA_B_MARK, +}; +static const unsigned int iic2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int iic2_c_mux[] = { + IIC2_SCL_C_MARK, IIC2_SDA_C_MARK, +}; +static const unsigned int iic2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; +static const unsigned int iic2_d_mux[] = { + IIC2_SCL_D_MARK, IIC2_SDA_D_MARK, +}; +static const unsigned int iic2_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), +}; +static const unsigned int iic2_e_mux[] = { + IIC2_SCL_E_MARK, IIC2_SDA_E_MARK, +}; +/* - IIC3 (I2C7) ------------------------------------------------------------ */ +static const unsigned int iic3_pins[] = { +/* SCL, SDA */ + PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), +}; +static const unsigned int iic3_mux[] = { + IIC3_SCL_MARK, IIC3_SDA_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +static const unsigned int intc_irq0_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_irq1_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_irq2_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 29), +}; +static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_irq3_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, +}; +/* - MMCIF0 ----------------------------------------------------------------- */ +static const unsigned int mmc0_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int mmc0_data1_mux[] = { + MMC0_D0_MARK, +}; +static const unsigned int mmc0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int mmc0_data4_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, +}; +static const unsigned int mmc0_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), + RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int mmc0_data8_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, + MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, +}; +static const unsigned int mmc0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), +}; +static const unsigned int mmc0_ctrl_mux[] = { + MMC0_CLK_MARK, MMC0_CMD_MARK, +}; +/* - MMCIF1 ----------------------------------------------------------------- */ +static const unsigned int mmc1_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(3, 26), +}; +static const unsigned int mmc1_data1_mux[] = { + MMC1_D0_MARK, +}; +static const unsigned int mmc1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), +}; +static const unsigned int mmc1_data4_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, +}; +static const unsigned int mmc1_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), + RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; +static const unsigned int mmc1_data8_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, + MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, +}; +static const unsigned int mmc1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), +}; +static const unsigned int mmc1_ctrl_mux[] = { + MMC1_CLK_MARK, MMC1_CMD_MARK, +}; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int msiof0_rx_mux[] = { + MSIOF0_RXD_MARK, +}; +static const unsigned int msiof0_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int msiof0_tx_mux[] = { + MSIOF0_TXD_MARK, +}; + +static const unsigned int msiof0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int msiof0_clk_b_mux[] = { + MSIOF0_SCK_B_MARK, +}; +static const unsigned int msiof0_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 12), +}; +static const unsigned int msiof0_ss1_b_mux[] = { + MSIOF0_SS1_B_MARK, +}; +static const unsigned int msiof0_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int msiof0_ss2_b_mux[] = { + MSIOF0_SS2_B_MARK, +}; +static const unsigned int msiof0_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 29), +}; +static const unsigned int msiof0_rx_b_mux[] = { + MSIOF0_RXD_B_MARK, +}; +static const unsigned int msiof0_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 28), +}; +static const unsigned int msiof0_tx_b_mux[] = { + MSIOF0_TXD_B_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 8), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(4, 9), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(4, 10), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(4, 11), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int msiof1_rx_mux[] = { + MSIOF1_RXD_MARK, +}; +static const unsigned int msiof1_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(4, 12), +}; +static const unsigned int msiof1_tx_mux[] = { + MSIOF1_TXD_MARK, +}; + +static const unsigned int msiof1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int msiof1_clk_b_mux[] = { + MSIOF1_SCK_B_MARK, +}; +static const unsigned int msiof1_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int msiof1_ss1_b_mux[] = { + MSIOF1_SS1_B_MARK, +}; +static const unsigned int msiof1_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int msiof1_ss2_b_mux[] = { + MSIOF1_SS2_B_MARK, +}; +static const unsigned int msiof1_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int msiof1_rx_b_mux[] = { + MSIOF1_RXD_B_MARK, +}; +static const unsigned int msiof1_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int msiof1_tx_b_mux[] = { + MSIOF1_TXD_B_MARK, +}; +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 27), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 26), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 30), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 31), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 29), +}; +static const unsigned int msiof2_rx_mux[] = { + MSIOF2_RXD_MARK, +}; +static const unsigned int msiof2_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 28), +}; +static const unsigned int msiof2_tx_mux[] = { + MSIOF2_TXD_MARK, +}; +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int msiof3_clk_mux[] = { + MSIOF3_SCK_MARK, +}; +static const unsigned int msiof3_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(4, 30), +}; +static const unsigned int msiof3_sync_mux[] = { + MSIOF3_SYNC_MARK, +}; +static const unsigned int msiof3_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(4, 31), +}; +static const unsigned int msiof3_ss1_mux[] = { + MSIOF3_SS1_MARK, +}; +static const unsigned int msiof3_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int msiof3_ss2_mux[] = { + MSIOF3_SS2_MARK, +}; +static const unsigned int msiof3_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int msiof3_rx_mux[] = { + MSIOF3_RXD_MARK, +}; +static const unsigned int msiof3_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int msiof3_tx_mux[] = { + MSIOF3_TXD_MARK, +}; + +static const unsigned int msiof3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int msiof3_clk_b_mux[] = { + MSIOF3_SCK_B_MARK, +}; +static const unsigned int msiof3_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof3_sync_b_mux[] = { + MSIOF3_SYNC_B_MARK, +}; +static const unsigned int msiof3_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int msiof3_rx_b_mux[] = { + MSIOF3_RXD_B_MARK, +}; +static const unsigned int msiof3_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int msiof3_tx_b_mux[] = { + MSIOF3_TXD_B_MARK, +}; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_MARK, CTS0_N_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), +}; +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_MARK, CTS1_N_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), +}; +static const unsigned int scif1_data_c_mux[] = { + RX1_C_MARK, TX1_C_MARK, +}; +static const unsigned int scif1_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), +}; +static const unsigned int scif1_data_d_mux[] = { + RX1_D_MARK, TX1_D_MARK, +}; +static const unsigned int scif1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int scif1_clk_d_mux[] = { + SCK1_D_MARK, +}; +static const unsigned int scif1_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +}; +static const unsigned int scif1_data_e_mux[] = { + RX1_E_MARK, TX1_E_MARK, +}; +static const unsigned int scif1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 20), +}; +static const unsigned int scif1_clk_e_mux[] = { + SCK1_E_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), +}; +static const unsigned int scif2_data_mux[] = { + RX2_MARK, TX2_MARK, +}; +static const unsigned int scif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int scif2_clk_mux[] = { + SCK2_MARK, +}; +static const unsigned int scif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int scif2_data_b_mux[] = { + RX2_B_MARK, TX2_B_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, +}; +static const unsigned int scifa0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), +}; +static const unsigned int scifa0_data_b_mux[] = { + SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK +}; +static const unsigned int scifa0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int scifa0_clk_b_mux[] = { + SCIFA0_SCK_B_MARK, +}; +static const unsigned int scifa0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), +}; +static const unsigned int scifa0_ctrl_b_mux[] = { + SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, +}; +static const unsigned int scifa1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), +}; +static const unsigned int scifa1_data_b_mux[] = { + SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, +}; +static const unsigned int scifa1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 23), +}; +static const unsigned int scifa1_clk_b_mux[] = { + SCIFA1_SCK_B_MARK, +}; +static const unsigned int scifa1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), +}; +static const unsigned int scifa1_ctrl_b_mux[] = { + SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, +}; +static const unsigned int scifa1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int scifa1_data_c_mux[] = { + SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, +}; +static const unsigned int scifa1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int scifa1_clk_c_mux[] = { + SCIFA1_SCK_C_MARK, +}; +static const unsigned int scifa1_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), +}; +static const unsigned int scifa1_ctrl_c_mux[] = { + SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, +}; +static const unsigned int scifa1_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), +}; +static const unsigned int scifa1_data_d_mux[] = { + SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, +}; +static const unsigned int scifa1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int scifa1_clk_d_mux[] = { + SCIFA1_SCK_D_MARK, +}; +static const unsigned int scifa1_ctrl_d_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), +}; +static const unsigned int scifa1_ctrl_d_mux[] = { + SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, +}; +static const unsigned int scifa2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int scifa2_clk_mux[] = { + SCIFA2_SCK_MARK, +}; +static const unsigned int scifa2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), +}; +static const unsigned int scifa2_ctrl_mux[] = { + SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, +}; +static const unsigned int scifa2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), +}; +static const unsigned int scifa2_data_b_mux[] = { + SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, +}; +static const unsigned int scifa2_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), +}; +static const unsigned int scifa2_data_c_mux[] = { + SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, +}; +static const unsigned int scifa2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 29), +}; +static const unsigned int scifa2_clk_c_mux[] = { + SCIFA2_SCK_C_MARK, +}; +/* - SCIFB0 ----------------------------------------------------------------- */ +static const unsigned int scifb0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), +}; +static const unsigned int scifb0_data_mux[] = { + SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, +}; +static const unsigned int scifb0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 8), +}; +static const unsigned int scifb0_clk_mux[] = { + SCIFB0_SCK_MARK, +}; +static const unsigned int scifb0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), +}; +static const unsigned int scifb0_ctrl_mux[] = { + SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, +}; +static const unsigned int scifb0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int scifb0_data_b_mux[] = { + SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, +}; +static const unsigned int scifb0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int scifb0_clk_b_mux[] = { + SCIFB0_SCK_B_MARK, +}; +static const unsigned int scifb0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), +}; +static const unsigned int scifb0_ctrl_b_mux[] = { + SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, +}; +static const unsigned int scifb0_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int scifb0_data_c_mux[] = { + SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, +}; +/* - SCIFB1 ----------------------------------------------------------------- */ +static const unsigned int scifb1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +}; +static const unsigned int scifb1_data_mux[] = { + SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, +}; +static const unsigned int scifb1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 14), +}; +static const unsigned int scifb1_clk_mux[] = { + SCIFB1_SCK_MARK, +}; +static const unsigned int scifb1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), +}; +static const unsigned int scifb1_ctrl_mux[] = { + SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, +}; +static const unsigned int scifb1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), +}; +static const unsigned int scifb1_data_b_mux[] = { + SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, +}; +static const unsigned int scifb1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int scifb1_clk_b_mux[] = { + SCIFB1_SCK_B_MARK, +}; +static const unsigned int scifb1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), +}; +static const unsigned int scifb1_ctrl_b_mux[] = { + SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, +}; +static const unsigned int scifb1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int scifb1_data_c_mux[] = { + SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, +}; +static const unsigned int scifb1_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), +}; +static const unsigned int scifb1_data_d_mux[] = { + SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, +}; +static const unsigned int scifb1_data_e_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), +}; +static const unsigned int scifb1_data_e_mux[] = { + SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, +}; +static const unsigned int scifb1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int scifb1_clk_e_mux[] = { + SCIFB1_SCK_E_MARK, +}; +static const unsigned int scifb1_data_f_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int scifb1_data_f_mux[] = { + SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, +}; +static const unsigned int scifb1_data_g_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +}; +static const unsigned int scifb1_data_g_mux[] = { + SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, +}; +static const unsigned int scifb1_clk_g_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 20), +}; +static const unsigned int scifb1_clk_g_mux[] = { + SCIFB1_SCK_G_MARK, +}; +/* - SCIFB2 ----------------------------------------------------------------- */ +static const unsigned int scifb2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int scifb2_data_mux[] = { + SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, +}; +static const unsigned int scifb2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 21), +}; +static const unsigned int scifb2_clk_mux[] = { + SCIFB2_SCK_MARK, +}; +static const unsigned int scifb2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), +}; +static const unsigned int scifb2_ctrl_mux[] = { + SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, +}; +static const unsigned int scifb2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), +}; +static const unsigned int scifb2_data_b_mux[] = { + SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, +}; +static const unsigned int scifb2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 31), +}; +static const unsigned int scifb2_clk_b_mux[] = { + SCIFB2_SCK_B_MARK, +}; +static const unsigned int scifb2_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), +}; +static const unsigned int scifb2_ctrl_b_mux[] = { + SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, +}; +static const unsigned int scifb2_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int scifb2_data_c_mux[] = { + SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 22), +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 23), +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 26), +}; +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), +}; +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, +}; +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), +}; +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 30), +}; +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 31), +}; +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { + /* SDATA0 */ + RCAR_GP_PIN(4, 5), +}; +static const unsigned int ssi0_data_mux[] = { + SSI_SDATA0_MARK, +}; +static const unsigned int ssi0129_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), +}; +static const unsigned int ssi0129_ctrl_mux[] = { + SSI_SCK0129_MARK, SSI_WS0129_MARK, +}; +static const unsigned int ssi1_data_pins[] = { + /* SDATA1 */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int ssi1_data_mux[] = { + SSI_SDATA1_MARK, +}; +static const unsigned int ssi1_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24), +}; +static const unsigned int ssi1_ctrl_mux[] = { + SSI_SCK1_MARK, SSI_WS1_MARK, +}; +static const unsigned int ssi2_data_pins[] = { + /* SDATA2 */ + RCAR_GP_PIN(4, 7), +}; +static const unsigned int ssi2_data_mux[] = { + SSI_SDATA2_MARK, +}; +static const unsigned int ssi2_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17), +}; +static const unsigned int ssi2_ctrl_mux[] = { + SSI_SCK2_MARK, SSI_WS2_MARK, +}; +static const unsigned int ssi3_data_pins[] = { + /* SDATA3 */ + RCAR_GP_PIN(4, 10), +}; +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK +}; +static const unsigned int ssi34_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; +static const unsigned int ssi34_ctrl_mux[] = { + SSI_SCK34_MARK, SSI_WS34_MARK, +}; +static const unsigned int ssi4_data_pins[] = { + /* SDATA4 */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int ssi4_data_mux[] = { + SSI_SDATA4_MARK, +}; +static const unsigned int ssi4_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +}; +static const unsigned int ssi4_ctrl_mux[] = { + SSI_SCK4_MARK, SSI_WS4_MARK, +}; +static const unsigned int ssi5_pins[] = { + /* SDATA5, SCK, WS */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), +}; +static const unsigned int ssi5_mux[] = { + SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK, +}; +static const unsigned int ssi5_b_pins[] = { + /* SDATA5, SCK, WS */ + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int ssi5_b_mux[] = { + SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK +}; +static const unsigned int ssi5_c_pins[] = { + /* SDATA5, SCK, WS */ + RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +}; +static const unsigned int ssi5_c_mux[] = { + SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK, +}; +static const unsigned int ssi6_pins[] = { + /* SDATA6, SCK, WS */ + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), +}; +static const unsigned int ssi6_mux[] = { + SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK, +}; +static const unsigned int ssi6_b_pins[] = { + /* SDATA6, SCK, WS */ + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27), +}; +static const unsigned int ssi6_b_mux[] = { + SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK, +}; +static const unsigned int ssi7_data_pins[] = { + /* SDATA7 */ + RCAR_GP_PIN(4, 22), +}; +static const unsigned int ssi7_data_mux[] = { + SSI_SDATA7_MARK, +}; +static const unsigned int ssi7_b_data_pins[] = { + /* SDATA7 */ + RCAR_GP_PIN(4, 22), +}; +static const unsigned int ssi7_b_data_mux[] = { + SSI_SDATA7_B_MARK, +}; +static const unsigned int ssi7_c_data_pins[] = { + /* SDATA7 */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int ssi7_c_data_mux[] = { + SSI_SDATA7_C_MARK, +}; +static const unsigned int ssi78_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), +}; +static const unsigned int ssi78_ctrl_mux[] = { + SSI_SCK78_MARK, SSI_WS78_MARK, +}; +static const unsigned int ssi78_b_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24), +}; +static const unsigned int ssi78_b_ctrl_mux[] = { + SSI_SCK78_B_MARK, SSI_WS78_B_MARK, +}; +static const unsigned int ssi78_c_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), +}; +static const unsigned int ssi78_c_ctrl_mux[] = { + SSI_SCK78_C_MARK, SSI_WS78_C_MARK, +}; +static const unsigned int ssi8_data_pins[] = { + /* SDATA8 */ + RCAR_GP_PIN(4, 23), +}; +static const unsigned int ssi8_data_mux[] = { + SSI_SDATA8_MARK, +}; +static const unsigned int ssi8_b_data_pins[] = { + /* SDATA8 */ + RCAR_GP_PIN(4, 23), +}; +static const unsigned int ssi8_b_data_mux[] = { + SSI_SDATA8_B_MARK, +}; +static const unsigned int ssi8_c_data_pins[] = { + /* SDATA8 */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int ssi8_c_data_mux[] = { + SSI_SDATA8_C_MARK, +}; +static const unsigned int ssi9_data_pins[] = { + /* SDATA9 */ + RCAR_GP_PIN(4, 24), +}; +static const unsigned int ssi9_data_mux[] = { + SSI_SDATA9_MARK, +}; +static const unsigned int ssi9_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), +}; +static const unsigned int ssi9_ctrl_mux[] = { + SSI_SCK9_MARK, SSI_WS9_MARK, +}; +/* - TPU0 ------------------------------------------------------------------- */ +static const unsigned int tpu0_to0_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int tpu0_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu0_to1_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 21), +}; +static const unsigned int tpu0_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu0_to2_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 22), +}; +static const unsigned int tpu0_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu0_to3_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 23), +}; +static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, +}; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + /* PWEN, OVC/VBUS */ + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), +}; +static const unsigned int usb0_mux[] = { + USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, +}; +static const unsigned int usb0_ovc_vbus_pins[] = { + /* OVC/VBUS */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int usb0_ovc_vbus_mux[] = { + USB0_OVC_VBUS_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), +}; +static const unsigned int usb1_mux[] = { + USB1_PWEN_MARK, USB1_OVC_MARK, +}; +/* - USB2 ------------------------------------------------------------------- */ +static const unsigned int usb2_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), +}; +static const unsigned int usb2_mux[] = { + USB2_PWEN_MARK, USB2_OVC_MARK, +}; + +union vin_data { + unsigned int data24[24]; + unsigned int data20[20]; + unsigned int data16[16]; + unsigned int data12[12]; + unsigned int data10[10]; + unsigned int data8[8]; + unsigned int data4[4]; +}; + +#define VIN_DATA_PIN_GROUP(n, s) \ + { \ + .name = #n#s, \ + .pins = n##_pins.data##s, \ + .mux = n##_mux.data##s, \ + .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ + } + +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + /* G */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + /* R */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, + }, +}; +static const unsigned int vin0_data18_pins[] = { + /* B */ + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + /* G */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + /* R */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), +}; +static const unsigned int vin0_data18_mux[] = { + /* B */ + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + RCAR_GP_PIN(0, 12), /* HSYNC */ + RCAR_GP_PIN(0, 13), /* VSYNC */ +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_N_MARK, + VI0_VSYNC_N_MARK, +}; +static const unsigned int vin0_field_pins[] = { + RCAR_GP_PIN(0, 15), +}; +static const unsigned int vin0_field_mux[] = { + VI0_FIELD_MARK, +}; +static const unsigned int vin0_clkenb_pins[] = { + RCAR_GP_PIN(0, 14), +}; +static const unsigned int vin0_clkenb_mux[] = { + VI0_CLKENB_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + RCAR_GP_PIN(2, 0), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const union vin_data vin1_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), + }, +}; +static const union vin_data vin1_data_mux = { + .data24 = { + /* B */ + VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, + VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, + VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, + VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, + /* G */ + VI1_G0_MARK, VI1_G1_MARK, + VI1_G2_MARK, VI1_G3_MARK, + VI1_G4_MARK, VI1_G5_MARK, + VI1_G6_MARK, VI1_G7_MARK, + /* R */ + VI1_R0_MARK, VI1_R1_MARK, + VI1_R2_MARK, VI1_R3_MARK, + VI1_R4_MARK, VI1_R5_MARK, + VI1_R6_MARK, VI1_R7_MARK, + }, +}; +static const unsigned int vin1_data18_pins[] = { + /* B */ + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), + /* G */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), +}; +static const unsigned int vin1_data18_mux[] = { + /* B */ + VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, + VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, + VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, + /* G */ + VI1_G2_MARK, VI1_G3_MARK, + VI1_G4_MARK, VI1_G5_MARK, + VI1_G6_MARK, VI1_G7_MARK, + /* R */ + VI1_R2_MARK, VI1_R3_MARK, + VI1_R4_MARK, VI1_R5_MARK, + VI1_R6_MARK, VI1_R7_MARK, +}; +static const unsigned int vin1_sync_pins[] = { + RCAR_GP_PIN(1, 24), /* HSYNC */ + RCAR_GP_PIN(1, 25), /* VSYNC */ +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_N_MARK, + VI1_VSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + RCAR_GP_PIN(1, 13), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + RCAR_GP_PIN(1, 26), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + RCAR_GP_PIN(2, 9), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; +/* - VIN2 ----------------------------------------------------------------- */ +static const union vin_data vin2_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + /* G */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), + }, +}; +static const union vin_data vin2_data_mux = { + .data24 = { + /* B */ + VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, + VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, + VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, + /* G */ + VI2_G0_MARK, VI2_G1_MARK, + VI2_G2_MARK, VI2_G3_MARK, + VI2_G4_MARK, VI2_G5_MARK, + VI2_G6_MARK, VI2_G7_MARK, + /* R */ + VI2_R0_MARK, VI2_R1_MARK, + VI2_R2_MARK, VI2_R3_MARK, + VI2_R4_MARK, VI2_R5_MARK, + VI2_R6_MARK, VI2_R7_MARK, + }, +}; +static const unsigned int vin2_data18_pins[] = { + /* B */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + /* G */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), +}; +static const unsigned int vin2_data18_mux[] = { + /* B */ + VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, + VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, + /* G */ + VI2_G2_MARK, VI2_G3_MARK, + VI2_G4_MARK, VI2_G5_MARK, + VI2_G6_MARK, VI2_G7_MARK, + /* R */ + VI2_R2_MARK, VI2_R3_MARK, + VI2_R4_MARK, VI2_R5_MARK, + VI2_R6_MARK, VI2_R7_MARK, +}; +static const unsigned int vin2_sync_pins[] = { + RCAR_GP_PIN(1, 16), /* HSYNC */ + RCAR_GP_PIN(1, 21), /* VSYNC */ +}; +static const unsigned int vin2_sync_mux[] = { + VI2_HSYNC_N_MARK, + VI2_VSYNC_N_MARK, +}; +static const unsigned int vin2_field_pins[] = { + RCAR_GP_PIN(1, 9), +}; +static const unsigned int vin2_field_mux[] = { + VI2_FIELD_MARK, +}; +static const unsigned int vin2_clkenb_pins[] = { + RCAR_GP_PIN(1, 8), +}; +static const unsigned int vin2_clkenb_mux[] = { + VI2_CLKENB_MARK, +}; +static const unsigned int vin2_clk_pins[] = { + RCAR_GP_PIN(1, 11), +}; +static const unsigned int vin2_clk_mux[] = { + VI2_CLK_MARK, +}; +/* - VIN3 ----------------------------------------------------------------- */ +static const unsigned int vin3_data8_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin3_data8_mux[] = { + VI3_DATA0_MARK, VI3_DATA1_MARK, + VI3_DATA2_MARK, VI3_DATA3_MARK, + VI3_DATA4_MARK, VI3_DATA5_MARK, + VI3_DATA6_MARK, VI3_DATA7_MARK, +}; +static const unsigned int vin3_sync_pins[] = { + RCAR_GP_PIN(1, 16), /* HSYNC */ + RCAR_GP_PIN(1, 17), /* VSYNC */ +}; +static const unsigned int vin3_sync_mux[] = { + VI3_HSYNC_N_MARK, + VI3_VSYNC_N_MARK, +}; +static const unsigned int vin3_field_pins[] = { + RCAR_GP_PIN(1, 15), +}; +static const unsigned int vin3_field_mux[] = { + VI3_FIELD_MARK, +}; +static const unsigned int vin3_clkenb_pins[] = { + RCAR_GP_PIN(1, 14), +}; +static const unsigned int vin3_clkenb_mux[] = { + VI3_CLKENB_MARK, +}; +static const unsigned int vin3_clk_pins[] = { + RCAR_GP_PIN(1, 23), +}; +static const unsigned int vin3_clk_mux[] = { + VI3_CLK_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync_0), + SH_PFC_PIN_GROUP(du_sync_1), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du2_clk_in), + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_data_c), + SH_PFC_PIN_GROUP(hscif0_ctrl_c), + SH_PFC_PIN_GROUP(hscif0_data_d), + SH_PFC_PIN_GROUP(hscif0_ctrl_d), + SH_PFC_PIN_GROUP(hscif0_data_e), + SH_PFC_PIN_GROUP(hscif0_ctrl_e), + SH_PFC_PIN_GROUP(hscif0_data_f), + SH_PFC_PIN_GROUP(hscif0_ctrl_f), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c2_e), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(iic0), + SH_PFC_PIN_GROUP(iic1), + SH_PFC_PIN_GROUP(iic1_b), + SH_PFC_PIN_GROUP(iic1_c), + SH_PFC_PIN_GROUP(iic2), + SH_PFC_PIN_GROUP(iic2_b), + SH_PFC_PIN_GROUP(iic2_c), + SH_PFC_PIN_GROUP(iic2_d), + SH_PFC_PIN_GROUP(iic2_e), + SH_PFC_PIN_GROUP(iic3), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_rx), + SH_PFC_PIN_GROUP(msiof3_tx), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_rx_b), + SH_PFC_PIN_GROUP(msiof3_tx_b), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_clk_d), + SH_PFC_PIN_GROUP(scif1_data_e), + SH_PFC_PIN_GROUP(scif1_clk_e), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa0_clk_b), + SH_PFC_PIN_GROUP(scifa0_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa1_clk_c), + SH_PFC_PIN_GROUP(scifa1_ctrl_c), + SH_PFC_PIN_GROUP(scifa1_data_d), + SH_PFC_PIN_GROUP(scifa1_clk_d), + SH_PFC_PIN_GROUP(scifa1_ctrl_d), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa2_data_c), + SH_PFC_PIN_GROUP(scifa2_clk_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_ctrl_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb1_data_e), + SH_PFC_PIN_GROUP(scifb1_clk_e), + SH_PFC_PIN_GROUP(scifb1_data_f), + SH_PFC_PIN_GROUP(scifb1_data_g), + SH_PFC_PIN_GROUP(scifb1_clk_g), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi0129_ctrl), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5), + SH_PFC_PIN_GROUP(ssi5_b), + SH_PFC_PIN_GROUP(ssi5_c), + SH_PFC_PIN_GROUP(ssi6), + SH_PFC_PIN_GROUP(ssi6_b), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi7_b_data), + SH_PFC_PIN_GROUP(ssi7_c_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi78_b_ctrl), + SH_PFC_PIN_GROUP(ssi78_c_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi8_b_data), + SH_PFC_PIN_GROUP(ssi8_c_data), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_ctrl), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc_vbus), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + VIN_DATA_PIN_GROUP(vin0_data, 4), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 24), + VIN_DATA_PIN_GROUP(vin1_data, 20), + SH_PFC_PIN_GROUP(vin1_data18), + VIN_DATA_PIN_GROUP(vin1_data, 16), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + VIN_DATA_PIN_GROUP(vin1_data, 4), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin2_data, 24), + SH_PFC_PIN_GROUP(vin2_data18), + VIN_DATA_PIN_GROUP(vin2_data, 16), + VIN_DATA_PIN_GROUP(vin2_data, 8), + VIN_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), + SH_PFC_PIN_GROUP(vin3_data8), + SH_PFC_PIN_GROUP(vin3_sync), + SH_PFC_PIN_GROUP(vin3_field), + SH_PFC_PIN_GROUP(vin3_clkenb), + SH_PFC_PIN_GROUP(vin3_clk), +}; + +static const char * const audio_clk_groups[] = { + "audio_clk_a", + "audio_clk_b", + "audio_clk_c", + "audio_clkout", + "audio_clkout_b", + "audio_clkout_c", + "audio_clkout_d", +}; + +static const char * const du_groups[] = { + "du_rgb666", + "du_rgb888", + "du_clk_out_0", + "du_clk_out_1", + "du_sync_0", + "du_sync_1", + "du_cde", +}; + +static const char * const du0_groups[] = { + "du0_clk_in", +}; + +static const char * const du1_groups[] = { + "du1_clk_in", +}; + +static const char * const du2_groups[] = { + "du2_clk_in", +}; + +static const char * const eth_groups[] = { + "eth_link", + "eth_magic", + "eth_mdio", + "eth_rmii", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", + "hscif0_data_b", + "hscif0_ctrl_b", + "hscif0_data_c", + "hscif0_ctrl_c", + "hscif0_data_d", + "hscif0_ctrl_d", + "hscif0_data_e", + "hscif0_ctrl_e", + "hscif0_data_f", + "hscif0_ctrl_f", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const i2c0_groups[] = { + "i2c0", +}; + +static const char * const i2c1_groups[] = { + "i2c1", + "i2c1_b", + "i2c1_c", +}; + +static const char * const i2c2_groups[] = { + "i2c2", + "i2c2_b", + "i2c2_c", + "i2c2_d", + "i2c2_e", +}; + +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const iic0_groups[] = { + "iic0", +}; + +static const char * const iic1_groups[] = { + "iic1", + "iic1_b", + "iic1_c", +}; + +static const char * const iic2_groups[] = { + "iic2", + "iic2_b", + "iic2_c", + "iic2_d", + "iic2_e", +}; + +static const char * const iic3_groups[] = { + "iic3", +}; + +static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq1", + "intc_irq2", + "intc_irq3", +}; + +static const char * const mmc0_groups[] = { + "mmc0_data1", + "mmc0_data4", + "mmc0_data8", + "mmc0_ctrl", +}; + +static const char * const mmc1_groups[] = { + "mmc1_data1", + "mmc1_data4", + "mmc1_data8", + "mmc1_ctrl", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_rx", + "msiof0_tx", + "msiof0_clk_b", + "msiof0_ss1_b", + "msiof0_ss2_b", + "msiof0_rx_b", + "msiof0_tx_b", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_rx", + "msiof1_tx", + "msiof1_clk_b", + "msiof1_ss1_b", + "msiof1_ss2_b", + "msiof1_rx_b", + "msiof1_tx_b", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_rx", + "msiof2_tx", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk", + "msiof3_sync", + "msiof3_ss1", + "msiof3_ss2", + "msiof3_rx", + "msiof3_tx", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_rx_b", + "msiof3_tx_b", +}; + +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", + "scif0_data_b", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_ctrl", + "scif1_data_b", + "scif1_data_c", + "scif1_data_d", + "scif1_clk_d", + "scif1_data_e", + "scif1_clk_e", +}; + +static const char * const scif2_groups[] = { + "scif2_data", + "scif2_clk", + "scif2_data_b", +}; + +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", + "scifa0_data_b", + "scifa0_clk_b", + "scifa0_ctrl_b", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", + "scifa1_data_b", + "scifa1_clk_b", + "scifa1_ctrl_b", + "scifa1_data_c", + "scifa1_clk_c", + "scifa1_ctrl_c", + "scifa1_data_d", + "scifa1_clk_d", + "scifa1_ctrl_d", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk", + "scifa2_ctrl", + "scifa2_data_b", + "scifa2_data_c", + "scifa2_clk_c", +}; + +static const char * const scifb0_groups[] = { + "scifb0_data", + "scifb0_clk", + "scifb0_ctrl", + "scifb0_data_b", + "scifb0_clk_b", + "scifb0_ctrl_b", + "scifb0_data_c", +}; + +static const char * const scifb1_groups[] = { + "scifb1_data", + "scifb1_clk", + "scifb1_ctrl", + "scifb1_data_b", + "scifb1_clk_b", + "scifb1_ctrl_b", + "scifb1_data_c", + "scifb1_data_d", + "scifb1_data_e", + "scifb1_clk_e", + "scifb1_data_f", + "scifb1_data_g", + "scifb1_clk_g", +}; + +static const char * const scifb2_groups[] = { + "scifb2_data", + "scifb2_clk", + "scifb2_ctrl", + "scifb2_data_b", + "scifb2_clk_b", + "scifb2_ctrl_b", + "scifb2_data_c", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", +}; + +static const char * const ssi_groups[] = { + "ssi0_data", + "ssi0129_ctrl", + "ssi1_data", + "ssi1_ctrl", + "ssi2_data", + "ssi2_ctrl", + "ssi3_data", + "ssi34_ctrl", + "ssi4_data", + "ssi4_ctrl", + "ssi5", + "ssi5_b", + "ssi5_c", + "ssi6", + "ssi6_b", + "ssi7_data", + "ssi7_b_data", + "ssi7_c_data", + "ssi78_ctrl", + "ssi78_b_ctrl", + "ssi78_c_ctrl", + "ssi8_data", + "ssi8_b_data", + "ssi8_c_data", + "ssi9_data", + "ssi9_ctrl", +}; + +static const char * const tpu0_groups[] = { + "tpu0_to0", + "tpu0_to1", + "tpu0_to2", + "tpu0_to3", +}; + +static const char * const usb0_groups[] = { + "usb0", + "usb0_ovc_vbus", +}; + +static const char * const usb1_groups[] = { + "usb1", +}; + +static const char * const usb2_groups[] = { + "usb2", +}; + +static const char * const vin0_groups[] = { + "vin0_data24", + "vin0_data20", + "vin0_data18", + "vin0_data16", + "vin0_data12", + "vin0_data10", + "vin0_data8", + "vin0_data4", + "vin0_sync", + "vin0_field", + "vin0_clkenb", + "vin0_clk", +}; + +static const char * const vin1_groups[] = { + "vin1_data24", + "vin1_data20", + "vin1_data18", + "vin1_data16", + "vin1_data12", + "vin1_data10", + "vin1_data8", + "vin1_data4", + "vin1_sync", + "vin1_field", + "vin1_clkenb", + "vin1_clk", +}; + +static const char * const vin2_groups[] = { + "vin2_data24", + "vin2_data18", + "vin2_data16", + "vin2_data8", + "vin2_data4", + "vin2_sync", + "vin2_field", + "vin2_clkenb", + "vin2_clk", +}; + +static const char * const vin3_groups[] = { + "vin3_data8", + "vin3_sync", + "vin3_field", + "vin3_clkenb", + "vin3_clk", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(du2), + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(iic0), + SH_PFC_FUNCTION(iic1), + SH_PFC_FUNCTION(iic2), + SH_PFC_FUNCTION(iic3), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tpu0), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP3_17_15, + GP_0_30_FN, FN_IP3_14_12, + GP_0_29_FN, FN_IP3_11_8, + GP_0_28_FN, FN_IP3_7_4, + GP_0_27_FN, FN_IP3_3_0, + GP_0_26_FN, FN_IP2_28_26, + GP_0_25_FN, FN_IP2_25_22, + GP_0_24_FN, FN_IP2_21_18, + GP_0_23_FN, FN_IP2_17_15, + GP_0_22_FN, FN_IP2_14_12, + GP_0_21_FN, FN_IP2_11_9, + GP_0_20_FN, FN_IP2_8_6, + GP_0_19_FN, FN_IP2_5_3, + GP_0_18_FN, FN_IP2_2_0, + GP_0_17_FN, FN_IP1_29_28, + GP_0_16_FN, FN_IP1_27_26, + GP_0_15_FN, FN_IP1_25_22, + GP_0_14_FN, FN_IP1_21_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_12, + GP_0_11_FN, FN_IP1_11_8, + GP_0_10_FN, FN_IP1_7_4, + GP_0_9_FN, FN_IP1_3_0, + GP_0_8_FN, FN_IP0_30_27, + GP_0_7_FN, FN_IP0_26_23, + GP_0_6_FN, FN_IP0_22_20, + GP_0_5_FN, FN_IP0_19_16, + GP_0_4_FN, FN_IP0_15_12, + GP_0_3_FN, FN_IP0_11_9, + GP_0_2_FN, FN_IP0_8_6, + GP_0_1_FN, FN_IP0_5_3, + GP_0_0_FN, FN_IP0_2_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + GP_1_29_FN, FN_IP6_13_11, + GP_1_28_FN, FN_IP6_10_9, + GP_1_27_FN, FN_IP6_8_6, + GP_1_26_FN, FN_IP6_5_3, + GP_1_25_FN, FN_IP6_2_0, + GP_1_24_FN, FN_IP5_29_27, + GP_1_23_FN, FN_IP5_26_24, + GP_1_22_FN, FN_IP5_23_21, + GP_1_21_FN, FN_IP5_20_18, + GP_1_20_FN, FN_IP5_17_15, + GP_1_19_FN, FN_IP5_14_13, + GP_1_18_FN, FN_IP5_12_10, + GP_1_17_FN, FN_IP5_9_6, + GP_1_16_FN, FN_IP5_5_3, + GP_1_15_FN, FN_IP5_2_0, + GP_1_14_FN, FN_IP4_29_27, + GP_1_13_FN, FN_IP4_26_24, + GP_1_12_FN, FN_IP4_23_21, + GP_1_11_FN, FN_IP4_20_18, + GP_1_10_FN, FN_IP4_17_15, + GP_1_9_FN, FN_IP4_14_12, + GP_1_8_FN, FN_IP4_11_9, + GP_1_7_FN, FN_IP4_8_6, + GP_1_6_FN, FN_IP4_5_3, + GP_1_5_FN, FN_IP4_2_0, + GP_1_4_FN, FN_IP3_31_29, + GP_1_3_FN, FN_IP3_28_26, + GP_1_2_FN, FN_IP3_25_23, + GP_1_1_FN, FN_IP3_22_20, + GP_1_0_FN, FN_IP3_19_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_FN, FN_IP7_15_13, + GP_2_28_FN, FN_IP7_12_10, + GP_2_27_FN, FN_IP7_9_8, + GP_2_26_FN, FN_IP7_7_6, + GP_2_25_FN, FN_IP7_5_3, + GP_2_24_FN, FN_IP7_2_0, + GP_2_23_FN, FN_IP6_31_29, + GP_2_22_FN, FN_IP6_28_26, + GP_2_21_FN, FN_IP6_25_23, + GP_2_20_FN, FN_IP6_22_20, + GP_2_19_FN, FN_IP6_19_17, + GP_2_18_FN, FN_IP6_16_14, + GP_2_17_FN, FN_VI1_DATA7_VI1_B7, + GP_2_16_FN, FN_IP8_27, + GP_2_15_FN, FN_IP8_26, + GP_2_14_FN, FN_IP8_25_24, + GP_2_13_FN, FN_IP8_23_22, + GP_2_12_FN, FN_IP8_21_20, + GP_2_11_FN, FN_IP8_19_18, + GP_2_10_FN, FN_IP8_17_16, + GP_2_9_FN, FN_IP8_15_14, + GP_2_8_FN, FN_IP8_13_12, + GP_2_7_FN, FN_IP8_11_10, + GP_2_6_FN, FN_IP8_9_8, + GP_2_5_FN, FN_IP8_7_6, + GP_2_4_FN, FN_IP8_5_4, + GP_2_3_FN, FN_IP8_3_2, + GP_2_2_FN, FN_IP8_1_0, + GP_2_1_FN, FN_IP7_30_29, + GP_2_0_FN, FN_IP7_28_27 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP11_21_18, + GP_3_30_FN, FN_IP11_17_15, + GP_3_29_FN, FN_IP11_14_13, + GP_3_28_FN, FN_IP11_12_11, + GP_3_27_FN, FN_IP11_10_9, + GP_3_26_FN, FN_IP11_8_7, + GP_3_25_FN, FN_IP11_6_5, + GP_3_24_FN, FN_IP11_4, + GP_3_23_FN, FN_IP11_3_0, + GP_3_22_FN, FN_IP10_29_26, + GP_3_21_FN, FN_IP10_25_23, + GP_3_20_FN, FN_IP10_22_19, + GP_3_19_FN, FN_IP10_18_15, + GP_3_18_FN, FN_IP10_14_11, + GP_3_17_FN, FN_IP10_10_7, + GP_3_16_FN, FN_IP10_6_4, + GP_3_15_FN, FN_IP10_3_0, + GP_3_14_FN, FN_IP9_31_28, + GP_3_13_FN, FN_IP9_27_26, + GP_3_12_FN, FN_IP9_25_24, + GP_3_11_FN, FN_IP9_23_22, + GP_3_10_FN, FN_IP9_21_20, + GP_3_9_FN, FN_IP9_19_18, + GP_3_8_FN, FN_IP9_17_16, + GP_3_7_FN, FN_IP9_15_12, + GP_3_6_FN, FN_IP9_11_8, + GP_3_5_FN, FN_IP9_7_6, + GP_3_4_FN, FN_IP9_5_4, + GP_3_3_FN, FN_IP9_3_2, + GP_3_2_FN, FN_IP9_1_0, + GP_3_1_FN, FN_IP8_30_29, + GP_3_0_FN, FN_IP8_28 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP14_18_16, + GP_4_30_FN, FN_IP14_15_12, + GP_4_29_FN, FN_IP14_11_9, + GP_4_28_FN, FN_IP14_8_6, + GP_4_27_FN, FN_IP14_5_3, + GP_4_26_FN, FN_IP14_2_0, + GP_4_25_FN, FN_IP13_30_29, + GP_4_24_FN, FN_IP13_28_26, + GP_4_23_FN, FN_IP13_25_23, + GP_4_22_FN, FN_IP13_22_19, + GP_4_21_FN, FN_IP13_18_16, + GP_4_20_FN, FN_IP13_15_13, + GP_4_19_FN, FN_IP13_12_10, + GP_4_18_FN, FN_IP13_9_7, + GP_4_17_FN, FN_IP13_6_3, + GP_4_16_FN, FN_IP13_2_0, + GP_4_15_FN, FN_IP12_30_28, + GP_4_14_FN, FN_IP12_27_25, + GP_4_13_FN, FN_IP12_24_23, + GP_4_12_FN, FN_IP12_22_20, + GP_4_11_FN, FN_IP12_19_17, + GP_4_10_FN, FN_IP12_16_14, + GP_4_9_FN, FN_IP12_13_11, + GP_4_8_FN, FN_IP12_10_8, + GP_4_7_FN, FN_IP12_7_6, + GP_4_6_FN, FN_IP12_5_4, + GP_4_5_FN, FN_IP12_3_2, + GP_4_4_FN, FN_IP12_1_0, + GP_4_3_FN, FN_IP11_31_30, + GP_4_2_FN, FN_IP11_29_27, + GP_4_1_FN, FN_IP11_26_24, + GP_4_0_FN, FN_IP11_23_22 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP7_24_22, + GP_5_30_FN, FN_IP7_21_19, + GP_5_29_FN, FN_IP7_18_16, + GP_5_28_FN, FN_DU_DOTCLKIN2, + GP_5_27_FN, FN_IP7_26_25, + GP_5_26_FN, FN_DU_DOTCLKIN0, + GP_5_25_FN, FN_AVS2, + GP_5_24_FN, FN_AVS1, + GP_5_23_FN, FN_USB2_OVC, + GP_5_22_FN, FN_USB2_PWEN, + GP_5_21_FN, FN_IP16_7, + GP_5_20_FN, FN_IP16_6, + GP_5_19_FN, FN_USB0_OVC_VBUS, + GP_5_18_FN, FN_USB0_PWEN, + GP_5_17_FN, FN_IP16_5_3, + GP_5_16_FN, FN_IP16_2_0, + GP_5_15_FN, FN_IP15_29_28, + GP_5_14_FN, FN_IP15_27_26, + GP_5_13_FN, FN_IP15_25_23, + GP_5_12_FN, FN_IP15_22_20, + GP_5_11_FN, FN_IP15_19_18, + GP_5_10_FN, FN_IP15_17_16, + GP_5_9_FN, FN_IP15_15_14, + GP_5_8_FN, FN_IP15_13_12, + GP_5_7_FN, FN_IP15_11_9, + GP_5_6_FN, FN_IP15_8_6, + GP_5_5_FN, FN_IP15_5_3, + GP_5_4_FN, FN_IP15_2_0, + GP_5_3_FN, FN_IP14_30_28, + GP_5_2_FN, FN_IP14_27_25, + GP_5_1_FN, FN_IP14_24_22, + GP_5_0_FN, FN_IP14_21_19 } + }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, + 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { + /* IP0_31 [1] */ + 0, 0, + /* IP0_30_27 [4] */ + FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_26_23 [4] */ + FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, + FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_22_20 [3] */ + FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, + FN_I2C2_SCL_C, 0, 0, + /* IP0_19_16 [4] */ + FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, + FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_15_12 [4] */ + FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, + FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_11_9 [3] */ + FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, + 0, 0, 0, + /* IP0_8_6 [3] */ + FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, + 0, 0, 0, + /* IP0_5_3 [3] */ + FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, + 0, 0, 0, + /* IP0_2_0 [3] */ + FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, + 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { + /* IP1_31_30 [2] */ + 0, 0, 0, 0, + /* IP1_29_28 [2] */ + FN_A1, FN_PWM4, 0, 0, + /* IP1_27_26 [2] */ + FN_A0, FN_PWM3, 0, 0, + /* IP1_25_22 [4] */ + FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, + FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_21_18 [4] */ + FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, + FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_17_15 [3] */ + FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, + FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, + 0, 0, 0, + /* IP1_14_12 [3] */ + FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, + FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, + 0, 0, + /* IP1_11_8 [4] */ + FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, + FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_7_4 [4] */ + FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, + FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_3_0 [4] */ + FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, + FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, + 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { + /* IP2_31_29 [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_28_26 [3] */ + FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, + FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, + /* IP2_25_22 [4] */ + FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, + FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_21_18 [4] */ + FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, + FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_17_15 [3] */ + FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, + 0, 0, 0, 0, + /* IP2_14_12 [3] */ + FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, + /* IP2_11_9 [3] */ + FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, + /* IP2_8_6 [3] */ + FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, + /* IP2_5_3 [3] */ + FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, + /* IP2_2_0 [3] */ + FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, + 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { + /* IP3_31_29 [3] */ + FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, + 0, 0, 0, + /* IP3_28_26 [3] */ + FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, + 0, 0, 0, 0, + /* IP3_25_23 [3] */ + FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, + /* IP3_22_20 [3] */ + FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, + /* IP3_19_18 [2] */ + FN_A16, FN_ATAWR1_N, 0, 0, + /* IP3_17_15 [3] */ + FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, + 0, 0, 0, 0, + /* IP3_14_12 [3] */ + FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, + 0, 0, 0, 0, + /* IP3_11_8 [4] */ + FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, + FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, + FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_7_4 [4] */ + FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, + FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_3_0 [4] */ + FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, + FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, + 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, + 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP4_31_30 [2] */ + 0, 0, 0, 0, + /* IP4_29_27 [3] */ + FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, + FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, + /* IP4_26_24 [3] */ + FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, + FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, + /* IP4_23_21 [3] */ + FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, + FN_HTX0_B, FN_MSIOF0_SS1_B, 0, + /* IP4_20_18 [3] */ + FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, + FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, + /* IP4_17_15 [3] */ + FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, + 0, 0, 0, + /* IP4_14_12 [3] */ + FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, + FN_VI2_FIELD_B, 0, 0, + /* IP4_11_9 [3] */ + FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, + FN_VI2_CLKENB_B, 0, 0, + /* IP4_8_6 [3] */ + FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, + /* IP4_5_3 [3] */ + FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, + /* IP4_2_0 [3] */ + FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, + 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { + /* IP5_31_30 [2] */ + 0, 0, 0, 0, + /* IP5_29_27 [3] */ + FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, + FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, + /* IP5_26_24 [3] */ + FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, + FN_MSIOF0_SCK_B, 0, + /* IP5_23_21 [3] */ + FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, + FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, + /* IP5_20_18 [3] */ + FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, + /* IP5_17_15 [3] */ + FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, + FN_INTC_IRQ4_N, 0, 0, + /* IP5_14_13 [2] */ + FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, + /* IP5_12_10 [3] */ + FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, + 0, 0, + /* IP5_9_6 [4] */ + FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, + FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, + FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, + /* IP5_5_3 [3] */ + FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, + FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, + FN_INTC_EN0_N, FN_I2C1_SCL, + /* IP5_2_0 [3] */ + FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, + FN_VI2_R3, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + /* IP6_31_29 [3] */ + FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, + /* IP6_28_26 [3] */ + FN_ETH_LINK, 0, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, + /* IP6_25_23 [3] */ + FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, + /* IP6_22_20 [3] */ + FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, + FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, + /* IP6_19_17 [3] */ + FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, + FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, + /* IP6_16_14 [3] */ + FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, + FN_I2C2_SCL_E, 0, + /* IP6_13_11 [3] */ + FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + /* IP6_10_9 [2] */ + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, + /* IP6_8_6 [3] */ + FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, + FN_SSI_SDATA8_C, 0, 0, 0, + /* IP6_5_3 [3] */ + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, + /* IP6_2_0 [3] */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { + /* IP7_31 [1] */ + 0, 0, + /* IP7_30_29 [2] */ + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, + /* IP7_28_27 [2] */ + FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, + /* IP7_26_25 [2] */ + FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, + /* IP7_24_22 [3] */ + FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, + 0, 0, 0, + /* IP7_21_19 [3] */ + FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, + FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, + /* IP7_18_16 [3] */ + FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, 0, 0, 0, + /* IP7_15_13 [3] */ + FN_ETH_MDC, 0, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, + /* IP7_12_10 [3] */ + FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, + FN_GLO_SCLK_C, 0, 0, 0, + /* IP7_9_8 [2] */ + FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, + /* IP7_7_6 [2] */ + FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, + /* IP7_5_3 [3] */ + FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, + /* IP7_2_0 [3] */ + FN_ETH_MDIO, 0, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2) { + /* IP8_31 [1] */ + 0, 0, + /* IP8_30_29 [2] */ + FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, + /* IP8_28 [1] */ + FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, + /* IP8_27 [1] */ + FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, + /* IP8_26 [1] */ + FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, + /* IP8_25_24 [2] */ + FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, + FN_AVB_MAGIC, 0, + /* IP8_23_22 [2] */ + FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, + /* IP8_21_20 [2] */ + FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, + /* IP8_19_18 [2] */ + FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, + /* IP8_17_16 [2] */ + FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, + /* IP8_15_14 [2] */ + FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, + /* IP8_13_12 [2] */ + FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, + /* IP8_11_10 [2] */ + FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, + /* IP8_9_8 [2] */ + FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, + /* IP8_7_6 [2] */ + FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, + /* IP8_5_4 [2] */ + FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, + /* IP8_3_2 [2] */ + FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, + /* IP8_1_0 [2] */ + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, + 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { + /* IP9_31_28 [4] */ + FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, + FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, + FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, + /* IP9_27_26 [2] */ + FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, + /* IP9_25_24 [2] */ + FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, + /* IP9_23_22 [2] */ + FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, + /* IP9_21_20 [2] */ + FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, + /* IP9_19_18 [2] */ + FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, + /* IP9_17_16 [2] */ + FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, + /* IP9_15_12 [4] */ + FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, + FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_11_8 [4] */ + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, + FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_7_6 [2] */ + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, + /* IP9_5_4 [2] */ + FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, + /* IP9_3_2 [2] */ + FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, + /* IP9_1_0 [2] */ + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, + 2, 4, 3, 4, 4, 4, 4, 3, 4) { + /* IP10_31_30 [2] */ + 0, 0, 0, 0, + /* IP10_29_26 [4] */ + FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, + FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, + FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, + /* IP10_25_23 [3] */ + FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, + FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, + /* IP10_22_19 [4] */ + FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, + /* IP10_18_15 [4] */ + FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, + 0, 0, 0, 0, 0, 0, + /* IP10_14_11 [4] */ + FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, + FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, + FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, + 0, 0, 0, 0, 0, 0, 0, + /* IP10_10_7 [4] */ + FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, + FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, + FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, + 0, 0, 0, 0, 0, 0, 0, + /* IP10_6_4 [3] */ + FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, + FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, + FN_VI3_DATA0_B, 0, + /* IP10_3_0 [4] */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, + FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, + FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { + /* IP11_31_30 [2] */ + FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, + /* IP11_29_27 [3] */ + FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + 0, 0, 0, + /* IP11_26_24 [3] */ + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, + 0, 0, 0, + /* IP11_23_22 [2] */ + FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, + /* IP11_21_18 [4] */ + FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0, + /* IP11_17_15 [3] */ + FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, + /* IP11_14_13 [2] */ + FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, + /* IP11_12_11 [2] */ + FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, + /* IP11_10_9 [2] */ + FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, + /* IP11_8_7 [2] */ + FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, + /* IP11_6_5 [2] */ + FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, + /* IP11_4 [1] */ + FN_SD3_CLK, FN_MMC1_CLK, + /* IP11_3_0 [4] */ + FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, + FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + /* IP12_31 [1] */ + 0, 0, + /* IP12_30_28 [3] */ + FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, + FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, + FN_CAN_DEBUGOUT4, 0, 0, + /* IP12_27_25 [3] */ + FN_SSI_SCK5, FN_SCIFB1_SCK, + FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, + FN_CAN_DEBUGOUT3, 0, 0, + /* IP12_24_23 [2] */ + FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, + FN_CAN_DEBUGOUT2, + /* IP12_22_20 [3] */ + FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, + FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, + /* IP12_19_17 [3] */ + FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, + FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, + /* IP12_16_14 [3] */ + FN_SSI_SDATA3, FN_STP_ISCLK_0, + FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, + /* IP12_13_11 [3] */ + FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, + FN_CAN_STEP0, 0, 0, 0, + /* IP12_10_8 [3] */ + FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, + FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, + /* IP12_7_6 [2] */ + FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, + /* IP12_5_4 [2] */ + FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, + /* IP12_3_2 [2] */ + FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, + /* IP12_1_0 [2] */ + FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, + 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { + /* IP13_31 [1] */ + 0, 0, + /* IP13_30_29 [2] */ + FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, + /* IP13_28_26 [3] */ + FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, + FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, + /* IP13_25_23 [3] */ + FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, + FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, + /* IP13_22_19 [4] */ + FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, + FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, + 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0, + /* IP13_18_16 [3] */ + FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, + FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, + /* IP13_15_13 [3] */ + FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, + FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, + /* IP13_12_10 [3] */ + FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5, + FN_CAN_DEBUGOUT8, 0, 0, + /* IP13_9_7 [3] */ + FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, + FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, + /* IP13_6_3 [4] */ + FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0, + FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, + FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_2_0 [3] */ + FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, + FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, + 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { + /* IP14_30 [1] */ + 0, 0, + /* IP14_30_28 [3] */ + FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, + FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, + FN_HRTS0_N_C, 0, + /* IP14_27_25 [3] */ + FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, + FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, + /* IP14_24_22 [3] */ + FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, + FN_LCDOUT9, 0, 0, 0, + /* IP14_21_19 [3] */ + FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, + FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, + /* IP14_18_16 [3] */ + FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, + /* IP14_15_12 [4] */ + FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, + FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, + 0, 0, 0, 0, 0, 0, 0, + /* IP14_11_9 [3] */ + FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, + 0, 0, 0, + /* IP14_8_6 [3] */ + FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, + 0, 0, 0, + /* IP14_5_3 [3] */ + FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, + FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, + /* IP14_2_0 [3] */ + FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, + FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, + FN_REMOCON, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, + 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { + /* IP15_31_30 [2] */ + 0, 0, 0, 0, + /* IP15_29_28 [2] */ + FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, + /* IP15_27_26 [2] */ + FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, + /* IP15_25_23 [3] */ + FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, + FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0, + /* IP15_22_20 [3] */ + FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, + FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, + /* IP15_19_18 [2] */ + FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, + /* IP15_17_16 [2] */ + FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, + /* IP15_15_14 [2] */ + FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, + /* IP15_13_12 [2] */ + FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, + /* IP15_11_9 [3] */ + FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, + 0, 0, 0, + /* IP15_8_6 [3] */ + FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, + FN_IIC2_SDA, FN_I2C2_SDA, 0, + /* IP15_5_3 [3] */ + FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, + FN_IIC2_SCL, FN_I2C2_SCL, 0, + /* IP15_2_0 [3] */ + FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, + 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { + /* IP16_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_19_16 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_15_12 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_11_8 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_7 [1] */ + FN_USB1_OVC, FN_TCLK1_B, + /* IP16_6 [1] */ + FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, + /* IP16_5_3 [3] */ + FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, + FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, + /* IP16_2_0 [3] */ + FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, + 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { + /* SEL_SCIF1 [3] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, 0, 0, 0, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, + FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, + FN_SEL_SCIFB1_6, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SCIFA1_3, + /* SEL_SCIF0 [1] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + /* SEL_SCIFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_SOF1 [1] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + /* SEL_SSI7 [2] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, + /* SEL_SSI6 [1] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + /* SEL_SSI5 [2] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, + /* SEL_VI3 [1] */ + FN_SEL_VI3_0, FN_SEL_VI3_1, + /* SEL_VI2 [1] */ + FN_SEL_VI2_0, FN_SEL_VI2_1, + /* SEL_VI1 [1] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, + /* SEL_VI0 [1] */ + FN_SEL_VI0_0, FN_SEL_VI0_1, + /* SEL_TSIF1 [2] */ + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, + /* RESERVED [1] */ + 0, 0, + /* SEL_LBS [1] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF3 [1] */ + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + /* SEL_SOF0 [1] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 1, 2, 1, 2, 1, 2, + 1, 1, 1, 3, 3, 2, 3, 2, 2) { + /* RESERVED [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* SEL_TMU1 [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_SCIFCLK [1] */ + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* SEL_CANCLK [1] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + /* SEL_SCIFA2 [2] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, + /* SEL_CAN1 [1] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_SCIF2 [1] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_SSP [1] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, + /* SEL_HSCIF0 [3] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, + /* RESERVED [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* SEL_SIM [2] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, + /* SEL_SSI8 [2] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 1, 1, 2, 4, 4, 2, 2, + 4, 2, 3, 2, 3, 2) { + /* SEL_IICDVFS [1] */ + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + /* SEL_IIC0 [1] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [3] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, 0, 0, 0, + /* SEL_IIC1 [2] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, + /* SEL_I2C2 [3] */ + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, 0, 0, 0, + /* SEL_I2C1 [2] */ + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7790_pinmux_info = { + .name = "r8a77900_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c new file mode 100644 index 00000000000..2e688dc4a3c --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -0,0 +1,5771 @@ +/* + * r8a7791 processor support - PFC hardware block. + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_data/gpio-rcar.h> + +#include "core.h" +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx), \ + PORT_GP_32(6, fn, sfx), \ + PORT_GP_32(7, fn, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, + FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, + FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, + FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, + FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, + FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, + + /* GPSR1 */ + FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, + FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, + FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, + FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, + FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, + FN_IP3_21_20, + + /* GPSR2 */ + FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, + FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, + FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, + FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, + FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, + FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, + FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, + FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, + FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, + FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, + FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, + FN_IP9_18_17, + + /* GPSR4 */ + FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, + FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2, + FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5, + FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, + FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, + FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, + FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, + + /* GPSR5 */ + FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, + FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, + FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, + FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, + FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, + FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, + + /* GPSR6 */ + FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, + FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, + FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK, + FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, + FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, + FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, + FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, + FN_USB1_OVC, FN_DU0_DOTCLKIN, + + /* GPSR7 */ + FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, + FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, + FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, + FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, + FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, + FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, + + /* IPSR0 */ + FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8, + FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15, + FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B, + FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B, + FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B, + FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK, + + /* IPSR1 */ + FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0, + FN_A9, FN_MSIOF1_SS2, FN_SDA0, + FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D, + FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D, + FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D, + FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, + FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, + FN_A15, FN_BPFCLK_C, + FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B, + FN_A17, FN_DACK2_B, FN_SDA0_C, + FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C, + + /* IPSR2 */ + FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B, + FN_A20, FN_SPCLK, + FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, + FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, + FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, + FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, + FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, + FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, + FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, + FN_EX_CS1_N, FN_MSIOF2_SCK, + FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, + FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1, + + /* IPSR3 */ + FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2, + FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, + FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, + FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, + FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, + FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, + FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, + FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, + FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, + FN_DREQ0, FN_PWM3, FN_TPU_TO3, + FN_DACK0, FN_DRACK0, FN_REMOCON, + FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, + FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, + FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, + FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, + + /* IPSR4 */ + FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, + FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D, + FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, + FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C, + FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, + FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E, + FN_GLO_Q1_D, FN_HCTS1_N_E, + FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, + FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3, + FN_SSI_SCK4, FN_GLO_SS_D, + FN_SSI_WS4, FN_GLO_RFON_D, + FN_SSI_SDATA4, FN_MSIOF2_SCK_D, + FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, + FN_MSIOF2_SYNC_D, FN_VI1_R2_B, + + /* IPSR5 */ + FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, + FN_MSIOF2_TXD_D, FN_VI1_R3_B, + FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, + FN_MSIOF2_SS1_D, FN_VI1_R4_B, + FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, + FN_MSIOF2_RXD_D, FN_VI1_R5_B, + FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, + FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, + FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, + FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, + FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, + FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, + FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, + FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, + FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, + + /* IPSR6 */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, + FN_SCIF_CLK, FN_BPFCLK_E, + FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, + FN_SCIFA2_RXD, FN_FMIN_E, + FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, + FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, + FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, + FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, + FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, + FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E, + FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, + FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, + + /* IPSR7 */ + FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, + FN_SCIF_CLK_B, FN_GPS_MAG_D, + FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, + FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, + FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, + FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, + FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, + FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, + FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, + FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, + FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, + FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, + FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, + FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, + FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, + FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, + FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, + FN_SCIFA1_SCK, FN_SSI_SCK78_B, + + /* IPSR8 */ + FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B, + FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, + FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, + FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, + FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, + FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, + FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, + FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, + FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, + FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, + FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, + FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, + FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, + FN_SCIFA2_SCK, FN_SSI_SDATA9_B, + FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, + FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, + FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, + + /* IPSR9 */ + FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD, + FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK, + FN_DU1_DOTCLKIN, FN_QSTVA_QVS, + FN_DU1_DOTCLKOUT0, FN_QCLK, + FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, + FN_TX3_B, FN_SCL2_B, FN_PWM4, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, + FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_CAN0_RX, FN_RX3_B, FN_SDA2_B, + FN_DU1_DISP, FN_QPOLA, + FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, + FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, + FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, + FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, + FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, + FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, + FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4, + FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, + + /* IPSR10 */ + FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4, + FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, + FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B, + FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, + FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B, + FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, + FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, + FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, + FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, + FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, + FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, + FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, + FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, + FN_TS_SDATA0_C, FN_ATACS11_N, + FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, + FN_TS_SCK0_C, FN_ATAG1_N, + FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, + FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, + FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D, + + /* IPSR11 */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, + FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, + FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, + FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, + FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, + FN_VI1_DATA7, FN_AVB_MDC, + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, + + /* IPSR12 */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E, + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + + /* IPSR13 */ + FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, + FN_ADICLK_B, FN_MSIOF0_SS1_C, + FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, + FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, + FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, + FN_ADICHS2_B, FN_MSIOF0_TXD_C, + FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B, + FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B, + FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B, + FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, + FN_SCIFA5_TXD_B, FN_TX3_C, + FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, + FN_SCIFA5_RXD_B, FN_RX3_C, + FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B, + FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B, + FN_SD1_DATA3, FN_IERX_B, + FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, + + /* IPSR14 */ + FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, + FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD, + FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1, + FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3, + FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, + FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, + FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B, + FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B, + FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B, + FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B, + FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, + FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, + FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, + FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, + + /* IPSR15 */ + FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, + FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, + FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, + FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, + FN_PWM5_B, FN_SCIFA3_TXD_C, + FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, + FN_VI1_G6_B, FN_SCIFA3_RXD_C, + FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, + FN_VI1_G7_B, FN_SCIFA3_SCK_C, + FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C, + FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C, + FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK, + FN_TCLK2, FN_VI1_DATA3_C, + FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C, + FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C, + + /* IPSR16 */ + FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, + FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, + FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, + FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, + FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, + + /* MOD_SEL */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_QSP_0, FN_SEL_QSP_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, + FN_SEL_HSCIF1_4, + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, + + /* MOD_SEL2 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF0_4, + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, + FN_SEL_SIM_0, FN_SEL_SIM_1, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + + /* MOD_SEL3 */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_MMC_0, FN_SEL_MMC_1, + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, + + /* MOD_SEL4 */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, + FN_SEL_RAD_0, FN_SEL_RAD_1, + FN_SEL_RCN_0, FN_SEL_RCN_1, + FN_SEL_RSP_0, FN_SEL_RSP_1, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, + FN_SEL_SCIF2_4, + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, + FN_SEL_SOF2_4, + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + EX_CS0_N_MARK, RD_N_MARK, + + AUDIO_CLKA_MARK, + + VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + + SD1_CLK_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, + DU0_DOTCLKIN_MARK, + + /* IPSR0 */ + D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, + D6_MARK, D7_MARK, D8_MARK, + D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK, + A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK, + A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK, + A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK, + A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK, + + /* IPSR1 */ + A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK, + A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK, + A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK, + A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK, + A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK, + A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK, + A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK, + A15_MARK, BPFCLK_C_MARK, + A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK, + A17_MARK, DACK2_B_MARK, SDA0_C_MARK, + A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK, + + /* IPSR2 */ + A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK, + SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK, + A20_MARK, SPCLK_MARK, + A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK, + A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK, + A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK, + A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK, + A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK, + RX1_MARK, SCIFA1_RXD_MARK, + CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK, + CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK, + EX_CS1_N_MARK, MSIOF2_SCK_MARK, + EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK, + EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK, + ATAG0_N_MARK, EX_WAIT1_MARK, + + /* IPSR3 */ + EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK, + EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK, + SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK, + BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK, + SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK, + RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK, + SCIFB0_RXD_B_MARK, DREQ1_D_MARK, + WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK, + WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK, + EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK, + DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK, + DACK0_MARK, DRACK0_MARK, REMOCON_MARK, + SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK, + SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK, + SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK, + SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK, + SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK, + SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK, + + /* IPSR4 */ + SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK, + SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK, + MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK, + SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK, + MSIOF2_TXD_C_MARK, GLO_I1_D_MARK, + SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK, + SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK, + SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK, + GLO_Q1_D_MARK, HCTS1_N_E_MARK, + SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK, + SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK, + SSI_SCK4_MARK, GLO_SS_D_MARK, + SSI_WS4_MARK, GLO_RFON_D_MARK, + SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK, + SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK, + MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK, + + /* IPSR5 */ + SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK, + MSIOF2_TXD_D_MARK, VI1_R3_B_MARK, + SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK, + MSIOF2_SS1_D_MARK, VI1_R4_B_MARK, + SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK, + MSIOF2_RXD_D_MARK, VI1_R5_B_MARK, + SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK, + SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK, + SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK, + SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK, + SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK, + SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK, + SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK, + SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK, + SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK, + + /* IPSR6 */ + AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, + SCIF_CLK_MARK, BPFCLK_E_MARK, + AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, + SCIFA2_RXD_MARK, FMIN_E_MARK, + AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, + IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, + IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, + IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, + IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, + IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK, + MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, + IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK, + IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, + SDA1_E_MARK, MSIOF2_SYNC_E_MARK, + IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK, + GPS_CLK_C_MARK, GPS_CLK_D_MARK, + IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK, + GPS_SIGN_C_MARK, GPS_SIGN_D_MARK, + + /* IPSR7 */ + IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK, + SCIF_CLK_B_MARK, GPS_MAG_D_MARK, + DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK, + SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK, + DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK, + SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK, + DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK, + DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK, + DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK, + DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK, + DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK, + DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK, + DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK, + SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK, + DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK, + SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK, + DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK, + SCIFA1_SCK_MARK, SSI_SCK78_B_MARK, + + /* IPSR8 */ + DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK, + DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK, + SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK, + DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK, + SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK, + DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK, + SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK, + DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK, + SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK, + DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK, + SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK, + DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK, + SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK, + DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK, + SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK, + DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK, + DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK, + DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK, + + /* IPSR9 */ + DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK, + DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK, + SCIF3_SCK_MARK, SCIFA3_SCK_MARK, + DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK, + DU1_DOTCLKOUT0_MARK, QCLK_MARK, + DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK, + TX3_B_MARK, SCL2_B_MARK, PWM4_MARK, + DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK, + DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK, + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, + CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK, + DU1_DISP_MARK, QPOLA_MARK, + DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK, + VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK, + VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK, + VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK, + VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK, + VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK, + VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK, + HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK, + + /* IPSR10 */ + VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK, + HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK, + VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK, + HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK, + VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK, + HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK, + VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK, + HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK, + VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK, + CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK, + VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK, + VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK, + VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK, + TS_SDATA0_C_MARK, ATACS11_N_MARK, + VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK, + TS_SCK0_C_MARK, ATAG1_N_MARK, + VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK, + VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK, + VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK, + + /* IPSR11 */ + VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK, + VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK, + VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, + SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, + VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, + TX4_B_MARK, SCIFA4_TXD_B_MARK, + VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, + RX4_B_MARK, SCIFA4_RXD_B_MARK, + VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, + VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, + VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, + VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, + VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, + VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, + VI1_DATA7_MARK, AVB_MDC_MARK, + ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK, + ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK, + + /* IPSR12 */ + ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK, + ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK, + ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, + SCL2_D_MARK, MSIOF1_RXD_E_MARK, + ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, + SDA2_D_MARK, MSIOF1_SCK_E_MARK, + ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, + CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, + ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, + CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, + ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, + ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, + ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, + ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, + STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, + ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, + STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, + ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, + + /* IPSR13 */ + STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK, + ADICLK_B_MARK, MSIOF0_SS1_C_MARK, + STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK, + STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK, + STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK, + ADICHS2_B_MARK, MSIOF0_TXD_C_MARK, + SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK, + SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK, + SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK, + SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK, + SCIFA5_TXD_B_MARK, TX3_C_MARK, + SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK, + SCIFA5_RXD_B_MARK, RX3_C_MARK, + SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK, + SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK, + SD1_DATA3_MARK, IERX_B_MARK, + SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK, + + /* IPSR14 */ + SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK, + SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK, + SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK, + SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK, + SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK, + SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK, + MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK, + VI1_CLK_C_MARK, VI1_G0_B_MARK, + MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK, + VI1_CLKENB_C_MARK, VI1_G1_B_MARK, + MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK, + MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK, + MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK, + VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK, + MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK, + VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK, + + /* IPSR15 */ + SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK, + SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK, + SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK, + GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK, + PWM5_B_MARK, SCIFA3_TXD_C_MARK, + GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK, + VI1_G6_B_MARK, SCIFA3_RXD_C_MARK, + GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK, + VI1_G7_B_MARK, SCIFA3_SCK_C_MARK, + HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK, + TCLK1_MARK, VI1_DATA1_C_MARK, + HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK, + HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK, + TCLK2_MARK, VI1_DATA3_C_MARK, + HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK, + CAN0_RX_B_MARK, VI1_DATA4_C_MARK, + HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK, + CAN0_TX_B_MARK, VI1_DATA5_C_MARK, + + /* IPSR16 */ + HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK, + GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, + HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, + GLO_SS_C_MARK, VI1_DATA7_C_MARK, + HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK, + HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, + HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, + PINMUX_MARK_END, +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N), + PINMUX_DATA(RD_N_MARK, FN_RD_N), + PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), + PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK), + PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0), + PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1), + PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2), + PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4), + PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5), + PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6), + PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), + PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), + PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), + PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN), + PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), + + /* IPSR0 */ + PINMUX_IPSR_DATA(IP0_0, D0), + PINMUX_IPSR_DATA(IP0_1, D1), + PINMUX_IPSR_DATA(IP0_2, D2), + PINMUX_IPSR_DATA(IP0_3, D3), + PINMUX_IPSR_DATA(IP0_4, D4), + PINMUX_IPSR_DATA(IP0_5, D5), + PINMUX_IPSR_DATA(IP0_6, D6), + PINMUX_IPSR_DATA(IP0_7, D7), + PINMUX_IPSR_DATA(IP0_8, D8), + PINMUX_IPSR_DATA(IP0_9, D9), + PINMUX_IPSR_DATA(IP0_10, D10), + PINMUX_IPSR_DATA(IP0_11, D11), + PINMUX_IPSR_DATA(IP0_12, D12), + PINMUX_IPSR_DATA(IP0_13, D13), + PINMUX_IPSR_DATA(IP0_14, D14), + PINMUX_IPSR_DATA(IP0_15, D15), + PINMUX_IPSR_DATA(IP0_18_16, A0), + PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), + PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2), + PINMUX_IPSR_DATA(IP0_18_16, PWM2_B), + PINMUX_IPSR_DATA(IP0_20_19, A1), + PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP0_22_21, A2), + PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP0_24_23, A3), + PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP0_26_25, A4), + PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP0_28_27, A5), + PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP0_30_29, A6), + PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), + + /* IPSR1 */ + PINMUX_IPSR_DATA(IP1_1_0, A7), + PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP1_3_2, A8), + PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0), + PINMUX_IPSR_DATA(IP1_5_4, A9), + PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0), + PINMUX_IPSR_DATA(IP1_7_6, A10), + PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), + PINMUX_IPSR_DATA(IP1_10_8, A11), + PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3), + PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), + PINMUX_IPSR_DATA(IP1_13_11, A12), + PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0), + PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3), + PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), + PINMUX_IPSR_DATA(IP1_16_14, A13), + PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2), + PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0), + PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), + PINMUX_IPSR_DATA(IP1_19_17, A14), + PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), + PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0), + PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), + PINMUX_IPSR_DATA(IP1_22_20, A15), + PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_DATA(IP1_25_23, A16), + PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1), + PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2), + PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP1_28_26, A17), + PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1), + PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2), + PINMUX_IPSR_DATA(IP1_31_29, A18), + PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0), + PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), + + /* IPSR2 */ + PINMUX_IPSR_DATA(IP2_2_0, A19), + PINMUX_IPSR_DATA(IP2_2_0, DACK1), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP2_2_0, A20), + PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0), + PINMUX_IPSR_DATA(IP2_6_5, A21), + PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), + PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0), + PINMUX_IPSR_DATA(IP2_9_7, A22), + PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0), + PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), + PINMUX_IPSR_DATA(IP2_12_10, A23), + PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0), + PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), + PINMUX_IPSR_DATA(IP2_15_13, A24), + PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0), + PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0), + PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_DATA(IP2_18_16, A25), + PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0), + PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0), + PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2), + PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_DATA(IP2_20_19, CS0_N), + PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1), + PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0), + PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26), + PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), + PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0), + PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N), + PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), + PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N), + PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0), + PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), + PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N), + PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0), + PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0), + PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1), + + /* IPSR3 */ + PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N), + PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0), + PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), + PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2), + PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N), + PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N), + PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), + PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_DATA(IP3_5_3, PWM1), + PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1), + PINMUX_IPSR_DATA(IP3_8_6, BS_N), + PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N), + PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), + PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_DATA(IP3_8_6, PWM2), + PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2), + PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N), + PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), + PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1), + PINMUX_IPSR_DATA(IP3_13_12, WE0_N), + PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP3_15_14, WE1_N), + PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1), + PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0), + PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP3_19_18, DREQ0), + PINMUX_IPSR_DATA(IP3_19_18, PWM3), + PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3), + PINMUX_IPSR_DATA(IP3_21_20, DACK0), + PINMUX_IPSR_DATA(IP3_21_20, DRACK0), + PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0), + PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0), + PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), + PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), + PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2), + PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), + PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0), + PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), + + /* IPSR4 */ + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1), + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1), + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3), + PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1), + PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), + PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2), + PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2), + PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2), + PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4), + PINMUX_IPSR_DATA(IP4_19, SSI_SCK34), + PINMUX_IPSR_DATA(IP4_20, SSI_WS34), + PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3), + PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4), + PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4), + PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4), + PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), + PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5), + PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), + PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), + PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B), + + /* IPSR5 */ + PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), + PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B), + PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), + PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B), + PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6), + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), + PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B), + PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), + PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B), + PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6), + PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B), + PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), + PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), + PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), + + /* IPSR6 */ + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4), + PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT), + PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_DATA(IP6_9_8, IRQ0), + PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N), + PINMUX_IPSR_DATA(IP6_11_10, IRQ1), + PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), + PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N), + PINMUX_IPSR_DATA(IP6_13_12, IRQ2), + PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N), + PINMUX_IPSR_DATA(IP6_15_14, IRQ3), + PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2), + PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N), + PINMUX_IPSR_DATA(IP6_18_16, IRQ4), + PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2), + PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N), + PINMUX_IPSR_DATA(IP6_20_19, IRQ5), + PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4), + PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_23_21, IRQ6), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_26_24, IRQ7), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP6_29_27, IRQ8), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), + + /* IPSR7 */ + PINMUX_IPSR_DATA(IP7_2_0, IRQ9), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0), + PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), + PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1), + PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), + PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2), + PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2), + PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), + PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3), + PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3), + PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), + PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4), + PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4), + PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), + PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5), + PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5), + PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), + PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6), + PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6), + PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7), + PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7), + PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0), + PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), + PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1), + PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), + PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2), + PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), + + /* IPSR8 */ + PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3), + PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4), + PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5), + PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6), + PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7), + PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0), + PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16), + PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), + PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1), + PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17), + PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), + PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2), + PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18), + PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B), + PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3), + PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4), + PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20), + PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5), + PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21), + PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0), + PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0), + + /* IPSR9 */ + PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6), + PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7), + PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23), + PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2), + PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), + PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), + PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS), + PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0), + PINMUX_IPSR_DATA(IP9_7, QCLK), + PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE), + PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1), + PINMUX_IPSR_DATA(IP9_10_8, PWM4), + PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP9_11, QSTH_QHS), + PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP9_12, QSTB_QHE), + PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE), + PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1), + PINMUX_IPSR_DATA(IP9_16, DU1_DISP), + PINMUX_IPSR_DATA(IP9_16, QPOLA), + PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE), + PINMUX_IPSR_DATA(IP9_18_17, QPOLB), + PINMUX_IPSR_DATA(IP9_18_17, PWM4_B), + PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0), + PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), + PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), + PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0), + PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), + PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), + PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), + PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3), + PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP9_31_29, VI0_G0), + PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0), + PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), + PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0), + PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N), + + /* IPSR10 */ + PINMUX_IPSR_DATA(IP10_2_0, VI0_G1), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N), + PINMUX_IPSR_DATA(IP10_5_3, VI0_G2), + PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N), + PINMUX_IPSR_DATA(IP10_8_6, VI0_G3), + PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N), + PINMUX_IPSR_DATA(IP10_11_9, VI0_G4), + PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), + PINMUX_IPSR_DATA(IP10_14_12, VI0_G5), + PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), + PINMUX_IPSR_DATA(IP10_16_15, VI0_G6), + PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK), + PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3), + PINMUX_IPSR_DATA(IP10_18_17, VI0_G7), + PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0), + PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3), + PINMUX_IPSR_DATA(IP10_21_19, VI0_R0), + PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1), + PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), + PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N), + PINMUX_IPSR_DATA(IP10_24_22, VI0_R1), + PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2), + PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N), + PINMUX_IPSR_DATA(IP10_26_25, VI0_R2), + PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3), + PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_DATA(IP10_28_27, VI0_R3), + PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4), + PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_DATA(IP10_31_29, VI0_R4), + PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5), + PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3), + + /* IPSR11 */ + PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), + PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), + PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), + PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), + PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_27, AVB_MDC), + PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), + PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), + + /* IPSR12 */ + PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), + PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), + PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), + PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), + PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), + PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), + PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), + PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), + PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), + PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), + PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), + + /* IPSR13 */ + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_6_5, AVB_COL), + PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK), + PINMUX_IPSR_DATA(IP13_9_7, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), + PINMUX_IPSR_DATA(IP13_10, SD0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_11, SD0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_12, SD0_DATA0), + PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_13, SD0_DATA1), + PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_14, SD0_DATA2), + PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_15, SD0_DATA3), + PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_18_16, SD0_CD), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2), + PINMUX_IPSR_DATA(IP13_21_19, SD0_WP), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2), + PINMUX_IPSR_DATA(IP13_22, SD1_CMD), + PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0), + PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_DATA(IP13_25, SD1_DATA1), + PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_26, SD1_DATA2), + PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_27, SD1_DATA3), + PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_30_28, SD1_CD), + PINMUX_IPSR_DATA(IP13_30_28, PWM0), + PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0), + PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2), + + /* IPSR14 */ + PINMUX_IPSR_DATA(IP14_1_0, SD1_WP), + PINMUX_IPSR_DATA(IP14_1_0, PWM1_B), + PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2), + PINMUX_IPSR_DATA(IP14_2, SD2_CLK), + PINMUX_IPSR_DATA(IP14_2, MMC_CLK), + PINMUX_IPSR_DATA(IP14_3, SD2_CMD), + PINMUX_IPSR_DATA(IP14_3, MMC_CMD), + PINMUX_IPSR_DATA(IP14_4, SD2_DATA0), + PINMUX_IPSR_DATA(IP14_4, MMC_D0), + PINMUX_IPSR_DATA(IP14_5, SD2_DATA1), + PINMUX_IPSR_DATA(IP14_5, MMC_D1), + PINMUX_IPSR_DATA(IP14_6, SD2_DATA2), + PINMUX_IPSR_DATA(IP14_6, MMC_D2), + PINMUX_IPSR_DATA(IP14_7, SD2_DATA3), + PINMUX_IPSR_DATA(IP14_7, MMC_D3), + PINMUX_IPSR_DATA(IP14_10_8, SD2_CD), + PINMUX_IPSR_DATA(IP14_10_8, MMC_D4), + PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2), + PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_DATA(IP14_13_11, SD2_WP), + PINMUX_IPSR_DATA(IP14_13_11, MMC_D5), + PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2), + PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B), + PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B), + PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2), + PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2), + PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B), + + /* IPSR15 */ + PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), + PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP15_8_6, PWM5_B), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_DATA(IP15_11_9, PWM5), + PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_DATA(IP15_14_12, PWM6), + PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_DATA(IP15_23_21, TCLK2), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), + + /* IPSR16 */ + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP16_7_6, MLB_CK), + PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N), + PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N), + PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT), + PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - Audio Clock ------------------------------------------------------------ */ +static const unsigned int audio_clk_a_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 28), +}; + +static const unsigned int audio_clk_a_mux[] = { + AUDIO_CLKA_MARK, +}; + +static const unsigned int audio_clk_b_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 29), +}; + +static const unsigned int audio_clk_b_mux[] = { + AUDIO_CLKB_MARK, +}; + +static const unsigned int audio_clk_b_b_pins[] = { + /* CLK */ + RCAR_GP_PIN(7, 20), +}; + +static const unsigned int audio_clk_b_b_mux[] = { + AUDIO_CLKB_B_MARK, +}; + +static const unsigned int audio_clk_c_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 30), +}; + +static const unsigned int audio_clk_c_mux[] = { + AUDIO_CLKC_MARK, +}; + +static const unsigned int audio_clkout_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 31), +}; + +static const unsigned int audio_clkout_mux[] = { + AUDIO_CLKOUT_MARK, +}; + + +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), +}; +static const unsigned int du_rgb666_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, +}; +static const unsigned int du_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10), + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), +}; +static const unsigned int du_rgb888_mux[] = { + DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, + DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, + DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, + DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, + DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, + DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, +}; +static const unsigned int du_clk_out_0_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(3, 25), +}; +static const unsigned int du_clk_out_0_mux[] = { + DU1_DOTCLKOUT0_MARK +}; +static const unsigned int du_clk_out_1_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(3, 26), +}; +static const unsigned int du_clk_out_1_mux[] = { + DU1_DOTCLKOUT1_MARK +}; +static const unsigned int du_sync_pins[] = { + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), +}; +static const unsigned int du_sync_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK +}; +static const unsigned int du_oddf_pins[] = { + /* EXDISP/EXODDF/EXCDE */ + RCAR_GP_PIN(3, 29), +}; +static const unsigned int du_oddf_mux[] = { + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, +}; +static const unsigned int du_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(3, 31), +}; +static const unsigned int du_cde_mux[] = { + DU1_CDE_MARK, +}; +static const unsigned int du_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(3, 30), +}; +static const unsigned int du_disp_mux[] = { + DU1_DISP_MARK, +}; +static const unsigned int du0_clk_in_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int du0_clk_in_mux[] = { + DU0_DOTCLKIN_MARK +}; +static const unsigned int du1_clk_in_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(3, 24), +}; +static const unsigned int du1_clk_in_mux[] = { + DU1_DOTCLKIN_MARK +}; +static const unsigned int du1_clk_in_b_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(7, 19), +}; +static const unsigned int du1_clk_in_b_mux[] = { + DU1_DOTCLKIN_B_MARK, +}; +static const unsigned int du1_clk_in_c_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(7, 20), +}; +static const unsigned int du1_clk_in_c_mux[] = { + DU1_DOTCLKIN_C_MARK, +}; +/* - ETH -------------------------------------------------------------------- */ +static const unsigned int eth_link_pins[] = { + /* LINK */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int eth_link_mux[] = { + ETH_LINK_MARK, +}; +static const unsigned int eth_magic_pins[] = { + /* MAGIC */ + RCAR_GP_PIN(5, 22), +}; +static const unsigned int eth_magic_mux[] = { + ETH_MAGIC_MARK, +}; +static const unsigned int eth_mdio_pins[] = { + /* MDC, MDIO */ + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13), +}; +static const unsigned int eth_mdio_mux[] = { + ETH_MDC_MARK, ETH_MDIO_MARK, +}; +static const unsigned int eth_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20), + RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19), +}; +static const unsigned int eth_rmii_mux[] = { + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, +}; +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; +static const unsigned int i2c0_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), +}; +static const unsigned int i2c0_b_mux[] = { + SCL0_B_MARK, SDA0_B_MARK, +}; +static const unsigned int i2c0_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1), +}; +static const unsigned int i2c0_c_mux[] = { + SCL0_C_MARK, SDA0_C_MARK, +}; +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), +}; +static const unsigned int i2c1_mux[] = { + SCL1_MARK, SDA1_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), +}; +static const unsigned int i2c1_b_mux[] = { + SCL1_B_MARK, SDA1_B_MARK, +}; +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; +static const unsigned int i2c1_c_mux[] = { + SCL1_C_MARK, SDA1_C_MARK, +}; +static const unsigned int i2c1_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), +}; +static const unsigned int i2c1_d_mux[] = { + SCL1_D_MARK, SDA1_D_MARK, +}; +static const unsigned int i2c1_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16), +}; +static const unsigned int i2c1_e_mux[] = { + SCL1_E_MARK, SDA1_E_MARK, +}; +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), +}; +static const unsigned int i2c2_mux[] = { + SCL2_MARK, SDA2_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), +}; +static const unsigned int i2c2_b_mux[] = { + SCL2_B_MARK, SDA2_B_MARK, +}; +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), +}; +static const unsigned int i2c2_c_mux[] = { + SCL2_C_MARK, SDA2_C_MARK, +}; +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), +}; +static const unsigned int i2c2_d_mux[] = { + SCL2_D_MARK, SDA2_D_MARK, +}; +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; +static const unsigned int i2c3_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +}; +static const unsigned int i2c3_b_mux[] = { + SCL3_B_MARK, SDA3_B_MARK, +}; +static const unsigned int i2c3_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), +}; +static const unsigned int i2c3_c_mux[] = { + SCL3_C_MARK, SDA3_C_MARK, +}; +static const unsigned int i2c3_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), +}; +static const unsigned int i2c3_d_mux[] = { + SCL3_D_MARK, SDA3_D_MARK, +}; +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), +}; +static const unsigned int i2c4_mux[] = { + SCL4_MARK, SDA4_MARK, +}; +static const unsigned int i2c4_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), +}; +static const unsigned int i2c4_b_mux[] = { + SCL4_B_MARK, SDA4_B_MARK, +}; +static const unsigned int i2c4_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), +}; +static const unsigned int i2c4_c_mux[] = { + SCL4_C_MARK, SDA4_C_MARK, +}; +/* - I2C7 ------------------------------------------------------------------- */ +static const unsigned int i2c7_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int i2c7_mux[] = { + SCL7_MARK, SDA7_MARK, +}; +static const unsigned int i2c7_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), +}; +static const unsigned int i2c7_b_mux[] = { + SCL7_B_MARK, SDA7_B_MARK, +}; +static const unsigned int i2c7_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int i2c7_c_mux[] = { + SCL7_C_MARK, SDA7_C_MARK, +}; +/* - I2C8 ------------------------------------------------------------------- */ +static const unsigned int i2c8_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), +}; +static const unsigned int i2c8_mux[] = { + SCL8_MARK, SDA8_MARK, +}; +static const unsigned int i2c8_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), +}; +static const unsigned int i2c8_b_mux[] = { + SCL8_B_MARK, SDA8_B_MARK, +}; +static const unsigned int i2c8_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), +}; +static const unsigned int i2c8_c_mux[] = { + SCL8_C_MARK, SDA8_C_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +static const unsigned int intc_irq0_pins[] = { + /* IRQ */ + RCAR_GP_PIN(7, 10), +}; +static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_irq1_pins[] = { + /* IRQ */ + RCAR_GP_PIN(7, 11), +}; +static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_irq2_pins[] = { + /* IRQ */ + RCAR_GP_PIN(7, 12), +}; +static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_irq3_pins[] = { + /* IRQ */ + RCAR_GP_PIN(7, 13), +}; +static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, +}; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int mmc_data1_mux[] = { + MMC_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), +}; +static const unsigned int mmc_data4_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), + RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int mmc_data8_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_CLK_MARK, MMC_CMD_MARK, +}; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 24), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(6, 25), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(6, 27), +}; +static const unsigned int msiof0_rx_mux[] = { + MSIOF0_RXD_MARK, +}; +static const unsigned int msiof0_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 26), +}; +static const unsigned int msiof0_tx_mux[] = { + MSIOF0_TXD_MARK, +}; + +static const unsigned int msiof0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int msiof0_clk_b_mux[] = { + MSIOF0_SCK_B_MARK, +}; +static const unsigned int msiof0_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int msiof0_sync_b_mux[] = { + MSIOF0_SYNC_B_MARK, +}; +static const unsigned int msiof0_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int msiof0_ss1_b_mux[] = { + MSIOF0_SS1_B_MARK, +}; +static const unsigned int msiof0_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int msiof0_ss2_b_mux[] = { + MSIOF0_SS2_B_MARK, +}; +static const unsigned int msiof0_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 21), +}; +static const unsigned int msiof0_rx_b_mux[] = { + MSIOF0_RXD_B_MARK, +}; +static const unsigned int msiof0_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int msiof0_tx_b_mux[] = { + MSIOF0_TXD_B_MARK, +}; + +static const unsigned int msiof0_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 26), +}; +static const unsigned int msiof0_clk_c_mux[] = { + MSIOF0_SCK_C_MARK, +}; +static const unsigned int msiof0_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 25), +}; +static const unsigned int msiof0_sync_c_mux[] = { + MSIOF0_SYNC_C_MARK, +}; +static const unsigned int msiof0_ss1_c_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 27), +}; +static const unsigned int msiof0_ss1_c_mux[] = { + MSIOF0_SS1_C_MARK, +}; +static const unsigned int msiof0_ss2_c_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 28), +}; +static const unsigned int msiof0_ss2_c_mux[] = { + MSIOF0_SS2_C_MARK, +}; +static const unsigned int msiof0_rx_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 29), +}; +static const unsigned int msiof0_rx_c_mux[] = { + MSIOF0_RXD_C_MARK, +}; +static const unsigned int msiof0_tx_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 30), +}; +static const unsigned int msiof0_tx_c_mux[] = { + MSIOF0_TXD_C_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 22), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 23), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 24), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 25), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 27), +}; +static const unsigned int msiof1_rx_mux[] = { + MSIOF1_RXD_MARK, +}; +static const unsigned int msiof1_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 26), +}; +static const unsigned int msiof1_tx_mux[] = { + MSIOF1_TXD_MARK, +}; + +static const unsigned int msiof1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 29), +}; +static const unsigned int msiof1_clk_b_mux[] = { + MSIOF1_SCK_B_MARK, +}; +static const unsigned int msiof1_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 30), +}; +static const unsigned int msiof1_sync_b_mux[] = { + MSIOF1_SYNC_B_MARK, +}; +static const unsigned int msiof1_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 31), +}; +static const unsigned int msiof1_ss1_b_mux[] = { + MSIOF1_SS1_B_MARK, +}; +static const unsigned int msiof1_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(7, 16), +}; +static const unsigned int msiof1_ss2_b_mux[] = { + MSIOF1_SS2_B_MARK, +}; +static const unsigned int msiof1_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(7, 18), +}; +static const unsigned int msiof1_rx_b_mux[] = { + MSIOF1_RXD_B_MARK, +}; +static const unsigned int msiof1_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(7, 17), +}; +static const unsigned int msiof1_tx_b_mux[] = { + MSIOF1_TXD_B_MARK, +}; + +static const unsigned int msiof1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int msiof1_clk_c_mux[] = { + MSIOF1_SCK_C_MARK, +}; +static const unsigned int msiof1_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int msiof1_sync_c_mux[] = { + MSIOF1_SYNC_C_MARK, +}; +static const unsigned int msiof1_rx_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 18), +}; +static const unsigned int msiof1_rx_c_mux[] = { + MSIOF1_RXD_C_MARK, +}; +static const unsigned int msiof1_tx_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 17), +}; +static const unsigned int msiof1_tx_c_mux[] = { + MSIOF1_TXD_C_MARK, +}; + +static const unsigned int msiof1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 28), +}; +static const unsigned int msiof1_clk_d_mux[] = { + MSIOF1_SCK_D_MARK, +}; +static const unsigned int msiof1_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 30), +}; +static const unsigned int msiof1_sync_d_mux[] = { + MSIOF1_SYNC_D_MARK, +}; +static const unsigned int msiof1_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 29), +}; +static const unsigned int msiof1_ss1_d_mux[] = { + MSIOF1_SS1_D_MARK, +}; +static const unsigned int msiof1_rx_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 27), +}; +static const unsigned int msiof1_rx_d_mux[] = { + MSIOF1_RXD_D_MARK, +}; +static const unsigned int msiof1_tx_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 26), +}; +static const unsigned int msiof1_tx_d_mux[] = { + MSIOF1_TXD_D_MARK, +}; + +static const unsigned int msiof1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int msiof1_clk_e_mux[] = { + MSIOF1_SCK_E_MARK, +}; +static const unsigned int msiof1_sync_e_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int msiof1_sync_e_mux[] = { + MSIOF1_SYNC_E_MARK, +}; +static const unsigned int msiof1_rx_e_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int msiof1_rx_e_mux[] = { + MSIOF1_RXD_E_MARK, +}; +static const unsigned int msiof1_tx_e_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int msiof1_tx_e_mux[] = { + MSIOF1_TXD_E_MARK, +}; +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 14), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int msiof2_rx_mux[] = { + MSIOF2_RXD_MARK, +}; +static const unsigned int msiof2_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int msiof2_tx_mux[] = { + MSIOF2_TXD_MARK, +}; + +static const unsigned int msiof2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 0), +}; +static const unsigned int msiof2_clk_b_mux[] = { + MSIOF2_SCK_B_MARK, +}; +static const unsigned int msiof2_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int msiof2_sync_b_mux[] = { + MSIOF2_SYNC_B_MARK, +}; +static const unsigned int msiof2_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int msiof2_ss1_b_mux[] = { + MSIOF2_SS1_B_MARK, +}; +static const unsigned int msiof2_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int msiof2_ss2_b_mux[] = { + MSIOF2_SS2_B_MARK, +}; +static const unsigned int msiof2_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int msiof2_rx_b_mux[] = { + MSIOF2_RXD_B_MARK, +}; +static const unsigned int msiof2_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 16), +}; +static const unsigned int msiof2_tx_b_mux[] = { + MSIOF2_TXD_B_MARK, +}; + +static const unsigned int msiof2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int msiof2_clk_c_mux[] = { + MSIOF2_SCK_C_MARK, +}; +static const unsigned int msiof2_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int msiof2_sync_c_mux[] = { + MSIOF2_SYNC_C_MARK, +}; +static const unsigned int msiof2_rx_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int msiof2_rx_c_mux[] = { + MSIOF2_RXD_C_MARK, +}; +static const unsigned int msiof2_tx_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int msiof2_tx_c_mux[] = { + MSIOF2_TXD_C_MARK, +}; + +static const unsigned int msiof2_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int msiof2_clk_d_mux[] = { + MSIOF2_SCK_D_MARK, +}; +static const unsigned int msiof2_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int msiof2_sync_d_mux[] = { + MSIOF2_SYNC_D_MARK, +}; +static const unsigned int msiof2_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 17), +}; +static const unsigned int msiof2_ss1_d_mux[] = { + MSIOF2_SS1_D_MARK, +}; +static const unsigned int msiof2_ss2_d_pins[] = { + /* SS2 */ + RCAR_GP_PIN(2, 19), +}; +static const unsigned int msiof2_ss2_d_mux[] = { + MSIOF2_SS2_D_MARK, +}; +static const unsigned int msiof2_rx_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 18), +}; +static const unsigned int msiof2_rx_d_mux[] = { + MSIOF2_RXD_D_MARK, +}; +static const unsigned int msiof2_tx_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int msiof2_tx_d_mux[] = { + MSIOF2_TXD_D_MARK, +}; + +static const unsigned int msiof2_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(7, 15), +}; +static const unsigned int msiof2_clk_e_mux[] = { + MSIOF2_SCK_E_MARK, +}; +static const unsigned int msiof2_sync_e_pins[] = { + /* SYNC */ + RCAR_GP_PIN(7, 16), +}; +static const unsigned int msiof2_sync_e_mux[] = { + MSIOF2_SYNC_E_MARK, +}; +static const unsigned int msiof2_rx_e_pins[] = { + /* RXD */ + RCAR_GP_PIN(7, 14), +}; +static const unsigned int msiof2_rx_e_mux[] = { + MSIOF2_RXD_E_MARK, +}; +static const unsigned int msiof2_tx_e_pins[] = { + /* TXD */ + RCAR_GP_PIN(7, 13), +}; +static const unsigned int msiof2_tx_e_mux[] = { + MSIOF2_TXD_E_MARK, +}; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; + +static const unsigned int qspi_ctrl_b_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), +}; +static const unsigned int qspi_ctrl_b_mux[] = { + SPCLK_B_MARK, SSL_B_MARK, +}; +static const unsigned int qspi_data2_b_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), +}; +static const unsigned int qspi_data2_b_mux[] = { + MOSI_IO0_B_MARK, MISO_IO1_B_MARK, +}; +static const unsigned int qspi_data4_b_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), +}; +static const unsigned int qspi_data4_b_mux[] = { + SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK, + IO2_B_MARK, IO3_B_MARK, SSL_B_MARK, +}; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), +}; +static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, +}; +static const unsigned int scif0_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25), +}; +static const unsigned int scif0_data_c_mux[] = { + RX0_C_MARK, TX0_C_MARK, +}; +static const unsigned int scif0_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), +}; +static const unsigned int scif0_data_d_mux[] = { + RX0_D_MARK, TX0_D_MARK, +}; +static const unsigned int scif0_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28), +}; +static const unsigned int scif0_data_e_mux[] = { + RX0_E_MARK, TX0_E_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), +}; +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int scif1_clk_b_mux[] = { + SCIF1_SCK_B_MARK, +}; +static const unsigned int scif1_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27), +}; +static const unsigned int scif1_data_c_mux[] = { + RX1_C_MARK, TX1_C_MARK, +}; +static const unsigned int scif1_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), +}; +static const unsigned int scif1_data_d_mux[] = { + RX1_D_MARK, TX1_D_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), +}; +static const unsigned int scif2_data_mux[] = { + RX2_MARK, TX2_MARK, +}; +static const unsigned int scif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), +}; +static const unsigned int scif2_data_b_mux[] = { + RX2_B_MARK, TX2_B_MARK, +}; +static const unsigned int scif2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int scif2_clk_b_mux[] = { + SCIF2_SCK_B_MARK, +}; +static const unsigned int scif2_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int scif2_data_c_mux[] = { + RX2_C_MARK, TX2_C_MARK, +}; +static const unsigned int scif2_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; +static const unsigned int scif2_data_e_mux[] = { + RX2_E_MARK, TX2_E_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), +}; +static const unsigned int scif3_data_mux[] = { + RX3_MARK, TX3_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 23), +}; +static const unsigned int scif3_clk_mux[] = { + SCIF3_SCK_MARK, +}; +static const unsigned int scif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26), +}; +static const unsigned int scif3_data_b_mux[] = { + RX3_B_MARK, TX3_B_MARK, +}; +static const unsigned int scif3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 8), +}; +static const unsigned int scif3_clk_b_mux[] = { + SCIF3_SCK_B_MARK, +}; +static const unsigned int scif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), +}; +static const unsigned int scif3_data_c_mux[] = { + RX3_C_MARK, TX3_C_MARK, +}; +static const unsigned int scif3_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26), +}; +static const unsigned int scif3_data_d_mux[] = { + RX3_D_MARK, TX3_D_MARK, +}; +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), +}; +static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, +}; +static const unsigned int scif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), +}; +static const unsigned int scif4_data_b_mux[] = { + RX4_B_MARK, TX4_B_MARK, +}; +static const unsigned int scif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), +}; +static const unsigned int scif4_data_c_mux[] = { + RX4_C_MARK, TX4_C_MARK, +}; +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), +}; +static const unsigned int scif5_data_mux[] = { + RX5_MARK, TX5_MARK, +}; +static const unsigned int scif5_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), +}; +static const unsigned int scif5_data_b_mux[] = { + RX5_B_MARK, TX5_B_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), +}; +static const unsigned int scifa0_data_b_mux[] = { + SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), +}; +static const unsigned int scifa1_data_b_mux[] = { + SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, +}; +static const unsigned int scifa1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int scifa1_clk_b_mux[] = { + SCIFA1_SCK_B_MARK, +}; +static const unsigned int scifa1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), +}; +static const unsigned int scifa1_data_c_mux[] = { + SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31), +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, +}; +static const unsigned int scifa2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int scifa2_clk_mux[] = { + SCIFA2_SCK_MARK, +}; +static const unsigned int scifa2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), +}; +static const unsigned int scifa2_data_b_mux[] = { + SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21), +}; +static const unsigned int scifa3_data_mux[] = { + SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, +}; +static const unsigned int scifa3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 23), +}; +static const unsigned int scifa3_clk_mux[] = { + SCIFA3_SCK_MARK, +}; +static const unsigned int scifa3_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), +}; +static const unsigned int scifa3_data_b_mux[] = { + SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, +}; +static const unsigned int scifa3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 8), +}; +static const unsigned int scifa3_clk_b_mux[] = { + SCIFA3_SCK_B_MARK, +}; +static const unsigned int scifa3_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20), +}; +static const unsigned int scifa3_data_c_mux[] = { + SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK, +}; +static const unsigned int scifa3_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(7, 22), +}; +static const unsigned int scifa3_clk_c_mux[] = { + SCIFA3_SCK_C_MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1), +}; +static const unsigned int scifa4_data_mux[] = { + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, +}; +static const unsigned int scifa4_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0), +}; +static const unsigned int scifa4_data_b_mux[] = { + SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, +}; +static const unsigned int scifa4_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21), +}; +static const unsigned int scifa4_data_c_mux[] = { + SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), +}; +static const unsigned int scifa5_data_mux[] = { + SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, +}; +static const unsigned int scifa5_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), +}; +static const unsigned int scifa5_data_b_mux[] = { + SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, +}; +static const unsigned int scifa5_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22), +}; +static const unsigned int scifa5_data_c_mux[] = { + SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, +}; +/* - SCIFB0 ----------------------------------------------------------------- */ +static const unsigned int scifb0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), +}; +static const unsigned int scifb0_data_mux[] = { + SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, +}; +static const unsigned int scifb0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(7, 2), +}; +static const unsigned int scifb0_clk_mux[] = { + SCIFB0_SCK_MARK, +}; +static const unsigned int scifb0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), +}; +static const unsigned int scifb0_ctrl_mux[] = { + SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, +}; +static const unsigned int scifb0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), +}; +static const unsigned int scifb0_data_b_mux[] = { + SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, +}; +static const unsigned int scifb0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 31), +}; +static const unsigned int scifb0_clk_b_mux[] = { + SCIFB0_SCK_B_MARK, +}; +static const unsigned int scifb0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23), +}; +static const unsigned int scifb0_ctrl_b_mux[] = { + SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, +}; +static const unsigned int scifb0_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int scifb0_data_c_mux[] = { + SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, +}; +static const unsigned int scifb0_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 30), +}; +static const unsigned int scifb0_clk_c_mux[] = { + SCIFB0_SCK_C_MARK, +}; +static const unsigned int scifb0_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), +}; +static const unsigned int scifb0_data_d_mux[] = { + SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK, +}; +static const unsigned int scifb0_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int scifb0_clk_d_mux[] = { + SCIFB0_SCK_D_MARK, +}; +/* - SCIFB1 ----------------------------------------------------------------- */ +static const unsigned int scifb1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), +}; +static const unsigned int scifb1_data_mux[] = { + SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, +}; +static const unsigned int scifb1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(7, 7), +}; +static const unsigned int scifb1_clk_mux[] = { + SCIFB1_SCK_MARK, +}; +static const unsigned int scifb1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), +}; +static const unsigned int scifb1_ctrl_mux[] = { + SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, +}; +static const unsigned int scifb1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), +}; +static const unsigned int scifb1_data_b_mux[] = { + SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, +}; +static const unsigned int scifb1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int scifb1_clk_b_mux[] = { + SCIFB1_SCK_B_MARK, +}; +static const unsigned int scifb1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), +}; +static const unsigned int scifb1_data_c_mux[] = { + SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, +}; +static const unsigned int scifb1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(7, 11), +}; +static const unsigned int scifb1_clk_c_mux[] = { + SCIFB1_SCK_C_MARK, +}; +static const unsigned int scifb1_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12), +}; +static const unsigned int scifb1_data_d_mux[] = { + SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, +}; +/* - SCIFB2 ----------------------------------------------------------------- */ +static const unsigned int scifb2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), +}; +static const unsigned int scifb2_data_mux[] = { + SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, +}; +static const unsigned int scifb2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int scifb2_clk_mux[] = { + SCIFB2_SCK_MARK, +}; +static const unsigned int scifb2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), +}; +static const unsigned int scifb2_ctrl_mux[] = { + SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, +}; +static const unsigned int scifb2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; +static const unsigned int scifb2_data_b_mux[] = { + SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, +}; +static const unsigned int scifb2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 31), +}; +static const unsigned int scifb2_clk_b_mux[] = { + SCIFB2_SCK_B_MARK, +}; +static const unsigned int scifb2_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), +}; +static const unsigned int scifb2_ctrl_b_mux[] = { + SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, +}; +static const unsigned int scifb2_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int scifb2_data_c_mux[] = { + SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, +}; +static const unsigned int scifb2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 27), +}; +static const unsigned int scifb2_clk_c_mux[] = { + SCIFB2_SCK_C_MARK, +}; +static const unsigned int scifb2_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25), +}; +static const unsigned int scifb2_data_d_mux[] = { + SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DATA0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(6, 6), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DATA0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(6, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(6, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DATA0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(6, 22), +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; + +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 2), +}; + +static const unsigned int ssi0_data_mux[] = { + SSI_SDATA0_MARK, +}; + +static const unsigned int ssi0_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(3, 4), +}; + +static const unsigned int ssi0_data_b_mux[] = { + SSI_SDATA0_B_MARK, +}; + +static const unsigned int ssi0129_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; + +static const unsigned int ssi0129_ctrl_mux[] = { + SSI_SCK0129_MARK, SSI_WS0129_MARK, +}; + +static const unsigned int ssi0129_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), +}; + +static const unsigned int ssi0129_ctrl_b_mux[] = { + SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK, +}; + +static const unsigned int ssi1_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 5), +}; + +static const unsigned int ssi1_data_mux[] = { + SSI_SDATA1_MARK, +}; + +static const unsigned int ssi1_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(3, 7), +}; + +static const unsigned int ssi1_data_b_mux[] = { + SSI_SDATA1_B_MARK, +}; + +static const unsigned int ssi1_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), +}; + +static const unsigned int ssi1_ctrl_mux[] = { + SSI_SCK1_MARK, SSI_WS1_MARK, +}; + +static const unsigned int ssi1_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), +}; + +static const unsigned int ssi1_ctrl_b_mux[] = { + SSI_SCK1_B_MARK, SSI_WS1_B_MARK, +}; + +static const unsigned int ssi2_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 8), +}; + +static const unsigned int ssi2_data_mux[] = { + SSI_SDATA2_MARK, +}; + +static const unsigned int ssi2_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), +}; + +static const unsigned int ssi2_ctrl_mux[] = { + SSI_SCK2_MARK, SSI_WS2_MARK, +}; + +static const unsigned int ssi3_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 11), +}; + +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK, +}; + +static const unsigned int ssi34_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), +}; + +static const unsigned int ssi34_ctrl_mux[] = { + SSI_SCK34_MARK, SSI_WS34_MARK, +}; + +static const unsigned int ssi4_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 14), +}; + +static const unsigned int ssi4_data_mux[] = { + SSI_SDATA4_MARK, +}; + +static const unsigned int ssi4_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), +}; + +static const unsigned int ssi4_ctrl_mux[] = { + SSI_SCK4_MARK, SSI_WS4_MARK, +}; + +static const unsigned int ssi5_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 17), +}; + +static const unsigned int ssi5_data_mux[] = { + SSI_SDATA5_MARK, +}; + +static const unsigned int ssi5_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), +}; + +static const unsigned int ssi5_ctrl_mux[] = { + SSI_SCK5_MARK, SSI_WS5_MARK, +}; + +static const unsigned int ssi6_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 20), +}; + +static const unsigned int ssi6_data_mux[] = { + SSI_SDATA6_MARK, +}; + +static const unsigned int ssi6_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), +}; + +static const unsigned int ssi6_ctrl_mux[] = { + SSI_SCK6_MARK, SSI_WS6_MARK, +}; + +static const unsigned int ssi7_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 23), +}; + +static const unsigned int ssi7_data_mux[] = { + SSI_SDATA7_MARK, +}; + +static const unsigned int ssi7_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(3, 12), +}; + +static const unsigned int ssi7_data_b_mux[] = { + SSI_SDATA7_B_MARK, +}; + +static const unsigned int ssi78_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +}; + +static const unsigned int ssi78_ctrl_mux[] = { + SSI_SCK78_MARK, SSI_WS78_MARK, +}; + +static const unsigned int ssi78_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; + +static const unsigned int ssi78_ctrl_b_mux[] = { + SSI_SCK78_B_MARK, SSI_WS78_B_MARK, +}; + +static const unsigned int ssi8_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 24), +}; + +static const unsigned int ssi8_data_mux[] = { + SSI_SDATA8_MARK, +}; + +static const unsigned int ssi8_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(3, 13), +}; + +static const unsigned int ssi8_data_b_mux[] = { + SSI_SDATA8_B_MARK, +}; + +static const unsigned int ssi9_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 27), +}; + +static const unsigned int ssi9_data_mux[] = { + SSI_SDATA9_MARK, +}; + +static const unsigned int ssi9_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(3, 18), +}; + +static const unsigned int ssi9_data_b_mux[] = { + SSI_SDATA9_B_MARK, +}; + +static const unsigned int ssi9_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), +}; + +static const unsigned int ssi9_ctrl_mux[] = { + SSI_SCK9_MARK, SSI_WS9_MARK, +}; + +static const unsigned int ssi9_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int ssi9_ctrl_b_mux[] = { + SSI_SCK9_B_MARK, SSI_WS9_B_MARK, +}; + +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + RCAR_GP_PIN(7, 23), /* PWEN */ + RCAR_GP_PIN(7, 24), /* OVC */ +}; +static const unsigned int usb0_mux[] = { + USB0_PWEN_MARK, + USB0_OVC_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_pins[] = { + RCAR_GP_PIN(7, 25), /* PWEN */ + RCAR_GP_PIN(6, 30), /* OVC */ +}; +static const unsigned int usb1_mux[] = { + USB1_PWEN_MARK, + USB1_OVC_MARK, +}; + +union vin_data { + unsigned int data24[24]; + unsigned int data20[20]; + unsigned int data16[16]; + unsigned int data12[12]; + unsigned int data10[10]; + unsigned int data8[8]; +}; + +#define VIN_DATA_PIN_GROUP(n, s) \ + { \ + .name = #n#s, \ + .pins = n##_pins.data##s, \ + .mux = n##_mux.data##s, \ + .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ + } + +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + /* G */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + /* R */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), + RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, + }, +}; +static const unsigned int vin0_data18_pins[] = { + /* B */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + /* G */ + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + /* R */ + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), + RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), +}; +static const unsigned int vin0_data18_mux[] = { + /* B */ + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + RCAR_GP_PIN(4, 3), /* HSYNC */ + RCAR_GP_PIN(4, 4), /* VSYNC */ +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_N_MARK, + VI0_VSYNC_N_MARK, +}; +static const unsigned int vin0_field_pins[] = { + RCAR_GP_PIN(4, 2), +}; +static const unsigned int vin0_field_mux[] = { + VI0_FIELD_MARK, +}; +static const unsigned int vin0_clkenb_pins[] = { + RCAR_GP_PIN(4, 1), +}; +static const unsigned int vin0_clkenb_mux[] = { + VI0_CLKENB_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + RCAR_GP_PIN(4, 0), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +/* - VIN1 ----------------------------------------------------------------- */ +static const unsigned int vin1_data8_pins[] = { + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), +}; +static const unsigned int vin1_data8_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, +}; +static const unsigned int vin1_sync_pins[] = { + RCAR_GP_PIN(5, 0), /* HSYNC */ + RCAR_GP_PIN(5, 1), /* VSYNC */ +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_N_MARK, + VI1_VSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + RCAR_GP_PIN(5, 3), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + RCAR_GP_PIN(5, 2), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + RCAR_GP_PIN(5, 4), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; +static const union vin_data vin1_b_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + /* G */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), + RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), + /* R */ + RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + }, +}; +static const union vin_data vin1_b_data_mux = { + .data24 = { + /* B */ + VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, + VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, + VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, + VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, + }, +}; +static const unsigned int vin1_b_data18_pins[] = { + /* B */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + /* G */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), + RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), + /* R */ + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), +}; +static const unsigned int vin1_b_data18_mux[] = { + /* B */ + VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, + VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, + VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, + VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, +}; +static const unsigned int vin1_b_sync_pins[] = { + RCAR_GP_PIN(3, 17), /* HSYNC */ + RCAR_GP_PIN(3, 18), /* VSYNC */ +}; +static const unsigned int vin1_b_sync_mux[] = { + VI1_HSYNC_N_B_MARK, + VI1_VSYNC_N_B_MARK, +}; +static const unsigned int vin1_b_field_pins[] = { + RCAR_GP_PIN(3, 20), +}; +static const unsigned int vin1_b_field_mux[] = { + VI1_FIELD_B_MARK, +}; +static const unsigned int vin1_b_clkenb_pins[] = { + RCAR_GP_PIN(3, 19), +}; +static const unsigned int vin1_b_clkenb_mux[] = { + VI1_CLKENB_B_MARK, +}; +static const unsigned int vin1_b_clk_pins[] = { + RCAR_GP_PIN(3, 16), +}; +static const unsigned int vin1_b_clk_mux[] = { + VI1_CLK_B_MARK, +}; +/* - VIN2 ----------------------------------------------------------------- */ +static const unsigned int vin2_data8_pins[] = { + RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), + RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), + RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), +}; +static const unsigned int vin2_data8_mux[] = { + VI2_DATA0_MARK, VI2_DATA1_MARK, + VI2_DATA2_MARK, VI2_DATA3_MARK, + VI2_DATA4_MARK, VI2_DATA5_MARK, + VI2_DATA6_MARK, VI2_DATA7_MARK, +}; +static const unsigned int vin2_sync_pins[] = { + RCAR_GP_PIN(4, 15), /* HSYNC */ + RCAR_GP_PIN(4, 16), /* VSYNC */ +}; +static const unsigned int vin2_sync_mux[] = { + VI2_HSYNC_N_MARK, + VI2_VSYNC_N_MARK, +}; +static const unsigned int vin2_field_pins[] = { + RCAR_GP_PIN(4, 18), +}; +static const unsigned int vin2_field_mux[] = { + VI2_FIELD_MARK, +}; +static const unsigned int vin2_clkenb_pins[] = { + RCAR_GP_PIN(4, 17), +}; +static const unsigned int vin2_clkenb_mux[] = { + VI2_CLKENB_MARK, +}; +static const unsigned int vin2_clk_pins[] = { + RCAR_GP_PIN(4, 19), +}; +static const unsigned int vin2_clk_mux[] = { + VI2_CLK_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in_b), + SH_PFC_PIN_GROUP(du1_clk_in_c), + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c0_b), + SH_PFC_PIN_GROUP(i2c0_c), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c1_e), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(i2c3_d), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c4_b), + SH_PFC_PIN_GROUP(i2c4_c), + SH_PFC_PIN_GROUP(i2c7), + SH_PFC_PIN_GROUP(i2c7_b), + SH_PFC_PIN_GROUP(i2c7_c), + SH_PFC_PIN_GROUP(i2c8), + SH_PFC_PIN_GROUP(i2c8_b), + SH_PFC_PIN_GROUP(i2c8_c), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_sync_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), + SH_PFC_PIN_GROUP(msiof0_clk_c), + SH_PFC_PIN_GROUP(msiof0_sync_c), + SH_PFC_PIN_GROUP(msiof0_ss1_c), + SH_PFC_PIN_GROUP(msiof0_ss2_c), + SH_PFC_PIN_GROUP(msiof0_rx_c), + SH_PFC_PIN_GROUP(msiof0_tx_c), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_rx_c), + SH_PFC_PIN_GROUP(msiof1_tx_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_rx_d), + SH_PFC_PIN_GROUP(msiof1_tx_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_rx_e), + SH_PFC_PIN_GROUP(msiof1_tx_e), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_rx_b), + SH_PFC_PIN_GROUP(msiof2_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_rx_c), + SH_PFC_PIN_GROUP(msiof2_tx_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_rx_d), + SH_PFC_PIN_GROUP(msiof2_tx_d), + SH_PFC_PIN_GROUP(msiof2_clk_e), + SH_PFC_PIN_GROUP(msiof2_sync_e), + SH_PFC_PIN_GROUP(msiof2_rx_e), + SH_PFC_PIN_GROUP(msiof2_tx_e), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(qspi_ctrl_b), + SH_PFC_PIN_GROUP(qspi_data2_b), + SH_PFC_PIN_GROUP(qspi_data4_b), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif0_data_e), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_data_e), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_clk_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif3_data_d), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif5_data), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_clk), + SH_PFC_PIN_GROUP(scifa3_data_b), + SH_PFC_PIN_GROUP(scifa3_clk_b), + SH_PFC_PIN_GROUP(scifa3_data_c), + SH_PFC_PIN_GROUP(scifa3_clk_c), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa4_data_b), + SH_PFC_PIN_GROUP(scifa4_data_c), + SH_PFC_PIN_GROUP(scifa5_data), + SH_PFC_PIN_GROUP(scifa5_data_b), + SH_PFC_PIN_GROUP(scifa5_data_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb0_clk_c), + SH_PFC_PIN_GROUP(scifb0_data_d), + SH_PFC_PIN_GROUP(scifb0_clk_d), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_clk_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(scifb2_clk_c), + SH_PFC_PIN_GROUP(scifb2_data_d), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi0_data_b), + SH_PFC_PIN_GROUP(ssi0129_ctrl), + SH_PFC_PIN_GROUP(ssi0129_ctrl_b), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi7_data_b), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi78_ctrl_b), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi8_data_b), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin1_b_data, 24), + VIN_DATA_PIN_GROUP(vin1_b_data, 20), + SH_PFC_PIN_GROUP(vin1_b_data18), + VIN_DATA_PIN_GROUP(vin1_b_data, 16), + VIN_DATA_PIN_GROUP(vin1_b_data, 12), + VIN_DATA_PIN_GROUP(vin1_b_data, 10), + VIN_DATA_PIN_GROUP(vin1_b_data, 8), + SH_PFC_PIN_GROUP(vin1_b_sync), + SH_PFC_PIN_GROUP(vin1_b_field), + SH_PFC_PIN_GROUP(vin1_b_clkenb), + SH_PFC_PIN_GROUP(vin1_b_clk), + SH_PFC_PIN_GROUP(vin2_data8), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), +}; + +static const char * const audio_clk_groups[] = { + "audio_clk_a", + "audio_clk_b", + "audio_clk_b_b", + "audio_clk_c", + "audio_clkout", +}; + +static const char * const du_groups[] = { + "du_rgb666", + "du_rgb888", + "du_clk_out_0", + "du_clk_out_1", + "du_sync", + "du_oddf", + "du_cde", + "du_disp", +}; + +static const char * const du0_groups[] = { + "du0_clk_in", +}; + +static const char * const du1_groups[] = { + "du1_clk_in", + "du1_clk_in_b", + "du1_clk_in_c", +}; + +static const char * const eth_groups[] = { + "eth_link", + "eth_magic", + "eth_mdio", + "eth_rmii", +}; + +static const char * const i2c0_groups[] = { + "i2c0", + "i2c0_b", + "i2c0_c", +}; + +static const char * const i2c1_groups[] = { + "i2c1", + "i2c1_b", + "i2c1_c", + "i2c1_d", + "i2c1_e", +}; + +static const char * const i2c2_groups[] = { + "i2c2", + "i2c2_b", + "i2c2_c", + "i2c2_d", +}; + +static const char * const i2c3_groups[] = { + "i2c3", + "i2c3_b", + "i2c3_c", + "i2c3_d", +}; + +static const char * const i2c4_groups[] = { + "i2c4", + "i2c4_b", + "i2c4_c", +}; + +static const char * const i2c7_groups[] = { + "i2c7", + "i2c7_b", + "i2c7_c", +}; + +static const char * const i2c8_groups[] = { + "i2c8", + "i2c8_b", + "i2c8_c", +}; + +static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq1", + "intc_irq2", + "intc_irq3", +}; + +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_rx", + "msiof0_tx", + "msiof0_clk_b", + "msiof0_sync_b", + "msiof0_ss1_b", + "msiof0_ss2_b", + "msiof0_rx_b", + "msiof0_tx_b", + "msiof0_clk_c", + "msiof0_sync_c", + "msiof0_ss1_c", + "msiof0_ss2_c", + "msiof0_rx_c", + "msiof0_tx_c", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_rx", + "msiof1_tx", + "msiof1_clk_b", + "msiof1_sync_b", + "msiof1_ss1_b", + "msiof1_ss2_b", + "msiof1_rx_b", + "msiof1_tx_b", + "msiof1_clk_c", + "msiof1_sync_c", + "msiof1_rx_c", + "msiof1_tx_c", + "msiof1_clk_d", + "msiof1_sync_d", + "msiof1_ss1_d", + "msiof1_rx_d", + "msiof1_tx_d", + "msiof1_clk_e", + "msiof1_sync_e", + "msiof1_rx_e", + "msiof1_tx_e", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_rx", + "msiof2_tx", + "msiof2_clk_b", + "msiof2_sync_b", + "msiof2_ss1_b", + "msiof2_ss2_b", + "msiof2_rx_b", + "msiof2_tx_b", + "msiof2_clk_c", + "msiof2_sync_c", + "msiof2_rx_c", + "msiof2_tx_c", + "msiof2_clk_d", + "msiof2_sync_d", + "msiof2_ss1_d", + "msiof2_ss2_d", + "msiof2_rx_d", + "msiof2_tx_d", + "msiof2_clk_e", + "msiof2_sync_e", + "msiof2_rx_e", + "msiof2_tx_e", +}; + +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", + "qspi_ctrl_b", + "qspi_data2_b", + "qspi_data4_b", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_data_b", + "scif0_data_c", + "scif0_data_d", + "scif0_data_e", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_data_b", + "scif1_clk_b", + "scif1_data_c", + "scif1_data_d", +}; + +static const char * const scif2_groups[] = { + "scif2_data", + "scif2_data_b", + "scif2_clk_b", + "scif2_data_c", + "scif2_data_e", +}; +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_data_b", + "scif3_clk_b", + "scif3_data_c", + "scif3_data_d", +}; +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_data_b", + "scif4_data_c", +}; +static const char * const scif5_groups[] = { + "scif5_data", + "scif5_data_b", +}; +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_data_b", +}; +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_data_b", + "scifa1_clk_b", + "scifa1_data_c", +}; +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk", + "scifa2_data_b", +}; +static const char * const scifa3_groups[] = { + "scifa3_data", + "scifa3_clk", + "scifa3_data_b", + "scifa3_clk_b", + "scifa3_data_c", + "scifa3_clk_c", +}; +static const char * const scifa4_groups[] = { + "scifa4_data", + "scifa4_data_b", + "scifa4_data_c", +}; +static const char * const scifa5_groups[] = { + "scifa5_data", + "scifa5_data_b", + "scifa5_data_c", +}; +static const char * const scifb0_groups[] = { + "scifb0_data", + "scifb0_clk", + "scifb0_ctrl", + "scifb0_data_b", + "scifb0_clk_b", + "scifb0_ctrl_b", + "scifb0_data_c", + "scifb0_clk_c", + "scifb0_data_d", + "scifb0_clk_d", +}; +static const char * const scifb1_groups[] = { + "scifb1_data", + "scifb1_clk", + "scifb1_ctrl", + "scifb1_data_b", + "scifb1_clk_b", + "scifb1_data_c", + "scifb1_clk_c", + "scifb1_data_d", +}; +static const char * const scifb2_groups[] = { + "scifb2_data", + "scifb2_clk", + "scifb2_ctrl", + "scifb2_data_b", + "scifb2_clk_b", + "scifb2_ctrl_b", + "scifb0_data_c", + "scifb2_clk_c", + "scifb2_data_d", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + +static const char * const ssi_groups[] = { + "ssi0_data", + "ssi0_data_b", + "ssi0129_ctrl", + "ssi0129_ctrl_b", + "ssi1_data", + "ssi1_data_b", + "ssi1_ctrl", + "ssi1_ctrl_b", + "ssi2_data", + "ssi2_ctrl", + "ssi3_data", + "ssi34_ctrl", + "ssi4_data", + "ssi4_ctrl", + "ssi5_data", + "ssi5_ctrl", + "ssi6_data", + "ssi6_ctrl", + "ssi7_data", + "ssi7_data_b", + "ssi78_ctrl", + "ssi78_ctrl_b", + "ssi8_data", + "ssi8_data_b", + "ssi9_data", + "ssi9_data_b", + "ssi9_ctrl", + "ssi9_ctrl_b", +}; + +static const char * const usb0_groups[] = { + "usb0", +}; +static const char * const usb1_groups[] = { + "usb1", +}; + +static const char * const vin0_groups[] = { + "vin0_data24", + "vin0_data20", + "vin0_data18", + "vin0_data16", + "vin0_data12", + "vin0_data10", + "vin0_data8", + "vin0_sync", + "vin0_field", + "vin0_clkenb", + "vin0_clk", +}; + +static const char * const vin1_groups[] = { + "vin1_data8", + "vin1_sync", + "vin1_field", + "vin1_clkenb", + "vin1_clk", + "vin1_b_data24", + "vin1_b_data20", + "vin1_b_data18", + "vin1_b_data16", + "vin1_b_data12", + "vin1_b_data10", + "vin1_b_data8", + "vin1_b_sync", + "vin1_b_field", + "vin1_b_clkenb", + "vin1_b_clk", +}; + +static const char * const vin2_groups[] = { + "vin2_data8", + "vin2_sync", + "vin2_field", + "vin2_clkenb", + "vin2_clk", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c7), + SH_PFC_FUNCTION(i2c8), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP1_22_20, + GP_0_30_FN, FN_IP1_19_17, + GP_0_29_FN, FN_IP1_16_14, + GP_0_28_FN, FN_IP1_13_11, + GP_0_27_FN, FN_IP1_10_8, + GP_0_26_FN, FN_IP1_7_6, + GP_0_25_FN, FN_IP1_5_4, + GP_0_24_FN, FN_IP1_3_2, + GP_0_23_FN, FN_IP1_1_0, + GP_0_22_FN, FN_IP0_30_29, + GP_0_21_FN, FN_IP0_28_27, + GP_0_20_FN, FN_IP0_26_25, + GP_0_19_FN, FN_IP0_24_23, + GP_0_18_FN, FN_IP0_22_21, + GP_0_17_FN, FN_IP0_20_19, + GP_0_16_FN, FN_IP0_18_16, + GP_0_15_FN, FN_IP0_15, + GP_0_14_FN, FN_IP0_14, + GP_0_13_FN, FN_IP0_13, + GP_0_12_FN, FN_IP0_12, + GP_0_11_FN, FN_IP0_11, + GP_0_10_FN, FN_IP0_10, + GP_0_9_FN, FN_IP0_9, + GP_0_8_FN, FN_IP0_8, + GP_0_7_FN, FN_IP0_7, + GP_0_6_FN, FN_IP0_6, + GP_0_5_FN, FN_IP0_5, + GP_0_4_FN, FN_IP0_4, + GP_0_3_FN, FN_IP0_3, + GP_0_2_FN, FN_IP0_2, + GP_0_1_FN, FN_IP0_1, + GP_0_0_FN, FN_IP0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_IP3_21_20, + GP_1_24_FN, FN_IP3_19_18, + GP_1_23_FN, FN_IP3_17_16, + GP_1_22_FN, FN_IP3_15_14, + GP_1_21_FN, FN_IP3_13_12, + GP_1_20_FN, FN_IP3_11_9, + GP_1_19_FN, FN_RD_N, + GP_1_18_FN, FN_IP3_8_6, + GP_1_17_FN, FN_IP3_5_3, + GP_1_16_FN, FN_IP3_2_0, + GP_1_15_FN, FN_IP2_29_27, + GP_1_14_FN, FN_IP2_26_25, + GP_1_13_FN, FN_IP2_24_23, + GP_1_12_FN, FN_EX_CS0_N, + GP_1_11_FN, FN_IP2_22_21, + GP_1_10_FN, FN_IP2_20_19, + GP_1_9_FN, FN_IP2_18_16, + GP_1_8_FN, FN_IP2_15_13, + GP_1_7_FN, FN_IP2_12_10, + GP_1_6_FN, FN_IP2_9_7, + GP_1_5_FN, FN_IP2_6_5, + GP_1_4_FN, FN_IP2_4_3, + GP_1_3_FN, FN_IP2_2_0, + GP_1_2_FN, FN_IP1_31_29, + GP_1_1_FN, FN_IP1_28_26, + GP_1_0_FN, FN_IP1_25_23, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_3, + GP_2_29_FN, FN_IP6_2_0, + GP_2_28_FN, FN_AUDIO_CLKA, + GP_2_27_FN, FN_IP5_31_29, + GP_2_26_FN, FN_IP5_28_26, + GP_2_25_FN, FN_IP5_25_24, + GP_2_24_FN, FN_IP5_23_22, + GP_2_23_FN, FN_IP5_21_20, + GP_2_22_FN, FN_IP5_19_17, + GP_2_21_FN, FN_IP5_16_15, + GP_2_20_FN, FN_IP5_14_12, + GP_2_19_FN, FN_IP5_11_9, + GP_2_18_FN, FN_IP5_8_6, + GP_2_17_FN, FN_IP5_5_3, + GP_2_16_FN, FN_IP5_2_0, + GP_2_15_FN, FN_IP4_30_28, + GP_2_14_FN, FN_IP4_27_26, + GP_2_13_FN, FN_IP4_25_24, + GP_2_12_FN, FN_IP4_23_22, + GP_2_11_FN, FN_IP4_21, + GP_2_10_FN, FN_IP4_20, + GP_2_9_FN, FN_IP4_19, + GP_2_8_FN, FN_IP4_18_16, + GP_2_7_FN, FN_IP4_15_13, + GP_2_6_FN, FN_IP4_12_10, + GP_2_5_FN, FN_IP4_9_8, + GP_2_4_FN, FN_IP4_7_5, + GP_2_3_FN, FN_IP4_4_2, + GP_2_2_FN, FN_IP4_1_0, + GP_2_1_FN, FN_IP3_30_28, + GP_2_0_FN, FN_IP3_27_25 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP9_18_17, + GP_3_30_FN, FN_IP9_16, + GP_3_29_FN, FN_IP9_15_13, + GP_3_28_FN, FN_IP9_12, + GP_3_27_FN, FN_IP9_11, + GP_3_26_FN, FN_IP9_10_8, + GP_3_25_FN, FN_IP9_7, + GP_3_24_FN, FN_IP9_6, + GP_3_23_FN, FN_IP9_5_3, + GP_3_22_FN, FN_IP9_2_0, + GP_3_21_FN, FN_IP8_30_28, + GP_3_20_FN, FN_IP8_27_26, + GP_3_19_FN, FN_IP8_25_24, + GP_3_18_FN, FN_IP8_23_21, + GP_3_17_FN, FN_IP8_20_18, + GP_3_16_FN, FN_IP8_17_15, + GP_3_15_FN, FN_IP8_14_12, + GP_3_14_FN, FN_IP8_11_9, + GP_3_13_FN, FN_IP8_8_6, + GP_3_12_FN, FN_IP8_5_3, + GP_3_11_FN, FN_IP8_2_0, + GP_3_10_FN, FN_IP7_29_27, + GP_3_9_FN, FN_IP7_26_24, + GP_3_8_FN, FN_IP7_23_21, + GP_3_7_FN, FN_IP7_20_19, + GP_3_6_FN, FN_IP7_18_17, + GP_3_5_FN, FN_IP7_16_15, + GP_3_4_FN, FN_IP7_14_13, + GP_3_3_FN, FN_IP7_12_11, + GP_3_2_FN, FN_IP7_10_9, + GP_3_1_FN, FN_IP7_8_6, + GP_3_0_FN, FN_IP7_5_3 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP15_5_4, + GP_4_30_FN, FN_IP15_3_2, + GP_4_29_FN, FN_IP15_1_0, + GP_4_28_FN, FN_IP11_8_6, + GP_4_27_FN, FN_IP11_5_3, + GP_4_26_FN, FN_IP11_2_0, + GP_4_25_FN, FN_IP10_31_29, + GP_4_24_FN, FN_IP10_28_27, + GP_4_23_FN, FN_IP10_26_25, + GP_4_22_FN, FN_IP10_24_22, + GP_4_21_FN, FN_IP10_21_19, + GP_4_20_FN, FN_IP10_18_17, + GP_4_19_FN, FN_IP10_16_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_31_29, + GP_4_12_FN, FN_VI0_DATA7_VI0_B7, + GP_4_11_FN, FN_VI0_DATA6_VI0_B6, + GP_4_10_FN, FN_VI0_DATA5_VI0_B5, + GP_4_9_FN, FN_VI0_DATA4_VI0_B4, + GP_4_8_FN, FN_IP9_28_27, + GP_4_7_FN, FN_VI0_DATA2_VI0_B2, + GP_4_6_FN, FN_VI0_DATA1_VI0_B1, + GP_4_5_FN, FN_VI0_DATA0_VI0_B0, + GP_4_4_FN, FN_IP9_26_25, + GP_4_3_FN, FN_IP9_24_23, + GP_4_2_FN, FN_IP9_22_21, + GP_4_1_FN, FN_IP9_20_19, + GP_4_0_FN, FN_VI0_CLK } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP3_24_22, + GP_5_30_FN, FN_IP13_9_7, + GP_5_29_FN, FN_IP13_6_5, + GP_5_28_FN, FN_IP13_4_3, + GP_5_27_FN, FN_IP13_2_0, + GP_5_26_FN, FN_IP12_29_27, + GP_5_25_FN, FN_IP12_26_24, + GP_5_24_FN, FN_IP12_23_22, + GP_5_23_FN, FN_IP12_21_20, + GP_5_22_FN, FN_IP12_19_18, + GP_5_21_FN, FN_IP12_17_16, + GP_5_20_FN, FN_IP12_15_13, + GP_5_19_FN, FN_IP12_12_10, + GP_5_18_FN, FN_IP12_9_7, + GP_5_17_FN, FN_IP12_6_4, + GP_5_16_FN, FN_IP12_3_2, + GP_5_15_FN, FN_IP12_1_0, + GP_5_14_FN, FN_IP11_31_30, + GP_5_13_FN, FN_IP11_29_28, + GP_5_12_FN, FN_IP11_27, + GP_5_11_FN, FN_IP11_26, + GP_5_10_FN, FN_IP11_25, + GP_5_9_FN, FN_IP11_24, + GP_5_8_FN, FN_IP11_23, + GP_5_7_FN, FN_IP11_22, + GP_5_6_FN, FN_IP11_21, + GP_5_5_FN, FN_IP11_20, + GP_5_4_FN, FN_IP11_19, + GP_5_3_FN, FN_IP11_18_17, + GP_5_2_FN, FN_IP11_16_15, + GP_5_1_FN, FN_IP11_14_12, + GP_5_0_FN, FN_IP11_11_9 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + GP_6_31_FN, FN_DU0_DOTCLKIN, + GP_6_30_FN, FN_USB1_OVC, + GP_6_29_FN, FN_IP14_31_29, + GP_6_28_FN, FN_IP14_28_26, + GP_6_27_FN, FN_IP14_25_23, + GP_6_26_FN, FN_IP14_22_20, + GP_6_25_FN, FN_IP14_19_17, + GP_6_24_FN, FN_IP14_16_14, + GP_6_23_FN, FN_IP14_13_11, + GP_6_22_FN, FN_IP14_10_8, + GP_6_21_FN, FN_IP14_7, + GP_6_20_FN, FN_IP14_6, + GP_6_19_FN, FN_IP14_5, + GP_6_18_FN, FN_IP14_4, + GP_6_17_FN, FN_IP14_3, + GP_6_16_FN, FN_IP14_2, + GP_6_15_FN, FN_IP14_1_0, + GP_6_14_FN, FN_IP13_30_28, + GP_6_13_FN, FN_IP13_27, + GP_6_12_FN, FN_IP13_26, + GP_6_11_FN, FN_IP13_25, + GP_6_10_FN, FN_IP13_24_23, + GP_6_9_FN, FN_IP13_22, + GP_6_8_FN, FN_SD1_CLK, + GP_6_7_FN, FN_IP13_21_19, + GP_6_6_FN, FN_IP13_18_16, + GP_6_5_FN, FN_IP13_15, + GP_6_4_FN, FN_IP13_14, + GP_6_3_FN, FN_IP13_13, + GP_6_2_FN, FN_IP13_12, + GP_6_1_FN, FN_IP13_11, + GP_6_0_FN, FN_IP13_10 } + }, + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_FN, FN_USB1_PWEN, + GP_7_24_FN, FN_USB0_OVC, + GP_7_23_FN, FN_USB0_PWEN, + GP_7_22_FN, FN_IP15_14_12, + GP_7_21_FN, FN_IP15_11_9, + GP_7_20_FN, FN_IP15_8_6, + GP_7_19_FN, FN_IP7_2_0, + GP_7_18_FN, FN_IP6_29_27, + GP_7_17_FN, FN_IP6_26_24, + GP_7_16_FN, FN_IP6_23_21, + GP_7_15_FN, FN_IP6_20_19, + GP_7_14_FN, FN_IP6_18_16, + GP_7_13_FN, FN_IP6_15_14, + GP_7_12_FN, FN_IP6_13_12, + GP_7_11_FN, FN_IP6_11_10, + GP_7_10_FN, FN_IP6_9_8, + GP_7_9_FN, FN_IP16_11_10, + GP_7_8_FN, FN_IP16_9_8, + GP_7_7_FN, FN_IP16_7_6, + GP_7_6_FN, FN_IP16_5_3, + GP_7_5_FN, FN_IP16_2_0, + GP_7_4_FN, FN_IP15_29_27, + GP_7_3_FN, FN_IP15_26_24, + GP_7_2_FN, FN_IP15_23_21, + GP_7_1_FN, FN_IP15_20_18, + GP_7_0_FN, FN_IP15_17_15 } + }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, + 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP0_31 [1] */ + 0, 0, + /* IP0_30_29 [2] */ + FN_A6, FN_MSIOF1_SCK, + 0, 0, + /* IP0_28_27 [2] */ + FN_A5, FN_MSIOF0_RXD_B, + 0, 0, + /* IP0_26_25 [2] */ + FN_A4, FN_MSIOF0_TXD_B, + 0, 0, + /* IP0_24_23 [2] */ + FN_A3, FN_MSIOF0_SS2_B, + 0, 0, + /* IP0_22_21 [2] */ + FN_A2, FN_MSIOF0_SS1_B, + 0, 0, + /* IP0_20_19 [2] */ + FN_A1, FN_MSIOF0_SYNC_B, + 0, 0, + /* IP0_18_16 [3] */ + FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B, + 0, 0, 0, + /* IP0_15 [1] */ + FN_D15, 0, + /* IP0_14 [1] */ + FN_D14, 0, + /* IP0_13 [1] */ + FN_D13, 0, + /* IP0_12 [1] */ + FN_D12, 0, + /* IP0_11 [1] */ + FN_D11, 0, + /* IP0_10 [1] */ + FN_D10, 0, + /* IP0_9 [1] */ + FN_D9, 0, + /* IP0_8 [1] */ + FN_D8, 0, + /* IP0_7 [1] */ + FN_D7, 0, + /* IP0_6 [1] */ + FN_D6, 0, + /* IP0_5 [1] */ + FN_D5, 0, + /* IP0_4 [1] */ + FN_D4, 0, + /* IP0_3 [1] */ + FN_D3, 0, + /* IP0_2 [1] */ + FN_D2, 0, + /* IP0_1 [1] */ + FN_D1, 0, + /* IP0_0 [1] */ + FN_D0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, + 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + /* IP1_31_29 [3] */ + FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, + 0, 0, 0, + /* IP1_28_26 [3] */ + FN_A17, FN_DACK2_B, 0, FN_SDA0_C, + 0, 0, 0, 0, + /* IP1_25_23 [3] */ + FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B, + 0, 0, 0, + /* IP1_22_20 [3] */ + FN_A15, FN_BPFCLK_C, + 0, 0, 0, 0, 0, 0, + /* IP1_19_17 [3] */ + FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, + 0, 0, 0, + /* IP1_16_14 [3] */ + FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, + 0, 0, 0, 0, + /* IP1_13_11 [3] */ + FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D, + 0, 0, 0, 0, + /* IP1_10_8 [3] */ + FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D, + 0, 0, 0, 0, + /* IP1_7_6 [2] */ + FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D, + /* IP1_5_4 [2] */ + FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0, + /* IP1_3_2 [2] */ + FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0, + /* IP1_1_0 [2] */ + FN_A7, FN_MSIOF1_SYNC, + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, + 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) { + /* IP2_31_20 [2] */ + 0, 0, 0, 0, + /* IP2_29_27 [3] */ + FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, + FN_ATAG0_N, 0, FN_EX_WAIT1, + 0, 0, + /* IP2_26_25 [2] */ + FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0, + /* IP2_24_23 [2] */ + FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0, + /* IP2_22_21 [2] */ + FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0, + /* IP2_20_19 [2] */ + FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0, + /* IP2_18_16 [3] */ + FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, + 0, 0, + /* IP2_15_13 [3] */ + FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, + 0, 0, 0, + /* IP2_12_0 [3] */ + FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, + 0, 0, 0, + /* IP2_9_7 [3] */ + FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, + 0, 0, 0, + /* IP2_6_5 [2] */ + FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0, + /* IP2_4_3 [2] */ + FN_A20, FN_SPCLK, 0, 0, + /* IP2_2_0 [3] */ + FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0, + FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, + 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) { + /* IP3_31 [1] */ + 0, 0, + /* IP3_30_28 [3] */ + FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, + FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, + 0, 0, 0, + /* IP3_27_25 [3] */ + FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, + FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, + 0, 0, 0, + /* IP3_24_22 [3] */ + FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, + FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, + /* IP3_21_20 [2] */ + FN_DACK0, FN_DRACK0, FN_REMOCON, 0, + /* IP3_19_18 [2] */ + FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0, + /* IP3_17_16 [2] */ + FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0, + /* IP3_15_14 [2] */ + FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, + /* IP3_13_12 [2] */ + FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0, + /* IP3_11_9 [3] */ + FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, + 0, 0, 0, + /* IP3_8_6 [3] */ + FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, + FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0, + /* IP3_5_3 [3] */ + FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B, + FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0, + /* IP3_2_0 [3] */ + FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, + 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) { + /* IP4_31 [1] */ + 0, 0, + /* IP4_30_28 [3] */ + FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, + FN_MSIOF2_SYNC_D, FN_VI1_R2_B, + 0, 0, + /* IP4_27_26 [2] */ + FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0, + /* IP4_25_24 [2] */ + FN_SSI_WS4, FN_GLO_RFON_D, 0, 0, + /* IP4_23_22 [2] */ + FN_SSI_SCK4, FN_GLO_SS_D, 0, 0, + /* IP4_21 [1] */ + FN_SSI_SDATA3, 0, + /* IP4_20 [1] */ + FN_SSI_WS34, 0, + /* IP4_19 [1] */ + FN_SSI_SCK34, 0, + /* IP4_18_16 [3] */ + FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, + 0, 0, 0, 0, + /* IP4_15_13 [3] */ + FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E, + FN_GLO_Q1_D, FN_HCTS1_N_E, + 0, 0, + /* IP4_12_10 [3] */ + FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, + 0, 0, 0, + /* IP4_9_8 [2] */ + FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C, + /* IP4_7_5 [3] */ + FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, + 0, 0, 0, + /* IP4_4_2 [3] */ + FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, + FN_MSIOF2_SYNC_C, FN_GLO_I0_D, + 0, 0, 0, + /* IP4_1_0 [2] */ + FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, + 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) { + /* IP5_31_29 [3] */ + FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, + 0, 0, 0, 0, 0, + /* IP5_28_26 [3] */ + FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, + 0, 0, 0, 0, + /* IP5_25_24 [2] */ + FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0, + /* IP5_23_22 [2] */ + FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0, + /* IP5_21_20 [2] */ + FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0, + /* IP5_19_17 [3] */ + FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, + 0, 0, 0, 0, + /* IP5_16_15 [2] */ + FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0, + /* IP5_14_12 [3] */ + FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, + 0, 0, 0, 0, + /* IP5_11_9 [3] */ + FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, + 0, 0, 0, 0, + /* IP5_8_6 [3] */ + FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, + FN_MSIOF2_RXD_D, FN_VI1_R5_B, + 0, 0, + /* IP5_5_3 [3] */ + FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, + FN_MSIOF2_SS1_D, FN_VI1_R4_B, + 0, 0, + /* IP5_2_0 [3] */ + FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, + FN_MSIOF2_TXD_D, FN_VI1_R3_B, + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) { + /* IP6_31_30 [2] */ + 0, 0, 0, 0, + /* IP6_29_27 [3] */ + FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, + FN_GPS_SIGN_C, FN_GPS_SIGN_D, + 0, 0, 0, + /* IP6_26_24 [3] */ + FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, + FN_GPS_CLK_C, FN_GPS_CLK_D, + 0, 0, 0, + /* IP6_23_21 [3] */ + FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, + FN_SDA1_E, FN_MSIOF2_SYNC_E, + 0, 0, 0, + /* IP6_20_19 [2] */ + FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, + /* IP6_18_16 [3] */ + FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + 0, 0, 0, + /* IP6_15_14 [2] */ + FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + /* IP6_13_12 [2] */ + FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, + /* IP6_11_10 [2] */ + FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, + /* IP6_9_8 [2] */ + FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, + /* IP6_7_6 [2] */ + FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, + /* IP6_5_3 [3] */ + FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, + FN_SCIFA2_RXD, FN_FMIN_E, + 0, 0, + /* IP6_2_0 [3] */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, + FN_SCIF_CLK, 0, FN_BPFCLK_E, + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) { + /* IP7_31_30 [2] */ + 0, 0, 0, 0, + /* IP7_29_27 [3] */ + FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, + FN_SCIFA1_SCK, FN_SSI_SCK78_B, + 0, 0, + /* IP7_26_24 [3] */ + FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, + FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, + 0, 0, + /* IP7_23_21 [3] */ + FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, + FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, + 0, 0, + /* IP7_20_19 [2] */ + FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0, + /* IP7_18_17 [2] */ + FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0, + /* IP7_16_15 [2] */ + FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0, + /* IP7_14_13 [2] */ + FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0, + /* IP7_12_11 [2] */ + FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0, + /* IP7_10_9 [2] */ + FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0, + /* IP7_8_6 [3] */ + FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, + FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, + 0, 0, + /* IP7_5_3 [3] */ + FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, + FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, + 0, 0, + /* IP7_2_0 [3] */ + FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, + FN_SCIF_CLK_B, FN_GPS_MAG_D, + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP8_31 [1] */ + 0, 0, + /* IP8_30_28 [3] */ + FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, + 0, 0, 0, + /* IP8_27_26 [2] */ + FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, + /* IP8_25_24 [2] */ + FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0, + /* IP8_23_21 [3] */ + FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, + FN_SCIFA2_SCK, FN_SSI_SDATA9_B, + 0, 0, + /* IP8_20_18 [3] */ + FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, + FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, + 0, 0, + /* IP8_17_15 [3] */ + FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, + FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, + 0, 0, + /* IP8_14_12 [3] */ + FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, + FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, + 0, 0, 0, + /* IP8_11_9 [3] */ + FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, + FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, + 0, 0, 0, + /* IP8_8_6 [3] */ + FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, + FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, + 0, 0, + /* IP8_5_3 [3] */ + FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, + FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, + 0, 0, + /* IP8_2_0 [3] */ + FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, + 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) { + /* IP9_31_29 [3] */ + FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4, + FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, + /* IP9_28_27 [2] */ + FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0, + /* IP9_26_25 [2] */ + FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, + /* IP9_24_23 [2] */ + FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, + /* IP9_22_21 [2] */ + FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, + /* IP9_20_19 [2] */ + FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, + /* IP9_18_17 [2] */ + FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0, + /* IP9_16 [1] */ + FN_DU1_DISP, FN_QPOLA, + /* IP9_15_13 [3] */ + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_CAN0_RX, FN_RX3_B, FN_SDA2_B, + 0, 0, 0, + /* IP9_12 [1] */ + FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, + /* IP9_11 [1] */ + FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, + /* IP9_10_8 [3] */ + FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, + FN_TX3_B, FN_SCL2_B, FN_PWM4, + 0, 0, + /* IP9_7 [1] */ + FN_DU1_DOTCLKOUT0, FN_QCLK, + /* IP9_6 [1] */ + FN_DU1_DOTCLKIN, FN_QSTVA_QVS, + /* IP9_5_3 [3] */ + FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, + FN_SCIF3_SCK, FN_SCIFA3_SCK, + 0, 0, 0, + /* IP9_2_0 [3] */ + FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, + 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) { + /* IP10_31_29 [3] */ + FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D, + 0, 0, 0, + /* IP10_28_27 [2] */ + FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, + /* IP10_26_25 [2] */ + FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, + /* IP10_24_22 [3] */ + FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N, + 0, 0, 0, + /* IP10_21_29 [3] */ + FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, + FN_TS_SDATA0_C, FN_ATACS11_N, + 0, 0, 0, + /* IP10_18_17 [2] */ + FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0, + /* IP10_16_15 [2] */ + FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0, + /* IP10_14_12 [3] */ + FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, + FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0, + /* IP10_11_9 [3] */ + FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, + FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, + 0, 0, + /* IP10_8_6 [3] */ + FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B, + FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0, + /* IP10_5_3 [3] */ + FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B, + FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, + /* IP10_2_0 [3] */ + FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4, + FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 3, 3, 3, 3, 3) { + /* IP11_31_30 [2] */ + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0, + /* IP11_29_28 [2] */ + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0, + /* IP11_27 [1] */ + FN_VI1_DATA7, FN_AVB_MDC, + /* IP11_26 [1] */ + FN_VI1_DATA6, FN_AVB_MAGIC, + /* IP11_25 [1] */ + FN_VI1_DATA5, FN_AVB_RX_DV, + /* IP11_24 [1] */ + FN_VI1_DATA4, FN_AVB_MDIO, + /* IP11_23 [1] */ + FN_VI1_DATA3, FN_AVB_RX_ER, + /* IP11_22 [1] */ + FN_VI1_DATA2, FN_AVB_RXD7, + /* IP11_21 [1] */ + FN_VI1_DATA1, FN_AVB_RXD6, + /* IP11_20 [1] */ + FN_VI1_DATA0, FN_AVB_RXD5, + /* IP11_19 [1] */ + FN_VI1_CLK, FN_AVB_RXD4, + /* IP11_18_17 [2] */ + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, + /* IP11_16_15 [2] */ + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, + /* IP11_14_12 [3] */ + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, + FN_RX4_B, FN_SCIFA4_RXD_B, + 0, 0, 0, + /* IP11_11_9 [3] */ + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, + FN_TX4_B, FN_SCIFA4_TXD_B, + 0, 0, 0, + /* IP11_8_6 [3] */ + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, + /* IP11_5_3 [3] */ + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + 0, 0, 0, + /* IP11_2_0 [3] */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { + /* IP12_31_30 [2] */ + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + 0, 0, 0, + /* IP12_26_24 [3] */ + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + 0, 0, 0, + /* IP12_23_22 [2] */ + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, + /* IP12_21_20 [2] */ + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, + /* IP12_19_18 [2] */ + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, + /* IP12_17_16 [2] */ + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + /* IP12_15_13 [3] */ + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + 0, 0, 0, + /* IP12_12_10 [3] */ + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + 0, 0, 0, + /* IP12_9_7 [3] */ + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, + FN_SDA2_D, FN_MSIOF1_SCK_E, + 0, 0, 0, + /* IP12_6_4 [3] */ + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + 0, 0, 0, + /* IP12_3_2 [2] */ + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + /* IP12_1_0 [2] */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, + 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, + 3, 2, 2, 3) { + /* IP13_31 [1] */ + 0, 0, + /* IP13_30_28 [3] */ + FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, + 0, 0, 0, 0, + /* IP13_27 [1] */ + FN_SD1_DATA3, FN_IERX_B, + /* IP13_26 [1] */ + FN_SD1_DATA2, FN_IECLK_B, + /* IP13_25 [1] */ + FN_SD1_DATA1, FN_IETX_B, + /* IP13_24_23 [2] */ + FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0, + /* IP13_22 [1] */ + FN_SD1_CMD, FN_REMOCON_B, + /* IP13_21_19 [3] */ + FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, + FN_SCIFA5_RXD_B, FN_RX3_C, + 0, 0, + /* IP13_18_16 [3] */ + FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, + FN_SCIFA5_TXD_B, FN_TX3_C, + 0, 0, + /* IP13_15 [1] */ + FN_SD0_DATA3, FN_SSL_B, + /* IP13_14 [1] */ + FN_SD0_DATA2, FN_IO3_B, + /* IP13_13 [1] */ + FN_SD0_DATA1, FN_IO2_B, + /* IP13_12 [1] */ + FN_SD0_DATA0, FN_MISO_IO1_B, + /* IP13_11 [1] */ + FN_SD0_CMD, FN_MOSI_IO0_B, + /* IP13_10 [1] */ + FN_SD0_CLK, FN_SPCLK_B, + /* IP13_9_7 [3] */ + FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, + FN_ADICHS2_B, FN_MSIOF0_TXD_C, + 0, 0, 0, + /* IP13_6_5 [2] */ + FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, + /* IP13_4_3 [2] */ + FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, + /* IP13_2_0 [3] */ + FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, + FN_ADICLK_B, FN_MSIOF0_SS1_C, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, + 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) { + /* IP14_31_29 [3] */ + FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, + FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0, + /* IP14_28_26 [3] */ + FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, + FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0, + /* IP14_25_23 [3] */ + FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B, + 0, 0, 0, + /* IP14_22_20 [3] */ + FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B, + 0, 0, 0, + /* IP14_19_17 [3] */ + FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0, + FN_VI1_CLKENB_C, FN_VI1_G1_B, + 0, 0, + /* IP14_16_14 [3] */ + FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0, + FN_VI1_CLK_C, FN_VI1_G0_B, + 0, 0, + /* IP14_13_11 [3] */ + FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, + 0, 0, 0, + /* IP14_10_8 [3] */ + FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, + 0, 0, 0, + /* IP14_7 [1] */ + FN_SD2_DATA3, FN_MMC_D3, + /* IP14_6 [1] */ + FN_SD2_DATA2, FN_MMC_D2, + /* IP14_5 [1] */ + FN_SD2_DATA1, FN_MMC_D1, + /* IP14_4 [1] */ + FN_SD2_DATA0, FN_MMC_D0, + /* IP14_3 [1] */ + FN_SD2_CMD, FN_MMC_CMD, + /* IP14_2 [1] */ + FN_SD2_CLK, FN_MMC_CLK, + /* IP14_1_0 [2] */ + FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, + 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) { + /* IP15_31_30 [2] */ + 0, 0, 0, 0, + /* IP15_29_27 [3] */ + FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C, + FN_CAN0_TX_B, FN_VI1_DATA5_C, + 0, 0, + /* IP15_26_24 [3] */ + FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C, + FN_CAN0_RX_B, FN_VI1_DATA4_C, + 0, 0, + /* IP15_23_21 [3] */ + FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK, + FN_TCLK2, FN_VI1_DATA3_C, 0, + /* IP15_20_18 [3] */ + FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C, + 0, 0, 0, + /* IP15_17_15 [3] */ + FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C, + FN_TCLK1, FN_VI1_DATA1_C, + 0, 0, + /* IP15_14_12 [3] */ + FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, + FN_VI1_G7_B, FN_SCIFA3_SCK_C, + 0, 0, + /* IP15_11_9 [3] */ + FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, + FN_VI1_G6_B, FN_SCIFA3_RXD_C, + 0, 0, + /* IP15_8_6 [3] */ + FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, + FN_PWM5_B, FN_SCIFA3_TXD_C, + 0, 0, 0, + /* IP15_5_4 [2] */ + FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0, + /* IP15_3_2 [2] */ + FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, + /* IP15_1_0 [2] */ + FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, + 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) { + /* IP16_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_19_16 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_15_12 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_11_10 [2] */ + FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, + /* IP16_9_8 [2] */ + FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, + /* IP16_7_6 [2] */ + FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, + /* IP16_5_3 [3] */ + FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, + FN_GLO_SS_C, FN_VI1_DATA7_C, + 0, 0, 0, + /* IP16_2_0 [3] */ + FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, + FN_GLO_SDATA_C, FN_VI1_DATA6_C, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, + 3, 2, 2, 2, 1, 2, 2, 2) { + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, + FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, + FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + 0, 0, 0, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* SEL_SCFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_QSP [1] */ + FN_SEL_QSP_0, FN_SEL_QSP_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_HSCIF1 [3] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, + FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_VI1 [2] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_TMU [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_LBS [2] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF0 [2] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 3, 2, 1, 1, 2, 2, + 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { + /* SEL_SCIF0 [3] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, + FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF [1] */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + /* SEL_CAN0 [3] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + 0, 0, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIF4 [2] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_ADG [1] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, + FN_SEL_FM_3, FN_SEL_FM_4, + 0, 0, 0, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, + /* SEL_SCIFA3 [2] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, + /* SEL_SIM [1] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 2, 2, 2, 2, 2, + 1, 1, 2, 2, 3, 2, 2, 2, 1) { + /* SEL_HSCIF2 [2] */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + /* SEL_CANCLK [2] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + /* SEL_IIC8 [2] */ + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0, + /* SEL_IIC7 [2] */ + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0, + /* SEL_IIC4 [2] */ + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0, + /* SEL_IIC3 [2] */ + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + /* SEL_SCIF3 [2] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* SEL_MMC [1] */ + FN_SEL_MMC_0, FN_SEL_MMC_1, + /* SEL_SCIF5 [1] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [2] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + /* SEL_IIC1 [3] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + 0, 0, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, + 3, 2, 2, 1, 1, 1, 1, 3, 2, + 2, 3, 1, 1, 1, 2, 2, 2, 2) { + /* SEL_SOF1 [3] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + 0, 0, 0, + /* SEL_HSCIF0 [2] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, + /* SEL_DIS [2] */ + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIF2 [3] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_SOF2 [3] */ + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, + FN_SEL_SOF2_3, FN_SEL_SOF2_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI0 [1] */ + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + /* SEL_SSP [2] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7791_pinmux_info = { + .name = "r8a77910_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index 01b425dfd16..3bda7bafd0a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -272,8 +272,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { - +static const u16 pinmux_data[] = { /* PA */ PINMUX_DATA(PA7_DATA, PA7_IN), PINMUX_DATA(PA6_DATA, PA6_IN), @@ -703,377 +702,380 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), }; -static struct pinmux_gpio pinmux_gpios[] = { - +static const struct sh_pfc_pin pinmux_pins[] = { /* PA */ - PINMUX_GPIO(GPIO_PA7, PA7_DATA), - PINMUX_GPIO(GPIO_PA6, PA6_DATA), - PINMUX_GPIO(GPIO_PA5, PA5_DATA), - PINMUX_GPIO(GPIO_PA4, PA4_DATA), - PINMUX_GPIO(GPIO_PA3, PA3_DATA), - PINMUX_GPIO(GPIO_PA2, PA2_DATA), - PINMUX_GPIO(GPIO_PA1, PA1_DATA), - PINMUX_GPIO(GPIO_PA0, PA0_DATA), + PINMUX_GPIO(PA7), + PINMUX_GPIO(PA6), + PINMUX_GPIO(PA5), + PINMUX_GPIO(PA4), + PINMUX_GPIO(PA3), + PINMUX_GPIO(PA2), + PINMUX_GPIO(PA1), + PINMUX_GPIO(PA0), /* PB */ - PINMUX_GPIO(GPIO_PB12, PB12_DATA), - PINMUX_GPIO(GPIO_PB11, PB11_DATA), - PINMUX_GPIO(GPIO_PB10, PB10_DATA), - PINMUX_GPIO(GPIO_PB9, PB9_DATA), - PINMUX_GPIO(GPIO_PB8, PB8_DATA), - PINMUX_GPIO(GPIO_PB7, PB7_DATA), - PINMUX_GPIO(GPIO_PB6, PB6_DATA), - PINMUX_GPIO(GPIO_PB5, PB5_DATA), - PINMUX_GPIO(GPIO_PB4, PB4_DATA), - PINMUX_GPIO(GPIO_PB3, PB3_DATA), - PINMUX_GPIO(GPIO_PB2, PB2_DATA), - PINMUX_GPIO(GPIO_PB1, PB1_DATA), - PINMUX_GPIO(GPIO_PB0, PB0_DATA), + PINMUX_GPIO(PB12), + PINMUX_GPIO(PB11), + PINMUX_GPIO(PB10), + PINMUX_GPIO(PB9), + PINMUX_GPIO(PB8), + PINMUX_GPIO(PB7), + PINMUX_GPIO(PB6), + PINMUX_GPIO(PB5), + PINMUX_GPIO(PB4), + PINMUX_GPIO(PB3), + PINMUX_GPIO(PB2), + PINMUX_GPIO(PB1), + PINMUX_GPIO(PB0), /* PC */ - PINMUX_GPIO(GPIO_PC14, PC14_DATA), - PINMUX_GPIO(GPIO_PC13, PC13_DATA), - PINMUX_GPIO(GPIO_PC12, PC12_DATA), - PINMUX_GPIO(GPIO_PC11, PC11_DATA), - PINMUX_GPIO(GPIO_PC10, PC10_DATA), - PINMUX_GPIO(GPIO_PC9, PC9_DATA), - PINMUX_GPIO(GPIO_PC8, PC8_DATA), - PINMUX_GPIO(GPIO_PC7, PC7_DATA), - PINMUX_GPIO(GPIO_PC6, PC6_DATA), - PINMUX_GPIO(GPIO_PC5, PC5_DATA), - PINMUX_GPIO(GPIO_PC4, PC4_DATA), - PINMUX_GPIO(GPIO_PC3, PC3_DATA), - PINMUX_GPIO(GPIO_PC2, PC2_DATA), - PINMUX_GPIO(GPIO_PC1, PC1_DATA), - PINMUX_GPIO(GPIO_PC0, PC0_DATA), + PINMUX_GPIO(PC14), + PINMUX_GPIO(PC13), + PINMUX_GPIO(PC12), + PINMUX_GPIO(PC11), + PINMUX_GPIO(PC10), + PINMUX_GPIO(PC9), + PINMUX_GPIO(PC8), + PINMUX_GPIO(PC7), + PINMUX_GPIO(PC6), + PINMUX_GPIO(PC5), + PINMUX_GPIO(PC4), + PINMUX_GPIO(PC3), + PINMUX_GPIO(PC2), + PINMUX_GPIO(PC1), + PINMUX_GPIO(PC0), /* PD */ - PINMUX_GPIO(GPIO_PD15, PD15_DATA), - PINMUX_GPIO(GPIO_PD14, PD14_DATA), - PINMUX_GPIO(GPIO_PD13, PD13_DATA), - PINMUX_GPIO(GPIO_PD12, PD12_DATA), - PINMUX_GPIO(GPIO_PD11, PD11_DATA), - PINMUX_GPIO(GPIO_PD10, PD10_DATA), - PINMUX_GPIO(GPIO_PD9, PD9_DATA), - PINMUX_GPIO(GPIO_PD8, PD8_DATA), - PINMUX_GPIO(GPIO_PD7, PD7_DATA), - PINMUX_GPIO(GPIO_PD6, PD6_DATA), - PINMUX_GPIO(GPIO_PD5, PD5_DATA), - PINMUX_GPIO(GPIO_PD4, PD4_DATA), - PINMUX_GPIO(GPIO_PD3, PD3_DATA), - PINMUX_GPIO(GPIO_PD2, PD2_DATA), - PINMUX_GPIO(GPIO_PD1, PD1_DATA), - PINMUX_GPIO(GPIO_PD0, PD0_DATA), + PINMUX_GPIO(PD15), + PINMUX_GPIO(PD14), + PINMUX_GPIO(PD13), + PINMUX_GPIO(PD12), + PINMUX_GPIO(PD11), + PINMUX_GPIO(PD10), + PINMUX_GPIO(PD9), + PINMUX_GPIO(PD8), + PINMUX_GPIO(PD7), + PINMUX_GPIO(PD6), + PINMUX_GPIO(PD5), + PINMUX_GPIO(PD4), + PINMUX_GPIO(PD3), + PINMUX_GPIO(PD2), + PINMUX_GPIO(PD1), + PINMUX_GPIO(PD0), /* PE */ - PINMUX_GPIO(GPIO_PE15, PE15_DATA), - PINMUX_GPIO(GPIO_PE14, PE14_DATA), - PINMUX_GPIO(GPIO_PE13, PE13_DATA), - PINMUX_GPIO(GPIO_PE12, PE12_DATA), - PINMUX_GPIO(GPIO_PE11, PE11_DATA), - PINMUX_GPIO(GPIO_PE10, PE10_DATA), - PINMUX_GPIO(GPIO_PE9, PE9_DATA), - PINMUX_GPIO(GPIO_PE8, PE8_DATA), - PINMUX_GPIO(GPIO_PE7, PE7_DATA), - PINMUX_GPIO(GPIO_PE6, PE6_DATA), - PINMUX_GPIO(GPIO_PE5, PE5_DATA), - PINMUX_GPIO(GPIO_PE4, PE4_DATA), - PINMUX_GPIO(GPIO_PE3, PE3_DATA), - PINMUX_GPIO(GPIO_PE2, PE2_DATA), - PINMUX_GPIO(GPIO_PE1, PE1_DATA), - PINMUX_GPIO(GPIO_PE0, PE0_DATA), + PINMUX_GPIO(PE15), + PINMUX_GPIO(PE14), + PINMUX_GPIO(PE13), + PINMUX_GPIO(PE12), + PINMUX_GPIO(PE11), + PINMUX_GPIO(PE10), + PINMUX_GPIO(PE9), + PINMUX_GPIO(PE8), + PINMUX_GPIO(PE7), + PINMUX_GPIO(PE6), + PINMUX_GPIO(PE5), + PINMUX_GPIO(PE4), + PINMUX_GPIO(PE3), + PINMUX_GPIO(PE2), + PINMUX_GPIO(PE1), + PINMUX_GPIO(PE0), /* PF */ - PINMUX_GPIO(GPIO_PF30, PF30_DATA), - PINMUX_GPIO(GPIO_PF29, PF29_DATA), - PINMUX_GPIO(GPIO_PF28, PF28_DATA), - PINMUX_GPIO(GPIO_PF27, PF27_DATA), - PINMUX_GPIO(GPIO_PF26, PF26_DATA), - PINMUX_GPIO(GPIO_PF25, PF25_DATA), - PINMUX_GPIO(GPIO_PF24, PF24_DATA), - PINMUX_GPIO(GPIO_PF23, PF23_DATA), - PINMUX_GPIO(GPIO_PF22, PF22_DATA), - PINMUX_GPIO(GPIO_PF21, PF21_DATA), - PINMUX_GPIO(GPIO_PF20, PF20_DATA), - PINMUX_GPIO(GPIO_PF19, PF19_DATA), - PINMUX_GPIO(GPIO_PF18, PF18_DATA), - PINMUX_GPIO(GPIO_PF17, PF17_DATA), - PINMUX_GPIO(GPIO_PF16, PF16_DATA), - PINMUX_GPIO(GPIO_PF15, PF15_DATA), - PINMUX_GPIO(GPIO_PF14, PF14_DATA), - PINMUX_GPIO(GPIO_PF13, PF13_DATA), - PINMUX_GPIO(GPIO_PF12, PF12_DATA), - PINMUX_GPIO(GPIO_PF11, PF11_DATA), - PINMUX_GPIO(GPIO_PF10, PF10_DATA), - PINMUX_GPIO(GPIO_PF9, PF9_DATA), - PINMUX_GPIO(GPIO_PF8, PF8_DATA), - PINMUX_GPIO(GPIO_PF7, PF7_DATA), - PINMUX_GPIO(GPIO_PF6, PF6_DATA), - PINMUX_GPIO(GPIO_PF5, PF5_DATA), - PINMUX_GPIO(GPIO_PF4, PF4_DATA), - PINMUX_GPIO(GPIO_PF3, PF3_DATA), - PINMUX_GPIO(GPIO_PF2, PF2_DATA), - PINMUX_GPIO(GPIO_PF1, PF1_DATA), - PINMUX_GPIO(GPIO_PF0, PF0_DATA), + PINMUX_GPIO(PF30), + PINMUX_GPIO(PF29), + PINMUX_GPIO(PF28), + PINMUX_GPIO(PF27), + PINMUX_GPIO(PF26), + PINMUX_GPIO(PF25), + PINMUX_GPIO(PF24), + PINMUX_GPIO(PF23), + PINMUX_GPIO(PF22), + PINMUX_GPIO(PF21), + PINMUX_GPIO(PF20), + PINMUX_GPIO(PF19), + PINMUX_GPIO(PF18), + PINMUX_GPIO(PF17), + PINMUX_GPIO(PF16), + PINMUX_GPIO(PF15), + PINMUX_GPIO(PF14), + PINMUX_GPIO(PF13), + PINMUX_GPIO(PF12), + PINMUX_GPIO(PF11), + PINMUX_GPIO(PF10), + PINMUX_GPIO(PF9), + PINMUX_GPIO(PF8), + PINMUX_GPIO(PF7), + PINMUX_GPIO(PF6), + PINMUX_GPIO(PF5), + PINMUX_GPIO(PF4), + PINMUX_GPIO(PF3), + PINMUX_GPIO(PF2), + PINMUX_GPIO(PF1), + PINMUX_GPIO(PF0), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* INTC */ - PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK), - PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), - - PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), - PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK), - PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK), + GPIO_FN(PINT7_PB), + GPIO_FN(PINT6_PB), + GPIO_FN(PINT5_PB), + GPIO_FN(PINT4_PB), + GPIO_FN(PINT3_PB), + GPIO_FN(PINT2_PB), + GPIO_FN(PINT1_PB), + GPIO_FN(PINT0_PB), + GPIO_FN(PINT7_PD), + GPIO_FN(PINT6_PD), + GPIO_FN(PINT5_PD), + GPIO_FN(PINT4_PD), + GPIO_FN(PINT3_PD), + GPIO_FN(PINT2_PD), + GPIO_FN(PINT1_PD), + GPIO_FN(PINT0_PD), + GPIO_FN(IRQ7_PB), + GPIO_FN(IRQ6_PB), + GPIO_FN(IRQ5_PB), + GPIO_FN(IRQ4_PB), + GPIO_FN(IRQ3_PB), + GPIO_FN(IRQ2_PB), + GPIO_FN(IRQ1_PB), + GPIO_FN(IRQ0_PB), + GPIO_FN(IRQ7_PD), + GPIO_FN(IRQ6_PD), + GPIO_FN(IRQ5_PD), + GPIO_FN(IRQ4_PD), + GPIO_FN(IRQ3_PD), + GPIO_FN(IRQ2_PD), + GPIO_FN(IRQ1_PD), + GPIO_FN(IRQ0_PD), + GPIO_FN(IRQ7_PE), + GPIO_FN(IRQ6_PE), + GPIO_FN(IRQ5_PE), + GPIO_FN(IRQ4_PE), + GPIO_FN(IRQ3_PE), + GPIO_FN(IRQ2_PE), + GPIO_FN(IRQ1_PE), + GPIO_FN(IRQ0_PE), + + GPIO_FN(WDTOVF), + GPIO_FN(IRQOUT), + GPIO_FN(REFOUT), + GPIO_FN(IRQOUT_REFOUT), + GPIO_FN(UBCTRG), /* CAN */ - PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), - PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), - PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), + GPIO_FN(CTX1), + GPIO_FN(CRX1), + GPIO_FN(CTX0), + GPIO_FN(CTX0_CTX1), + GPIO_FN(CRX0), + GPIO_FN(CRX0_CRX1), /* IIC3 */ - PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), - PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), - PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), - PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), - PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), - PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), - PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), - PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + GPIO_FN(SDA3), + GPIO_FN(SCL3), + GPIO_FN(SDA2), + GPIO_FN(SCL2), + GPIO_FN(SDA1), + GPIO_FN(SCL1), + GPIO_FN(SDA0), + GPIO_FN(SCL0), /* DMAC */ - PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK), - PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK), - PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK), - PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK), - PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK), - PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK), - PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK), - PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), + GPIO_FN(TEND0_PD), + GPIO_FN(TEND0_PE), + GPIO_FN(DACK0_PD), + GPIO_FN(DACK0_PE), + GPIO_FN(DREQ0_PD), + GPIO_FN(DREQ0_PE), + GPIO_FN(TEND1_PD), + GPIO_FN(TEND1_PE), + GPIO_FN(DACK1_PD), + GPIO_FN(DACK1_PE), + GPIO_FN(DREQ1_PD), + GPIO_FN(DREQ1_PE), + GPIO_FN(DACK2), + GPIO_FN(DREQ2), + GPIO_FN(DACK3), + GPIO_FN(DREQ3), /* ADC */ - PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK), + GPIO_FN(ADTRG_PD), + GPIO_FN(ADTRG_PE), /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), - PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), - PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), - PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK), - PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK), - PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK), - PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK), - PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK), - PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK), - PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), - PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), - PINMUX_GPIO(GPIO_FN_A1, A1_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), - PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(CS4), + GPIO_FN(MRES), + GPIO_FN(BS), + GPIO_FN(IOIS16), + GPIO_FN(CS1), + GPIO_FN(CS6_CE1B), + GPIO_FN(CE2B), + GPIO_FN(CS5_CE1A), + GPIO_FN(CE2A), + GPIO_FN(FRAME), + GPIO_FN(WAIT), + GPIO_FN(RDWR), + GPIO_FN(CKE), + GPIO_FN(CASU), + GPIO_FN(BREQ), + GPIO_FN(RASU), + GPIO_FN(BACK), + GPIO_FN(CASL), + GPIO_FN(RASL), + GPIO_FN(WE3_DQMUU_AH_ICIO_WR), + GPIO_FN(WE2_DQMUL_ICIORD), + GPIO_FN(WE1_DQMLU_WE), + GPIO_FN(WE0_DQMLL), + GPIO_FN(CS3), + GPIO_FN(CS2), + GPIO_FN(A1), + GPIO_FN(A0), + GPIO_FN(CS7), /* TMU */ - PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), - PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK), - PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK), - PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK), - PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK), + GPIO_FN(TIOC4D), + GPIO_FN(TIOC4C), + GPIO_FN(TIOC4B), + GPIO_FN(TIOC4A), + GPIO_FN(TIOC3D), + GPIO_FN(TIOC3C), + GPIO_FN(TIOC3B), + GPIO_FN(TIOC3A), + GPIO_FN(TIOC2B), + GPIO_FN(TIOC1B), + GPIO_FN(TIOC2A), + GPIO_FN(TIOC1A), + GPIO_FN(TIOC0D), + GPIO_FN(TIOC0C), + GPIO_FN(TIOC0B), + GPIO_FN(TIOC0A), + GPIO_FN(TCLKD_PD), + GPIO_FN(TCLKC_PD), + GPIO_FN(TCLKB_PD), + GPIO_FN(TCLKA_PD), + GPIO_FN(TCLKD_PF), + GPIO_FN(TCLKC_PF), + GPIO_FN(TCLKB_PF), + GPIO_FN(TCLKA_PF), /* SSU */ - PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK), - PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK), - PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK), - PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK), - PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK), - PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK), + GPIO_FN(SCS0_PD), + GPIO_FN(SSO0_PD), + GPIO_FN(SSI0_PD), + GPIO_FN(SSCK0_PD), + GPIO_FN(SCS0_PF), + GPIO_FN(SSO0_PF), + GPIO_FN(SSI0_PF), + GPIO_FN(SSCK0_PF), + GPIO_FN(SCS1_PD), + GPIO_FN(SSO1_PD), + GPIO_FN(SSI1_PD), + GPIO_FN(SSCK1_PD), + GPIO_FN(SCS1_PF), + GPIO_FN(SSO1_PF), + GPIO_FN(SSI1_PF), + GPIO_FN(SSCK1_PF), /* SCIF */ - PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), - PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), - PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), - PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), - PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + GPIO_FN(TXD0), + GPIO_FN(RXD0), + GPIO_FN(SCK0), + GPIO_FN(TXD1), + GPIO_FN(RXD1), + GPIO_FN(SCK1), + GPIO_FN(TXD2), + GPIO_FN(RXD2), + GPIO_FN(SCK2), + GPIO_FN(RTS3), + GPIO_FN(CTS3), + GPIO_FN(TXD3), + GPIO_FN(RXD3), + GPIO_FN(SCK3), /* SSI */ - PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), + GPIO_FN(AUDIO_CLK), + GPIO_FN(SSIDATA3), + GPIO_FN(SSIWS3), + GPIO_FN(SSISCK3), + GPIO_FN(SSIDATA2), + GPIO_FN(SSIWS2), + GPIO_FN(SSISCK2), + GPIO_FN(SSIDATA1), + GPIO_FN(SSIWS1), + GPIO_FN(SSISCK1), + GPIO_FN(SSIDATA0), + GPIO_FN(SSIWS0), + GPIO_FN(SSISCK0), /* FLCTL */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), - PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), - PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), - PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), - PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), - PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), - PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), - PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), - PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), - PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), - PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), + GPIO_FN(FCE), + GPIO_FN(FRB), + GPIO_FN(NAF7), + GPIO_FN(NAF6), + GPIO_FN(NAF5), + GPIO_FN(NAF4), + GPIO_FN(NAF3), + GPIO_FN(NAF2), + GPIO_FN(NAF1), + GPIO_FN(NAF0), + GPIO_FN(FSC), + GPIO_FN(FOE), + GPIO_FN(FCDE), + GPIO_FN(FWE), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), - PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), + GPIO_FN(LCD_VEPWC), + GPIO_FN(LCD_VCPWC), + GPIO_FN(LCD_CLK), + GPIO_FN(LCD_FLM), + GPIO_FN(LCD_M_DISP), + GPIO_FN(LCD_CL2), + GPIO_FN(LCD_CL1), + GPIO_FN(LCD_DON), + GPIO_FN(LCD_DATA15), + GPIO_FN(LCD_DATA14), + GPIO_FN(LCD_DATA13), + GPIO_FN(LCD_DATA12), + GPIO_FN(LCD_DATA11), + GPIO_FN(LCD_DATA10), + GPIO_FN(LCD_DATA9), + GPIO_FN(LCD_DATA8), + GPIO_FN(LCD_DATA7), + GPIO_FN(LCD_DATA6), + GPIO_FN(LCD_DATA5), + GPIO_FN(LCD_DATA4), + GPIO_FN(LCD_DATA3), + GPIO_FN(LCD_DATA2), + GPIO_FN(LCD_DATA1), + GPIO_FN(LCD_DATA0), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) { 0, 0, 0, 0, @@ -1525,7 +1527,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) { 0, 0, 0, 0, 0, 0, 0, 0, @@ -1571,19 +1573,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7203_pinmux_info = { +const struct sh_pfc_soc_info sh7203_pinmux_info = { .name = "sh7203_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_LCD_DATA0, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 2ba5639dcf3..e1cb6dc0502 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -604,8 +604,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { - +static const u16 pinmux_data[] = { /* Port A */ PINMUX_DATA(PA3_DATA, PA3_IN), PINMUX_DATA(PA2_DATA, PA2_IN), @@ -1072,401 +1071,404 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SD_D2_MARK, PK0MD_10), }; -static struct pinmux_gpio pinmux_gpios[] = { - +static const struct sh_pfc_pin pinmux_pins[] = { /* Port A */ - PINMUX_GPIO(GPIO_PA3, PA3_DATA), - PINMUX_GPIO(GPIO_PA2, PA2_DATA), - PINMUX_GPIO(GPIO_PA1, PA1_DATA), - PINMUX_GPIO(GPIO_PA0, PA0_DATA), + PINMUX_GPIO(PA3), + PINMUX_GPIO(PA2), + PINMUX_GPIO(PA1), + PINMUX_GPIO(PA0), /* Port B */ - PINMUX_GPIO(GPIO_PB22, PB22_DATA), - PINMUX_GPIO(GPIO_PB21, PB21_DATA), - PINMUX_GPIO(GPIO_PB20, PB20_DATA), - PINMUX_GPIO(GPIO_PB19, PB19_DATA), - PINMUX_GPIO(GPIO_PB18, PB18_DATA), - PINMUX_GPIO(GPIO_PB17, PB17_DATA), - PINMUX_GPIO(GPIO_PB16, PB16_DATA), - PINMUX_GPIO(GPIO_PB15, PB15_DATA), - PINMUX_GPIO(GPIO_PB14, PB14_DATA), - PINMUX_GPIO(GPIO_PB13, PB13_DATA), - PINMUX_GPIO(GPIO_PB12, PB12_DATA), - PINMUX_GPIO(GPIO_PB11, PB11_DATA), - PINMUX_GPIO(GPIO_PB10, PB10_DATA), - PINMUX_GPIO(GPIO_PB9, PB9_DATA), - PINMUX_GPIO(GPIO_PB8, PB8_DATA), - PINMUX_GPIO(GPIO_PB7, PB7_DATA), - PINMUX_GPIO(GPIO_PB6, PB6_DATA), - PINMUX_GPIO(GPIO_PB5, PB5_DATA), - PINMUX_GPIO(GPIO_PB4, PB4_DATA), - PINMUX_GPIO(GPIO_PB3, PB3_DATA), - PINMUX_GPIO(GPIO_PB2, PB2_DATA), - PINMUX_GPIO(GPIO_PB1, PB1_DATA), + PINMUX_GPIO(PB22), + PINMUX_GPIO(PB21), + PINMUX_GPIO(PB20), + PINMUX_GPIO(PB19), + PINMUX_GPIO(PB18), + PINMUX_GPIO(PB17), + PINMUX_GPIO(PB16), + PINMUX_GPIO(PB15), + PINMUX_GPIO(PB14), + PINMUX_GPIO(PB13), + PINMUX_GPIO(PB12), + PINMUX_GPIO(PB11), + PINMUX_GPIO(PB10), + PINMUX_GPIO(PB9), + PINMUX_GPIO(PB8), + PINMUX_GPIO(PB7), + PINMUX_GPIO(PB6), + PINMUX_GPIO(PB5), + PINMUX_GPIO(PB4), + PINMUX_GPIO(PB3), + PINMUX_GPIO(PB2), + PINMUX_GPIO(PB1), /* Port C */ - PINMUX_GPIO(GPIO_PC10, PC10_DATA), - PINMUX_GPIO(GPIO_PC9, PC9_DATA), - PINMUX_GPIO(GPIO_PC8, PC8_DATA), - PINMUX_GPIO(GPIO_PC7, PC7_DATA), - PINMUX_GPIO(GPIO_PC6, PC6_DATA), - PINMUX_GPIO(GPIO_PC5, PC5_DATA), - PINMUX_GPIO(GPIO_PC4, PC4_DATA), - PINMUX_GPIO(GPIO_PC3, PC3_DATA), - PINMUX_GPIO(GPIO_PC2, PC2_DATA), - PINMUX_GPIO(GPIO_PC1, PC1_DATA), - PINMUX_GPIO(GPIO_PC0, PC0_DATA), + PINMUX_GPIO(PC10), + PINMUX_GPIO(PC9), + PINMUX_GPIO(PC8), + PINMUX_GPIO(PC7), + PINMUX_GPIO(PC6), + PINMUX_GPIO(PC5), + PINMUX_GPIO(PC4), + PINMUX_GPIO(PC3), + PINMUX_GPIO(PC2), + PINMUX_GPIO(PC1), + PINMUX_GPIO(PC0), /* Port D */ - PINMUX_GPIO(GPIO_PD15, PD15_DATA), - PINMUX_GPIO(GPIO_PD14, PD14_DATA), - PINMUX_GPIO(GPIO_PD13, PD13_DATA), - PINMUX_GPIO(GPIO_PD12, PD12_DATA), - PINMUX_GPIO(GPIO_PD11, PD11_DATA), - PINMUX_GPIO(GPIO_PD10, PD10_DATA), - PINMUX_GPIO(GPIO_PD9, PD9_DATA), - PINMUX_GPIO(GPIO_PD8, PD8_DATA), - PINMUX_GPIO(GPIO_PD7, PD7_DATA), - PINMUX_GPIO(GPIO_PD6, PD6_DATA), - PINMUX_GPIO(GPIO_PD5, PD5_DATA), - PINMUX_GPIO(GPIO_PD4, PD4_DATA), - PINMUX_GPIO(GPIO_PD3, PD3_DATA), - PINMUX_GPIO(GPIO_PD2, PD2_DATA), - PINMUX_GPIO(GPIO_PD1, PD1_DATA), - PINMUX_GPIO(GPIO_PD0, PD0_DATA), + PINMUX_GPIO(PD15), + PINMUX_GPIO(PD14), + PINMUX_GPIO(PD13), + PINMUX_GPIO(PD12), + PINMUX_GPIO(PD11), + PINMUX_GPIO(PD10), + PINMUX_GPIO(PD9), + PINMUX_GPIO(PD8), + PINMUX_GPIO(PD7), + PINMUX_GPIO(PD6), + PINMUX_GPIO(PD5), + PINMUX_GPIO(PD4), + PINMUX_GPIO(PD3), + PINMUX_GPIO(PD2), + PINMUX_GPIO(PD1), + PINMUX_GPIO(PD0), /* Port E */ - PINMUX_GPIO(GPIO_PE5, PE5_DATA), - PINMUX_GPIO(GPIO_PE4, PE4_DATA), - PINMUX_GPIO(GPIO_PE3, PE3_DATA), - PINMUX_GPIO(GPIO_PE2, PE2_DATA), - PINMUX_GPIO(GPIO_PE1, PE1_DATA), - PINMUX_GPIO(GPIO_PE0, PE0_DATA), + PINMUX_GPIO(PE5), + PINMUX_GPIO(PE4), + PINMUX_GPIO(PE3), + PINMUX_GPIO(PE2), + PINMUX_GPIO(PE1), + PINMUX_GPIO(PE0), /* Port F */ - PINMUX_GPIO(GPIO_PF12, PF12_DATA), - PINMUX_GPIO(GPIO_PF11, PF11_DATA), - PINMUX_GPIO(GPIO_PF10, PF10_DATA), - PINMUX_GPIO(GPIO_PF9, PF9_DATA), - PINMUX_GPIO(GPIO_PF8, PF8_DATA), - PINMUX_GPIO(GPIO_PF7, PF7_DATA), - PINMUX_GPIO(GPIO_PF6, PF6_DATA), - PINMUX_GPIO(GPIO_PF5, PF5_DATA), - PINMUX_GPIO(GPIO_PF4, PF4_DATA), - PINMUX_GPIO(GPIO_PF3, PF3_DATA), - PINMUX_GPIO(GPIO_PF2, PF2_DATA), - PINMUX_GPIO(GPIO_PF1, PF1_DATA), - PINMUX_GPIO(GPIO_PF0, PF0_DATA), + PINMUX_GPIO(PF12), + PINMUX_GPIO(PF11), + PINMUX_GPIO(PF10), + PINMUX_GPIO(PF9), + PINMUX_GPIO(PF8), + PINMUX_GPIO(PF7), + PINMUX_GPIO(PF6), + PINMUX_GPIO(PF5), + PINMUX_GPIO(PF4), + PINMUX_GPIO(PF3), + PINMUX_GPIO(PF2), + PINMUX_GPIO(PF1), + PINMUX_GPIO(PF0), /* Port G */ - PINMUX_GPIO(GPIO_PG24, PG24_DATA), - PINMUX_GPIO(GPIO_PG23, PG23_DATA), - PINMUX_GPIO(GPIO_PG22, PG22_DATA), - PINMUX_GPIO(GPIO_PG21, PG21_DATA), - PINMUX_GPIO(GPIO_PG20, PG20_DATA), - PINMUX_GPIO(GPIO_PG19, PG19_DATA), - PINMUX_GPIO(GPIO_PG18, PG18_DATA), - PINMUX_GPIO(GPIO_PG17, PG17_DATA), - PINMUX_GPIO(GPIO_PG16, PG16_DATA), - PINMUX_GPIO(GPIO_PG15, PG15_DATA), - PINMUX_GPIO(GPIO_PG14, PG14_DATA), - PINMUX_GPIO(GPIO_PG13, PG13_DATA), - PINMUX_GPIO(GPIO_PG12, PG12_DATA), - PINMUX_GPIO(GPIO_PG11, PG11_DATA), - PINMUX_GPIO(GPIO_PG10, PG10_DATA), - PINMUX_GPIO(GPIO_PG9, PG9_DATA), - PINMUX_GPIO(GPIO_PG8, PG8_DATA), - PINMUX_GPIO(GPIO_PG7, PG7_DATA), - PINMUX_GPIO(GPIO_PG6, PG6_DATA), - PINMUX_GPIO(GPIO_PG5, PG5_DATA), - PINMUX_GPIO(GPIO_PG4, PG4_DATA), - PINMUX_GPIO(GPIO_PG3, PG3_DATA), - PINMUX_GPIO(GPIO_PG2, PG2_DATA), - PINMUX_GPIO(GPIO_PG1, PG1_DATA), - PINMUX_GPIO(GPIO_PG0, PG0_DATA), + PINMUX_GPIO(PG24), + PINMUX_GPIO(PG23), + PINMUX_GPIO(PG22), + PINMUX_GPIO(PG21), + PINMUX_GPIO(PG20), + PINMUX_GPIO(PG19), + PINMUX_GPIO(PG18), + PINMUX_GPIO(PG17), + PINMUX_GPIO(PG16), + PINMUX_GPIO(PG15), + PINMUX_GPIO(PG14), + PINMUX_GPIO(PG13), + PINMUX_GPIO(PG12), + PINMUX_GPIO(PG11), + PINMUX_GPIO(PG10), + PINMUX_GPIO(PG9), + PINMUX_GPIO(PG8), + PINMUX_GPIO(PG7), + PINMUX_GPIO(PG6), + PINMUX_GPIO(PG5), + PINMUX_GPIO(PG4), + PINMUX_GPIO(PG3), + PINMUX_GPIO(PG2), + PINMUX_GPIO(PG1), + PINMUX_GPIO(PG0), /* Port H - Port H does not have a Data Register */ /* Port I - not on device */ /* Port J */ - PINMUX_GPIO(GPIO_PJ11, PJ11_DATA), - PINMUX_GPIO(GPIO_PJ10, PJ10_DATA), - PINMUX_GPIO(GPIO_PJ9, PJ9_DATA), - PINMUX_GPIO(GPIO_PJ8, PJ8_DATA), - PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), - PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), - PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), - PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), - PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), - PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), - PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), - PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), + PINMUX_GPIO(PJ11), + PINMUX_GPIO(PJ10), + PINMUX_GPIO(PJ9), + PINMUX_GPIO(PJ8), + PINMUX_GPIO(PJ7), + PINMUX_GPIO(PJ6), + PINMUX_GPIO(PJ5), + PINMUX_GPIO(PJ4), + PINMUX_GPIO(PJ3), + PINMUX_GPIO(PJ2), + PINMUX_GPIO(PJ1), + PINMUX_GPIO(PJ0), /* Port K */ - PINMUX_GPIO(GPIO_PK11, PK11_DATA), - PINMUX_GPIO(GPIO_PK10, PK10_DATA), - PINMUX_GPIO(GPIO_PK9, PK9_DATA), - PINMUX_GPIO(GPIO_PK8, PK8_DATA), - PINMUX_GPIO(GPIO_PK7, PK7_DATA), - PINMUX_GPIO(GPIO_PK6, PK6_DATA), - PINMUX_GPIO(GPIO_PK5, PK5_DATA), - PINMUX_GPIO(GPIO_PK4, PK4_DATA), - PINMUX_GPIO(GPIO_PK3, PK3_DATA), - PINMUX_GPIO(GPIO_PK2, PK2_DATA), - PINMUX_GPIO(GPIO_PK1, PK1_DATA), - PINMUX_GPIO(GPIO_PK0, PK0_DATA), + PINMUX_GPIO(PK11), + PINMUX_GPIO(PK10), + PINMUX_GPIO(PK9), + PINMUX_GPIO(PK8), + PINMUX_GPIO(PK7), + PINMUX_GPIO(PK6), + PINMUX_GPIO(PK5), + PINMUX_GPIO(PK4), + PINMUX_GPIO(PK3), + PINMUX_GPIO(PK2), + PINMUX_GPIO(PK1), + PINMUX_GPIO(PK0), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* INTC */ - PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), - - PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), + GPIO_FN(PINT7_PG), + GPIO_FN(PINT6_PG), + GPIO_FN(PINT5_PG), + GPIO_FN(PINT4_PG), + GPIO_FN(PINT3_PG), + GPIO_FN(PINT2_PG), + GPIO_FN(PINT1_PG), + + GPIO_FN(IRQ7_PC), + GPIO_FN(IRQ6_PC), + GPIO_FN(IRQ5_PC), + GPIO_FN(IRQ4_PC), + GPIO_FN(IRQ3_PG), + GPIO_FN(IRQ2_PG), + GPIO_FN(IRQ1_PJ), + GPIO_FN(IRQ0_PJ), + GPIO_FN(IRQ3_PE), + GPIO_FN(IRQ2_PE), + GPIO_FN(IRQ1_PE), + GPIO_FN(IRQ0_PE), /* WDT */ - PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), + GPIO_FN(WDTOVF), /* CAN */ - PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), - PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), + GPIO_FN(CTX1), + GPIO_FN(CRX1), + GPIO_FN(CTX0), + GPIO_FN(CRX0), + GPIO_FN(CRX0_CRX1), /* DMAC */ - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + GPIO_FN(TEND0), + GPIO_FN(DACK0), + GPIO_FN(DREQ0), + GPIO_FN(TEND1), + GPIO_FN(DACK1), + GPIO_FN(DREQ1), /* ADC */ - PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + GPIO_FN(ADTRG), /* BSCh */ - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_A20, A20_MARK), - PINMUX_GPIO(GPIO_FN_A19, A19_MARK), - PINMUX_GPIO(GPIO_FN_A18, A18_MARK), - PINMUX_GPIO(GPIO_FN_A17, A17_MARK), - PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_A15, A15_MARK), - PINMUX_GPIO(GPIO_FN_A14, A14_MARK), - PINMUX_GPIO(GPIO_FN_A13, A13_MARK), - PINMUX_GPIO(GPIO_FN_A12, A12_MARK), - PINMUX_GPIO(GPIO_FN_A11, A11_MARK), - PINMUX_GPIO(GPIO_FN_A10, A10_MARK), - PINMUX_GPIO(GPIO_FN_A9, A9_MARK), - PINMUX_GPIO(GPIO_FN_A8, A8_MARK), - PINMUX_GPIO(GPIO_FN_A7, A7_MARK), - PINMUX_GPIO(GPIO_FN_A6, A6_MARK), - PINMUX_GPIO(GPIO_FN_A5, A5_MARK), - PINMUX_GPIO(GPIO_FN_A4, A4_MARK), - PINMUX_GPIO(GPIO_FN_A3, A3_MARK), - PINMUX_GPIO(GPIO_FN_A2, A2_MARK), - PINMUX_GPIO(GPIO_FN_A1, A1_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), - - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), - PINMUX_GPIO(GPIO_FN_D7, D7_MARK), - PINMUX_GPIO(GPIO_FN_D6, D6_MARK), - PINMUX_GPIO(GPIO_FN_D5, D5_MARK), - PINMUX_GPIO(GPIO_FN_D4, D4_MARK), - PINMUX_GPIO(GPIO_FN_D3, D3_MARK), - PINMUX_GPIO(GPIO_FN_D2, D2_MARK), - PINMUX_GPIO(GPIO_FN_D1, D1_MARK), - PINMUX_GPIO(GPIO_FN_D0, D0_MARK), - - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), - PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), - PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), - PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), - PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_RD, RD_MARK), - PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), - PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK), - PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK), - PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), - PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), - PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), - PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), - PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(A20), + GPIO_FN(A19), + GPIO_FN(A18), + GPIO_FN(A17), + GPIO_FN(A16), + GPIO_FN(A15), + GPIO_FN(A14), + GPIO_FN(A13), + GPIO_FN(A12), + GPIO_FN(A11), + GPIO_FN(A10), + GPIO_FN(A9), + GPIO_FN(A8), + GPIO_FN(A7), + GPIO_FN(A6), + GPIO_FN(A5), + GPIO_FN(A4), + GPIO_FN(A3), + GPIO_FN(A2), + GPIO_FN(A1), + GPIO_FN(A0), + + GPIO_FN(D15), + GPIO_FN(D14), + GPIO_FN(D13), + GPIO_FN(D12), + GPIO_FN(D11), + GPIO_FN(D10), + GPIO_FN(D9), + GPIO_FN(D8), + GPIO_FN(D7), + GPIO_FN(D6), + GPIO_FN(D5), + GPIO_FN(D4), + GPIO_FN(D3), + GPIO_FN(D2), + GPIO_FN(D1), + GPIO_FN(D0), + + GPIO_FN(BS), + GPIO_FN(CS4), + GPIO_FN(CS3), + GPIO_FN(CS2), + GPIO_FN(CS1), + GPIO_FN(CS0), + GPIO_FN(CS6CE1B), + GPIO_FN(CS5CE1A), + GPIO_FN(CE2A), + GPIO_FN(CE2B), + GPIO_FN(RD), + GPIO_FN(RDWR), + GPIO_FN(ICIOWRAH), + GPIO_FN(ICIORD), + GPIO_FN(WE1DQMUWE), + GPIO_FN(WE0DQML), + GPIO_FN(RAS), + GPIO_FN(CAS), + GPIO_FN(CKE), + GPIO_FN(WAIT), + GPIO_FN(BREQ), + GPIO_FN(BACK), + GPIO_FN(IOIS16), /* TMU */ - PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), - PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), - PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), - PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), + GPIO_FN(TIOC4D), + GPIO_FN(TIOC4C), + GPIO_FN(TIOC4B), + GPIO_FN(TIOC4A), + GPIO_FN(TIOC3D), + GPIO_FN(TIOC3C), + GPIO_FN(TIOC3B), + GPIO_FN(TIOC3A), + GPIO_FN(TIOC2B), + GPIO_FN(TIOC1B), + GPIO_FN(TIOC2A), + GPIO_FN(TIOC1A), + GPIO_FN(TIOC0D), + GPIO_FN(TIOC0C), + GPIO_FN(TIOC0B), + GPIO_FN(TIOC0A), + GPIO_FN(TCLKD), + GPIO_FN(TCLKC), + GPIO_FN(TCLKB), + GPIO_FN(TCLKA), /* SCIF */ - PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), - PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), - PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), - PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), - PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), - PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), - PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), - PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), - PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), - PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), - PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), - PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), - PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), - PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), - PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), + GPIO_FN(TXD0), + GPIO_FN(RXD0), + GPIO_FN(SCK0), + GPIO_FN(TXD1), + GPIO_FN(RXD1), + GPIO_FN(SCK1), + GPIO_FN(TXD2), + GPIO_FN(RXD2), + GPIO_FN(SCK2), + GPIO_FN(RTS3), + GPIO_FN(CTS3), + GPIO_FN(TXD3), + GPIO_FN(RXD3), + GPIO_FN(SCK3), + GPIO_FN(TXD4), + GPIO_FN(RXD4), + GPIO_FN(TXD5), + GPIO_FN(RXD5), + GPIO_FN(TXD6), + GPIO_FN(RXD6), + GPIO_FN(TXD7), + GPIO_FN(RXD7), + GPIO_FN(RTS1), + GPIO_FN(CTS1), /* RSPI */ - PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK), - PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK), - PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK), - PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), - PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK), - PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), - PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), - PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK), - PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), + GPIO_FN(RSPCK0), + GPIO_FN(MOSI0), + GPIO_FN(MISO0_PF12), + GPIO_FN(MISO1), + GPIO_FN(SSL00), + GPIO_FN(RSPCK1), + GPIO_FN(MOSI1), + GPIO_FN(MISO1_PG19), + GPIO_FN(SSL10), /* IIC3 */ - PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), - PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), - PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), - PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), - PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), - PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + GPIO_FN(SCL0), + GPIO_FN(SCL1), + GPIO_FN(SCL2), + GPIO_FN(SDA0), + GPIO_FN(SDA1), + GPIO_FN(SDA2), /* SSI */ - PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), - PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), - PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), + GPIO_FN(SSISCK0), + GPIO_FN(SSIWS0), + GPIO_FN(SSITXD0), + GPIO_FN(SSIRXD0), + GPIO_FN(SSIWS1), + GPIO_FN(SSIWS2), + GPIO_FN(SSIWS3), + GPIO_FN(SSISCK1), + GPIO_FN(SSISCK2), + GPIO_FN(SSISCK3), + GPIO_FN(SSIDATA1), + GPIO_FN(SSIDATA2), + GPIO_FN(SSIDATA3), + GPIO_FN(AUDIO_CLK), /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ - PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), + GPIO_FN(SIOFTXD), + GPIO_FN(SIOFRXD), + GPIO_FN(SIOFSYNC), + GPIO_FN(SIOFSCK), /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ - PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), - PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), + GPIO_FN(SPDIF_IN), + GPIO_FN(SPDIF_OUT), /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + GPIO_FN(FCE), + GPIO_FN(FRB), /* VDC3 */ - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), - - PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), - - PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), - - PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), - - PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), + GPIO_FN(DV_CLK), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_HSYNC), + + GPIO_FN(DV_DATA7), + GPIO_FN(DV_DATA6), + GPIO_FN(DV_DATA5), + GPIO_FN(DV_DATA4), + GPIO_FN(DV_DATA3), + GPIO_FN(DV_DATA2), + GPIO_FN(DV_DATA1), + GPIO_FN(DV_DATA0), + + GPIO_FN(LCD_CLK), + GPIO_FN(LCD_EXTCLK), + GPIO_FN(LCD_VSYNC), + GPIO_FN(LCD_HSYNC), + GPIO_FN(LCD_DE), + + GPIO_FN(LCD_DATA15), + GPIO_FN(LCD_DATA14), + GPIO_FN(LCD_DATA13), + GPIO_FN(LCD_DATA12), + GPIO_FN(LCD_DATA11), + GPIO_FN(LCD_DATA10), + GPIO_FN(LCD_DATA9), + GPIO_FN(LCD_DATA8), + GPIO_FN(LCD_DATA7), + GPIO_FN(LCD_DATA6), + GPIO_FN(LCD_DATA5), + GPIO_FN(LCD_DATA4), + GPIO_FN(LCD_DATA3), + GPIO_FN(LCD_DATA2), + GPIO_FN(LCD_DATA1), + GPIO_FN(LCD_DATA0), + + GPIO_FN(LCD_M_DISP), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2032,7 +2034,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) { 0, 0, 0, 0, 0, 0, 0, PA3_DATA, 0, 0, 0, 0, 0, 0, 0, PA2_DATA } @@ -2110,19 +2112,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { } }; -struct sh_pfc_soc_info sh7264_pinmux_info = { +const struct sh_pfc_soc_info sh7264_pinmux_info = { .name = "sh7264_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA3, - .last_gpio = GPIO_FN_LCD_M_DISP, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index b1b5d6d4ad7..7a11320ad96 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -781,8 +781,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { - +static const u16 pinmux_data[] = { /* Port A */ PINMUX_DATA(PA1_DATA, PA1_IN), PINMUX_DATA(PA0_DATA, PA0_IN), @@ -1452,500 +1451,504 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PWM1A_MARK, PJ0MD_100), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* Port A */ - PINMUX_GPIO(GPIO_PA1, PA1_DATA), - PINMUX_GPIO(GPIO_PA0, PA0_DATA), + PINMUX_GPIO(PA1), + PINMUX_GPIO(PA0), /* Port B */ - PINMUX_GPIO(GPIO_PB22, PB22_DATA), - PINMUX_GPIO(GPIO_PB21, PB21_DATA), - PINMUX_GPIO(GPIO_PB20, PB20_DATA), - PINMUX_GPIO(GPIO_PB19, PB19_DATA), - PINMUX_GPIO(GPIO_PB18, PB18_DATA), - PINMUX_GPIO(GPIO_PB17, PB17_DATA), - PINMUX_GPIO(GPIO_PB16, PB16_DATA), - PINMUX_GPIO(GPIO_PB15, PB15_DATA), - PINMUX_GPIO(GPIO_PB14, PB14_DATA), - PINMUX_GPIO(GPIO_PB13, PB13_DATA), - PINMUX_GPIO(GPIO_PB12, PB12_DATA), - PINMUX_GPIO(GPIO_PB11, PB11_DATA), - PINMUX_GPIO(GPIO_PB10, PB10_DATA), - PINMUX_GPIO(GPIO_PB9, PB9_DATA), - PINMUX_GPIO(GPIO_PB8, PB8_DATA), - PINMUX_GPIO(GPIO_PB7, PB7_DATA), - PINMUX_GPIO(GPIO_PB6, PB6_DATA), - PINMUX_GPIO(GPIO_PB5, PB5_DATA), - PINMUX_GPIO(GPIO_PB4, PB4_DATA), - PINMUX_GPIO(GPIO_PB3, PB3_DATA), - PINMUX_GPIO(GPIO_PB2, PB2_DATA), - PINMUX_GPIO(GPIO_PB1, PB1_DATA), + PINMUX_GPIO(PB22), + PINMUX_GPIO(PB21), + PINMUX_GPIO(PB20), + PINMUX_GPIO(PB19), + PINMUX_GPIO(PB18), + PINMUX_GPIO(PB17), + PINMUX_GPIO(PB16), + PINMUX_GPIO(PB15), + PINMUX_GPIO(PB14), + PINMUX_GPIO(PB13), + PINMUX_GPIO(PB12), + PINMUX_GPIO(PB11), + PINMUX_GPIO(PB10), + PINMUX_GPIO(PB9), + PINMUX_GPIO(PB8), + PINMUX_GPIO(PB7), + PINMUX_GPIO(PB6), + PINMUX_GPIO(PB5), + PINMUX_GPIO(PB4), + PINMUX_GPIO(PB3), + PINMUX_GPIO(PB2), + PINMUX_GPIO(PB1), /* Port C */ - PINMUX_GPIO(GPIO_PC8, PC8_DATA), - PINMUX_GPIO(GPIO_PC7, PC7_DATA), - PINMUX_GPIO(GPIO_PC6, PC6_DATA), - PINMUX_GPIO(GPIO_PC5, PC5_DATA), - PINMUX_GPIO(GPIO_PC4, PC4_DATA), - PINMUX_GPIO(GPIO_PC3, PC3_DATA), - PINMUX_GPIO(GPIO_PC2, PC2_DATA), - PINMUX_GPIO(GPIO_PC1, PC1_DATA), - PINMUX_GPIO(GPIO_PC0, PC0_DATA), + PINMUX_GPIO(PC8), + PINMUX_GPIO(PC7), + PINMUX_GPIO(PC6), + PINMUX_GPIO(PC5), + PINMUX_GPIO(PC4), + PINMUX_GPIO(PC3), + PINMUX_GPIO(PC2), + PINMUX_GPIO(PC1), + PINMUX_GPIO(PC0), /* Port D */ - PINMUX_GPIO(GPIO_PD15, PD15_DATA), - PINMUX_GPIO(GPIO_PD14, PD14_DATA), - PINMUX_GPIO(GPIO_PD13, PD13_DATA), - PINMUX_GPIO(GPIO_PD12, PD12_DATA), - PINMUX_GPIO(GPIO_PD11, PD11_DATA), - PINMUX_GPIO(GPIO_PD10, PD10_DATA), - PINMUX_GPIO(GPIO_PD9, PD9_DATA), - PINMUX_GPIO(GPIO_PD8, PD8_DATA), - PINMUX_GPIO(GPIO_PD7, PD7_DATA), - PINMUX_GPIO(GPIO_PD6, PD6_DATA), - PINMUX_GPIO(GPIO_PD5, PD5_DATA), - PINMUX_GPIO(GPIO_PD4, PD4_DATA), - PINMUX_GPIO(GPIO_PD3, PD3_DATA), - PINMUX_GPIO(GPIO_PD2, PD2_DATA), - PINMUX_GPIO(GPIO_PD1, PD1_DATA), - PINMUX_GPIO(GPIO_PD0, PD0_DATA), + PINMUX_GPIO(PD15), + PINMUX_GPIO(PD14), + PINMUX_GPIO(PD13), + PINMUX_GPIO(PD12), + PINMUX_GPIO(PD11), + PINMUX_GPIO(PD10), + PINMUX_GPIO(PD9), + PINMUX_GPIO(PD8), + PINMUX_GPIO(PD7), + PINMUX_GPIO(PD6), + PINMUX_GPIO(PD5), + PINMUX_GPIO(PD4), + PINMUX_GPIO(PD3), + PINMUX_GPIO(PD2), + PINMUX_GPIO(PD1), + PINMUX_GPIO(PD0), /* Port E */ - PINMUX_GPIO(GPIO_PE7, PE7_DATA), - PINMUX_GPIO(GPIO_PE6, PE6_DATA), - PINMUX_GPIO(GPIO_PE5, PE5_DATA), - PINMUX_GPIO(GPIO_PE4, PE4_DATA), - PINMUX_GPIO(GPIO_PE3, PE3_DATA), - PINMUX_GPIO(GPIO_PE2, PE2_DATA), - PINMUX_GPIO(GPIO_PE1, PE1_DATA), - PINMUX_GPIO(GPIO_PE0, PE0_DATA), + PINMUX_GPIO(PE7), + PINMUX_GPIO(PE6), + PINMUX_GPIO(PE5), + PINMUX_GPIO(PE4), + PINMUX_GPIO(PE3), + PINMUX_GPIO(PE2), + PINMUX_GPIO(PE1), + PINMUX_GPIO(PE0), /* Port F */ - PINMUX_GPIO(GPIO_PF23, PF23_DATA), - PINMUX_GPIO(GPIO_PF22, PF22_DATA), - PINMUX_GPIO(GPIO_PF21, PF21_DATA), - PINMUX_GPIO(GPIO_PF20, PF20_DATA), - PINMUX_GPIO(GPIO_PF19, PF19_DATA), - PINMUX_GPIO(GPIO_PF18, PF18_DATA), - PINMUX_GPIO(GPIO_PF17, PF17_DATA), - PINMUX_GPIO(GPIO_PF16, PF16_DATA), - PINMUX_GPIO(GPIO_PF15, PF15_DATA), - PINMUX_GPIO(GPIO_PF14, PF14_DATA), - PINMUX_GPIO(GPIO_PF13, PF13_DATA), - PINMUX_GPIO(GPIO_PF12, PF12_DATA), - PINMUX_GPIO(GPIO_PF11, PF11_DATA), - PINMUX_GPIO(GPIO_PF10, PF10_DATA), - PINMUX_GPIO(GPIO_PF9, PF9_DATA), - PINMUX_GPIO(GPIO_PF8, PF8_DATA), - PINMUX_GPIO(GPIO_PF7, PF7_DATA), - PINMUX_GPIO(GPIO_PF6, PF6_DATA), - PINMUX_GPIO(GPIO_PF5, PF5_DATA), - PINMUX_GPIO(GPIO_PF4, PF4_DATA), - PINMUX_GPIO(GPIO_PF3, PF3_DATA), - PINMUX_GPIO(GPIO_PF2, PF2_DATA), - PINMUX_GPIO(GPIO_PF1, PF1_DATA), - PINMUX_GPIO(GPIO_PF0, PF0_DATA), + PINMUX_GPIO(PF23), + PINMUX_GPIO(PF22), + PINMUX_GPIO(PF21), + PINMUX_GPIO(PF20), + PINMUX_GPIO(PF19), + PINMUX_GPIO(PF18), + PINMUX_GPIO(PF17), + PINMUX_GPIO(PF16), + PINMUX_GPIO(PF15), + PINMUX_GPIO(PF14), + PINMUX_GPIO(PF13), + PINMUX_GPIO(PF12), + PINMUX_GPIO(PF11), + PINMUX_GPIO(PF10), + PINMUX_GPIO(PF9), + PINMUX_GPIO(PF8), + PINMUX_GPIO(PF7), + PINMUX_GPIO(PF6), + PINMUX_GPIO(PF5), + PINMUX_GPIO(PF4), + PINMUX_GPIO(PF3), + PINMUX_GPIO(PF2), + PINMUX_GPIO(PF1), + PINMUX_GPIO(PF0), /* Port G */ - PINMUX_GPIO(GPIO_PG27, PG27_DATA), - PINMUX_GPIO(GPIO_PG26, PG26_DATA), - PINMUX_GPIO(GPIO_PG25, PG25_DATA), - PINMUX_GPIO(GPIO_PG24, PG24_DATA), - PINMUX_GPIO(GPIO_PG23, PG23_DATA), - PINMUX_GPIO(GPIO_PG22, PG22_DATA), - PINMUX_GPIO(GPIO_PG21, PG21_DATA), - PINMUX_GPIO(GPIO_PG20, PG20_DATA), - PINMUX_GPIO(GPIO_PG19, PG19_DATA), - PINMUX_GPIO(GPIO_PG18, PG18_DATA), - PINMUX_GPIO(GPIO_PG17, PG17_DATA), - PINMUX_GPIO(GPIO_PG16, PG16_DATA), - PINMUX_GPIO(GPIO_PG15, PG15_DATA), - PINMUX_GPIO(GPIO_PG14, PG14_DATA), - PINMUX_GPIO(GPIO_PG13, PG13_DATA), - PINMUX_GPIO(GPIO_PG12, PG12_DATA), - PINMUX_GPIO(GPIO_PG11, PG11_DATA), - PINMUX_GPIO(GPIO_PG10, PG10_DATA), - PINMUX_GPIO(GPIO_PG9, PG9_DATA), - PINMUX_GPIO(GPIO_PG8, PG8_DATA), - PINMUX_GPIO(GPIO_PG7, PG7_DATA), - PINMUX_GPIO(GPIO_PG6, PG6_DATA), - PINMUX_GPIO(GPIO_PG5, PG5_DATA), - PINMUX_GPIO(GPIO_PG4, PG4_DATA), - PINMUX_GPIO(GPIO_PG3, PG3_DATA), - PINMUX_GPIO(GPIO_PG2, PG2_DATA), - PINMUX_GPIO(GPIO_PG1, PG1_DATA), - PINMUX_GPIO(GPIO_PG0, PG0_DATA), + PINMUX_GPIO(PG27), + PINMUX_GPIO(PG26), + PINMUX_GPIO(PG25), + PINMUX_GPIO(PG24), + PINMUX_GPIO(PG23), + PINMUX_GPIO(PG22), + PINMUX_GPIO(PG21), + PINMUX_GPIO(PG20), + PINMUX_GPIO(PG19), + PINMUX_GPIO(PG18), + PINMUX_GPIO(PG17), + PINMUX_GPIO(PG16), + PINMUX_GPIO(PG15), + PINMUX_GPIO(PG14), + PINMUX_GPIO(PG13), + PINMUX_GPIO(PG12), + PINMUX_GPIO(PG11), + PINMUX_GPIO(PG10), + PINMUX_GPIO(PG9), + PINMUX_GPIO(PG8), + PINMUX_GPIO(PG7), + PINMUX_GPIO(PG6), + PINMUX_GPIO(PG5), + PINMUX_GPIO(PG4), + PINMUX_GPIO(PG3), + PINMUX_GPIO(PG2), + PINMUX_GPIO(PG1), + PINMUX_GPIO(PG0), /* Port H - Port H does not have a Data Register */ /* Port I - not on device */ /* Port J */ - PINMUX_GPIO(GPIO_PJ31, PJ31_DATA), - PINMUX_GPIO(GPIO_PJ30, PJ30_DATA), - PINMUX_GPIO(GPIO_PJ29, PJ29_DATA), - PINMUX_GPIO(GPIO_PJ28, PJ28_DATA), - PINMUX_GPIO(GPIO_PJ27, PJ27_DATA), - PINMUX_GPIO(GPIO_PJ26, PJ26_DATA), - PINMUX_GPIO(GPIO_PJ25, PJ25_DATA), - PINMUX_GPIO(GPIO_PJ24, PJ24_DATA), - PINMUX_GPIO(GPIO_PJ23, PJ23_DATA), - PINMUX_GPIO(GPIO_PJ22, PJ22_DATA), - PINMUX_GPIO(GPIO_PJ21, PJ21_DATA), - PINMUX_GPIO(GPIO_PJ20, PJ20_DATA), - PINMUX_GPIO(GPIO_PJ19, PJ19_DATA), - PINMUX_GPIO(GPIO_PJ18, PJ18_DATA), - PINMUX_GPIO(GPIO_PJ17, PJ17_DATA), - PINMUX_GPIO(GPIO_PJ16, PJ16_DATA), - PINMUX_GPIO(GPIO_PJ15, PJ15_DATA), - PINMUX_GPIO(GPIO_PJ14, PJ14_DATA), - PINMUX_GPIO(GPIO_PJ13, PJ13_DATA), - PINMUX_GPIO(GPIO_PJ12, PJ12_DATA), - PINMUX_GPIO(GPIO_PJ11, PJ11_DATA), - PINMUX_GPIO(GPIO_PJ10, PJ10_DATA), - PINMUX_GPIO(GPIO_PJ9, PJ9_DATA), - PINMUX_GPIO(GPIO_PJ8, PJ8_DATA), - PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), - PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), - PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), - PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), - PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), - PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), - PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), - PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), + PINMUX_GPIO(PJ31), + PINMUX_GPIO(PJ30), + PINMUX_GPIO(PJ29), + PINMUX_GPIO(PJ28), + PINMUX_GPIO(PJ27), + PINMUX_GPIO(PJ26), + PINMUX_GPIO(PJ25), + PINMUX_GPIO(PJ24), + PINMUX_GPIO(PJ23), + PINMUX_GPIO(PJ22), + PINMUX_GPIO(PJ21), + PINMUX_GPIO(PJ20), + PINMUX_GPIO(PJ19), + PINMUX_GPIO(PJ18), + PINMUX_GPIO(PJ17), + PINMUX_GPIO(PJ16), + PINMUX_GPIO(PJ15), + PINMUX_GPIO(PJ14), + PINMUX_GPIO(PJ13), + PINMUX_GPIO(PJ12), + PINMUX_GPIO(PJ11), + PINMUX_GPIO(PJ10), + PINMUX_GPIO(PJ9), + PINMUX_GPIO(PJ8), + PINMUX_GPIO(PJ7), + PINMUX_GPIO(PJ6), + PINMUX_GPIO(PJ5), + PINMUX_GPIO(PJ4), + PINMUX_GPIO(PJ3), + PINMUX_GPIO(PJ2), + PINMUX_GPIO(PJ1), + PINMUX_GPIO(PJ0), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* INTC */ - PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK), - - PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK), - PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK), - PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK), - PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK), + GPIO_FN(IRQ7_PG), + GPIO_FN(IRQ6_PG), + GPIO_FN(IRQ5_PG), + GPIO_FN(IRQ4_PG), + GPIO_FN(IRQ3_PG), + GPIO_FN(IRQ2_PG), + GPIO_FN(IRQ1_PG), + GPIO_FN(IRQ0_PG), + GPIO_FN(IRQ7_PF), + GPIO_FN(IRQ6_PF), + GPIO_FN(IRQ5_PF), + GPIO_FN(IRQ4_PF), + GPIO_FN(IRQ3_PJ), + GPIO_FN(IRQ2_PJ), + GPIO_FN(IRQ1_PJ), + GPIO_FN(IRQ0_PJ), + GPIO_FN(IRQ1_PC), + GPIO_FN(IRQ0_PC), + + GPIO_FN(PINT7_PG), + GPIO_FN(PINT6_PG), + GPIO_FN(PINT5_PG), + GPIO_FN(PINT4_PG), + GPIO_FN(PINT3_PG), + GPIO_FN(PINT2_PG), + GPIO_FN(PINT1_PG), + GPIO_FN(PINT0_PG), + GPIO_FN(PINT7_PH), + GPIO_FN(PINT6_PH), + GPIO_FN(PINT5_PH), + GPIO_FN(PINT4_PH), + GPIO_FN(PINT3_PH), + GPIO_FN(PINT2_PH), + GPIO_FN(PINT1_PH), + GPIO_FN(PINT0_PH), + GPIO_FN(PINT7_PJ), + GPIO_FN(PINT6_PJ), + GPIO_FN(PINT5_PJ), + GPIO_FN(PINT4_PJ), + GPIO_FN(PINT3_PJ), + GPIO_FN(PINT2_PJ), + GPIO_FN(PINT1_PJ), + GPIO_FN(PINT0_PJ), /* WDT */ - PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), + GPIO_FN(WDTOVF), /* CAN */ - PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), - PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), - PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), - PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0_CRX1_CRX2_MARK), + GPIO_FN(CTX1), + GPIO_FN(CRX1), + GPIO_FN(CTX0), + GPIO_FN(CRX0), + GPIO_FN(CRX0_CRX1), + GPIO_FN(CRX0_CRX1_CRX2), /* DMAC */ - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + GPIO_FN(TEND0), + GPIO_FN(DACK0), + GPIO_FN(DREQ0), + GPIO_FN(TEND1), + GPIO_FN(DACK1), + GPIO_FN(DREQ1), /* ADC */ - PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + GPIO_FN(ADTRG), /* BSCh */ - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_A20, A20_MARK), - PINMUX_GPIO(GPIO_FN_A19, A19_MARK), - PINMUX_GPIO(GPIO_FN_A18, A18_MARK), - PINMUX_GPIO(GPIO_FN_A17, A17_MARK), - PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_A15, A15_MARK), - PINMUX_GPIO(GPIO_FN_A14, A14_MARK), - PINMUX_GPIO(GPIO_FN_A13, A13_MARK), - PINMUX_GPIO(GPIO_FN_A12, A12_MARK), - PINMUX_GPIO(GPIO_FN_A11, A11_MARK), - PINMUX_GPIO(GPIO_FN_A10, A10_MARK), - PINMUX_GPIO(GPIO_FN_A9, A9_MARK), - PINMUX_GPIO(GPIO_FN_A8, A8_MARK), - PINMUX_GPIO(GPIO_FN_A7, A7_MARK), - PINMUX_GPIO(GPIO_FN_A6, A6_MARK), - PINMUX_GPIO(GPIO_FN_A5, A5_MARK), - PINMUX_GPIO(GPIO_FN_A4, A4_MARK), - PINMUX_GPIO(GPIO_FN_A3, A3_MARK), - PINMUX_GPIO(GPIO_FN_A2, A2_MARK), - PINMUX_GPIO(GPIO_FN_A1, A1_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), - - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), - PINMUX_GPIO(GPIO_FN_D7, D7_MARK), - PINMUX_GPIO(GPIO_FN_D6, D6_MARK), - PINMUX_GPIO(GPIO_FN_D5, D5_MARK), - PINMUX_GPIO(GPIO_FN_D4, D4_MARK), - PINMUX_GPIO(GPIO_FN_D3, D3_MARK), - PINMUX_GPIO(GPIO_FN_D2, D2_MARK), - PINMUX_GPIO(GPIO_FN_D1, D1_MARK), - PINMUX_GPIO(GPIO_FN_D0, D0_MARK), - - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), - PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), - PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), - PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), - PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_RD, RD_MARK), - PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), - PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK), - PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK), - PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), - PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), - PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), - PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), - PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(A20), + GPIO_FN(A19), + GPIO_FN(A18), + GPIO_FN(A17), + GPIO_FN(A16), + GPIO_FN(A15), + GPIO_FN(A14), + GPIO_FN(A13), + GPIO_FN(A12), + GPIO_FN(A11), + GPIO_FN(A10), + GPIO_FN(A9), + GPIO_FN(A8), + GPIO_FN(A7), + GPIO_FN(A6), + GPIO_FN(A5), + GPIO_FN(A4), + GPIO_FN(A3), + GPIO_FN(A2), + GPIO_FN(A1), + GPIO_FN(A0), + + GPIO_FN(D15), + GPIO_FN(D14), + GPIO_FN(D13), + GPIO_FN(D12), + GPIO_FN(D11), + GPIO_FN(D10), + GPIO_FN(D9), + GPIO_FN(D8), + GPIO_FN(D7), + GPIO_FN(D6), + GPIO_FN(D5), + GPIO_FN(D4), + GPIO_FN(D3), + GPIO_FN(D2), + GPIO_FN(D1), + GPIO_FN(D0), + + GPIO_FN(BS), + GPIO_FN(CS4), + GPIO_FN(CS3), + GPIO_FN(CS2), + GPIO_FN(CS1), + GPIO_FN(CS0), + GPIO_FN(CS5CE1A), + GPIO_FN(CE2A), + GPIO_FN(CE2B), + GPIO_FN(RD), + GPIO_FN(RDWR), + GPIO_FN(WE3ICIOWRAHDQMUU), + GPIO_FN(WE2ICIORDDQMUL), + GPIO_FN(WE1DQMUWE), + GPIO_FN(WE0DQML), + GPIO_FN(RAS), + GPIO_FN(CAS), + GPIO_FN(CKE), + GPIO_FN(WAIT), + GPIO_FN(BREQ), + GPIO_FN(BACK), + GPIO_FN(IOIS16), /* TMU */ - PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), - PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), - PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), - PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), - PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), - PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), + GPIO_FN(TIOC4D), + GPIO_FN(TIOC4C), + GPIO_FN(TIOC4B), + GPIO_FN(TIOC4A), + GPIO_FN(TIOC3D), + GPIO_FN(TIOC3C), + GPIO_FN(TIOC3B), + GPIO_FN(TIOC3A), + GPIO_FN(TIOC2B), + GPIO_FN(TIOC1B), + GPIO_FN(TIOC2A), + GPIO_FN(TIOC1A), + GPIO_FN(TIOC0D), + GPIO_FN(TIOC0C), + GPIO_FN(TIOC0B), + GPIO_FN(TIOC0A), + GPIO_FN(TCLKD), + GPIO_FN(TCLKC), + GPIO_FN(TCLKB), + GPIO_FN(TCLKA), /* SCIF */ - PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), - PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), - PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), - PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), - PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), - PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), - PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), - PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK), - PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), - PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), - PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK), - PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK), - PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK), - PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), - PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), - PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK), - PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), - PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), - PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK), - PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK), + GPIO_FN(SCK0), + GPIO_FN(TXD0), + GPIO_FN(RXD0), + GPIO_FN(SCK1), + GPIO_FN(TXD1), + GPIO_FN(RXD1), + GPIO_FN(RTS1), + GPIO_FN(CTS1), + GPIO_FN(SCK2), + GPIO_FN(TXD2), + GPIO_FN(RXD2), + GPIO_FN(SCK3), + GPIO_FN(TXD3), + GPIO_FN(RXD3), + GPIO_FN(SCK4), + GPIO_FN(TXD4), + GPIO_FN(RXD4), + GPIO_FN(SCK5), + GPIO_FN(TXD5), + GPIO_FN(RXD5), + GPIO_FN(RTS5), + GPIO_FN(CTS5), + GPIO_FN(SCK6), + GPIO_FN(TXD6), + GPIO_FN(RXD6), + GPIO_FN(SCK7), + GPIO_FN(TXD7), + GPIO_FN(RXD7), + GPIO_FN(RTS7), + GPIO_FN(CTS7), /* RSPI */ - PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK), - PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK), - PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK), - PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK), - PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK), - PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK), - PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK), - PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK), - PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), - PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), - PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), - PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), + GPIO_FN(RSPCK0_PJ16), + GPIO_FN(SSL00_PJ17), + GPIO_FN(MOSI0_PJ18), + GPIO_FN(MISO0_PJ19), + GPIO_FN(RSPCK0_PB17), + GPIO_FN(SSL00_PB18), + GPIO_FN(MOSI0_PB19), + GPIO_FN(MISO0_PB20), + GPIO_FN(RSPCK1), + GPIO_FN(MOSI1), + GPIO_FN(MISO1), + GPIO_FN(SSL10), /* IIC3 */ - PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), - PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), - PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), - PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), - PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), - PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + GPIO_FN(SCL0), + GPIO_FN(SCL1), + GPIO_FN(SCL2), + GPIO_FN(SDA0), + GPIO_FN(SDA1), + GPIO_FN(SDA2), /* SSI */ - PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), - PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), - PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), - PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), - PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), - PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), - PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK), + GPIO_FN(SSISCK0), + GPIO_FN(SSIWS0), + GPIO_FN(SSITXD0), + GPIO_FN(SSIRXD0), + GPIO_FN(SSIWS1), + GPIO_FN(SSIWS2), + GPIO_FN(SSIWS3), + GPIO_FN(SSISCK1), + GPIO_FN(SSISCK2), + GPIO_FN(SSISCK3), + GPIO_FN(SSIDATA1), + GPIO_FN(SSIDATA2), + GPIO_FN(SSIDATA3), + GPIO_FN(AUDIO_CLK), + GPIO_FN(AUDIO_XOUT), /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ - PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), + GPIO_FN(SIOFTXD), + GPIO_FN(SIOFRXD), + GPIO_FN(SIOFSYNC), + GPIO_FN(SIOFSCK), /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ - PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), - PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), + GPIO_FN(SPDIF_IN), + GPIO_FN(SPDIF_OUT), /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + GPIO_FN(FCE), + GPIO_FN(FRB), /* VDC3 */ - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), - - PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), - - PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), - - PINMUX_GPIO(GPIO_FN_LCD_DATA23_PG23, LCD_DATA23_PG23_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA22_PG22, LCD_DATA22_PG22_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA21_PG21, LCD_DATA21_PG21_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA20_PG20, LCD_DATA20_PG20_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA19_PG19, LCD_DATA19_PG19_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA18_PG18, LCD_DATA18_PG18_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA17_PG17, LCD_DATA17_PG17_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA16_PG16, LCD_DATA16_PG16_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA15_PG15, LCD_DATA15_PG15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14_PG14, LCD_DATA14_PG14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13_PG13, LCD_DATA13_PG13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12_PG12, LCD_DATA12_PG12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11_PG11, LCD_DATA11_PG11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10_PG10, LCD_DATA10_PG10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9_PG9, LCD_DATA9_PG9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8_PG8, LCD_DATA8_PG8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7_PG7, LCD_DATA7_PG7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6_PG6, LCD_DATA6_PG6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5_PG5, LCD_DATA5_PG5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4_PG4, LCD_DATA4_PG4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3_PG3, LCD_DATA3_PG3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2_PG2, LCD_DATA2_PG2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1_PG1, LCD_DATA1_PG1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0_PG0, LCD_DATA0_PG0_MARK), - - PINMUX_GPIO(GPIO_FN_LCD_DATA23_PJ23, LCD_DATA23_PJ23_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA22_PJ22, LCD_DATA22_PJ22_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA21_PJ21, LCD_DATA21_PJ21_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA20_PJ20, LCD_DATA20_PJ20_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA19_PJ19, LCD_DATA19_PJ19_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA18_PJ18, LCD_DATA18_PJ18_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA17_PJ17, LCD_DATA17_PJ17_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA16_PJ16, LCD_DATA16_PJ16_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA15_PJ15, LCD_DATA15_PJ15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14_PJ14, LCD_DATA14_PJ14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13_PJ13, LCD_DATA13_PJ13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12_PJ12, LCD_DATA12_PJ12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11_PJ11, LCD_DATA11_PJ11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10_PJ10, LCD_DATA10_PJ10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9_PJ9, LCD_DATA9_PJ9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8_PJ8, LCD_DATA8_PJ8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7_PJ7, LCD_DATA7_PJ7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6_PJ6, LCD_DATA6_PJ6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5_PJ5, LCD_DATA5_PJ5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4_PJ4, LCD_DATA4_PJ4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3_PJ3, LCD_DATA3_PJ3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2_PJ2, LCD_DATA2_PJ2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1_PJ1, LCD_DATA1_PJ1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0_PJ0, LCD_DATA0_PJ0_MARK), - - PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), + GPIO_FN(DV_CLK), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_HSYNC), + + GPIO_FN(DV_DATA23), + GPIO_FN(DV_DATA22), + GPIO_FN(DV_DATA21), + GPIO_FN(DV_DATA20), + GPIO_FN(DV_DATA19), + GPIO_FN(DV_DATA18), + GPIO_FN(DV_DATA17), + GPIO_FN(DV_DATA16), + GPIO_FN(DV_DATA15), + GPIO_FN(DV_DATA14), + GPIO_FN(DV_DATA13), + GPIO_FN(DV_DATA12), + GPIO_FN(DV_DATA11), + GPIO_FN(DV_DATA10), + GPIO_FN(DV_DATA9), + GPIO_FN(DV_DATA8), + GPIO_FN(DV_DATA7), + GPIO_FN(DV_DATA6), + GPIO_FN(DV_DATA5), + GPIO_FN(DV_DATA4), + GPIO_FN(DV_DATA3), + GPIO_FN(DV_DATA2), + GPIO_FN(DV_DATA1), + GPIO_FN(DV_DATA0), + + GPIO_FN(LCD_CLK), + GPIO_FN(LCD_EXTCLK), + GPIO_FN(LCD_VSYNC), + GPIO_FN(LCD_HSYNC), + GPIO_FN(LCD_DE), + + GPIO_FN(LCD_DATA23_PG23), + GPIO_FN(LCD_DATA22_PG22), + GPIO_FN(LCD_DATA21_PG21), + GPIO_FN(LCD_DATA20_PG20), + GPIO_FN(LCD_DATA19_PG19), + GPIO_FN(LCD_DATA18_PG18), + GPIO_FN(LCD_DATA17_PG17), + GPIO_FN(LCD_DATA16_PG16), + GPIO_FN(LCD_DATA15_PG15), + GPIO_FN(LCD_DATA14_PG14), + GPIO_FN(LCD_DATA13_PG13), + GPIO_FN(LCD_DATA12_PG12), + GPIO_FN(LCD_DATA11_PG11), + GPIO_FN(LCD_DATA10_PG10), + GPIO_FN(LCD_DATA9_PG9), + GPIO_FN(LCD_DATA8_PG8), + GPIO_FN(LCD_DATA7_PG7), + GPIO_FN(LCD_DATA6_PG6), + GPIO_FN(LCD_DATA5_PG5), + GPIO_FN(LCD_DATA4_PG4), + GPIO_FN(LCD_DATA3_PG3), + GPIO_FN(LCD_DATA2_PG2), + GPIO_FN(LCD_DATA1_PG1), + GPIO_FN(LCD_DATA0_PG0), + + GPIO_FN(LCD_DATA23_PJ23), + GPIO_FN(LCD_DATA22_PJ22), + GPIO_FN(LCD_DATA21_PJ21), + GPIO_FN(LCD_DATA20_PJ20), + GPIO_FN(LCD_DATA19_PJ19), + GPIO_FN(LCD_DATA18_PJ18), + GPIO_FN(LCD_DATA17_PJ17), + GPIO_FN(LCD_DATA16_PJ16), + GPIO_FN(LCD_DATA15_PJ15), + GPIO_FN(LCD_DATA14_PJ14), + GPIO_FN(LCD_DATA13_PJ13), + GPIO_FN(LCD_DATA12_PJ12), + GPIO_FN(LCD_DATA11_PJ11), + GPIO_FN(LCD_DATA10_PJ10), + GPIO_FN(LCD_DATA9_PJ9), + GPIO_FN(LCD_DATA8_PJ8), + GPIO_FN(LCD_DATA7_PJ7), + GPIO_FN(LCD_DATA6_PJ6), + GPIO_FN(LCD_DATA5_PJ5), + GPIO_FN(LCD_DATA4_PJ4), + GPIO_FN(LCD_DATA3_PJ3), + GPIO_FN(LCD_DATA2_PJ2), + GPIO_FN(LCD_DATA1_PJ1), + GPIO_FN(LCD_DATA0_PJ0), + + GPIO_FN(LCD_M_DISP), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* "name" addr register_size Field_Width */ /* where Field_Width is 1 for single mode registers or 4 for upto 16 @@ -2734,7 +2737,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) { 0, 0, 0, 0, 0, 0, 0, PA1_DATA, 0, 0, 0, 0, 0, 0, 0, PA0_DATA } @@ -2813,19 +2816,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { } }; -struct sh_pfc_soc_info sh7269_pinmux_info = { +const struct sh_pfc_soc_info sh7269_pinmux_info = { .name = "sh7269_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA1, - .last_gpio = GPIO_FN_LCD_M_DISP, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index d44e7f02069..d9158b3b291 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -20,19 +20,43 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/io.h> #include <linux/kernel.h> -#include <mach/irqs.h> -#include <mach/sh7372.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/sh_intc.h> +#include "core.h" #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ - PORT_10(fn, pfx##10, sfx), PORT_10(fn, pfx##11, sfx), \ - PORT_10(fn, pfx##12, sfx), PORT_10(fn, pfx##13, sfx), \ - PORT_10(fn, pfx##14, sfx), PORT_10(fn, pfx##15, sfx), \ - PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ - PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) +#define CPU_ALL_PORT(fn, pfx, sfx) \ + PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ + PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \ + PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \ + PORT_10(140, fn, pfx##14, sfx), PORT_10(150, fn, pfx##15, sfx), \ + PORT_10(160, fn, pfx##16, sfx), PORT_10(170, fn, pfx##17, sfx), \ + PORT_10(180, fn, pfx##18, sfx), PORT_1(190, fn, pfx##190, sfx) + +#define IRQC_PIN_MUX(irq, pin) \ +static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +}; \ +static const unsigned int intc_irq##irq##_mux[] = { \ + IRQ##irq##_MARK, \ +} + +#define IRQC_PINS_MUX(irq, pin0, pin1) \ +static const unsigned int intc_irq##irq##_0_pins[] = { \ + pin0, \ +}; \ +static const unsigned int intc_irq##irq##_0_mux[] = { \ + IRQ##irq##_##pin0##_MARK, \ +}; \ +static const unsigned int intc_irq##irq##_1_pins[] = { \ + pin1, \ +}; \ +static const unsigned int intc_irq##irq##_1_mux[] = { \ + IRQ##irq##_##pin1##_MARK, \ +} enum { PINMUX_RESERVED = 0, @@ -47,16 +71,6 @@ enum { PORT_ALL(IN), PINMUX_INPUT_END, - /* PORT0_IN_PU -> PORT190_IN_PU */ - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), - PINMUX_INPUT_PULLUP_END, - - /* PORT0_IN_PD -> PORT190_IN_PD */ - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), - PINMUX_INPUT_PULLDOWN_END, - /* PORT0_OUT -> PORT190_OUT */ PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), @@ -368,124 +382,8 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { - - /* specify valid pin states for each pin in GPIO mode */ - PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), - PORT_DATA_O(2), PORT_DATA_I_PD(3), - PORT_DATA_I_PD(4), PORT_DATA_I_PD(5), - PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7), - PORT_DATA_IO_PD(8), PORT_DATA_O(9), - - PORT_DATA_O(10), PORT_DATA_O(11), - PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13), - PORT_DATA_IO_PD(14), PORT_DATA_O(15), - PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), - PORT_DATA_I_PD(18), PORT_DATA_IO(19), - - PORT_DATA_IO(20), PORT_DATA_IO(21), - PORT_DATA_IO(22), PORT_DATA_IO(23), - PORT_DATA_IO(24), PORT_DATA_IO(25), - PORT_DATA_IO(26), PORT_DATA_IO(27), - PORT_DATA_IO(28), PORT_DATA_IO(29), - - PORT_DATA_IO(30), PORT_DATA_IO(31), - PORT_DATA_IO(32), PORT_DATA_IO(33), - PORT_DATA_IO(34), PORT_DATA_IO(35), - PORT_DATA_IO(36), PORT_DATA_IO(37), - PORT_DATA_IO(38), PORT_DATA_IO(39), - - PORT_DATA_IO(40), PORT_DATA_IO(41), - PORT_DATA_IO(42), PORT_DATA_IO(43), - PORT_DATA_IO(44), PORT_DATA_IO(45), - PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47), - PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49), - - PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51), - PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53), - PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55), - PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57), - PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59), - - PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61), - PORT_DATA_IO(62), PORT_DATA_O(63), - PORT_DATA_O(64), PORT_DATA_IO_PU(65), - PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/ - PORT_DATA_O(68), PORT_DATA_IO(69), - - PORT_DATA_IO(70), PORT_DATA_IO(71), - PORT_DATA_O(72), PORT_DATA_I_PU(73), - PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75), - PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), - PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), - - PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), - PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83), - PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85), - PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87), - PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89), - - PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91), - PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), - PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), - PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97), - PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/ - - PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101), - PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103), - PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), - PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107), - PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109), - - PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111), - PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113), - PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115), - PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117), - PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), - - PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121), - PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), - PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125), - PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127), - PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129), - - PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131), - PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133), - PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135), - PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137), - PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139), - - PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141), - PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143), - PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145), - PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147), - PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149), - - PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), - PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153), - PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155), - PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), - PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159), - - PORT_DATA_O(160), PORT_DATA_IO_PD(161), - PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), - PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165), - PORT_DATA_I_PD(166), PORT_DATA_I_PD(167), - PORT_DATA_I_PD(168), PORT_DATA_I_PD(169), - - PORT_DATA_I_PD(170), PORT_DATA_O(171), - PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173), - PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175), - PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177), - PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179), - - PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181), - PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183), - PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185), - PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187), - PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189), - - PORT_DATA_IO_PU_PD(190), +static const u16 pinmux_data[] = { + PINMUX_DATA_ALL(), /* IRQ */ PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), @@ -929,278 +827,1298 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), }; -static struct pinmux_gpio pinmux_gpios[] = { - - /* PORT */ - GPIO_PORT_ALL(), - - /* IRQ */ - GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), - GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), - GPIO_FN(IRQ3_16), GPIO_FN(IRQ4_17), GPIO_FN(IRQ4_163), - GPIO_FN(IRQ5), GPIO_FN(IRQ6_39), GPIO_FN(IRQ6_164), - GPIO_FN(IRQ7_40), GPIO_FN(IRQ7_167), GPIO_FN(IRQ8_41), - GPIO_FN(IRQ8_168), GPIO_FN(IRQ9_42), GPIO_FN(IRQ9_169), - GPIO_FN(IRQ10), GPIO_FN(IRQ11), GPIO_FN(IRQ12_80), - GPIO_FN(IRQ12_137), GPIO_FN(IRQ13_81), GPIO_FN(IRQ13_145), - GPIO_FN(IRQ14_82), GPIO_FN(IRQ14_146), GPIO_FN(IRQ15_83), - GPIO_FN(IRQ15_147), GPIO_FN(IRQ16_84), GPIO_FN(IRQ16_170), - GPIO_FN(IRQ17), GPIO_FN(IRQ18), GPIO_FN(IRQ19), - GPIO_FN(IRQ20), GPIO_FN(IRQ21), GPIO_FN(IRQ22), - GPIO_FN(IRQ23), GPIO_FN(IRQ24), GPIO_FN(IRQ25), - GPIO_FN(IRQ26_121), GPIO_FN(IRQ26_172), GPIO_FN(IRQ27_122), - GPIO_FN(IRQ27_180), GPIO_FN(IRQ28_123), GPIO_FN(IRQ28_181), - GPIO_FN(IRQ29_129), GPIO_FN(IRQ29_182), GPIO_FN(IRQ30_130), - GPIO_FN(IRQ30_183), GPIO_FN(IRQ31_138), GPIO_FN(IRQ31_184), - - /* MSIOF0 */ - GPIO_FN(MSIOF0_TSYNC), GPIO_FN(MSIOF0_TSCK), GPIO_FN(MSIOF0_RXD), - GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_MCK0), - GPIO_FN(MSIOF0_MCK1), GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TXD), - - /* MSIOF1 */ - GPIO_FN(MSIOF1_TSCK_39), GPIO_FN(MSIOF1_TSCK_88), - GPIO_FN(MSIOF1_TSYNC_40), GPIO_FN(MSIOF1_TSYNC_89), - GPIO_FN(MSIOF1_TXD_41), GPIO_FN(MSIOF1_TXD_90), - GPIO_FN(MSIOF1_RXD_42), GPIO_FN(MSIOF1_RXD_91), - GPIO_FN(MSIOF1_SS1_43), GPIO_FN(MSIOF1_SS1_92), - GPIO_FN(MSIOF1_SS2_44), GPIO_FN(MSIOF1_SS2_93), - GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), - GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), - - /* MSIOF2 */ - GPIO_FN(MSIOF2_RSCK), GPIO_FN(MSIOF2_RSYNC), GPIO_FN(MSIOF2_MCK0), - GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_SS1), GPIO_FN(MSIOF2_SS2), - GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD), - GPIO_FN(MSIOF2_TXD), - - /* BBIF1 */ - GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK), - GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), - GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N), - - /* BBIF2 */ - GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1), - GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD), - - /* FSI */ - GPIO_FN(FSIACK), GPIO_FN(FSIBCK), GPIO_FN(FSIAILR), - GPIO_FN(FSIAIBT), GPIO_FN(FSIAISLD), GPIO_FN(FSIAOMC), - GPIO_FN(FSIAOLR), GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), - GPIO_FN(FSIASPDIF_11), GPIO_FN(FSIASPDIF_15), - - /* FMSI */ - GPIO_FN(FMSOCK), GPIO_FN(FMSOOLR), GPIO_FN(FMSIOLR), - GPIO_FN(FMSOOBT), GPIO_FN(FMSIOBT), GPIO_FN(FMSOSLD), - GPIO_FN(FMSOILR), GPIO_FN(FMSIILR), GPIO_FN(FMSOIBT), - GPIO_FN(FMSIIBT), GPIO_FN(FMSISLD), GPIO_FN(FMSICK), - - /* SCIFA0 */ - GPIO_FN(SCIFA0_TXD), GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_SCK), - GPIO_FN(SCIFA0_RTS), GPIO_FN(SCIFA0_CTS), - - /* SCIFA1 */ - GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_SCK), - GPIO_FN(SCIFA1_RTS), GPIO_FN(SCIFA1_CTS), - - /* SCIFA2 */ - GPIO_FN(SCIFA2_CTS1), GPIO_FN(SCIFA2_RTS1), GPIO_FN(SCIFA2_TXD1), - GPIO_FN(SCIFA2_RXD1), GPIO_FN(SCIFA2_SCK1), - - /* SCIFA3 */ - GPIO_FN(SCIFA3_CTS_43), GPIO_FN(SCIFA3_CTS_140), - GPIO_FN(SCIFA3_RTS_44), GPIO_FN(SCIFA3_RTS_141), - GPIO_FN(SCIFA3_SCK), GPIO_FN(SCIFA3_TXD), - GPIO_FN(SCIFA3_RXD), - - /* SCIFA4 */ - GPIO_FN(SCIFA4_RXD), GPIO_FN(SCIFA4_TXD), - - /* SCIFA5 */ - GPIO_FN(SCIFA5_RXD), GPIO_FN(SCIFA5_TXD), - - /* SCIFB */ - GPIO_FN(SCIFB_SCK), GPIO_FN(SCIFB_RTS), GPIO_FN(SCIFB_CTS), - GPIO_FN(SCIFB_TXD), GPIO_FN(SCIFB_RXD), - - /* CEU */ - GPIO_FN(VIO_HD), GPIO_FN(VIO_CKO1), GPIO_FN(VIO_CKO2), - GPIO_FN(VIO_VD), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD), - GPIO_FN(VIO_CKO), GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), - GPIO_FN(VIO_D2), GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), - GPIO_FN(VIO_D5), GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), - GPIO_FN(VIO_D8), GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), - GPIO_FN(VIO_D11), GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), - GPIO_FN(VIO_D14), GPIO_FN(VIO_D15), - - /* USB0 */ - GPIO_FN(IDIN_0), GPIO_FN(EXTLP_0), GPIO_FN(OVCN2_0), - GPIO_FN(PWEN_0), GPIO_FN(OVCN_0), GPIO_FN(VBUS0_0), - - /* USB1 */ - GPIO_FN(IDIN_1_18), GPIO_FN(IDIN_1_113), - GPIO_FN(OVCN_1_114), GPIO_FN(OVCN_1_162), - GPIO_FN(PWEN_1_115), GPIO_FN(PWEN_1_138), - GPIO_FN(EXTLP_1), GPIO_FN(OVCN2_1), - GPIO_FN(VBUS0_1), - - /* GPIO */ - GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPO0), GPIO_FN(GPO1), - - /* BSC */ - GPIO_FN(BS), GPIO_FN(WE1), GPIO_FN(CKO), - GPIO_FN(WAIT), GPIO_FN(RDWR), - - GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), - GPIO_FN(A3), GPIO_FN(A6), GPIO_FN(A7), - GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10), - GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), - GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), - GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19), - GPIO_FN(A20), GPIO_FN(A21), GPIO_FN(A22), - GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), - GPIO_FN(A26), - - GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), - GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(CS6A), +#define __I (SH_PFC_PIN_CFG_INPUT) +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) +#define __PU (SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define SH7372_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) +#define SH7372_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) +#define SH7372_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD) +#define SH7372_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO) +#define SH7372_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD) +#define SH7372_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU) +#define SH7372_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) +#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) +#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) + +static const struct sh_pfc_pin pinmux_pins[] = { + /* Table 57-1 (I/O and Pull U/D) */ + SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1), + SH7372_PIN_O(2), SH7372_PIN_I_PD(3), + SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5), + SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7), + SH7372_PIN_IO_PD(8), SH7372_PIN_O(9), + SH7372_PIN_O(10), SH7372_PIN_O(11), + SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13), + SH7372_PIN_IO_PD(14), SH7372_PIN_O(15), + SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17), + SH7372_PIN_I_PD(18), SH7372_PIN_IO(19), + SH7372_PIN_IO(20), SH7372_PIN_IO(21), + SH7372_PIN_IO(22), SH7372_PIN_IO(23), + SH7372_PIN_IO(24), SH7372_PIN_IO(25), + SH7372_PIN_IO(26), SH7372_PIN_IO(27), + SH7372_PIN_IO(28), SH7372_PIN_IO(29), + SH7372_PIN_IO(30), SH7372_PIN_IO(31), + SH7372_PIN_IO(32), SH7372_PIN_IO(33), + SH7372_PIN_IO(34), SH7372_PIN_IO(35), + SH7372_PIN_IO(36), SH7372_PIN_IO(37), + SH7372_PIN_IO(38), SH7372_PIN_IO(39), + SH7372_PIN_IO(40), SH7372_PIN_IO(41), + SH7372_PIN_IO(42), SH7372_PIN_IO(43), + SH7372_PIN_IO(44), SH7372_PIN_IO(45), + SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47), + SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49), + SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51), + SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53), + SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55), + SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57), + SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59), + SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61), + SH7372_PIN_IO(62), SH7372_PIN_O(63), + SH7372_PIN_O(64), SH7372_PIN_IO_PU(65), + SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67), + SH7372_PIN_O(68), SH7372_PIN_IO(69), + SH7372_PIN_IO(70), SH7372_PIN_IO(71), + SH7372_PIN_O(72), SH7372_PIN_I_PU(73), + SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75), + SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77), + SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79), + SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81), + SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83), + SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85), + SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87), + SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89), + SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91), + SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93), + SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95), + SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97), + SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99), + SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101), + SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103), + SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105), + SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107), + SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109), + SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111), + SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113), + SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115), + SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117), + SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119), + SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121), + SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123), + SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125), + SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127), + SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129), + SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131), + SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133), + SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135), + SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137), + SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139), + SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141), + SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143), + SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145), + SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147), + SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149), + SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151), + SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153), + SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155), + SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157), + SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159), + SH7372_PIN_O(160), SH7372_PIN_IO_PD(161), + SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163), + SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165), + SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167), + SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169), + SH7372_PIN_I_PD(170), SH7372_PIN_O(171), + SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173), + SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175), + SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177), + SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179), + SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181), + SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183), + SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185), + SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187), + SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189), + SH7372_PIN_IO_PU_PD(190), +}; - /* BSC/FLCTL */ - GPIO_FN(RD_FSC), GPIO_FN(WE0_FWE), GPIO_FN(A4_FOE), - GPIO_FN(A5_FCDE), GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), - GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), GPIO_FN(D4_NAF4), - GPIO_FN(D5_NAF5), GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), - GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), GPIO_FN(D10_NAF10), - GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), - GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), +/* - BSC -------------------------------------------------------------------- */ +static const unsigned int bsc_data8_pins[] = { + /* D[0:7] */ + 46, 47, 48, 49, 50, 51, 52, 53, +}; +static const unsigned int bsc_data8_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, +}; +static const unsigned int bsc_data16_pins[] = { + /* D[0:15] */ + 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, +}; +static const unsigned int bsc_data16_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int bsc_cs0_pins[] = { + /* CS */ + 62, +}; +static const unsigned int bsc_cs0_mux[] = { + CS0_MARK, +}; +static const unsigned int bsc_cs2_pins[] = { + /* CS */ + 63, +}; +static const unsigned int bsc_cs2_mux[] = { + CS2_MARK, +}; +static const unsigned int bsc_cs4_pins[] = { + /* CS */ + 64, +}; +static const unsigned int bsc_cs4_mux[] = { + CS4_MARK, +}; +static const unsigned int bsc_cs5a_pins[] = { + /* CS */ + 65, +}; +static const unsigned int bsc_cs5a_mux[] = { + CS5A_MARK, +}; +static const unsigned int bsc_cs5b_pins[] = { + /* CS */ + 66, +}; +static const unsigned int bsc_cs5b_mux[] = { + CS5B_MARK, +}; +static const unsigned int bsc_cs6a_pins[] = { + /* CS */ + 67, +}; +static const unsigned int bsc_cs6a_mux[] = { + CS6A_MARK, +}; +static const unsigned int bsc_rd_we8_pins[] = { + /* RD, WE[0] */ + 69, 70, +}; +static const unsigned int bsc_rd_we8_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, +}; +static const unsigned int bsc_rd_we16_pins[] = { + /* RD, WE[0:1] */ + 69, 70, 71, +}; +static const unsigned int bsc_rd_we16_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, +}; +static const unsigned int bsc_bs_pins[] = { + /* BS */ + 19, +}; +static const unsigned int bsc_bs_mux[] = { + BS_MARK, +}; +static const unsigned int bsc_rdwr_pins[] = { + /* RDWR */ + 75, +}; +static const unsigned int bsc_rdwr_mux[] = { + RDWR_MARK, +}; +static const unsigned int bsc_wait_pins[] = { + /* WAIT */ + 74, +}; +static const unsigned int bsc_wait_mux[] = { + WAIT_MARK, +}; +/* - CEU -------------------------------------------------------------------- */ +static const unsigned int ceu_data_0_7_pins[] = { + /* D[0:7] */ + 102, 103, 104, 105, 106, 107, 108, 109, +}; +static const unsigned int ceu_data_0_7_mux[] = { + VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK, + VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK, +}; +static const unsigned int ceu_data_8_15_pins[] = { + /* D[8:15] */ + 110, 111, 112, 113, 114, 115, 116, 117, +}; +static const unsigned int ceu_data_8_15_mux[] = { + VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, + VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK, +}; +static const unsigned int ceu_clk_0_pins[] = { + /* CKO */ + 120, +}; +static const unsigned int ceu_clk_0_mux[] = { + VIO_CKO_MARK, +}; +static const unsigned int ceu_clk_1_pins[] = { + /* CKO */ + 16, +}; +static const unsigned int ceu_clk_1_mux[] = { + VIO_CKO1_MARK, +}; +static const unsigned int ceu_clk_2_pins[] = { + /* CKO */ + 17, +}; +static const unsigned int ceu_clk_2_mux[] = { + VIO_CKO2_MARK, +}; +static const unsigned int ceu_sync_pins[] = { + /* CLK, VD, HD */ + 118, 100, 101, +}; +static const unsigned int ceu_sync_mux[] = { + VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, +}; +static const unsigned int ceu_field_pins[] = { + /* FIELD */ + 119, +}; +static const unsigned int ceu_field_mux[] = { + VIO_FIELD_MARK, +}; +/* - FLCTL ------------------------------------------------------------------ */ +static const unsigned int flctl_data_pins[] = { + /* NAF[0:15] */ + 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, +}; +static const unsigned int flctl_data_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int flctl_ce0_pins[] = { + /* CE */ + 68, +}; +static const unsigned int flctl_ce0_mux[] = { + FCE0_MARK, +}; +static const unsigned int flctl_ce1_pins[] = { + /* CE */ + 66, +}; +static const unsigned int flctl_ce1_mux[] = { + FCE1_MARK, +}; +static const unsigned int flctl_ctrl_pins[] = { + /* FCDE, FOE, FSC, FWE, FRB */ + 24, 23, 69, 70, 73, +}; +static const unsigned int flctl_ctrl_mux[] = { + A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK, +}; +/* - FSIA ------------------------------------------------------------------- */ +static const unsigned int fsia_mclk_in_pins[] = { + /* CK */ + 4, +}; +static const unsigned int fsia_mclk_in_mux[] = { + FSIACK_MARK, +}; +static const unsigned int fsia_mclk_out_pins[] = { + /* OMC */ + 8, +}; +static const unsigned int fsia_mclk_out_mux[] = { + FSIAOMC_MARK, +}; +static const unsigned int fsia_sclk_in_pins[] = { + /* ILR, IBT */ + 5, 6, +}; +static const unsigned int fsia_sclk_in_mux[] = { + FSIAILR_MARK, FSIAIBT_MARK, +}; +static const unsigned int fsia_sclk_out_pins[] = { + /* OLR, OBT */ + 9, 10, +}; +static const unsigned int fsia_sclk_out_mux[] = { + FSIAOLR_MARK, FSIAOBT_MARK, +}; +static const unsigned int fsia_data_in_pins[] = { + /* ISLD */ + 7, +}; +static const unsigned int fsia_data_in_mux[] = { + FSIAISLD_MARK, +}; +static const unsigned int fsia_data_out_pins[] = { + /* OSLD */ + 11, +}; +static const unsigned int fsia_data_out_mux[] = { + FSIAOSLD_MARK, +}; +static const unsigned int fsia_spdif_0_pins[] = { + /* SPDIF */ + 11, +}; +static const unsigned int fsia_spdif_0_mux[] = { + FSIASPDIF_11_MARK, +}; +static const unsigned int fsia_spdif_1_pins[] = { + /* SPDIF */ + 15, +}; +static const unsigned int fsia_spdif_1_mux[] = { + FSIASPDIF_15_MARK, +}; +/* - FSIB ------------------------------------------------------------------- */ +static const unsigned int fsib_mclk_in_pins[] = { + /* CK */ + 4, +}; +static const unsigned int fsib_mclk_in_mux[] = { + FSIBCK_MARK, +}; +/* - HDMI ------------------------------------------------------------------- */ +static const unsigned int hdmi_pins[] = { + /* HPD, CEC */ + 169, 170, +}; +static const unsigned int hdmi_mux[] = { + HDMI_HPD_MARK, HDMI_CEC_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +IRQC_PINS_MUX(0, 6, 162); +IRQC_PIN_MUX(1, 12); +IRQC_PINS_MUX(2, 4, 5); +IRQC_PINS_MUX(3, 8, 16); +IRQC_PINS_MUX(4, 17, 163); +IRQC_PIN_MUX(5, 18); +IRQC_PINS_MUX(6, 39, 164); +IRQC_PINS_MUX(7, 40, 167); +IRQC_PINS_MUX(8, 41, 168); +IRQC_PINS_MUX(9, 42, 169); +IRQC_PIN_MUX(10, 65); +IRQC_PIN_MUX(11, 67); +IRQC_PINS_MUX(12, 80, 137); +IRQC_PINS_MUX(13, 81, 145); +IRQC_PINS_MUX(14, 82, 146); +IRQC_PINS_MUX(15, 83, 147); +IRQC_PINS_MUX(16, 84, 170); +IRQC_PIN_MUX(17, 85); +IRQC_PIN_MUX(18, 86); +IRQC_PIN_MUX(19, 87); +IRQC_PIN_MUX(20, 92); +IRQC_PIN_MUX(21, 93); +IRQC_PIN_MUX(22, 94); +IRQC_PIN_MUX(23, 95); +IRQC_PIN_MUX(24, 112); +IRQC_PIN_MUX(25, 119); +IRQC_PINS_MUX(26, 121, 172); +IRQC_PINS_MUX(27, 122, 180); +IRQC_PINS_MUX(28, 123, 181); +IRQC_PINS_MUX(29, 129, 182); +IRQC_PINS_MUX(30, 130, 183); +IRQC_PINS_MUX(31, 138, 184); +/* - KEYSC ------------------------------------------------------------------ */ +static const unsigned int keysc_in04_0_pins[] = { + /* KEYIN[0:4] */ + 136, 135, 134, 133, 132, +}; +static const unsigned int keysc_in04_0_mux[] = { + KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK, + KEYIN4_MARK, +}; +static const unsigned int keysc_in04_1_pins[] = { + /* KEYIN[0:4] */ + 121, 122, 123, 124, 132, +}; +static const unsigned int keysc_in04_1_mux[] = { + KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK, + KEYIN4_MARK, +}; +static const unsigned int keysc_in5_pins[] = { + /* KEYIN5 */ + 131, +}; +static const unsigned int keysc_in5_mux[] = { + KEYIN5_MARK, +}; +static const unsigned int keysc_in6_pins[] = { + /* KEYIN6 */ + 130, +}; +static const unsigned int keysc_in6_mux[] = { + KEYIN6_MARK, +}; +static const unsigned int keysc_in7_pins[] = { + /* KEYIN7 */ + 129, +}; +static const unsigned int keysc_in7_mux[] = { + KEYIN7_MARK, +}; +static const unsigned int keysc_out4_pins[] = { + /* KEYOUT[0:3] */ + 128, 127, 126, 125, +}; +static const unsigned int keysc_out4_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, +}; +static const unsigned int keysc_out5_pins[] = { + /* KEYOUT[0:4] */ + 128, 127, 126, 125, 124, +}; +static const unsigned int keysc_out5_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, +}; +static const unsigned int keysc_out6_pins[] = { + /* KEYOUT[0:5] */ + 128, 127, 126, 125, 124, 123, +}; +static const unsigned int keysc_out6_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, KEYOUT5_MARK, +}; +static const unsigned int keysc_out8_pins[] = { + /* KEYOUT[0:7] */ + 128, 127, 126, 125, 124, 123, 122, 121, +}; +static const unsigned int keysc_out8_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, +}; +/* - LCD -------------------------------------------------------------------- */ +static const unsigned int lcd_data8_pins[] = { + /* D[0:7] */ + 121, 122, 123, 124, 125, 126, 127, 128, +}; +static const unsigned int lcd_data8_mux[] = { + /* LCDC */ + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, +}; +static const unsigned int lcd_data9_pins[] = { + /* D[0:8] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, + 137, 138, 139, 140, 141, 142, 143, 144, +}; +static const unsigned int lcd_data9_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, +}; +static const unsigned int lcd_data12_pins[] = { + /* D[0:11] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, +}; +static const unsigned int lcd_data12_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, +}; +static const unsigned int lcd_data16_pins[] = { + /* D[0:15] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, 133, 134, 135, 136, +}; +static const unsigned int lcd_data16_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, +}; +static const unsigned int lcd_data18_pins[] = { + /* D[0:17] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, 133, 134, 135, 136, + 137, 138, +}; +static const unsigned int lcd_data18_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, +}; +static const unsigned int lcd_data24_pins[] = { + /* D[0:23] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, 133, 134, 135, 136, + 137, 138, 139, 140, 141, 142, 143, 144, +}; +static const unsigned int lcd_data24_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, + LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, +}; +static const unsigned int lcd_display_pins[] = { + /* DON */ + 151, +}; +static const unsigned int lcd_display_mux[] = { + LCDDON_MARK, +}; +static const unsigned int lcd_lclk_pins[] = { + /* LCLK */ + 150, +}; +static const unsigned int lcd_lclk_mux[] = { + LCDLCLK_MARK, +}; +static const unsigned int lcd_sync_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 146, 145, 147, 149, +}; +static const unsigned int lcd_sync_mux[] = { + LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK, +}; +static const unsigned int lcd_sys_pins[] = { + /* CS, WR, RD, RS */ + 145, 147, 148, 149, +}; +static const unsigned int lcd_sys_mux[] = { + LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK, +}; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ + 84, +}; +static const unsigned int mmc0_data1_0_mux[] = { + MMCD0_0_MARK, +}; +static const unsigned int mmc0_data4_0_pins[] = { + /* D[0:3] */ + 84, 85, 86, 87, +}; +static const unsigned int mmc0_data4_0_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, +}; +static const unsigned int mmc0_data8_0_pins[] = { + /* D[0:7] */ + 84, 85, 86, 87, 88, 89, 90, 91, +}; +static const unsigned int mmc0_data8_0_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, + MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, +}; +static const unsigned int mmc0_ctrl_0_pins[] = { + /* CMD, CLK */ + 92, 99, +}; +static const unsigned int mmc0_ctrl_0_mux[] = { + MMCCMD0_MARK, MMCCLK0_MARK, +}; - /* MMCIF(1) */ - GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2), - GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5), - GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0), - GPIO_FN(MMCCLK0), +static const unsigned int mmc0_data1_1_pins[] = { + /* D[0] */ + 54, +}; +static const unsigned int mmc0_data1_1_mux[] = { + MMCD1_0_MARK, +}; +static const unsigned int mmc0_data4_1_pins[] = { + /* D[0:3] */ + 54, 55, 56, 57, +}; +static const unsigned int mmc0_data4_1_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, +}; +static const unsigned int mmc0_data8_1_pins[] = { + /* D[0:7] */ + 54, 55, 56, 57, 58, 59, 60, 61, +}; +static const unsigned int mmc0_data8_1_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, + MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, +}; +static const unsigned int mmc0_ctrl_1_pins[] = { + /* CMD, CLK */ + 67, 66, +}; +static const unsigned int mmc0_ctrl_1_mux[] = { + MMCCMD1_MARK, MMCCLK1_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + 153, 152, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + 156, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + 157, 158, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + 155, 154, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + 159, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + 160, 161, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + 97, 96, +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK, +}; +static const unsigned int scifa2_clk_pins[] = { + /* SCK */ + 98, +}; +static const unsigned int scifa2_clk_mux[] = { + SCIFA2_SCK1_MARK, +}; +static const unsigned int scifa2_ctrl_pins[] = { + /* RTS, CTS */ + 95, 94, +}; +static const unsigned int scifa2_ctrl_mux[] = { + SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_pins[] = { + /* RXD, TXD */ + 144, 143, +}; +static const unsigned int scifa3_data_mux[] = { + SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, +}; +static const unsigned int scifa3_clk_pins[] = { + /* SCK */ + 142, +}; +static const unsigned int scifa3_clk_mux[] = { + SCIFA3_SCK_MARK, +}; +static const unsigned int scifa3_ctrl_0_pins[] = { + /* RTS, CTS */ + 44, 43, +}; +static const unsigned int scifa3_ctrl_0_mux[] = { + SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK, +}; +static const unsigned int scifa3_ctrl_1_pins[] = { + /* RTS, CTS */ + 141, 140, +}; +static const unsigned int scifa3_ctrl_1_mux[] = { + SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_pins[] = { + /* RXD, TXD */ + 5, 6, +}; +static const unsigned int scifa4_data_mux[] = { + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_pins[] = { + /* RXD, TXD */ + 8, 12, +}; +static const unsigned int scifa5_data_mux[] = { + SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, +}; +/* - SCIFB ------------------------------------------------------------------ */ +static const unsigned int scifb_data_pins[] = { + /* RXD, TXD */ + 166, 165, +}; +static const unsigned int scifb_data_mux[] = { + SCIFB_RXD_MARK, SCIFB_TXD_MARK, +}; +static const unsigned int scifb_clk_pins[] = { + /* SCK */ + 162, +}; +static const unsigned int scifb_clk_mux[] = { + SCIFB_SCK_MARK, +}; +static const unsigned int scifb_ctrl_pins[] = { + /* RTS, CTS */ + 163, 164, +}; +static const unsigned int scifb_ctrl_mux[] = { + SCIFB_RTS_MARK, SCIFB_CTS_MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + 173, +}; +static const unsigned int sdhi0_data1_mux[] = { + SDHID0_0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + 173, 174, 175, 176, +}; +static const unsigned int sdhi0_data4_mux[] = { + SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CMD, CLK */ + 177, 171, +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SDHICMD0_MARK, SDHICLK0_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + 172, +}; +static const unsigned int sdhi0_cd_mux[] = { + SDHICD0_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + 178, +}; +static const unsigned int sdhi0_wp_mux[] = { + SDHIWP0_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + 180, +}; +static const unsigned int sdhi1_data1_mux[] = { + SDHID1_0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + 180, 181, 182, 183, +}; +static const unsigned int sdhi1_data4_mux[] = { + SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CMD, CLK */ + 184, 179, +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SDHICMD1_MARK, SDHICLK1_MARK, +}; - /* MMCIF(2) */ - GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2), - GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5), - GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1), - GPIO_FN(MMCCMD1), +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + 186, +}; +static const unsigned int sdhi2_data1_mux[] = { + SDHID2_0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + 186, 187, 188, 189, +}; +static const unsigned int sdhi2_data4_mux[] = { + SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CMD, CLK */ + 190, 185, +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SDHICMD2_MARK, SDHICLK2_MARK, +}; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_vbus_pins[] = { + /* VBUS */ + 167, +}; +static const unsigned int usb0_vbus_mux[] = { + VBUS0_0_MARK, +}; +static const unsigned int usb0_otg_id_pins[] = { + /* IDIN */ + 113, +}; +static const unsigned int usb0_otg_id_mux[] = { + IDIN_0_MARK, +}; +static const unsigned int usb0_otg_ctrl_pins[] = { + /* PWEN, EXTLP, OVCN, OVCN2 */ + 116, 114, 117, 115, +}; +static const unsigned int usb0_otg_ctrl_mux[] = { + PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_vbus_pins[] = { + /* VBUS */ + 168, +}; +static const unsigned int usb1_vbus_mux[] = { + VBUS0_1_MARK, +}; +static const unsigned int usb1_otg_id_0_pins[] = { + /* IDIN */ + 113, +}; +static const unsigned int usb1_otg_id_0_mux[] = { + IDIN_1_113_MARK, +}; +static const unsigned int usb1_otg_id_1_pins[] = { + /* IDIN */ + 18, +}; +static const unsigned int usb1_otg_id_1_mux[] = { + IDIN_1_18_MARK, +}; +static const unsigned int usb1_otg_ctrl_0_pins[] = { + /* PWEN, EXTLP, OVCN, OVCN2 */ + 115, 116, 114, 117, 113, +}; +static const unsigned int usb1_otg_ctrl_0_mux[] = { + PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK, +}; +static const unsigned int usb1_otg_ctrl_1_pins[] = { + /* PWEN, EXTLP, OVCN, OVCN2 */ + 138, 116, 162, 117, 18, +}; +static const unsigned int usb1_otg_ctrl_1_mux[] = { + PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK, +}; - /* SPU2 */ - GPIO_FN(VINT_I), +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data8), + SH_PFC_PIN_GROUP(bsc_data16), + SH_PFC_PIN_GROUP(bsc_cs0), + SH_PFC_PIN_GROUP(bsc_cs2), + SH_PFC_PIN_GROUP(bsc_cs4), + SH_PFC_PIN_GROUP(bsc_cs5a), + SH_PFC_PIN_GROUP(bsc_cs5b), + SH_PFC_PIN_GROUP(bsc_cs6a), + SH_PFC_PIN_GROUP(bsc_rd_we8), + SH_PFC_PIN_GROUP(bsc_rd_we16), + SH_PFC_PIN_GROUP(bsc_bs), + SH_PFC_PIN_GROUP(bsc_rdwr), + SH_PFC_PIN_GROUP(ceu_data_0_7), + SH_PFC_PIN_GROUP(ceu_data_8_15), + SH_PFC_PIN_GROUP(ceu_clk_0), + SH_PFC_PIN_GROUP(ceu_clk_1), + SH_PFC_PIN_GROUP(ceu_clk_2), + SH_PFC_PIN_GROUP(ceu_sync), + SH_PFC_PIN_GROUP(ceu_field), + SH_PFC_PIN_GROUP(flctl_data), + SH_PFC_PIN_GROUP(flctl_ce0), + SH_PFC_PIN_GROUP(flctl_ce1), + SH_PFC_PIN_GROUP(flctl_ctrl), + SH_PFC_PIN_GROUP(fsia_mclk_in), + SH_PFC_PIN_GROUP(fsia_mclk_out), + SH_PFC_PIN_GROUP(fsia_sclk_in), + SH_PFC_PIN_GROUP(fsia_sclk_out), + SH_PFC_PIN_GROUP(fsia_data_in), + SH_PFC_PIN_GROUP(fsia_data_out), + SH_PFC_PIN_GROUP(fsia_spdif_0), + SH_PFC_PIN_GROUP(fsia_spdif_1), + SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(hdmi), + SH_PFC_PIN_GROUP(intc_irq0_0), + SH_PFC_PIN_GROUP(intc_irq0_1), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2_0), + SH_PFC_PIN_GROUP(intc_irq2_1), + SH_PFC_PIN_GROUP(intc_irq3_0), + SH_PFC_PIN_GROUP(intc_irq3_1), + SH_PFC_PIN_GROUP(intc_irq4_0), + SH_PFC_PIN_GROUP(intc_irq4_1), + SH_PFC_PIN_GROUP(intc_irq5), + SH_PFC_PIN_GROUP(intc_irq6_0), + SH_PFC_PIN_GROUP(intc_irq6_1), + SH_PFC_PIN_GROUP(intc_irq7_0), + SH_PFC_PIN_GROUP(intc_irq7_1), + SH_PFC_PIN_GROUP(intc_irq8_0), + SH_PFC_PIN_GROUP(intc_irq8_1), + SH_PFC_PIN_GROUP(intc_irq9_0), + SH_PFC_PIN_GROUP(intc_irq9_1), + SH_PFC_PIN_GROUP(intc_irq10), + SH_PFC_PIN_GROUP(intc_irq11), + SH_PFC_PIN_GROUP(intc_irq12_0), + SH_PFC_PIN_GROUP(intc_irq12_1), + SH_PFC_PIN_GROUP(intc_irq13_0), + SH_PFC_PIN_GROUP(intc_irq13_1), + SH_PFC_PIN_GROUP(intc_irq14_0), + SH_PFC_PIN_GROUP(intc_irq14_1), + SH_PFC_PIN_GROUP(intc_irq15_0), + SH_PFC_PIN_GROUP(intc_irq15_1), + SH_PFC_PIN_GROUP(intc_irq16_0), + SH_PFC_PIN_GROUP(intc_irq16_1), + SH_PFC_PIN_GROUP(intc_irq17), + SH_PFC_PIN_GROUP(intc_irq18), + SH_PFC_PIN_GROUP(intc_irq19), + SH_PFC_PIN_GROUP(intc_irq20), + SH_PFC_PIN_GROUP(intc_irq21), + SH_PFC_PIN_GROUP(intc_irq22), + SH_PFC_PIN_GROUP(intc_irq23), + SH_PFC_PIN_GROUP(intc_irq24), + SH_PFC_PIN_GROUP(intc_irq25), + SH_PFC_PIN_GROUP(intc_irq26_0), + SH_PFC_PIN_GROUP(intc_irq26_1), + SH_PFC_PIN_GROUP(intc_irq27_0), + SH_PFC_PIN_GROUP(intc_irq27_1), + SH_PFC_PIN_GROUP(intc_irq28_0), + SH_PFC_PIN_GROUP(intc_irq28_1), + SH_PFC_PIN_GROUP(intc_irq29_0), + SH_PFC_PIN_GROUP(intc_irq29_1), + SH_PFC_PIN_GROUP(intc_irq30_0), + SH_PFC_PIN_GROUP(intc_irq30_1), + SH_PFC_PIN_GROUP(intc_irq31_0), + SH_PFC_PIN_GROUP(intc_irq31_1), + SH_PFC_PIN_GROUP(keysc_in04_0), + SH_PFC_PIN_GROUP(keysc_in04_1), + SH_PFC_PIN_GROUP(keysc_in5), + SH_PFC_PIN_GROUP(keysc_in6), + SH_PFC_PIN_GROUP(keysc_in7), + SH_PFC_PIN_GROUP(keysc_out4), + SH_PFC_PIN_GROUP(keysc_out5), + SH_PFC_PIN_GROUP(keysc_out6), + SH_PFC_PIN_GROUP(keysc_out8), + SH_PFC_PIN_GROUP(lcd_data8), + SH_PFC_PIN_GROUP(lcd_data9), + SH_PFC_PIN_GROUP(lcd_data12), + SH_PFC_PIN_GROUP(lcd_data16), + SH_PFC_PIN_GROUP(lcd_data18), + SH_PFC_PIN_GROUP(lcd_data24), + SH_PFC_PIN_GROUP(lcd_display), + SH_PFC_PIN_GROUP(lcd_lclk), + SH_PFC_PIN_GROUP(lcd_sync), + SH_PFC_PIN_GROUP(lcd_sys), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), + SH_PFC_PIN_GROUP(mmc0_ctrl_0), + SH_PFC_PIN_GROUP(mmc0_data1_1), + SH_PFC_PIN_GROUP(mmc0_data4_1), + SH_PFC_PIN_GROUP(mmc0_data8_1), + SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_clk), + SH_PFC_PIN_GROUP(scifa3_ctrl_0), + SH_PFC_PIN_GROUP(scifa3_ctrl_1), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa5_data), + SH_PFC_PIN_GROUP(scifb_data), + SH_PFC_PIN_GROUP(scifb_clk), + SH_PFC_PIN_GROUP(scifb_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(usb0_vbus), + SH_PFC_PIN_GROUP(usb0_otg_id), + SH_PFC_PIN_GROUP(usb0_otg_ctrl), + SH_PFC_PIN_GROUP(usb1_vbus), + SH_PFC_PIN_GROUP(usb1_otg_id_0), + SH_PFC_PIN_GROUP(usb1_otg_id_1), + SH_PFC_PIN_GROUP(usb1_otg_ctrl_0), + SH_PFC_PIN_GROUP(usb1_otg_ctrl_1), +}; - /* FLCTL */ - GPIO_FN(FCE1), GPIO_FN(FCE0), GPIO_FN(FRB), +static const char * const bsc_groups[] = { + "bsc_data8", + "bsc_data16", + "bsc_cs0", + "bsc_cs2", + "bsc_cs4", + "bsc_cs5a", + "bsc_cs5b", + "bsc_cs6a", + "bsc_rd_we8", + "bsc_rd_we16", + "bsc_bs", + "bsc_rdwr", +}; - /* HSI */ - GPIO_FN(GP_RX_FLAG), GPIO_FN(GP_RX_DATA), GPIO_FN(GP_TX_READY), - GPIO_FN(GP_RX_WAKE), GPIO_FN(MP_TX_FLAG), GPIO_FN(MP_TX_DATA), - GPIO_FN(MP_RX_READY), GPIO_FN(MP_TX_WAKE), +static const char * const ceu_groups[] = { + "ceu_data_0_7", + "ceu_data_8_15", + "ceu_clk_0", + "ceu_clk_1", + "ceu_clk_2", + "ceu_sync", + "ceu_field", +}; - /* MFI */ - GPIO_FN(MFIv6), - GPIO_FN(MFIv4), +static const char * const flctl_groups[] = { + "flctl_data", + "flctl_ce0", + "flctl_ce1", + "flctl_ctrl", +}; - GPIO_FN(MEMC_BUSCLK_MEMC_A0), GPIO_FN(MEMC_ADV_MEMC_DREQ0), - GPIO_FN(MEMC_WAIT_MEMC_DREQ1), GPIO_FN(MEMC_CS1_MEMC_A1), - GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_NOE), - GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_INT), +static const char * const fsia_groups[] = { + "fsia_mclk_in", + "fsia_mclk_out", + "fsia_sclk_in", + "fsia_sclk_out", + "fsia_data_in", + "fsia_data_out", + "fsia_spdif_0", + "fsia_spdif_1", +}; - GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), - GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), - GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), - GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), - GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), - GPIO_FN(MEMC_AD15), +static const char * const fsib_groups[] = { + "fsib_mclk_in", +}; - /* SIM */ - GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), GPIO_FN(SIM_D), +static const char * const hdmi_groups[] = { + "hdmi", +}; - /* TPU */ - GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO2_93), - GPIO_FN(TPU0TO2_99), GPIO_FN(TPU0TO3), +static const char * const intc_groups[] = { + "intc_irq0_0", + "intc_irq0_1", + "intc_irq1", + "intc_irq2_0", + "intc_irq2_1", + "intc_irq3_0", + "intc_irq3_1", + "intc_irq4_0", + "intc_irq4_1", + "intc_irq5", + "intc_irq6_0", + "intc_irq6_1", + "intc_irq7_0", + "intc_irq7_1", + "intc_irq8_0", + "intc_irq8_1", + "intc_irq9_0", + "intc_irq9_1", + "intc_irq10", + "intc_irq11", + "intc_irq12_0", + "intc_irq12_1", + "intc_irq13_0", + "intc_irq13_1", + "intc_irq14_0", + "intc_irq14_1", + "intc_irq15_0", + "intc_irq15_1", + "intc_irq16_0", + "intc_irq16_1", + "intc_irq17", + "intc_irq18", + "intc_irq19", + "intc_irq20", + "intc_irq21", + "intc_irq22", + "intc_irq23", + "intc_irq24", + "intc_irq25", + "intc_irq26_0", + "intc_irq26_1", + "intc_irq27_0", + "intc_irq27_1", + "intc_irq28_0", + "intc_irq28_1", + "intc_irq29_0", + "intc_irq29_1", + "intc_irq30_0", + "intc_irq30_1", + "intc_irq31_0", + "intc_irq31_1", +}; - /* I2C2 */ - GPIO_FN(I2C_SCL2), GPIO_FN(I2C_SDA2), +static const char * const keysc_groups[] = { + "keysc_in04_0", + "keysc_in04_1", + "keysc_in5", + "keysc_in6", + "keysc_in7", + "keysc_out4", + "keysc_out5", + "keysc_out6", + "keysc_out8", +}; - /* I2C3(1) */ - GPIO_FN(I2C_SCL3), GPIO_FN(I2C_SDA3), +static const char * const lcd_groups[] = { + "lcd_data8", + "lcd_data9", + "lcd_data12", + "lcd_data16", + "lcd_data18", + "lcd_data24", + "lcd_display", + "lcd_lclk", + "lcd_sync", + "lcd_sys", +}; - /* I2C3(2) */ - GPIO_FN(I2C_SCL3S), GPIO_FN(I2C_SDA3S), +static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", + "mmc0_data8_0", + "mmc0_ctrl_0", + "mmc0_data1_1", + "mmc0_data4_1", + "mmc0_data8_1", + "mmc0_ctrl_1", +}; - /* I2C4(2) */ - GPIO_FN(I2C_SCL4), GPIO_FN(I2C_SDA4), +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; - /* I2C4(2) */ - GPIO_FN(I2C_SCL4S), GPIO_FN(I2C_SDA4S), +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; - /* KEYSC */ - GPIO_FN(KEYOUT0), GPIO_FN(KEYIN0_121), GPIO_FN(KEYIN0_136), - GPIO_FN(KEYOUT1), GPIO_FN(KEYIN1_122), GPIO_FN(KEYIN1_135), - GPIO_FN(KEYOUT2), GPIO_FN(KEYIN2_123), GPIO_FN(KEYIN2_134), - GPIO_FN(KEYOUT3), GPIO_FN(KEYIN3_124), GPIO_FN(KEYIN3_133), - GPIO_FN(KEYOUT4), GPIO_FN(KEYIN4), GPIO_FN(KEYOUT5), - GPIO_FN(KEYIN5), GPIO_FN(KEYOUT6), GPIO_FN(KEYIN6), - GPIO_FN(KEYOUT7), GPIO_FN(KEYIN7), +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk", + "scifa2_ctrl", +}; - /* LCDC */ - GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDVSYN), - GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(LCDRD), - GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(LCDLCLK), - GPIO_FN(LCDDON), - - GPIO_FN(LCDD0), GPIO_FN(LCDD1), GPIO_FN(LCDD2), - GPIO_FN(LCDD3), GPIO_FN(LCDD4), GPIO_FN(LCDD5), - GPIO_FN(LCDD6), GPIO_FN(LCDD7), GPIO_FN(LCDD8), - GPIO_FN(LCDD9), GPIO_FN(LCDD10), GPIO_FN(LCDD11), - GPIO_FN(LCDD12), GPIO_FN(LCDD13), GPIO_FN(LCDD14), - GPIO_FN(LCDD15), GPIO_FN(LCDD16), GPIO_FN(LCDD17), - GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20), - GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23), - - GPIO_FN(LCDC0_SELECT), - GPIO_FN(LCDC1_SELECT), +static const char * const scifa3_groups[] = { + "scifa3_data", + "scifa3_clk", + "scifa3_ctrl_0", + "scifa3_ctrl_1", +}; - /* IRDA */ - GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), - GPIO_FN(IROUT_139), GPIO_FN(IROUT_140), +static const char * const scifa4_groups[] = { + "scifa4_data", +}; - /* TSIF1 */ - GPIO_FN(TS0_1SELECT), - GPIO_FN(TS0_2SELECT), - GPIO_FN(TS1_1SELECT), - GPIO_FN(TS1_2SELECT), +static const char * const scifa5_groups[] = { + "scifa5_data", +}; - GPIO_FN(TS_SPSYNC1), GPIO_FN(TS_SDAT1), - GPIO_FN(TS_SDEN1), GPIO_FN(TS_SCK1), +static const char * const scifb_groups[] = { + "scifb_data", + "scifb_clk", + "scifb_ctrl", +}; - /* TSIF2 */ - GPIO_FN(TS_SPSYNC2), GPIO_FN(TS_SDAT2), - GPIO_FN(TS_SDEN2), GPIO_FN(TS_SCK2), +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; - /* HDMI */ - GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", +}; - /* SDHI0 */ - GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0), - GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1), - GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3), +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", +}; - /* SDHI1 */ - GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0), - GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3), +static const char * const usb0_groups[] = { + "usb0_vbus", + "usb0_otg_id", + "usb0_otg_ctrl", +}; - /* SDHI2 */ - GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0), - GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3), +static const char * const usb1_groups[] = { + "usb1_vbus", + "usb1_otg_id_0", + "usb1_otg_id_1", + "usb1_otg_ctrl_0", + "usb1_otg_ctrl_1", +}; - /* SDENC */ - GPIO_FN(SDENC_CPG), - GPIO_FN(SDENC_DV_CLKI), +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu), + SH_PFC_FUNCTION(flctl), + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(keysc), + SH_PFC_FUNCTION(lcd), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifb), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xE6051000), /* PORT0CR */ PORTCR(1, 0xE6051001), /* PORT1CR */ PORTCR(2, 0xE6051002), /* PORT2CR */ @@ -1472,7 +2390,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) { PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, @@ -1597,56 +2515,125 @@ static struct pinmux_data_reg pinmux_data_regs[] = { #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) -static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0), - PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0), - PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0), - PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0), - PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0), - PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0), - PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0), - PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0), - PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0), - PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0), - PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0), - PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0), - PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0), - PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0), - PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0), - PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0), - PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0), - PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0), - PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0), - PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0), - PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0), - PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0), - PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0), - PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0), - PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0), - PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0), - PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0), - PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0), - PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0), - PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0), - PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0), - PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0), -}; - -struct sh_pfc_soc_info sh7372_pinmux_info = { +static const struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(EXT_IRQ16L(0), 6, 162), + PINMUX_IRQ(EXT_IRQ16L(1), 12), + PINMUX_IRQ(EXT_IRQ16L(2), 4, 5), + PINMUX_IRQ(EXT_IRQ16L(3), 8, 16), + PINMUX_IRQ(EXT_IRQ16L(4), 17, 163), + PINMUX_IRQ(EXT_IRQ16L(5), 18), + PINMUX_IRQ(EXT_IRQ16L(6), 39, 164), + PINMUX_IRQ(EXT_IRQ16L(7), 40, 167), + PINMUX_IRQ(EXT_IRQ16L(8), 41, 168), + PINMUX_IRQ(EXT_IRQ16L(9), 42, 169), + PINMUX_IRQ(EXT_IRQ16L(10), 65), + PINMUX_IRQ(EXT_IRQ16L(11), 67), + PINMUX_IRQ(EXT_IRQ16L(12), 80, 137), + PINMUX_IRQ(EXT_IRQ16L(13), 81, 145), + PINMUX_IRQ(EXT_IRQ16L(14), 82, 146), + PINMUX_IRQ(EXT_IRQ16L(15), 83, 147), + PINMUX_IRQ(EXT_IRQ16H(16), 84, 170), + PINMUX_IRQ(EXT_IRQ16H(17), 85), + PINMUX_IRQ(EXT_IRQ16H(18), 86), + PINMUX_IRQ(EXT_IRQ16H(19), 87), + PINMUX_IRQ(EXT_IRQ16H(20), 92), + PINMUX_IRQ(EXT_IRQ16H(21), 93), + PINMUX_IRQ(EXT_IRQ16H(22), 94), + PINMUX_IRQ(EXT_IRQ16H(23), 95), + PINMUX_IRQ(EXT_IRQ16H(24), 112), + PINMUX_IRQ(EXT_IRQ16H(25), 119), + PINMUX_IRQ(EXT_IRQ16H(26), 121, 172), + PINMUX_IRQ(EXT_IRQ16H(27), 122, 180), + PINMUX_IRQ(EXT_IRQ16H(28), 123, 181), + PINMUX_IRQ(EXT_IRQ16H(29), 129, 182), + PINMUX_IRQ(EXT_IRQ16H(30), 130, 183), + PINMUX_IRQ(EXT_IRQ16H(31), 138, 184), +}; + +#define PORTnCR_PULMD_OFF (0 << 6) +#define PORTnCR_PULMD_DOWN (2 << 6) +#define PORTnCR_PULMD_UP (3 << 6) +#define PORTnCR_PULMD_MASK (3 << 6) + +struct sh7372_portcr_group { + unsigned int end_pin; + unsigned int offset; +}; + +static const struct sh7372_portcr_group sh7372_portcr_offsets[] = { + { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 }, + { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 }, +}; + +static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) { + const struct sh7372_portcr_group *group = + &sh7372_portcr_offsets[i]; + + if (pin <= group->end_pin) + return pfc->windows->virt + group->offset + pin; + } + + return NULL; +} + +static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; + + switch (value) { + case PORTnCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTnCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTnCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTnCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTnCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +static const struct sh_pfc_soc_operations sh7372_pinmux_ops = { + .get_bias = sh7372_pinmux_get_bias, + .set_bias = sh7372_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info sh7372_pinmux_info = { .name = "sh7372_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .ops = &sh7372_pinmux_ops, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PORT0, - .last_gpio = GPIO_FN_SDENC_DV_CLKI, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 709008e9412..ee370de4609 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -18,42 +18,47 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/io.h> #include <linux/kernel.h> -#include <mach/sh73a0.h> +#include <linux/module.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/slab.h> + +#ifndef CONFIG_ARCH_MULTIPLATFORM #include <mach/irqs.h> +#endif +#include "core.h" #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \ - PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \ - PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \ - PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \ - PORT_10(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ - PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ - PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \ - PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \ - PORT_1(fn, pfx##118, sfx), \ - PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ - PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \ - PORT_10(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \ - PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \ - PORT_1(fn, pfx##164, sfx), \ - PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ - PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ - PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ - PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ - PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \ - PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \ - PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \ - PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \ - PORT_1(fn, pfx##282, sfx), \ - PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \ - PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx) +#define CPU_ALL_PORT(fn, pfx, sfx) \ + PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ + PORT_10(100, fn, pfx##10, sfx), \ + PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \ + PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \ + PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \ + PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \ + PORT_1(118, fn, pfx##118, sfx), \ + PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \ + PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \ + PORT_10(150, fn, pfx##15, sfx), \ + PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \ + PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \ + PORT_1(164, fn, pfx##164, sfx), \ + PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \ + PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \ + PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \ + PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \ + PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \ + PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \ + PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \ + PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \ + PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \ + PORT_1(282, fn, pfx##282, sfx), \ + PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \ + PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx) enum { PINMUX_RESERVED = 0, @@ -66,14 +71,6 @@ enum { PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */ PINMUX_INPUT_END, - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ - PINMUX_INPUT_PULLUP_END, - - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ - PINMUX_INPUT_PULLDOWN_END, - PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */ PINMUX_OUTPUT_END, @@ -468,328 +465,12 @@ enum { EDBGREQ_PD_MARK, EDBGREQ_PU_MARK, - /* Functions with pull-ups */ - KEYIN0_PU_MARK, - KEYIN1_PU_MARK, - KEYIN2_PU_MARK, - KEYIN3_PU_MARK, - KEYIN4_PU_MARK, - KEYIN5_PU_MARK, - KEYIN6_PU_MARK, - KEYIN7_PU_MARK, - SDHICD0_PU_MARK, - SDHID0_0_PU_MARK, - SDHID0_1_PU_MARK, - SDHID0_2_PU_MARK, - SDHID0_3_PU_MARK, - SDHICMD0_PU_MARK, - SDHIWP0_PU_MARK, - SDHID1_0_PU_MARK, - SDHID1_1_PU_MARK, - SDHID1_2_PU_MARK, - SDHID1_3_PU_MARK, - SDHICMD1_PU_MARK, - SDHID2_0_PU_MARK, - SDHID2_1_PU_MARK, - SDHID2_2_PU_MARK, - SDHID2_3_PU_MARK, - SDHICMD2_PU_MARK, - MMCCMD0_PU_MARK, - MMCCMD1_PU_MARK, - MMCD0_0_PU_MARK, - MMCD0_1_PU_MARK, - MMCD0_2_PU_MARK, - MMCD0_3_PU_MARK, - MMCD0_4_PU_MARK, - MMCD0_5_PU_MARK, - MMCD0_6_PU_MARK, - MMCD0_7_PU_MARK, - FSIBISLD_PU_MARK, - FSIACK_PU_MARK, - FSIAILR_PU_MARK, - FSIAIBT_PU_MARK, - FSIAISLD_PU_MARK, - PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const u16 pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ - - /* Table 25-1 (I/O and Pull U/D) */ - PORT_DATA_I_PD(0), - PORT_DATA_I_PU(1), - PORT_DATA_I_PU(2), - PORT_DATA_I_PU(3), - PORT_DATA_I_PU(4), - PORT_DATA_I_PU(5), - PORT_DATA_I_PU(6), - PORT_DATA_I_PU(7), - PORT_DATA_I_PU(8), - PORT_DATA_I_PD(9), - PORT_DATA_I_PD(10), - PORT_DATA_I_PU_PD(11), - PORT_DATA_IO_PU_PD(12), - PORT_DATA_IO_PU_PD(13), - PORT_DATA_IO_PU_PD(14), - PORT_DATA_IO_PU_PD(15), - PORT_DATA_IO_PD(16), - PORT_DATA_IO_PD(17), - PORT_DATA_IO_PU(18), - PORT_DATA_IO_PU(19), - PORT_DATA_O(20), - PORT_DATA_O(21), - PORT_DATA_O(22), - PORT_DATA_O(23), - PORT_DATA_O(24), - PORT_DATA_I_PD(25), - PORT_DATA_I_PD(26), - PORT_DATA_IO_PU(27), - PORT_DATA_IO_PU(28), - PORT_DATA_IO_PD(29), - PORT_DATA_IO_PD(30), - PORT_DATA_IO_PU(31), - PORT_DATA_IO_PD(32), - PORT_DATA_I_PU_PD(33), - PORT_DATA_IO_PD(34), - PORT_DATA_I_PU_PD(35), - PORT_DATA_IO_PD(36), - PORT_DATA_IO(37), - PORT_DATA_O(38), - PORT_DATA_I_PU(39), - PORT_DATA_I_PU_PD(40), - PORT_DATA_O(41), - PORT_DATA_IO_PD(42), - PORT_DATA_IO_PU_PD(43), - PORT_DATA_IO_PU_PD(44), - PORT_DATA_IO_PD(45), - PORT_DATA_IO_PD(46), - PORT_DATA_IO_PD(47), - PORT_DATA_I_PD(48), - PORT_DATA_IO_PU_PD(49), - PORT_DATA_IO_PD(50), - - PORT_DATA_IO_PD(51), - PORT_DATA_O(52), - PORT_DATA_IO_PU_PD(53), - PORT_DATA_IO_PU_PD(54), - PORT_DATA_IO_PD(55), - PORT_DATA_I_PU_PD(56), - PORT_DATA_IO(57), - PORT_DATA_IO(58), - PORT_DATA_IO(59), - PORT_DATA_IO(60), - PORT_DATA_IO(61), - PORT_DATA_IO_PD(62), - PORT_DATA_IO_PD(63), - PORT_DATA_IO_PU_PD(64), - PORT_DATA_IO_PD(65), - PORT_DATA_IO_PU_PD(66), - PORT_DATA_IO_PU_PD(67), - PORT_DATA_IO_PU_PD(68), - PORT_DATA_IO_PU_PD(69), - PORT_DATA_IO_PU_PD(70), - PORT_DATA_IO_PU_PD(71), - PORT_DATA_IO_PU_PD(72), - PORT_DATA_I_PU_PD(73), - PORT_DATA_IO_PU(74), - PORT_DATA_IO_PU(75), - PORT_DATA_IO_PU(76), - PORT_DATA_IO_PU(77), - PORT_DATA_IO_PU(78), - PORT_DATA_IO_PU(79), - PORT_DATA_IO_PU(80), - PORT_DATA_IO_PU(81), - PORT_DATA_IO_PU(82), - PORT_DATA_IO_PU(83), - PORT_DATA_IO_PU(84), - PORT_DATA_IO_PU(85), - PORT_DATA_IO_PU(86), - PORT_DATA_IO_PU(87), - PORT_DATA_IO_PU(88), - PORT_DATA_IO_PU(89), - PORT_DATA_O(90), - PORT_DATA_IO_PU(91), - PORT_DATA_O(92), - PORT_DATA_IO_PU(93), - PORT_DATA_O(94), - PORT_DATA_I_PU_PD(95), - PORT_DATA_IO(96), - PORT_DATA_IO(97), - PORT_DATA_IO(98), - PORT_DATA_I_PU(99), - PORT_DATA_O(100), - PORT_DATA_O(101), - PORT_DATA_I_PU(102), - PORT_DATA_IO_PD(103), - PORT_DATA_I_PU_PD(104), - PORT_DATA_I_PD(105), - PORT_DATA_I_PD(106), - PORT_DATA_I_PU_PD(107), - PORT_DATA_I_PU_PD(108), - PORT_DATA_IO_PD(109), - PORT_DATA_IO_PD(110), - PORT_DATA_IO_PU_PD(111), - PORT_DATA_IO_PU_PD(112), - PORT_DATA_IO_PU_PD(113), - PORT_DATA_IO_PD(114), - PORT_DATA_IO_PU(115), - PORT_DATA_IO_PU(116), - PORT_DATA_IO_PU_PD(117), - PORT_DATA_IO_PU_PD(118), - PORT_DATA_IO_PD(128), - - PORT_DATA_IO_PD(129), - PORT_DATA_IO_PU_PD(130), - PORT_DATA_IO_PD(131), - PORT_DATA_IO_PD(132), - PORT_DATA_IO_PD(133), - PORT_DATA_IO_PU_PD(134), - PORT_DATA_IO_PU_PD(135), - PORT_DATA_IO_PU_PD(136), - PORT_DATA_IO_PU_PD(137), - PORT_DATA_IO_PD(138), - PORT_DATA_IO_PD(139), - PORT_DATA_IO_PD(140), - PORT_DATA_IO_PD(141), - PORT_DATA_IO_PD(142), - PORT_DATA_IO_PD(143), - PORT_DATA_IO_PU_PD(144), - PORT_DATA_IO_PD(145), - PORT_DATA_IO_PU_PD(146), - PORT_DATA_IO_PU_PD(147), - PORT_DATA_IO_PU_PD(148), - PORT_DATA_IO_PU_PD(149), - PORT_DATA_I_PU_PD(150), - PORT_DATA_IO_PU_PD(151), - PORT_DATA_IO_PU_PD(152), - PORT_DATA_IO_PD(153), - PORT_DATA_IO_PD(154), - PORT_DATA_I_PU_PD(155), - PORT_DATA_IO_PU_PD(156), - PORT_DATA_I_PD(157), - PORT_DATA_IO_PD(158), - PORT_DATA_IO_PU_PD(159), - PORT_DATA_IO_PU_PD(160), - PORT_DATA_I_PU_PD(161), - PORT_DATA_I_PU_PD(162), - PORT_DATA_IO_PU_PD(163), - PORT_DATA_I_PU_PD(164), - PORT_DATA_IO_PD(192), - PORT_DATA_IO_PU_PD(193), - PORT_DATA_IO_PD(194), - PORT_DATA_IO_PU_PD(195), - PORT_DATA_IO_PD(196), - PORT_DATA_IO_PD(197), - PORT_DATA_IO_PD(198), - PORT_DATA_IO_PD(199), - PORT_DATA_IO_PU_PD(200), - PORT_DATA_IO_PU_PD(201), - PORT_DATA_IO_PU_PD(202), - PORT_DATA_IO_PU_PD(203), - PORT_DATA_IO_PU_PD(204), - PORT_DATA_IO_PU_PD(205), - PORT_DATA_IO_PU_PD(206), - PORT_DATA_IO_PD(207), - PORT_DATA_IO_PD(208), - PORT_DATA_IO_PD(209), - PORT_DATA_IO_PD(210), - PORT_DATA_IO_PD(211), - PORT_DATA_IO_PD(212), - PORT_DATA_IO_PD(213), - PORT_DATA_IO_PU_PD(214), - PORT_DATA_IO_PU_PD(215), - PORT_DATA_IO_PD(216), - PORT_DATA_IO_PD(217), - PORT_DATA_O(218), - PORT_DATA_IO_PD(219), - PORT_DATA_IO_PD(220), - PORT_DATA_IO_PU_PD(221), - PORT_DATA_IO_PU_PD(222), - PORT_DATA_I_PU_PD(223), - PORT_DATA_I_PU_PD(224), - - PORT_DATA_IO_PU_PD(225), - PORT_DATA_O(226), - PORT_DATA_IO_PU_PD(227), - PORT_DATA_I_PU_PD(228), - PORT_DATA_I_PD(229), - PORT_DATA_IO(230), - PORT_DATA_IO_PU_PD(231), - PORT_DATA_IO_PU_PD(232), - PORT_DATA_I_PU_PD(233), - PORT_DATA_IO_PU_PD(234), - PORT_DATA_IO_PU_PD(235), - PORT_DATA_IO_PU_PD(236), - PORT_DATA_IO_PD(237), - PORT_DATA_IO_PU_PD(238), - PORT_DATA_IO_PU_PD(239), - PORT_DATA_IO_PU_PD(240), - PORT_DATA_O(241), - PORT_DATA_I_PD(242), - PORT_DATA_IO_PU_PD(243), - PORT_DATA_IO_PU_PD(244), - PORT_DATA_IO_PU_PD(245), - PORT_DATA_IO_PU_PD(246), - PORT_DATA_IO_PU_PD(247), - PORT_DATA_IO_PU_PD(248), - PORT_DATA_IO_PU_PD(249), - PORT_DATA_IO_PU_PD(250), - PORT_DATA_IO_PU_PD(251), - PORT_DATA_IO_PU_PD(252), - PORT_DATA_IO_PU_PD(253), - PORT_DATA_IO_PU_PD(254), - PORT_DATA_IO_PU_PD(255), - PORT_DATA_IO_PU_PD(256), - PORT_DATA_IO_PU_PD(257), - PORT_DATA_IO_PU_PD(258), - PORT_DATA_IO_PU_PD(259), - PORT_DATA_IO_PU_PD(260), - PORT_DATA_IO_PU_PD(261), - PORT_DATA_IO_PU_PD(262), - PORT_DATA_IO_PU_PD(263), - PORT_DATA_IO_PU_PD(264), - PORT_DATA_IO_PU_PD(265), - PORT_DATA_IO_PU_PD(266), - PORT_DATA_IO_PU_PD(267), - PORT_DATA_IO_PU_PD(268), - PORT_DATA_IO_PU_PD(269), - PORT_DATA_IO_PU_PD(270), - PORT_DATA_IO_PU_PD(271), - PORT_DATA_IO_PU_PD(272), - PORT_DATA_IO_PU_PD(273), - PORT_DATA_IO_PU_PD(274), - PORT_DATA_IO_PU_PD(275), - PORT_DATA_IO_PU_PD(276), - PORT_DATA_IO_PU_PD(277), - PORT_DATA_IO_PU_PD(278), - PORT_DATA_IO_PU_PD(279), - PORT_DATA_IO_PU_PD(280), - PORT_DATA_O(281), - PORT_DATA_O(282), - PORT_DATA_I_PU(288), - PORT_DATA_IO_PU_PD(289), - PORT_DATA_IO_PU_PD(290), - PORT_DATA_IO_PU_PD(291), - PORT_DATA_IO_PU_PD(292), - PORT_DATA_IO_PU_PD(293), - PORT_DATA_IO_PU_PD(294), - PORT_DATA_IO_PU_PD(295), - PORT_DATA_IO_PU_PD(296), - PORT_DATA_IO_PU_PD(297), - PORT_DATA_IO_PU_PD(298), - - PORT_DATA_IO_PU_PD(299), - PORT_DATA_IO_PU_PD(300), - PORT_DATA_IO_PU_PD(301), - PORT_DATA_IO_PU_PD(302), - PORT_DATA_IO_PU_PD(303), - PORT_DATA_IO_PU_PD(304), - PORT_DATA_IO_PU_PD(305), - PORT_DATA_O(306), - PORT_DATA_O(307), - PORT_DATA_I_PU(308), - PORT_DATA_O(309), + PINMUX_DATA_ALL(), /* Table 25-1 (Function 0-7) */ PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), @@ -1358,28 +1039,19 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU, - MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), - PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, - MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), - PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, - MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), - PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, - MSEL4CR_MSEL15_0), \ + PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), - PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, - MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0), PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), @@ -1485,743 +1157,1990 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), +}; - /* Functions with pull-ups */ - PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), - PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), - PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), - PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), - PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), - PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), - PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), - PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), - - PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), - PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), - PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), - PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), - PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), - PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), - PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU), - PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), - PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), - PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), - PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), - PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), - PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), - PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), - PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), - PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), - PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), - - PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, - MSEL4CR_MSEL15_1), - - PINMUX_DATA(MMCD0_0_PU_MARK, - PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_1_PU_MARK, - PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_2_PU_MARK, - PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_3_PU_MARK, - PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_4_PU_MARK, - PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_5_PU_MARK, - PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_6_PU_MARK, - PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_7_PU_MARK, - PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0), - - PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), - PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), - PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), - PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), - PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - GPIO_PORT_ALL(), - - /* Table 25-1 (Functions 0-7) */ - GPIO_FN(VBUS_0), - GPIO_FN(GPI0), - GPIO_FN(GPI1), - GPIO_FN(GPI2), - GPIO_FN(GPI3), - GPIO_FN(GPI4), - GPIO_FN(GPI5), - GPIO_FN(GPI6), - GPIO_FN(GPI7), - GPIO_FN(SCIFA7_RXD), - GPIO_FN(SCIFA7_CTS_), - GPIO_FN(GPO7), \ - GPIO_FN(MFG0_OUT2), - GPIO_FN(GPO6), \ - GPIO_FN(MFG1_OUT2), - GPIO_FN(GPO5), \ - GPIO_FN(SCIFA0_SCK), \ - GPIO_FN(FSICOSLDT3), \ - GPIO_FN(PORT16_VIO_CKOR), - GPIO_FN(SCIFA0_TXD), - GPIO_FN(SCIFA7_TXD), - GPIO_FN(SCIFA7_RTS_), \ - GPIO_FN(PORT19_VIO_CKO2), - GPIO_FN(GPO0), - GPIO_FN(GPO1), - GPIO_FN(GPO2), \ - GPIO_FN(STATUS0), - GPIO_FN(GPO3), \ - GPIO_FN(STATUS1), - GPIO_FN(GPO4), \ - GPIO_FN(STATUS2), - GPIO_FN(VINT), - GPIO_FN(TCKON), - GPIO_FN(XDVFS1), \ - GPIO_FN(PORT27_I2C_SCL2), \ - GPIO_FN(PORT27_I2C_SCL3), \ - GPIO_FN(MFG0_OUT1), \ - GPIO_FN(PORT27_IROUT), - GPIO_FN(XDVFS2), \ - GPIO_FN(PORT28_I2C_SDA2), \ - GPIO_FN(PORT28_I2C_SDA3), \ - GPIO_FN(PORT28_TPU1TO1), - GPIO_FN(SIM_RST), \ - GPIO_FN(PORT29_TPU1TO1), - GPIO_FN(SIM_CLK), \ - GPIO_FN(PORT30_VIO_CKOR), - GPIO_FN(SIM_D), \ - GPIO_FN(PORT31_IROUT), - GPIO_FN(SCIFA4_TXD), - GPIO_FN(SCIFA4_RXD), \ - GPIO_FN(XWUP), - GPIO_FN(SCIFA4_RTS_), - GPIO_FN(SCIFA4_CTS_), - GPIO_FN(FSIBOBT), \ - GPIO_FN(FSIBIBT), - GPIO_FN(FSIBOLR), \ - GPIO_FN(FSIBILR), - GPIO_FN(FSIBOSLD), - GPIO_FN(FSIBISLD), - GPIO_FN(VACK), - GPIO_FN(XTAL1L), - GPIO_FN(SCIFA0_RTS_), \ - GPIO_FN(FSICOSLDT2), - GPIO_FN(SCIFA0_RXD), - GPIO_FN(SCIFA0_CTS_), \ - GPIO_FN(FSICOSLDT1), - GPIO_FN(FSICOBT), \ - GPIO_FN(FSICIBT), \ - GPIO_FN(FSIDOBT), \ - GPIO_FN(FSIDIBT), - GPIO_FN(FSICOLR), \ - GPIO_FN(FSICILR), \ - GPIO_FN(FSIDOLR), \ - GPIO_FN(FSIDILR), - GPIO_FN(FSICOSLD), \ - GPIO_FN(PORT47_FSICSPDIF), - GPIO_FN(FSICISLD), \ - GPIO_FN(FSIDISLD), - GPIO_FN(FSIACK), \ - GPIO_FN(PORT49_IRDA_OUT), \ - GPIO_FN(PORT49_IROUT), \ - GPIO_FN(FSIAOMC), - GPIO_FN(FSIAOLR), \ - GPIO_FN(BBIF2_TSYNC2), \ - GPIO_FN(TPU2TO2), \ - GPIO_FN(FSIAILR), - - GPIO_FN(FSIAOBT), \ - GPIO_FN(BBIF2_TSCK2), \ - GPIO_FN(TPU2TO3), \ - GPIO_FN(FSIAIBT), - GPIO_FN(FSIAOSLD), \ - GPIO_FN(BBIF2_TXD2), - GPIO_FN(FSIASPDIF), \ - GPIO_FN(PORT53_IRDA_IN), \ - GPIO_FN(TPU3TO3), \ - GPIO_FN(FSIBSPDIF), \ - GPIO_FN(PORT53_FSICSPDIF), - GPIO_FN(FSIBCK), \ - GPIO_FN(PORT54_IRDA_FIRSEL), \ - GPIO_FN(TPU3TO2), \ - GPIO_FN(FSIBOMC), \ - GPIO_FN(FSICCK), \ - GPIO_FN(FSICOMC), - GPIO_FN(FSIAISLD), \ - GPIO_FN(TPU0TO0), - GPIO_FN(A0), \ - GPIO_FN(BS_), - GPIO_FN(A12), \ - GPIO_FN(PORT58_KEYOUT7), \ - GPIO_FN(TPU4TO2), - GPIO_FN(A13), \ - GPIO_FN(PORT59_KEYOUT6), \ - GPIO_FN(TPU0TO1), - GPIO_FN(A14), \ - GPIO_FN(KEYOUT5), - GPIO_FN(A15), \ - GPIO_FN(KEYOUT4), - GPIO_FN(A16), \ - GPIO_FN(KEYOUT3), \ - GPIO_FN(MSIOF0_SS1), - GPIO_FN(A17), \ - GPIO_FN(KEYOUT2), \ - GPIO_FN(MSIOF0_TSYNC), - GPIO_FN(A18), \ - GPIO_FN(KEYOUT1), \ - GPIO_FN(MSIOF0_TSCK), - GPIO_FN(A19), \ - GPIO_FN(KEYOUT0), \ - GPIO_FN(MSIOF0_TXD), - GPIO_FN(A20), \ - GPIO_FN(KEYIN0), \ - GPIO_FN(MSIOF0_RSCK), - GPIO_FN(A21), \ - GPIO_FN(KEYIN1), \ - GPIO_FN(MSIOF0_RSYNC), - GPIO_FN(A22), \ - GPIO_FN(KEYIN2), \ - GPIO_FN(MSIOF0_MCK0), - GPIO_FN(A23), \ - GPIO_FN(KEYIN3), \ - GPIO_FN(MSIOF0_MCK1), - GPIO_FN(A24), \ - GPIO_FN(KEYIN4), \ - GPIO_FN(MSIOF0_RXD), - GPIO_FN(A25), \ - GPIO_FN(KEYIN5), \ - GPIO_FN(MSIOF0_SS2), - GPIO_FN(A26), \ - GPIO_FN(KEYIN6), - GPIO_FN(KEYIN7), - GPIO_FN(D0_NAF0), - GPIO_FN(D1_NAF1), - GPIO_FN(D2_NAF2), - GPIO_FN(D3_NAF3), - GPIO_FN(D4_NAF4), - GPIO_FN(D5_NAF5), - GPIO_FN(D6_NAF6), - GPIO_FN(D7_NAF7), - GPIO_FN(D8_NAF8), - GPIO_FN(D9_NAF9), - GPIO_FN(D10_NAF10), - GPIO_FN(D11_NAF11), - GPIO_FN(D12_NAF12), - GPIO_FN(D13_NAF13), - GPIO_FN(D14_NAF14), - GPIO_FN(D15_NAF15), - GPIO_FN(CS4_), - GPIO_FN(CS5A_), \ - GPIO_FN(PORT91_RDWR), - GPIO_FN(CS5B_), \ - GPIO_FN(FCE1_), - GPIO_FN(CS6B_), \ - GPIO_FN(DACK0), - GPIO_FN(FCE0_), \ - GPIO_FN(CS6A_), - GPIO_FN(WAIT_), \ - GPIO_FN(DREQ0), - GPIO_FN(RD__FSC), - GPIO_FN(WE0__FWE), \ - GPIO_FN(RDWR_FWE), - GPIO_FN(WE1_), - GPIO_FN(FRB), - GPIO_FN(CKO), - GPIO_FN(NBRSTOUT_), - GPIO_FN(NBRST_), - GPIO_FN(BBIF2_TXD), - GPIO_FN(BBIF2_RXD), - GPIO_FN(BBIF2_SYNC), - GPIO_FN(BBIF2_SCK), - GPIO_FN(SCIFA3_CTS_), \ - GPIO_FN(MFG3_IN2), - GPIO_FN(SCIFA3_RXD), \ - GPIO_FN(MFG3_IN1), - GPIO_FN(BBIF1_SS2), \ - GPIO_FN(SCIFA3_RTS_), \ - GPIO_FN(MFG3_OUT1), - GPIO_FN(SCIFA3_TXD), - GPIO_FN(HSI_RX_DATA), \ - GPIO_FN(BBIF1_RXD), - GPIO_FN(HSI_TX_WAKE), \ - GPIO_FN(BBIF1_TSCK), - GPIO_FN(HSI_TX_DATA), \ - GPIO_FN(BBIF1_TSYNC), - GPIO_FN(HSI_TX_READY), \ - GPIO_FN(BBIF1_TXD), - GPIO_FN(HSI_RX_READY), \ - GPIO_FN(BBIF1_RSCK), \ - GPIO_FN(PORT115_I2C_SCL2), \ - GPIO_FN(PORT115_I2C_SCL3), - GPIO_FN(HSI_RX_WAKE), \ - GPIO_FN(BBIF1_RSYNC), \ - GPIO_FN(PORT116_I2C_SDA2), \ - GPIO_FN(PORT116_I2C_SDA3), - GPIO_FN(HSI_RX_FLAG), \ - GPIO_FN(BBIF1_SS1), \ - GPIO_FN(BBIF1_FLOW), - GPIO_FN(HSI_TX_FLAG), - GPIO_FN(VIO_VD), \ - GPIO_FN(PORT128_LCD2VSYN), \ - GPIO_FN(VIO2_VD), \ - GPIO_FN(LCD2D0), - - GPIO_FN(VIO_HD), \ - GPIO_FN(PORT129_LCD2HSYN), \ - GPIO_FN(PORT129_LCD2CS_), \ - GPIO_FN(VIO2_HD), \ - GPIO_FN(LCD2D1), - GPIO_FN(VIO_D0), \ - GPIO_FN(PORT130_MSIOF2_RXD), \ - GPIO_FN(LCD2D10), - GPIO_FN(VIO_D1), \ - GPIO_FN(PORT131_KEYOUT6), \ - GPIO_FN(PORT131_MSIOF2_SS1), \ - GPIO_FN(PORT131_KEYOUT11), \ - GPIO_FN(LCD2D11), - GPIO_FN(VIO_D2), \ - GPIO_FN(PORT132_KEYOUT7), \ - GPIO_FN(PORT132_MSIOF2_SS2), \ - GPIO_FN(PORT132_KEYOUT10), \ - GPIO_FN(LCD2D12), - GPIO_FN(VIO_D3), \ - GPIO_FN(MSIOF2_TSYNC), \ - GPIO_FN(LCD2D13), - GPIO_FN(VIO_D4), \ - GPIO_FN(MSIOF2_TXD), \ - GPIO_FN(LCD2D14), - GPIO_FN(VIO_D5), \ - GPIO_FN(MSIOF2_TSCK), \ - GPIO_FN(LCD2D15), - GPIO_FN(VIO_D6), \ - GPIO_FN(PORT136_KEYOUT8), \ - GPIO_FN(LCD2D16), - GPIO_FN(VIO_D7), \ - GPIO_FN(PORT137_KEYOUT9), \ - GPIO_FN(LCD2D17), - GPIO_FN(VIO_D8), \ - GPIO_FN(PORT138_KEYOUT8), \ - GPIO_FN(VIO2_D0), \ - GPIO_FN(LCD2D6), - GPIO_FN(VIO_D9), \ - GPIO_FN(PORT139_KEYOUT9), \ - GPIO_FN(VIO2_D1), \ - GPIO_FN(LCD2D7), - GPIO_FN(VIO_D10), \ - GPIO_FN(TPU0TO2), \ - GPIO_FN(VIO2_D2), \ - GPIO_FN(LCD2D8), - GPIO_FN(VIO_D11), \ - GPIO_FN(TPU0TO3), \ - GPIO_FN(VIO2_D3), \ - GPIO_FN(LCD2D9), - GPIO_FN(VIO_D12), \ - GPIO_FN(PORT142_KEYOUT10), \ - GPIO_FN(VIO2_D4), \ - GPIO_FN(LCD2D2), - GPIO_FN(VIO_D13), \ - GPIO_FN(PORT143_KEYOUT11), \ - GPIO_FN(PORT143_KEYOUT6), \ - GPIO_FN(VIO2_D5), \ - GPIO_FN(LCD2D3), - GPIO_FN(VIO_D14), \ - GPIO_FN(PORT144_KEYOUT7), \ - GPIO_FN(VIO2_D6), \ - GPIO_FN(LCD2D4), - GPIO_FN(VIO_D15), \ - GPIO_FN(TPU1TO3), \ - GPIO_FN(PORT145_LCD2DISP), \ - GPIO_FN(PORT145_LCD2RS), \ - GPIO_FN(VIO2_D7), \ - GPIO_FN(LCD2D5), - GPIO_FN(VIO_CLK), \ - GPIO_FN(LCD2DCK), \ - GPIO_FN(PORT146_LCD2WR_), \ - GPIO_FN(VIO2_CLK), \ - GPIO_FN(LCD2D18), - GPIO_FN(VIO_FIELD), \ - GPIO_FN(LCD2RD_), \ - GPIO_FN(VIO2_FIELD), \ - GPIO_FN(LCD2D19), - GPIO_FN(VIO_CKO), - GPIO_FN(A27), \ - GPIO_FN(PORT149_RDWR), \ - GPIO_FN(MFG0_IN1), \ - GPIO_FN(PORT149_KEYOUT9), - GPIO_FN(MFG0_IN2), - GPIO_FN(TS_SPSYNC3), \ - GPIO_FN(MSIOF2_RSCK), - GPIO_FN(TS_SDAT3), \ - GPIO_FN(MSIOF2_RSYNC), - GPIO_FN(TPU1TO2), \ - GPIO_FN(TS_SDEN3), \ - GPIO_FN(PORT153_MSIOF2_SS1), - GPIO_FN(SCIFA2_TXD1), \ - GPIO_FN(MSIOF2_MCK0), - GPIO_FN(SCIFA2_RXD1), \ - GPIO_FN(MSIOF2_MCK1), - GPIO_FN(SCIFA2_RTS1_), \ - GPIO_FN(PORT156_MSIOF2_SS2), - GPIO_FN(SCIFA2_CTS1_), \ - GPIO_FN(PORT157_MSIOF2_RXD), - GPIO_FN(DINT_), \ - GPIO_FN(SCIFA2_SCK1), \ - GPIO_FN(TS_SCK3), - GPIO_FN(PORT159_SCIFB_SCK), \ - GPIO_FN(PORT159_SCIFA5_SCK), \ - GPIO_FN(NMI), - GPIO_FN(PORT160_SCIFB_TXD), \ - GPIO_FN(PORT160_SCIFA5_TXD), - GPIO_FN(PORT161_SCIFB_CTS_), \ - GPIO_FN(PORT161_SCIFA5_CTS_), - GPIO_FN(PORT162_SCIFB_RXD), \ - GPIO_FN(PORT162_SCIFA5_RXD), - GPIO_FN(PORT163_SCIFB_RTS_), \ - GPIO_FN(PORT163_SCIFA5_RTS_), \ - GPIO_FN(TPU3TO0), - GPIO_FN(LCDD0), - GPIO_FN(LCDD1), \ - GPIO_FN(PORT193_SCIFA5_CTS_), \ - GPIO_FN(BBIF2_TSYNC1), - GPIO_FN(LCDD2), \ - GPIO_FN(PORT194_SCIFA5_RTS_), \ - GPIO_FN(BBIF2_TSCK1), - GPIO_FN(LCDD3), \ - GPIO_FN(PORT195_SCIFA5_RXD), \ - GPIO_FN(BBIF2_TXD1), - GPIO_FN(LCDD4), \ - GPIO_FN(PORT196_SCIFA5_TXD), - GPIO_FN(LCDD5), \ - GPIO_FN(PORT197_SCIFA5_SCK), \ - GPIO_FN(MFG2_OUT2), \ - GPIO_FN(TPU2TO1), - GPIO_FN(LCDD6), - GPIO_FN(LCDD7), \ - GPIO_FN(TPU4TO1), \ - GPIO_FN(MFG4_OUT2), - GPIO_FN(LCDD8), \ - GPIO_FN(D16), - GPIO_FN(LCDD9), \ - GPIO_FN(D17), - GPIO_FN(LCDD10), \ - GPIO_FN(D18), - GPIO_FN(LCDD11), \ - GPIO_FN(D19), - GPIO_FN(LCDD12), \ - GPIO_FN(D20), - GPIO_FN(LCDD13), \ - GPIO_FN(D21), - GPIO_FN(LCDD14), \ - GPIO_FN(D22), - GPIO_FN(LCDD15), \ - GPIO_FN(PORT207_MSIOF0L_SS1), \ - GPIO_FN(D23), - GPIO_FN(LCDD16), \ - GPIO_FN(PORT208_MSIOF0L_SS2), \ - GPIO_FN(D24), - GPIO_FN(LCDD17), \ - GPIO_FN(D25), - GPIO_FN(LCDD18), \ - GPIO_FN(DREQ2), \ - GPIO_FN(PORT210_MSIOF0L_SS1), \ - GPIO_FN(D26), - GPIO_FN(LCDD19), \ - GPIO_FN(PORT211_MSIOF0L_SS2), \ - GPIO_FN(D27), - GPIO_FN(LCDD20), \ - GPIO_FN(TS_SPSYNC1), \ - GPIO_FN(MSIOF0L_MCK0), \ - GPIO_FN(D28), - GPIO_FN(LCDD21), \ - GPIO_FN(TS_SDAT1), \ - GPIO_FN(MSIOF0L_MCK1), \ - GPIO_FN(D29), - GPIO_FN(LCDD22), \ - GPIO_FN(TS_SDEN1), \ - GPIO_FN(MSIOF0L_RSCK), \ - GPIO_FN(D30), - GPIO_FN(LCDD23), \ - GPIO_FN(TS_SCK1), \ - GPIO_FN(MSIOF0L_RSYNC), \ - GPIO_FN(D31), - GPIO_FN(LCDDCK), \ - GPIO_FN(LCDWR_), - GPIO_FN(LCDRD_), \ - GPIO_FN(DACK2), \ - GPIO_FN(PORT217_LCD2RS), \ - GPIO_FN(MSIOF0L_TSYNC), \ - GPIO_FN(VIO2_FIELD3), \ - GPIO_FN(PORT217_LCD2DISP), - GPIO_FN(LCDHSYN), \ - GPIO_FN(LCDCS_), \ - GPIO_FN(LCDCS2_), \ - GPIO_FN(DACK3), \ - GPIO_FN(PORT218_VIO_CKOR), - GPIO_FN(LCDDISP), \ - GPIO_FN(LCDRS), \ - GPIO_FN(PORT219_LCD2WR_), \ - GPIO_FN(DREQ3), \ - GPIO_FN(MSIOF0L_TSCK), \ - GPIO_FN(VIO2_CLK3), \ - GPIO_FN(LCD2DCK_2), - GPIO_FN(LCDVSYN), \ - GPIO_FN(LCDVSYN2), - GPIO_FN(LCDLCLK), \ - GPIO_FN(DREQ1), \ - GPIO_FN(PORT221_LCD2CS_), \ - GPIO_FN(PWEN), \ - GPIO_FN(MSIOF0L_RXD), \ - GPIO_FN(VIO2_HD3), \ - GPIO_FN(PORT221_LCD2HSYN), - GPIO_FN(LCDDON), \ - GPIO_FN(LCDDON2), \ - GPIO_FN(DACK1), \ - GPIO_FN(OVCN), \ - GPIO_FN(MSIOF0L_TXD), \ - GPIO_FN(VIO2_VD3), \ - GPIO_FN(PORT222_LCD2VSYN), - - GPIO_FN(SCIFA1_TXD), \ - GPIO_FN(OVCN2), - GPIO_FN(EXTLP), \ - GPIO_FN(SCIFA1_SCK), \ - GPIO_FN(PORT226_VIO_CKO2), - GPIO_FN(SCIFA1_RTS_), \ - GPIO_FN(IDIN), - GPIO_FN(SCIFA1_RXD), - GPIO_FN(SCIFA1_CTS_), \ - GPIO_FN(MFG1_IN1), - GPIO_FN(MSIOF1_TXD), \ - GPIO_FN(SCIFA2_TXD2), - GPIO_FN(MSIOF1_TSYNC), \ - GPIO_FN(SCIFA2_CTS2_), - GPIO_FN(MSIOF1_TSCK), \ - GPIO_FN(SCIFA2_SCK2), - GPIO_FN(MSIOF1_RXD), \ - GPIO_FN(SCIFA2_RXD2), - GPIO_FN(MSIOF1_RSCK), \ - GPIO_FN(SCIFA2_RTS2_), \ - GPIO_FN(VIO2_CLK2), \ - GPIO_FN(LCD2D20), - GPIO_FN(MSIOF1_RSYNC), \ - GPIO_FN(MFG1_IN2), \ - GPIO_FN(VIO2_VD2), \ - GPIO_FN(LCD2D21), - GPIO_FN(MSIOF1_MCK0), \ - GPIO_FN(PORT236_I2C_SDA2), - GPIO_FN(MSIOF1_MCK1), \ - GPIO_FN(PORT237_I2C_SCL2), - GPIO_FN(MSIOF1_SS1), \ - GPIO_FN(VIO2_FIELD2), \ - GPIO_FN(LCD2D22), - GPIO_FN(MSIOF1_SS2), \ - GPIO_FN(VIO2_HD2), \ - GPIO_FN(LCD2D23), - GPIO_FN(SCIFA6_TXD), - GPIO_FN(PORT241_IRDA_OUT), \ - GPIO_FN(PORT241_IROUT), \ - GPIO_FN(MFG4_OUT1), \ - GPIO_FN(TPU4TO0), - GPIO_FN(PORT242_IRDA_IN), \ - GPIO_FN(MFG4_IN2), - GPIO_FN(PORT243_IRDA_FIRSEL), \ - GPIO_FN(PORT243_VIO_CKO2), - GPIO_FN(PORT244_SCIFA5_CTS_), \ - GPIO_FN(MFG2_IN1), \ - GPIO_FN(PORT244_SCIFB_CTS_), \ - GPIO_FN(MSIOF2R_RXD), - GPIO_FN(PORT245_SCIFA5_RTS_), \ - GPIO_FN(MFG2_IN2), \ - GPIO_FN(PORT245_SCIFB_RTS_), \ - GPIO_FN(MSIOF2R_TXD), - GPIO_FN(PORT246_SCIFA5_RXD), \ - GPIO_FN(MFG1_OUT1), \ - GPIO_FN(PORT246_SCIFB_RXD), \ - GPIO_FN(TPU1TO0), - GPIO_FN(PORT247_SCIFA5_TXD), \ - GPIO_FN(MFG3_OUT2), \ - GPIO_FN(PORT247_SCIFB_TXD), \ - GPIO_FN(TPU3TO1), - GPIO_FN(PORT248_SCIFA5_SCK), \ - GPIO_FN(MFG2_OUT1), \ - GPIO_FN(PORT248_SCIFB_SCK), \ - GPIO_FN(TPU2TO0), \ - GPIO_FN(PORT248_I2C_SCL3), \ - GPIO_FN(MSIOF2R_TSCK), - GPIO_FN(PORT249_IROUT), \ - GPIO_FN(MFG4_IN1), \ - GPIO_FN(PORT249_I2C_SDA3), \ - GPIO_FN(MSIOF2R_TSYNC), - GPIO_FN(SDHICLK0), - GPIO_FN(SDHICD0), - GPIO_FN(SDHID0_0), - GPIO_FN(SDHID0_1), - GPIO_FN(SDHID0_2), - GPIO_FN(SDHID0_3), - GPIO_FN(SDHICMD0), - GPIO_FN(SDHIWP0), - GPIO_FN(SDHICLK1), - GPIO_FN(SDHID1_0), \ - GPIO_FN(TS_SPSYNC2), - GPIO_FN(SDHID1_1), \ - GPIO_FN(TS_SDAT2), - GPIO_FN(SDHID1_2), \ - GPIO_FN(TS_SDEN2), - GPIO_FN(SDHID1_3), \ - GPIO_FN(TS_SCK2), - GPIO_FN(SDHICMD1), - GPIO_FN(SDHICLK2), - GPIO_FN(SDHID2_0), \ - GPIO_FN(TS_SPSYNC4), - GPIO_FN(SDHID2_1), \ - GPIO_FN(TS_SDAT4), - GPIO_FN(SDHID2_2), \ - GPIO_FN(TS_SDEN4), - GPIO_FN(SDHID2_3), \ - GPIO_FN(TS_SCK4), - GPIO_FN(SDHICMD2), - GPIO_FN(MMCCLK0), - GPIO_FN(MMCD0_0), - GPIO_FN(MMCD0_1), - GPIO_FN(MMCD0_2), - GPIO_FN(MMCD0_3), - GPIO_FN(MMCD0_4), \ - GPIO_FN(TS_SPSYNC5), - GPIO_FN(MMCD0_5), \ - GPIO_FN(TS_SDAT5), - GPIO_FN(MMCD0_6), \ - GPIO_FN(TS_SDEN5), - GPIO_FN(MMCD0_7), \ - GPIO_FN(TS_SCK5), - GPIO_FN(MMCCMD0), - GPIO_FN(RESETOUTS_), \ - GPIO_FN(EXTAL2OUT), - GPIO_FN(MCP_WAIT__MCP_FRB), - GPIO_FN(MCP_CKO), \ - GPIO_FN(MMCCLK1), - GPIO_FN(MCP_D15_MCP_NAF15), - GPIO_FN(MCP_D14_MCP_NAF14), - GPIO_FN(MCP_D13_MCP_NAF13), - GPIO_FN(MCP_D12_MCP_NAF12), - GPIO_FN(MCP_D11_MCP_NAF11), - GPIO_FN(MCP_D10_MCP_NAF10), - GPIO_FN(MCP_D9_MCP_NAF9), - GPIO_FN(MCP_D8_MCP_NAF8), \ - GPIO_FN(MMCCMD1), - GPIO_FN(MCP_D7_MCP_NAF7), \ - GPIO_FN(MMCD1_7), - - GPIO_FN(MCP_D6_MCP_NAF6), \ - GPIO_FN(MMCD1_6), - GPIO_FN(MCP_D5_MCP_NAF5), \ - GPIO_FN(MMCD1_5), - GPIO_FN(MCP_D4_MCP_NAF4), \ - GPIO_FN(MMCD1_4), - GPIO_FN(MCP_D3_MCP_NAF3), \ - GPIO_FN(MMCD1_3), - GPIO_FN(MCP_D2_MCP_NAF2), \ - GPIO_FN(MMCD1_2), - GPIO_FN(MCP_D1_MCP_NAF1), \ - GPIO_FN(MMCD1_1), - GPIO_FN(MCP_D0_MCP_NAF0), \ - GPIO_FN(MMCD1_0), - GPIO_FN(MCP_NBRSTOUT_), - GPIO_FN(MCP_WE0__MCP_FWE), \ - GPIO_FN(MCP_RDWR_MCP_FWE), +#define __I (SH_PFC_PIN_CFG_INPUT) +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) +#define __PU (SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) +#define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) +#define SH73A0_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD) +#define SH73A0_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO) +#define SH73A0_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD) +#define SH73A0_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU) +#define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) +#define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) + +/* Pin numbers for pins without a corresponding GPIO port number are computed + * from the row and column numbers with a 1000 offset to avoid collisions with + * GPIO port numbers. + */ +#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) - /* MSEL2 special cases */ - GPIO_FN(TSIF2_TS_XX1), - GPIO_FN(TSIF2_TS_XX2), - GPIO_FN(TSIF2_TS_XX3), - GPIO_FN(TSIF2_TS_XX4), - GPIO_FN(TSIF2_TS_XX5), - GPIO_FN(TSIF1_TS_XX1), - GPIO_FN(TSIF1_TS_XX2), - GPIO_FN(TSIF1_TS_XX3), - GPIO_FN(TSIF1_TS_XX4), - GPIO_FN(TSIF1_TS_XX5), - GPIO_FN(TSIF0_TS_XX1), - GPIO_FN(TSIF0_TS_XX2), - GPIO_FN(TSIF0_TS_XX3), - GPIO_FN(TSIF0_TS_XX4), - GPIO_FN(TSIF0_TS_XX5), - GPIO_FN(MST1_TS_XX1), - GPIO_FN(MST1_TS_XX2), - GPIO_FN(MST1_TS_XX3), - GPIO_FN(MST1_TS_XX4), - GPIO_FN(MST1_TS_XX5), - GPIO_FN(MST0_TS_XX1), - GPIO_FN(MST0_TS_XX2), - GPIO_FN(MST0_TS_XX3), - GPIO_FN(MST0_TS_XX4), - GPIO_FN(MST0_TS_XX5), +static const struct sh_pfc_pin pinmux_pins[] = { + /* Table 25-1 (I/O and Pull U/D) */ + SH73A0_PIN_I_PD(0), + SH73A0_PIN_I_PU(1), + SH73A0_PIN_I_PU(2), + SH73A0_PIN_I_PU(3), + SH73A0_PIN_I_PU(4), + SH73A0_PIN_I_PU(5), + SH73A0_PIN_I_PU(6), + SH73A0_PIN_I_PU(7), + SH73A0_PIN_I_PU(8), + SH73A0_PIN_I_PD(9), + SH73A0_PIN_I_PD(10), + SH73A0_PIN_I_PU_PD(11), + SH73A0_PIN_IO_PU_PD(12), + SH73A0_PIN_IO_PU_PD(13), + SH73A0_PIN_IO_PU_PD(14), + SH73A0_PIN_IO_PU_PD(15), + SH73A0_PIN_IO_PD(16), + SH73A0_PIN_IO_PD(17), + SH73A0_PIN_IO_PU(18), + SH73A0_PIN_IO_PU(19), + SH73A0_PIN_O(20), + SH73A0_PIN_O(21), + SH73A0_PIN_O(22), + SH73A0_PIN_O(23), + SH73A0_PIN_O(24), + SH73A0_PIN_I_PD(25), + SH73A0_PIN_I_PD(26), + SH73A0_PIN_IO_PU(27), + SH73A0_PIN_IO_PU(28), + SH73A0_PIN_IO_PD(29), + SH73A0_PIN_IO_PD(30), + SH73A0_PIN_IO_PU(31), + SH73A0_PIN_IO_PD(32), + SH73A0_PIN_I_PU_PD(33), + SH73A0_PIN_IO_PD(34), + SH73A0_PIN_I_PU_PD(35), + SH73A0_PIN_IO_PD(36), + SH73A0_PIN_IO(37), + SH73A0_PIN_O(38), + SH73A0_PIN_I_PU(39), + SH73A0_PIN_I_PU_PD(40), + SH73A0_PIN_O(41), + SH73A0_PIN_IO_PD(42), + SH73A0_PIN_IO_PU_PD(43), + SH73A0_PIN_IO_PU_PD(44), + SH73A0_PIN_IO_PD(45), + SH73A0_PIN_IO_PD(46), + SH73A0_PIN_IO_PD(47), + SH73A0_PIN_I_PD(48), + SH73A0_PIN_IO_PU_PD(49), + SH73A0_PIN_IO_PD(50), + SH73A0_PIN_IO_PD(51), + SH73A0_PIN_O(52), + SH73A0_PIN_IO_PU_PD(53), + SH73A0_PIN_IO_PU_PD(54), + SH73A0_PIN_IO_PD(55), + SH73A0_PIN_I_PU_PD(56), + SH73A0_PIN_IO(57), + SH73A0_PIN_IO(58), + SH73A0_PIN_IO(59), + SH73A0_PIN_IO(60), + SH73A0_PIN_IO(61), + SH73A0_PIN_IO_PD(62), + SH73A0_PIN_IO_PD(63), + SH73A0_PIN_IO_PU_PD(64), + SH73A0_PIN_IO_PD(65), + SH73A0_PIN_IO_PU_PD(66), + SH73A0_PIN_IO_PU_PD(67), + SH73A0_PIN_IO_PU_PD(68), + SH73A0_PIN_IO_PU_PD(69), + SH73A0_PIN_IO_PU_PD(70), + SH73A0_PIN_IO_PU_PD(71), + SH73A0_PIN_IO_PU_PD(72), + SH73A0_PIN_I_PU_PD(73), + SH73A0_PIN_IO_PU(74), + SH73A0_PIN_IO_PU(75), + SH73A0_PIN_IO_PU(76), + SH73A0_PIN_IO_PU(77), + SH73A0_PIN_IO_PU(78), + SH73A0_PIN_IO_PU(79), + SH73A0_PIN_IO_PU(80), + SH73A0_PIN_IO_PU(81), + SH73A0_PIN_IO_PU(82), + SH73A0_PIN_IO_PU(83), + SH73A0_PIN_IO_PU(84), + SH73A0_PIN_IO_PU(85), + SH73A0_PIN_IO_PU(86), + SH73A0_PIN_IO_PU(87), + SH73A0_PIN_IO_PU(88), + SH73A0_PIN_IO_PU(89), + SH73A0_PIN_O(90), + SH73A0_PIN_IO_PU(91), + SH73A0_PIN_O(92), + SH73A0_PIN_IO_PU(93), + SH73A0_PIN_O(94), + SH73A0_PIN_I_PU_PD(95), + SH73A0_PIN_IO(96), + SH73A0_PIN_IO(97), + SH73A0_PIN_IO(98), + SH73A0_PIN_I_PU(99), + SH73A0_PIN_O(100), + SH73A0_PIN_O(101), + SH73A0_PIN_I_PU(102), + SH73A0_PIN_IO_PD(103), + SH73A0_PIN_I_PU_PD(104), + SH73A0_PIN_I_PD(105), + SH73A0_PIN_I_PD(106), + SH73A0_PIN_I_PU_PD(107), + SH73A0_PIN_I_PU_PD(108), + SH73A0_PIN_IO_PD(109), + SH73A0_PIN_IO_PD(110), + SH73A0_PIN_IO_PU_PD(111), + SH73A0_PIN_IO_PU_PD(112), + SH73A0_PIN_IO_PU_PD(113), + SH73A0_PIN_IO_PD(114), + SH73A0_PIN_IO_PU(115), + SH73A0_PIN_IO_PU(116), + SH73A0_PIN_IO_PU_PD(117), + SH73A0_PIN_IO_PU_PD(118), + SH73A0_PIN_IO_PD(128), + SH73A0_PIN_IO_PD(129), + SH73A0_PIN_IO_PU_PD(130), + SH73A0_PIN_IO_PD(131), + SH73A0_PIN_IO_PD(132), + SH73A0_PIN_IO_PD(133), + SH73A0_PIN_IO_PU_PD(134), + SH73A0_PIN_IO_PU_PD(135), + SH73A0_PIN_IO_PU_PD(136), + SH73A0_PIN_IO_PU_PD(137), + SH73A0_PIN_IO_PD(138), + SH73A0_PIN_IO_PD(139), + SH73A0_PIN_IO_PD(140), + SH73A0_PIN_IO_PD(141), + SH73A0_PIN_IO_PD(142), + SH73A0_PIN_IO_PD(143), + SH73A0_PIN_IO_PU_PD(144), + SH73A0_PIN_IO_PD(145), + SH73A0_PIN_IO_PU_PD(146), + SH73A0_PIN_IO_PU_PD(147), + SH73A0_PIN_IO_PU_PD(148), + SH73A0_PIN_IO_PU_PD(149), + SH73A0_PIN_I_PU_PD(150), + SH73A0_PIN_IO_PU_PD(151), + SH73A0_PIN_IO_PU_PD(152), + SH73A0_PIN_IO_PD(153), + SH73A0_PIN_IO_PD(154), + SH73A0_PIN_I_PU_PD(155), + SH73A0_PIN_IO_PU_PD(156), + SH73A0_PIN_I_PD(157), + SH73A0_PIN_IO_PD(158), + SH73A0_PIN_IO_PU_PD(159), + SH73A0_PIN_IO_PU_PD(160), + SH73A0_PIN_I_PU_PD(161), + SH73A0_PIN_I_PU_PD(162), + SH73A0_PIN_IO_PU_PD(163), + SH73A0_PIN_I_PU_PD(164), + SH73A0_PIN_IO_PD(192), + SH73A0_PIN_IO_PU_PD(193), + SH73A0_PIN_IO_PD(194), + SH73A0_PIN_IO_PU_PD(195), + SH73A0_PIN_IO_PD(196), + SH73A0_PIN_IO_PD(197), + SH73A0_PIN_IO_PD(198), + SH73A0_PIN_IO_PD(199), + SH73A0_PIN_IO_PU_PD(200), + SH73A0_PIN_IO_PU_PD(201), + SH73A0_PIN_IO_PU_PD(202), + SH73A0_PIN_IO_PU_PD(203), + SH73A0_PIN_IO_PU_PD(204), + SH73A0_PIN_IO_PU_PD(205), + SH73A0_PIN_IO_PU_PD(206), + SH73A0_PIN_IO_PD(207), + SH73A0_PIN_IO_PD(208), + SH73A0_PIN_IO_PD(209), + SH73A0_PIN_IO_PD(210), + SH73A0_PIN_IO_PD(211), + SH73A0_PIN_IO_PD(212), + SH73A0_PIN_IO_PD(213), + SH73A0_PIN_IO_PU_PD(214), + SH73A0_PIN_IO_PU_PD(215), + SH73A0_PIN_IO_PD(216), + SH73A0_PIN_IO_PD(217), + SH73A0_PIN_O(218), + SH73A0_PIN_IO_PD(219), + SH73A0_PIN_IO_PD(220), + SH73A0_PIN_IO_PU_PD(221), + SH73A0_PIN_IO_PU_PD(222), + SH73A0_PIN_I_PU_PD(223), + SH73A0_PIN_I_PU_PD(224), + SH73A0_PIN_IO_PU_PD(225), + SH73A0_PIN_O(226), + SH73A0_PIN_IO_PU_PD(227), + SH73A0_PIN_I_PU_PD(228), + SH73A0_PIN_I_PD(229), + SH73A0_PIN_IO(230), + SH73A0_PIN_IO_PU_PD(231), + SH73A0_PIN_IO_PU_PD(232), + SH73A0_PIN_I_PU_PD(233), + SH73A0_PIN_IO_PU_PD(234), + SH73A0_PIN_IO_PU_PD(235), + SH73A0_PIN_IO_PU_PD(236), + SH73A0_PIN_IO_PD(237), + SH73A0_PIN_IO_PU_PD(238), + SH73A0_PIN_IO_PU_PD(239), + SH73A0_PIN_IO_PU_PD(240), + SH73A0_PIN_O(241), + SH73A0_PIN_I_PD(242), + SH73A0_PIN_IO_PU_PD(243), + SH73A0_PIN_IO_PU_PD(244), + SH73A0_PIN_IO_PU_PD(245), + SH73A0_PIN_IO_PU_PD(246), + SH73A0_PIN_IO_PU_PD(247), + SH73A0_PIN_IO_PU_PD(248), + SH73A0_PIN_IO_PU_PD(249), + SH73A0_PIN_IO_PU_PD(250), + SH73A0_PIN_IO_PU_PD(251), + SH73A0_PIN_IO_PU_PD(252), + SH73A0_PIN_IO_PU_PD(253), + SH73A0_PIN_IO_PU_PD(254), + SH73A0_PIN_IO_PU_PD(255), + SH73A0_PIN_IO_PU_PD(256), + SH73A0_PIN_IO_PU_PD(257), + SH73A0_PIN_IO_PU_PD(258), + SH73A0_PIN_IO_PU_PD(259), + SH73A0_PIN_IO_PU_PD(260), + SH73A0_PIN_IO_PU_PD(261), + SH73A0_PIN_IO_PU_PD(262), + SH73A0_PIN_IO_PU_PD(263), + SH73A0_PIN_IO_PU_PD(264), + SH73A0_PIN_IO_PU_PD(265), + SH73A0_PIN_IO_PU_PD(266), + SH73A0_PIN_IO_PU_PD(267), + SH73A0_PIN_IO_PU_PD(268), + SH73A0_PIN_IO_PU_PD(269), + SH73A0_PIN_IO_PU_PD(270), + SH73A0_PIN_IO_PU_PD(271), + SH73A0_PIN_IO_PU_PD(272), + SH73A0_PIN_IO_PU_PD(273), + SH73A0_PIN_IO_PU_PD(274), + SH73A0_PIN_IO_PU_PD(275), + SH73A0_PIN_IO_PU_PD(276), + SH73A0_PIN_IO_PU_PD(277), + SH73A0_PIN_IO_PU_PD(278), + SH73A0_PIN_IO_PU_PD(279), + SH73A0_PIN_IO_PU_PD(280), + SH73A0_PIN_O(281), + SH73A0_PIN_O(282), + SH73A0_PIN_I_PU(288), + SH73A0_PIN_IO_PU_PD(289), + SH73A0_PIN_IO_PU_PD(290), + SH73A0_PIN_IO_PU_PD(291), + SH73A0_PIN_IO_PU_PD(292), + SH73A0_PIN_IO_PU_PD(293), + SH73A0_PIN_IO_PU_PD(294), + SH73A0_PIN_IO_PU_PD(295), + SH73A0_PIN_IO_PU_PD(296), + SH73A0_PIN_IO_PU_PD(297), + SH73A0_PIN_IO_PU_PD(298), + SH73A0_PIN_IO_PU_PD(299), + SH73A0_PIN_IO_PU_PD(300), + SH73A0_PIN_IO_PU_PD(301), + SH73A0_PIN_IO_PU_PD(302), + SH73A0_PIN_IO_PU_PD(303), + SH73A0_PIN_IO_PU_PD(304), + SH73A0_PIN_IO_PU_PD(305), + SH73A0_PIN_O(306), + SH73A0_PIN_O(307), + SH73A0_PIN_I_PU(308), + SH73A0_PIN_O(309), + + /* Pins not associated with a GPIO port */ + SH_PFC_PIN_NAMED(6, 26, F26), +}; - /* MSEL3 special cases */ - GPIO_FN(SDHI0_VCCQ_MC0_ON), - GPIO_FN(SDHI0_VCCQ_MC0_OFF), - GPIO_FN(DEBUG_MON_VIO), - GPIO_FN(DEBUG_MON_LCDD), - GPIO_FN(LCDC_LCDC0), - GPIO_FN(LCDC_LCDC1), +/* - BSC -------------------------------------------------------------------- */ +static const unsigned int bsc_data_0_7_pins[] = { + /* D[0:7] */ + 74, 75, 76, 77, 78, 79, 80, 81, +}; +static const unsigned int bsc_data_0_7_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, +}; +static const unsigned int bsc_data_8_15_pins[] = { + /* D[8:15] */ + 82, 83, 84, 85, 86, 87, 88, 89, +}; +static const unsigned int bsc_data_8_15_mux[] = { + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int bsc_cs4_pins[] = { + /* CS */ + 90, +}; +static const unsigned int bsc_cs4_mux[] = { + CS4__MARK, +}; +static const unsigned int bsc_cs5_a_pins[] = { + /* CS */ + 91, +}; +static const unsigned int bsc_cs5_a_mux[] = { + CS5A__MARK, +}; +static const unsigned int bsc_cs5_b_pins[] = { + /* CS */ + 92, +}; +static const unsigned int bsc_cs5_b_mux[] = { + CS5B__MARK, +}; +static const unsigned int bsc_cs6_a_pins[] = { + /* CS */ + 94, +}; +static const unsigned int bsc_cs6_a_mux[] = { + CS6A__MARK, +}; +static const unsigned int bsc_cs6_b_pins[] = { + /* CS */ + 93, +}; +static const unsigned int bsc_cs6_b_mux[] = { + CS6B__MARK, +}; +static const unsigned int bsc_rd_pins[] = { + /* RD */ + 96, +}; +static const unsigned int bsc_rd_mux[] = { + RD__FSC_MARK, +}; +static const unsigned int bsc_rdwr_0_pins[] = { + /* RDWR */ + 91, +}; +static const unsigned int bsc_rdwr_0_mux[] = { + PORT91_RDWR_MARK, +}; +static const unsigned int bsc_rdwr_1_pins[] = { + /* RDWR */ + 97, +}; +static const unsigned int bsc_rdwr_1_mux[] = { + RDWR_FWE_MARK, +}; +static const unsigned int bsc_rdwr_2_pins[] = { + /* RDWR */ + 149, +}; +static const unsigned int bsc_rdwr_2_mux[] = { + PORT149_RDWR_MARK, +}; +static const unsigned int bsc_we0_pins[] = { + /* WE0 */ + 97, +}; +static const unsigned int bsc_we0_mux[] = { + WE0__FWE_MARK, +}; +static const unsigned int bsc_we1_pins[] = { + /* WE1 */ + 98, +}; +static const unsigned int bsc_we1_mux[] = { + WE1__MARK, +}; +/* - FSIA ------------------------------------------------------------------- */ +static const unsigned int fsia_mclk_in_pins[] = { + /* CK */ + 49, +}; +static const unsigned int fsia_mclk_in_mux[] = { + FSIACK_MARK, +}; +static const unsigned int fsia_mclk_out_pins[] = { + /* OMC */ + 49, +}; +static const unsigned int fsia_mclk_out_mux[] = { + FSIAOMC_MARK, +}; +static const unsigned int fsia_sclk_in_pins[] = { + /* ILR, IBT */ + 50, 51, +}; +static const unsigned int fsia_sclk_in_mux[] = { + FSIAILR_MARK, FSIAIBT_MARK, +}; +static const unsigned int fsia_sclk_out_pins[] = { + /* OLR, OBT */ + 50, 51, +}; +static const unsigned int fsia_sclk_out_mux[] = { + FSIAOLR_MARK, FSIAOBT_MARK, +}; +static const unsigned int fsia_data_in_pins[] = { + /* ISLD */ + 55, +}; +static const unsigned int fsia_data_in_mux[] = { + FSIAISLD_MARK, +}; +static const unsigned int fsia_data_out_pins[] = { + /* OSLD */ + 52, +}; +static const unsigned int fsia_data_out_mux[] = { + FSIAOSLD_MARK, +}; +static const unsigned int fsia_spdif_pins[] = { + /* SPDIF */ + 53, +}; +static const unsigned int fsia_spdif_mux[] = { + FSIASPDIF_MARK, +}; +/* - FSIB ------------------------------------------------------------------- */ +static const unsigned int fsib_mclk_in_pins[] = { + /* CK */ + 54, +}; +static const unsigned int fsib_mclk_in_mux[] = { + FSIBCK_MARK, +}; +static const unsigned int fsib_mclk_out_pins[] = { + /* OMC */ + 54, +}; +static const unsigned int fsib_mclk_out_mux[] = { + FSIBOMC_MARK, +}; +static const unsigned int fsib_sclk_in_pins[] = { + /* ILR, IBT */ + 37, 36, +}; +static const unsigned int fsib_sclk_in_mux[] = { + FSIBILR_MARK, FSIBIBT_MARK, +}; +static const unsigned int fsib_sclk_out_pins[] = { + /* OLR, OBT */ + 37, 36, +}; +static const unsigned int fsib_sclk_out_mux[] = { + FSIBOLR_MARK, FSIBOBT_MARK, +}; +static const unsigned int fsib_data_in_pins[] = { + /* ISLD */ + 39, +}; +static const unsigned int fsib_data_in_mux[] = { + FSIBISLD_MARK, +}; +static const unsigned int fsib_data_out_pins[] = { + /* OSLD */ + 38, +}; +static const unsigned int fsib_data_out_mux[] = { + FSIBOSLD_MARK, +}; +static const unsigned int fsib_spdif_pins[] = { + /* SPDIF */ + 53, +}; +static const unsigned int fsib_spdif_mux[] = { + FSIBSPDIF_MARK, +}; +/* - FSIC ------------------------------------------------------------------- */ +static const unsigned int fsic_mclk_in_pins[] = { + /* CK */ + 54, +}; +static const unsigned int fsic_mclk_in_mux[] = { + FSICCK_MARK, +}; +static const unsigned int fsic_mclk_out_pins[] = { + /* OMC */ + 54, +}; +static const unsigned int fsic_mclk_out_mux[] = { + FSICOMC_MARK, +}; +static const unsigned int fsic_sclk_in_pins[] = { + /* ILR, IBT */ + 46, 45, +}; +static const unsigned int fsic_sclk_in_mux[] = { + FSICILR_MARK, FSICIBT_MARK, +}; +static const unsigned int fsic_sclk_out_pins[] = { + /* OLR, OBT */ + 46, 45, +}; +static const unsigned int fsic_sclk_out_mux[] = { + FSICOLR_MARK, FSICOBT_MARK, +}; +static const unsigned int fsic_data_in_pins[] = { + /* ISLD */ + 48, +}; +static const unsigned int fsic_data_in_mux[] = { + FSICISLD_MARK, +}; +static const unsigned int fsic_data_out_pins[] = { + /* OSLD, OSLDT1, OSLDT2, OSLDT3 */ + 47, 44, 42, 16, +}; +static const unsigned int fsic_data_out_mux[] = { + FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK, +}; +static const unsigned int fsic_spdif_0_pins[] = { + /* SPDIF */ + 53, +}; +static const unsigned int fsic_spdif_0_mux[] = { + PORT53_FSICSPDIF_MARK, +}; +static const unsigned int fsic_spdif_1_pins[] = { + /* SPDIF */ + 47, +}; +static const unsigned int fsic_spdif_1_mux[] = { + PORT47_FSICSPDIF_MARK, +}; +/* - FSID ------------------------------------------------------------------- */ +static const unsigned int fsid_sclk_in_pins[] = { + /* ILR, IBT */ + 46, 45, +}; +static const unsigned int fsid_sclk_in_mux[] = { + FSIDILR_MARK, FSIDIBT_MARK, +}; +static const unsigned int fsid_sclk_out_pins[] = { + /* OLR, OBT */ + 46, 45, +}; +static const unsigned int fsid_sclk_out_mux[] = { + FSIDOLR_MARK, FSIDOBT_MARK, +}; +static const unsigned int fsid_data_in_pins[] = { + /* ISLD */ + 48, +}; +static const unsigned int fsid_data_in_mux[] = { + FSIDISLD_MARK, +}; +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_0_pins[] = { + /* SCL, SDA */ + 237, 236, +}; +static const unsigned int i2c2_0_mux[] = { + PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK, +}; +static const unsigned int i2c2_1_pins[] = { + /* SCL, SDA */ + 27, 28, +}; +static const unsigned int i2c2_1_mux[] = { + PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK, +}; +static const unsigned int i2c2_2_pins[] = { + /* SCL, SDA */ + 115, 116, +}; +static const unsigned int i2c2_2_mux[] = { + PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK, +}; +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_0_pins[] = { + /* SCL, SDA */ + 248, 249, +}; +static const unsigned int i2c3_0_mux[] = { + PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK, +}; +static const unsigned int i2c3_1_pins[] = { + /* SCL, SDA */ + 27, 28, +}; +static const unsigned int i2c3_1_mux[] = { + PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK, +}; +static const unsigned int i2c3_2_pins[] = { + /* SCL, SDA */ + 115, 116, +}; +static const unsigned int i2c3_2_mux[] = { + PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK, +}; +/* - IrDA ------------------------------------------------------------------- */ +static const unsigned int irda_0_pins[] = { + /* OUT, IN, FIRSEL */ + 241, 242, 243, +}; +static const unsigned int irda_0_mux[] = { + PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK, +}; +static const unsigned int irda_1_pins[] = { + /* OUT, IN, FIRSEL */ + 49, 53, 54, +}; +static const unsigned int irda_1_mux[] = { + PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK, +}; +/* - KEYSC ------------------------------------------------------------------ */ +static const unsigned int keysc_in5_pins[] = { + /* KEYIN[0:4] */ + 66, 67, 68, 69, 70, +}; +static const unsigned int keysc_in5_mux[] = { + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, + KEYIN4_MARK, +}; +static const unsigned int keysc_in6_pins[] = { + /* KEYIN[0:5] */ + 66, 67, 68, 69, 70, 71, +}; +static const unsigned int keysc_in6_mux[] = { + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, + KEYIN4_MARK, KEYIN5_MARK, +}; +static const unsigned int keysc_in7_pins[] = { + /* KEYIN[0:6] */ + 66, 67, 68, 69, 70, 71, 72, +}; +static const unsigned int keysc_in7_mux[] = { + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, + KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, +}; +static const unsigned int keysc_in8_pins[] = { + /* KEYIN[0:7] */ + 66, 67, 68, 69, 70, 71, 72, 73, +}; +static const unsigned int keysc_in8_mux[] = { + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, + KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, +}; +static const unsigned int keysc_out04_pins[] = { + /* KEYOUT[0:4] */ + 65, 64, 63, 62, 61, +}; +static const unsigned int keysc_out04_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK, +}; +static const unsigned int keysc_out5_pins[] = { + /* KEYOUT5 */ + 60, +}; +static const unsigned int keysc_out5_mux[] = { + KEYOUT5_MARK, +}; +static const unsigned int keysc_out6_0_pins[] = { + /* KEYOUT6 */ + 59, +}; +static const unsigned int keysc_out6_0_mux[] = { + PORT59_KEYOUT6_MARK, +}; +static const unsigned int keysc_out6_1_pins[] = { + /* KEYOUT6 */ + 131, +}; +static const unsigned int keysc_out6_1_mux[] = { + PORT131_KEYOUT6_MARK, +}; +static const unsigned int keysc_out6_2_pins[] = { + /* KEYOUT6 */ + 143, +}; +static const unsigned int keysc_out6_2_mux[] = { + PORT143_KEYOUT6_MARK, +}; +static const unsigned int keysc_out7_0_pins[] = { + /* KEYOUT7 */ + 58, +}; +static const unsigned int keysc_out7_0_mux[] = { + PORT58_KEYOUT7_MARK, +}; +static const unsigned int keysc_out7_1_pins[] = { + /* KEYOUT7 */ + 132, +}; +static const unsigned int keysc_out7_1_mux[] = { + PORT132_KEYOUT7_MARK, +}; +static const unsigned int keysc_out7_2_pins[] = { + /* KEYOUT7 */ + 144, +}; +static const unsigned int keysc_out7_2_mux[] = { + PORT144_KEYOUT7_MARK, +}; +static const unsigned int keysc_out8_0_pins[] = { + /* KEYOUT8 */ + PIN_NUMBER(6, 26), +}; +static const unsigned int keysc_out8_0_mux[] = { + KEYOUT8_MARK, +}; +static const unsigned int keysc_out8_1_pins[] = { + /* KEYOUT8 */ + 136, +}; +static const unsigned int keysc_out8_1_mux[] = { + PORT136_KEYOUT8_MARK, +}; +static const unsigned int keysc_out8_2_pins[] = { + /* KEYOUT8 */ + 138, +}; +static const unsigned int keysc_out8_2_mux[] = { + PORT138_KEYOUT8_MARK, +}; +static const unsigned int keysc_out9_0_pins[] = { + /* KEYOUT9 */ + 137, +}; +static const unsigned int keysc_out9_0_mux[] = { + PORT137_KEYOUT9_MARK, +}; +static const unsigned int keysc_out9_1_pins[] = { + /* KEYOUT9 */ + 139, +}; +static const unsigned int keysc_out9_1_mux[] = { + PORT139_KEYOUT9_MARK, +}; +static const unsigned int keysc_out9_2_pins[] = { + /* KEYOUT9 */ + 149, +}; +static const unsigned int keysc_out9_2_mux[] = { + PORT149_KEYOUT9_MARK, +}; +static const unsigned int keysc_out10_0_pins[] = { + /* KEYOUT10 */ + 132, +}; +static const unsigned int keysc_out10_0_mux[] = { + PORT132_KEYOUT10_MARK, +}; +static const unsigned int keysc_out10_1_pins[] = { + /* KEYOUT10 */ + 142, +}; +static const unsigned int keysc_out10_1_mux[] = { + PORT142_KEYOUT10_MARK, +}; +static const unsigned int keysc_out11_0_pins[] = { + /* KEYOUT11 */ + 131, +}; +static const unsigned int keysc_out11_0_mux[] = { + PORT131_KEYOUT11_MARK, +}; +static const unsigned int keysc_out11_1_pins[] = { + /* KEYOUT11 */ + 143, +}; +static const unsigned int keysc_out11_1_mux[] = { + PORT143_KEYOUT11_MARK, +}; +/* - LCD -------------------------------------------------------------------- */ +static const unsigned int lcd_data8_pins[] = { + /* D[0:7] */ + 192, 193, 194, 195, 196, 197, 198, 199, +}; +static const unsigned int lcd_data8_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, +}; +static const unsigned int lcd_data9_pins[] = { + /* D[0:8] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, +}; +static const unsigned int lcd_data9_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, +}; +static const unsigned int lcd_data12_pins[] = { + /* D[0:11] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, +}; +static const unsigned int lcd_data12_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, +}; +static const unsigned int lcd_data16_pins[] = { + /* D[0:15] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, +}; +static const unsigned int lcd_data16_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, +}; +static const unsigned int lcd_data18_pins[] = { + /* D[0:17] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, +}; +static const unsigned int lcd_data18_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, +}; +static const unsigned int lcd_data24_pins[] = { + /* D[0:23] */ + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212, 213, 214, 215 +}; +static const unsigned int lcd_data24_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, + LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, +}; +static const unsigned int lcd_display_pins[] = { + /* DON */ + 222, +}; +static const unsigned int lcd_display_mux[] = { + LCDDON_MARK, +}; +static const unsigned int lcd_lclk_pins[] = { + /* LCLK */ + 221, +}; +static const unsigned int lcd_lclk_mux[] = { + LCDLCLK_MARK, +}; +static const unsigned int lcd_sync_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 220, 218, 216, 219, +}; +static const unsigned int lcd_sync_mux[] = { + LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK, +}; +static const unsigned int lcd_sys_pins[] = { + /* CS, WR, RD, RS */ + 218, 216, 217, 219, +}; +static const unsigned int lcd_sys_mux[] = { + LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK, +}; +/* - LCD2 ------------------------------------------------------------------- */ +static const unsigned int lcd2_data8_pins[] = { + /* D[0:7] */ + 128, 129, 142, 143, 144, 145, 138, 139, +}; +static const unsigned int lcd2_data8_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, +}; +static const unsigned int lcd2_data9_pins[] = { + /* D[0:8] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, +}; +static const unsigned int lcd2_data9_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, +}; +static const unsigned int lcd2_data12_pins[] = { + /* D[0:12] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, 141, 130, 131, +}; +static const unsigned int lcd2_data12_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, +}; +static const unsigned int lcd2_data16_pins[] = { + /* D[0:15] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, 141, 130, 131, 132, 133, 134, 135, +}; +static const unsigned int lcd2_data16_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, + LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, +}; +static const unsigned int lcd2_data18_pins[] = { + /* D[0:17] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, 141, 130, 131, 132, 133, 134, 135, + 136, 137, +}; +static const unsigned int lcd2_data18_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, + LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, + LCD2D16_MARK, LCD2D17_MARK, +}; +static const unsigned int lcd2_data24_pins[] = { + /* D[0:23] */ + 128, 129, 142, 143, 144, 145, 138, 139, + 140, 141, 130, 131, 132, 133, 134, 135, + 136, 137, 146, 147, 234, 235, 238, 239 +}; +static const unsigned int lcd2_data24_mux[] = { + LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, + LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, + LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, + LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, + LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK, + LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK, +}; +static const unsigned int lcd2_sync_0_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 128, 129, 146, 145, +}; +static const unsigned int lcd2_sync_0_mux[] = { + PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK, + LCD2DCK_MARK, PORT145_LCD2DISP_MARK, +}; +static const unsigned int lcd2_sync_1_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 222, 221, 219, 217, +}; +static const unsigned int lcd2_sync_1_mux[] = { + PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK, + LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK, +}; +static const unsigned int lcd2_sys_0_pins[] = { + /* CS, WR, RD, RS */ + 129, 146, 147, 145, +}; +static const unsigned int lcd2_sys_0_mux[] = { + PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK, + LCD2RD__MARK, PORT145_LCD2RS_MARK, +}; +static const unsigned int lcd2_sys_1_pins[] = { + /* CS, WR, RD, RS */ + 221, 219, 147, 217, +}; +static const unsigned int lcd2_sys_1_mux[] = { + PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK, + LCD2RD__MARK, PORT217_LCD2RS_MARK, +}; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc0_data1_0_pins[] = { + /* D[0] */ + 271, +}; +static const unsigned int mmc0_data1_0_mux[] = { + MMCD0_0_MARK, +}; +static const unsigned int mmc0_data4_0_pins[] = { + /* D[0:3] */ + 271, 272, 273, 274, +}; +static const unsigned int mmc0_data4_0_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, +}; +static const unsigned int mmc0_data8_0_pins[] = { + /* D[0:7] */ + 271, 272, 273, 274, 275, 276, 277, 278, +}; +static const unsigned int mmc0_data8_0_mux[] = { + MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, + MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, +}; +static const unsigned int mmc0_ctrl_0_pins[] = { + /* CMD, CLK */ + 279, 270, +}; +static const unsigned int mmc0_ctrl_0_mux[] = { + MMCCMD0_MARK, MMCCLK0_MARK, +}; - /* MSEL4 special cases */ - GPIO_FN(IRQ9_MEM_INT), - GPIO_FN(IRQ9_MCP_INT), - GPIO_FN(A11), - GPIO_FN(KEYOUT8), - GPIO_FN(TPU4TO3), - GPIO_FN(RESETA_N_PU_ON), - GPIO_FN(RESETA_N_PU_OFF), - GPIO_FN(EDBGREQ_PD), - GPIO_FN(EDBGREQ_PU), - - /* Functions with pull-ups */ - GPIO_FN(KEYIN0_PU), - GPIO_FN(KEYIN1_PU), - GPIO_FN(KEYIN2_PU), - GPIO_FN(KEYIN3_PU), - GPIO_FN(KEYIN4_PU), - GPIO_FN(KEYIN5_PU), - GPIO_FN(KEYIN6_PU), - GPIO_FN(KEYIN7_PU), - GPIO_FN(SDHICD0_PU), - GPIO_FN(SDHID0_0_PU), - GPIO_FN(SDHID0_1_PU), - GPIO_FN(SDHID0_2_PU), - GPIO_FN(SDHID0_3_PU), - GPIO_FN(SDHICMD0_PU), - GPIO_FN(SDHIWP0_PU), - GPIO_FN(SDHID1_0_PU), - GPIO_FN(SDHID1_1_PU), - GPIO_FN(SDHID1_2_PU), - GPIO_FN(SDHID1_3_PU), - GPIO_FN(SDHICMD1_PU), - GPIO_FN(SDHID2_0_PU), - GPIO_FN(SDHID2_1_PU), - GPIO_FN(SDHID2_2_PU), - GPIO_FN(SDHID2_3_PU), - GPIO_FN(SDHICMD2_PU), - GPIO_FN(MMCCMD0_PU), - GPIO_FN(MMCCMD1_PU), - GPIO_FN(MMCD0_0_PU), - GPIO_FN(MMCD0_1_PU), - GPIO_FN(MMCD0_2_PU), - GPIO_FN(MMCD0_3_PU), - GPIO_FN(MMCD0_4_PU), - GPIO_FN(MMCD0_5_PU), - GPIO_FN(MMCD0_6_PU), - GPIO_FN(MMCD0_7_PU), - GPIO_FN(FSIACK_PU), - GPIO_FN(FSIAILR_PU), - GPIO_FN(FSIAIBT_PU), - GPIO_FN(FSIAISLD_PU), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const unsigned int mmc0_data1_1_pins[] = { + /* D[0] */ + 305, +}; +static const unsigned int mmc0_data1_1_mux[] = { + MMCD1_0_MARK, +}; +static const unsigned int mmc0_data4_1_pins[] = { + /* D[0:3] */ + 305, 304, 303, 302, +}; +static const unsigned int mmc0_data4_1_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, +}; +static const unsigned int mmc0_data8_1_pins[] = { + /* D[0:7] */ + 305, 304, 303, 302, 301, 300, 299, 298, +}; +static const unsigned int mmc0_data8_1_mux[] = { + MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, + MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, +}; +static const unsigned int mmc0_ctrl_1_pins[] = { + /* CMD, CLK */ + 297, 289, +}; +static const unsigned int mmc0_ctrl_1_mux[] = { + MMCCMD1_MARK, MMCCLK1_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + 43, 17, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + 16, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + 42, 44, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS__MARK, SCIFA0_CTS__MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + 228, 225, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + 226, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + 227, 229, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS__MARK, SCIFA1_CTS__MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_0_pins[] = { + /* RXD, TXD */ + 155, 154, +}; +static const unsigned int scifa2_data_0_mux[] = { + SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK, +}; +static const unsigned int scifa2_clk_0_pins[] = { + /* SCK */ + 158, +}; +static const unsigned int scifa2_clk_0_mux[] = { + SCIFA2_SCK1_MARK, +}; +static const unsigned int scifa2_ctrl_0_pins[] = { + /* RTS, CTS */ + 156, 157, +}; +static const unsigned int scifa2_ctrl_0_mux[] = { + SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK, +}; +static const unsigned int scifa2_data_1_pins[] = { + /* RXD, TXD */ + 233, 230, +}; +static const unsigned int scifa2_data_1_mux[] = { + SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK, +}; +static const unsigned int scifa2_clk_1_pins[] = { + /* SCK */ + 232, +}; +static const unsigned int scifa2_clk_1_mux[] = { + SCIFA2_SCK2_MARK, +}; +static const unsigned int scifa2_ctrl_1_pins[] = { + /* RTS, CTS */ + 234, 231, +}; +static const unsigned int scifa2_ctrl_1_mux[] = { + SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_pins[] = { + /* RXD, TXD */ + 108, 110, +}; +static const unsigned int scifa3_data_mux[] = { + SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, +}; +static const unsigned int scifa3_ctrl_pins[] = { + /* RTS, CTS */ + 109, 107, +}; +static const unsigned int scifa3_ctrl_mux[] = { + SCIFA3_RTS__MARK, SCIFA3_CTS__MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_pins[] = { + /* RXD, TXD */ + 33, 32, +}; +static const unsigned int scifa4_data_mux[] = { + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, +}; +static const unsigned int scifa4_ctrl_pins[] = { + /* RTS, CTS */ + 34, 35, +}; +static const unsigned int scifa4_ctrl_mux[] = { + SCIFA4_RTS__MARK, SCIFA4_CTS__MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_0_pins[] = { + /* RXD, TXD */ + 246, 247, +}; +static const unsigned int scifa5_data_0_mux[] = { + PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK, +}; +static const unsigned int scifa5_clk_0_pins[] = { + /* SCK */ + 248, +}; +static const unsigned int scifa5_clk_0_mux[] = { + PORT248_SCIFA5_SCK_MARK, +}; +static const unsigned int scifa5_ctrl_0_pins[] = { + /* RTS, CTS */ + 245, 244, +}; +static const unsigned int scifa5_ctrl_0_mux[] = { + PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK, +}; +static const unsigned int scifa5_data_1_pins[] = { + /* RXD, TXD */ + 195, 196, +}; +static const unsigned int scifa5_data_1_mux[] = { + PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK, +}; +static const unsigned int scifa5_clk_1_pins[] = { + /* SCK */ + 197, +}; +static const unsigned int scifa5_clk_1_mux[] = { + PORT197_SCIFA5_SCK_MARK, +}; +static const unsigned int scifa5_ctrl_1_pins[] = { + /* RTS, CTS */ + 194, 193, +}; +static const unsigned int scifa5_ctrl_1_mux[] = { + PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK, +}; +static const unsigned int scifa5_data_2_pins[] = { + /* RXD, TXD */ + 162, 160, +}; +static const unsigned int scifa5_data_2_mux[] = { + PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK, +}; +static const unsigned int scifa5_clk_2_pins[] = { + /* SCK */ + 159, +}; +static const unsigned int scifa5_clk_2_mux[] = { + PORT159_SCIFA5_SCK_MARK, +}; +static const unsigned int scifa5_ctrl_2_pins[] = { + /* RTS, CTS */ + 163, 161, +}; +static const unsigned int scifa5_ctrl_2_mux[] = { + PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK, +}; +/* - SCIFA6 ----------------------------------------------------------------- */ +static const unsigned int scifa6_pins[] = { + /* TXD */ + 240, +}; +static const unsigned int scifa6_mux[] = { + SCIFA6_TXD_MARK, +}; +/* - SCIFA7 ----------------------------------------------------------------- */ +static const unsigned int scifa7_data_pins[] = { + /* RXD, TXD */ + 12, 18, +}; +static const unsigned int scifa7_data_mux[] = { + SCIFA7_RXD_MARK, SCIFA7_TXD_MARK, +}; +static const unsigned int scifa7_ctrl_pins[] = { + /* RTS, CTS */ + 19, 13, +}; +static const unsigned int scifa7_ctrl_mux[] = { + SCIFA7_RTS__MARK, SCIFA7_CTS__MARK, +}; +/* - SCIFB ------------------------------------------------------------------ */ +static const unsigned int scifb_data_0_pins[] = { + /* RXD, TXD */ + 162, 160, +}; +static const unsigned int scifb_data_0_mux[] = { + PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK, +}; +static const unsigned int scifb_clk_0_pins[] = { + /* SCK */ + 159, +}; +static const unsigned int scifb_clk_0_mux[] = { + PORT159_SCIFB_SCK_MARK, +}; +static const unsigned int scifb_ctrl_0_pins[] = { + /* RTS, CTS */ + 163, 161, +}; +static const unsigned int scifb_ctrl_0_mux[] = { + PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK, +}; +static const unsigned int scifb_data_1_pins[] = { + /* RXD, TXD */ + 246, 247, +}; +static const unsigned int scifb_data_1_mux[] = { + PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK, +}; +static const unsigned int scifb_clk_1_pins[] = { + /* SCK */ + 248, +}; +static const unsigned int scifb_clk_1_mux[] = { + PORT248_SCIFB_SCK_MARK, +}; +static const unsigned int scifb_ctrl_1_pins[] = { + /* RTS, CTS */ + 245, 244, +}; +static const unsigned int scifb_ctrl_1_mux[] = { + PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK, +}; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + 252, +}; +static const unsigned int sdhi0_data1_mux[] = { + SDHID0_0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + 252, 253, 254, 255, +}; +static const unsigned int sdhi0_data4_mux[] = { + SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CMD, CLK */ + 256, 250, +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SDHICMD0_MARK, SDHICLK0_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + 251, +}; +static const unsigned int sdhi0_cd_mux[] = { + SDHICD0_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + 257, +}; +static const unsigned int sdhi0_wp_mux[] = { + SDHIWP0_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + 259, +}; +static const unsigned int sdhi1_data1_mux[] = { + SDHID1_0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + 259, 260, 261, 262, +}; +static const unsigned int sdhi1_data4_mux[] = { + SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CMD, CLK */ + 263, 258, +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SDHICMD1_MARK, SDHICLK1_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + 265, +}; +static const unsigned int sdhi2_data1_mux[] = { + SDHID2_0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + 265, 266, 267, 268, +}; +static const unsigned int sdhi2_data4_mux[] = { + SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CMD, CLK */ + 269, 264, +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SDHICMD2_MARK, SDHICLK2_MARK, +}; +/* - TPU0 ------------------------------------------------------------------- */ +static const unsigned int tpu0_to0_pins[] = { + /* TO */ + 55, +}; +static const unsigned int tpu0_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu0_to1_pins[] = { + /* TO */ + 59, +}; +static const unsigned int tpu0_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu0_to2_pins[] = { + /* TO */ + 140, +}; +static const unsigned int tpu0_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu0_to3_pins[] = { + /* TO */ + 141, +}; +static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, +}; +/* - TPU1 ------------------------------------------------------------------- */ +static const unsigned int tpu1_to0_pins[] = { + /* TO */ + 246, +}; +static const unsigned int tpu1_to0_mux[] = { + TPU1TO0_MARK, +}; +static const unsigned int tpu1_to1_0_pins[] = { + /* TO */ + 28, +}; +static const unsigned int tpu1_to1_0_mux[] = { + PORT28_TPU1TO1_MARK, +}; +static const unsigned int tpu1_to1_1_pins[] = { + /* TO */ + 29, +}; +static const unsigned int tpu1_to1_1_mux[] = { + PORT29_TPU1TO1_MARK, +}; +static const unsigned int tpu1_to2_pins[] = { + /* TO */ + 153, +}; +static const unsigned int tpu1_to2_mux[] = { + TPU1TO2_MARK, +}; +static const unsigned int tpu1_to3_pins[] = { + /* TO */ + 145, +}; +static const unsigned int tpu1_to3_mux[] = { + TPU1TO3_MARK, +}; +/* - TPU2 ------------------------------------------------------------------- */ +static const unsigned int tpu2_to0_pins[] = { + /* TO */ + 248, +}; +static const unsigned int tpu2_to0_mux[] = { + TPU2TO0_MARK, +}; +static const unsigned int tpu2_to1_pins[] = { + /* TO */ + 197, +}; +static const unsigned int tpu2_to1_mux[] = { + TPU2TO1_MARK, +}; +static const unsigned int tpu2_to2_pins[] = { + /* TO */ + 50, +}; +static const unsigned int tpu2_to2_mux[] = { + TPU2TO2_MARK, +}; +static const unsigned int tpu2_to3_pins[] = { + /* TO */ + 51, +}; +static const unsigned int tpu2_to3_mux[] = { + TPU2TO3_MARK, +}; +/* - TPU3 ------------------------------------------------------------------- */ +static const unsigned int tpu3_to0_pins[] = { + /* TO */ + 163, +}; +static const unsigned int tpu3_to0_mux[] = { + TPU3TO0_MARK, +}; +static const unsigned int tpu3_to1_pins[] = { + /* TO */ + 247, +}; +static const unsigned int tpu3_to1_mux[] = { + TPU3TO1_MARK, +}; +static const unsigned int tpu3_to2_pins[] = { + /* TO */ + 54, +}; +static const unsigned int tpu3_to2_mux[] = { + TPU3TO2_MARK, +}; +static const unsigned int tpu3_to3_pins[] = { + /* TO */ + 53, +}; +static const unsigned int tpu3_to3_mux[] = { + TPU3TO3_MARK, +}; +/* - TPU4 ------------------------------------------------------------------- */ +static const unsigned int tpu4_to0_pins[] = { + /* TO */ + 241, +}; +static const unsigned int tpu4_to0_mux[] = { + TPU4TO0_MARK, +}; +static const unsigned int tpu4_to1_pins[] = { + /* TO */ + 199, +}; +static const unsigned int tpu4_to1_mux[] = { + TPU4TO1_MARK, +}; +static const unsigned int tpu4_to2_pins[] = { + /* TO */ + 58, +}; +static const unsigned int tpu4_to2_mux[] = { + TPU4TO2_MARK, +}; +static const unsigned int tpu4_to3_pins[] = { + /* TO */ +}; +static const unsigned int tpu4_to3_mux[] = { + TPU4TO3_MARK, +}; +/* - USB -------------------------------------------------------------------- */ +static const unsigned int usb_vbus_pins[] = { + /* VBUS */ + 0, +}; +static const unsigned int usb_vbus_mux[] = { + VBUS_0_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data_0_7), + SH_PFC_PIN_GROUP(bsc_data_8_15), + SH_PFC_PIN_GROUP(bsc_cs4), + SH_PFC_PIN_GROUP(bsc_cs5_a), + SH_PFC_PIN_GROUP(bsc_cs5_b), + SH_PFC_PIN_GROUP(bsc_cs6_a), + SH_PFC_PIN_GROUP(bsc_cs6_b), + SH_PFC_PIN_GROUP(bsc_rd), + SH_PFC_PIN_GROUP(bsc_rdwr_0), + SH_PFC_PIN_GROUP(bsc_rdwr_1), + SH_PFC_PIN_GROUP(bsc_rdwr_2), + SH_PFC_PIN_GROUP(bsc_we0), + SH_PFC_PIN_GROUP(bsc_we1), + SH_PFC_PIN_GROUP(fsia_mclk_in), + SH_PFC_PIN_GROUP(fsia_mclk_out), + SH_PFC_PIN_GROUP(fsia_sclk_in), + SH_PFC_PIN_GROUP(fsia_sclk_out), + SH_PFC_PIN_GROUP(fsia_data_in), + SH_PFC_PIN_GROUP(fsia_data_out), + SH_PFC_PIN_GROUP(fsia_spdif), + SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(fsib_mclk_out), + SH_PFC_PIN_GROUP(fsib_sclk_in), + SH_PFC_PIN_GROUP(fsib_sclk_out), + SH_PFC_PIN_GROUP(fsib_data_in), + SH_PFC_PIN_GROUP(fsib_data_out), + SH_PFC_PIN_GROUP(fsib_spdif), + SH_PFC_PIN_GROUP(fsic_mclk_in), + SH_PFC_PIN_GROUP(fsic_mclk_out), + SH_PFC_PIN_GROUP(fsic_sclk_in), + SH_PFC_PIN_GROUP(fsic_sclk_out), + SH_PFC_PIN_GROUP(fsic_data_in), + SH_PFC_PIN_GROUP(fsic_data_out), + SH_PFC_PIN_GROUP(fsic_spdif_0), + SH_PFC_PIN_GROUP(fsic_spdif_1), + SH_PFC_PIN_GROUP(fsid_sclk_in), + SH_PFC_PIN_GROUP(fsid_sclk_out), + SH_PFC_PIN_GROUP(fsid_data_in), + SH_PFC_PIN_GROUP(i2c2_0), + SH_PFC_PIN_GROUP(i2c2_1), + SH_PFC_PIN_GROUP(i2c2_2), + SH_PFC_PIN_GROUP(i2c3_0), + SH_PFC_PIN_GROUP(i2c3_1), + SH_PFC_PIN_GROUP(i2c3_2), + SH_PFC_PIN_GROUP(irda_0), + SH_PFC_PIN_GROUP(irda_1), + SH_PFC_PIN_GROUP(keysc_in5), + SH_PFC_PIN_GROUP(keysc_in6), + SH_PFC_PIN_GROUP(keysc_in7), + SH_PFC_PIN_GROUP(keysc_in8), + SH_PFC_PIN_GROUP(keysc_out04), + SH_PFC_PIN_GROUP(keysc_out5), + SH_PFC_PIN_GROUP(keysc_out6_0), + SH_PFC_PIN_GROUP(keysc_out6_1), + SH_PFC_PIN_GROUP(keysc_out6_2), + SH_PFC_PIN_GROUP(keysc_out7_0), + SH_PFC_PIN_GROUP(keysc_out7_1), + SH_PFC_PIN_GROUP(keysc_out7_2), + SH_PFC_PIN_GROUP(keysc_out8_0), + SH_PFC_PIN_GROUP(keysc_out8_1), + SH_PFC_PIN_GROUP(keysc_out8_2), + SH_PFC_PIN_GROUP(keysc_out9_0), + SH_PFC_PIN_GROUP(keysc_out9_1), + SH_PFC_PIN_GROUP(keysc_out9_2), + SH_PFC_PIN_GROUP(keysc_out10_0), + SH_PFC_PIN_GROUP(keysc_out10_1), + SH_PFC_PIN_GROUP(keysc_out11_0), + SH_PFC_PIN_GROUP(keysc_out11_1), + SH_PFC_PIN_GROUP(lcd_data8), + SH_PFC_PIN_GROUP(lcd_data9), + SH_PFC_PIN_GROUP(lcd_data12), + SH_PFC_PIN_GROUP(lcd_data16), + SH_PFC_PIN_GROUP(lcd_data18), + SH_PFC_PIN_GROUP(lcd_data24), + SH_PFC_PIN_GROUP(lcd_display), + SH_PFC_PIN_GROUP(lcd_lclk), + SH_PFC_PIN_GROUP(lcd_sync), + SH_PFC_PIN_GROUP(lcd_sys), + SH_PFC_PIN_GROUP(lcd2_data8), + SH_PFC_PIN_GROUP(lcd2_data9), + SH_PFC_PIN_GROUP(lcd2_data12), + SH_PFC_PIN_GROUP(lcd2_data16), + SH_PFC_PIN_GROUP(lcd2_data18), + SH_PFC_PIN_GROUP(lcd2_data24), + SH_PFC_PIN_GROUP(lcd2_sync_0), + SH_PFC_PIN_GROUP(lcd2_sync_1), + SH_PFC_PIN_GROUP(lcd2_sys_0), + SH_PFC_PIN_GROUP(lcd2_sys_1), + SH_PFC_PIN_GROUP(mmc0_data1_0), + SH_PFC_PIN_GROUP(mmc0_data4_0), + SH_PFC_PIN_GROUP(mmc0_data8_0), + SH_PFC_PIN_GROUP(mmc0_ctrl_0), + SH_PFC_PIN_GROUP(mmc0_data1_1), + SH_PFC_PIN_GROUP(mmc0_data4_1), + SH_PFC_PIN_GROUP(mmc0_data8_1), + SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa2_data_0), + SH_PFC_PIN_GROUP(scifa2_clk_0), + SH_PFC_PIN_GROUP(scifa2_ctrl_0), + SH_PFC_PIN_GROUP(scifa2_data_1), + SH_PFC_PIN_GROUP(scifa2_clk_1), + SH_PFC_PIN_GROUP(scifa2_ctrl_1), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_ctrl), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa4_ctrl), + SH_PFC_PIN_GROUP(scifa5_data_0), + SH_PFC_PIN_GROUP(scifa5_clk_0), + SH_PFC_PIN_GROUP(scifa5_ctrl_0), + SH_PFC_PIN_GROUP(scifa5_data_1), + SH_PFC_PIN_GROUP(scifa5_clk_1), + SH_PFC_PIN_GROUP(scifa5_ctrl_1), + SH_PFC_PIN_GROUP(scifa5_data_2), + SH_PFC_PIN_GROUP(scifa5_clk_2), + SH_PFC_PIN_GROUP(scifa5_ctrl_2), + SH_PFC_PIN_GROUP(scifa6), + SH_PFC_PIN_GROUP(scifa7_data), + SH_PFC_PIN_GROUP(scifa7_ctrl), + SH_PFC_PIN_GROUP(scifb_data_0), + SH_PFC_PIN_GROUP(scifb_clk_0), + SH_PFC_PIN_GROUP(scifb_ctrl_0), + SH_PFC_PIN_GROUP(scifb_data_1), + SH_PFC_PIN_GROUP(scifb_clk_1), + SH_PFC_PIN_GROUP(scifb_ctrl_1), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), + SH_PFC_PIN_GROUP(tpu1_to0), + SH_PFC_PIN_GROUP(tpu1_to1_0), + SH_PFC_PIN_GROUP(tpu1_to1_1), + SH_PFC_PIN_GROUP(tpu1_to2), + SH_PFC_PIN_GROUP(tpu1_to3), + SH_PFC_PIN_GROUP(tpu2_to0), + SH_PFC_PIN_GROUP(tpu2_to1), + SH_PFC_PIN_GROUP(tpu2_to2), + SH_PFC_PIN_GROUP(tpu2_to3), + SH_PFC_PIN_GROUP(tpu3_to0), + SH_PFC_PIN_GROUP(tpu3_to1), + SH_PFC_PIN_GROUP(tpu3_to2), + SH_PFC_PIN_GROUP(tpu3_to3), + SH_PFC_PIN_GROUP(tpu4_to0), + SH_PFC_PIN_GROUP(tpu4_to1), + SH_PFC_PIN_GROUP(tpu4_to2), + SH_PFC_PIN_GROUP(tpu4_to3), + SH_PFC_PIN_GROUP(usb_vbus), +}; + +static const char * const bsc_groups[] = { + "bsc_data_0_7", + "bsc_data_8_15", + "bsc_cs4", + "bsc_cs5_a", + "bsc_cs5_b", + "bsc_cs6_a", + "bsc_cs6_b", + "bsc_rd", + "bsc_rdwr_0", + "bsc_rdwr_1", + "bsc_rdwr_2", + "bsc_we0", + "bsc_we1", +}; + +static const char * const fsia_groups[] = { + "fsia_mclk_in", + "fsia_mclk_out", + "fsia_sclk_in", + "fsia_sclk_out", + "fsia_data_in", + "fsia_data_out", + "fsia_spdif", +}; + +static const char * const fsib_groups[] = { + "fsib_mclk_in", + "fsib_mclk_out", + "fsib_sclk_in", + "fsib_sclk_out", + "fsib_data_in", + "fsib_data_out", + "fsib_spdif", +}; + +static const char * const fsic_groups[] = { + "fsic_mclk_in", + "fsic_mclk_out", + "fsic_sclk_in", + "fsic_sclk_out", + "fsic_data_in", + "fsic_data_out", + "fsic_spdif", +}; + +static const char * const fsid_groups[] = { + "fsid_sclk_in", + "fsid_sclk_out", + "fsid_data_in", +}; + +static const char * const i2c2_groups[] = { + "i2c2_0", + "i2c2_1", + "i2c2_2", +}; + +static const char * const i2c3_groups[] = { + "i2c3_0", + "i2c3_1", + "i2c3_2", +}; + +static const char * const irda_groups[] = { + "irda_0", + "irda_1", +}; + +static const char * const keysc_groups[] = { + "keysc_in5", + "keysc_in6", + "keysc_in7", + "keysc_in8", + "keysc_out04", + "keysc_out5", + "keysc_out6_0", + "keysc_out6_1", + "keysc_out6_2", + "keysc_out7_0", + "keysc_out7_1", + "keysc_out7_2", + "keysc_out8_0", + "keysc_out8_1", + "keysc_out8_2", + "keysc_out9_0", + "keysc_out9_1", + "keysc_out9_2", + "keysc_out10_0", + "keysc_out10_1", + "keysc_out11_0", + "keysc_out11_1", +}; + +static const char * const lcd_groups[] = { + "lcd_data8", + "lcd_data9", + "lcd_data12", + "lcd_data16", + "lcd_data18", + "lcd_data24", + "lcd_display", + "lcd_lclk", + "lcd_sync", + "lcd_sys", +}; + +static const char * const lcd2_groups[] = { + "lcd2_data8", + "lcd2_data9", + "lcd2_data12", + "lcd2_data16", + "lcd2_data18", + "lcd2_data24", + "lcd2_sync_0", + "lcd2_sync_1", + "lcd2_sys_0", + "lcd2_sys_1", +}; + +static const char * const mmc0_groups[] = { + "mmc0_data1_0", + "mmc0_data4_0", + "mmc0_data8_0", + "mmc0_ctrl_0", + "mmc0_data1_1", + "mmc0_data4_1", + "mmc0_data8_1", + "mmc0_ctrl_1", +}; + +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data_0", + "scifa2_clk_0", + "scifa2_ctrl_0", + "scifa2_data_1", + "scifa2_clk_1", + "scifa2_ctrl_1", +}; + +static const char * const scifa3_groups[] = { + "scifa3_data", + "scifa3_ctrl", +}; + +static const char * const scifa4_groups[] = { + "scifa4_data", + "scifa4_ctrl", +}; + +static const char * const scifa5_groups[] = { + "scifa5_data_0", + "scifa5_clk_0", + "scifa5_ctrl_0", + "scifa5_data_1", + "scifa5_clk_1", + "scifa5_ctrl_1", + "scifa5_data_2", + "scifa5_clk_2", + "scifa5_ctrl_2", +}; + +static const char * const scifa6_groups[] = { + "scifa6", +}; + +static const char * const scifa7_groups[] = { + "scifa7_data", + "scifa7_ctrl", +}; + +static const char * const scifb_groups[] = { + "scifb_data_0", + "scifb_clk_0", + "scifb_ctrl_0", + "scifb_data_1", + "scifb_clk_1", + "scifb_ctrl_1", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", +}; + +static const char * const usb_groups[] = { + "usb_vbus", +}; + +static const char * const tpu0_groups[] = { + "tpu0_to0", + "tpu0_to1", + "tpu0_to2", + "tpu0_to3", +}; + +static const char * const tpu1_groups[] = { + "tpu1_to0", + "tpu1_to1_0", + "tpu1_to1_1", + "tpu1_to2", + "tpu1_to3", +}; + +static const char * const tpu2_groups[] = { + "tpu2_to0", + "tpu2_to1", + "tpu2_to2", + "tpu2_to3", +}; + +static const char * const tpu3_groups[] = { + "tpu3_to0", + "tpu3_to1", + "tpu3_to2", + "tpu3_to3", +}; + +static const char * const tpu4_groups[] = { + "tpu4_to0", + "tpu4_to1", + "tpu4_to2", + "tpu4_to3", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(fsic), + SH_PFC_FUNCTION(fsid), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(irda), + SH_PFC_FUNCTION(keysc), + SH_PFC_FUNCTION(lcd), + SH_PFC_FUNCTION(lcd2), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifa6), + SH_PFC_FUNCTION(scifa7), + SH_PFC_FUNCTION(scifb), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(tpu0), + SH_PFC_FUNCTION(tpu1), + SH_PFC_FUNCTION(tpu2), + SH_PFC_FUNCTION(tpu3), + SH_PFC_FUNCTION(tpu4), + SH_PFC_FUNCTION(usb), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ PORTCR(1, 0xe6050001), /* PORT1CR */ PORTCR(2, 0xe6050002), /* PORT2CR */ @@ -2629,7 +3548,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, @@ -2733,60 +3652,238 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ -#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) -#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) - -static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), - PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0), - PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0), - PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0), - PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0), - PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0), - PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0), - PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0), - PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0), - PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0), - PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0), - PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0), - PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0), - PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0), - PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0), - PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0), - PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0), - PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0), - PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0), - PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0), - PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0), - PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0), - PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0), - PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0), - PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0), - PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0), - PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0), - PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0), - PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0), - PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0), - PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0), - PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0), -}; - -struct sh_pfc_soc_info sh73a0_pinmux_info = { +static const struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(irq_pin(0), 11), + PINMUX_IRQ(irq_pin(1), 10), + PINMUX_IRQ(irq_pin(2), 149), + PINMUX_IRQ(irq_pin(3), 224), + PINMUX_IRQ(irq_pin(4), 159), + PINMUX_IRQ(irq_pin(5), 227), + PINMUX_IRQ(irq_pin(6), 147), + PINMUX_IRQ(irq_pin(7), 150), + PINMUX_IRQ(irq_pin(8), 223), + PINMUX_IRQ(irq_pin(9), 56, 308), + PINMUX_IRQ(irq_pin(10), 54), + PINMUX_IRQ(irq_pin(11), 238), + PINMUX_IRQ(irq_pin(12), 156), + PINMUX_IRQ(irq_pin(13), 239), + PINMUX_IRQ(irq_pin(14), 251), + PINMUX_IRQ(irq_pin(15), 0), + PINMUX_IRQ(irq_pin(16), 249), + PINMUX_IRQ(irq_pin(17), 234), + PINMUX_IRQ(irq_pin(18), 13), + PINMUX_IRQ(irq_pin(19), 9), + PINMUX_IRQ(irq_pin(20), 14), + PINMUX_IRQ(irq_pin(21), 15), + PINMUX_IRQ(irq_pin(22), 40), + PINMUX_IRQ(irq_pin(23), 53), + PINMUX_IRQ(irq_pin(24), 118), + PINMUX_IRQ(irq_pin(25), 164), + PINMUX_IRQ(irq_pin(26), 115), + PINMUX_IRQ(irq_pin(27), 116), + PINMUX_IRQ(irq_pin(28), 117), + PINMUX_IRQ(irq_pin(29), 28), + PINMUX_IRQ(irq_pin(30), 27), + PINMUX_IRQ(irq_pin(31), 26), +}; + +/* ----------------------------------------------------------------------------- + * VCCQ MC0 regulator + */ + +static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable) +{ + struct sh_pfc *pfc = reg->reg_data; + void __iomem *addr = pfc->windows[1].virt + 4; + unsigned long flags; + u32 value; + + spin_lock_irqsave(&pfc->lock, flags); + + value = ioread32(addr); + + if (enable) + value |= BIT(28); + else + value &= ~BIT(28); + + iowrite32(value, addr); + + spin_unlock_irqrestore(&pfc->lock, flags); +} + +static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg) +{ + sh73a0_vccq_mc0_endisable(reg, true); + return 0; +} + +static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg) +{ + sh73a0_vccq_mc0_endisable(reg, false); + return 0; +} + +static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg) +{ + struct sh_pfc *pfc = reg->reg_data; + void __iomem *addr = pfc->windows[1].virt + 4; + unsigned long flags; + u32 value; + + spin_lock_irqsave(&pfc->lock, flags); + value = ioread32(addr); + spin_unlock_irqrestore(&pfc->lock, flags); + + return !!(value & BIT(28)); +} + +static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg) +{ + return 3300000; +} + +static struct regulator_ops sh73a0_vccq_mc0_ops = { + .enable = sh73a0_vccq_mc0_enable, + .disable = sh73a0_vccq_mc0_disable, + .is_enabled = sh73a0_vccq_mc0_is_enabled, + .get_voltage = sh73a0_vccq_mc0_get_voltage, +}; + +static const struct regulator_desc sh73a0_vccq_mc0_desc = { + .owner = THIS_MODULE, + .name = "vccq_mc0", + .type = REGULATOR_VOLTAGE, + .ops = &sh73a0_vccq_mc0_ops, +}; + +static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = { + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"), +}; + +static const struct regulator_init_data sh73a0_vccq_mc0_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers), + .consumer_supplies = sh73a0_vccq_mc0_consumers, +}; + +/* ----------------------------------------------------------------------------- + * Pin bias + */ + +#define PORTnCR_PULMD_OFF (0 << 6) +#define PORTnCR_PULMD_DOWN (2 << 6) +#define PORTnCR_PULMD_UP (3 << 6) +#define PORTnCR_PULMD_MASK (3 << 6) + +static const unsigned int sh73a0_portcr_offsets[] = { + 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000, + 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000, +}; + +static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *addr = pfc->windows->virt + + sh73a0_portcr_offsets[pin >> 5] + pin; + u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; + + switch (value) { + case PORTnCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTnCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTnCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr = pfc->windows->virt + + sh73a0_portcr_offsets[pin >> 5] + pin; + u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTnCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTnCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +/* ----------------------------------------------------------------------------- + * SoC information + */ + +struct sh73a0_pinmux_data { + struct regulator_dev *vccq_mc0; +}; + +static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) +{ + struct sh73a0_pinmux_data *data; + struct regulator_config cfg = { }; + int ret; + + data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + cfg.dev = pfc->dev; + cfg.init_data = &sh73a0_vccq_mc0_init_data; + cfg.driver_data = pfc; + + data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg); + if (IS_ERR(data->vccq_mc0)) { + ret = PTR_ERR(data->vccq_mc0); + dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n", + ret); + return ret; + } + + pfc->soc_data = data; + + return 0; +} + +static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc) +{ + struct sh73a0_pinmux_data *data = pfc->soc_data; + + regulator_unregister(data->vccq_mc0); +} + +static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { + .init = sh73a0_pinmux_soc_init, + .exit = sh73a0_pinmux_soc_exit, + .get_bias = sh73a0_pinmux_get_bias, + .set_bias = sh73a0_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info sh73a0_pinmux_info = { .name = "sh73a0_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .ops = &sh73a0_pinmux_ops, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PORT0, - .last_gpio = GPIO_FN_FSIAISLD_PU, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 10872ed688a..13d05f88bc0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -81,36 +81,6 @@ enum { PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, PINMUX_INPUT_END, - PINMUX_INPUT_PULLUP_BEGIN, - PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, - PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, - PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU, - PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU, - PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU, - PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU, - PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, - PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, - PTE4_IN_PU, PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, - PTF0_IN_PU, - PTG6_IN_PU, PTG5_IN_PU, PTG4_IN_PU, - PTG3_IN_PU, PTG2_IN_PU, PTG1_IN_PU, PTG0_IN_PU, - PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, - PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, - PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU, - PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, - PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, - PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, PTL3_IN_PU, - PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, - PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU, - PTP4_IN_PU, PTP3_IN_PU, PTP2_IN_PU, PTP1_IN_PU, PTP0_IN_PU, - PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU, - PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU, - PTS4_IN_PU, PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU, - PTT4_IN_PU, PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, - PTU4_IN_PU, PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, - PTV4_IN_PU, PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, - PINMUX_INPUT_PULLUP_END, - PINMUX_OUTPUT_BEGIN, PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, @@ -262,55 +232,55 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const u16 pinmux_data[] = { /* PTA GPIO */ - PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), - PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), - PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU), - PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), - PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), - PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), - PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), - PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), + PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), + PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT), + PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT), + PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT), + PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT), + PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT), /* PTB GPIO */ - PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU), - PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU), - PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU), - PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU), - PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU), - PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), - PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), - PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU), + PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), + PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), + PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), + PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), + PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), + PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), + PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), + PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), /* PTC GPIO */ - PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU), - PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU), - PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU), - PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU), - PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU), - PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU), - PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU), - PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU), + PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT), + PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT), + PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT), + PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), + PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), + PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), + PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT), + PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), /* PTD GPIO */ - PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU), - PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU), - PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU), - PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU), - PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU), - PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU), - PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU), - PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU), + PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT), + PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT), + PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT), + PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT), + PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT), + PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT), + PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT), + PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), /* PTE GPIO */ PINMUX_DATA(PTE6_DATA, PTE6_IN), PINMUX_DATA(PTE5_DATA, PTE5_IN), - PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU), - PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU), - PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU), - PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU), - PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU), + PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), + PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), + PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT), + PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT), + PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT), /* PTF GPIO */ PINMUX_DATA(PTF6_DATA, PTF6_IN), @@ -319,102 +289,102 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTF3_DATA, PTF3_IN), PINMUX_DATA(PTF2_DATA, PTF2_IN), PINMUX_DATA(PTF1_DATA, PTF1_IN), - PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU), + PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT), /* PTG GPIO */ - PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT, PTG6_IN_PU), - PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT, PTG5_IN_PU), - PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT, PTG4_IN_PU), - PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT, PTG3_IN_PU), - PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT, PTG2_IN_PU), - PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT, PTG1_IN_PU), - PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT, PTG0_IN_PU), + PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT), + PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT), + PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT), + PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT), + PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT), + PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT), + PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT), /* PTH GPIO */ - PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU), - PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU), - PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU), - PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU), - PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU), - PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU), - PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU), + PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT), + PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT), + PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT), + PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT), + PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT), + PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT), + PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT), /* PTJ GPIO */ - PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT, PTJ6_IN_PU), - PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT, PTJ5_IN_PU), - PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT, PTJ4_IN_PU), - PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU), - PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU), - PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU), - PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU), + PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT), + PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT), + PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT), + PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT), + PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT), + PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT), + PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT), /* PTK GPIO */ - PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU), - PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU), - PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU), - PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU), + PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT), + PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT), + PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT), + PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), /* PTL GPIO */ - PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU), - PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU), - PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU), - PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU), - PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU), + PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT), + PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), + PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), + PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), + PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT), /* PTM GPIO */ - PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU), - PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU), - PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU), - PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU), - PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU), - PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU), - PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU), - PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU), + PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT), + PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT), + PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT), + PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT), + PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT), + PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT), + PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT), + PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), /* PTP GPIO */ - PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT, PTP4_IN_PU), - PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT, PTP3_IN_PU), - PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT, PTP2_IN_PU), - PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT, PTP1_IN_PU), - PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT, PTP0_IN_PU), + PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT), + PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT), + PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT), + PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT), + PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT), /* PTR GPIO */ - PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU), - PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU), - PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU), - PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU), - PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT, PTR3_IN_PU), - PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT, PTR2_IN_PU), - PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU), - PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU), + PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT), + PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT), + PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT), + PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT), + PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT), + PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT), + PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT), + PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT), /* PTS GPIO */ - PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU), - PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU), - PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU), - PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU), - PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU), + PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT), + PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT), + PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT), + PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT), + PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), /* PTT GPIO */ - PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU), - PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU), - PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU), - PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU), - PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU), + PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), + PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), + PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT), + PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT), + PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT), /* PTU GPIO */ - PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU), - PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU), - PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU), - PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU), - PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU), + PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT), + PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT), + PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT), + PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT), + PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT), /* PTV GPIO */ - PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU), - PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU), - PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU), - PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU), - PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU), + PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT), + PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT), + PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT), + PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT), + PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT), /* PTA FN */ PINMUX_DATA(D23_MARK, PTA7_FN), @@ -606,404 +576,407 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ - PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), - PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), - PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), - PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), - PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), - PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), - PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), - PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), + PINMUX_GPIO(PTA7), + PINMUX_GPIO(PTA6), + PINMUX_GPIO(PTA5), + PINMUX_GPIO(PTA4), + PINMUX_GPIO(PTA3), + PINMUX_GPIO(PTA2), + PINMUX_GPIO(PTA1), + PINMUX_GPIO(PTA0), /* PTB */ - PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), - PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), - PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), - PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), - PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), - PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), - PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), - PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), + PINMUX_GPIO(PTB7), + PINMUX_GPIO(PTB6), + PINMUX_GPIO(PTB5), + PINMUX_GPIO(PTB4), + PINMUX_GPIO(PTB3), + PINMUX_GPIO(PTB2), + PINMUX_GPIO(PTB1), + PINMUX_GPIO(PTB0), /* PTC */ - PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), - PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), - PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), - PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), - PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), - PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), - PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), - PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), + PINMUX_GPIO(PTC7), + PINMUX_GPIO(PTC6), + PINMUX_GPIO(PTC5), + PINMUX_GPIO(PTC4), + PINMUX_GPIO(PTC3), + PINMUX_GPIO(PTC2), + PINMUX_GPIO(PTC1), + PINMUX_GPIO(PTC0), /* PTD */ - PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), - PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), - PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), - PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), - PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), - PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), - PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), - PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), + PINMUX_GPIO(PTD7), + PINMUX_GPIO(PTD6), + PINMUX_GPIO(PTD5), + PINMUX_GPIO(PTD4), + PINMUX_GPIO(PTD3), + PINMUX_GPIO(PTD2), + PINMUX_GPIO(PTD1), + PINMUX_GPIO(PTD0), /* PTE */ - PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), - PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), - PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), - PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), - PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), - PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), - PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), + PINMUX_GPIO(PTE6), + PINMUX_GPIO(PTE5), + PINMUX_GPIO(PTE4), + PINMUX_GPIO(PTE3), + PINMUX_GPIO(PTE2), + PINMUX_GPIO(PTE1), + PINMUX_GPIO(PTE0), /* PTF */ - PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), - PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), - PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), - PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), - PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), - PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), - PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), + PINMUX_GPIO(PTF6), + PINMUX_GPIO(PTF5), + PINMUX_GPIO(PTF4), + PINMUX_GPIO(PTF3), + PINMUX_GPIO(PTF2), + PINMUX_GPIO(PTF1), + PINMUX_GPIO(PTF0), /* PTG */ - PINMUX_GPIO(GPIO_PTG6, PTG6_DATA), - PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), - PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), - PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), - PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), - PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), - PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), + PINMUX_GPIO(PTG6), + PINMUX_GPIO(PTG5), + PINMUX_GPIO(PTG4), + PINMUX_GPIO(PTG3), + PINMUX_GPIO(PTG2), + PINMUX_GPIO(PTG1), + PINMUX_GPIO(PTG0), /* PTH */ - PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), - PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), - PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), - PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), - PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), - PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), - PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), + PINMUX_GPIO(PTH6), + PINMUX_GPIO(PTH5), + PINMUX_GPIO(PTH4), + PINMUX_GPIO(PTH3), + PINMUX_GPIO(PTH2), + PINMUX_GPIO(PTH1), + PINMUX_GPIO(PTH0), /* PTJ */ - PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), - PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), - PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), - PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), - PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), - PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), - PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), + PINMUX_GPIO(PTJ6), + PINMUX_GPIO(PTJ5), + PINMUX_GPIO(PTJ4), + PINMUX_GPIO(PTJ3), + PINMUX_GPIO(PTJ2), + PINMUX_GPIO(PTJ1), + PINMUX_GPIO(PTJ0), /* PTK */ - PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), - PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), - PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), - PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), + PINMUX_GPIO(PTK3), + PINMUX_GPIO(PTK2), + PINMUX_GPIO(PTK1), + PINMUX_GPIO(PTK0), /* PTL */ - PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), - PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), - PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), - PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), - PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), + PINMUX_GPIO(PTL7), + PINMUX_GPIO(PTL6), + PINMUX_GPIO(PTL5), + PINMUX_GPIO(PTL4), + PINMUX_GPIO(PTL3), /* PTM */ - PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), - PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), - PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), - PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), - PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), - PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), - PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), - PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), + PINMUX_GPIO(PTM7), + PINMUX_GPIO(PTM6), + PINMUX_GPIO(PTM5), + PINMUX_GPIO(PTM4), + PINMUX_GPIO(PTM3), + PINMUX_GPIO(PTM2), + PINMUX_GPIO(PTM1), + PINMUX_GPIO(PTM0), /* PTP */ - PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), - PINMUX_GPIO(GPIO_PTP3, PTP3_DATA), - PINMUX_GPIO(GPIO_PTP2, PTP2_DATA), - PINMUX_GPIO(GPIO_PTP1, PTP1_DATA), - PINMUX_GPIO(GPIO_PTP0, PTP0_DATA), + PINMUX_GPIO(PTP4), + PINMUX_GPIO(PTP3), + PINMUX_GPIO(PTP2), + PINMUX_GPIO(PTP1), + PINMUX_GPIO(PTP0), /* PTR */ - PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), - PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), - PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), - PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), - PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), - PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), - PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), - PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), + PINMUX_GPIO(PTR7), + PINMUX_GPIO(PTR6), + PINMUX_GPIO(PTR5), + PINMUX_GPIO(PTR4), + PINMUX_GPIO(PTR3), + PINMUX_GPIO(PTR2), + PINMUX_GPIO(PTR1), + PINMUX_GPIO(PTR0), /* PTS */ - PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), - PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), - PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), - PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), - PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), + PINMUX_GPIO(PTS4), + PINMUX_GPIO(PTS3), + PINMUX_GPIO(PTS2), + PINMUX_GPIO(PTS1), + PINMUX_GPIO(PTS0), /* PTT */ - PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), - PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), - PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), - PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), - PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), + PINMUX_GPIO(PTT4), + PINMUX_GPIO(PTT3), + PINMUX_GPIO(PTT2), + PINMUX_GPIO(PTT1), + PINMUX_GPIO(PTT0), /* PTU */ - PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), - PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), - PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), - PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), - PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), + PINMUX_GPIO(PTU4), + PINMUX_GPIO(PTU3), + PINMUX_GPIO(PTU2), + PINMUX_GPIO(PTU1), + PINMUX_GPIO(PTU0), /* PTV */ - PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), - PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), - PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), - PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), - PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), + PINMUX_GPIO(PTV4), + PINMUX_GPIO(PTV3), + PINMUX_GPIO(PTV2), + PINMUX_GPIO(PTV1), + PINMUX_GPIO(PTV0), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), - PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), - PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), - PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_A20, A20_MARK), - PINMUX_GPIO(GPIO_FN_A19, A19_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), - PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(IOIS16), + GPIO_FN(RAS), + GPIO_FN(CAS), + GPIO_FN(CKE), + GPIO_FN(CS5B_CE1A), + GPIO_FN(CS6B_CE1B), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(A20), + GPIO_FN(A19), + GPIO_FN(A0), + GPIO_FN(REFOUT), + GPIO_FN(IRQOUT), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), - PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), - PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), - PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), - PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), + GPIO_FN(LCD_DATA15), + GPIO_FN(LCD_DATA14), + GPIO_FN(LCD_DATA13), + GPIO_FN(LCD_DATA12), + GPIO_FN(LCD_DATA11), + GPIO_FN(LCD_DATA10), + GPIO_FN(LCD_DATA9), + GPIO_FN(LCD_DATA8), + GPIO_FN(LCD_DATA7), + GPIO_FN(LCD_DATA6), + GPIO_FN(LCD_DATA5), + GPIO_FN(LCD_DATA4), + GPIO_FN(LCD_DATA3), + GPIO_FN(LCD_DATA2), + GPIO_FN(LCD_DATA1), + GPIO_FN(LCD_DATA0), + GPIO_FN(LCD_M_DISP), + GPIO_FN(LCD_CL1), + GPIO_FN(LCD_CL2), + GPIO_FN(LCD_DON), + GPIO_FN(LCD_FLM), + GPIO_FN(LCD_VEPWC), + GPIO_FN(LCD_VCPWC), /* AFEIF */ - PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK), - PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK), - PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK), - PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK), - PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK), - PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK), - PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK), + GPIO_FN(AFE_RXIN), + GPIO_FN(AFE_RDET), + GPIO_FN(AFE_FS), + GPIO_FN(AFE_TXOUT), + GPIO_FN(AFE_SCLK), + GPIO_FN(AFE_RLYCNT), + GPIO_FN(AFE_HC1), /* IIC */ - PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK), - PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK), + GPIO_FN(IIC_SCL), + GPIO_FN(IIC_SDA), /* DAC */ - PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK), - PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK), + GPIO_FN(DA1), + GPIO_FN(DA0), /* ADC */ - PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), - PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), - PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), - PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + GPIO_FN(AN3), + GPIO_FN(AN2), + GPIO_FN(AN1), + GPIO_FN(AN0), + GPIO_FN(ADTRG), /* USB */ - PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK), - - PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK), - PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP, - USB1_PWR_EN_USBF_UPLUP_MARK), - PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK), + GPIO_FN(USB1D_RCV), + GPIO_FN(USB1D_TXSE0), + GPIO_FN(USB1D_TXDPLS), + GPIO_FN(USB1D_DMNS), + GPIO_FN(USB1D_DPLS), + GPIO_FN(USB1D_SPEED), + GPIO_FN(USB1D_TXENL), + + GPIO_FN(USB2_PWR_EN), + GPIO_FN(USB1_PWR_EN_USBF_UPLUP), + GPIO_FN(USB1D_SUSPEND), /* INTC */ - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK), + GPIO_FN(IRQ5), + GPIO_FN(IRQ4), + GPIO_FN(IRQ3_IRL3), + GPIO_FN(IRQ2_IRL2), + GPIO_FN(IRQ1_IRL1), + GPIO_FN(IRQ0_IRL0), /* PCC */ - PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK), - PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK), - PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK), - PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK), - PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK), - PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK), - PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK), - PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK), - PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK), - PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK), + GPIO_FN(PCC_REG), + GPIO_FN(PCC_DRV), + GPIO_FN(PCC_BVD2), + GPIO_FN(PCC_BVD1), + GPIO_FN(PCC_CD2), + GPIO_FN(PCC_CD1), + GPIO_FN(PCC_RESET), + GPIO_FN(PCC_RDY), + GPIO_FN(PCC_VS2), + GPIO_FN(PCC_VS1), /* HUDI */ - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK), - PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK), - PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK), - PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK), - PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK), - PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), + GPIO_FN(AUDCK), + GPIO_FN(AUDSYNC), + GPIO_FN(ASEBRKAK), + GPIO_FN(TRST), + GPIO_FN(TMS), + GPIO_FN(TDO), + GPIO_FN(TDI), + GPIO_FN(TCK), /* DMAC */ - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + GPIO_FN(DACK1), + GPIO_FN(DREQ1), + GPIO_FN(DACK0), + GPIO_FN(DREQ0), + GPIO_FN(TEND1), + GPIO_FN(TEND0), /* SIOF0 */ - PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), + GPIO_FN(SIOF0_SYNC), + GPIO_FN(SIOF0_MCLK), + GPIO_FN(SIOF0_TXD), + GPIO_FN(SIOF0_RXD), + GPIO_FN(SIOF0_SCK), /* SIOF1 */ - PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), + GPIO_FN(SIOF1_SYNC), + GPIO_FN(SIOF1_MCLK), + GPIO_FN(SIOF1_TXD), + GPIO_FN(SIOF1_RXD), + GPIO_FN(SIOF1_SCK), /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + GPIO_FN(SCIF0_TXD), + GPIO_FN(SCIF0_RXD), + GPIO_FN(SCIF0_RTS), + GPIO_FN(SCIF0_CTS), + GPIO_FN(SCIF0_SCK), /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + GPIO_FN(SCIF1_TXD), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_RTS), + GPIO_FN(SCIF1_CTS), + GPIO_FN(SCIF1_SCK), /* TPU */ - PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK), - PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK), + GPIO_FN(TPU_TO1), + GPIO_FN(TPU_TO0), + GPIO_FN(TPU_TI3B), + GPIO_FN(TPU_TI3A), + GPIO_FN(TPU_TI2B), + GPIO_FN(TPU_TI2A), + GPIO_FN(TPU_TO3), + GPIO_FN(TPU_TO2), /* SIM */ - PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), - PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), + GPIO_FN(SIM_D), + GPIO_FN(SIM_CLK), + GPIO_FN(SIM_RST), /* MMC */ - PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), - PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK), - PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK), + GPIO_FN(MMC_DAT), + GPIO_FN(MMC_CMD), + GPIO_FN(MMC_CLK), + GPIO_FN(MMC_VDDON), + GPIO_FN(MMC_ODMOD), /* SYSC */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + GPIO_FN(STATUS0), + GPIO_FN(STATUS1), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { - PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, - PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, - PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN, - PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, - PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, - PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, - PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, - PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } + PTA7_FN, PTA7_OUT, 0, PTA7_IN, + PTA6_FN, PTA6_OUT, 0, PTA6_IN, + PTA5_FN, PTA5_OUT, 0, PTA5_IN, + PTA4_FN, PTA4_OUT, 0, PTA4_IN, + PTA3_FN, PTA3_OUT, 0, PTA3_IN, + PTA2_FN, PTA2_OUT, 0, PTA2_IN, + PTA1_FN, PTA1_OUT, 0, PTA1_IN, + PTA0_FN, PTA0_OUT, 0, PTA0_IN } }, { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { - PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN, - PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN, - PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN, - PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN, - PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN, - PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, - PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, - PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN } + PTB7_FN, PTB7_OUT, 0, PTB7_IN, + PTB6_FN, PTB6_OUT, 0, PTB6_IN, + PTB5_FN, PTB5_OUT, 0, PTB5_IN, + PTB4_FN, PTB4_OUT, 0, PTB4_IN, + PTB3_FN, PTB3_OUT, 0, PTB3_IN, + PTB2_FN, PTB2_OUT, 0, PTB2_IN, + PTB1_FN, PTB1_OUT, 0, PTB1_IN, + PTB0_FN, PTB0_OUT, 0, PTB0_IN } }, { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { - PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN, - PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN, - PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN, - PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN, - PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN, - PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN, - PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN, - PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN } + PTC7_FN, PTC7_OUT, 0, PTC7_IN, + PTC6_FN, PTC6_OUT, 0, PTC6_IN, + PTC5_FN, PTC5_OUT, 0, PTC5_IN, + PTC4_FN, PTC4_OUT, 0, PTC4_IN, + PTC3_FN, PTC3_OUT, 0, PTC3_IN, + PTC2_FN, PTC2_OUT, 0, PTC2_IN, + PTC1_FN, PTC1_OUT, 0, PTC1_IN, + PTC0_FN, PTC0_OUT, 0, PTC0_IN } }, { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { - PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN, - PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN, - PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN, - PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN, - PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN, - PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN, - PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN, - PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN } + PTD7_FN, PTD7_OUT, 0, PTD7_IN, + PTD6_FN, PTD6_OUT, 0, PTD6_IN, + PTD5_FN, PTD5_OUT, 0, PTD5_IN, + PTD4_FN, PTD4_OUT, 0, PTD4_IN, + PTD3_FN, PTD3_OUT, 0, PTD3_IN, + PTD2_FN, PTD2_OUT, 0, PTD2_IN, + PTD1_FN, PTD1_OUT, 0, PTD1_IN, + PTD0_FN, PTD0_OUT, 0, PTD0_IN } }, { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { 0, 0, 0, 0, PTE6_FN, 0, 0, PTE6_IN, PTE5_FN, 0, 0, PTE5_IN, - PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN, - PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN, - PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN, - PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN, - PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN } + PTE4_FN, PTE4_OUT, 0, PTE4_IN, + PTE3_FN, PTE3_OUT, 0, PTE3_IN, + PTE2_FN, PTE2_OUT, 0, PTE2_IN, + PTE1_FN, PTE1_OUT, 0, PTE1_IN, + PTE0_FN, PTE0_OUT, 0, PTE0_IN } }, { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { 0, 0, 0, 0, @@ -1017,128 +990,128 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { }, { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { 0, 0, 0, 0, - PTG6_FN, PTG6_OUT, PTG6_IN_PU, PTG6_IN, - PTG5_FN, PTG5_OUT, PTG5_IN_PU, PTG5_IN, - PTG4_FN, PTG4_OUT, PTG4_IN_PU, PTG4_IN, - PTG3_FN, PTG3_OUT, PTG3_IN_PU, PTG3_IN, - PTG2_FN, PTG2_OUT, PTG2_IN_PU, PTG2_IN, - PTG1_FN, PTG1_OUT, PTG1_IN_PU, PTG1_IN, - PTG0_FN, PTG0_OUT, PTG0_IN_PU, PTG0_IN } + PTG6_FN, PTG6_OUT, 0, PTG6_IN, + PTG5_FN, PTG5_OUT, 0, PTG5_IN, + PTG4_FN, PTG4_OUT, 0, PTG4_IN, + PTG3_FN, PTG3_OUT, 0, PTG3_IN, + PTG2_FN, PTG2_OUT, 0, PTG2_IN, + PTG1_FN, PTG1_OUT, 0, PTG1_IN, + PTG0_FN, PTG0_OUT, 0, PTG0_IN } }, { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { 0, 0, 0, 0, - PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN, - PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN, - PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN, - PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN, - PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN, - PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN, - PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN } + PTH6_FN, PTH6_OUT, 0, PTH6_IN, + PTH5_FN, PTH5_OUT, 0, PTH5_IN, + PTH4_FN, PTH4_OUT, 0, PTH4_IN, + PTH3_FN, PTH3_OUT, 0, PTH3_IN, + PTH2_FN, PTH2_OUT, 0, PTH2_IN, + PTH1_FN, PTH1_OUT, 0, PTH1_IN, + PTH0_FN, PTH0_OUT, 0, PTH0_IN } }, { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { 0, 0, 0, 0, - PTJ6_FN, PTJ6_OUT, PTJ6_IN_PU, PTJ6_IN, - PTJ5_FN, PTJ5_OUT, PTJ5_IN_PU, PTJ5_IN, - PTJ4_FN, PTJ4_OUT, PTJ4_IN_PU, PTJ4_IN, - PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN, - PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN, - PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, - PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } + PTJ6_FN, PTJ6_OUT, 0, PTJ6_IN, + PTJ5_FN, PTJ5_OUT, 0, PTJ5_IN, + PTJ4_FN, PTJ4_OUT, 0, PTJ4_IN, + PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN, + PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN, + PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN, + PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN } }, { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN, - PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN, - PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN, - PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN } + PTK3_FN, PTK3_OUT, 0, PTK3_IN, + PTK2_FN, PTK2_OUT, 0, PTK2_IN, + PTK1_FN, PTK1_OUT, 0, PTK1_IN, + PTK0_FN, PTK0_OUT, 0, PTK0_IN } }, { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { - PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN, - PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN, - PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN, - PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN, - PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN, + PTL7_FN, PTL7_OUT, 0, PTL7_IN, + PTL6_FN, PTL6_OUT, 0, PTL6_IN, + PTL5_FN, PTL5_OUT, 0, PTL5_IN, + PTL4_FN, PTL4_OUT, 0, PTL4_IN, + PTL3_FN, PTL3_OUT, 0, PTL3_IN, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { - PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN, - PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN, - PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN, - PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN, - PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN, - PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN, - PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN, - PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN } + PTM7_FN, PTM7_OUT, 0, PTM7_IN, + PTM6_FN, PTM6_OUT, 0, PTM6_IN, + PTM5_FN, PTM5_OUT, 0, PTM5_IN, + PTM4_FN, PTM4_OUT, 0, PTM4_IN, + PTM3_FN, PTM3_OUT, 0, PTM3_IN, + PTM2_FN, PTM2_OUT, 0, PTM2_IN, + PTM1_FN, PTM1_OUT, 0, PTM1_IN, + PTM0_FN, PTM0_OUT, 0, PTM0_IN } }, { PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PTP4_FN, PTP4_OUT, PTP4_IN_PU, PTP4_IN, - PTP3_FN, PTP3_OUT, PTP3_IN_PU, PTP3_IN, - PTP2_FN, PTP2_OUT, PTP2_IN_PU, PTP2_IN, - PTP1_FN, PTP1_OUT, PTP1_IN_PU, PTP1_IN, - PTP0_FN, PTP0_OUT, PTP0_IN_PU, PTP0_IN } + PTP4_FN, PTP4_OUT, 0, PTP4_IN, + PTP3_FN, PTP3_OUT, 0, PTP3_IN, + PTP2_FN, PTP2_OUT, 0, PTP2_IN, + PTP1_FN, PTP1_OUT, 0, PTP1_IN, + PTP0_FN, PTP0_OUT, 0, PTP0_IN } }, { PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2) { - PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN, - PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN, - PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN, - PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN, - PTR3_FN, PTR3_OUT, PTR3_IN_PU, PTR3_IN, - PTR2_FN, PTR2_OUT, PTR2_IN_PU, PTR2_IN, - PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN, - PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN } + PTR7_FN, PTR7_OUT, 0, PTR7_IN, + PTR6_FN, PTR6_OUT, 0, PTR6_IN, + PTR5_FN, PTR5_OUT, 0, PTR5_IN, + PTR4_FN, PTR4_OUT, 0, PTR4_IN, + PTR3_FN, PTR3_OUT, 0, PTR3_IN, + PTR2_FN, PTR2_OUT, 0, PTR2_IN, + PTR1_FN, PTR1_OUT, 0, PTR1_IN, + PTR0_FN, PTR0_OUT, 0, PTR0_IN } }, { PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN, - PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN, - PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN, - PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN, - PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN } + PTS4_FN, PTS4_OUT, 0, PTS4_IN, + PTS3_FN, PTS3_OUT, 0, PTS3_IN, + PTS2_FN, PTS2_OUT, 0, PTS2_IN, + PTS1_FN, PTS1_OUT, 0, PTS1_IN, + PTS0_FN, PTS0_OUT, 0, PTS0_IN } }, { PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN, - PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN, - PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN, - PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN, - PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN } + PTT4_FN, PTT4_OUT, 0, PTT4_IN, + PTT3_FN, PTT3_OUT, 0, PTT3_IN, + PTT2_FN, PTT2_OUT, 0, PTT2_IN, + PTT1_FN, PTT1_OUT, 0, PTT1_IN, + PTT0_FN, PTT0_OUT, 0, PTT0_IN } }, { PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN, - PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN, - PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN, - PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN, - PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN } + PTU4_FN, PTU4_OUT, 0, PTU4_IN, + PTU3_FN, PTU3_OUT, 0, PTU3_IN, + PTU2_FN, PTU2_OUT, 0, PTU2_IN, + PTU1_FN, PTU1_OUT, 0, PTU1_IN, + PTU0_FN, PTU0_OUT, 0, PTU0_IN } }, { PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN, - PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN, - PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN, - PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN, - PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN } + PTV4_FN, PTV4_OUT, 0, PTV4_IN, + PTV3_FN, PTV3_OUT, 0, PTV3_IN, + PTV2_FN, PTV2_OUT, 0, PTV2_IN, + PTV1_FN, PTV1_OUT, 0, PTV1_IN, + PTV0_FN, PTV0_OUT, 0, PTV0_IN } }, {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050140, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -1214,20 +1187,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7720_pinmux_info = { +const struct sh_pfc_soc_info sh7720_pinmux_info = { .name = "sh7720_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_STATUS1, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index 2de0929315e..914d872c37a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -77,39 +77,6 @@ enum { PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN, PINMUX_INPUT_END, - PINMUX_INPUT_PULLDOWN_BEGIN, - PTA7_IN_PD, PTA6_IN_PD, PTA5_IN_PD, PTA4_IN_PD, - PTA3_IN_PD, PTA2_IN_PD, PTA1_IN_PD, PTA0_IN_PD, - PTE7_IN_PD, PTE6_IN_PD, PTE5_IN_PD, PTE4_IN_PD, PTE1_IN_PD, PTE0_IN_PD, - PTF6_IN_PD, PTF5_IN_PD, PTF4_IN_PD, PTF3_IN_PD, PTF2_IN_PD, PTF1_IN_PD, - PTH6_IN_PD, PTH5_IN_PD, PTH1_IN_PD, PTH0_IN_PD, - PTK6_IN_PD, PTK5_IN_PD, PTK4_IN_PD, PTK3_IN_PD, PTK2_IN_PD, PTK0_IN_PD, - PTL7_IN_PD, PTL6_IN_PD, PTL5_IN_PD, PTL4_IN_PD, - PTL3_IN_PD, PTL2_IN_PD, PTL1_IN_PD, PTL0_IN_PD, - PTM7_IN_PD, PTM6_IN_PD, PTM5_IN_PD, PTM4_IN_PD, - PTM3_IN_PD, PTM2_IN_PD, PTM1_IN_PD, PTM0_IN_PD, - PTQ5_IN_PD, PTQ4_IN_PD, PTQ3_IN_PD, PTQ2_IN_PD, - PTS4_IN_PD, PTS2_IN_PD, PTS1_IN_PD, - PTT4_IN_PD, PTT3_IN_PD, PTT2_IN_PD, PTT1_IN_PD, - PTU4_IN_PD, PTU3_IN_PD, PTU2_IN_PD, PTU1_IN_PD, PTU0_IN_PD, - PTV4_IN_PD, PTV3_IN_PD, PTV2_IN_PD, PTV1_IN_PD, PTV0_IN_PD, - PTW6_IN_PD, PTW4_IN_PD, PTW3_IN_PD, PTW2_IN_PD, PTW1_IN_PD, PTW0_IN_PD, - PTX6_IN_PD, PTX5_IN_PD, PTX4_IN_PD, - PTX3_IN_PD, PTX2_IN_PD, PTX1_IN_PD, PTX0_IN_PD, - PINMUX_INPUT_PULLDOWN_END, - - PINMUX_INPUT_PULLUP_BEGIN, - PTC7_IN_PU, PTC5_IN_PU, - PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, - PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, - PTJ1_IN_PU, PTJ0_IN_PU, - PTQ0_IN_PU, - PTR2_IN_PU, - PTX6_IN_PU, - PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY0_IN_PU, - PTZ5_IN_PU, PTZ4_IN_PU, PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, - PINMUX_INPUT_PULLUP_END, - PINMUX_OUTPUT_BEGIN, PTA7_OUT, PTA5_OUT, PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, @@ -296,16 +263,16 @@ enum { PINMUX_FUNCTION_END, }; -static pinmux_enum_t pinmux_data[] = { +static const u16 pinmux_data[] = { /* PTA */ - PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT), - PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD), - PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_IN_PD, PTA5_OUT), - PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_IN_PD), - PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_IN_PD), - PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_IN_PD), - PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_IN_PD), - PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_IN_PD), + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN), + PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), + PINMUX_DATA(PTA4_DATA, PTA4_IN), + PINMUX_DATA(PTA3_DATA, PTA3_IN), + PINMUX_DATA(PTA2_DATA, PTA2_IN), + PINMUX_DATA(PTA1_DATA, PTA1_IN), + PINMUX_DATA(PTA0_DATA, PTA0_IN), /* PTB */ PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), @@ -318,38 +285,38 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), /* PTC */ - PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_IN_PU), - PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_IN_PU), + PINMUX_DATA(PTC7_DATA, PTC7_IN), + PINMUX_DATA(PTC5_DATA, PTC5_IN), PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), /* PTD */ - PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_IN_PU), - PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN, PTD6_IN_PU), - PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN, PTD5_IN_PU), - PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN, PTD4_IN_PU), - PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN, PTD3_IN_PU), - PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN, PTD2_IN_PU), - PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN, PTD1_IN_PU), + PINMUX_DATA(PTD7_DATA, PTD7_IN), + PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN), + PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN), + PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN), + PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN), + PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN), + PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN), PINMUX_DATA(PTD0_DATA, PTD0_OUT), /* PTE */ - PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN, PTE7_IN_PD), - PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN, PTE6_IN_PD), - PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN, PTE5_IN_PD), - PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN, PTE4_IN_PD), - PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN, PTE1_IN_PD), - PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN, PTE0_IN_PD), + PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN), + PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN), + PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN), + PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN), + PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN), + PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN), /* PTF */ - PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN, PTF6_IN_PD), - PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN, PTF5_IN_PD), - PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN, PTF4_IN_PD), - PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN, PTF3_IN_PD), - PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN, PTF2_IN_PD), - PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_IN_PD), + PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN), + PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN), + PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN), + PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN), + PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN), + PINMUX_DATA(PTF1_DATA, PTF1_IN), PINMUX_DATA(PTF0_DATA, PTF0_OUT), /* PTG */ @@ -361,49 +328,49 @@ static pinmux_enum_t pinmux_data[] = { /* PTH */ PINMUX_DATA(PTH7_DATA, PTH7_OUT), - PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN, PTH6_IN_PD), - PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN, PTH5_IN_PD), + PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN), + PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN), PINMUX_DATA(PTH4_DATA, PTH4_OUT), PINMUX_DATA(PTH3_DATA, PTH3_OUT), PINMUX_DATA(PTH2_DATA, PTH2_OUT), - PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN, PTH1_IN_PD), - PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN, PTH0_IN_PD), + PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN), + PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN), /* PTJ */ PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), PINMUX_DATA(PTJ6_DATA, PTJ6_OUT), PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), - PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU), - PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU), + PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN), + PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN), /* PTK */ - PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN, PTK6_IN_PD), - PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN, PTK5_IN_PD), - PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN, PTK4_IN_PD), - PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN, PTK3_IN_PD), - PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_IN_PD), + PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN), + PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN), + PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN), + PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN), + PINMUX_DATA(PTK2_DATA, PTK2_IN), PINMUX_DATA(PTK1_DATA, PTK1_OUT), - PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN, PTK0_IN_PD), + PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN), /* PTL */ - PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN, PTL7_IN_PD), - PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN, PTL6_IN_PD), - PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN, PTL5_IN_PD), - PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN, PTL4_IN_PD), - PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN, PTL3_IN_PD), - PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN, PTL2_IN_PD), - PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN, PTL1_IN_PD), - PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN, PTL0_IN_PD), + PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN), + PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN), + PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN), + PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN), + PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN), + PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN), + PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN), + PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN), /* PTM */ - PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN, PTM7_IN_PD), - PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN, PTM6_IN_PD), - PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN, PTM5_IN_PD), - PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN, PTM4_IN_PD), - PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN, PTM3_IN_PD), - PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN, PTM2_IN_PD), - PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN, PTM1_IN_PD), - PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN, PTM0_IN_PD), + PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN), + PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN), + PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN), + PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN), + PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN), + PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN), + PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN), + PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN), /* PTN */ PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN), @@ -417,80 +384,80 @@ static pinmux_enum_t pinmux_data[] = { /* PTQ */ PINMUX_DATA(PTQ6_DATA, PTQ6_OUT), - PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN, PTQ5_IN_PD), - PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN, PTQ4_IN_PD), - PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN, PTQ3_IN_PD), - PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_IN_PD), + PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN), + PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN), + PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN), + PINMUX_DATA(PTQ2_DATA, PTQ2_IN), PINMUX_DATA(PTQ1_DATA, PTQ1_OUT), - PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN, PTQ0_IN_PU), + PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN), /* PTR */ PINMUX_DATA(PTR4_DATA, PTR4_OUT), PINMUX_DATA(PTR3_DATA, PTR3_OUT), - PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), + PINMUX_DATA(PTR2_DATA, PTR2_IN), PINMUX_DATA(PTR1_DATA, PTR1_OUT), PINMUX_DATA(PTR0_DATA, PTR0_OUT), /* PTS */ - PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_IN_PD), + PINMUX_DATA(PTS4_DATA, PTS4_IN), PINMUX_DATA(PTS3_DATA, PTS3_OUT), - PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN, PTS2_IN_PD), - PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_IN_PD), + PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN), + PINMUX_DATA(PTS1_DATA, PTS1_IN), PINMUX_DATA(PTS0_DATA, PTS0_OUT), /* PTT */ - PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN, PTT4_IN_PD), - PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN, PTT3_IN_PD), - PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN, PTT2_IN_PD), - PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_IN_PD), + PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN), + PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN), + PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN), + PINMUX_DATA(PTT1_DATA, PTT1_IN), PINMUX_DATA(PTT0_DATA, PTT0_OUT), /* PTU */ - PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN, PTU4_IN_PD), - PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN, PTU3_IN_PD), - PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN, PTU2_IN_PD), - PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_IN_PD), - PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN, PTU0_IN_PD), + PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN), + PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN), + PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN), + PINMUX_DATA(PTU1_DATA, PTU1_IN), + PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN), /* PTV */ - PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN, PTV4_IN_PD), - PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN, PTV3_IN_PD), - PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN, PTV2_IN_PD), - PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN, PTV1_IN_PD), - PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN, PTV0_IN_PD), + PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN), + PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN), + PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN), + PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN), + PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN), /* PTW */ - PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_IN_PD), + PINMUX_DATA(PTW6_DATA, PTW6_IN), PINMUX_DATA(PTW5_DATA, PTW5_OUT), - PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN, PTW4_IN_PD), - PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN, PTW3_IN_PD), - PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN, PTW2_IN_PD), - PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN, PTW1_IN_PD), - PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN, PTW0_IN_PD), + PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN), + PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN), + PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN), + PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN), + PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN), /* PTX */ - PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN, PTX6_IN_PD), - PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN, PTX5_IN_PD), - PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN, PTX4_IN_PD), - PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN, PTX3_IN_PD), - PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN, PTX2_IN_PD), - PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN, PTX1_IN_PD), - PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN, PTX0_IN_PD), + PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN), + PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN), + PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN), + PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN), + PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN), + PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN), + PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN), /* PTY */ - PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN, PTY5_IN_PU), - PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN, PTY4_IN_PU), - PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN, PTY3_IN_PU), - PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN, PTY2_IN_PU), + PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN), + PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN), + PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN), + PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN), PINMUX_DATA(PTY1_DATA, PTY1_OUT), - PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN, PTY0_IN_PU), + PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN), /* PTZ */ - PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_IN_PU), - PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_IN_PU), - PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_IN_PU), - PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_IN_PU), - PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_IN_PU), + PINMUX_DATA(PTZ5_DATA, PTZ5_IN), + PINMUX_DATA(PTZ4_DATA, PTZ4_IN), + PINMUX_DATA(PTZ3_DATA, PTZ3_IN), + PINMUX_DATA(PTZ2_DATA, PTZ2_IN), + PINMUX_DATA(PTZ1_DATA, PTZ1_IN), /* SCIF0 */ PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD), @@ -787,493 +754,497 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ - PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), - PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), - PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), - PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), - PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), - PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), - PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), - PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), + PINMUX_GPIO(PTA7), + PINMUX_GPIO(PTA6), + PINMUX_GPIO(PTA5), + PINMUX_GPIO(PTA4), + PINMUX_GPIO(PTA3), + PINMUX_GPIO(PTA2), + PINMUX_GPIO(PTA1), + PINMUX_GPIO(PTA0), /* PTB */ - PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), - PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), - PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), - PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), - PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), - PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), - PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), - PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), + PINMUX_GPIO(PTB7), + PINMUX_GPIO(PTB6), + PINMUX_GPIO(PTB5), + PINMUX_GPIO(PTB4), + PINMUX_GPIO(PTB3), + PINMUX_GPIO(PTB2), + PINMUX_GPIO(PTB1), + PINMUX_GPIO(PTB0), /* PTC */ - PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), - PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), - PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), - PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), - PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), - PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), + PINMUX_GPIO(PTC7), + PINMUX_GPIO(PTC5), + PINMUX_GPIO(PTC4), + PINMUX_GPIO(PTC3), + PINMUX_GPIO(PTC2), + PINMUX_GPIO(PTC0), /* PTD */ - PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), - PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), - PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), - PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), - PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), - PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), - PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), - PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), + PINMUX_GPIO(PTD7), + PINMUX_GPIO(PTD6), + PINMUX_GPIO(PTD5), + PINMUX_GPIO(PTD4), + PINMUX_GPIO(PTD3), + PINMUX_GPIO(PTD2), + PINMUX_GPIO(PTD1), + PINMUX_GPIO(PTD0), /* PTE */ - PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), - PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), - PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), - PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), - PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), - PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), + PINMUX_GPIO(PTE7), + PINMUX_GPIO(PTE6), + PINMUX_GPIO(PTE5), + PINMUX_GPIO(PTE4), + PINMUX_GPIO(PTE1), + PINMUX_GPIO(PTE0), /* PTF */ - PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), - PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), - PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), - PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), - PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), - PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), - PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), + PINMUX_GPIO(PTF6), + PINMUX_GPIO(PTF5), + PINMUX_GPIO(PTF4), + PINMUX_GPIO(PTF3), + PINMUX_GPIO(PTF2), + PINMUX_GPIO(PTF1), + PINMUX_GPIO(PTF0), /* PTG */ - PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), - PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), - PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), - PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), - PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), + PINMUX_GPIO(PTG4), + PINMUX_GPIO(PTG3), + PINMUX_GPIO(PTG2), + PINMUX_GPIO(PTG1), + PINMUX_GPIO(PTG0), /* PTH */ - PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), - PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), - PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), - PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), - PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), - PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), - PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), - PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), + PINMUX_GPIO(PTH7), + PINMUX_GPIO(PTH6), + PINMUX_GPIO(PTH5), + PINMUX_GPIO(PTH4), + PINMUX_GPIO(PTH3), + PINMUX_GPIO(PTH2), + PINMUX_GPIO(PTH1), + PINMUX_GPIO(PTH0), /* PTJ */ - PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), - PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), - PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), - PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), - PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), + PINMUX_GPIO(PTJ7), + PINMUX_GPIO(PTJ6), + PINMUX_GPIO(PTJ5), + PINMUX_GPIO(PTJ1), + PINMUX_GPIO(PTJ0), /* PTK */ - PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), - PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), - PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), - PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), - PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), - PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), - PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), + PINMUX_GPIO(PTK6), + PINMUX_GPIO(PTK5), + PINMUX_GPIO(PTK4), + PINMUX_GPIO(PTK3), + PINMUX_GPIO(PTK2), + PINMUX_GPIO(PTK1), + PINMUX_GPIO(PTK0), /* PTL */ - PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), - PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), - PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), - PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), - PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), - PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), - PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), - PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), + PINMUX_GPIO(PTL7), + PINMUX_GPIO(PTL6), + PINMUX_GPIO(PTL5), + PINMUX_GPIO(PTL4), + PINMUX_GPIO(PTL3), + PINMUX_GPIO(PTL2), + PINMUX_GPIO(PTL1), + PINMUX_GPIO(PTL0), /* PTM */ - PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), - PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), - PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), - PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), - PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), - PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), - PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), - PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), + PINMUX_GPIO(PTM7), + PINMUX_GPIO(PTM6), + PINMUX_GPIO(PTM5), + PINMUX_GPIO(PTM4), + PINMUX_GPIO(PTM3), + PINMUX_GPIO(PTM2), + PINMUX_GPIO(PTM1), + PINMUX_GPIO(PTM0), /* PTN */ - PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), - PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), - PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), - PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), - PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), - PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), - PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), - PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), + PINMUX_GPIO(PTN7), + PINMUX_GPIO(PTN6), + PINMUX_GPIO(PTN5), + PINMUX_GPIO(PTN4), + PINMUX_GPIO(PTN3), + PINMUX_GPIO(PTN2), + PINMUX_GPIO(PTN1), + PINMUX_GPIO(PTN0), /* PTQ */ - PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), - PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), - PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), - PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), - PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), - PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), - PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), + PINMUX_GPIO(PTQ6), + PINMUX_GPIO(PTQ5), + PINMUX_GPIO(PTQ4), + PINMUX_GPIO(PTQ3), + PINMUX_GPIO(PTQ2), + PINMUX_GPIO(PTQ1), + PINMUX_GPIO(PTQ0), /* PTR */ - PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), - PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), - PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), - PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), - PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), + PINMUX_GPIO(PTR4), + PINMUX_GPIO(PTR3), + PINMUX_GPIO(PTR2), + PINMUX_GPIO(PTR1), + PINMUX_GPIO(PTR0), /* PTS */ - PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), - PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), - PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), - PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), - PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), + PINMUX_GPIO(PTS4), + PINMUX_GPIO(PTS3), + PINMUX_GPIO(PTS2), + PINMUX_GPIO(PTS1), + PINMUX_GPIO(PTS0), /* PTT */ - PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), - PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), - PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), - PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), - PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), + PINMUX_GPIO(PTT4), + PINMUX_GPIO(PTT3), + PINMUX_GPIO(PTT2), + PINMUX_GPIO(PTT1), + PINMUX_GPIO(PTT0), /* PTU */ - PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), - PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), - PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), - PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), - PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), + PINMUX_GPIO(PTU4), + PINMUX_GPIO(PTU3), + PINMUX_GPIO(PTU2), + PINMUX_GPIO(PTU1), + PINMUX_GPIO(PTU0), /* PTV */ - PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), - PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), - PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), - PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), - PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), + PINMUX_GPIO(PTV4), + PINMUX_GPIO(PTV3), + PINMUX_GPIO(PTV2), + PINMUX_GPIO(PTV1), + PINMUX_GPIO(PTV0), /* PTW */ - PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), - PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), - PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), - PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), - PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), - PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), - PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), + PINMUX_GPIO(PTW6), + PINMUX_GPIO(PTW5), + PINMUX_GPIO(PTW4), + PINMUX_GPIO(PTW3), + PINMUX_GPIO(PTW2), + PINMUX_GPIO(PTW1), + PINMUX_GPIO(PTW0), /* PTX */ - PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), - PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), - PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), - PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), - PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), - PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), - PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), + PINMUX_GPIO(PTX6), + PINMUX_GPIO(PTX5), + PINMUX_GPIO(PTX4), + PINMUX_GPIO(PTX3), + PINMUX_GPIO(PTX2), + PINMUX_GPIO(PTX1), + PINMUX_GPIO(PTX0), /* PTY */ - PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), - PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), - PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), - PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), - PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), - PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), + PINMUX_GPIO(PTY5), + PINMUX_GPIO(PTY4), + PINMUX_GPIO(PTY3), + PINMUX_GPIO(PTY2), + PINMUX_GPIO(PTY1), + PINMUX_GPIO(PTY0), /* PTZ */ - PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), - PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), - PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), - PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), - PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), + PINMUX_GPIO(PTZ5), + PINMUX_GPIO(PTZ4), + PINMUX_GPIO(PTZ3), + PINMUX_GPIO(PTZ2), + PINMUX_GPIO(PTZ1), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + GPIO_FN(SCIF0_TXD), + GPIO_FN(SCIF0_RXD), + GPIO_FN(SCIF0_RTS), + GPIO_FN(SCIF0_CTS), + GPIO_FN(SCIF0_SCK), /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + GPIO_FN(SCIF1_TXD), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_RTS), + GPIO_FN(SCIF1_CTS), + GPIO_FN(SCIF1_SCK), /* SCIF2 */ - PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), + GPIO_FN(SCIF2_TXD), + GPIO_FN(SCIF2_RXD), + GPIO_FN(SCIF2_RTS), + GPIO_FN(SCIF2_CTS), + GPIO_FN(SCIF2_SCK), /* SIO */ - PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK), - PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK), - PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK), - PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK), - PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK), + GPIO_FN(SIOTXD), + GPIO_FN(SIORXD), + GPIO_FN(SIOD), + GPIO_FN(SIOSTRB0), + GPIO_FN(SIOSTRB1), + GPIO_FN(SIOSCK), + GPIO_FN(SIOMCK), /* CEU */ - PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), - PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK), - PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), + GPIO_FN(VIO_D15), + GPIO_FN(VIO_D14), + GPIO_FN(VIO_D13), + GPIO_FN(VIO_D12), + GPIO_FN(VIO_D11), + GPIO_FN(VIO_D10), + GPIO_FN(VIO_D9), + GPIO_FN(VIO_D8), + GPIO_FN(VIO_D7), + GPIO_FN(VIO_D6), + GPIO_FN(VIO_D5), + GPIO_FN(VIO_D4), + GPIO_FN(VIO_D3), + GPIO_FN(VIO_D2), + GPIO_FN(VIO_D1), + GPIO_FN(VIO_D0), + GPIO_FN(VIO_CLK), + GPIO_FN(VIO_VD), + GPIO_FN(VIO_HD), + GPIO_FN(VIO_FLD), + GPIO_FN(VIO_CKO), + GPIO_FN(VIO_STEX), + GPIO_FN(VIO_STEM), + GPIO_FN(VIO_VD2), + GPIO_FN(VIO_HD2), + GPIO_FN(VIO_CLK2), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), - PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), - PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), - PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), - PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), - PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), - PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), - PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), - PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), - PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), - PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), - PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), - PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), - PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), - PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), - PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), - PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), - PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), - PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), - PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), - PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), - PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), - PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), - PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), + GPIO_FN(LCDD23), + GPIO_FN(LCDD22), + GPIO_FN(LCDD21), + GPIO_FN(LCDD20), + GPIO_FN(LCDD19), + GPIO_FN(LCDD18), + GPIO_FN(LCDD17), + GPIO_FN(LCDD16), + GPIO_FN(LCDD15), + GPIO_FN(LCDD14), + GPIO_FN(LCDD13), + GPIO_FN(LCDD12), + GPIO_FN(LCDD11), + GPIO_FN(LCDD10), + GPIO_FN(LCDD9), + GPIO_FN(LCDD8), + GPIO_FN(LCDD7), + GPIO_FN(LCDD6), + GPIO_FN(LCDD5), + GPIO_FN(LCDD4), + GPIO_FN(LCDD3), + GPIO_FN(LCDD2), + GPIO_FN(LCDD1), + GPIO_FN(LCDD0), + GPIO_FN(LCDLCLK), /* Main LCD */ - PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), + GPIO_FN(LCDDON), + GPIO_FN(LCDVCPWC), + GPIO_FN(LCDVEPWC), + GPIO_FN(LCDVSYN), /* Main LCD - RGB Mode */ - PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), - PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), + GPIO_FN(LCDDCK), + GPIO_FN(LCDHSYN), + GPIO_FN(LCDDISP), /* Main LCD - SYS Mode */ - PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), - PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), - PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), + GPIO_FN(LCDRS), + GPIO_FN(LCDCS), + GPIO_FN(LCDWR), + GPIO_FN(LCDRD), /* Sub LCD - SYS Mode */ - PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK), + GPIO_FN(LCDDON2), + GPIO_FN(LCDVCPWC2), + GPIO_FN(LCDVEPWC2), + GPIO_FN(LCDVSYN2), + GPIO_FN(LCDCS2), /* BSC */ - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), + GPIO_FN(IOIS16), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(BS), + GPIO_FN(CS6B_CE1B), + GPIO_FN(WAIT), + GPIO_FN(CS6A_CE2B), /* SBSC */ - PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK), - PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK), - PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK), - PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK), - PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK), - PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK), - PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK), - PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK), - PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK), - PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK), - PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK), - PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK), - PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK), - PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK), - PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK), - PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK), - PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK), + GPIO_FN(HPD63), + GPIO_FN(HPD62), + GPIO_FN(HPD61), + GPIO_FN(HPD60), + GPIO_FN(HPD59), + GPIO_FN(HPD58), + GPIO_FN(HPD57), + GPIO_FN(HPD56), + GPIO_FN(HPD55), + GPIO_FN(HPD54), + GPIO_FN(HPD53), + GPIO_FN(HPD52), + GPIO_FN(HPD51), + GPIO_FN(HPD50), + GPIO_FN(HPD49), + GPIO_FN(HPD48), + GPIO_FN(HPDQM7), + GPIO_FN(HPDQM6), + GPIO_FN(HPDQM5), + GPIO_FN(HPDQM4), /* IRQ */ - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), + GPIO_FN(IRQ0), + GPIO_FN(IRQ1), + GPIO_FN(IRQ2), + GPIO_FN(IRQ3), + GPIO_FN(IRQ4), + GPIO_FN(IRQ5), + GPIO_FN(IRQ6), + GPIO_FN(IRQ7), /* SDHI */ - PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK), - PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK), - PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK), - PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK), - PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK), - PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK), - PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK), + GPIO_FN(SDHICD), + GPIO_FN(SDHIWP), + GPIO_FN(SDHID3), + GPIO_FN(SDHID2), + GPIO_FN(SDHID1), + GPIO_FN(SDHID0), + GPIO_FN(SDHICMD), + GPIO_FN(SDHICLK), /* SIU - Port A */ - PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK), - PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK), + GPIO_FN(SIUAOLR), + GPIO_FN(SIUAOBT), + GPIO_FN(SIUAISLD), + GPIO_FN(SIUAILR), + GPIO_FN(SIUAIBT), + GPIO_FN(SIUAOSLD), + GPIO_FN(SIUMCKA), + GPIO_FN(SIUFCKA), /* SIU - Port B */ - PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK), - PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK), + GPIO_FN(SIUBOLR), + GPIO_FN(SIUBOBT), + GPIO_FN(SIUBISLD), + GPIO_FN(SIUBILR), + GPIO_FN(SIUBIBT), + GPIO_FN(SIUBOSLD), + GPIO_FN(SIUMCKB), + GPIO_FN(SIUFCKB), /* AUD */ - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + GPIO_FN(AUDSYNC), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), /* DMAC */ - PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + GPIO_FN(DACK), + GPIO_FN(DREQ0), /* VOU */ - PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), - PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), - PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), - PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), - PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), - PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), - PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), - PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), - PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), - PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), - PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), - PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), - PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), - PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), - PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), - PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), + GPIO_FN(DV_CLKI), + GPIO_FN(DV_CLK), + GPIO_FN(DV_HSYNC), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_D15), + GPIO_FN(DV_D14), + GPIO_FN(DV_D13), + GPIO_FN(DV_D12), + GPIO_FN(DV_D11), + GPIO_FN(DV_D10), + GPIO_FN(DV_D9), + GPIO_FN(DV_D8), + GPIO_FN(DV_D7), + GPIO_FN(DV_D6), + GPIO_FN(DV_D5), + GPIO_FN(DV_D4), + GPIO_FN(DV_D3), + GPIO_FN(DV_D2), + GPIO_FN(DV_D1), + GPIO_FN(DV_D0), /* CPG */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), + GPIO_FN(STATUS0), + GPIO_FN(PDSTATUS), /* SIOF0 */ - PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), + GPIO_FN(SIOF0_MCK), + GPIO_FN(SIOF0_SCK), + GPIO_FN(SIOF0_SYNC), + GPIO_FN(SIOF0_SS1), + GPIO_FN(SIOF0_SS2), + GPIO_FN(SIOF0_TXD), + GPIO_FN(SIOF0_RXD), /* SIOF1 */ - PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), + GPIO_FN(SIOF1_MCK), + GPIO_FN(SIOF1_SCK), + GPIO_FN(SIOF1_SYNC), + GPIO_FN(SIOF1_SS1), + GPIO_FN(SIOF1_SS2), + GPIO_FN(SIOF1_TXD), + GPIO_FN(SIOF1_RXD), /* SIM */ - PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), - PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), + GPIO_FN(SIM_D), + GPIO_FN(SIM_CLK), + GPIO_FN(SIM_RST), /* TSIF */ - PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK), - PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK), - PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK), - PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK), + GPIO_FN(TS_SDAT), + GPIO_FN(TS_SCK), + GPIO_FN(TS_SDEN), + GPIO_FN(TS_SPSYNC), /* IRDA */ - PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), - PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), + GPIO_FN(IRDA_IN), + GPIO_FN(IRDA_OUT), /* TPU */ - PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK), + GPIO_FN(TPUTO), /* FLCTL */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), - PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), - PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), - PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), - PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), - PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), - PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), - PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), - PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), - PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), - PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + GPIO_FN(FCE), + GPIO_FN(NAF7), + GPIO_FN(NAF6), + GPIO_FN(NAF5), + GPIO_FN(NAF4), + GPIO_FN(NAF3), + GPIO_FN(NAF2), + GPIO_FN(NAF1), + GPIO_FN(NAF0), + GPIO_FN(FCDE), + GPIO_FN(FOE), + GPIO_FN(FSC), + GPIO_FN(FWE), + GPIO_FN(FRB), /* KEYSC */ - PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), + GPIO_FN(KEYIN0), + GPIO_FN(KEYIN1), + GPIO_FN(KEYIN2), + GPIO_FN(KEYIN3), + GPIO_FN(KEYIN4), + GPIO_FN(KEYOUT0), + GPIO_FN(KEYOUT1), + GPIO_FN(KEYOUT2), + GPIO_FN(KEYOUT3), + GPIO_FN(KEYOUT4_IN6), + GPIO_FN(KEYOUT5_IN5), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { - VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN, - VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN, - VIO_D5_SCIF1_TXD, PTA5_OUT, PTA5_IN_PD, PTA5_IN, - VIO_D4, 0, PTA4_IN_PD, PTA4_IN, - VIO_D3, 0, PTA3_IN_PD, PTA3_IN, - VIO_D2, 0, PTA2_IN_PD, PTA2_IN, - VIO_D1, 0, PTA1_IN_PD, PTA1_IN, - VIO_D0_LCDLCLK, 0, PTA0_IN_PD, PTA0_IN } + VIO_D7_SCIF1_SCK, PTA7_OUT, 0, PTA7_IN, + VIO_D6_SCIF1_RXD, 0, 0, PTA6_IN, + VIO_D5_SCIF1_TXD, PTA5_OUT, 0, PTA5_IN, + VIO_D4, 0, 0, PTA4_IN, + VIO_D3, 0, 0, PTA3_IN, + VIO_D2, 0, 0, PTA2_IN, + VIO_D1, 0, 0, PTA1_IN, + VIO_D0_LCDLCLK, 0, 0, PTA0_IN } }, { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { HPD55, PTB7_OUT, 0, PTB7_IN, @@ -1286,9 +1257,9 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { HPD48, PTB0_OUT, 0, PTB0_IN } }, { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { - 0, 0, PTC7_IN_PU, PTC7_IN, + 0, 0, 0, PTC7_IN, 0, 0, 0, 0, - IOIS16, 0, PTC5_IN_PU, PTC5_IN, + IOIS16, 0, 0, PTC5_IN, HPDQM7, PTC4_OUT, 0, PTC4_IN, HPDQM6, PTC3_OUT, 0, PTC3_IN, HPDQM5, PTC2_OUT, 0, PTC2_IN, @@ -1296,33 +1267,33 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { HPDQM4, PTC0_OUT, 0, PTC0_IN } }, { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { - SDHICD, 0, PTD7_IN_PU, PTD7_IN, - SDHIWP, PTD6_OUT, PTD6_IN_PU, PTD6_IN, - SDHID3, PTD5_OUT, PTD5_IN_PU, PTD5_IN, - IRQ2_SDHID2, PTD4_OUT, PTD4_IN_PU, PTD4_IN, - SDHID1, PTD3_OUT, PTD3_IN_PU, PTD3_IN, - SDHID0, PTD2_OUT, PTD2_IN_PU, PTD2_IN, - SDHICMD, PTD1_OUT, PTD1_IN_PU, PTD1_IN, + SDHICD, 0, 0, PTD7_IN, + SDHIWP, PTD6_OUT, 0, PTD6_IN, + SDHID3, PTD5_OUT, 0, PTD5_IN, + IRQ2_SDHID2, PTD4_OUT, 0, PTD4_IN, + SDHID1, PTD3_OUT, 0, PTD3_IN, + SDHID0, PTD2_OUT, 0, PTD2_IN, + SDHICMD, PTD1_OUT, 0, PTD1_IN, SDHICLK, PTD0_OUT, 0, 0 } }, { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { - A25, PTE7_OUT, PTE7_IN_PD, PTE7_IN, - A24, PTE6_OUT, PTE6_IN_PD, PTE6_IN, - A23, PTE5_OUT, PTE5_IN_PD, PTE5_IN, - A22, PTE4_OUT, PTE4_IN_PD, PTE4_IN, + A25, PTE7_OUT, 0, PTE7_IN, + A24, PTE6_OUT, 0, PTE6_IN, + A23, PTE5_OUT, 0, PTE5_IN, + A22, PTE4_OUT, 0, PTE4_IN, 0, 0, 0, 0, 0, 0, 0, 0, - IRQ5, PTE1_OUT, PTE1_IN_PD, PTE1_IN, - IRQ4_BS, PTE0_OUT, PTE0_IN_PD, PTE0_IN } + IRQ5, PTE1_OUT, 0, PTE1_IN, + IRQ4_BS, PTE0_OUT, 0, PTE0_IN } }, { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { 0, 0, 0, 0, - PTF6, PTF6_OUT, PTF6_IN_PD, PTF6_IN, - SIOSCK_SIUBOBT, PTF5_OUT, PTF5_IN_PD, PTF5_IN, - SIOSTRB1_SIUBOLR, PTF4_OUT, PTF4_IN_PD, PTF4_IN, - SIOSTRB0_SIUBIBT, PTF3_OUT, PTF3_IN_PD, PTF3_IN, - SIOD_SIUBILR, PTF2_OUT, PTF2_IN_PD, PTF2_IN, - SIORXD_SIUBISLD, 0, PTF1_IN_PD, PTF1_IN, + PTF6, PTF6_OUT, 0, PTF6_IN, + SIOSCK_SIUBOBT, PTF5_OUT, 0, PTF5_IN, + SIOSTRB1_SIUBOLR, PTF4_OUT, 0, PTF4_IN, + SIOSTRB0_SIUBIBT, PTF3_OUT, 0, PTF3_IN, + SIOD_SIUBILR, PTF2_OUT, 0, PTF2_IN, + SIORXD_SIUBISLD, 0, 0, PTF1_IN, SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 } }, { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { @@ -1337,13 +1308,13 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { }, { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0, - LCDVSYN2_DACK, PTH6_OUT, PTH6_IN_PD, PTH6_IN, - LCDVSYN, PTH5_OUT, PTH5_IN_PD, PTH5_IN, + LCDVSYN2_DACK, PTH6_OUT, 0, PTH6_IN, + LCDVSYN, PTH5_OUT, 0, PTH5_IN, LCDDISP_LCDRS, PTH4_OUT, 0, 0, LCDHSYN_LCDCS, PTH3_OUT, 0, 0, LCDDON_LCDDON2, PTH2_OUT, 0, 0, - LCDD17_DV_HSYNC, PTH1_OUT, PTH1_IN_PD, PTH1_IN, - LCDD16_DV_VSYNC, PTH0_OUT, PTH0_IN_PD, PTH0_IN } + LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN, + LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN } }, { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { STATUS0, PTJ7_OUT, 0, 0, @@ -1352,38 +1323,38 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - IRQ1, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, - IRQ0, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } + IRQ1, PTJ1_OUT, 0, PTJ1_IN, + IRQ0, PTJ0_OUT, 0, PTJ0_IN } }, { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { 0, 0, 0, 0, - SIUAILR_SIOF1_SS2, PTK6_OUT, PTK6_IN_PD, PTK6_IN, - SIUAIBT_SIOF1_SS1, PTK5_OUT, PTK5_IN_PD, PTK5_IN, - SIUAOLR_SIOF1_SYNC, PTK4_OUT, PTK4_IN_PD, PTK4_IN, - SIUAOBT_SIOF1_SCK, PTK3_OUT, PTK3_IN_PD, PTK3_IN, - SIUAISLD_SIOF1_RXD, 0, PTK2_IN_PD, PTK2_IN, + SIUAILR_SIOF1_SS2, PTK6_OUT, 0, PTK6_IN, + SIUAIBT_SIOF1_SS1, PTK5_OUT, 0, PTK5_IN, + SIUAOLR_SIOF1_SYNC, PTK4_OUT, 0, PTK4_IN, + SIUAOBT_SIOF1_SCK, PTK3_OUT, 0, PTK3_IN, + SIUAISLD_SIOF1_RXD, 0, 0, PTK2_IN, SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0, - PTK0, PTK0_OUT, PTK0_IN_PD, PTK0_IN } + PTK0, PTK0_OUT, 0, PTK0_IN } }, { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { - LCDD15_DV_D15, PTL7_OUT, PTL7_IN_PD, PTL7_IN, - LCDD14_DV_D14, PTL6_OUT, PTL6_IN_PD, PTL6_IN, - LCDD13_DV_D13, PTL5_OUT, PTL5_IN_PD, PTL5_IN, - LCDD12_DV_D12, PTL4_OUT, PTL4_IN_PD, PTL4_IN, - LCDD11_DV_D11, PTL3_OUT, PTL3_IN_PD, PTL3_IN, - LCDD10_DV_D10, PTL2_OUT, PTL2_IN_PD, PTL2_IN, - LCDD9_DV_D9, PTL1_OUT, PTL1_IN_PD, PTL1_IN, - LCDD8_DV_D8, PTL0_OUT, PTL0_IN_PD, PTL0_IN } + LCDD15_DV_D15, PTL7_OUT, 0, PTL7_IN, + LCDD14_DV_D14, PTL6_OUT, 0, PTL6_IN, + LCDD13_DV_D13, PTL5_OUT, 0, PTL5_IN, + LCDD12_DV_D12, PTL4_OUT, 0, PTL4_IN, + LCDD11_DV_D11, PTL3_OUT, 0, PTL3_IN, + LCDD10_DV_D10, PTL2_OUT, 0, PTL2_IN, + LCDD9_DV_D9, PTL1_OUT, 0, PTL1_IN, + LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN } }, { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { - LCDD7_DV_D7, PTM7_OUT, PTM7_IN_PD, PTM7_IN, - LCDD6_DV_D6, PTM6_OUT, PTM6_IN_PD, PTM6_IN, - LCDD5_DV_D5, PTM5_OUT, PTM5_IN_PD, PTM5_IN, - LCDD4_DV_D4, PTM4_OUT, PTM4_IN_PD, PTM4_IN, - LCDD3_DV_D3, PTM3_OUT, PTM3_IN_PD, PTM3_IN, - LCDD2_DV_D2, PTM2_OUT, PTM2_IN_PD, PTM2_IN, - LCDD1_DV_D1, PTM1_OUT, PTM1_IN_PD, PTM1_IN, - LCDD0_DV_D0, PTM0_OUT, PTM0_IN_PD, PTM0_IN } + LCDD7_DV_D7, PTM7_OUT, 0, PTM7_IN, + LCDD6_DV_D6, PTM6_OUT, 0, PTM6_IN, + LCDD5_DV_D5, PTM5_OUT, 0, PTM5_IN, + LCDD4_DV_D4, PTM4_OUT, 0, PTM4_IN, + LCDD3_DV_D3, PTM3_OUT, 0, PTM3_IN, + LCDD2_DV_D2, PTM2_OUT, 0, PTM2_IN, + LCDD1_DV_D1, PTM1_OUT, 0, PTM1_IN, + LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN } }, { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { HPD63, PTN7_OUT, 0, PTN7_IN, @@ -1398,12 +1369,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { 0, 0, 0, 0, SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0, - SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, PTQ5_IN_PD, PTQ5_IN, - SIOF0_SYNC_TS_SDEN, PTQ4_OUT, PTQ4_IN_PD, PTQ4_IN, - SIOF0_SCK_TS_SCK, PTQ3_OUT, PTQ3_IN_PD, PTQ3_IN, - PTQ2, 0, PTQ2_IN_PD, PTQ2_IN, + SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, 0, PTQ5_IN, + SIOF0_SYNC_TS_SDEN, PTQ4_OUT, 0, PTQ4_IN, + SIOF0_SCK_TS_SCK, PTQ3_OUT, 0, PTQ3_IN, + PTQ2, 0, 0, PTQ2_IN, PTQ1, PTQ1_OUT, 0, 0, - PTQ0, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN } + PTQ0, PTQ0_OUT, 0, PTQ0_IN } }, { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { 0, 0, 0, 0, @@ -1411,7 +1382,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, LCDRD, PTR4_OUT, 0, 0, CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0, - WAIT, 0, PTR2_IN_PU, PTR2_IN, + WAIT, 0, 0, PTR2_IN, LCDDCK_LCDWR, PTR1_OUT, 0, 0, LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 } }, @@ -1419,80 +1390,80 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - SCIF0_CTS_SIUAISPD, 0, PTS4_IN_PD, PTS4_IN, + SCIF0_CTS_SIUAISPD, 0, 0, PTS4_IN, SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0, - SCIF0_SCK_TPUTO, PTS2_OUT, PTS2_IN_PD, PTS2_IN, - SCIF0_RXD, 0, PTS1_IN_PD, PTS1_IN, + SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN, + SCIF0_RXD, 0, 0, PTS1_IN, SCIF0_TXD, PTS0_OUT, 0, 0 } }, { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - FOE_VIO_VD2, PTT4_OUT, PTT4_IN_PD, PTT4_IN, - FWE, PTT3_OUT, PTT3_IN_PD, PTT3_IN, - FSC, PTT2_OUT, PTT2_IN_PD, PTT2_IN, - DREQ0, 0, PTT1_IN_PD, PTT1_IN, + FOE_VIO_VD2, PTT4_OUT, 0, PTT4_IN, + FWE, PTT3_OUT, 0, PTT3_IN, + FSC, PTT2_OUT, 0, PTT2_IN, + DREQ0, 0, 0, PTT1_IN, FCDE, PTT0_OUT, 0, 0 } }, { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - NAF2_VIO_D10, PTU4_OUT, PTU4_IN_PD, PTU4_IN, - NAF1_VIO_D9, PTU3_OUT, PTU3_IN_PD, PTU3_IN, - NAF0_VIO_D8, PTU2_OUT, PTU2_IN_PD, PTU2_IN, - FRB_VIO_CLK2, 0, PTU1_IN_PD, PTU1_IN, - FCE_VIO_HD2, PTU0_OUT, PTU0_IN_PD, PTU0_IN } + NAF2_VIO_D10, PTU4_OUT, 0, PTU4_IN, + NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN, + NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN, + FRB_VIO_CLK2, 0, 0, PTU1_IN, + FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN } }, { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - NAF7_VIO_D15, PTV4_OUT, PTV4_IN_PD, PTV4_IN, - NAF6_VIO_D14, PTV3_OUT, PTV3_IN_PD, PTV3_IN, - NAF5_VIO_D13, PTV2_OUT, PTV2_IN_PD, PTV2_IN, - NAF4_VIO_D12, PTV1_OUT, PTV1_IN_PD, PTV1_IN, - NAF3_VIO_D11, PTV0_OUT, PTV0_IN_PD, PTV0_IN } + NAF7_VIO_D15, PTV4_OUT, 0, PTV4_IN, + NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN, + NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN, + NAF4_VIO_D12, PTV1_OUT, 0, PTV1_IN, + NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN } }, { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { 0, 0, 0, 0, - VIO_FLD_SCIF2_CTS, 0, PTW6_IN_PD, PTW6_IN, + VIO_FLD_SCIF2_CTS, 0, 0, PTW6_IN, VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0, - VIO_STEX_SCIF2_SCK, PTW4_OUT, PTW4_IN_PD, PTW4_IN, - VIO_STEM_SCIF2_TXD, PTW3_OUT, PTW3_IN_PD, PTW3_IN, - VIO_HD_SCIF2_RXD, PTW2_OUT, PTW2_IN_PD, PTW2_IN, - VIO_VD_SCIF1_CTS, PTW1_OUT, PTW1_IN_PD, PTW1_IN, - VIO_CLK_SCIF1_RTS, PTW0_OUT, PTW0_IN_PD, PTW0_IN } + VIO_STEX_SCIF2_SCK, PTW4_OUT, 0, PTW4_IN, + VIO_STEM_SCIF2_TXD, PTW3_OUT, 0, PTW3_IN, + VIO_HD_SCIF2_RXD, PTW2_OUT, 0, PTW2_IN, + VIO_VD_SCIF1_CTS, PTW1_OUT, 0, PTW1_IN, + VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN } }, { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { 0, 0, 0, 0, - CS6A_CE2B, PTX6_OUT, PTX6_IN_PU, PTX6_IN, - LCDD23, PTX5_OUT, PTX5_IN_PD, PTX5_IN, - LCDD22, PTX4_OUT, PTX4_IN_PD, PTX4_IN, - LCDD21, PTX3_OUT, PTX3_IN_PD, PTX3_IN, - LCDD20, PTX2_OUT, PTX2_IN_PD, PTX2_IN, - LCDD19_DV_CLKI, PTX1_OUT, PTX1_IN_PD, PTX1_IN, - LCDD18_DV_CLK, PTX0_OUT, PTX0_IN_PD, PTX0_IN } + CS6A_CE2B, PTX6_OUT, 0, PTX6_IN, + LCDD23, PTX5_OUT, 0, PTX5_IN, + LCDD22, PTX4_OUT, 0, PTX4_IN, + LCDD21, PTX3_OUT, 0, PTX3_IN, + LCDD20, PTX2_OUT, 0, PTX2_IN, + LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN, + LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN } }, { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, - KEYOUT5_IN5, PTY5_OUT, PTY5_IN_PU, PTY5_IN, - KEYOUT4_IN6, PTY4_OUT, PTY4_IN_PU, PTY4_IN, - KEYOUT3, PTY3_OUT, PTY3_IN_PU, PTY3_IN, - KEYOUT2, PTY2_OUT, PTY2_IN_PU, PTY2_IN, + KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN, + KEYOUT4_IN6, PTY4_OUT, 0, PTY4_IN, + KEYOUT3, PTY3_OUT, 0, PTY3_IN, + KEYOUT2, PTY2_OUT, 0, PTY2_IN, KEYOUT1, PTY1_OUT, 0, 0, - KEYOUT0, PTY0_OUT, PTY0_IN_PU, PTY0_IN } + KEYOUT0, PTY0_OUT, 0, PTY0_IN } }, { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, - KEYIN4_IRQ7, 0, PTZ5_IN_PU, PTZ5_IN, - KEYIN3, 0, PTZ4_IN_PU, PTZ4_IN, - KEYIN2, 0, PTZ3_IN_PU, PTZ3_IN, - KEYIN1, 0, PTZ2_IN_PU, PTZ2_IN, - KEYIN0_IRQ6, 0, PTZ1_IN_PU, PTZ1_IN, + KEYIN4_IRQ7, 0, 0, PTZ5_IN, + KEYIN3, 0, 0, PTZ4_IN, + KEYIN2, 0, 0, PTZ3_IN, + KEYIN1, 0, 0, PTZ2_IN, + KEYIN0_IRQ6, 0, 0, PTZ1_IN, 0, 0, 0, 0 } }, { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { @@ -1660,7 +1631,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -1756,21 +1727,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7722_pinmux_info = { +const struct sh_pfc_soc_info sh7722_pinmux_info = { .name = "sh7722_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_KEYOUT5_IN5, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index 609673d3d70..4eb7eae2e6d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -102,12 +102,6 @@ enum { PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, PINMUX_INPUT_END, - PINMUX_INPUT_PULLUP_BEGIN, - PTA4_IN_PU, PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, - PTB2_IN_PU, PTB1_IN_PU, - PTR2_IN_PU, - PINMUX_INPUT_PULLUP_END, - PINMUX_OUTPUT_BEGIN, PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, @@ -350,16 +344,16 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const u16 pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), - PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), - PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), - PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), - PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), - PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), + PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT), + PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT), + PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT), + PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT), + PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT), /* PTB GPIO */ PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), @@ -367,8 +361,8 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), - PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), - PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), + PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), + PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), /* PTC GPIO */ @@ -487,7 +481,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT), PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT), PINMUX_DATA(PTR3_DATA, PTR3_IN), - PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), + PINMUX_DATA(PTR2_DATA, PTR2_IN), PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT), PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT), @@ -923,604 +917,608 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ - PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), - PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), - PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), - PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), - PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), - PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), - PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), - PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), + PINMUX_GPIO(PTA7), + PINMUX_GPIO(PTA6), + PINMUX_GPIO(PTA5), + PINMUX_GPIO(PTA4), + PINMUX_GPIO(PTA3), + PINMUX_GPIO(PTA2), + PINMUX_GPIO(PTA1), + PINMUX_GPIO(PTA0), /* PTB */ - PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), - PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), - PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), - PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), - PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), - PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), - PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), - PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), + PINMUX_GPIO(PTB7), + PINMUX_GPIO(PTB6), + PINMUX_GPIO(PTB5), + PINMUX_GPIO(PTB4), + PINMUX_GPIO(PTB3), + PINMUX_GPIO(PTB2), + PINMUX_GPIO(PTB1), + PINMUX_GPIO(PTB0), /* PTC */ - PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), - PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), - PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), - PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), - PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), - PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), - PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), - PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), + PINMUX_GPIO(PTC7), + PINMUX_GPIO(PTC6), + PINMUX_GPIO(PTC5), + PINMUX_GPIO(PTC4), + PINMUX_GPIO(PTC3), + PINMUX_GPIO(PTC2), + PINMUX_GPIO(PTC1), + PINMUX_GPIO(PTC0), /* PTD */ - PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), - PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), - PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), - PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), - PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), - PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), - PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), - PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), + PINMUX_GPIO(PTD7), + PINMUX_GPIO(PTD6), + PINMUX_GPIO(PTD5), + PINMUX_GPIO(PTD4), + PINMUX_GPIO(PTD3), + PINMUX_GPIO(PTD2), + PINMUX_GPIO(PTD1), + PINMUX_GPIO(PTD0), /* PTE */ - PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), - PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), - PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), - PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), - PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), - PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), + PINMUX_GPIO(PTE5), + PINMUX_GPIO(PTE4), + PINMUX_GPIO(PTE3), + PINMUX_GPIO(PTE2), + PINMUX_GPIO(PTE1), + PINMUX_GPIO(PTE0), /* PTF */ - PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), - PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), - PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), - PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), - PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), - PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), - PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), - PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), + PINMUX_GPIO(PTF7), + PINMUX_GPIO(PTF6), + PINMUX_GPIO(PTF5), + PINMUX_GPIO(PTF4), + PINMUX_GPIO(PTF3), + PINMUX_GPIO(PTF2), + PINMUX_GPIO(PTF1), + PINMUX_GPIO(PTF0), /* PTG */ - PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), - PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), - PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), - PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), - PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), - PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), + PINMUX_GPIO(PTG5), + PINMUX_GPIO(PTG4), + PINMUX_GPIO(PTG3), + PINMUX_GPIO(PTG2), + PINMUX_GPIO(PTG1), + PINMUX_GPIO(PTG0), /* PTH */ - PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), - PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), - PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), - PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), - PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), - PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), - PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), - PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), + PINMUX_GPIO(PTH7), + PINMUX_GPIO(PTH6), + PINMUX_GPIO(PTH5), + PINMUX_GPIO(PTH4), + PINMUX_GPIO(PTH3), + PINMUX_GPIO(PTH2), + PINMUX_GPIO(PTH1), + PINMUX_GPIO(PTH0), /* PTJ */ - PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), - PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), - PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), - PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), - PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), - PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), + PINMUX_GPIO(PTJ7), + PINMUX_GPIO(PTJ5), + PINMUX_GPIO(PTJ3), + PINMUX_GPIO(PTJ2), + PINMUX_GPIO(PTJ1), + PINMUX_GPIO(PTJ0), /* PTK */ - PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), - PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), - PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), - PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), - PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), - PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), - PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), - PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), + PINMUX_GPIO(PTK7), + PINMUX_GPIO(PTK6), + PINMUX_GPIO(PTK5), + PINMUX_GPIO(PTK4), + PINMUX_GPIO(PTK3), + PINMUX_GPIO(PTK2), + PINMUX_GPIO(PTK1), + PINMUX_GPIO(PTK0), /* PTL */ - PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), - PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), - PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), - PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), - PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), - PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), - PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), - PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), + PINMUX_GPIO(PTL7), + PINMUX_GPIO(PTL6), + PINMUX_GPIO(PTL5), + PINMUX_GPIO(PTL4), + PINMUX_GPIO(PTL3), + PINMUX_GPIO(PTL2), + PINMUX_GPIO(PTL1), + PINMUX_GPIO(PTL0), /* PTM */ - PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), - PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), - PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), - PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), - PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), - PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), - PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), - PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), + PINMUX_GPIO(PTM7), + PINMUX_GPIO(PTM6), + PINMUX_GPIO(PTM5), + PINMUX_GPIO(PTM4), + PINMUX_GPIO(PTM3), + PINMUX_GPIO(PTM2), + PINMUX_GPIO(PTM1), + PINMUX_GPIO(PTM0), /* PTN */ - PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), - PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), - PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), - PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), - PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), - PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), - PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), - PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), + PINMUX_GPIO(PTN7), + PINMUX_GPIO(PTN6), + PINMUX_GPIO(PTN5), + PINMUX_GPIO(PTN4), + PINMUX_GPIO(PTN3), + PINMUX_GPIO(PTN2), + PINMUX_GPIO(PTN1), + PINMUX_GPIO(PTN0), /* PTQ */ - PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), - PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), - PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), - PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), + PINMUX_GPIO(PTQ3), + PINMUX_GPIO(PTQ2), + PINMUX_GPIO(PTQ1), + PINMUX_GPIO(PTQ0), /* PTR */ - PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), - PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), - PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), - PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), - PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), - PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), - PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), - PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), + PINMUX_GPIO(PTR7), + PINMUX_GPIO(PTR6), + PINMUX_GPIO(PTR5), + PINMUX_GPIO(PTR4), + PINMUX_GPIO(PTR3), + PINMUX_GPIO(PTR2), + PINMUX_GPIO(PTR1), + PINMUX_GPIO(PTR0), /* PTS */ - PINMUX_GPIO(GPIO_PTS7, PTS7_DATA), - PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), - PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), - PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), - PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), - PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), - PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), - PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), + PINMUX_GPIO(PTS7), + PINMUX_GPIO(PTS6), + PINMUX_GPIO(PTS5), + PINMUX_GPIO(PTS4), + PINMUX_GPIO(PTS3), + PINMUX_GPIO(PTS2), + PINMUX_GPIO(PTS1), + PINMUX_GPIO(PTS0), /* PTT */ - PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), - PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), - PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), - PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), - PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), - PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), + PINMUX_GPIO(PTT5), + PINMUX_GPIO(PTT4), + PINMUX_GPIO(PTT3), + PINMUX_GPIO(PTT2), + PINMUX_GPIO(PTT1), + PINMUX_GPIO(PTT0), /* PTU */ - PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), - PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), - PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), - PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), - PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), - PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), + PINMUX_GPIO(PTU5), + PINMUX_GPIO(PTU4), + PINMUX_GPIO(PTU3), + PINMUX_GPIO(PTU2), + PINMUX_GPIO(PTU1), + PINMUX_GPIO(PTU0), /* PTV */ - PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), - PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), - PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), - PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), - PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), - PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), - PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), - PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), + PINMUX_GPIO(PTV7), + PINMUX_GPIO(PTV6), + PINMUX_GPIO(PTV5), + PINMUX_GPIO(PTV4), + PINMUX_GPIO(PTV3), + PINMUX_GPIO(PTV2), + PINMUX_GPIO(PTV1), + PINMUX_GPIO(PTV0), /* PTW */ - PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), - PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), - PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), - PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), - PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), - PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), - PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), - PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), + PINMUX_GPIO(PTW7), + PINMUX_GPIO(PTW6), + PINMUX_GPIO(PTW5), + PINMUX_GPIO(PTW4), + PINMUX_GPIO(PTW3), + PINMUX_GPIO(PTW2), + PINMUX_GPIO(PTW1), + PINMUX_GPIO(PTW0), /* PTX */ - PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), - PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), - PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), - PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), - PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), - PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), - PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), - PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), + PINMUX_GPIO(PTX7), + PINMUX_GPIO(PTX6), + PINMUX_GPIO(PTX5), + PINMUX_GPIO(PTX4), + PINMUX_GPIO(PTX3), + PINMUX_GPIO(PTX2), + PINMUX_GPIO(PTX1), + PINMUX_GPIO(PTX0), /* PTY */ - PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), - PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), - PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), - PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), - PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), - PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), - PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), - PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), + PINMUX_GPIO(PTY7), + PINMUX_GPIO(PTY6), + PINMUX_GPIO(PTY5), + PINMUX_GPIO(PTY4), + PINMUX_GPIO(PTY3), + PINMUX_GPIO(PTY2), + PINMUX_GPIO(PTY1), + PINMUX_GPIO(PTY0), /* PTZ */ - PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), - PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), - PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), - PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), - PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), - PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), - PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), - PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), + PINMUX_GPIO(PTZ7), + PINMUX_GPIO(PTZ6), + PINMUX_GPIO(PTZ5), + PINMUX_GPIO(PTZ4), + PINMUX_GPIO(PTZ3), + PINMUX_GPIO(PTZ2), + PINMUX_GPIO(PTZ1), + PINMUX_GPIO(PTZ0), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK), + GPIO_FN(SCIF0_PTT_TXD), + GPIO_FN(SCIF0_PTT_RXD), + GPIO_FN(SCIF0_PTT_SCK), + GPIO_FN(SCIF0_PTU_TXD), + GPIO_FN(SCIF0_PTU_RXD), + GPIO_FN(SCIF0_PTU_SCK), /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK), + GPIO_FN(SCIF1_PTS_TXD), + GPIO_FN(SCIF1_PTS_RXD), + GPIO_FN(SCIF1_PTS_SCK), + GPIO_FN(SCIF1_PTV_TXD), + GPIO_FN(SCIF1_PTV_RXD), + GPIO_FN(SCIF1_PTV_SCK), /* SCIF2 */ - PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK), + GPIO_FN(SCIF2_PTT_TXD), + GPIO_FN(SCIF2_PTT_RXD), + GPIO_FN(SCIF2_PTT_SCK), + GPIO_FN(SCIF2_PTU_TXD), + GPIO_FN(SCIF2_PTU_RXD), + GPIO_FN(SCIF2_PTU_SCK), /* SCIF3 */ - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK), + GPIO_FN(SCIF3_PTS_TXD), + GPIO_FN(SCIF3_PTS_RXD), + GPIO_FN(SCIF3_PTS_SCK), + GPIO_FN(SCIF3_PTS_RTS), + GPIO_FN(SCIF3_PTS_CTS), + GPIO_FN(SCIF3_PTV_TXD), + GPIO_FN(SCIF3_PTV_RXD), + GPIO_FN(SCIF3_PTV_SCK), + GPIO_FN(SCIF3_PTV_RTS), + GPIO_FN(SCIF3_PTV_CTS), /* SCIF4 */ - PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK), + GPIO_FN(SCIF4_PTE_TXD), + GPIO_FN(SCIF4_PTE_RXD), + GPIO_FN(SCIF4_PTE_SCK), + GPIO_FN(SCIF4_PTN_TXD), + GPIO_FN(SCIF4_PTN_RXD), + GPIO_FN(SCIF4_PTN_SCK), /* SCIF5 */ - PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK), + GPIO_FN(SCIF5_PTE_TXD), + GPIO_FN(SCIF5_PTE_RXD), + GPIO_FN(SCIF5_PTE_SCK), + GPIO_FN(SCIF5_PTN_TXD), + GPIO_FN(SCIF5_PTN_RXD), + GPIO_FN(SCIF5_PTN_SCK), /* CEU */ - PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK), - PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), - PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), - PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), + GPIO_FN(VIO_D15), + GPIO_FN(VIO_D14), + GPIO_FN(VIO_D13), + GPIO_FN(VIO_D12), + GPIO_FN(VIO_D11), + GPIO_FN(VIO_D10), + GPIO_FN(VIO_D9), + GPIO_FN(VIO_D8), + GPIO_FN(VIO_D7), + GPIO_FN(VIO_D6), + GPIO_FN(VIO_D5), + GPIO_FN(VIO_D4), + GPIO_FN(VIO_D3), + GPIO_FN(VIO_D2), + GPIO_FN(VIO_D1), + GPIO_FN(VIO_D0), + GPIO_FN(VIO_CLK1), + GPIO_FN(VIO_VD1), + GPIO_FN(VIO_HD1), + GPIO_FN(VIO_FLD), + GPIO_FN(VIO_CKO), + GPIO_FN(VIO_VD2), + GPIO_FN(VIO_HD2), + GPIO_FN(VIO_CLK2), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), - PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), - PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), - PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), - PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), - PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), - PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), - PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), - PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), - PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), - PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), - PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), - PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), - PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), - PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), - PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), - PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), - PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), - PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), - PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), - PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), - PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), - PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), - PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK), + GPIO_FN(LCDD23), + GPIO_FN(LCDD22), + GPIO_FN(LCDD21), + GPIO_FN(LCDD20), + GPIO_FN(LCDD19), + GPIO_FN(LCDD18), + GPIO_FN(LCDD17), + GPIO_FN(LCDD16), + GPIO_FN(LCDD15), + GPIO_FN(LCDD14), + GPIO_FN(LCDD13), + GPIO_FN(LCDD12), + GPIO_FN(LCDD11), + GPIO_FN(LCDD10), + GPIO_FN(LCDD9), + GPIO_FN(LCDD8), + GPIO_FN(LCDD7), + GPIO_FN(LCDD6), + GPIO_FN(LCDD5), + GPIO_FN(LCDD4), + GPIO_FN(LCDD3), + GPIO_FN(LCDD2), + GPIO_FN(LCDD1), + GPIO_FN(LCDD0), + GPIO_FN(LCDLCLK_PTR), + GPIO_FN(LCDLCLK_PTW), /* Main LCD */ - PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), + GPIO_FN(LCDDON), + GPIO_FN(LCDVCPWC), + GPIO_FN(LCDVEPWC), + GPIO_FN(LCDVSYN), /* Main LCD - RGB Mode */ - PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), - PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), + GPIO_FN(LCDDCK), + GPIO_FN(LCDHSYN), + GPIO_FN(LCDDISP), /* Main LCD - SYS Mode */ - PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), - PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), - PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), + GPIO_FN(LCDRS), + GPIO_FN(LCDCS), + GPIO_FN(LCDWR), + GPIO_FN(LCDRD), /* IRQ */ - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), + GPIO_FN(IRQ0), + GPIO_FN(IRQ1), + GPIO_FN(IRQ2), + GPIO_FN(IRQ3), + GPIO_FN(IRQ4), + GPIO_FN(IRQ5), + GPIO_FN(IRQ6), + GPIO_FN(IRQ7), /* AUD */ - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + GPIO_FN(AUDCK), + GPIO_FN(AUDSYNC), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), /* SDHI0 (PTD) */ - PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK), + GPIO_FN(SDHI0CD_PTD), + GPIO_FN(SDHI0WP_PTD), + GPIO_FN(SDHI0D3_PTD), + GPIO_FN(SDHI0D2_PTD), + GPIO_FN(SDHI0D1_PTD), + GPIO_FN(SDHI0D0_PTD), + GPIO_FN(SDHI0CMD_PTD), + GPIO_FN(SDHI0CLK_PTD), /* SDHI0 (PTS) */ - PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK), + GPIO_FN(SDHI0CD_PTS), + GPIO_FN(SDHI0WP_PTS), + GPIO_FN(SDHI0D3_PTS), + GPIO_FN(SDHI0D2_PTS), + GPIO_FN(SDHI0D1_PTS), + GPIO_FN(SDHI0D0_PTS), + GPIO_FN(SDHI0CMD_PTS), + GPIO_FN(SDHI0CLK_PTS), /* SDHI1 */ - PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), + GPIO_FN(SDHI1CD), + GPIO_FN(SDHI1WP), + GPIO_FN(SDHI1D3), + GPIO_FN(SDHI1D2), + GPIO_FN(SDHI1D1), + GPIO_FN(SDHI1D0), + GPIO_FN(SDHI1CMD), + GPIO_FN(SDHI1CLK), /* SIUA */ - PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK), - PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK), - PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK), - PINMUX_GPIO(GPIO_FN_SIUAOSPD, SIUAOSPD_MARK), + GPIO_FN(SIUAFCK), + GPIO_FN(SIUAILR), + GPIO_FN(SIUAIBT), + GPIO_FN(SIUAISLD), + GPIO_FN(SIUAOLR), + GPIO_FN(SIUAOBT), + GPIO_FN(SIUAOSLD), + GPIO_FN(SIUAMCK), + GPIO_FN(SIUAISPD), + GPIO_FN(SIUAOSPD), /* SIUB */ - PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK), - PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), - PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), - PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK), + GPIO_FN(SIUBFCK), + GPIO_FN(SIUBILR), + GPIO_FN(SIUBIBT), + GPIO_FN(SIUBISLD), + GPIO_FN(SIUBOLR), + GPIO_FN(SIUBOBT), + GPIO_FN(SIUBOSLD), + GPIO_FN(SIUBMCK), /* IRDA */ - PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), - PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), + GPIO_FN(IRDA_IN), + GPIO_FN(IRDA_OUT), /* VOU */ - PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), - PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), - PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), - PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), - PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), - PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), - PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), - PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), - PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), - PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), - PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), - PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), - PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), - PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), - PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), - PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), + GPIO_FN(DV_CLKI), + GPIO_FN(DV_CLK), + GPIO_FN(DV_HSYNC), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_D15), + GPIO_FN(DV_D14), + GPIO_FN(DV_D13), + GPIO_FN(DV_D12), + GPIO_FN(DV_D11), + GPIO_FN(DV_D10), + GPIO_FN(DV_D9), + GPIO_FN(DV_D8), + GPIO_FN(DV_D7), + GPIO_FN(DV_D6), + GPIO_FN(DV_D5), + GPIO_FN(DV_D4), + GPIO_FN(DV_D3), + GPIO_FN(DV_D2), + GPIO_FN(DV_D1), + GPIO_FN(DV_D0), /* KEYSC */ - PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), + GPIO_FN(KEYIN0), + GPIO_FN(KEYIN1), + GPIO_FN(KEYIN2), + GPIO_FN(KEYIN3), + GPIO_FN(KEYIN4), + GPIO_FN(KEYOUT0), + GPIO_FN(KEYOUT1), + GPIO_FN(KEYOUT2), + GPIO_FN(KEYOUT3), + GPIO_FN(KEYOUT4_IN6), + GPIO_FN(KEYOUT5_IN5), /* MSIOF0 (PTF) */ - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK), + GPIO_FN(MSIOF0_PTF_TXD), + GPIO_FN(MSIOF0_PTF_RXD), + GPIO_FN(MSIOF0_PTF_MCK), + GPIO_FN(MSIOF0_PTF_TSYNC), + GPIO_FN(MSIOF0_PTF_TSCK), + GPIO_FN(MSIOF0_PTF_RSYNC), + GPIO_FN(MSIOF0_PTF_RSCK), + GPIO_FN(MSIOF0_PTF_SS1), + GPIO_FN(MSIOF0_PTF_SS2), /* MSIOF0 (PTT+PTX) */ - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK), + GPIO_FN(MSIOF0_PTT_TXD), + GPIO_FN(MSIOF0_PTT_RXD), + GPIO_FN(MSIOF0_PTX_MCK), + GPIO_FN(MSIOF0_PTT_TSYNC), + GPIO_FN(MSIOF0_PTT_TSCK), + GPIO_FN(MSIOF0_PTT_RSYNC), + GPIO_FN(MSIOF0_PTT_RSCK), + GPIO_FN(MSIOF0_PTT_SS1), + GPIO_FN(MSIOF0_PTT_SS2), /* MSIOF1 */ - PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), + GPIO_FN(MSIOF1_TXD), + GPIO_FN(MSIOF1_RXD), + GPIO_FN(MSIOF1_MCK), + GPIO_FN(MSIOF1_TSYNC), + GPIO_FN(MSIOF1_TSCK), + GPIO_FN(MSIOF1_RSYNC), + GPIO_FN(MSIOF1_RSCK), + GPIO_FN(MSIOF1_SS1), + GPIO_FN(MSIOF1_SS2), /* TSIF */ - PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK), - PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK), - PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK), + GPIO_FN(TS0_SDAT), + GPIO_FN(TS0_SCK), + GPIO_FN(TS0_SDEN), + GPIO_FN(TS0_SPSYNC), /* FLCTL */ - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), - PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), - PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), - PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), - PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), - PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), - PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), - PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), - PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), - PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), - PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + GPIO_FN(FCE), + GPIO_FN(NAF7), + GPIO_FN(NAF6), + GPIO_FN(NAF5), + GPIO_FN(NAF4), + GPIO_FN(NAF3), + GPIO_FN(NAF2), + GPIO_FN(NAF1), + GPIO_FN(NAF0), + GPIO_FN(FCDE), + GPIO_FN(FOE), + GPIO_FN(FSC), + GPIO_FN(FWE), + GPIO_FN(FRB), /* DMAC */ - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + GPIO_FN(DACK1), + GPIO_FN(DREQ1), + GPIO_FN(DACK0), + GPIO_FN(DREQ0), /* ADC */ - PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), - PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), - PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), - PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + GPIO_FN(AN3), + GPIO_FN(AN2), + GPIO_FN(AN1), + GPIO_FN(AN0), + GPIO_FN(ADTRG), /* CPG */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), + GPIO_FN(STATUS0), + GPIO_FN(PDSTATUS), /* TPU */ - PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), + GPIO_FN(TPUTO0), + GPIO_FN(TPUTO1), + GPIO_FN(TPUTO2), + GPIO_FN(TPUTO3), /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), - PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), - PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(IOIS16), + GPIO_FN(WAIT), + GPIO_FN(BS), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(CS6B_CE1B), + GPIO_FN(CS6A_CE2B), + GPIO_FN(CS5B_CE1A), + GPIO_FN(CS5A_CE2A), + GPIO_FN(WE3_ICIOWR), + GPIO_FN(WE2_ICIORD), /* ATAPI */ - PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), - PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), - PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), - PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), - PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), - PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), - PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), - PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), - PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), - PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), - PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), - PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), - PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), - PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), - PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), - PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), - PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), - PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), - PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), - PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), - PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), - PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), - PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), - PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), - PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), - PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), - PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), - PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), + GPIO_FN(IDED15), + GPIO_FN(IDED14), + GPIO_FN(IDED13), + GPIO_FN(IDED12), + GPIO_FN(IDED11), + GPIO_FN(IDED10), + GPIO_FN(IDED9), + GPIO_FN(IDED8), + GPIO_FN(IDED7), + GPIO_FN(IDED6), + GPIO_FN(IDED5), + GPIO_FN(IDED4), + GPIO_FN(IDED3), + GPIO_FN(IDED2), + GPIO_FN(IDED1), + GPIO_FN(IDED0), + GPIO_FN(DIRECTION), + GPIO_FN(EXBUF_ENB), + GPIO_FN(IDERST), + GPIO_FN(IODACK), + GPIO_FN(IODREQ), + GPIO_FN(IDEIORDY), + GPIO_FN(IDEINT), + GPIO_FN(IDEIOWR), + GPIO_FN(IDEIORD), + GPIO_FN(IDECS1), + GPIO_FN(IDECS0), + GPIO_FN(IDEA2), + GPIO_FN(IDEA1), + GPIO_FN(IDEA0), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { PTA7_FN, PTA7_OUT, 0, PTA7_IN, PTA6_FN, PTA6_OUT, 0, PTA6_IN, PTA5_FN, PTA5_OUT, 0, PTA5_IN, - PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, - PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, - PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, - PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, - PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } + PTA4_FN, PTA4_OUT, 0, PTA4_IN, + PTA3_FN, PTA3_OUT, 0, PTA3_IN, + PTA2_FN, PTA2_OUT, 0, PTA2_IN, + PTA1_FN, PTA1_OUT, 0, PTA1_IN, + PTA0_FN, PTA0_OUT, 0, PTA0_IN } }, { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { PTB7_FN, PTB7_OUT, 0, PTB7_IN, @@ -1528,8 +1526,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTB5_FN, PTB5_OUT, 0, PTB5_IN, PTB4_FN, PTB4_OUT, 0, PTB4_IN, PTB3_FN, PTB3_OUT, 0, PTB3_IN, - PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, - PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, + PTB2_FN, PTB2_OUT, 0, PTB2_IN, + PTB1_FN, PTB1_OUT, 0, PTB1_IN, PTB0_FN, PTB0_OUT, 0, PTB0_IN } }, { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { @@ -1658,7 +1656,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTR5_FN, PTR5_OUT, 0, PTR5_IN, PTR4_FN, PTR4_OUT, 0, PTR4_IN, PTR3_FN, 0, 0, PTR3_IN, - PTR2_FN, 0, PTR2_IN_PU, PTR2_IN, + PTR2_FN, 0, 0, PTR2_IN, PTR1_FN, PTR1_OUT, 0, PTR1_IN, PTR0_FN, PTR0_OUT, 0, PTR0_IN } }, @@ -1785,7 +1783,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -1881,20 +1879,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7723_pinmux_info = { +const struct sh_pfc_soc_info sh7723_pinmux_info = { .name = "sh7723_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_IDEA0, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 233fbf750b3..74a1a7f1317 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -117,52 +117,6 @@ enum { PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, PINMUX_INPUT_END, - PINMUX_INPUT_PULLUP_BEGIN, - PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, - PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, - PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU, - PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU, - PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU, - PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU, - PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, - PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, - PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU, - PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, - PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU, - PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU, - PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, - PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, - PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, - PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU, - PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, - PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, - PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU, - PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, - PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU, - PTN7_IN_PU, PTN6_IN_PU, PTN5_IN_PU, PTN4_IN_PU, - PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU, - PTQ7_IN_PU, PTQ6_IN_PU, PTQ5_IN_PU, PTQ4_IN_PU, - PTQ3_IN_PU, PTQ2_IN_PU, PTQ1_IN_PU, PTQ0_IN_PU, - PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU, - PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU, - PTS6_IN_PU, PTS5_IN_PU, PTS4_IN_PU, - PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU, - PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU, - PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, - PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, - PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, - PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, - PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, - PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU, - PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU, - PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, - PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, - PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, - PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, - PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU, - PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU, - PINMUX_INPUT_PULLUP_END, - PINMUX_OUTPUT_BEGIN, PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, @@ -572,66 +526,66 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const u16 pinmux_data[] = { /* PTA GPIO */ - PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), - PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), - PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU), - PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), - PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), - PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), - PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), - PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), + PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), + PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT), + PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT), + PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT), + PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT), + PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT), /* PTB GPIO */ - PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU), - PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU), - PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU), - PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU), - PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU), - PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), - PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), - PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU), + PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), + PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), + PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), + PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), + PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), + PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), + PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), + PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), /* PTC GPIO */ - PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU), - PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU), - PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU), - PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU), - PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU), - PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU), - PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU), - PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU), + PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT), + PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT), + PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT), + PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), + PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), + PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), + PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT), + PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), /* PTD GPIO */ - PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU), - PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU), - PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU), - PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU), - PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU), - PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU), - PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU), - PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU), + PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT), + PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT), + PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT), + PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT), + PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT), + PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT), + PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT), + PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), /* PTE GPIO */ - PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT, PTE7_IN_PU), - PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT, PTE6_IN_PU), - PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT, PTE5_IN_PU), - PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU), - PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU), - PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU), - PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU), - PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU), + PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT), + PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT), + PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT), + PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), + PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), + PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT), + PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT), + PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT), /* PTF GPIO */ - PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT, PTF7_IN_PU), - PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT, PTF6_IN_PU), - PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT, PTF5_IN_PU), - PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT, PTF4_IN_PU), - PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT, PTF3_IN_PU), - PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT, PTF2_IN_PU), - PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT, PTF1_IN_PU), - PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU), + PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT), + PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT), + PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT), + PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT), + PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT), + PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT), + PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT), + PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT), /* PTG GPIO */ PINMUX_DATA(PTG5_DATA, PTG5_OUT), @@ -642,162 +596,162 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTG0_DATA, PTG0_OUT), /* PTH GPIO */ - PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT, PTH7_IN_PU), - PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU), - PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU), - PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU), - PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU), - PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU), - PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU), - PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU), + PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT), + PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT), + PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT), + PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT), + PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT), + PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT), + PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT), + PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT), /* PTJ GPIO */ PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), PINMUX_DATA(PTJ6_DATA, PTJ6_OUT), PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), - PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU), - PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU), - PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU), - PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU), + PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT), + PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT), + PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT), + PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT), /* PTK GPIO */ - PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT, PTK7_IN_PU), - PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT, PTK6_IN_PU), - PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT, PTK5_IN_PU), - PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT, PTK4_IN_PU), - PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU), - PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU), - PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU), - PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU), + PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT), + PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT), + PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT), + PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT), + PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT), + PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT), + PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT), + PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), /* PTL GPIO */ - PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU), - PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU), - PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU), - PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU), - PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU), - PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT, PTL2_IN_PU), - PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT, PTL1_IN_PU), - PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT, PTL0_IN_PU), + PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT), + PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), + PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), + PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), + PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT), + PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT), + PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT), + PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT), /* PTM GPIO */ - PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU), - PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU), - PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU), - PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU), - PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU), - PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU), - PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU), - PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU), + PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT), + PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT), + PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT), + PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT), + PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT), + PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT), + PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT), + PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), /* PTN GPIO */ - PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT, PTN7_IN_PU), - PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT, PTN6_IN_PU), - PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT, PTN5_IN_PU), - PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT, PTN4_IN_PU), - PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT, PTN3_IN_PU), - PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT, PTN2_IN_PU), - PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT, PTN1_IN_PU), - PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT, PTN0_IN_PU), + PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT), + PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT), + PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT), + PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT), + PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT), + PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT), + PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT), + PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT), /* PTQ GPIO */ - PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT, PTQ7_IN_PU), - PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT, PTQ6_IN_PU), - PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT, PTQ5_IN_PU), - PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT, PTQ4_IN_PU), - PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT, PTQ3_IN_PU), - PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT, PTQ2_IN_PU), - PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT, PTQ1_IN_PU), - PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT, PTQ0_IN_PU), + PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT), + PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT), + PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT), + PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT), + PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT), + PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT), + PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT), + PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT), /* PTR GPIO */ - PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU), - PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU), - PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU), - PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU), - PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_IN_PU), - PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), - PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU), - PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU), + PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT), + PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT), + PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT), + PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT), + PINMUX_DATA(PTR3_DATA, PTR3_IN), + PINMUX_DATA(PTR2_DATA, PTR2_IN), + PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT), + PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT), /* PTS GPIO */ - PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT, PTS6_IN_PU), - PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT, PTS5_IN_PU), - PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU), - PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU), - PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU), - PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU), - PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU), + PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT), + PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT), + PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT), + PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT), + PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT), + PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT), + PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), /* PTT GPIO */ - PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT, PTT7_IN_PU), - PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT, PTT6_IN_PU), - PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT, PTT5_IN_PU), - PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU), - PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU), - PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU), - PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU), - PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU), + PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT), + PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT), + PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT), + PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), + PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), + PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT), + PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT), + PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT), /* PTU GPIO */ - PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT, PTU7_IN_PU), - PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT, PTU6_IN_PU), - PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT, PTU5_IN_PU), - PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU), - PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU), - PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU), - PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU), - PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU), + PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT), + PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT), + PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT), + PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT), + PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT), + PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT), + PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT), + PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT), /* PTV GPIO */ - PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT, PTV7_IN_PU), - PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT, PTV6_IN_PU), - PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT, PTV5_IN_PU), - PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU), - PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU), - PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU), - PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU), - PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU), + PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT), + PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT), + PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT), + PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT), + PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT), + PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT), + PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT), + PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT), /* PTW GPIO */ - PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT, PTW7_IN_PU), - PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT, PTW6_IN_PU), - PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT, PTW5_IN_PU), - PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT, PTW4_IN_PU), - PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT, PTW3_IN_PU), - PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT, PTW2_IN_PU), - PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT, PTW1_IN_PU), - PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT, PTW0_IN_PU), + PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT), + PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT), + PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT), + PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT), + PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT), + PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT), + PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT), + PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT), /* PTX GPIO */ - PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT, PTX7_IN_PU), - PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT, PTX6_IN_PU), - PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT, PTX5_IN_PU), - PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT, PTX4_IN_PU), - PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT, PTX3_IN_PU), - PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT, PTX2_IN_PU), - PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT, PTX1_IN_PU), - PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT, PTX0_IN_PU), + PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT), + PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT), + PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT), + PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT), + PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT), + PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT), + PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT), + PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT), /* PTY GPIO */ - PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT, PTY7_IN_PU), - PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT, PTY6_IN_PU), - PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT, PTY5_IN_PU), - PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT, PTY4_IN_PU), - PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT, PTY3_IN_PU), - PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT, PTY2_IN_PU), - PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT, PTY1_IN_PU), - PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT, PTY0_IN_PU), + PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT), + PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT), + PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT), + PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT), + PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT), + PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT), + PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT), + PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT), /* PTZ GPIO */ - PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT, PTZ7_IN_PU), - PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT, PTZ6_IN_PU), - PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT, PTZ5_IN_PU), - PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT, PTZ4_IN_PU), - PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT, PTZ3_IN_PU), - PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT, PTZ2_IN_PU), - PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT, PTZ1_IN_PU), - PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT, PTZ0_IN_PU), + PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT), + PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT), + PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT), + PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT), + PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT), + PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT), + PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT), + PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT), /* PTA FN */ PINMUX_DATA(D23_MARK, PSA15_0, PSA14_0, PTA7_FN), @@ -1192,657 +1146,661 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ - PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), - PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), - PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), - PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), - PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), - PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), - PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), - PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), + PINMUX_GPIO(PTA7), + PINMUX_GPIO(PTA6), + PINMUX_GPIO(PTA5), + PINMUX_GPIO(PTA4), + PINMUX_GPIO(PTA3), + PINMUX_GPIO(PTA2), + PINMUX_GPIO(PTA1), + PINMUX_GPIO(PTA0), /* PTB */ - PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), - PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), - PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), - PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), - PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), - PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), - PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), - PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), + PINMUX_GPIO(PTB7), + PINMUX_GPIO(PTB6), + PINMUX_GPIO(PTB5), + PINMUX_GPIO(PTB4), + PINMUX_GPIO(PTB3), + PINMUX_GPIO(PTB2), + PINMUX_GPIO(PTB1), + PINMUX_GPIO(PTB0), /* PTC */ - PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), - PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), - PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), - PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), - PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), - PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), - PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), - PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), + PINMUX_GPIO(PTC7), + PINMUX_GPIO(PTC6), + PINMUX_GPIO(PTC5), + PINMUX_GPIO(PTC4), + PINMUX_GPIO(PTC3), + PINMUX_GPIO(PTC2), + PINMUX_GPIO(PTC1), + PINMUX_GPIO(PTC0), /* PTD */ - PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), - PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), - PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), - PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), - PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), - PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), - PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), - PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), + PINMUX_GPIO(PTD7), + PINMUX_GPIO(PTD6), + PINMUX_GPIO(PTD5), + PINMUX_GPIO(PTD4), + PINMUX_GPIO(PTD3), + PINMUX_GPIO(PTD2), + PINMUX_GPIO(PTD1), + PINMUX_GPIO(PTD0), /* PTE */ - PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), - PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), - PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), - PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), - PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), - PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), - PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), - PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), + PINMUX_GPIO(PTE7), + PINMUX_GPIO(PTE6), + PINMUX_GPIO(PTE5), + PINMUX_GPIO(PTE4), + PINMUX_GPIO(PTE3), + PINMUX_GPIO(PTE2), + PINMUX_GPIO(PTE1), + PINMUX_GPIO(PTE0), /* PTF */ - PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), - PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), - PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), - PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), - PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), - PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), - PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), - PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), + PINMUX_GPIO(PTF7), + PINMUX_GPIO(PTF6), + PINMUX_GPIO(PTF5), + PINMUX_GPIO(PTF4), + PINMUX_GPIO(PTF3), + PINMUX_GPIO(PTF2), + PINMUX_GPIO(PTF1), + PINMUX_GPIO(PTF0), /* PTG */ - PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), - PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), - PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), - PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), - PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), - PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), + PINMUX_GPIO(PTG5), + PINMUX_GPIO(PTG4), + PINMUX_GPIO(PTG3), + PINMUX_GPIO(PTG2), + PINMUX_GPIO(PTG1), + PINMUX_GPIO(PTG0), /* PTH */ - PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), - PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), - PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), - PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), - PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), - PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), - PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), - PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), + PINMUX_GPIO(PTH7), + PINMUX_GPIO(PTH6), + PINMUX_GPIO(PTH5), + PINMUX_GPIO(PTH4), + PINMUX_GPIO(PTH3), + PINMUX_GPIO(PTH2), + PINMUX_GPIO(PTH1), + PINMUX_GPIO(PTH0), /* PTJ */ - PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), - PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), - PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), - PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), - PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), - PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), - PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), + PINMUX_GPIO(PTJ7), + PINMUX_GPIO(PTJ6), + PINMUX_GPIO(PTJ5), + PINMUX_GPIO(PTJ3), + PINMUX_GPIO(PTJ2), + PINMUX_GPIO(PTJ1), + PINMUX_GPIO(PTJ0), /* PTK */ - PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), - PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), - PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), - PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), - PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), - PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), - PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), - PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), + PINMUX_GPIO(PTK7), + PINMUX_GPIO(PTK6), + PINMUX_GPIO(PTK5), + PINMUX_GPIO(PTK4), + PINMUX_GPIO(PTK3), + PINMUX_GPIO(PTK2), + PINMUX_GPIO(PTK1), + PINMUX_GPIO(PTK0), /* PTL */ - PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), - PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), - PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), - PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), - PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), - PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), - PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), - PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), + PINMUX_GPIO(PTL7), + PINMUX_GPIO(PTL6), + PINMUX_GPIO(PTL5), + PINMUX_GPIO(PTL4), + PINMUX_GPIO(PTL3), + PINMUX_GPIO(PTL2), + PINMUX_GPIO(PTL1), + PINMUX_GPIO(PTL0), /* PTM */ - PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), - PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), - PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), - PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), - PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), - PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), - PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), - PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), + PINMUX_GPIO(PTM7), + PINMUX_GPIO(PTM6), + PINMUX_GPIO(PTM5), + PINMUX_GPIO(PTM4), + PINMUX_GPIO(PTM3), + PINMUX_GPIO(PTM2), + PINMUX_GPIO(PTM1), + PINMUX_GPIO(PTM0), /* PTN */ - PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), - PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), - PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), - PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), - PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), - PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), - PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), - PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), + PINMUX_GPIO(PTN7), + PINMUX_GPIO(PTN6), + PINMUX_GPIO(PTN5), + PINMUX_GPIO(PTN4), + PINMUX_GPIO(PTN3), + PINMUX_GPIO(PTN2), + PINMUX_GPIO(PTN1), + PINMUX_GPIO(PTN0), /* PTQ */ - PINMUX_GPIO(GPIO_PTQ7, PTQ7_DATA), - PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), - PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), - PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), - PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), - PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), - PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), - PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), + PINMUX_GPIO(PTQ7), + PINMUX_GPIO(PTQ6), + PINMUX_GPIO(PTQ5), + PINMUX_GPIO(PTQ4), + PINMUX_GPIO(PTQ3), + PINMUX_GPIO(PTQ2), + PINMUX_GPIO(PTQ1), + PINMUX_GPIO(PTQ0), /* PTR */ - PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), - PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), - PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), - PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), - PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), - PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), - PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), - PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), + PINMUX_GPIO(PTR7), + PINMUX_GPIO(PTR6), + PINMUX_GPIO(PTR5), + PINMUX_GPIO(PTR4), + PINMUX_GPIO(PTR3), + PINMUX_GPIO(PTR2), + PINMUX_GPIO(PTR1), + PINMUX_GPIO(PTR0), /* PTS */ - PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), - PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), - PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), - PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), - PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), - PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), - PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), + PINMUX_GPIO(PTS6), + PINMUX_GPIO(PTS5), + PINMUX_GPIO(PTS4), + PINMUX_GPIO(PTS3), + PINMUX_GPIO(PTS2), + PINMUX_GPIO(PTS1), + PINMUX_GPIO(PTS0), /* PTT */ - PINMUX_GPIO(GPIO_PTT7, PTT7_DATA), - PINMUX_GPIO(GPIO_PTT6, PTT6_DATA), - PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), - PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), - PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), - PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), - PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), - PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), + PINMUX_GPIO(PTT7), + PINMUX_GPIO(PTT6), + PINMUX_GPIO(PTT5), + PINMUX_GPIO(PTT4), + PINMUX_GPIO(PTT3), + PINMUX_GPIO(PTT2), + PINMUX_GPIO(PTT1), + PINMUX_GPIO(PTT0), /* PTU */ - PINMUX_GPIO(GPIO_PTU7, PTU7_DATA), - PINMUX_GPIO(GPIO_PTU6, PTU6_DATA), - PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), - PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), - PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), - PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), - PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), - PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), + PINMUX_GPIO(PTU7), + PINMUX_GPIO(PTU6), + PINMUX_GPIO(PTU5), + PINMUX_GPIO(PTU4), + PINMUX_GPIO(PTU3), + PINMUX_GPIO(PTU2), + PINMUX_GPIO(PTU1), + PINMUX_GPIO(PTU0), /* PTV */ - PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), - PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), - PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), - PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), - PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), - PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), - PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), - PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), + PINMUX_GPIO(PTV7), + PINMUX_GPIO(PTV6), + PINMUX_GPIO(PTV5), + PINMUX_GPIO(PTV4), + PINMUX_GPIO(PTV3), + PINMUX_GPIO(PTV2), + PINMUX_GPIO(PTV1), + PINMUX_GPIO(PTV0), /* PTW */ - PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), - PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), - PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), - PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), - PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), - PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), - PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), - PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), + PINMUX_GPIO(PTW7), + PINMUX_GPIO(PTW6), + PINMUX_GPIO(PTW5), + PINMUX_GPIO(PTW4), + PINMUX_GPIO(PTW3), + PINMUX_GPIO(PTW2), + PINMUX_GPIO(PTW1), + PINMUX_GPIO(PTW0), /* PTX */ - PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), - PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), - PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), - PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), - PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), - PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), - PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), - PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), + PINMUX_GPIO(PTX7), + PINMUX_GPIO(PTX6), + PINMUX_GPIO(PTX5), + PINMUX_GPIO(PTX4), + PINMUX_GPIO(PTX3), + PINMUX_GPIO(PTX2), + PINMUX_GPIO(PTX1), + PINMUX_GPIO(PTX0), /* PTY */ - PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), - PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), - PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), - PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), - PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), - PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), - PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), - PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), + PINMUX_GPIO(PTY7), + PINMUX_GPIO(PTY6), + PINMUX_GPIO(PTY5), + PINMUX_GPIO(PTY4), + PINMUX_GPIO(PTY3), + PINMUX_GPIO(PTY2), + PINMUX_GPIO(PTY1), + PINMUX_GPIO(PTY0), /* PTZ */ - PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), - PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), - PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), - PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), - PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), - PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), - PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), - PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), + PINMUX_GPIO(PTZ7), + PINMUX_GPIO(PTZ6), + PINMUX_GPIO(PTZ5), + PINMUX_GPIO(PTZ4), + PINMUX_GPIO(PTZ3), + PINMUX_GPIO(PTZ2), + PINMUX_GPIO(PTZ1), + PINMUX_GPIO(PTZ0), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* BSC */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), - PINMUX_GPIO(GPIO_FN_D7, D7_MARK), - PINMUX_GPIO(GPIO_FN_D6, D6_MARK), - PINMUX_GPIO(GPIO_FN_D5, D5_MARK), - PINMUX_GPIO(GPIO_FN_D4, D4_MARK), - PINMUX_GPIO(GPIO_FN_D3, D3_MARK), - PINMUX_GPIO(GPIO_FN_D2, D2_MARK), - PINMUX_GPIO(GPIO_FN_D1, D1_MARK), - PINMUX_GPIO(GPIO_FN_D0, D0_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), - PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), - PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), - PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), - PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(D15), + GPIO_FN(D14), + GPIO_FN(D13), + GPIO_FN(D12), + GPIO_FN(D11), + GPIO_FN(D10), + GPIO_FN(D9), + GPIO_FN(D8), + GPIO_FN(D7), + GPIO_FN(D6), + GPIO_FN(D5), + GPIO_FN(D4), + GPIO_FN(D3), + GPIO_FN(D2), + GPIO_FN(D1), + GPIO_FN(D0), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(CS6B_CE1B), + GPIO_FN(CS6A_CE2B), + GPIO_FN(CS5B_CE1A), + GPIO_FN(CS5A_CE2A), + GPIO_FN(WE3_ICIOWR), + GPIO_FN(WE2_ICIORD), + GPIO_FN(IOIS16), + GPIO_FN(WAIT), + GPIO_FN(BS), /* KEYSC */ - PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), - PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), - PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), + GPIO_FN(KEYOUT5_IN5), + GPIO_FN(KEYOUT4_IN6), + GPIO_FN(KEYIN4), + GPIO_FN(KEYIN3), + GPIO_FN(KEYIN2), + GPIO_FN(KEYIN1), + GPIO_FN(KEYIN0), + GPIO_FN(KEYOUT3), + GPIO_FN(KEYOUT2), + GPIO_FN(KEYOUT1), + GPIO_FN(KEYOUT0), /* ATAPI */ - PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), - PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), - PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), - PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), - PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), - PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), - PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), - PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), - PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), - PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), - PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), - PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), - PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), - PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), - PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), - PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), - PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), - PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), - PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), - PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), - PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), - PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), - PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), - PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), - PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), - PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), - PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), - PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), - PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), + GPIO_FN(IDED15), + GPIO_FN(IDED14), + GPIO_FN(IDED13), + GPIO_FN(IDED12), + GPIO_FN(IDED11), + GPIO_FN(IDED10), + GPIO_FN(IDED9), + GPIO_FN(IDED8), + GPIO_FN(IDED7), + GPIO_FN(IDED6), + GPIO_FN(IDED5), + GPIO_FN(IDED4), + GPIO_FN(IDED3), + GPIO_FN(IDED2), + GPIO_FN(IDED1), + GPIO_FN(IDED0), + GPIO_FN(IDEA2), + GPIO_FN(IDEA1), + GPIO_FN(IDEA0), + GPIO_FN(IDEIOWR), + GPIO_FN(IODREQ), + GPIO_FN(IDECS0), + GPIO_FN(IDECS1), + GPIO_FN(IDEIORD), + GPIO_FN(DIRECTION), + GPIO_FN(EXBUF_ENB), + GPIO_FN(IDERST), + GPIO_FN(IODACK), + GPIO_FN(IDEINT), + GPIO_FN(IDEIORDY), /* TPU */ - PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), - PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), - PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK), - PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK), + GPIO_FN(TPUTO3), + GPIO_FN(TPUTO2), + GPIO_FN(TPUTO1), + GPIO_FN(TPUTO0), + GPIO_FN(TPUTI3), + GPIO_FN(TPUTI2), /* LCDC */ - PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), - PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), - PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), - PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), - PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), - PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), - PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), - PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), - PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), - PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), - PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), - PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), - PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), - PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), - PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), - PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), - PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), - PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), - PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), - PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), - PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), - PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), - PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), - PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), - PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), - PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), - PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), - PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), - PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), - PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), - PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), - PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), - PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), - PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), + GPIO_FN(LCDD23), + GPIO_FN(LCDD22), + GPIO_FN(LCDD21), + GPIO_FN(LCDD20), + GPIO_FN(LCDD19), + GPIO_FN(LCDD18), + GPIO_FN(LCDD17), + GPIO_FN(LCDD16), + GPIO_FN(LCDD15), + GPIO_FN(LCDD14), + GPIO_FN(LCDD13), + GPIO_FN(LCDD12), + GPIO_FN(LCDD11), + GPIO_FN(LCDD10), + GPIO_FN(LCDD9), + GPIO_FN(LCDD8), + GPIO_FN(LCDD7), + GPIO_FN(LCDD6), + GPIO_FN(LCDD5), + GPIO_FN(LCDD4), + GPIO_FN(LCDD3), + GPIO_FN(LCDD2), + GPIO_FN(LCDD1), + GPIO_FN(LCDD0), + GPIO_FN(LCDVSYN), + GPIO_FN(LCDDISP), + GPIO_FN(LCDRS), + GPIO_FN(LCDHSYN), + GPIO_FN(LCDCS), + GPIO_FN(LCDDON), + GPIO_FN(LCDDCK), + GPIO_FN(LCDWR), + GPIO_FN(LCDVEPWC), + GPIO_FN(LCDVCPWC), + GPIO_FN(LCDRD), + GPIO_FN(LCDLCLK), /* SCIF0 */ - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + GPIO_FN(SCIF0_TXD), + GPIO_FN(SCIF0_RXD), + GPIO_FN(SCIF0_SCK), /* SCIF1 */ - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), + GPIO_FN(SCIF1_SCK), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_TXD), /* SCIF2 */ - PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK), + GPIO_FN(SCIF2_L_TXD), + GPIO_FN(SCIF2_L_SCK), + GPIO_FN(SCIF2_L_RXD), + GPIO_FN(SCIF2_V_TXD), + GPIO_FN(SCIF2_V_SCK), + GPIO_FN(SCIF2_V_RXD), /* SCIF3 */ - PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK), + GPIO_FN(SCIF3_V_SCK), + GPIO_FN(SCIF3_V_RXD), + GPIO_FN(SCIF3_V_TXD), + GPIO_FN(SCIF3_V_CTS), + GPIO_FN(SCIF3_V_RTS), + GPIO_FN(SCIF3_I_SCK), + GPIO_FN(SCIF3_I_RXD), + GPIO_FN(SCIF3_I_TXD), + GPIO_FN(SCIF3_I_CTS), + GPIO_FN(SCIF3_I_RTS), /* SCIF4 */ - PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), + GPIO_FN(SCIF4_SCK), + GPIO_FN(SCIF4_RXD), + GPIO_FN(SCIF4_TXD), /* SCIF5 */ - PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), + GPIO_FN(SCIF5_SCK), + GPIO_FN(SCIF5_RXD), + GPIO_FN(SCIF5_TXD), /* FSI */ - PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK), - PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK), - PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK), - PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK), - PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK), - PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK), - PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK), - PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK), - PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK), - PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK), - PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK), + GPIO_FN(FSIMCKB), + GPIO_FN(FSIMCKA), + GPIO_FN(FSIOASD), + GPIO_FN(FSIIABCK), + GPIO_FN(FSIIALRCK), + GPIO_FN(FSIOABCK), + GPIO_FN(FSIOALRCK), + GPIO_FN(CLKAUDIOAO), + GPIO_FN(FSIIBSD), + GPIO_FN(FSIOBSD), + GPIO_FN(FSIIBBCK), + GPIO_FN(FSIIBLRCK), + GPIO_FN(FSIOBBCK), + GPIO_FN(FSIOBLRCK), + GPIO_FN(CLKAUDIOBO), + GPIO_FN(FSIIASD), /* AUD */ - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + GPIO_FN(AUDCK), + GPIO_FN(AUDSYNC), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), /* VIO */ - PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), + GPIO_FN(VIO_CKO), /* VIO0 */ - PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK), + GPIO_FN(VIO0_D15), + GPIO_FN(VIO0_D14), + GPIO_FN(VIO0_D13), + GPIO_FN(VIO0_D12), + GPIO_FN(VIO0_D11), + GPIO_FN(VIO0_D10), + GPIO_FN(VIO0_D9), + GPIO_FN(VIO0_D8), + GPIO_FN(VIO0_D7), + GPIO_FN(VIO0_D6), + GPIO_FN(VIO0_D5), + GPIO_FN(VIO0_D4), + GPIO_FN(VIO0_D3), + GPIO_FN(VIO0_D2), + GPIO_FN(VIO0_D1), + GPIO_FN(VIO0_D0), + GPIO_FN(VIO0_VD), + GPIO_FN(VIO0_CLK), + GPIO_FN(VIO0_FLD), + GPIO_FN(VIO0_HD), /* VIO1 */ - PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK), - PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK), + GPIO_FN(VIO1_D7), + GPIO_FN(VIO1_D6), + GPIO_FN(VIO1_D5), + GPIO_FN(VIO1_D4), + GPIO_FN(VIO1_D3), + GPIO_FN(VIO1_D2), + GPIO_FN(VIO1_D1), + GPIO_FN(VIO1_D0), + GPIO_FN(VIO1_FLD), + GPIO_FN(VIO1_HD), + GPIO_FN(VIO1_VD), + GPIO_FN(VIO1_CLK), /* Eth */ - PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK), - PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK), - PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK), - PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK), - PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK), + GPIO_FN(RMII_RXD0), + GPIO_FN(RMII_RXD1), + GPIO_FN(RMII_TXD0), + GPIO_FN(RMII_TXD1), + GPIO_FN(RMII_REF_CLK), + GPIO_FN(RMII_TX_EN), + GPIO_FN(RMII_RX_ER), + GPIO_FN(RMII_CRS_DV), + GPIO_FN(LNKSTA), + GPIO_FN(MDIO), + GPIO_FN(MDC), /* System */ - PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), - PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + GPIO_FN(PDSTATUS), + GPIO_FN(STATUS2), + GPIO_FN(STATUS0), /* VOU */ - PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), - PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), - PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), - PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), - PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), - PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), - PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), - PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), - PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), - PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), - PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), - PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), - PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), - PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), - PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), - PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), - PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + GPIO_FN(DV_D15), + GPIO_FN(DV_D14), + GPIO_FN(DV_D13), + GPIO_FN(DV_D12), + GPIO_FN(DV_D11), + GPIO_FN(DV_D10), + GPIO_FN(DV_D9), + GPIO_FN(DV_D8), + GPIO_FN(DV_D7), + GPIO_FN(DV_D6), + GPIO_FN(DV_D5), + GPIO_FN(DV_D4), + GPIO_FN(DV_D3), + GPIO_FN(DV_D2), + GPIO_FN(DV_D1), + GPIO_FN(DV_D0), + GPIO_FN(DV_CLKI), + GPIO_FN(DV_CLK), + GPIO_FN(DV_VSYNC), + GPIO_FN(DV_HSYNC), /* MSIOF0 */ - PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK), + GPIO_FN(MSIOF0_RXD), + GPIO_FN(MSIOF0_TXD), + GPIO_FN(MSIOF0_MCK), + GPIO_FN(MSIOF0_TSCK), + GPIO_FN(MSIOF0_SS1), + GPIO_FN(MSIOF0_SS2), + GPIO_FN(MSIOF0_TSYNC), + GPIO_FN(MSIOF0_RSCK), + GPIO_FN(MSIOF0_RSYNC), /* MSIOF1 */ - PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), - PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), + GPIO_FN(MSIOF1_RXD), + GPIO_FN(MSIOF1_TXD), + GPIO_FN(MSIOF1_MCK), + GPIO_FN(MSIOF1_TSCK), + GPIO_FN(MSIOF1_SS1), + GPIO_FN(MSIOF1_SS2), + GPIO_FN(MSIOF1_TSYNC), + GPIO_FN(MSIOF1_RSCK), + GPIO_FN(MSIOF1_RSYNC), /* DMAC */ - PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK), + GPIO_FN(DMAC_DACK0), + GPIO_FN(DMAC_DREQ0), + GPIO_FN(DMAC_DACK1), + GPIO_FN(DMAC_DREQ1), /* SDHI0 */ - PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK), - PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK), + GPIO_FN(SDHI0CD), + GPIO_FN(SDHI0WP), + GPIO_FN(SDHI0CMD), + GPIO_FN(SDHI0CLK), + GPIO_FN(SDHI0D3), + GPIO_FN(SDHI0D2), + GPIO_FN(SDHI0D1), + GPIO_FN(SDHI0D0), /* SDHI1 */ - PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), - PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), + GPIO_FN(SDHI1CD), + GPIO_FN(SDHI1WP), + GPIO_FN(SDHI1CMD), + GPIO_FN(SDHI1CLK), + GPIO_FN(SDHI1D3), + GPIO_FN(SDHI1D2), + GPIO_FN(SDHI1D1), + GPIO_FN(SDHI1D0), /* MMC */ - PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK), - PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), - PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), + GPIO_FN(MMC_D7), + GPIO_FN(MMC_D6), + GPIO_FN(MMC_D5), + GPIO_FN(MMC_D4), + GPIO_FN(MMC_D3), + GPIO_FN(MMC_D2), + GPIO_FN(MMC_D1), + GPIO_FN(MMC_D0), + GPIO_FN(MMC_CLK), + GPIO_FN(MMC_CMD), /* IrDA */ - PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), - PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), + GPIO_FN(IRDA_OUT), + GPIO_FN(IRDA_IN), /* TSIF */ - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK), - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK), - PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK), + GPIO_FN(TSIF_TS0_SDAT), + GPIO_FN(TSIF_TS0_SCK), + GPIO_FN(TSIF_TS0_SDEN), + GPIO_FN(TSIF_TS0_SPSYNC), /* IRQ */ - PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK), + GPIO_FN(INTC_IRQ7), + GPIO_FN(INTC_IRQ6), + GPIO_FN(INTC_IRQ5), + GPIO_FN(INTC_IRQ4), + GPIO_FN(INTC_IRQ3), + GPIO_FN(INTC_IRQ2), + GPIO_FN(INTC_IRQ1), + GPIO_FN(INTC_IRQ0), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { - PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, - PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, - PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN, - PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, - PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, - PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, - PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, - PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } + PTA7_FN, PTA7_OUT, 0, PTA7_IN, + PTA6_FN, PTA6_OUT, 0, PTA6_IN, + PTA5_FN, PTA5_OUT, 0, PTA5_IN, + PTA4_FN, PTA4_OUT, 0, PTA4_IN, + PTA3_FN, PTA3_OUT, 0, PTA3_IN, + PTA2_FN, PTA2_OUT, 0, PTA2_IN, + PTA1_FN, PTA1_OUT, 0, PTA1_IN, + PTA0_FN, PTA0_OUT, 0, PTA0_IN } }, { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { - PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN, - PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN, - PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN, - PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN, - PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN, - PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, - PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, - PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN } + PTB7_FN, PTB7_OUT, 0, PTB7_IN, + PTB6_FN, PTB6_OUT, 0, PTB6_IN, + PTB5_FN, PTB5_OUT, 0, PTB5_IN, + PTB4_FN, PTB4_OUT, 0, PTB4_IN, + PTB3_FN, PTB3_OUT, 0, PTB3_IN, + PTB2_FN, PTB2_OUT, 0, PTB2_IN, + PTB1_FN, PTB1_OUT, 0, PTB1_IN, + PTB0_FN, PTB0_OUT, 0, PTB0_IN } }, { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { - PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN, - PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN, - PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN, - PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN, - PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN, - PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN, - PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN, - PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN } + PTC7_FN, PTC7_OUT, 0, PTC7_IN, + PTC6_FN, PTC6_OUT, 0, PTC6_IN, + PTC5_FN, PTC5_OUT, 0, PTC5_IN, + PTC4_FN, PTC4_OUT, 0, PTC4_IN, + PTC3_FN, PTC3_OUT, 0, PTC3_IN, + PTC2_FN, PTC2_OUT, 0, PTC2_IN, + PTC1_FN, PTC1_OUT, 0, PTC1_IN, + PTC0_FN, PTC0_OUT, 0, PTC0_IN } }, { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { - PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN, - PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN, - PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN, - PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN, - PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN, - PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN, - PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN, - PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN } + PTD7_FN, PTD7_OUT, 0, PTD7_IN, + PTD6_FN, PTD6_OUT, 0, PTD6_IN, + PTD5_FN, PTD5_OUT, 0, PTD5_IN, + PTD4_FN, PTD4_OUT, 0, PTD4_IN, + PTD3_FN, PTD3_OUT, 0, PTD3_IN, + PTD2_FN, PTD2_OUT, 0, PTD2_IN, + PTD1_FN, PTD1_OUT, 0, PTD1_IN, + PTD0_FN, PTD0_OUT, 0, PTD0_IN } }, { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { - PTE7_FN, PTE7_OUT, PTE7_IN_PU, PTE7_IN, - PTE6_FN, PTE6_OUT, PTE6_IN_PU, PTE6_IN, - PTE5_FN, PTE5_OUT, PTE5_IN_PU, PTE5_IN, - PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN, - PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN, - PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN, - PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN, - PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN } + PTE7_FN, PTE7_OUT, 0, PTE7_IN, + PTE6_FN, PTE6_OUT, 0, PTE6_IN, + PTE5_FN, PTE5_OUT, 0, PTE5_IN, + PTE4_FN, PTE4_OUT, 0, PTE4_IN, + PTE3_FN, PTE3_OUT, 0, PTE3_IN, + PTE2_FN, PTE2_OUT, 0, PTE2_IN, + PTE1_FN, PTE1_OUT, 0, PTE1_IN, + PTE0_FN, PTE0_OUT, 0, PTE0_IN } }, { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { - PTF7_FN, PTF7_OUT, PTF7_IN_PU, PTF7_IN, - PTF6_FN, PTF6_OUT, PTF6_IN_PU, PTF6_IN, - PTF5_FN, PTF5_OUT, PTF5_IN_PU, PTF5_IN, - PTF4_FN, PTF4_OUT, PTF4_IN_PU, PTF4_IN, - PTF3_FN, PTF3_OUT, PTF3_IN_PU, PTF3_IN, - PTF2_FN, PTF2_OUT, PTF2_IN_PU, PTF2_IN, - PTF1_FN, PTF1_OUT, PTF1_IN_PU, PTF1_IN, - PTF0_FN, PTF0_OUT, PTF0_IN_PU, PTF0_IN } + PTF7_FN, PTF7_OUT, 0, PTF7_IN, + PTF6_FN, PTF6_OUT, 0, PTF6_IN, + PTF5_FN, PTF5_OUT, 0, PTF5_IN, + PTF4_FN, PTF4_OUT, 0, PTF4_IN, + PTF3_FN, PTF3_OUT, 0, PTF3_IN, + PTF2_FN, PTF2_OUT, 0, PTF2_IN, + PTF1_FN, PTF1_OUT, 0, PTF1_IN, + PTF0_FN, PTF0_OUT, 0, PTF0_IN } }, { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { 0, 0, 0, 0, @@ -1855,164 +1813,164 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTG0_FN, PTG0_OUT, 0, 0 } }, { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { - PTH7_FN, PTH7_OUT, PTH7_IN_PU, PTH7_IN, - PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN, - PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN, - PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN, - PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN, - PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN, - PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN, - PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN } + PTH7_FN, PTH7_OUT, 0, PTH7_IN, + PTH6_FN, PTH6_OUT, 0, PTH6_IN, + PTH5_FN, PTH5_OUT, 0, PTH5_IN, + PTH4_FN, PTH4_OUT, 0, PTH4_IN, + PTH3_FN, PTH3_OUT, 0, PTH3_IN, + PTH2_FN, PTH2_OUT, 0, PTH2_IN, + PTH1_FN, PTH1_OUT, 0, PTH1_IN, + PTH0_FN, PTH0_OUT, 0, PTH0_IN } }, { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { PTJ7_FN, PTJ7_OUT, 0, 0, PTJ6_FN, PTJ6_OUT, 0, 0, PTJ5_FN, PTJ5_OUT, 0, 0, 0, 0, 0, 0, - PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN, - PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN, - PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, - PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } + PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN, + PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN, + PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN, + PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN } }, { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { - PTK7_FN, PTK7_OUT, PTK7_IN_PU, PTK7_IN, - PTK6_FN, PTK6_OUT, PTK6_IN_PU, PTK6_IN, - PTK5_FN, PTK5_OUT, PTK5_IN_PU, PTK5_IN, - PTK4_FN, PTK4_OUT, PTK4_IN_PU, PTK4_IN, - PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN, - PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN, - PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN, - PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN } + PTK7_FN, PTK7_OUT, 0, PTK7_IN, + PTK6_FN, PTK6_OUT, 0, PTK6_IN, + PTK5_FN, PTK5_OUT, 0, PTK5_IN, + PTK4_FN, PTK4_OUT, 0, PTK4_IN, + PTK3_FN, PTK3_OUT, 0, PTK3_IN, + PTK2_FN, PTK2_OUT, 0, PTK2_IN, + PTK1_FN, PTK1_OUT, 0, PTK1_IN, + PTK0_FN, PTK0_OUT, 0, PTK0_IN } }, { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { - PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN, - PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN, - PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN, - PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN, - PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN, - PTL2_FN, PTL2_OUT, PTL2_IN_PU, PTL2_IN, - PTL1_FN, PTL1_OUT, PTL1_IN_PU, PTL1_IN, - PTL0_FN, PTL0_OUT, PTL0_IN_PU, PTL0_IN } + PTL7_FN, PTL7_OUT, 0, PTL7_IN, + PTL6_FN, PTL6_OUT, 0, PTL6_IN, + PTL5_FN, PTL5_OUT, 0, PTL5_IN, + PTL4_FN, PTL4_OUT, 0, PTL4_IN, + PTL3_FN, PTL3_OUT, 0, PTL3_IN, + PTL2_FN, PTL2_OUT, 0, PTL2_IN, + PTL1_FN, PTL1_OUT, 0, PTL1_IN, + PTL0_FN, PTL0_OUT, 0, PTL0_IN } }, { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { - PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN, - PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN, - PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN, - PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN, - PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN, - PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN, - PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN, - PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN } + PTM7_FN, PTM7_OUT, 0, PTM7_IN, + PTM6_FN, PTM6_OUT, 0, PTM6_IN, + PTM5_FN, PTM5_OUT, 0, PTM5_IN, + PTM4_FN, PTM4_OUT, 0, PTM4_IN, + PTM3_FN, PTM3_OUT, 0, PTM3_IN, + PTM2_FN, PTM2_OUT, 0, PTM2_IN, + PTM1_FN, PTM1_OUT, 0, PTM1_IN, + PTM0_FN, PTM0_OUT, 0, PTM0_IN } }, { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { - PTN7_FN, PTN7_OUT, PTN7_IN_PU, PTN7_IN, - PTN6_FN, PTN6_OUT, PTN6_IN_PU, PTN6_IN, - PTN5_FN, PTN5_OUT, PTN5_IN_PU, PTN5_IN, - PTN4_FN, PTN4_OUT, PTN4_IN_PU, PTN4_IN, - PTN3_FN, PTN3_OUT, PTN3_IN_PU, PTN3_IN, - PTN2_FN, PTN2_OUT, PTN2_IN_PU, PTN2_IN, - PTN1_FN, PTN1_OUT, PTN1_IN_PU, PTN1_IN, - PTN0_FN, PTN0_OUT, PTN0_IN_PU, PTN0_IN } + PTN7_FN, PTN7_OUT, 0, PTN7_IN, + PTN6_FN, PTN6_OUT, 0, PTN6_IN, + PTN5_FN, PTN5_OUT, 0, PTN5_IN, + PTN4_FN, PTN4_OUT, 0, PTN4_IN, + PTN3_FN, PTN3_OUT, 0, PTN3_IN, + PTN2_FN, PTN2_OUT, 0, PTN2_IN, + PTN1_FN, PTN1_OUT, 0, PTN1_IN, + PTN0_FN, PTN0_OUT, 0, PTN0_IN } }, { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { - PTQ7_FN, PTQ7_OUT, PTQ7_IN_PU, PTQ7_IN, - PTQ6_FN, PTQ6_OUT, PTQ6_IN_PU, PTQ6_IN, - PTQ5_FN, PTQ5_OUT, PTQ5_IN_PU, PTQ5_IN, - PTQ4_FN, PTQ4_OUT, PTQ4_IN_PU, PTQ4_IN, - PTQ3_FN, PTQ3_OUT, PTQ3_IN_PU, PTQ3_IN, - PTQ2_FN, PTQ2_OUT, PTQ2_IN_PU, PTQ2_IN, - PTQ1_FN, PTQ1_OUT, PTQ1_IN_PU, PTQ1_IN, - PTQ0_FN, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN } + PTQ7_FN, PTQ7_OUT, 0, PTQ7_IN, + PTQ6_FN, PTQ6_OUT, 0, PTQ6_IN, + PTQ5_FN, PTQ5_OUT, 0, PTQ5_IN, + PTQ4_FN, PTQ4_OUT, 0, PTQ4_IN, + PTQ3_FN, PTQ3_OUT, 0, PTQ3_IN, + PTQ2_FN, PTQ2_OUT, 0, PTQ2_IN, + PTQ1_FN, PTQ1_OUT, 0, PTQ1_IN, + PTQ0_FN, PTQ0_OUT, 0, PTQ0_IN } }, { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { - PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN, - PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN, - PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN, - PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN, - PTR3_FN, 0, PTR3_IN_PU, PTR3_IN, - PTR2_FN, 0, PTR2_IN_PU, PTR2_IN, - PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN, - PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN } + PTR7_FN, PTR7_OUT, 0, PTR7_IN, + PTR6_FN, PTR6_OUT, 0, PTR6_IN, + PTR5_FN, PTR5_OUT, 0, PTR5_IN, + PTR4_FN, PTR4_OUT, 0, PTR4_IN, + PTR3_FN, 0, 0, PTR3_IN, + PTR2_FN, 0, 0, PTR2_IN, + PTR1_FN, PTR1_OUT, 0, PTR1_IN, + PTR0_FN, PTR0_OUT, 0, PTR0_IN } }, { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { 0, 0, 0, 0, - PTS6_FN, PTS6_OUT, PTS6_IN_PU, PTS6_IN, - PTS5_FN, PTS5_OUT, PTS5_IN_PU, PTS5_IN, - PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN, - PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN, - PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN, - PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN, - PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN } + PTS6_FN, PTS6_OUT, 0, PTS6_IN, + PTS5_FN, PTS5_OUT, 0, PTS5_IN, + PTS4_FN, PTS4_OUT, 0, PTS4_IN, + PTS3_FN, PTS3_OUT, 0, PTS3_IN, + PTS2_FN, PTS2_OUT, 0, PTS2_IN, + PTS1_FN, PTS1_OUT, 0, PTS1_IN, + PTS0_FN, PTS0_OUT, 0, PTS0_IN } }, { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { - PTT7_FN, PTT7_OUT, PTT7_IN_PU, PTT7_IN, - PTT6_FN, PTT6_OUT, PTT6_IN_PU, PTT6_IN, - PTT5_FN, PTT5_OUT, PTT5_IN_PU, PTT5_IN, - PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN, - PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN, - PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN, - PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN, - PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN } + PTT7_FN, PTT7_OUT, 0, PTT7_IN, + PTT6_FN, PTT6_OUT, 0, PTT6_IN, + PTT5_FN, PTT5_OUT, 0, PTT5_IN, + PTT4_FN, PTT4_OUT, 0, PTT4_IN, + PTT3_FN, PTT3_OUT, 0, PTT3_IN, + PTT2_FN, PTT2_OUT, 0, PTT2_IN, + PTT1_FN, PTT1_OUT, 0, PTT1_IN, + PTT0_FN, PTT0_OUT, 0, PTT0_IN } }, { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { - PTU7_FN, PTU7_OUT, PTU7_IN_PU, PTU7_IN, - PTU6_FN, PTU6_OUT, PTU6_IN_PU, PTU6_IN, - PTU5_FN, PTU5_OUT, PTU5_IN_PU, PTU5_IN, - PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN, - PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN, - PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN, - PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN, - PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN } + PTU7_FN, PTU7_OUT, 0, PTU7_IN, + PTU6_FN, PTU6_OUT, 0, PTU6_IN, + PTU5_FN, PTU5_OUT, 0, PTU5_IN, + PTU4_FN, PTU4_OUT, 0, PTU4_IN, + PTU3_FN, PTU3_OUT, 0, PTU3_IN, + PTU2_FN, PTU2_OUT, 0, PTU2_IN, + PTU1_FN, PTU1_OUT, 0, PTU1_IN, + PTU0_FN, PTU0_OUT, 0, PTU0_IN } }, { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { - PTV7_FN, PTV7_OUT, PTV7_IN_PU, PTV7_IN, - PTV6_FN, PTV6_OUT, PTV6_IN_PU, PTV6_IN, - PTV5_FN, PTV5_OUT, PTV5_IN_PU, PTV5_IN, - PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN, - PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN, - PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN, - PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN, - PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN } + PTV7_FN, PTV7_OUT, 0, PTV7_IN, + PTV6_FN, PTV6_OUT, 0, PTV6_IN, + PTV5_FN, PTV5_OUT, 0, PTV5_IN, + PTV4_FN, PTV4_OUT, 0, PTV4_IN, + PTV3_FN, PTV3_OUT, 0, PTV3_IN, + PTV2_FN, PTV2_OUT, 0, PTV2_IN, + PTV1_FN, PTV1_OUT, 0, PTV1_IN, + PTV0_FN, PTV0_OUT, 0, PTV0_IN } }, { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { - PTW7_FN, PTW7_OUT, PTW7_IN_PU, PTW7_IN, - PTW6_FN, PTW6_OUT, PTW6_IN_PU, PTW6_IN, - PTW5_FN, PTW5_OUT, PTW5_IN_PU, PTW5_IN, - PTW4_FN, PTW4_OUT, PTW4_IN_PU, PTW4_IN, - PTW3_FN, PTW3_OUT, PTW3_IN_PU, PTW3_IN, - PTW2_FN, PTW2_OUT, PTW2_IN_PU, PTW2_IN, - PTW1_FN, PTW1_OUT, PTW1_IN_PU, PTW1_IN, - PTW0_FN, PTW0_OUT, PTW0_IN_PU, PTW0_IN } + PTW7_FN, PTW7_OUT, 0, PTW7_IN, + PTW6_FN, PTW6_OUT, 0, PTW6_IN, + PTW5_FN, PTW5_OUT, 0, PTW5_IN, + PTW4_FN, PTW4_OUT, 0, PTW4_IN, + PTW3_FN, PTW3_OUT, 0, PTW3_IN, + PTW2_FN, PTW2_OUT, 0, PTW2_IN, + PTW1_FN, PTW1_OUT, 0, PTW1_IN, + PTW0_FN, PTW0_OUT, 0, PTW0_IN } }, { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { - PTX7_FN, PTX7_OUT, PTX7_IN_PU, PTX7_IN, - PTX6_FN, PTX6_OUT, PTX6_IN_PU, PTX6_IN, - PTX5_FN, PTX5_OUT, PTX5_IN_PU, PTX5_IN, - PTX4_FN, PTX4_OUT, PTX4_IN_PU, PTX4_IN, - PTX3_FN, PTX3_OUT, PTX3_IN_PU, PTX3_IN, - PTX2_FN, PTX2_OUT, PTX2_IN_PU, PTX2_IN, - PTX1_FN, PTX1_OUT, PTX1_IN_PU, PTX1_IN, - PTX0_FN, PTX0_OUT, PTX0_IN_PU, PTX0_IN } + PTX7_FN, PTX7_OUT, 0, PTX7_IN, + PTX6_FN, PTX6_OUT, 0, PTX6_IN, + PTX5_FN, PTX5_OUT, 0, PTX5_IN, + PTX4_FN, PTX4_OUT, 0, PTX4_IN, + PTX3_FN, PTX3_OUT, 0, PTX3_IN, + PTX2_FN, PTX2_OUT, 0, PTX2_IN, + PTX1_FN, PTX1_OUT, 0, PTX1_IN, + PTX0_FN, PTX0_OUT, 0, PTX0_IN } }, { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { - PTY7_FN, PTY7_OUT, PTY7_IN_PU, PTY7_IN, - PTY6_FN, PTY6_OUT, PTY6_IN_PU, PTY6_IN, - PTY5_FN, PTY5_OUT, PTY5_IN_PU, PTY5_IN, - PTY4_FN, PTY4_OUT, PTY4_IN_PU, PTY4_IN, - PTY3_FN, PTY3_OUT, PTY3_IN_PU, PTY3_IN, - PTY2_FN, PTY2_OUT, PTY2_IN_PU, PTY2_IN, - PTY1_FN, PTY1_OUT, PTY1_IN_PU, PTY1_IN, - PTY0_FN, PTY0_OUT, PTY0_IN_PU, PTY0_IN } + PTY7_FN, PTY7_OUT, 0, PTY7_IN, + PTY6_FN, PTY6_OUT, 0, PTY6_IN, + PTY5_FN, PTY5_OUT, 0, PTY5_IN, + PTY4_FN, PTY4_OUT, 0, PTY4_IN, + PTY3_FN, PTY3_OUT, 0, PTY3_IN, + PTY2_FN, PTY2_OUT, 0, PTY2_IN, + PTY1_FN, PTY1_OUT, 0, PTY1_IN, + PTY0_FN, PTY0_OUT, 0, PTY0_IN } }, { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { - PTZ7_FN, PTZ7_OUT, PTZ7_IN_PU, PTZ7_IN, - PTZ6_FN, PTZ6_OUT, PTZ6_IN_PU, PTZ6_IN, - PTZ5_FN, PTZ5_OUT, PTZ5_IN_PU, PTZ5_IN, - PTZ4_FN, PTZ4_OUT, PTZ4_IN_PU, PTZ4_IN, - PTZ3_FN, PTZ3_OUT, PTZ3_IN_PU, PTZ3_IN, - PTZ2_FN, PTZ2_OUT, PTZ2_IN_PU, PTZ2_IN, - PTZ1_FN, PTZ1_OUT, PTZ1_IN_PU, PTZ1_IN, - PTZ0_FN, PTZ0_OUT, PTZ0_IN_PU, PTZ0_IN } + PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN, + PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN, + PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN, + PTZ4_FN, PTZ4_OUT, 0, PTZ4_IN, + PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN, + PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN, + PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN, + PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN } }, { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { PSA15_0, PSA15_1, @@ -2107,7 +2065,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -2203,20 +2161,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7724_pinmux_info = { +const struct sh_pfc_soc_info sh7724_pinmux_info = { .name = "sh7724_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_INTC_IRQ0, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index 23d76d262c3..e53dd1cb162 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -14,57 +14,30 @@ #include "sh_pfc.h" -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define CPU_32_PORT5(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ - PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ - PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ - PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx), \ - PORT_1(fn, pfx##10, sfx), PORT_1(fn, pfx##11, sfx) - -/* GPSR0 - GPSR5 */ -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT(fn, pfx##_0_, sfx), \ - CPU_32_PORT(fn, pfx##_1_, sfx), \ - CPU_32_PORT(fn, pfx##_2_, sfx), \ - CPU_32_PORT(fn, pfx##_3_, sfx), \ - CPU_32_PORT(fn, pfx##_4_, sfx), \ - CPU_32_PORT5(fn, pfx##_5_, sfx) - -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) - -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA - -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) - -#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ - FN_##ipsr, FN_##fn) +#define PORT_GP_12(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_12(5, fn, sfx) + +#undef _GP_DATA +#define _GP_DATA(bank, pin, name, sfx) \ + PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT) + +#define _GP_INOUTSEL(bank, pin, name, sfx) name##_IN, name##_OUT +#define _GP_INDT(bank, pin, name, sfx) name##_DATA +#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused) +#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused) enum { PINMUX_RESERVED = 0, @@ -609,7 +582,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT), @@ -1384,9 +1357,13 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0), GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1), GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0), @@ -1665,7 +1642,7 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) { GP_0_31_FN, FN_IP2_2_0, GP_0_30_FN, FN_IP1_31_29, @@ -2434,7 +2411,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { /* GPIO 0 - 5*/ { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } }, { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } }, @@ -2451,22 +2428,20 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7734_pinmux_info = { +const struct sh_pfc_soc_info sh7734_pinmux_info = { .name = "sh7734_pfc", .unlock_reg = 0xFFFC0000, - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_ST_CLKOUT, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index 5ed74cd0ba9..625661a88c5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -132,46 +132,6 @@ enum { PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, PINMUX_INPUT_END, - PINMUX_INPUT_PULLUP_BEGIN, - PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, - PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, - PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, - PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, - PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU, - PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, - PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU, - PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU, - PTG7_IN_PU, PTG6_IN_PU, PTG4_IN_PU, - PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, - PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, - PTI7_IN_PU, PTI6_IN_PU, PTI4_IN_PU, - PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU, - PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU, - PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, - PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU, - PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, - PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, - PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU, - PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, - PTN4_IN_PU, - PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU, - PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU, - PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU, - PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU, - PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, - PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, - PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, - PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, - PTV3_IN_PU, PTV2_IN_PU, - PTW1_IN_PU, PTW0_IN_PU, - PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, - PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, - PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, - PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, - PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU, - PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU, - PINMUX_INPUT_PULLUP_END, - PINMUX_OUTPUT_BEGIN, PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, @@ -526,7 +486,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { +static const u16 pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), @@ -1114,624 +1074,628 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PTA */ - PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), - PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), - PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), - PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), - PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), - PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), - PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), - PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), + PINMUX_GPIO(PTA7), + PINMUX_GPIO(PTA6), + PINMUX_GPIO(PTA5), + PINMUX_GPIO(PTA4), + PINMUX_GPIO(PTA3), + PINMUX_GPIO(PTA2), + PINMUX_GPIO(PTA1), + PINMUX_GPIO(PTA0), /* PTB */ - PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), - PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), - PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), - PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), - PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), - PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), - PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), - PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), + PINMUX_GPIO(PTB7), + PINMUX_GPIO(PTB6), + PINMUX_GPIO(PTB5), + PINMUX_GPIO(PTB4), + PINMUX_GPIO(PTB3), + PINMUX_GPIO(PTB2), + PINMUX_GPIO(PTB1), + PINMUX_GPIO(PTB0), /* PTC */ - PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), - PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), - PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), - PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), - PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), - PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), - PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), - PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), + PINMUX_GPIO(PTC7), + PINMUX_GPIO(PTC6), + PINMUX_GPIO(PTC5), + PINMUX_GPIO(PTC4), + PINMUX_GPIO(PTC3), + PINMUX_GPIO(PTC2), + PINMUX_GPIO(PTC1), + PINMUX_GPIO(PTC0), /* PTD */ - PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), - PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), - PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), - PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), - PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), - PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), - PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), - PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), + PINMUX_GPIO(PTD7), + PINMUX_GPIO(PTD6), + PINMUX_GPIO(PTD5), + PINMUX_GPIO(PTD4), + PINMUX_GPIO(PTD3), + PINMUX_GPIO(PTD2), + PINMUX_GPIO(PTD1), + PINMUX_GPIO(PTD0), /* PTE */ - PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), - PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), - PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), - PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), - PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), - PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), - PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), - PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), + PINMUX_GPIO(PTE7), + PINMUX_GPIO(PTE6), + PINMUX_GPIO(PTE5), + PINMUX_GPIO(PTE4), + PINMUX_GPIO(PTE3), + PINMUX_GPIO(PTE2), + PINMUX_GPIO(PTE1), + PINMUX_GPIO(PTE0), /* PTF */ - PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), - PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), - PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), - PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), - PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), - PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), - PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), - PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), + PINMUX_GPIO(PTF7), + PINMUX_GPIO(PTF6), + PINMUX_GPIO(PTF5), + PINMUX_GPIO(PTF4), + PINMUX_GPIO(PTF3), + PINMUX_GPIO(PTF2), + PINMUX_GPIO(PTF1), + PINMUX_GPIO(PTF0), /* PTG */ - PINMUX_GPIO(GPIO_PTG7, PTG7_DATA), - PINMUX_GPIO(GPIO_PTG6, PTG6_DATA), - PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), - PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), - PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), - PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), - PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), - PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), + PINMUX_GPIO(PTG7), + PINMUX_GPIO(PTG6), + PINMUX_GPIO(PTG5), + PINMUX_GPIO(PTG4), + PINMUX_GPIO(PTG3), + PINMUX_GPIO(PTG2), + PINMUX_GPIO(PTG1), + PINMUX_GPIO(PTG0), /* PTH */ - PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), - PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), - PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), - PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), - PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), - PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), - PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), - PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), + PINMUX_GPIO(PTH7), + PINMUX_GPIO(PTH6), + PINMUX_GPIO(PTH5), + PINMUX_GPIO(PTH4), + PINMUX_GPIO(PTH3), + PINMUX_GPIO(PTH2), + PINMUX_GPIO(PTH1), + PINMUX_GPIO(PTH0), /* PTI */ - PINMUX_GPIO(GPIO_PTI7, PTI7_DATA), - PINMUX_GPIO(GPIO_PTI6, PTI6_DATA), - PINMUX_GPIO(GPIO_PTI5, PTI5_DATA), - PINMUX_GPIO(GPIO_PTI4, PTI4_DATA), - PINMUX_GPIO(GPIO_PTI3, PTI3_DATA), - PINMUX_GPIO(GPIO_PTI2, PTI2_DATA), - PINMUX_GPIO(GPIO_PTI1, PTI1_DATA), - PINMUX_GPIO(GPIO_PTI0, PTI0_DATA), + PINMUX_GPIO(PTI7), + PINMUX_GPIO(PTI6), + PINMUX_GPIO(PTI5), + PINMUX_GPIO(PTI4), + PINMUX_GPIO(PTI3), + PINMUX_GPIO(PTI2), + PINMUX_GPIO(PTI1), + PINMUX_GPIO(PTI0), /* PTJ */ - PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), - PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), - PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), - PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), - PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), - PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), - PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), + PINMUX_GPIO(PTJ6), + PINMUX_GPIO(PTJ5), + PINMUX_GPIO(PTJ4), + PINMUX_GPIO(PTJ3), + PINMUX_GPIO(PTJ2), + PINMUX_GPIO(PTJ1), + PINMUX_GPIO(PTJ0), /* PTK */ - PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), - PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), - PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), - PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), - PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), - PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), - PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), - PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), + PINMUX_GPIO(PTK7), + PINMUX_GPIO(PTK6), + PINMUX_GPIO(PTK5), + PINMUX_GPIO(PTK4), + PINMUX_GPIO(PTK3), + PINMUX_GPIO(PTK2), + PINMUX_GPIO(PTK1), + PINMUX_GPIO(PTK0), /* PTL */ - PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), - PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), - PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), - PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), - PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), - PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), - PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), + PINMUX_GPIO(PTL6), + PINMUX_GPIO(PTL5), + PINMUX_GPIO(PTL4), + PINMUX_GPIO(PTL3), + PINMUX_GPIO(PTL2), + PINMUX_GPIO(PTL1), + PINMUX_GPIO(PTL0), /* PTM */ - PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), - PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), - PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), - PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), - PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), - PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), - PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), - PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), + PINMUX_GPIO(PTM7), + PINMUX_GPIO(PTM6), + PINMUX_GPIO(PTM5), + PINMUX_GPIO(PTM4), + PINMUX_GPIO(PTM3), + PINMUX_GPIO(PTM2), + PINMUX_GPIO(PTM1), + PINMUX_GPIO(PTM0), /* PTN */ - PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), - PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), - PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), - PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), - PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), - PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), - PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), + PINMUX_GPIO(PTN6), + PINMUX_GPIO(PTN5), + PINMUX_GPIO(PTN4), + PINMUX_GPIO(PTN3), + PINMUX_GPIO(PTN2), + PINMUX_GPIO(PTN1), + PINMUX_GPIO(PTN0), /* PTO */ - PINMUX_GPIO(GPIO_PTO7, PTO7_DATA), - PINMUX_GPIO(GPIO_PTO6, PTO6_DATA), - PINMUX_GPIO(GPIO_PTO5, PTO5_DATA), - PINMUX_GPIO(GPIO_PTO4, PTO4_DATA), - PINMUX_GPIO(GPIO_PTO3, PTO3_DATA), - PINMUX_GPIO(GPIO_PTO2, PTO2_DATA), - PINMUX_GPIO(GPIO_PTO1, PTO1_DATA), - PINMUX_GPIO(GPIO_PTO0, PTO0_DATA), + PINMUX_GPIO(PTO7), + PINMUX_GPIO(PTO6), + PINMUX_GPIO(PTO5), + PINMUX_GPIO(PTO4), + PINMUX_GPIO(PTO3), + PINMUX_GPIO(PTO2), + PINMUX_GPIO(PTO1), + PINMUX_GPIO(PTO0), /* PTP */ - PINMUX_GPIO(GPIO_PTP7, PTP7_DATA), - PINMUX_GPIO(GPIO_PTP6, PTP6_DATA), - PINMUX_GPIO(GPIO_PTP5, PTP5_DATA), - PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), - PINMUX_GPIO(GPIO_PTP3, PTP3_DATA), - PINMUX_GPIO(GPIO_PTP2, PTP2_DATA), - PINMUX_GPIO(GPIO_PTP1, PTP1_DATA), - PINMUX_GPIO(GPIO_PTP0, PTP0_DATA), + PINMUX_GPIO(PTP7), + PINMUX_GPIO(PTP6), + PINMUX_GPIO(PTP5), + PINMUX_GPIO(PTP4), + PINMUX_GPIO(PTP3), + PINMUX_GPIO(PTP2), + PINMUX_GPIO(PTP1), + PINMUX_GPIO(PTP0), /* PTQ */ - PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), - PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), - PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), - PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), - PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), - PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), - PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), + PINMUX_GPIO(PTQ6), + PINMUX_GPIO(PTQ5), + PINMUX_GPIO(PTQ4), + PINMUX_GPIO(PTQ3), + PINMUX_GPIO(PTQ2), + PINMUX_GPIO(PTQ1), + PINMUX_GPIO(PTQ0), /* PTR */ - PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), - PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), - PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), - PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), - PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), - PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), - PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), - PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), + PINMUX_GPIO(PTR7), + PINMUX_GPIO(PTR6), + PINMUX_GPIO(PTR5), + PINMUX_GPIO(PTR4), + PINMUX_GPIO(PTR3), + PINMUX_GPIO(PTR2), + PINMUX_GPIO(PTR1), + PINMUX_GPIO(PTR0), /* PTS */ - PINMUX_GPIO(GPIO_PTS7, PTS7_DATA), - PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), - PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), - PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), - PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), - PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), - PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), - PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), + PINMUX_GPIO(PTS7), + PINMUX_GPIO(PTS6), + PINMUX_GPIO(PTS5), + PINMUX_GPIO(PTS4), + PINMUX_GPIO(PTS3), + PINMUX_GPIO(PTS2), + PINMUX_GPIO(PTS1), + PINMUX_GPIO(PTS0), /* PTT */ - PINMUX_GPIO(GPIO_PTT7, PTT7_DATA), - PINMUX_GPIO(GPIO_PTT6, PTT6_DATA), - PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), - PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), - PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), - PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), - PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), - PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), + PINMUX_GPIO(PTT7), + PINMUX_GPIO(PTT6), + PINMUX_GPIO(PTT5), + PINMUX_GPIO(PTT4), + PINMUX_GPIO(PTT3), + PINMUX_GPIO(PTT2), + PINMUX_GPIO(PTT1), + PINMUX_GPIO(PTT0), /* PTU */ - PINMUX_GPIO(GPIO_PTU7, PTU7_DATA), - PINMUX_GPIO(GPIO_PTU6, PTU6_DATA), - PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), - PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), - PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), - PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), - PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), - PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), + PINMUX_GPIO(PTU7), + PINMUX_GPIO(PTU6), + PINMUX_GPIO(PTU5), + PINMUX_GPIO(PTU4), + PINMUX_GPIO(PTU3), + PINMUX_GPIO(PTU2), + PINMUX_GPIO(PTU1), + PINMUX_GPIO(PTU0), /* PTV */ - PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), - PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), - PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), - PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), - PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), - PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), - PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), - PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), + PINMUX_GPIO(PTV7), + PINMUX_GPIO(PTV6), + PINMUX_GPIO(PTV5), + PINMUX_GPIO(PTV4), + PINMUX_GPIO(PTV3), + PINMUX_GPIO(PTV2), + PINMUX_GPIO(PTV1), + PINMUX_GPIO(PTV0), /* PTW */ - PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), - PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), - PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), - PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), - PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), - PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), - PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), - PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), + PINMUX_GPIO(PTW7), + PINMUX_GPIO(PTW6), + PINMUX_GPIO(PTW5), + PINMUX_GPIO(PTW4), + PINMUX_GPIO(PTW3), + PINMUX_GPIO(PTW2), + PINMUX_GPIO(PTW1), + PINMUX_GPIO(PTW0), /* PTX */ - PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), - PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), - PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), - PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), - PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), - PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), - PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), - PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), + PINMUX_GPIO(PTX7), + PINMUX_GPIO(PTX6), + PINMUX_GPIO(PTX5), + PINMUX_GPIO(PTX4), + PINMUX_GPIO(PTX3), + PINMUX_GPIO(PTX2), + PINMUX_GPIO(PTX1), + PINMUX_GPIO(PTX0), /* PTY */ - PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), - PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), - PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), - PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), - PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), - PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), - PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), - PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), + PINMUX_GPIO(PTY7), + PINMUX_GPIO(PTY6), + PINMUX_GPIO(PTY5), + PINMUX_GPIO(PTY4), + PINMUX_GPIO(PTY3), + PINMUX_GPIO(PTY2), + PINMUX_GPIO(PTY1), + PINMUX_GPIO(PTY0), /* PTZ */ - PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), - PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), - PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), - PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), - PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), - PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), - PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), - PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), + PINMUX_GPIO(PTZ7), + PINMUX_GPIO(PTZ6), + PINMUX_GPIO(PTZ5), + PINMUX_GPIO(PTZ4), + PINMUX_GPIO(PTZ3), + PINMUX_GPIO(PTZ2), + PINMUX_GPIO(PTZ1), + PINMUX_GPIO(PTZ0), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* PTA (mobule: LBSC, RGMII) */ - PINMUX_GPIO(GPIO_FN_BS, BS_MARK), - PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), - PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), - PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), - PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), - PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), - PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), - PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), + GPIO_FN(BS), + GPIO_FN(RDWR), + GPIO_FN(WE1), + GPIO_FN(RDY), + GPIO_FN(ET0_MDC), + GPIO_FN(ET0_MDIO), + GPIO_FN(ET1_MDC), + GPIO_FN(ET1_MDIO), /* PTB (mobule: INTC, ONFI, TMU) */ - PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), - PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), - PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), - PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), - PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), - PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), - PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), - PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), - PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK), - PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK), - PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK), - PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK), - PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK), - PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK), - PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK), - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), + GPIO_FN(IRQ15), + GPIO_FN(IRQ14), + GPIO_FN(IRQ13), + GPIO_FN(IRQ12), + GPIO_FN(IRQ11), + GPIO_FN(IRQ10), + GPIO_FN(IRQ9), + GPIO_FN(IRQ8), + GPIO_FN(ON_NRE), + GPIO_FN(ON_NWE), + GPIO_FN(ON_NWP), + GPIO_FN(ON_NCE0), + GPIO_FN(ON_R_B0), + GPIO_FN(ON_ALE), + GPIO_FN(ON_CLE), + GPIO_FN(TCLK), /* PTC (mobule: IRQ, PWMU) */ - PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), - PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), - PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), - PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK), - PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK), - PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK), - PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK), - PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK), - PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK), + GPIO_FN(IRQ7), + GPIO_FN(IRQ6), + GPIO_FN(IRQ5), + GPIO_FN(IRQ4), + GPIO_FN(IRQ3), + GPIO_FN(IRQ2), + GPIO_FN(IRQ1), + GPIO_FN(IRQ0), + GPIO_FN(PWMU0), + GPIO_FN(PWMU1), + GPIO_FN(PWMU2), + GPIO_FN(PWMU3), + GPIO_FN(PWMU4), + GPIO_FN(PWMU5), /* PTD (mobule: SPI0, DMAC) */ - PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK), - PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + GPIO_FN(SP0_MOSI), + GPIO_FN(SP0_MISO), + GPIO_FN(SP0_SCK), + GPIO_FN(SP0_SCK_FB), + GPIO_FN(SP0_SS0), + GPIO_FN(SP0_SS1), + GPIO_FN(SP0_SS2), + GPIO_FN(SP0_SS3), + GPIO_FN(DREQ0), + GPIO_FN(DACK0), + GPIO_FN(TEND0), /* PTE (mobule: RMII) */ - PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK), + GPIO_FN(RMII0_CRS_DV), + GPIO_FN(RMII0_TXD1), + GPIO_FN(RMII0_TXD0), + GPIO_FN(RMII0_TXEN), + GPIO_FN(RMII0_REFCLK), + GPIO_FN(RMII0_RXD1), + GPIO_FN(RMII0_RXD0), + GPIO_FN(RMII0_RX_ER), /* PTF (mobule: RMII, SerMux) */ - PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK), - PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), + GPIO_FN(RMII1_CRS_DV), + GPIO_FN(RMII1_TXD1), + GPIO_FN(RMII1_TXD0), + GPIO_FN(RMII1_TXEN), + GPIO_FN(RMII1_REFCLK), + GPIO_FN(RMII1_RXD1), + GPIO_FN(RMII1_RXD0), + GPIO_FN(RMII1_RX_ER), + GPIO_FN(RAC_RI), /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ - PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK), - PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), - PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), - PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), - PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), - PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), - PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), + GPIO_FN(BOOTFMS), + GPIO_FN(BOOTWP), + GPIO_FN(A25), + GPIO_FN(A24), + GPIO_FN(SERIRQ), + GPIO_FN(WDTOVF), + GPIO_FN(LPCPD), + GPIO_FN(LDRQ), + GPIO_FN(MMCCLK), + GPIO_FN(MMCCMD), /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ - PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), - PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), - PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), - PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), - PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_WP, WP_MARK), - PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), + GPIO_FN(SP1_MOSI), + GPIO_FN(SP1_MISO), + GPIO_FN(SP1_SCK), + GPIO_FN(SP1_SCK_FB), + GPIO_FN(SP1_SS0), + GPIO_FN(SP1_SS1), + GPIO_FN(WP), + GPIO_FN(FMS0), + GPIO_FN(TEND1), + GPIO_FN(DREQ1), + GPIO_FN(DACK1), + GPIO_FN(ADTRG1), + GPIO_FN(ADTRG0), /* PTI (mobule: LBSC, SDHI) */ - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), - PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), - PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), - PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), - PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), - PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), - PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), - PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), + GPIO_FN(D15), + GPIO_FN(D14), + GPIO_FN(D13), + GPIO_FN(D12), + GPIO_FN(D11), + GPIO_FN(D10), + GPIO_FN(D9), + GPIO_FN(D8), + GPIO_FN(SD_WP), + GPIO_FN(SD_CD), + GPIO_FN(SD_CLK), + GPIO_FN(SD_CMD), + GPIO_FN(SD_D3), + GPIO_FN(SD_D2), + GPIO_FN(SD_D1), + GPIO_FN(SD_D0), /* PTJ (mobule: SCIF234, SERMUX) */ - PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), - PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), - PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), - PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), + GPIO_FN(RTS3), + GPIO_FN(CTS3), + GPIO_FN(TXD3), + GPIO_FN(RXD3), + GPIO_FN(RTS4), + GPIO_FN(RXD4), + GPIO_FN(TXD4), /* PTK (mobule: SERMUX, LBSC, SCIF) */ - PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), - PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), - PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), - PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK), - PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), - PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), - PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), - PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + GPIO_FN(COM2_TXD), + GPIO_FN(COM2_RXD), + GPIO_FN(COM2_RTS), + GPIO_FN(COM2_CTS), + GPIO_FN(COM2_DTR), + GPIO_FN(COM2_DSR), + GPIO_FN(COM2_DCD), + GPIO_FN(CLKOUT), + GPIO_FN(SCK2), + GPIO_FN(SCK4), + GPIO_FN(SCK3), /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ - PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), - PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), - PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), - PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), - PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), - PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), - PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), - PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + GPIO_FN(RAC_RXD), + GPIO_FN(RAC_RTS), + GPIO_FN(RAC_CTS), + GPIO_FN(RAC_DTR), + GPIO_FN(RAC_DSR), + GPIO_FN(RAC_DCD), + GPIO_FN(RAC_TXD), + GPIO_FN(RXD2), + GPIO_FN(CS5), + GPIO_FN(CS6), + GPIO_FN(AUDSYNC), + GPIO_FN(AUDCK), + GPIO_FN(TXD2), /* PTM (mobule: LBSC, IIC) */ - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_RD, RD_MARK), - PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), - PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), - PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), - PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), - PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), - PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), + GPIO_FN(CS4), + GPIO_FN(RD), + GPIO_FN(WE0), + GPIO_FN(CS0), + GPIO_FN(SDA6), + GPIO_FN(SCL6), + GPIO_FN(SDA7), + GPIO_FN(SCL7), /* PTN (mobule: USB, JMC, SGPIO, WDT) */ - PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK), - PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK), - PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), - PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), - PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), - PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), - PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), - PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK), + GPIO_FN(VBUS_EN), + GPIO_FN(VBUS_OC), + GPIO_FN(JMCTCK), + GPIO_FN(JMCTMS), + GPIO_FN(JMCTDO), + GPIO_FN(JMCTDI), + GPIO_FN(JMCTRST), + GPIO_FN(SGPIO1_CLK), + GPIO_FN(SGPIO1_LOAD), + GPIO_FN(SGPIO1_DI), + GPIO_FN(SGPIO1_DO), + GPIO_FN(SUB_CLKIN), /* PTO (mobule: SGPIO, SerMux) */ - PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK), - PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), - PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), + GPIO_FN(SGPIO0_CLK), + GPIO_FN(SGPIO0_LOAD), + GPIO_FN(SGPIO0_DI), + GPIO_FN(SGPIO0_DO), + GPIO_FN(SGPIO2_CLK), + GPIO_FN(SGPIO2_LOAD), + GPIO_FN(SGPIO2_DI), + GPIO_FN(SGPIO2_DO), + GPIO_FN(COM1_TXD), + GPIO_FN(COM1_RXD), + GPIO_FN(COM1_RTS), + GPIO_FN(COM1_CTS), /* PTP (mobule: EVC, ADC) */ /* PTQ (mobule: LPC) */ - PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), - PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK), - PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK), - PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK), - PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK), - PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK), - PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK), + GPIO_FN(LAD3), + GPIO_FN(LAD2), + GPIO_FN(LAD1), + GPIO_FN(LAD0), + GPIO_FN(LFRAME), + GPIO_FN(LRESET), + GPIO_FN(LCLK), /* PTR (mobule: GRA, IIC) */ - PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK), - PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK), - PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK), - PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK), - PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), - PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), - PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), - PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), - PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), - PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + GPIO_FN(DDC3), + GPIO_FN(DDC2), + GPIO_FN(SDA8), + GPIO_FN(SCL8), + GPIO_FN(SDA2), + GPIO_FN(SCL2), + GPIO_FN(SDA1), + GPIO_FN(SCL1), + GPIO_FN(SDA0), + GPIO_FN(SCL0), /* PTS (mobule: GRA, IIC) */ - PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK), - PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK), - PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK), - PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK), - PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK), - PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK), - PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK), - PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK), - PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), - PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), + GPIO_FN(DDC1), + GPIO_FN(DDC0), + GPIO_FN(SDA9), + GPIO_FN(SCL9), + GPIO_FN(SDA5), + GPIO_FN(SCL5), + GPIO_FN(SDA4), + GPIO_FN(SCL4), + GPIO_FN(SDA3), + GPIO_FN(SCL3), /* PTT (mobule: PWMX, AUD) */ - PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK), - PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK), - PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK), - PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK), - PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK), - PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK), - PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK), - PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), - PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + GPIO_FN(PWMX7), + GPIO_FN(PWMX6), + GPIO_FN(PWMX5), + GPIO_FN(PWMX4), + GPIO_FN(PWMX3), + GPIO_FN(PWMX2), + GPIO_FN(PWMX1), + GPIO_FN(PWMX0), + GPIO_FN(AUDATA3), + GPIO_FN(AUDATA2), + GPIO_FN(AUDATA1), + GPIO_FN(AUDATA0), + GPIO_FN(STATUS1), + GPIO_FN(STATUS0), /* PTU (mobule: LPC, APM) */ - PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), - PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK), - PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK), - PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK), - PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK), - PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK), - PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK), - PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK), - PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK), + GPIO_FN(LGPIO7), + GPIO_FN(LGPIO6), + GPIO_FN(LGPIO5), + GPIO_FN(LGPIO4), + GPIO_FN(LGPIO3), + GPIO_FN(LGPIO2), + GPIO_FN(LGPIO1), + GPIO_FN(LGPIO0), + GPIO_FN(APMONCTL_O), + GPIO_FN(APMPWBTOUT_O), + GPIO_FN(APMSCI_O), + GPIO_FN(APMVDDON), + GPIO_FN(APMSLPBTN), + GPIO_FN(APMPWRBTN), + GPIO_FN(APMS5N), + GPIO_FN(APMS3N), /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ - PINMUX_GPIO(GPIO_FN_A23, A23_MARK), - PINMUX_GPIO(GPIO_FN_A22, A22_MARK), - PINMUX_GPIO(GPIO_FN_A21, A21_MARK), - PINMUX_GPIO(GPIO_FN_A20, A20_MARK), - PINMUX_GPIO(GPIO_FN_A19, A19_MARK), - PINMUX_GPIO(GPIO_FN_A18, A18_MARK), - PINMUX_GPIO(GPIO_FN_A17, A17_MARK), - PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK), - PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK), - PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), - PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), - PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK), - PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK), - PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK), - PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK), + GPIO_FN(A23), + GPIO_FN(A22), + GPIO_FN(A21), + GPIO_FN(A20), + GPIO_FN(A19), + GPIO_FN(A18), + GPIO_FN(A17), + GPIO_FN(A16), + GPIO_FN(COM2_RI), + GPIO_FN(R_SPI_MOSI), + GPIO_FN(R_SPI_MISO), + GPIO_FN(R_SPI_RSPCK), + GPIO_FN(R_SPI_SSL0), + GPIO_FN(R_SPI_SSL1), + GPIO_FN(EVENT7), + GPIO_FN(EVENT6), + GPIO_FN(VBIOS_DI), + GPIO_FN(VBIOS_DO), + GPIO_FN(VBIOS_CLK), + GPIO_FN(VBIOS_CS), /* PTW (mobule: LBSC, EVC, SCIF) */ - PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_A15, A15_MARK), - PINMUX_GPIO(GPIO_FN_A14, A14_MARK), - PINMUX_GPIO(GPIO_FN_A13, A13_MARK), - PINMUX_GPIO(GPIO_FN_A12, A12_MARK), - PINMUX_GPIO(GPIO_FN_A11, A11_MARK), - PINMUX_GPIO(GPIO_FN_A10, A10_MARK), - PINMUX_GPIO(GPIO_FN_A9, A9_MARK), - PINMUX_GPIO(GPIO_FN_A8, A8_MARK), - PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), - PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), - PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), - PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), - PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), - PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), - PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), - PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), + GPIO_FN(A16), + GPIO_FN(A15), + GPIO_FN(A14), + GPIO_FN(A13), + GPIO_FN(A12), + GPIO_FN(A11), + GPIO_FN(A10), + GPIO_FN(A9), + GPIO_FN(A8), + GPIO_FN(EVENT5), + GPIO_FN(EVENT4), + GPIO_FN(EVENT3), + GPIO_FN(EVENT2), + GPIO_FN(EVENT1), + GPIO_FN(EVENT0), + GPIO_FN(CTS4), + GPIO_FN(CTS2), /* PTX (mobule: LBSC) */ - PINMUX_GPIO(GPIO_FN_A7, A7_MARK), - PINMUX_GPIO(GPIO_FN_A6, A6_MARK), - PINMUX_GPIO(GPIO_FN_A5, A5_MARK), - PINMUX_GPIO(GPIO_FN_A4, A4_MARK), - PINMUX_GPIO(GPIO_FN_A3, A3_MARK), - PINMUX_GPIO(GPIO_FN_A2, A2_MARK), - PINMUX_GPIO(GPIO_FN_A1, A1_MARK), - PINMUX_GPIO(GPIO_FN_A0, A0_MARK), - PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), - PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), - PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), + GPIO_FN(A7), + GPIO_FN(A6), + GPIO_FN(A5), + GPIO_FN(A4), + GPIO_FN(A3), + GPIO_FN(A2), + GPIO_FN(A1), + GPIO_FN(A0), + GPIO_FN(RTS2), + GPIO_FN(SIM_D), + GPIO_FN(SIM_CLK), + GPIO_FN(SIM_RST), /* PTY (mobule: LBSC) */ - PINMUX_GPIO(GPIO_FN_D7, D7_MARK), - PINMUX_GPIO(GPIO_FN_D6, D6_MARK), - PINMUX_GPIO(GPIO_FN_D5, D5_MARK), - PINMUX_GPIO(GPIO_FN_D4, D4_MARK), - PINMUX_GPIO(GPIO_FN_D3, D3_MARK), - PINMUX_GPIO(GPIO_FN_D2, D2_MARK), - PINMUX_GPIO(GPIO_FN_D1, D1_MARK), - PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + GPIO_FN(D7), + GPIO_FN(D6), + GPIO_FN(D5), + GPIO_FN(D4), + GPIO_FN(D3), + GPIO_FN(D2), + GPIO_FN(D1), + GPIO_FN(D0), /* PTZ (mobule: eMMC, ONFI) */ - PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK), - PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK), + GPIO_FN(MMCDAT7), + GPIO_FN(MMCDAT6), + GPIO_FN(MMCDAT5), + GPIO_FN(MMCDAT4), + GPIO_FN(MMCDAT3), + GPIO_FN(MMCDAT2), + GPIO_FN(MMCDAT1), + GPIO_FN(MMCDAT0), + GPIO_FN(ON_DQ7), + GPIO_FN(ON_DQ6), + GPIO_FN(ON_DQ5), + GPIO_FN(ON_DQ4), + GPIO_FN(ON_DQ3), + GPIO_FN(ON_DQ2), + GPIO_FN(ON_DQ1), + GPIO_FN(ON_DQ0), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { - PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU, - PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU, - PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU, - PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU, - PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU, - PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU, - PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU, - PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU } + PTA7_FN, PTA7_OUT, PTA7_IN, 0, + PTA6_FN, PTA6_OUT, PTA6_IN, 0, + PTA5_FN, PTA5_OUT, PTA5_IN, 0, + PTA4_FN, PTA4_OUT, PTA4_IN, 0, + PTA3_FN, PTA3_OUT, PTA3_IN, 0, + PTA2_FN, PTA2_OUT, PTA2_IN, 0, + PTA1_FN, PTA1_OUT, PTA1_IN, 0, + PTA0_FN, PTA0_OUT, PTA0_IN, 0 } }, { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) { PTB7_FN, PTB7_OUT, PTB7_IN, 0, @@ -1754,100 +1718,100 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTC0_FN, PTC0_OUT, PTC0_IN, 0 } }, { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) { - PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU, - PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU, - PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU, - PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU, - PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU, - PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU, - PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU, - PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU } + PTD7_FN, PTD7_OUT, PTD7_IN, 0, + PTD6_FN, PTD6_OUT, PTD6_IN, 0, + PTD5_FN, PTD5_OUT, PTD5_IN, 0, + PTD4_FN, PTD4_OUT, PTD4_IN, 0, + PTD3_FN, PTD3_OUT, PTD3_IN, 0, + PTD2_FN, PTD2_OUT, PTD2_IN, 0, + PTD1_FN, PTD1_OUT, PTD1_IN, 0, + PTD0_FN, PTD0_OUT, PTD0_IN, 0 } }, { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) { - PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU, - PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU, - PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU, - PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU, - PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU, - PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU, - PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU, - PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU } + PTE7_FN, PTE7_OUT, PTE7_IN, 0, + PTE6_FN, PTE6_OUT, PTE6_IN, 0, + PTE5_FN, PTE5_OUT, PTE5_IN, 0, + PTE4_FN, PTE4_OUT, PTE4_IN, 0, + PTE3_FN, PTE3_OUT, PTE3_IN, 0, + PTE2_FN, PTE2_OUT, PTE2_IN, 0, + PTE1_FN, PTE1_OUT, PTE1_IN, 0, + PTE0_FN, PTE0_OUT, PTE0_IN, 0 } }, { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) { - PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU, - PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU, - PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU, - PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU, - PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU, - PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU, - PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU, - PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU } + PTF7_FN, PTF7_OUT, PTF7_IN, 0, + PTF6_FN, PTF6_OUT, PTF6_IN, 0, + PTF5_FN, PTF5_OUT, PTF5_IN, 0, + PTF4_FN, PTF4_OUT, PTF4_IN, 0, + PTF3_FN, PTF3_OUT, PTF3_IN, 0, + PTF2_FN, PTF2_OUT, PTF2_IN, 0, + PTF1_FN, PTF1_OUT, PTF1_IN, 0, + PTF0_FN, PTF0_OUT, PTF0_IN, 0 } }, { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) { - PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU , - PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU , + PTG7_FN, PTG7_OUT, PTG7_IN, 0, + PTG6_FN, PTG6_OUT, PTG6_IN, 0, PTG5_FN, PTG5_OUT, PTG5_IN, 0, - PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU , + PTG4_FN, PTG4_OUT, PTG4_IN, 0, PTG3_FN, PTG3_OUT, PTG3_IN, 0, PTG2_FN, PTG2_OUT, PTG2_IN, 0, PTG1_FN, PTG1_OUT, PTG1_IN, 0, PTG0_FN, PTG0_OUT, PTG0_IN, 0 } }, { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) { - PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU, - PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU, - PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU, - PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU, - PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU, - PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU, - PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU, - PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU } + PTH7_FN, PTH7_OUT, PTH7_IN, 0, + PTH6_FN, PTH6_OUT, PTH6_IN, 0, + PTH5_FN, PTH5_OUT, PTH5_IN, 0, + PTH4_FN, PTH4_OUT, PTH4_IN, 0, + PTH3_FN, PTH3_OUT, PTH3_IN, 0, + PTH2_FN, PTH2_OUT, PTH2_IN, 0, + PTH1_FN, PTH1_OUT, PTH1_IN, 0, + PTH0_FN, PTH0_OUT, PTH0_IN, 0 } }, { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) { - PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU, - PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU, + PTI7_FN, PTI7_OUT, PTI7_IN, 0, + PTI6_FN, PTI6_OUT, PTI6_IN, 0, PTI5_FN, PTI5_OUT, PTI5_IN, 0, - PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU, - PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU, - PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU, - PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU, - PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU } + PTI4_FN, PTI4_OUT, PTI4_IN, 0, + PTI3_FN, PTI3_OUT, PTI3_IN, 0, + PTI2_FN, PTI2_OUT, PTI2_IN, 0, + PTI1_FN, PTI1_OUT, PTI1_IN, 0, + PTI0_FN, PTI0_OUT, PTI0_IN, 0 } }, { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) { 0, 0, 0, 0, /* reserved: always set 1 */ - PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU, - PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU, - PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU, - PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU, - PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU, - PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU, - PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU } + PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0, + PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0, + PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0, + PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0, + PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0, + PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0, + PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 } }, { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) { - PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU, - PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU, - PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU, - PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU, - PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU, - PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU, - PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU, - PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU } + PTK7_FN, PTK7_OUT, PTK7_IN, 0, + PTK6_FN, PTK6_OUT, PTK6_IN, 0, + PTK5_FN, PTK5_OUT, PTK5_IN, 0, + PTK4_FN, PTK4_OUT, PTK4_IN, 0, + PTK3_FN, PTK3_OUT, PTK3_IN, 0, + PTK2_FN, PTK2_OUT, PTK2_IN, 0, + PTK1_FN, PTK1_OUT, PTK1_IN, 0, + PTK0_FN, PTK0_OUT, PTK0_IN, 0 } }, { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) { 0, 0, 0, 0, /* reserved: always set 1 */ - PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU, - PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU, - PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU, - PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU, - PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU, - PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU, - PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU } + PTL6_FN, PTL6_OUT, PTL6_IN, 0, + PTL5_FN, PTL5_OUT, PTL5_IN, 0, + PTL4_FN, PTL4_OUT, PTL4_IN, 0, + PTL3_FN, PTL3_OUT, PTL3_IN, 0, + PTL2_FN, PTL2_OUT, PTL2_IN, 0, + PTL1_FN, PTL1_OUT, PTL1_IN, 0, + PTL0_FN, PTL0_OUT, PTL0_IN, 0 } }, { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) { - PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU, - PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU, - PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU, - PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU, + PTM7_FN, PTM7_OUT, PTM7_IN, 0, + PTM6_FN, PTM6_OUT, PTM6_IN, 0, + PTM5_FN, PTM5_OUT, PTM5_IN, 0, + PTM4_FN, PTM4_OUT, PTM4_IN, 0, PTM3_FN, PTM3_OUT, PTM3_IN, 0, PTM2_FN, PTM2_OUT, PTM2_IN, 0, PTM1_FN, PTM1_OUT, PTM1_IN, 0, @@ -1857,21 +1821,21 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, /* reserved: always set 1 */ PTN6_FN, PTN6_OUT, PTN6_IN, 0, PTN5_FN, PTN5_OUT, PTN5_IN, 0, - PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU, - PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU, - PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU, - PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU, - PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU } + PTN4_FN, PTN4_OUT, PTN4_IN, 0, + PTN3_FN, PTN3_OUT, PTN3_IN, 0, + PTN2_FN, PTN2_OUT, PTN2_IN, 0, + PTN1_FN, PTN1_OUT, PTN1_IN, 0, + PTN0_FN, PTN0_OUT, PTN0_IN, 0 } }, { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) { - PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU, - PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU, - PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU, - PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU, - PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU, - PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU, - PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU, - PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU } + PTO7_FN, PTO7_OUT, PTO7_IN, 0, + PTO6_FN, PTO6_OUT, PTO6_IN, 0, + PTO5_FN, PTO5_OUT, PTO5_IN, 0, + PTO4_FN, PTO4_OUT, PTO4_IN, 0, + PTO3_FN, PTO3_OUT, PTO3_IN, 0, + PTO2_FN, PTO2_OUT, PTO2_IN, 0, + PTO1_FN, PTO1_OUT, PTO1_IN, 0, + PTO0_FN, PTO0_OUT, PTO0_IN, 0 } }, #if 0 /* FIXME: Remove it? */ { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) { @@ -1916,32 +1880,32 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTS0_FN, PTS0_OUT, PTS0_IN, 0 } }, { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) { - PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU, - PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU, - PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU, - PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU, - PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU, - PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU, - PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU, - PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU } + PTT7_FN, PTT7_OUT, PTT7_IN, 0, + PTT6_FN, PTT6_OUT, PTT6_IN, 0, + PTT5_FN, PTT5_OUT, PTT5_IN, 0, + PTT4_FN, PTT4_OUT, PTT4_IN, 0, + PTT3_FN, PTT3_OUT, PTT3_IN, 0, + PTT2_FN, PTT2_OUT, PTT2_IN, 0, + PTT1_FN, PTT1_OUT, PTT1_IN, 0, + PTT0_FN, PTT0_OUT, PTT0_IN, 0 } }, { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) { - PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU, - PTU6_FN, PTU6_OUT, PTU6_IN, PTU6_IN_PU, - PTU5_FN, PTU5_OUT, PTU5_IN, PTU5_IN_PU, - PTU4_FN, PTU4_OUT, PTU4_IN, PTU4_IN_PU, - PTU3_FN, PTU3_OUT, PTU3_IN, PTU3_IN_PU, - PTU2_FN, PTU2_OUT, PTU2_IN, PTU2_IN_PU, - PTU1_FN, PTU1_OUT, PTU1_IN, PTU1_IN_PU, - PTU0_FN, PTU0_OUT, PTU0_IN, PTU0_IN_PU } + PTU7_FN, PTU7_OUT, PTU7_IN, 0, + PTU6_FN, PTU6_OUT, PTU6_IN, 0, + PTU5_FN, PTU5_OUT, PTU5_IN, 0, + PTU4_FN, PTU4_OUT, PTU4_IN, 0, + PTU3_FN, PTU3_OUT, PTU3_IN, 0, + PTU2_FN, PTU2_OUT, PTU2_IN, 0, + PTU1_FN, PTU1_OUT, PTU1_IN, 0, + PTU0_FN, PTU0_OUT, PTU0_IN, 0 } }, { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) { - PTV7_FN, PTV7_OUT, PTV7_IN, PTV7_IN_PU, - PTV6_FN, PTV6_OUT, PTV6_IN, PTV6_IN_PU, - PTV5_FN, PTV5_OUT, PTV5_IN, PTV5_IN_PU, - PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU, - PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU, - PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU, + PTV7_FN, PTV7_OUT, PTV7_IN, 0, + PTV6_FN, PTV6_OUT, PTV6_IN, 0, + PTV5_FN, PTV5_OUT, PTV5_IN, 0, + PTV4_FN, PTV4_OUT, PTV4_IN, 0, + PTV3_FN, PTV3_OUT, PTV3_IN, 0, + PTV2_FN, PTV2_OUT, PTV2_IN, 0, PTV1_FN, PTV1_OUT, PTV1_IN, 0, PTV0_FN, PTV0_OUT, PTV0_IN, 0 } }, @@ -1952,28 +1916,28 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTW4_FN, PTW4_OUT, PTW4_IN, 0, PTW3_FN, PTW3_OUT, PTW3_IN, 0, PTW2_FN, PTW2_OUT, PTW2_IN, 0, - PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU, - PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU } + PTW1_FN, PTW1_OUT, PTW1_IN, 0, + PTW0_FN, PTW0_OUT, PTW0_IN, 0 } }, { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) { - PTX7_FN, PTX7_OUT, PTX7_IN, PTX7_IN_PU, - PTX6_FN, PTX6_OUT, PTX6_IN, PTX6_IN_PU, - PTX5_FN, PTX5_OUT, PTX5_IN, PTX5_IN_PU, - PTX4_FN, PTX4_OUT, PTX4_IN, PTX4_IN_PU, - PTX3_FN, PTX3_OUT, PTX3_IN, PTX3_IN_PU, - PTX2_FN, PTX2_OUT, PTX2_IN, PTX2_IN_PU, - PTX1_FN, PTX1_OUT, PTX1_IN, PTX1_IN_PU, - PTX0_FN, PTX0_OUT, PTX0_IN, PTX0_IN_PU } + PTX7_FN, PTX7_OUT, PTX7_IN, 0, + PTX6_FN, PTX6_OUT, PTX6_IN, 0, + PTX5_FN, PTX5_OUT, PTX5_IN, 0, + PTX4_FN, PTX4_OUT, PTX4_IN, 0, + PTX3_FN, PTX3_OUT, PTX3_IN, 0, + PTX2_FN, PTX2_OUT, PTX2_IN, 0, + PTX1_FN, PTX1_OUT, PTX1_IN, 0, + PTX0_FN, PTX0_OUT, PTX0_IN, 0 } }, { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) { - PTY7_FN, PTY7_OUT, PTY7_IN, PTY7_IN_PU, - PTY6_FN, PTY6_OUT, PTY6_IN, PTY6_IN_PU, - PTY5_FN, PTY5_OUT, PTY5_IN, PTY5_IN_PU, - PTY4_FN, PTY4_OUT, PTY4_IN, PTY4_IN_PU, - PTY3_FN, PTY3_OUT, PTY3_IN, PTY3_IN_PU, - PTY2_FN, PTY2_OUT, PTY2_IN, PTY2_IN_PU, - PTY1_FN, PTY1_OUT, PTY1_IN, PTY1_IN_PU, - PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU } + PTY7_FN, PTY7_OUT, PTY7_IN, 0, + PTY6_FN, PTY6_OUT, PTY6_IN, 0, + PTY5_FN, PTY5_OUT, PTY5_IN, 0, + PTY4_FN, PTY4_OUT, PTY4_IN, 0, + PTY3_FN, PTY3_OUT, PTY3_IN, 0, + PTY2_FN, PTY2_OUT, PTY2_IN, 0, + PTY1_FN, PTY1_OUT, PTY1_IN, 0, + PTY0_FN, PTY0_OUT, PTY0_IN, 0 } }, { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) { PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0, @@ -2152,7 +2116,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xffec0034, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -2260,20 +2224,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7757_pinmux_info = { +const struct sh_pfc_soc_info sh7757_pinmux_info = { .name = "sh7757_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA0, - .last_gpio = GPIO_FN_ON_DQ0, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index 3b1825d925b..b38dd7e3e37 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -77,36 +77,6 @@ enum { PR3_IN, PR2_IN, PR1_IN, PR0_IN, PINMUX_INPUT_END, - PINMUX_INPUT_PULLUP_BEGIN, - PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, - PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, - PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, - PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, - PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, - PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, - PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, - PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, - PE5_IN_PU, PE4_IN_PU, PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU, - PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, - PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, - PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU, - PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU, - PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU, - PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, - PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU, - PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU, PJ0_IN_PU, - PK7_IN_PU, PK6_IN_PU, PK5_IN_PU, PK4_IN_PU, - PK3_IN_PU, PK2_IN_PU, PK1_IN_PU, PK0_IN_PU, - PL7_IN_PU, PL6_IN_PU, PL5_IN_PU, PL4_IN_PU, - PL3_IN_PU, PL2_IN_PU, PL1_IN_PU, PL0_IN_PU, - PM1_IN_PU, PM0_IN_PU, - PN7_IN_PU, PN6_IN_PU, PN5_IN_PU, PN4_IN_PU, - PN3_IN_PU, PN2_IN_PU, PN1_IN_PU, PN0_IN_PU, - PP5_IN_PU, PP4_IN_PU, PP3_IN_PU, PP2_IN_PU, PP1_IN_PU, PP0_IN_PU, - PQ4_IN_PU, PQ3_IN_PU, PQ2_IN_PU, PQ1_IN_PU, PQ0_IN_PU, - PR3_IN_PU, PR2_IN_PU, PR1_IN_PU, PR0_IN_PU, - PINMUX_INPUT_PULLUP_END, - PINMUX_OUTPUT_BEGIN, PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, @@ -355,150 +325,149 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { - +static const u16 pinmux_data[] = { /* PA GPIO */ - PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), - PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), - PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), - PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), - PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), - PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), - PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), - PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), + PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), + PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), + PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), + PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), + PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), + PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), + PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), + PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), /* PB GPIO */ - PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), - PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), - PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), - PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), - PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), - PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), - PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), - PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), + PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), + PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), + PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), + PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), + PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), + PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), + PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), + PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), /* PC GPIO */ - PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), - PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), - PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), - PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), - PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), - PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), - PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), - PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), + PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), + PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), + PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), + PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), + PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), + PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), + PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), + PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), /* PD GPIO */ - PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), - PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), - PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), - PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), - PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), - PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), - PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), - PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), + PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), + PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), + PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), + PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), + PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), + PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), + PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), + PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), /* PE GPIO */ - PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU), - PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU), - PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU), - PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU), - PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU), - PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU), + PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT), + PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT), + PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT), + PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT), + PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT), + PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT), /* PF GPIO */ - PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), - PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), - PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), - PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), - PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), - PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), - PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), - PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), + PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), + PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), + PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), + PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), + PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), + PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), + PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), + PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), /* PG GPIO */ - PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), - PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), - PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), - PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU), - PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU), - PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU), - PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU), - PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU), + PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), + PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), + PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), + PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT), + PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT), + PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT), + PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT), + PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT), /* PH GPIO */ - PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU), - PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU), - PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), - PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), - PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), - PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), - PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), - PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), + PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT), + PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT), + PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), + PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), + PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), + PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), + PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), + PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), /* PJ GPIO */ - PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU), - PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU), - PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU), - PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU), - PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU), - PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU), - PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU), - PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT, PJ0_IN_PU), + PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT), + PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT), + PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT), + PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT), + PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT), + PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT), + PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT), + PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT), /* PK GPIO */ - PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT, PK7_IN_PU), - PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT, PK6_IN_PU), - PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT, PK5_IN_PU), - PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT, PK4_IN_PU), - PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT, PK3_IN_PU), - PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT, PK2_IN_PU), - PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT, PK1_IN_PU), - PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT, PK0_IN_PU), + PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT), + PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT), + PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT), + PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT), + PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT), + PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT), + PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT), + PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT), /* PL GPIO */ - PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT, PL7_IN_PU), - PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT, PL6_IN_PU), - PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT, PL5_IN_PU), - PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT, PL4_IN_PU), - PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT, PL3_IN_PU), - PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT, PL2_IN_PU), - PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT, PL1_IN_PU), - PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT, PL0_IN_PU), + PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT), + PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT), + PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT), + PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT), + PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT), + PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT), + PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT), + PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT), /* PM GPIO */ - PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT, PM1_IN_PU), - PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT, PM0_IN_PU), + PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT), + PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT), /* PN GPIO */ - PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT, PN7_IN_PU), - PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT, PN6_IN_PU), - PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT, PN5_IN_PU), - PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT, PN4_IN_PU), - PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT, PN3_IN_PU), - PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT, PN2_IN_PU), - PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT, PN1_IN_PU), - PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT, PN0_IN_PU), + PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT), + PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT), + PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT), + PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT), + PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT), + PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT), + PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT), + PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT), /* PP GPIO */ - PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT, PP5_IN_PU), - PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT, PP4_IN_PU), - PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT, PP3_IN_PU), - PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT, PP2_IN_PU), - PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT, PP1_IN_PU), - PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT, PP0_IN_PU), + PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT), + PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT), + PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT), + PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT), + PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT), + PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT), /* PQ GPIO */ - PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT, PQ4_IN_PU), - PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT, PQ3_IN_PU), - PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT, PQ2_IN_PU), - PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT, PQ1_IN_PU), - PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT, PQ0_IN_PU), + PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT), + PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT), + PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT), + PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT), + PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT), /* PR GPIO */ - PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT, PR3_IN_PU), - PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT, PR2_IN_PU), - PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT, PR1_IN_PU), - PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT, PR0_IN_PU), + PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT), + PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT), + PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT), + PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT), /* PA FN */ PINMUX_DATA(D63_AD31_MARK, PA7_FN), @@ -702,428 +671,432 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PA */ - PINMUX_GPIO(GPIO_PA7, PA7_DATA), - PINMUX_GPIO(GPIO_PA6, PA6_DATA), - PINMUX_GPIO(GPIO_PA5, PA5_DATA), - PINMUX_GPIO(GPIO_PA4, PA4_DATA), - PINMUX_GPIO(GPIO_PA3, PA3_DATA), - PINMUX_GPIO(GPIO_PA2, PA2_DATA), - PINMUX_GPIO(GPIO_PA1, PA1_DATA), - PINMUX_GPIO(GPIO_PA0, PA0_DATA), + PINMUX_GPIO(PA7), + PINMUX_GPIO(PA6), + PINMUX_GPIO(PA5), + PINMUX_GPIO(PA4), + PINMUX_GPIO(PA3), + PINMUX_GPIO(PA2), + PINMUX_GPIO(PA1), + PINMUX_GPIO(PA0), /* PB */ - PINMUX_GPIO(GPIO_PB7, PB7_DATA), - PINMUX_GPIO(GPIO_PB6, PB6_DATA), - PINMUX_GPIO(GPIO_PB5, PB5_DATA), - PINMUX_GPIO(GPIO_PB4, PB4_DATA), - PINMUX_GPIO(GPIO_PB3, PB3_DATA), - PINMUX_GPIO(GPIO_PB2, PB2_DATA), - PINMUX_GPIO(GPIO_PB1, PB1_DATA), - PINMUX_GPIO(GPIO_PB0, PB0_DATA), + PINMUX_GPIO(PB7), + PINMUX_GPIO(PB6), + PINMUX_GPIO(PB5), + PINMUX_GPIO(PB4), + PINMUX_GPIO(PB3), + PINMUX_GPIO(PB2), + PINMUX_GPIO(PB1), + PINMUX_GPIO(PB0), /* PC */ - PINMUX_GPIO(GPIO_PC7, PC7_DATA), - PINMUX_GPIO(GPIO_PC6, PC6_DATA), - PINMUX_GPIO(GPIO_PC5, PC5_DATA), - PINMUX_GPIO(GPIO_PC4, PC4_DATA), - PINMUX_GPIO(GPIO_PC3, PC3_DATA), - PINMUX_GPIO(GPIO_PC2, PC2_DATA), - PINMUX_GPIO(GPIO_PC1, PC1_DATA), - PINMUX_GPIO(GPIO_PC0, PC0_DATA), + PINMUX_GPIO(PC7), + PINMUX_GPIO(PC6), + PINMUX_GPIO(PC5), + PINMUX_GPIO(PC4), + PINMUX_GPIO(PC3), + PINMUX_GPIO(PC2), + PINMUX_GPIO(PC1), + PINMUX_GPIO(PC0), /* PD */ - PINMUX_GPIO(GPIO_PD7, PD7_DATA), - PINMUX_GPIO(GPIO_PD6, PD6_DATA), - PINMUX_GPIO(GPIO_PD5, PD5_DATA), - PINMUX_GPIO(GPIO_PD4, PD4_DATA), - PINMUX_GPIO(GPIO_PD3, PD3_DATA), - PINMUX_GPIO(GPIO_PD2, PD2_DATA), - PINMUX_GPIO(GPIO_PD1, PD1_DATA), - PINMUX_GPIO(GPIO_PD0, PD0_DATA), + PINMUX_GPIO(PD7), + PINMUX_GPIO(PD6), + PINMUX_GPIO(PD5), + PINMUX_GPIO(PD4), + PINMUX_GPIO(PD3), + PINMUX_GPIO(PD2), + PINMUX_GPIO(PD1), + PINMUX_GPIO(PD0), /* PE */ - PINMUX_GPIO(GPIO_PE5, PE5_DATA), - PINMUX_GPIO(GPIO_PE4, PE4_DATA), - PINMUX_GPIO(GPIO_PE3, PE3_DATA), - PINMUX_GPIO(GPIO_PE2, PE2_DATA), - PINMUX_GPIO(GPIO_PE1, PE1_DATA), - PINMUX_GPIO(GPIO_PE0, PE0_DATA), + PINMUX_GPIO(PE5), + PINMUX_GPIO(PE4), + PINMUX_GPIO(PE3), + PINMUX_GPIO(PE2), + PINMUX_GPIO(PE1), + PINMUX_GPIO(PE0), /* PF */ - PINMUX_GPIO(GPIO_PF7, PF7_DATA), - PINMUX_GPIO(GPIO_PF6, PF6_DATA), - PINMUX_GPIO(GPIO_PF5, PF5_DATA), - PINMUX_GPIO(GPIO_PF4, PF4_DATA), - PINMUX_GPIO(GPIO_PF3, PF3_DATA), - PINMUX_GPIO(GPIO_PF2, PF2_DATA), - PINMUX_GPIO(GPIO_PF1, PF1_DATA), - PINMUX_GPIO(GPIO_PF0, PF0_DATA), + PINMUX_GPIO(PF7), + PINMUX_GPIO(PF6), + PINMUX_GPIO(PF5), + PINMUX_GPIO(PF4), + PINMUX_GPIO(PF3), + PINMUX_GPIO(PF2), + PINMUX_GPIO(PF1), + PINMUX_GPIO(PF0), /* PG */ - PINMUX_GPIO(GPIO_PG7, PG7_DATA), - PINMUX_GPIO(GPIO_PG6, PG6_DATA), - PINMUX_GPIO(GPIO_PG5, PG5_DATA), - PINMUX_GPIO(GPIO_PG4, PG4_DATA), - PINMUX_GPIO(GPIO_PG3, PG3_DATA), - PINMUX_GPIO(GPIO_PG2, PG2_DATA), - PINMUX_GPIO(GPIO_PG1, PG1_DATA), - PINMUX_GPIO(GPIO_PG0, PG0_DATA), + PINMUX_GPIO(PG7), + PINMUX_GPIO(PG6), + PINMUX_GPIO(PG5), + PINMUX_GPIO(PG4), + PINMUX_GPIO(PG3), + PINMUX_GPIO(PG2), + PINMUX_GPIO(PG1), + PINMUX_GPIO(PG0), /* PH */ - PINMUX_GPIO(GPIO_PH7, PH7_DATA), - PINMUX_GPIO(GPIO_PH6, PH6_DATA), - PINMUX_GPIO(GPIO_PH5, PH5_DATA), - PINMUX_GPIO(GPIO_PH4, PH4_DATA), - PINMUX_GPIO(GPIO_PH3, PH3_DATA), - PINMUX_GPIO(GPIO_PH2, PH2_DATA), - PINMUX_GPIO(GPIO_PH1, PH1_DATA), - PINMUX_GPIO(GPIO_PH0, PH0_DATA), + PINMUX_GPIO(PH7), + PINMUX_GPIO(PH6), + PINMUX_GPIO(PH5), + PINMUX_GPIO(PH4), + PINMUX_GPIO(PH3), + PINMUX_GPIO(PH2), + PINMUX_GPIO(PH1), + PINMUX_GPIO(PH0), /* PJ */ - PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), - PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), - PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), - PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), - PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), - PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), - PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), - PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), + PINMUX_GPIO(PJ7), + PINMUX_GPIO(PJ6), + PINMUX_GPIO(PJ5), + PINMUX_GPIO(PJ4), + PINMUX_GPIO(PJ3), + PINMUX_GPIO(PJ2), + PINMUX_GPIO(PJ1), + PINMUX_GPIO(PJ0), /* PK */ - PINMUX_GPIO(GPIO_PK7, PK7_DATA), - PINMUX_GPIO(GPIO_PK6, PK6_DATA), - PINMUX_GPIO(GPIO_PK5, PK5_DATA), - PINMUX_GPIO(GPIO_PK4, PK4_DATA), - PINMUX_GPIO(GPIO_PK3, PK3_DATA), - PINMUX_GPIO(GPIO_PK2, PK2_DATA), - PINMUX_GPIO(GPIO_PK1, PK1_DATA), - PINMUX_GPIO(GPIO_PK0, PK0_DATA), + PINMUX_GPIO(PK7), + PINMUX_GPIO(PK6), + PINMUX_GPIO(PK5), + PINMUX_GPIO(PK4), + PINMUX_GPIO(PK3), + PINMUX_GPIO(PK2), + PINMUX_GPIO(PK1), + PINMUX_GPIO(PK0), /* PL */ - PINMUX_GPIO(GPIO_PL7, PL7_DATA), - PINMUX_GPIO(GPIO_PL6, PL6_DATA), - PINMUX_GPIO(GPIO_PL5, PL5_DATA), - PINMUX_GPIO(GPIO_PL4, PL4_DATA), - PINMUX_GPIO(GPIO_PL3, PL3_DATA), - PINMUX_GPIO(GPIO_PL2, PL2_DATA), - PINMUX_GPIO(GPIO_PL1, PL1_DATA), - PINMUX_GPIO(GPIO_PL0, PL0_DATA), + PINMUX_GPIO(PL7), + PINMUX_GPIO(PL6), + PINMUX_GPIO(PL5), + PINMUX_GPIO(PL4), + PINMUX_GPIO(PL3), + PINMUX_GPIO(PL2), + PINMUX_GPIO(PL1), + PINMUX_GPIO(PL0), /* PM */ - PINMUX_GPIO(GPIO_PM1, PM1_DATA), - PINMUX_GPIO(GPIO_PM0, PM0_DATA), + PINMUX_GPIO(PM1), + PINMUX_GPIO(PM0), /* PN */ - PINMUX_GPIO(GPIO_PN7, PN7_DATA), - PINMUX_GPIO(GPIO_PN6, PN6_DATA), - PINMUX_GPIO(GPIO_PN5, PN5_DATA), - PINMUX_GPIO(GPIO_PN4, PN4_DATA), - PINMUX_GPIO(GPIO_PN3, PN3_DATA), - PINMUX_GPIO(GPIO_PN2, PN2_DATA), - PINMUX_GPIO(GPIO_PN1, PN1_DATA), - PINMUX_GPIO(GPIO_PN0, PN0_DATA), + PINMUX_GPIO(PN7), + PINMUX_GPIO(PN6), + PINMUX_GPIO(PN5), + PINMUX_GPIO(PN4), + PINMUX_GPIO(PN3), + PINMUX_GPIO(PN2), + PINMUX_GPIO(PN1), + PINMUX_GPIO(PN0), /* PP */ - PINMUX_GPIO(GPIO_PP5, PP5_DATA), - PINMUX_GPIO(GPIO_PP4, PP4_DATA), - PINMUX_GPIO(GPIO_PP3, PP3_DATA), - PINMUX_GPIO(GPIO_PP2, PP2_DATA), - PINMUX_GPIO(GPIO_PP1, PP1_DATA), - PINMUX_GPIO(GPIO_PP0, PP0_DATA), + PINMUX_GPIO(PP5), + PINMUX_GPIO(PP4), + PINMUX_GPIO(PP3), + PINMUX_GPIO(PP2), + PINMUX_GPIO(PP1), + PINMUX_GPIO(PP0), /* PQ */ - PINMUX_GPIO(GPIO_PQ4, PQ4_DATA), - PINMUX_GPIO(GPIO_PQ3, PQ3_DATA), - PINMUX_GPIO(GPIO_PQ2, PQ2_DATA), - PINMUX_GPIO(GPIO_PQ1, PQ1_DATA), - PINMUX_GPIO(GPIO_PQ0, PQ0_DATA), + PINMUX_GPIO(PQ4), + PINMUX_GPIO(PQ3), + PINMUX_GPIO(PQ2), + PINMUX_GPIO(PQ1), + PINMUX_GPIO(PQ0), /* PR */ - PINMUX_GPIO(GPIO_PR3, PR3_DATA), - PINMUX_GPIO(GPIO_PR2, PR2_DATA), - PINMUX_GPIO(GPIO_PR1, PR1_DATA), - PINMUX_GPIO(GPIO_PR0, PR0_DATA), + PINMUX_GPIO(PR3), + PINMUX_GPIO(PR2), + PINMUX_GPIO(PR1), + PINMUX_GPIO(PR0), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* FN */ - PINMUX_GPIO(GPIO_FN_D63_AD31, D63_AD31_MARK), - PINMUX_GPIO(GPIO_FN_D62_AD30, D62_AD30_MARK), - PINMUX_GPIO(GPIO_FN_D61_AD29, D61_AD29_MARK), - PINMUX_GPIO(GPIO_FN_D60_AD28, D60_AD28_MARK), - PINMUX_GPIO(GPIO_FN_D59_AD27, D59_AD27_MARK), - PINMUX_GPIO(GPIO_FN_D58_AD26, D58_AD26_MARK), - PINMUX_GPIO(GPIO_FN_D57_AD25, D57_AD25_MARK), - PINMUX_GPIO(GPIO_FN_D56_AD24, D56_AD24_MARK), - PINMUX_GPIO(GPIO_FN_D55_AD23, D55_AD23_MARK), - PINMUX_GPIO(GPIO_FN_D54_AD22, D54_AD22_MARK), - PINMUX_GPIO(GPIO_FN_D53_AD21, D53_AD21_MARK), - PINMUX_GPIO(GPIO_FN_D52_AD20, D52_AD20_MARK), - PINMUX_GPIO(GPIO_FN_D51_AD19, D51_AD19_MARK), - PINMUX_GPIO(GPIO_FN_D50_AD18, D50_AD18_MARK), - PINMUX_GPIO(GPIO_FN_D49_AD17_DB5, D49_AD17_DB5_MARK), - PINMUX_GPIO(GPIO_FN_D48_AD16_DB4, D48_AD16_DB4_MARK), - PINMUX_GPIO(GPIO_FN_D47_AD15_DB3, D47_AD15_DB3_MARK), - PINMUX_GPIO(GPIO_FN_D46_AD14_DB2, D46_AD14_DB2_MARK), - PINMUX_GPIO(GPIO_FN_D45_AD13_DB1, D45_AD13_DB1_MARK), - PINMUX_GPIO(GPIO_FN_D44_AD12_DB0, D44_AD12_DB0_MARK), - PINMUX_GPIO(GPIO_FN_D43_AD11_DG5, D43_AD11_DG5_MARK), - PINMUX_GPIO(GPIO_FN_D42_AD10_DG4, D42_AD10_DG4_MARK), - PINMUX_GPIO(GPIO_FN_D41_AD9_DG3, D41_AD9_DG3_MARK), - PINMUX_GPIO(GPIO_FN_D40_AD8_DG2, D40_AD8_DG2_MARK), - PINMUX_GPIO(GPIO_FN_D39_AD7_DG1, D39_AD7_DG1_MARK), - PINMUX_GPIO(GPIO_FN_D38_AD6_DG0, D38_AD6_DG0_MARK), - PINMUX_GPIO(GPIO_FN_D37_AD5_DR5, D37_AD5_DR5_MARK), - PINMUX_GPIO(GPIO_FN_D36_AD4_DR4, D36_AD4_DR4_MARK), - PINMUX_GPIO(GPIO_FN_D35_AD3_DR3, D35_AD3_DR3_MARK), - PINMUX_GPIO(GPIO_FN_D34_AD2_DR2, D34_AD2_DR2_MARK), - PINMUX_GPIO(GPIO_FN_D33_AD1_DR1, D33_AD1_DR1_MARK), - PINMUX_GPIO(GPIO_FN_D32_AD0_DR0, D32_AD0_DR0_MARK), - PINMUX_GPIO(GPIO_FN_REQ1, REQ1_MARK), - PINMUX_GPIO(GPIO_FN_REQ2, REQ2_MARK), - PINMUX_GPIO(GPIO_FN_REQ3, REQ3_MARK), - PINMUX_GPIO(GPIO_FN_GNT1, GNT1_MARK), - PINMUX_GPIO(GPIO_FN_GNT2, GNT2_MARK), - PINMUX_GPIO(GPIO_FN_GNT3, GNT3_MARK), - PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_INTD, INTD_MARK), - PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), - PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), - PINMUX_GPIO(GPIO_FN_FRE, FRE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), - PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_TXD_PJ, SIOF_TXD_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_RXD_PJ, SIOF_RXD_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_SYNC_PJ, SIOF_SYNC_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_MCLK_PJ, SIOF_MCLK_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_SCK_PJ, SIOF_SCK_PJ_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0_PK3, DRAK0_PK3_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1_PK2, DRAK1_PK2_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), - PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_TXD_PK, SIOF_TXD_PK_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), - PINMUX_GPIO(GPIO_FN_MMCDAT, MMCDAT_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_SCK_PK, SIOF_SCK_PK_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0_PK1, DRAK0_PK1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1_PK0, DRAK1_PK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_INTB, INTB_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), - PINMUX_GPIO(GPIO_FN_INTC, INTC_MARK), - PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), - PINMUX_GPIO(GPIO_FN_FD4, FD4_MARK), - PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), - PINMUX_GPIO(GPIO_FN_FD5, FD5_MARK), - PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), - PINMUX_GPIO(GPIO_FN_FD6, FD6_MARK), - PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), - PINMUX_GPIO(GPIO_FN_FD7, FD7_MARK), - PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_BREQ_BSACK, BREQ_BSACK_MARK), - PINMUX_GPIO(GPIO_FN_BACK_BSREQ, BACK_BSREQ_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), - PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), - PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FD0, FD0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), - PINMUX_GPIO(GPIO_FN_FD1, FD1_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), - PINMUX_GPIO(GPIO_FN_FD2, FD2_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FD3, FD3_MARK), - PINMUX_GPIO(GPIO_FN_DEVSEL_DCLKOUT, DEVSEL_DCLKOUT_MARK), - PINMUX_GPIO(GPIO_FN_STOP_CDE, STOP_CDE_MARK), - PINMUX_GPIO(GPIO_FN_LOCK_ODDF, LOCK_ODDF_MARK), - PINMUX_GPIO(GPIO_FN_TRDY_DISPL, TRDY_DISPL_MARK), - PINMUX_GPIO(GPIO_FN_IRDY_HSYNC, IRDY_HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_PCIFRAME_VSYNC, PCIFRAME_VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_INTA, INTA_MARK), - PINMUX_GPIO(GPIO_FN_GNT0_GNTIN, GNT0_GNTIN_MARK), - PINMUX_GPIO(GPIO_FN_REQ0_REQOUT, REQ0_REQOUT_MARK), - PINMUX_GPIO(GPIO_FN_PERR, PERR_MARK), - PINMUX_GPIO(GPIO_FN_SERR, SERR_MARK), - PINMUX_GPIO(GPIO_FN_WE7_CBE3, WE7_CBE3_MARK), - PINMUX_GPIO(GPIO_FN_WE6_CBE2, WE6_CBE2_MARK), - PINMUX_GPIO(GPIO_FN_WE5_CBE1, WE5_CBE1_MARK), - PINMUX_GPIO(GPIO_FN_WE4_CBE0, WE4_CBE0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SIOF_RXD, SIOF_RXD_MARK), - PINMUX_GPIO(GPIO_FN_MRESETOUT, MRESETOUT_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), + GPIO_FN(D63_AD31), + GPIO_FN(D62_AD30), + GPIO_FN(D61_AD29), + GPIO_FN(D60_AD28), + GPIO_FN(D59_AD27), + GPIO_FN(D58_AD26), + GPIO_FN(D57_AD25), + GPIO_FN(D56_AD24), + GPIO_FN(D55_AD23), + GPIO_FN(D54_AD22), + GPIO_FN(D53_AD21), + GPIO_FN(D52_AD20), + GPIO_FN(D51_AD19), + GPIO_FN(D50_AD18), + GPIO_FN(D49_AD17_DB5), + GPIO_FN(D48_AD16_DB4), + GPIO_FN(D47_AD15_DB3), + GPIO_FN(D46_AD14_DB2), + GPIO_FN(D45_AD13_DB1), + GPIO_FN(D44_AD12_DB0), + GPIO_FN(D43_AD11_DG5), + GPIO_FN(D42_AD10_DG4), + GPIO_FN(D41_AD9_DG3), + GPIO_FN(D40_AD8_DG2), + GPIO_FN(D39_AD7_DG1), + GPIO_FN(D38_AD6_DG0), + GPIO_FN(D37_AD5_DR5), + GPIO_FN(D36_AD4_DR4), + GPIO_FN(D35_AD3_DR3), + GPIO_FN(D34_AD2_DR2), + GPIO_FN(D33_AD1_DR1), + GPIO_FN(D32_AD0_DR0), + GPIO_FN(REQ1), + GPIO_FN(REQ2), + GPIO_FN(REQ3), + GPIO_FN(GNT1), + GPIO_FN(GNT2), + GPIO_FN(GNT3), + GPIO_FN(MMCCLK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(SCIF1_SCK), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_TXD), + GPIO_FN(SCIF0_CTS), + GPIO_FN(INTD), + GPIO_FN(FCE), + GPIO_FN(SCIF0_RTS), + GPIO_FN(HSPI_CS), + GPIO_FN(FSE), + GPIO_FN(SCIF0_SCK), + GPIO_FN(HSPI_CLK), + GPIO_FN(FRE), + GPIO_FN(SCIF0_RXD), + GPIO_FN(HSPI_RX), + GPIO_FN(FRB), + GPIO_FN(SCIF0_TXD), + GPIO_FN(HSPI_TX), + GPIO_FN(FWE), + GPIO_FN(SCIF5_TXD), + GPIO_FN(HAC1_SYNC), + GPIO_FN(SSI1_WS), + GPIO_FN(SIOF_TXD_PJ), + GPIO_FN(HAC0_SDOUT), + GPIO_FN(SSI0_SDATA), + GPIO_FN(SIOF_RXD_PJ), + GPIO_FN(HAC0_SDIN), + GPIO_FN(SSI0_SCK), + GPIO_FN(SIOF_SYNC_PJ), + GPIO_FN(HAC0_SYNC), + GPIO_FN(SSI0_WS), + GPIO_FN(SIOF_MCLK_PJ), + GPIO_FN(HAC_RES), + GPIO_FN(SIOF_SCK_PJ), + GPIO_FN(HAC0_BITCLK), + GPIO_FN(SSI0_CLK), + GPIO_FN(HAC1_BITCLK), + GPIO_FN(SSI1_CLK), + GPIO_FN(TCLK), + GPIO_FN(IOIS16), + GPIO_FN(STATUS0), + GPIO_FN(DRAK0_PK3), + GPIO_FN(STATUS1), + GPIO_FN(DRAK1_PK2), + GPIO_FN(DACK2), + GPIO_FN(SCIF2_TXD), + GPIO_FN(MMCCMD), + GPIO_FN(SIOF_TXD_PK), + GPIO_FN(DACK3), + GPIO_FN(SCIF2_SCK), + GPIO_FN(MMCDAT), + GPIO_FN(SIOF_SCK_PK), + GPIO_FN(DREQ0), + GPIO_FN(DREQ1), + GPIO_FN(DRAK0_PK1), + GPIO_FN(DRAK1_PK0), + GPIO_FN(DREQ2), + GPIO_FN(INTB), + GPIO_FN(DREQ3), + GPIO_FN(INTC), + GPIO_FN(DRAK2), + GPIO_FN(CE2A), + GPIO_FN(IRL4), + GPIO_FN(FD4), + GPIO_FN(IRL5), + GPIO_FN(FD5), + GPIO_FN(IRL6), + GPIO_FN(FD6), + GPIO_FN(IRL7), + GPIO_FN(FD7), + GPIO_FN(DRAK3), + GPIO_FN(CE2B), + GPIO_FN(BREQ_BSACK), + GPIO_FN(BACK_BSREQ), + GPIO_FN(SCIF5_RXD), + GPIO_FN(HAC1_SDIN), + GPIO_FN(SSI1_SCK), + GPIO_FN(SCIF5_SCK), + GPIO_FN(HAC1_SDOUT), + GPIO_FN(SSI1_SDATA), + GPIO_FN(SCIF3_TXD), + GPIO_FN(FCLE), + GPIO_FN(SCIF3_RXD), + GPIO_FN(FALE), + GPIO_FN(SCIF3_SCK), + GPIO_FN(FD0), + GPIO_FN(SCIF4_TXD), + GPIO_FN(FD1), + GPIO_FN(SCIF4_RXD), + GPIO_FN(FD2), + GPIO_FN(SCIF4_SCK), + GPIO_FN(FD3), + GPIO_FN(DEVSEL_DCLKOUT), + GPIO_FN(STOP_CDE), + GPIO_FN(LOCK_ODDF), + GPIO_FN(TRDY_DISPL), + GPIO_FN(IRDY_HSYNC), + GPIO_FN(PCIFRAME_VSYNC), + GPIO_FN(INTA), + GPIO_FN(GNT0_GNTIN), + GPIO_FN(REQ0_REQOUT), + GPIO_FN(PERR), + GPIO_FN(SERR), + GPIO_FN(WE7_CBE3), + GPIO_FN(WE6_CBE2), + GPIO_FN(WE5_CBE1), + GPIO_FN(WE4_CBE0), + GPIO_FN(SCIF2_RXD), + GPIO_FN(SIOF_RXD), + GPIO_FN(MRESETOUT), + GPIO_FN(IRQOUT), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) { - PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, - PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, - PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, - PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, - PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, - PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, - PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, - PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU } + PA7_FN, PA7_OUT, PA7_IN, 0, + PA6_FN, PA6_OUT, PA6_IN, 0, + PA5_FN, PA5_OUT, PA5_IN, 0, + PA4_FN, PA4_OUT, PA4_IN, 0, + PA3_FN, PA3_OUT, PA3_IN, 0, + PA2_FN, PA2_OUT, PA2_IN, 0, + PA1_FN, PA1_OUT, PA1_IN, 0, + PA0_FN, PA0_OUT, PA0_IN, 0 } }, { PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) { - PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, - PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, - PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, - PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, - PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, - PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, - PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, - PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU } + PB7_FN, PB7_OUT, PB7_IN, 0, + PB6_FN, PB6_OUT, PB6_IN, 0, + PB5_FN, PB5_OUT, PB5_IN, 0, + PB4_FN, PB4_OUT, PB4_IN, 0, + PB3_FN, PB3_OUT, PB3_IN, 0, + PB2_FN, PB2_OUT, PB2_IN, 0, + PB1_FN, PB1_OUT, PB1_IN, 0, + PB0_FN, PB0_OUT, PB0_IN, 0 } }, { PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2) { - PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, - PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, - PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, - PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, - PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, - PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, - PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, - PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU } + PC7_FN, PC7_OUT, PC7_IN, 0, + PC6_FN, PC6_OUT, PC6_IN, 0, + PC5_FN, PC5_OUT, PC5_IN, 0, + PC4_FN, PC4_OUT, PC4_IN, 0, + PC3_FN, PC3_OUT, PC3_IN, 0, + PC2_FN, PC2_OUT, PC2_IN, 0, + PC1_FN, PC1_OUT, PC1_IN, 0, + PC0_FN, PC0_OUT, PC0_IN, 0 } }, { PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2) { - PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, - PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, - PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, - PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, - PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, - PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, - PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, - PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU } + PD7_FN, PD7_OUT, PD7_IN, 0, + PD6_FN, PD6_OUT, PD6_IN, 0, + PD5_FN, PD5_OUT, PD5_IN, 0, + PD4_FN, PD4_OUT, PD4_IN, 0, + PD3_FN, PD3_OUT, PD3_IN, 0, + PD2_FN, PD2_OUT, PD2_IN, 0, + PD1_FN, PD1_OUT, PD1_IN, 0, + PD0_FN, PD0_OUT, PD0_IN, 0 } }, { PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, - PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU, - PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU, - PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU, - PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU, - PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU, - PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU } + PE5_FN, PE5_OUT, PE5_IN, 0, + PE4_FN, PE4_OUT, PE4_IN, 0, + PE3_FN, PE3_OUT, PE3_IN, 0, + PE2_FN, PE2_OUT, PE2_IN, 0, + PE1_FN, PE1_OUT, PE1_IN, 0, + PE0_FN, PE0_OUT, PE0_IN, 0 } }, { PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2) { - PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, - PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, - PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, - PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, - PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, - PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, - PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, - PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU } + PF7_FN, PF7_OUT, PF7_IN, 0, + PF6_FN, PF6_OUT, PF6_IN, 0, + PF5_FN, PF5_OUT, PF5_IN, 0, + PF4_FN, PF4_OUT, PF4_IN, 0, + PF3_FN, PF3_OUT, PF3_IN, 0, + PF2_FN, PF2_OUT, PF2_IN, 0, + PF1_FN, PF1_OUT, PF1_IN, 0, + PF0_FN, PF0_OUT, PF0_IN, 0 } }, { PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2) { - PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, - PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, - PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, - PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU, - PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU, - PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU, - PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU, - PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU } + PG7_FN, PG7_OUT, PG7_IN, 0, + PG6_FN, PG6_OUT, PG6_IN, 0, + PG5_FN, PG5_OUT, PG5_IN, 0, + PG4_FN, PG4_OUT, PG4_IN, 0, + PG3_FN, PG3_OUT, PG3_IN, 0, + PG2_FN, PG2_OUT, PG2_IN, 0, + PG1_FN, PG1_OUT, PG1_IN, 0, + PG0_FN, PG0_OUT, PG0_IN, 0 } }, { PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2) { - PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU, - PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU, - PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, - PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, - PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, - PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, - PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, - PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU } + PH7_FN, PH7_OUT, PH7_IN, 0, + PH6_FN, PH6_OUT, PH6_IN, 0, + PH5_FN, PH5_OUT, PH5_IN, 0, + PH4_FN, PH4_OUT, PH4_IN, 0, + PH3_FN, PH3_OUT, PH3_IN, 0, + PH2_FN, PH2_OUT, PH2_IN, 0, + PH1_FN, PH1_OUT, PH1_IN, 0, + PH0_FN, PH0_OUT, PH0_IN, 0 } }, { PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2) { - PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU, - PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU, - PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU, - PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU, - PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU, - PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU, - PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU, - PJ0_FN, PJ0_OUT, PJ0_IN, PJ0_IN_PU } + PJ7_FN, PJ7_OUT, PJ7_IN, 0, + PJ6_FN, PJ6_OUT, PJ6_IN, 0, + PJ5_FN, PJ5_OUT, PJ5_IN, 0, + PJ4_FN, PJ4_OUT, PJ4_IN, 0, + PJ3_FN, PJ3_OUT, PJ3_IN, 0, + PJ2_FN, PJ2_OUT, PJ2_IN, 0, + PJ1_FN, PJ1_OUT, PJ1_IN, 0, + PJ0_FN, PJ0_OUT, PJ0_IN, 0 } }, { PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2) { - PK7_FN, PK7_OUT, PK7_IN, PK7_IN_PU, - PK6_FN, PK6_OUT, PK6_IN, PK6_IN_PU, - PK5_FN, PK5_OUT, PK5_IN, PK5_IN_PU, - PK4_FN, PK4_OUT, PK4_IN, PK4_IN_PU, - PK3_FN, PK3_OUT, PK3_IN, PK3_IN_PU, - PK2_FN, PK2_OUT, PK2_IN, PK2_IN_PU, - PK1_FN, PK1_OUT, PK1_IN, PK1_IN_PU, - PK0_FN, PK0_OUT, PK0_IN, PK0_IN_PU } + PK7_FN, PK7_OUT, PK7_IN, 0, + PK6_FN, PK6_OUT, PK6_IN, 0, + PK5_FN, PK5_OUT, PK5_IN, 0, + PK4_FN, PK4_OUT, PK4_IN, 0, + PK3_FN, PK3_OUT, PK3_IN, 0, + PK2_FN, PK2_OUT, PK2_IN, 0, + PK1_FN, PK1_OUT, PK1_IN, 0, + PK0_FN, PK0_OUT, PK0_IN, 0 } }, { PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2) { - PL7_FN, PL7_OUT, PL7_IN, PL7_IN_PU, - PL6_FN, PL6_OUT, PL6_IN, PL6_IN_PU, - PL5_FN, PL5_OUT, PL5_IN, PL5_IN_PU, - PL4_FN, PL4_OUT, PL4_IN, PL4_IN_PU, - PL3_FN, PL3_OUT, PL3_IN, PL3_IN_PU, - PL2_FN, PL2_OUT, PL2_IN, PL2_IN_PU, - PL1_FN, PL1_OUT, PL1_IN, PL1_IN_PU, - PL0_FN, PL0_OUT, PL0_IN, PL0_IN_PU } + PL7_FN, PL7_OUT, PL7_IN, 0, + PL6_FN, PL6_OUT, PL6_IN, 0, + PL5_FN, PL5_OUT, PL5_IN, 0, + PL4_FN, PL4_OUT, PL4_IN, 0, + PL3_FN, PL3_OUT, PL3_IN, 0, + PL2_FN, PL2_OUT, PL2_IN, 0, + PL1_FN, PL1_OUT, PL1_IN, 0, + PL0_FN, PL0_OUT, PL0_IN, 0 } }, { PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2) { 0, 0, 0, 0, @@ -1132,48 +1105,48 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PM1_FN, PM1_OUT, PM1_IN, PM1_IN_PU, - PM0_FN, PM0_OUT, PM0_IN, PM0_IN_PU } + PM1_FN, PM1_OUT, PM1_IN, 0, + PM0_FN, PM0_OUT, PM0_IN, 0 } }, { PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2) { - PN7_FN, PN7_OUT, PN7_IN, PN7_IN_PU, - PN6_FN, PN6_OUT, PN6_IN, PN6_IN_PU, - PN5_FN, PN5_OUT, PN5_IN, PN5_IN_PU, - PN4_FN, PN4_OUT, PN4_IN, PN4_IN_PU, - PN3_FN, PN3_OUT, PN3_IN, PN3_IN_PU, - PN2_FN, PN2_OUT, PN2_IN, PN2_IN_PU, - PN1_FN, PN1_OUT, PN1_IN, PN1_IN_PU, - PN0_FN, PN0_OUT, PN0_IN, PN0_IN_PU } + PN7_FN, PN7_OUT, PN7_IN, 0, + PN6_FN, PN6_OUT, PN6_IN, 0, + PN5_FN, PN5_OUT, PN5_IN, 0, + PN4_FN, PN4_OUT, PN4_IN, 0, + PN3_FN, PN3_OUT, PN3_IN, 0, + PN2_FN, PN2_OUT, PN2_IN, 0, + PN1_FN, PN1_OUT, PN1_IN, 0, + PN0_FN, PN0_OUT, PN0_IN, 0 } }, { PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, - PP5_FN, PP5_OUT, PP5_IN, PP5_IN_PU, - PP4_FN, PP4_OUT, PP4_IN, PP4_IN_PU, - PP3_FN, PP3_OUT, PP3_IN, PP3_IN_PU, - PP2_FN, PP2_OUT, PP2_IN, PP2_IN_PU, - PP1_FN, PP1_OUT, PP1_IN, PP1_IN_PU, - PP0_FN, PP0_OUT, PP0_IN, PP0_IN_PU } + PP5_FN, PP5_OUT, PP5_IN, 0, + PP4_FN, PP4_OUT, PP4_IN, 0, + PP3_FN, PP3_OUT, PP3_IN, 0, + PP2_FN, PP2_OUT, PP2_IN, 0, + PP1_FN, PP1_OUT, PP1_IN, 0, + PP0_FN, PP0_OUT, PP0_IN, 0 } }, { PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PQ4_FN, PQ4_OUT, PQ4_IN, PQ4_IN_PU, - PQ3_FN, PQ3_OUT, PQ3_IN, PQ3_IN_PU, - PQ2_FN, PQ2_OUT, PQ2_IN, PQ2_IN_PU, - PQ1_FN, PQ1_OUT, PQ1_IN, PQ1_IN_PU, - PQ0_FN, PQ0_OUT, PQ0_IN, PQ0_IN_PU } + PQ4_FN, PQ4_OUT, PQ4_IN, 0, + PQ3_FN, PQ3_OUT, PQ3_IN, 0, + PQ2_FN, PQ2_OUT, PQ2_IN, 0, + PQ1_FN, PQ1_OUT, PQ1_IN, 0, + PQ0_FN, PQ0_OUT, PQ0_IN, 0 } }, { PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PR3_FN, PR3_OUT, PR3_IN, PR3_IN_PU, - PR2_FN, PR2_OUT, PR2_IN, PR2_IN_PU, - PR1_FN, PR1_OUT, PR1_IN, PR1_IN_PU, - PR0_FN, PR0_OUT, PR0_IN, PR0_IN_PU } + PR3_FN, PR3_OUT, PR3_IN, 0, + PR2_FN, PR2_OUT, PR2_IN, 0, + PR1_FN, PR1_OUT, PR1_IN, 0, + PR0_FN, PR0_OUT, PR0_IN, 0 } }, { PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1) { P1MSEL15_0, P1MSEL15_1, @@ -1214,7 +1187,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xffe70020, 8) { PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } @@ -1282,20 +1255,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7785_pinmux_info = { +const struct sh_pfc_soc_info sh7785_pinmux_info = { .name = "sh7785_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_IRQOUT, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index 1e18b58f9e5..6cb4e0aaf20 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -60,25 +60,6 @@ enum { PJ3_IN, PJ2_IN, PJ1_IN, PINMUX_INPUT_END, - PINMUX_INPUT_PULLUP_BEGIN, - PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, - PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, - PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, - PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, - PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, - PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, - PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, - PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, - PE7_IN_PU, PE6_IN_PU, - PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, - PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, - PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, - PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU, - PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, - PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU, - PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU, - PINMUX_INPUT_PULLUP_END, - PINMUX_OUTPUT_BEGIN, PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, @@ -191,85 +172,84 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t pinmux_data[] = { - +static const u16 pinmux_data[] = { /* PA GPIO */ - PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), - PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), - PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), - PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), - PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), - PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), - PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), - PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), + PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), + PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), + PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), + PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), + PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), + PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), + PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), + PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), /* PB GPIO */ - PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), - PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), - PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), - PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), - PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), - PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), - PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), - PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), + PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), + PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), + PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), + PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), + PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), + PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), + PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), + PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), /* PC GPIO */ - PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), - PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), - PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), - PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), - PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), - PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), - PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), - PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), + PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), + PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), + PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), + PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), + PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), + PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), + PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), + PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), /* PD GPIO */ - PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), - PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), - PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), - PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), - PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), - PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), - PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), - PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), + PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), + PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), + PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), + PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), + PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), + PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), + PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), + PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), /* PE GPIO */ - PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU), - PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU), + PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT), + PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT), /* PF GPIO */ - PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), - PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), - PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), - PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), - PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), - PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), - PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), - PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), + PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), + PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), + PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), + PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), + PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), + PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), + PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), + PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), /* PG GPIO */ - PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), - PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), - PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), + PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), + PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), + PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), /* PH GPIO */ - PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU), - PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU), - PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), - PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), - PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), - PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), - PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), - PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), + PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT), + PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT), + PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), + PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), + PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), + PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), + PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), + PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), /* PJ GPIO */ - PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU), - PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU), - PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU), - PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU), - PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU), - PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU), - PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU), + PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT), + PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT), + PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT), + PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT), + PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT), + PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT), + PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT), /* PA FN */ PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN), @@ -427,268 +407,272 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), }; -static struct pinmux_gpio pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PA */ - PINMUX_GPIO(GPIO_PA7, PA7_DATA), - PINMUX_GPIO(GPIO_PA6, PA6_DATA), - PINMUX_GPIO(GPIO_PA5, PA5_DATA), - PINMUX_GPIO(GPIO_PA4, PA4_DATA), - PINMUX_GPIO(GPIO_PA3, PA3_DATA), - PINMUX_GPIO(GPIO_PA2, PA2_DATA), - PINMUX_GPIO(GPIO_PA1, PA1_DATA), - PINMUX_GPIO(GPIO_PA0, PA0_DATA), + PINMUX_GPIO(PA7), + PINMUX_GPIO(PA6), + PINMUX_GPIO(PA5), + PINMUX_GPIO(PA4), + PINMUX_GPIO(PA3), + PINMUX_GPIO(PA2), + PINMUX_GPIO(PA1), + PINMUX_GPIO(PA0), /* PB */ - PINMUX_GPIO(GPIO_PB7, PB7_DATA), - PINMUX_GPIO(GPIO_PB6, PB6_DATA), - PINMUX_GPIO(GPIO_PB5, PB5_DATA), - PINMUX_GPIO(GPIO_PB4, PB4_DATA), - PINMUX_GPIO(GPIO_PB3, PB3_DATA), - PINMUX_GPIO(GPIO_PB2, PB2_DATA), - PINMUX_GPIO(GPIO_PB1, PB1_DATA), - PINMUX_GPIO(GPIO_PB0, PB0_DATA), + PINMUX_GPIO(PB7), + PINMUX_GPIO(PB6), + PINMUX_GPIO(PB5), + PINMUX_GPIO(PB4), + PINMUX_GPIO(PB3), + PINMUX_GPIO(PB2), + PINMUX_GPIO(PB1), + PINMUX_GPIO(PB0), /* PC */ - PINMUX_GPIO(GPIO_PC7, PC7_DATA), - PINMUX_GPIO(GPIO_PC6, PC6_DATA), - PINMUX_GPIO(GPIO_PC5, PC5_DATA), - PINMUX_GPIO(GPIO_PC4, PC4_DATA), - PINMUX_GPIO(GPIO_PC3, PC3_DATA), - PINMUX_GPIO(GPIO_PC2, PC2_DATA), - PINMUX_GPIO(GPIO_PC1, PC1_DATA), - PINMUX_GPIO(GPIO_PC0, PC0_DATA), + PINMUX_GPIO(PC7), + PINMUX_GPIO(PC6), + PINMUX_GPIO(PC5), + PINMUX_GPIO(PC4), + PINMUX_GPIO(PC3), + PINMUX_GPIO(PC2), + PINMUX_GPIO(PC1), + PINMUX_GPIO(PC0), /* PD */ - PINMUX_GPIO(GPIO_PD7, PD7_DATA), - PINMUX_GPIO(GPIO_PD6, PD6_DATA), - PINMUX_GPIO(GPIO_PD5, PD5_DATA), - PINMUX_GPIO(GPIO_PD4, PD4_DATA), - PINMUX_GPIO(GPIO_PD3, PD3_DATA), - PINMUX_GPIO(GPIO_PD2, PD2_DATA), - PINMUX_GPIO(GPIO_PD1, PD1_DATA), - PINMUX_GPIO(GPIO_PD0, PD0_DATA), + PINMUX_GPIO(PD7), + PINMUX_GPIO(PD6), + PINMUX_GPIO(PD5), + PINMUX_GPIO(PD4), + PINMUX_GPIO(PD3), + PINMUX_GPIO(PD2), + PINMUX_GPIO(PD1), + PINMUX_GPIO(PD0), /* PE */ - PINMUX_GPIO(GPIO_PE7, PE7_DATA), - PINMUX_GPIO(GPIO_PE6, PE6_DATA), + PINMUX_GPIO(PE7), + PINMUX_GPIO(PE6), /* PF */ - PINMUX_GPIO(GPIO_PF7, PF7_DATA), - PINMUX_GPIO(GPIO_PF6, PF6_DATA), - PINMUX_GPIO(GPIO_PF5, PF5_DATA), - PINMUX_GPIO(GPIO_PF4, PF4_DATA), - PINMUX_GPIO(GPIO_PF3, PF3_DATA), - PINMUX_GPIO(GPIO_PF2, PF2_DATA), - PINMUX_GPIO(GPIO_PF1, PF1_DATA), - PINMUX_GPIO(GPIO_PF0, PF0_DATA), + PINMUX_GPIO(PF7), + PINMUX_GPIO(PF6), + PINMUX_GPIO(PF5), + PINMUX_GPIO(PF4), + PINMUX_GPIO(PF3), + PINMUX_GPIO(PF2), + PINMUX_GPIO(PF1), + PINMUX_GPIO(PF0), /* PG */ - PINMUX_GPIO(GPIO_PG7, PG7_DATA), - PINMUX_GPIO(GPIO_PG6, PG6_DATA), - PINMUX_GPIO(GPIO_PG5, PG5_DATA), + PINMUX_GPIO(PG7), + PINMUX_GPIO(PG6), + PINMUX_GPIO(PG5), /* PH */ - PINMUX_GPIO(GPIO_PH7, PH7_DATA), - PINMUX_GPIO(GPIO_PH6, PH6_DATA), - PINMUX_GPIO(GPIO_PH5, PH5_DATA), - PINMUX_GPIO(GPIO_PH4, PH4_DATA), - PINMUX_GPIO(GPIO_PH3, PH3_DATA), - PINMUX_GPIO(GPIO_PH2, PH2_DATA), - PINMUX_GPIO(GPIO_PH1, PH1_DATA), - PINMUX_GPIO(GPIO_PH0, PH0_DATA), + PINMUX_GPIO(PH7), + PINMUX_GPIO(PH6), + PINMUX_GPIO(PH5), + PINMUX_GPIO(PH4), + PINMUX_GPIO(PH3), + PINMUX_GPIO(PH2), + PINMUX_GPIO(PH1), + PINMUX_GPIO(PH0), /* PJ */ - PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), - PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), - PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), - PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), - PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), - PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), - PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), + PINMUX_GPIO(PJ7), + PINMUX_GPIO(PJ6), + PINMUX_GPIO(PJ5), + PINMUX_GPIO(PJ4), + PINMUX_GPIO(PJ3), + PINMUX_GPIO(PJ2), + PINMUX_GPIO(PJ1), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* FN */ - PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK), - PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK), - PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK), - PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK), - PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK), - PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK), - PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK), - PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), - PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), - PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK), - PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK), - PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK), - PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK), - PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK), - PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK), - PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK), - PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK), - PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK), - PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK), - PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), - PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK), - PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), - PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK), - PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK), - PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK), - PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK), - PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK), - PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK), - PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK), - PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK), - PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK), - PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), - PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), - PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), - PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), - PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), - PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), - PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK), - PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), - PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), - PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), - PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), - PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), - PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK), - PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK), - PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), - PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK), - PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), + GPIO_FN(CDE), + GPIO_FN(ETH_MAGIC), + GPIO_FN(DISP), + GPIO_FN(ETH_LINK), + GPIO_FN(DR5), + GPIO_FN(ETH_TX_ER), + GPIO_FN(DR4), + GPIO_FN(ETH_TX_EN), + GPIO_FN(DR3), + GPIO_FN(ETH_TXD3), + GPIO_FN(DR2), + GPIO_FN(ETH_TXD2), + GPIO_FN(DR1), + GPIO_FN(ETH_TXD1), + GPIO_FN(DR0), + GPIO_FN(ETH_TXD0), + GPIO_FN(VSYNC), + GPIO_FN(HSPI_CLK), + GPIO_FN(ODDF), + GPIO_FN(HSPI_CS), + GPIO_FN(DG5), + GPIO_FN(ETH_MDIO), + GPIO_FN(DG4), + GPIO_FN(ETH_RX_CLK), + GPIO_FN(DG3), + GPIO_FN(ETH_MDC), + GPIO_FN(DG2), + GPIO_FN(ETH_COL), + GPIO_FN(DG1), + GPIO_FN(ETH_TX_CLK), + GPIO_FN(DG0), + GPIO_FN(ETH_CRS), + GPIO_FN(DCLKIN), + GPIO_FN(HSPI_RX), + GPIO_FN(HSYNC), + GPIO_FN(HSPI_TX), + GPIO_FN(DB5), + GPIO_FN(ETH_RXD3), + GPIO_FN(DB4), + GPIO_FN(ETH_RXD2), + GPIO_FN(DB3), + GPIO_FN(ETH_RXD1), + GPIO_FN(DB2), + GPIO_FN(ETH_RXD0), + GPIO_FN(DB1), + GPIO_FN(ETH_RX_DV), + GPIO_FN(DB0), + GPIO_FN(ETH_RX_ER), + GPIO_FN(DCLKOUT), + GPIO_FN(SCIF1_SCK), + GPIO_FN(SCIF1_RXD), + GPIO_FN(SCIF1_TXD), + GPIO_FN(DACK1), + GPIO_FN(BACK), + GPIO_FN(FALE), + GPIO_FN(DACK0), + GPIO_FN(FCLE), + GPIO_FN(DREQ1), + GPIO_FN(BREQ), + GPIO_FN(USB_OVC1), + GPIO_FN(DREQ0), + GPIO_FN(USB_OVC0), + GPIO_FN(USB_PENC1), + GPIO_FN(USB_PENC0), + GPIO_FN(HAC1_SDOUT), + GPIO_FN(SSI1_SDATA), + GPIO_FN(SDIF1CMD), + GPIO_FN(HAC1_SDIN), + GPIO_FN(SSI1_SCK), + GPIO_FN(SDIF1CD), + GPIO_FN(HAC1_SYNC), + GPIO_FN(SSI1_WS), + GPIO_FN(SDIF1WP), + GPIO_FN(HAC1_BITCLK), + GPIO_FN(SSI1_CLK), + GPIO_FN(SDIF1CLK), + GPIO_FN(HAC0_SDOUT), + GPIO_FN(SSI0_SDATA), + GPIO_FN(SDIF1D3), + GPIO_FN(HAC0_SDIN), + GPIO_FN(SSI0_SCK), + GPIO_FN(SDIF1D2), + GPIO_FN(HAC0_SYNC), + GPIO_FN(SSI0_WS), + GPIO_FN(SDIF1D1), + GPIO_FN(HAC0_BITCLK), + GPIO_FN(SSI0_CLK), + GPIO_FN(SDIF1D0), + GPIO_FN(SCIF3_SCK), + GPIO_FN(SSI2_SDATA), + GPIO_FN(SCIF3_RXD), + GPIO_FN(TCLK), + GPIO_FN(SSI2_SCK), + GPIO_FN(SCIF3_TXD), + GPIO_FN(HAC_RES), + GPIO_FN(SSI2_WS), + GPIO_FN(DACK3), + GPIO_FN(SDIF0CMD), + GPIO_FN(DACK2), + GPIO_FN(SDIF0CD), + GPIO_FN(DREQ3), + GPIO_FN(SDIF0WP), + GPIO_FN(SCIF0_CTS), + GPIO_FN(DREQ2), + GPIO_FN(SDIF0CLK), + GPIO_FN(SCIF0_RTS), + GPIO_FN(IRL7), + GPIO_FN(SDIF0D3), + GPIO_FN(SCIF0_SCK), + GPIO_FN(IRL6), + GPIO_FN(SDIF0D2), + GPIO_FN(SCIF0_RXD), + GPIO_FN(IRL5), + GPIO_FN(SDIF0D1), + GPIO_FN(SCIF0_TXD), + GPIO_FN(IRL4), + GPIO_FN(SDIF0D0), + GPIO_FN(SCIF5_SCK), + GPIO_FN(FRB), + GPIO_FN(SCIF5_RXD), + GPIO_FN(IOIS16), + GPIO_FN(SCIF5_TXD), + GPIO_FN(CE2B), + GPIO_FN(DRAK3), + GPIO_FN(CE2A), + GPIO_FN(SCIF4_SCK), + GPIO_FN(DRAK2), + GPIO_FN(SSI3_WS), + GPIO_FN(SCIF4_RXD), + GPIO_FN(DRAK1), + GPIO_FN(SSI3_SDATA), + GPIO_FN(FSTATUS), + GPIO_FN(SCIF4_TXD), + GPIO_FN(DRAK0), + GPIO_FN(SSI3_SCK), + GPIO_FN(FSE), }; -static struct pinmux_cfg_reg pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) { - PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, - PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, - PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, - PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, - PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, - PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, - PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, - PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU } + PA7_FN, PA7_OUT, PA7_IN, 0, + PA6_FN, PA6_OUT, PA6_IN, 0, + PA5_FN, PA5_OUT, PA5_IN, 0, + PA4_FN, PA4_OUT, PA4_IN, 0, + PA3_FN, PA3_OUT, PA3_IN, 0, + PA2_FN, PA2_OUT, PA2_IN, 0, + PA1_FN, PA1_OUT, PA1_IN, 0, + PA0_FN, PA0_OUT, PA0_IN, 0 } }, { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) { - PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, - PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, - PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, - PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, - PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, - PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, - PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, - PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU } + PB7_FN, PB7_OUT, PB7_IN, 0, + PB6_FN, PB6_OUT, PB6_IN, 0, + PB5_FN, PB5_OUT, PB5_IN, 0, + PB4_FN, PB4_OUT, PB4_IN, 0, + PB3_FN, PB3_OUT, PB3_IN, 0, + PB2_FN, PB2_OUT, PB2_IN, 0, + PB1_FN, PB1_OUT, PB1_IN, 0, + PB0_FN, PB0_OUT, PB0_IN, 0 } }, { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) { - PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, - PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, - PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, - PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, - PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, - PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, - PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, - PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU } + PC7_FN, PC7_OUT, PC7_IN, 0, + PC6_FN, PC6_OUT, PC6_IN, 0, + PC5_FN, PC5_OUT, PC5_IN, 0, + PC4_FN, PC4_OUT, PC4_IN, 0, + PC3_FN, PC3_OUT, PC3_IN, 0, + PC2_FN, PC2_OUT, PC2_IN, 0, + PC1_FN, PC1_OUT, PC1_IN, 0, + PC0_FN, PC0_OUT, PC0_IN, 0 } }, { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) { - PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, - PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, - PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, - PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, - PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, - PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, - PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, - PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU } + PD7_FN, PD7_OUT, PD7_IN, 0, + PD6_FN, PD6_OUT, PD6_IN, 0, + PD5_FN, PD5_OUT, PD5_IN, 0, + PD4_FN, PD4_OUT, PD4_IN, 0, + PD3_FN, PD3_OUT, PD3_IN, 0, + PD2_FN, PD2_OUT, PD2_IN, 0, + PD1_FN, PD1_OUT, PD1_IN, 0, + PD0_FN, PD0_OUT, PD0_IN, 0 } }, { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) { - PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU, - PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU, + PE7_FN, PE7_OUT, PE7_IN, 0, + PE6_FN, PE6_OUT, PE6_IN, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -697,19 +681,19 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, } }, { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) { - PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, - PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, - PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, - PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, - PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, - PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, - PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, - PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU } + PF7_FN, PF7_OUT, PF7_IN, 0, + PF6_FN, PF6_OUT, PF6_IN, 0, + PF5_FN, PF5_OUT, PF5_IN, 0, + PF4_FN, PF4_OUT, PF4_IN, 0, + PF3_FN, PF3_OUT, PF3_IN, 0, + PF2_FN, PF2_OUT, PF2_IN, 0, + PF1_FN, PF1_OUT, PF1_IN, 0, + PF0_FN, PF0_OUT, PF0_IN, 0 } }, { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) { - PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, - PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, - PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, + PG7_FN, PG7_OUT, PG7_IN, 0, + PG6_FN, PG6_OUT, PG6_IN, 0, + PG5_FN, PG5_OUT, PG5_IN, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -717,23 +701,23 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, } }, { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) { - PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU, - PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU, - PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, - PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, - PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, - PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, - PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, - PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU } + PH7_FN, PH7_OUT, PH7_IN, 0, + PH6_FN, PH6_OUT, PH6_IN, 0, + PH5_FN, PH5_OUT, PH5_IN, 0, + PH4_FN, PH4_OUT, PH4_IN, 0, + PH3_FN, PH3_OUT, PH3_IN, 0, + PH2_FN, PH2_OUT, PH2_IN, 0, + PH1_FN, PH1_OUT, PH1_IN, 0, + PH0_FN, PH0_OUT, PH0_IN, 0 } }, { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) { - PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU, - PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU, - PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU, - PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU, - PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU, - PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU, - PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU, + PJ7_FN, PJ7_OUT, PJ7_IN, 0, + PJ6_FN, PJ6_OUT, PJ6_IN, 0, + PJ5_FN, PJ5_OUT, PJ5_IN, 0, + PJ4_FN, PJ4_OUT, PJ4_IN, 0, + PJ3_FN, PJ3_OUT, PJ3_IN, 0, + PJ2_FN, PJ2_OUT, PJ2_IN, 0, + PJ1_FN, PJ1_OUT, PJ1_IN, 0, 0, 0, 0, 0, } }, { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) { @@ -775,7 +759,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static struct pinmux_data_reg pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) { PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } @@ -815,20 +799,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info sh7786_pinmux_info = { +const struct sh_pfc_soc_info sh7786_pinmux_info = { .name = "sh7786_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_IRL4, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index ccf6918b03c..a3fcb2284d9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -56,26 +56,6 @@ enum { PH3_IN, PH2_IN, PH1_IN, PH0_IN, PINMUX_INPUT_END, - PINMUX_INPUT_PULLUP_BEGIN, - PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, - PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, - PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, - PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, - PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, - PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, - PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, - PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, - PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU, - PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU, - PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, - PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, - PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU, - PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU, - - PH5_IN_PU, PH4_IN_PU, - PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, - PINMUX_INPUT_PULLUP_END, - PINMUX_OUTPUT_BEGIN, PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, @@ -147,85 +127,84 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t shx3_pinmux_data[] = { - +static const u16 pinmux_data[] = { /* PA GPIO */ - PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), - PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), - PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), - PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), - PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), - PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), - PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), - PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), + PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), + PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), + PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), + PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), + PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), + PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), + PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), + PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), /* PB GPIO */ - PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), - PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), - PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), - PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), - PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), - PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), - PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), - PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), + PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), + PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), + PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), + PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), + PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), + PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), + PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), + PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), /* PC GPIO */ - PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), - PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), - PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), - PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), - PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), - PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), - PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), - PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), + PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), + PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), + PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), + PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), + PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), + PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), + PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), + PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), /* PD GPIO */ - PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), - PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), - PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), - PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), - PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), - PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), - PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), - PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), + PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), + PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), + PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), + PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), + PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), + PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), + PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), + PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), /* PE GPIO */ - PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU), - PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU), - PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU), - PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU), - PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU), - PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU), - PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU), - PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU), + PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT), + PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT), + PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT), + PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT), + PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT), + PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT), + PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT), + PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT), /* PF GPIO */ - PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), - PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), - PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), - PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), - PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), - PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), - PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), - PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), + PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), + PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), + PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), + PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), + PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), + PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), + PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), + PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), /* PG GPIO */ - PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), - PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), - PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), - PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU), - PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU), - PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU), - PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU), - PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU), + PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), + PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), + PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), + PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT), + PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT), + PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT), + PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT), + PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT), /* PH GPIO */ - PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), - PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), - PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), - PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), - PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), - PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), + PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), + PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), + PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), + PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), + PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), + PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), /* PA FN */ PINMUX_DATA(D31_MARK, PA7_FN), @@ -306,227 +285,231 @@ static pinmux_enum_t shx3_pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, PH0_FN), }; -static struct pinmux_gpio shx3_pinmux_gpios[] = { +static const struct sh_pfc_pin pinmux_pins[] = { /* PA */ - PINMUX_GPIO(GPIO_PA7, PA7_DATA), - PINMUX_GPIO(GPIO_PA6, PA6_DATA), - PINMUX_GPIO(GPIO_PA5, PA5_DATA), - PINMUX_GPIO(GPIO_PA4, PA4_DATA), - PINMUX_GPIO(GPIO_PA3, PA3_DATA), - PINMUX_GPIO(GPIO_PA2, PA2_DATA), - PINMUX_GPIO(GPIO_PA1, PA1_DATA), - PINMUX_GPIO(GPIO_PA0, PA0_DATA), + PINMUX_GPIO(PA7), + PINMUX_GPIO(PA6), + PINMUX_GPIO(PA5), + PINMUX_GPIO(PA4), + PINMUX_GPIO(PA3), + PINMUX_GPIO(PA2), + PINMUX_GPIO(PA1), + PINMUX_GPIO(PA0), /* PB */ - PINMUX_GPIO(GPIO_PB7, PB7_DATA), - PINMUX_GPIO(GPIO_PB6, PB6_DATA), - PINMUX_GPIO(GPIO_PB5, PB5_DATA), - PINMUX_GPIO(GPIO_PB4, PB4_DATA), - PINMUX_GPIO(GPIO_PB3, PB3_DATA), - PINMUX_GPIO(GPIO_PB2, PB2_DATA), - PINMUX_GPIO(GPIO_PB1, PB1_DATA), - PINMUX_GPIO(GPIO_PB0, PB0_DATA), + PINMUX_GPIO(PB7), + PINMUX_GPIO(PB6), + PINMUX_GPIO(PB5), + PINMUX_GPIO(PB4), + PINMUX_GPIO(PB3), + PINMUX_GPIO(PB2), + PINMUX_GPIO(PB1), + PINMUX_GPIO(PB0), /* PC */ - PINMUX_GPIO(GPIO_PC7, PC7_DATA), - PINMUX_GPIO(GPIO_PC6, PC6_DATA), - PINMUX_GPIO(GPIO_PC5, PC5_DATA), - PINMUX_GPIO(GPIO_PC4, PC4_DATA), - PINMUX_GPIO(GPIO_PC3, PC3_DATA), - PINMUX_GPIO(GPIO_PC2, PC2_DATA), - PINMUX_GPIO(GPIO_PC1, PC1_DATA), - PINMUX_GPIO(GPIO_PC0, PC0_DATA), + PINMUX_GPIO(PC7), + PINMUX_GPIO(PC6), + PINMUX_GPIO(PC5), + PINMUX_GPIO(PC4), + PINMUX_GPIO(PC3), + PINMUX_GPIO(PC2), + PINMUX_GPIO(PC1), + PINMUX_GPIO(PC0), /* PD */ - PINMUX_GPIO(GPIO_PD7, PD7_DATA), - PINMUX_GPIO(GPIO_PD6, PD6_DATA), - PINMUX_GPIO(GPIO_PD5, PD5_DATA), - PINMUX_GPIO(GPIO_PD4, PD4_DATA), - PINMUX_GPIO(GPIO_PD3, PD3_DATA), - PINMUX_GPIO(GPIO_PD2, PD2_DATA), - PINMUX_GPIO(GPIO_PD1, PD1_DATA), - PINMUX_GPIO(GPIO_PD0, PD0_DATA), + PINMUX_GPIO(PD7), + PINMUX_GPIO(PD6), + PINMUX_GPIO(PD5), + PINMUX_GPIO(PD4), + PINMUX_GPIO(PD3), + PINMUX_GPIO(PD2), + PINMUX_GPIO(PD1), + PINMUX_GPIO(PD0), /* PE */ - PINMUX_GPIO(GPIO_PE7, PE7_DATA), - PINMUX_GPIO(GPIO_PE6, PE6_DATA), - PINMUX_GPIO(GPIO_PE5, PE5_DATA), - PINMUX_GPIO(GPIO_PE4, PE4_DATA), - PINMUX_GPIO(GPIO_PE3, PE3_DATA), - PINMUX_GPIO(GPIO_PE2, PE2_DATA), - PINMUX_GPIO(GPIO_PE1, PE1_DATA), - PINMUX_GPIO(GPIO_PE0, PE0_DATA), + PINMUX_GPIO(PE7), + PINMUX_GPIO(PE6), + PINMUX_GPIO(PE5), + PINMUX_GPIO(PE4), + PINMUX_GPIO(PE3), + PINMUX_GPIO(PE2), + PINMUX_GPIO(PE1), + PINMUX_GPIO(PE0), /* PF */ - PINMUX_GPIO(GPIO_PF7, PF7_DATA), - PINMUX_GPIO(GPIO_PF6, PF6_DATA), - PINMUX_GPIO(GPIO_PF5, PF5_DATA), - PINMUX_GPIO(GPIO_PF4, PF4_DATA), - PINMUX_GPIO(GPIO_PF3, PF3_DATA), - PINMUX_GPIO(GPIO_PF2, PF2_DATA), - PINMUX_GPIO(GPIO_PF1, PF1_DATA), - PINMUX_GPIO(GPIO_PF0, PF0_DATA), + PINMUX_GPIO(PF7), + PINMUX_GPIO(PF6), + PINMUX_GPIO(PF5), + PINMUX_GPIO(PF4), + PINMUX_GPIO(PF3), + PINMUX_GPIO(PF2), + PINMUX_GPIO(PF1), + PINMUX_GPIO(PF0), /* PG */ - PINMUX_GPIO(GPIO_PG7, PG7_DATA), - PINMUX_GPIO(GPIO_PG6, PG6_DATA), - PINMUX_GPIO(GPIO_PG5, PG5_DATA), - PINMUX_GPIO(GPIO_PG4, PG4_DATA), - PINMUX_GPIO(GPIO_PG3, PG3_DATA), - PINMUX_GPIO(GPIO_PG2, PG2_DATA), - PINMUX_GPIO(GPIO_PG1, PG1_DATA), - PINMUX_GPIO(GPIO_PG0, PG0_DATA), + PINMUX_GPIO(PG7), + PINMUX_GPIO(PG6), + PINMUX_GPIO(PG5), + PINMUX_GPIO(PG4), + PINMUX_GPIO(PG3), + PINMUX_GPIO(PG2), + PINMUX_GPIO(PG1), + PINMUX_GPIO(PG0), /* PH */ - PINMUX_GPIO(GPIO_PH5, PH5_DATA), - PINMUX_GPIO(GPIO_PH4, PH4_DATA), - PINMUX_GPIO(GPIO_PH3, PH3_DATA), - PINMUX_GPIO(GPIO_PH2, PH2_DATA), - PINMUX_GPIO(GPIO_PH1, PH1_DATA), - PINMUX_GPIO(GPIO_PH0, PH0_DATA), + PINMUX_GPIO(PH5), + PINMUX_GPIO(PH4), + PINMUX_GPIO(PH3), + PINMUX_GPIO(PH2), + PINMUX_GPIO(PH1), + PINMUX_GPIO(PH0), +}; + +#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) +static const struct pinmux_func pinmux_func_gpios[] = { /* FN */ - PINMUX_GPIO(GPIO_FN_D31, D31_MARK), - PINMUX_GPIO(GPIO_FN_D30, D30_MARK), - PINMUX_GPIO(GPIO_FN_D29, D29_MARK), - PINMUX_GPIO(GPIO_FN_D28, D28_MARK), - PINMUX_GPIO(GPIO_FN_D27, D27_MARK), - PINMUX_GPIO(GPIO_FN_D26, D26_MARK), - PINMUX_GPIO(GPIO_FN_D25, D25_MARK), - PINMUX_GPIO(GPIO_FN_D24, D24_MARK), - PINMUX_GPIO(GPIO_FN_D23, D23_MARK), - PINMUX_GPIO(GPIO_FN_D22, D22_MARK), - PINMUX_GPIO(GPIO_FN_D21, D21_MARK), - PINMUX_GPIO(GPIO_FN_D20, D20_MARK), - PINMUX_GPIO(GPIO_FN_D19, D19_MARK), - PINMUX_GPIO(GPIO_FN_D18, D18_MARK), - PINMUX_GPIO(GPIO_FN_D17, D17_MARK), - PINMUX_GPIO(GPIO_FN_D16, D16_MARK), - PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), - PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), - PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK), - PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK), - PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), - PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK), - PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), - PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), - PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), - PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), - PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), - PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), - PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), - PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), - PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), - PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), - PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK), - PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK), - PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK), - PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK), - PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), - PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), - PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), - PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), - PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), - PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), + GPIO_FN(D31), + GPIO_FN(D30), + GPIO_FN(D29), + GPIO_FN(D28), + GPIO_FN(D27), + GPIO_FN(D26), + GPIO_FN(D25), + GPIO_FN(D24), + GPIO_FN(D23), + GPIO_FN(D22), + GPIO_FN(D21), + GPIO_FN(D20), + GPIO_FN(D19), + GPIO_FN(D18), + GPIO_FN(D17), + GPIO_FN(D16), + GPIO_FN(BACK), + GPIO_FN(BREQ), + GPIO_FN(WE3), + GPIO_FN(WE2), + GPIO_FN(CS6), + GPIO_FN(CS5), + GPIO_FN(CS4), + GPIO_FN(CLKOUTENB), + GPIO_FN(DACK3), + GPIO_FN(DACK2), + GPIO_FN(DACK1), + GPIO_FN(DACK0), + GPIO_FN(DREQ3), + GPIO_FN(DREQ2), + GPIO_FN(DREQ1), + GPIO_FN(DREQ0), + GPIO_FN(IRQ3), + GPIO_FN(IRQ2), + GPIO_FN(IRQ1), + GPIO_FN(IRQ0), + GPIO_FN(DRAK3), + GPIO_FN(DRAK2), + GPIO_FN(DRAK1), + GPIO_FN(DRAK0), + GPIO_FN(SCK3), + GPIO_FN(SCK2), + GPIO_FN(SCK1), + GPIO_FN(SCK0), + GPIO_FN(IRL3), + GPIO_FN(IRL2), + GPIO_FN(IRL1), + GPIO_FN(IRL0), + GPIO_FN(TXD3), + GPIO_FN(TXD2), + GPIO_FN(TXD1), + GPIO_FN(TXD0), + GPIO_FN(RXD3), + GPIO_FN(RXD2), + GPIO_FN(RXD1), + GPIO_FN(RXD0), + GPIO_FN(CE2B), + GPIO_FN(CE2A), + GPIO_FN(IOIS16), + GPIO_FN(STATUS1), + GPIO_FN(STATUS0), + GPIO_FN(IRQOUT), }; -static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { +static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { - PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, - PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, - PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, - PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, - PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, - PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, - PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, - PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU, - PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, - PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, - PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, - PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, - PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, - PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, - PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, - PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, }, + PA7_FN, PA7_OUT, PA7_IN, 0, + PA6_FN, PA6_OUT, PA6_IN, 0, + PA5_FN, PA5_OUT, PA5_IN, 0, + PA4_FN, PA4_OUT, PA4_IN, 0, + PA3_FN, PA3_OUT, PA3_IN, 0, + PA2_FN, PA2_OUT, PA2_IN, 0, + PA1_FN, PA1_OUT, PA1_IN, 0, + PA0_FN, PA0_OUT, PA0_IN, 0, + PB7_FN, PB7_OUT, PB7_IN, 0, + PB6_FN, PB6_OUT, PB6_IN, 0, + PB5_FN, PB5_OUT, PB5_IN, 0, + PB4_FN, PB4_OUT, PB4_IN, 0, + PB3_FN, PB3_OUT, PB3_IN, 0, + PB2_FN, PB2_OUT, PB2_IN, 0, + PB1_FN, PB1_OUT, PB1_IN, 0, + PB0_FN, PB0_OUT, PB0_IN, 0, }, }, { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) { - PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, - PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, - PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, - PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, - PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, - PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, - PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, - PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU, - PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, - PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, - PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, - PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, - PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, - PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, - PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, - PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, }, + PC7_FN, PC7_OUT, PC7_IN, 0, + PC6_FN, PC6_OUT, PC6_IN, 0, + PC5_FN, PC5_OUT, PC5_IN, 0, + PC4_FN, PC4_OUT, PC4_IN, 0, + PC3_FN, PC3_OUT, PC3_IN, 0, + PC2_FN, PC2_OUT, PC2_IN, 0, + PC1_FN, PC1_OUT, PC1_IN, 0, + PC0_FN, PC0_OUT, PC0_IN, 0, + PD7_FN, PD7_OUT, PD7_IN, 0, + PD6_FN, PD6_OUT, PD6_IN, 0, + PD5_FN, PD5_OUT, PD5_IN, 0, + PD4_FN, PD4_OUT, PD4_IN, 0, + PD3_FN, PD3_OUT, PD3_IN, 0, + PD2_FN, PD2_OUT, PD2_IN, 0, + PD1_FN, PD1_OUT, PD1_IN, 0, + PD0_FN, PD0_OUT, PD0_IN, 0, }, }, { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) { - PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU, - PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU, - PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU, - PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU, - PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU, - PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU, - PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU, - PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU, - PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, - PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, - PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, - PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, - PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, - PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, - PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, - PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, }, + PE7_FN, PE7_OUT, PE7_IN, 0, + PE6_FN, PE6_OUT, PE6_IN, 0, + PE5_FN, PE5_OUT, PE5_IN, 0, + PE4_FN, PE4_OUT, PE4_IN, 0, + PE3_FN, PE3_OUT, PE3_IN, 0, + PE2_FN, PE2_OUT, PE2_IN, 0, + PE1_FN, PE1_OUT, PE1_IN, 0, + PE0_FN, PE0_OUT, PE0_IN, 0, + PF7_FN, PF7_OUT, PF7_IN, 0, + PF6_FN, PF6_OUT, PF6_IN, 0, + PF5_FN, PF5_OUT, PF5_IN, 0, + PF4_FN, PF4_OUT, PF4_IN, 0, + PF3_FN, PF3_OUT, PF3_IN, 0, + PF2_FN, PF2_OUT, PF2_IN, 0, + PF1_FN, PF1_OUT, PF1_IN, 0, + PF0_FN, PF0_OUT, PF0_IN, 0, }, }, { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) { - PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, - PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, - PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, - PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU, - PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU, - PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU, - PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU, - PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU, + PG7_FN, PG7_OUT, PG7_IN, 0, + PG6_FN, PG6_OUT, PG6_IN, 0, + PG5_FN, PG5_OUT, PG5_IN, 0, + PG4_FN, PG4_OUT, PG4_IN, 0, + PG3_FN, PG3_OUT, PG3_IN, 0, + PG2_FN, PG2_OUT, PG2_IN, 0, + PG1_FN, PG1_OUT, PG1_IN, 0, + PG0_FN, PG0_OUT, PG0_IN, 0, 0, 0, 0, 0, 0, 0, 0, 0, - PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, - PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, - PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, - PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, - PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, - PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, }, + PH5_FN, PH5_OUT, PH5_IN, 0, + PH4_FN, PH4_OUT, PH4_IN, 0, + PH3_FN, PH3_OUT, PH3_IN, 0, + PH2_FN, PH2_OUT, PH2_IN, 0, + PH1_FN, PH1_OUT, PH1_IN, 0, + PH0_FN, PH0_OUT, PH0_IN, 0, }, }, { }, }; -static struct pinmux_data_reg shx3_pinmux_data_regs[] = { +static const struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { 0, 0, 0, 0, 0, 0, 0, 0, PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, @@ -562,21 +545,17 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = { { }, }; -struct sh_pfc_soc_info shx3_pinmux_info = { +const struct sh_pfc_soc_info shx3_pinmux_info = { .name = "shx3_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, - PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PA7, - .last_gpio = GPIO_FN_STATUS0, - .gpios = shx3_pinmux_gpios, - .gpio_data = shx3_pinmux_data, - .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data), - .cfg_regs = shx3_pinmux_config_regs, - .data_regs = shx3_pinmux_data_regs, + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .func_gpios = pinmux_func_gpios, + .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, }; diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 11e0e1374d6..e758af95c20 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -9,13 +9,14 @@ */ #define DRV_NAME "sh-pfc" -#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt #include <linux/device.h> #include <linux/err.h> #include <linux/init.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> @@ -24,25 +25,28 @@ #include <linux/spinlock.h> #include "core.h" +#include "../core.h" +#include "../pinconf.h" + +struct sh_pfc_pin_config { + u32 type; +}; struct sh_pfc_pinctrl { struct pinctrl_dev *pctl; - struct sh_pfc *pfc; + struct pinctrl_desc pctl_desc; - struct pinmux_gpio **functions; - unsigned int nr_functions; - - struct pinctrl_pin_desc *pads; - unsigned int nr_pads; + struct sh_pfc *pfc; - spinlock_t lock; + struct pinctrl_pin_desc *pins; + struct sh_pfc_pin_config *configs; }; static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->nr_pads; + return pmx->pfc->info->nr_groups; } static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, @@ -50,16 +54,16 @@ static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->pads[selector].name; + return pmx->pfc->info->groups[selector].name; } -static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, +static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - *pins = &pmx->pads[group].number; - *num_pins = 1; + *pins = pmx->pfc->info->groups[selector].pins; + *num_pins = pmx->pfc->info->groups[selector].nr_pins; return 0; } @@ -70,18 +74,221 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, "%s", DRV_NAME); } -static struct pinctrl_ops sh_pfc_pinctrl_ops = { +#ifdef CONFIG_OF +static int sh_pfc_map_add_config(struct pinctrl_map *map, + const char *group_or_pin, + enum pinctrl_map_type type, + unsigned long *configs, + unsigned int num_configs) +{ + unsigned long *cfgs; + + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), + GFP_KERNEL); + if (cfgs == NULL) + return -ENOMEM; + + map->type = type; + map->data.configs.group_or_pin = group_or_pin; + map->data.configs.configs = cfgs; + map->data.configs.num_configs = num_configs; + + return 0; +} + +static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps, unsigned int *index) +{ + struct pinctrl_map *maps = *map; + unsigned int nmaps = *num_maps; + unsigned int idx = *index; + unsigned int num_configs; + const char *function = NULL; + unsigned long *configs; + struct property *prop; + unsigned int num_groups; + unsigned int num_pins; + const char *group; + const char *pin; + int ret; + + /* Parse the function and configuration properties. At least a function + * or one configuration must be specified. + */ + ret = of_property_read_string(np, "renesas,function", &function); + if (ret < 0 && ret != -EINVAL) { + dev_err(dev, "Invalid function in DT\n"); + return ret; + } + + ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + if (ret < 0) + return ret; + + if (!function && num_configs == 0) { + dev_err(dev, + "DT node must contain at least a function or config\n"); + goto done; + } + + /* Count the number of pins and groups and reallocate mappings. */ + ret = of_property_count_strings(np, "renesas,pins"); + if (ret == -EINVAL) { + num_pins = 0; + } else if (ret < 0) { + dev_err(dev, "Invalid pins list in DT\n"); + goto done; + } else { + num_pins = ret; + } + + ret = of_property_count_strings(np, "renesas,groups"); + if (ret == -EINVAL) { + num_groups = 0; + } else if (ret < 0) { + dev_err(dev, "Invalid pin groups list in DT\n"); + goto done; + } else { + num_groups = ret; + } + + if (!num_pins && !num_groups) { + dev_err(dev, "No pin or group provided in DT node\n"); + ret = -ENODEV; + goto done; + } + + if (function) + nmaps += num_groups; + if (configs) + nmaps += num_pins + num_groups; + + maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL); + if (maps == NULL) { + ret = -ENOMEM; + goto done; + } + + *map = maps; + *num_maps = nmaps; + + /* Iterate over pins and groups and create the mappings. */ + of_property_for_each_string(np, "renesas,groups", prop, group) { + if (function) { + maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; + maps[idx].data.mux.group = group; + maps[idx].data.mux.function = function; + idx++; + } + + if (configs) { + ret = sh_pfc_map_add_config(&maps[idx], group, + PIN_MAP_TYPE_CONFIGS_GROUP, + configs, num_configs); + if (ret < 0) + goto done; + + idx++; + } + } + + if (!configs) { + ret = 0; + goto done; + } + + of_property_for_each_string(np, "renesas,pins", prop, pin) { + ret = sh_pfc_map_add_config(&maps[idx], pin, + PIN_MAP_TYPE_CONFIGS_PIN, + configs, num_configs); + if (ret < 0) + goto done; + + idx++; + } + +done: + *index = idx; + kfree(configs); + return ret; +} + +static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + unsigned int i; + + if (map == NULL) + return; + + for (i = 0; i < num_maps; ++i) { + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || + map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + } + + kfree(map); +} + +static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = pmx->pfc->dev; + struct device_node *child; + unsigned int index; + int ret; + + *map = NULL; + *num_maps = 0; + index = 0; + + for_each_child_of_node(np, child) { + ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps, + &index); + if (ret < 0) + goto done; + } + + /* If no mapping has been found in child nodes try the config node. */ + if (*num_maps == 0) { + ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index); + if (ret < 0) + goto done; + } + + if (*num_maps) + return 0; + + dev_err(dev, "no mapping found in node %s\n", np->full_name); + ret = -EINVAL; + +done: + if (ret < 0) + sh_pfc_dt_free_map(pctldev, *map, *num_maps); + + return ret; +} +#endif /* CONFIG_OF */ + +static const struct pinctrl_ops sh_pfc_pinctrl_ops = { .get_groups_count = sh_pfc_get_groups_count, .get_group_name = sh_pfc_get_group_name, .get_group_pins = sh_pfc_get_group_pins, .pin_dbg_show = sh_pfc_pin_dbg_show, +#ifdef CONFIG_OF + .dt_node_to_map = sh_pfc_dt_node_to_map, + .dt_free_map = sh_pfc_dt_free_map, +#endif }; static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->nr_functions; + return pmx->pfc->info->nr_functions; } static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, @@ -89,136 +296,113 @@ static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->functions[selector]->name; + return pmx->pfc->info->functions[selector].name; } -static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func, +static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, + unsigned selector, const char * const **groups, unsigned * const num_groups) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - *groups = &pmx->functions[func]->name; - *num_groups = 1; + *groups = pmx->pfc->info->functions[selector].groups; + *num_groups = pmx->pfc->info->functions[selector].nr_groups; return 0; } -static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func, +static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { - return 0; -} + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; + const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; + unsigned long flags; + unsigned int i; + int ret = 0; -static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, - unsigned group) -{ -} + spin_lock_irqsave(&pfc->lock, flags); -static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset) -{ - if (sh_pfc_config_gpio(pfc, offset, - PINMUX_TYPE_FUNCTION, - GPIO_CFG_DRYRUN) != 0) - return -EINVAL; + for (i = 0; i < grp->nr_pins; ++i) { + int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - if (sh_pfc_config_gpio(pfc, offset, - PINMUX_TYPE_FUNCTION, - GPIO_CFG_REQ) != 0) - return -EINVAL; + if (cfg->type != PINMUX_TYPE_NONE) { + ret = -EBUSY; + goto done; + } + } - return 0; + for (i = 0; i < grp->nr_pins; ++i) { + ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); + if (ret < 0) + break; + } + +done: + spin_unlock_irqrestore(&pfc->lock, flags); + return ret; } -static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, - int new_type) +static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; + const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; unsigned long flags; - int pinmux_type; - int ret = -EINVAL; + unsigned int i; spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; + for (i = 0; i < grp->nr_pins; ++i) { + int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - /* - * See if the present config needs to first be de-configured. - */ - switch (pinmux_type) { - case PINMUX_TYPE_GPIO: - break; - case PINMUX_TYPE_OUTPUT: - case PINMUX_TYPE_INPUT: - case PINMUX_TYPE_INPUT_PULLUP: - case PINMUX_TYPE_INPUT_PULLDOWN: - sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); - break; - default: - goto err; + cfg->type = PINMUX_TYPE_NONE; } - /* - * Dry run - */ - if (sh_pfc_config_gpio(pfc, offset, new_type, - GPIO_CFG_DRYRUN) != 0) - goto err; - - /* - * Request - */ - if (sh_pfc_config_gpio(pfc, offset, new_type, - GPIO_CFG_REQ) != 0) - goto err; - - pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE; - pfc->info->gpios[offset].flags |= new_type; - - ret = 0; - -err: spin_unlock_irqrestore(&pfc->lock, flags); - - return ret; } - static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; + int idx = sh_pfc_get_pin_index(pfc, offset); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; - int ret, pinmux_type; + int ret; spin_lock_irqsave(&pfc->lock, flags); - pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; + if (cfg->type != PINMUX_TYPE_NONE) { + dev_err(pfc->dev, + "Pin %u is busy, can't configure it as GPIO.\n", + offset); + ret = -EBUSY; + goto done; + } - switch (pinmux_type) { - case PINMUX_TYPE_FUNCTION: - pr_notice_once("Use of GPIO API for function requests is " - "deprecated, convert to pinctrl\n"); - /* handle for now */ - ret = sh_pfc_config_function(pfc, offset); - if (unlikely(ret < 0)) - goto err; + if (!pfc->gpio) { + /* If GPIOs are handled externally the pin mux type need to be + * set to GPIO here. + */ + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - break; - case PINMUX_TYPE_GPIO: - case PINMUX_TYPE_INPUT: - case PINMUX_TYPE_OUTPUT: - break; - default: - pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type); - ret = -ENOTSUPP; - goto err; + ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); + if (ret < 0) + goto done; } + cfg->type = PINMUX_TYPE_GPIO; + ret = 0; -err: +done: spin_unlock_irqrestore(&pfc->lock, flags); return ret; @@ -230,15 +414,12 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; + int idx = sh_pfc_get_pin_index(pfc, offset); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; - int pinmux_type; spin_lock_irqsave(&pfc->lock, flags); - - pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; - - sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); - + cfg->type = PINMUX_TYPE_NONE; spin_unlock_irqrestore(&pfc->lock, flags); } @@ -247,172 +428,197 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, unsigned offset, bool input) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; + struct sh_pfc *pfc = pmx->pfc; + int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; + int idx = sh_pfc_get_pin_index(pfc, offset); + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + unsigned long flags; + unsigned int dir; + int ret; + + /* Check if the requested direction is supported by the pin. Not all SoC + * provide pin config data, so perform the check conditionally. + */ + if (pin->configs) { + dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; + if (!(pin->configs & dir)) + return -EINVAL; + } - return sh_pfc_reconfig_pin(pmx->pfc, offset, type); + spin_lock_irqsave(&pfc->lock, flags); + + ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); + if (ret < 0) + goto done; + + cfg->type = new_type; + +done: + spin_unlock_irqrestore(&pfc->lock, flags); + return ret; } -static struct pinmux_ops sh_pfc_pinmux_ops = { +static const struct pinmux_ops sh_pfc_pinmux_ops = { .get_functions_count = sh_pfc_get_functions_count, .get_function_name = sh_pfc_get_function_name, .get_function_groups = sh_pfc_get_function_groups, - .enable = sh_pfc_noop_enable, - .disable = sh_pfc_noop_disable, + .enable = sh_pfc_func_enable, + .disable = sh_pfc_func_disable, .gpio_request_enable = sh_pfc_gpio_request_enable, .gpio_disable_free = sh_pfc_gpio_disable_free, .gpio_set_direction = sh_pfc_gpio_set_direction, }; -static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *config) +/* Check whether the requested parameter is supported for a pin. */ +static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, + enum pin_config_param param) { - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - struct sh_pfc *pfc = pmx->pfc; + int idx = sh_pfc_get_pin_index(pfc, _pin); + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - *config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE; + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + return true; - return 0; -} + case PIN_CONFIG_BIAS_PULL_UP: + return pin->configs & SH_PFC_PIN_CFG_PULL_UP; -static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) -{ - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + case PIN_CONFIG_BIAS_PULL_DOWN: + return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; - /* Validate the new type */ - if (config >= PINMUX_FLAG_TYPE) - return -EINVAL; - - return sh_pfc_reconfig_pin(pmx->pfc, pin, config); + default: + return false; + } } -static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin) +static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, + unsigned long *config) { - const char *pinmux_type_str[] = { - [PINMUX_TYPE_NONE] = "none", - [PINMUX_TYPE_FUNCTION] = "function", - [PINMUX_TYPE_GPIO] = "gpio", - [PINMUX_TYPE_OUTPUT] = "output", - [PINMUX_TYPE_INPUT] = "input", - [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up", - [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down", - }; - unsigned long config; - int rc; - - rc = sh_pfc_pinconf_get(pctldev, pin, &config); - if (unlikely(rc != 0)) - return; - - seq_printf(s, " %s", pinmux_type_str[config]); -} - -static struct pinconf_ops sh_pfc_pinconf_ops = { - .pin_config_get = sh_pfc_pinconf_get, - .pin_config_set = sh_pfc_pinconf_set, - .pin_config_dbg_show = sh_pfc_pinconf_dbg_show, -}; + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned long flags; + unsigned int bias; -static struct pinctrl_gpio_range sh_pfc_gpio_range = { - .name = DRV_NAME, - .id = 0, -}; + if (!sh_pfc_pinconf_validate(pfc, _pin, param)) + return -ENOTSUPP; -static struct pinctrl_desc sh_pfc_pinctrl_desc = { - .name = DRV_NAME, - .owner = THIS_MODULE, - .pctlops = &sh_pfc_pinctrl_ops, - .pmxops = &sh_pfc_pinmux_ops, - .confops = &sh_pfc_pinconf_ops, -}; + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!pfc->info->ops || !pfc->info->ops->get_bias) + return -ENOTSUPP; -static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, - struct pinmux_gpio *gpio, unsigned offset) -{ - struct pinmux_data_reg *dummy; - unsigned long flags; - int bit; + spin_lock_irqsave(&pfc->lock, flags); + bias = pfc->info->ops->get_bias(pfc, _pin); + spin_unlock_irqrestore(&pfc->lock, flags); - gpio->flags &= ~PINMUX_FLAG_TYPE; + if (bias != param) + return -EINVAL; - if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0) - gpio->flags |= PINMUX_TYPE_GPIO; - else { - gpio->flags |= PINMUX_TYPE_FUNCTION; + *config = 0; + break; - spin_lock_irqsave(&pmx->lock, flags); - pmx->nr_functions++; - spin_unlock_irqrestore(&pmx->lock, flags); + default: + return -ENOTSUPP; } + + return 0; } -/* pinmux ranges -> pinctrl pin descs */ -static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) +static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, + unsigned long *configs, unsigned num_configs) { + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; + enum pin_config_param param; unsigned long flags; - int i; + unsigned int i; - pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1; + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); - pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads, - GFP_KERNEL); - if (unlikely(!pmx->pads)) { - pmx->nr_pads = 0; - return -ENOMEM; - } + if (!sh_pfc_pinconf_validate(pfc, _pin, param)) + return -ENOTSUPP; - spin_lock_irqsave(&pfc->lock, flags); + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_DISABLE: + if (!pfc->info->ops || !pfc->info->ops->set_bias) + return -ENOTSUPP; - /* - * We don't necessarily have a 1:1 mapping between pin and linux - * GPIO number, as the latter maps to the associated enum_id. - * Care needs to be taken to translate back to pin space when - * dealing with any pin configurations. - */ - for (i = 0; i < pmx->nr_pads; i++) { - struct pinctrl_pin_desc *pin = pmx->pads + i; - struct pinmux_gpio *gpio = pfc->info->gpios + i; + spin_lock_irqsave(&pfc->lock, flags); + pfc->info->ops->set_bias(pfc, _pin, param); + spin_unlock_irqrestore(&pfc->lock, flags); - pin->number = pfc->info->first_gpio + i; - pin->name = gpio->name; + break; - /* XXX */ - if (unlikely(!gpio->enum_id)) - continue; + default: + return -ENOTSUPP; + } + } /* for each config */ - sh_pfc_map_one_gpio(pfc, pmx, gpio, i); - } + return 0; +} - spin_unlock_irqrestore(&pfc->lock, flags); +static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, + unsigned long *configs, + unsigned num_configs) +{ + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins; + unsigned int num_pins; + unsigned int i; - sh_pfc_pinctrl_desc.pins = pmx->pads; - sh_pfc_pinctrl_desc.npins = pmx->nr_pads; + pins = pmx->pfc->info->groups[group].pins; + num_pins = pmx->pfc->info->groups[group].nr_pins; + + for (i = 0; i < num_pins; ++i) + sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); return 0; } -static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) +static const struct pinconf_ops sh_pfc_pinconf_ops = { + .is_generic = true, + .pin_config_get = sh_pfc_pinconf_get, + .pin_config_set = sh_pfc_pinconf_set, + .pin_config_group_set = sh_pfc_pinconf_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +/* PFC ranges -> pinctrl pin descs */ +static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { - unsigned long flags; - int i, fn; + unsigned int i; - pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions * - sizeof(*pmx->functions), GFP_KERNEL); - if (unlikely(!pmx->functions)) + /* Allocate and initialize the pins and configs arrays. */ + pmx->pins = devm_kzalloc(pfc->dev, + sizeof(*pmx->pins) * pfc->info->nr_pins, + GFP_KERNEL); + if (unlikely(!pmx->pins)) return -ENOMEM; - spin_lock_irqsave(&pmx->lock, flags); + pmx->configs = devm_kzalloc(pfc->dev, + sizeof(*pmx->configs) * pfc->info->nr_pins, + GFP_KERNEL); + if (unlikely(!pmx->configs)) + return -ENOMEM; - for (i = fn = 0; i < pmx->nr_pads; i++) { - struct pinmux_gpio *gpio = pfc->info->gpios + i; + for (i = 0; i < pfc->info->nr_pins; ++i) { + const struct sh_pfc_pin *info = &pfc->info->pins[i]; + struct sh_pfc_pin_config *cfg = &pmx->configs[i]; + struct pinctrl_pin_desc *pin = &pmx->pins[i]; - if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION) - pmx->functions[fn++] = gpio; + /* If the pin number is equal to -1 all pins are considered */ + pin->number = info->pin != (u16)-1 ? info->pin : i; + pin->name = info->name; + cfg->type = PINMUX_TYPE_NONE; } - spin_unlock_irqrestore(&pmx->lock, flags); - return 0; } @@ -425,29 +631,24 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) if (unlikely(!pmx)) return -ENOMEM; - spin_lock_init(&pmx->lock); - pmx->pfc = pfc; pfc->pinctrl = pmx; - ret = sh_pfc_map_gpios(pfc, pmx); - if (unlikely(ret != 0)) - return ret; - - ret = sh_pfc_map_functions(pfc, pmx); - if (unlikely(ret != 0)) + ret = sh_pfc_map_pins(pfc, pmx); + if (ret < 0) return ret; - pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx); - if (IS_ERR(pmx->pctl)) - return PTR_ERR(pmx->pctl); + pmx->pctl_desc.name = DRV_NAME; + pmx->pctl_desc.owner = THIS_MODULE; + pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; + pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; + pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; + pmx->pctl_desc.pins = pmx->pins; + pmx->pctl_desc.npins = pfc->info->nr_pins; - sh_pfc_gpio_range.npins = pfc->info->last_gpio - - pfc->info->first_gpio + 1; - sh_pfc_gpio_range.base = pfc->info->first_gpio; - sh_pfc_gpio_range.pin_base = pfc->info->first_gpio; - - pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range); + pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx); + if (pmx->pctl == NULL) + return -EINVAL; return 0; } diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 13049c4c8d3..d482c40b012 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -11,170 +11,296 @@ #ifndef __SH_PFC_H #define __SH_PFC_H +#include <linux/bug.h> #include <linux/stringify.h> -#include <asm-generic/gpio.h> - -typedef unsigned short pinmux_enum_t; -typedef unsigned short pinmux_flag_t; enum { PINMUX_TYPE_NONE, - PINMUX_TYPE_FUNCTION, PINMUX_TYPE_GPIO, PINMUX_TYPE_OUTPUT, PINMUX_TYPE_INPUT, - PINMUX_TYPE_INPUT_PULLUP, - PINMUX_TYPE_INPUT_PULLDOWN, +}; - PINMUX_FLAG_TYPE, /* must be last */ +#define SH_PFC_PIN_CFG_INPUT (1 << 0) +#define SH_PFC_PIN_CFG_OUTPUT (1 << 1) +#define SH_PFC_PIN_CFG_PULL_UP (1 << 2) +#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) +#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) + +struct sh_pfc_pin { + u16 pin; + u16 enum_id; + const char *name; + unsigned int configs; }; -#define PINMUX_FLAG_DBIT_SHIFT 5 -#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT) -#define PINMUX_FLAG_DREG_SHIFT 10 -#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) +#define SH_PFC_PIN_GROUP(n) \ + { \ + .name = #n, \ + .pins = n##_pins, \ + .mux = n##_mux, \ + .nr_pins = ARRAY_SIZE(n##_pins), \ + } -struct pinmux_gpio { - pinmux_enum_t enum_id; - pinmux_flag_t flags; +struct sh_pfc_pin_group { const char *name; + const unsigned int *pins; + const unsigned int *mux; + unsigned int nr_pins; }; -#define PINMUX_GPIO(gpio, data_or_mark) \ - [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE } +#define SH_PFC_FUNCTION(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .nr_groups = ARRAY_SIZE(n##_groups), \ + } -#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 +struct sh_pfc_function { + const char *name; + const char * const *groups; + unsigned int nr_groups; +}; + +struct pinmux_func { + u16 enum_id; + const char *name; +}; struct pinmux_cfg_reg { unsigned long reg, reg_width, field_width; - unsigned long *cnt; - pinmux_enum_t *enum_ids; - unsigned long *var_field_width; + const u16 *enum_ids; + const unsigned long *var_field_width; }; #define PINMUX_CFG_REG(name, r, r_width, f_width) \ .reg = r, .reg_width = r_width, .field_width = f_width, \ - .cnt = (unsigned long [r_width / f_width]) {}, \ - .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) + .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ .reg = r, .reg_width = r_width, \ - .cnt = (unsigned long [r_width]) {}, \ - .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ - .enum_ids = (pinmux_enum_t []) + .var_field_width = (const unsigned long [r_width]) \ + { var_fw0, var_fwn, 0 }, \ + .enum_ids = (const u16 []) struct pinmux_data_reg { - unsigned long reg, reg_width, reg_shadow; - pinmux_enum_t *enum_ids; - void __iomem *mapped_reg; + unsigned long reg, reg_width; + const u16 *enum_ids; }; #define PINMUX_DATA_REG(name, r, r_width) \ .reg = r, .reg_width = r_width, \ - .enum_ids = (pinmux_enum_t [r_width]) \ + .enum_ids = (const u16 [r_width]) \ struct pinmux_irq { int irq; - pinmux_enum_t *enum_ids; + const short *gpios; }; +#ifdef CONFIG_ARCH_MULTIPLATFORM +#define PINMUX_IRQ(irq_nr, ids...) \ + { .gpios = (const short []) { ids, -1 } } +#else #define PINMUX_IRQ(irq_nr, ids...) \ - { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \ + { .irq = irq_nr, .gpios = (const short []) { ids, -1 } } +#endif struct pinmux_range { - pinmux_enum_t begin; - pinmux_enum_t end; - pinmux_enum_t force; + u16 begin; + u16 end; + u16 force; +}; + +struct sh_pfc; + +struct sh_pfc_soc_operations { + int (*init)(struct sh_pfc *pfc); + void (*exit)(struct sh_pfc *pfc); + unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); + void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias); }; struct sh_pfc_soc_info { - char *name; - pinmux_enum_t reserved_id; - struct pinmux_range data; + const char *name; + const struct sh_pfc_soc_operations *ops; + struct pinmux_range input; - struct pinmux_range input_pd; - struct pinmux_range input_pu; struct pinmux_range output; - struct pinmux_range mark; struct pinmux_range function; - unsigned first_gpio, last_gpio; + const struct sh_pfc_pin *pins; + unsigned int nr_pins; + const struct sh_pfc_pin_group *groups; + unsigned int nr_groups; + const struct sh_pfc_function *functions; + unsigned int nr_functions; + + const struct pinmux_func *func_gpios; + unsigned int nr_func_gpios; - struct pinmux_gpio *gpios; - struct pinmux_cfg_reg *cfg_regs; - struct pinmux_data_reg *data_regs; + const struct pinmux_cfg_reg *cfg_regs; + const struct pinmux_data_reg *data_regs; - pinmux_enum_t *gpio_data; + const u16 *gpio_data; unsigned int gpio_data_size; - struct pinmux_irq *gpio_irq; + const struct pinmux_irq *gpio_irq; unsigned int gpio_irq_size; unsigned long unlock_reg; }; -enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; - -/* helper macro for port */ -#define PORT_1(fn, pfx, sfx) fn(pfx, sfx) - -#define PORT_10(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ - PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ - PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ - PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) +/* ----------------------------------------------------------------------------- + * Helper macros to create pin and port lists + */ -#define PORT_90(fn, pfx, sfx) \ - PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ - PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ - PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ - PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ - PORT_10(fn, pfx##9, sfx) +/* + * sh_pfc_soc_info gpio_data array macros + */ -#define _PORT_ALL(pfx, sfx) pfx##_##sfx -#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) -#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) -#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) -#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) +#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 -/* helper macro for pinmux_enum_t */ -#define PORT_DATA_I(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) +#define PINMUX_IPSR_NOGP(ispr, fn) \ + PINMUX_DATA(fn##_MARK, FN_##fn) +#define PINMUX_IPSR_DATA(ipsr, fn) \ + PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) +#define PINMUX_IPSR_NOGM(ispr, fn, ms) \ + PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) +#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ + PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \ + PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) -#define PORT_DATA_I_PD(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ - PORT##nr##_IN, PORT##nr##_IN_PD) +/* + * GP port style (32 ports banks) + */ -#define PORT_DATA_I_PU(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ - PORT##nr##_IN, PORT##nr##_IN_PU) +#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) + +#define PORT_GP_32(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ + PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ + PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) + +#define PORT_GP_32_REV(bank, fn, sfx) \ + PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ + PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ + PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ + PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ + PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ + PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ + PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ + PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ + PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ + PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ + PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ + PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ + PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ + PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ + PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ + PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) + +/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ +#define _GP_ALL(bank, pin, name, sfx) name##_##sfx +#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) + +/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ +#define _GP_GPIO(bank, _pin, _name, sfx) \ + [(bank * 32) + _pin] = { \ + .pin = (bank * 32) + _pin, \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + } +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) -#define PORT_DATA_I_PU_PD(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ - PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) +/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ +#define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) -#define PORT_DATA_O(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) +/* + * PORT style (linear pin space) + */ -#define PORT_DATA_IO(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ - PORT##nr##_IN) +#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) + +#define PORT_10(pn, fn, pfx, sfx) \ + PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ + PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ + PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ + PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ + PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) + +#define PORT_90(pn, fn, pfx, sfx) \ + PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ + PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ + PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ + PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ + PORT_10(pn+90, fn, pfx##9, sfx) + +/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ +#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx +#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) + +/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ +#define PINMUX_GPIO(_pin) \ + [GPIO_##_pin] = { \ + .pin = (u16)-1, \ + .name = __stringify(GPIO_##_pin), \ + .enum_id = _pin##_DATA, \ + } -#define PORT_DATA_IO_PD(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ - PORT##nr##_IN, PORT##nr##_IN_PD) +/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ +#define SH_PFC_PIN_CFG(_pin, cfgs) \ + { \ + .pin = _pin, \ + .name = __stringify(PORT##_pin), \ + .enum_id = PORT##_pin##_DATA, \ + .configs = cfgs, \ + } -#define PORT_DATA_IO_PU(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ - PORT##nr##_IN, PORT##nr##_IN_PU) +/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ +#define SH_PFC_PIN_NAMED(row, col, _name) \ + { \ + .pin = PIN_NUMBER(row, col), \ + .name = __stringify(PIN_##_name), \ + .configs = SH_PFC_PIN_CFG_NO_GPIO, \ + } -#define PORT_DATA_IO_PU_PD(nr) \ - PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ - PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) +/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, + * PORT_name_OUT, PORT_name_IN marks + */ +#define _PORT_DATA(pn, pfx, sfx) \ + PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ + PORT##pfx##_OUT, PORT##pfx##_IN) +#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + +/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ +#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ + [gpio - (base)] = { \ + .name = __stringify(gpio), \ + .enum_id = data_or_mark, \ + } +#define GPIO_FN(str) \ + PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) -/* helper macro for top 4 bits in PORTnCR */ +/* + * PORTnCR macro + */ #define _PCRH(in, in_pd, in_pu, out) \ 0, (out), (in), 0, \ 0, 0, 0, 0, \ @@ -184,8 +310,7 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; #define PORTCR(nr, reg) \ { \ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ - PORT##nr##_IN_PU, PORT##nr##_OUT), \ + _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ PORT##nr##_FN0, PORT##nr##_FN1, \ PORT##nr##_FN2, PORT##nr##_FN3, \ PORT##nr##_FN4, PORT##nr##_FN5, \ diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile new file mode 100644 index 00000000000..3ffc475ce40 --- /dev/null +++ b/drivers/pinctrl/sirf/Makefile @@ -0,0 +1,5 @@ +# CSR SiRFsoc pinmux support + +obj-y += pinctrl-sirf.o +obj-y += pinctrl-prima2.o +obj-y += pinctrl-atlas6.o diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c new file mode 100644 index 00000000000..c4dd3d5cf9c --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c @@ -0,0 +1,1095 @@ +/* + * pinctrl pads, groups, functions for CSR SiRFatlasVI + * + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/pinctrl/pinctrl.h> +#include <linux/bitops.h> + +#include "pinctrl-sirf.h" + +/* + * pad list for the pinmux subsystem + * refer to atlasVI_io_table_v0.93.xls + */ +static const struct pinctrl_pin_desc sirfsoc_pads[] = { + PINCTRL_PIN(0, "gpio0-0"), + PINCTRL_PIN(1, "gpio0-1"), + PINCTRL_PIN(2, "gpio0-2"), + PINCTRL_PIN(3, "gpio0-3"), + PINCTRL_PIN(4, "pwm0"), + PINCTRL_PIN(5, "pwm1"), + PINCTRL_PIN(6, "pwm2"), + PINCTRL_PIN(7, "pwm3"), + PINCTRL_PIN(8, "warm_rst_b"), + PINCTRL_PIN(9, "odo_0"), + PINCTRL_PIN(10, "odo_1"), + PINCTRL_PIN(11, "dr_dir"), + PINCTRL_PIN(12, "rts_0"), + PINCTRL_PIN(13, "scl_1"), + PINCTRL_PIN(14, "ntrst"), + PINCTRL_PIN(15, "sda_1"), + PINCTRL_PIN(16, "x_ldd[16]"), + PINCTRL_PIN(17, "x_ldd[17]"), + PINCTRL_PIN(18, "x_ldd[18]"), + PINCTRL_PIN(19, "x_ldd[19]"), + PINCTRL_PIN(20, "x_ldd[20]"), + PINCTRL_PIN(21, "x_ldd[21]"), + PINCTRL_PIN(22, "x_ldd[22]"), + PINCTRL_PIN(23, "x_ldd[23]"), + PINCTRL_PIN(24, "gps_sgn"), + PINCTRL_PIN(25, "gps_mag"), + PINCTRL_PIN(26, "gps_clk"), + PINCTRL_PIN(27, "sd_cd_b_2"), + PINCTRL_PIN(28, "sd_vcc_on_2"), + PINCTRL_PIN(29, "sd_wp_b_2"), + PINCTRL_PIN(30, "sd_clk_3"), + PINCTRL_PIN(31, "sd_cmd_3"), + + PINCTRL_PIN(32, "x_sd_dat_3[0]"), + PINCTRL_PIN(33, "x_sd_dat_3[1]"), + PINCTRL_PIN(34, "x_sd_dat_3[2]"), + PINCTRL_PIN(35, "x_sd_dat_3[3]"), + PINCTRL_PIN(36, "usb_clk"), + PINCTRL_PIN(37, "usb_dir"), + PINCTRL_PIN(38, "usb_nxt"), + PINCTRL_PIN(39, "usb_stp"), + PINCTRL_PIN(40, "usb_dat[7]"), + PINCTRL_PIN(41, "usb_dat[6]"), + PINCTRL_PIN(42, "x_cko_1"), + PINCTRL_PIN(43, "spi_clk_1"), + PINCTRL_PIN(44, "spi_dout_1"), + PINCTRL_PIN(45, "spi_din_1"), + PINCTRL_PIN(46, "spi_en_1"), + PINCTRL_PIN(47, "x_txd_1"), + PINCTRL_PIN(48, "x_txd_2"), + PINCTRL_PIN(49, "x_rxd_1"), + PINCTRL_PIN(50, "x_rxd_2"), + PINCTRL_PIN(51, "x_usclk_0"), + PINCTRL_PIN(52, "x_utxd_0"), + PINCTRL_PIN(53, "x_urxd_0"), + PINCTRL_PIN(54, "x_utfs_0"), + PINCTRL_PIN(55, "x_urfs_0"), + PINCTRL_PIN(56, "usb_dat5"), + PINCTRL_PIN(57, "usb_dat4"), + PINCTRL_PIN(58, "usb_dat3"), + PINCTRL_PIN(59, "usb_dat2"), + PINCTRL_PIN(60, "usb_dat1"), + PINCTRL_PIN(61, "usb_dat0"), + PINCTRL_PIN(62, "x_ldd[14]"), + PINCTRL_PIN(63, "x_ldd[15]"), + + PINCTRL_PIN(64, "x_gps_gpio"), + PINCTRL_PIN(65, "x_ldd[13]"), + PINCTRL_PIN(66, "x_df_we_b"), + PINCTRL_PIN(67, "x_df_re_b"), + PINCTRL_PIN(68, "x_txd_0"), + PINCTRL_PIN(69, "x_rxd_0"), + PINCTRL_PIN(70, "x_l_lck"), + PINCTRL_PIN(71, "x_l_fck"), + PINCTRL_PIN(72, "x_l_de"), + PINCTRL_PIN(73, "x_ldd[0]"), + PINCTRL_PIN(74, "x_ldd[1]"), + PINCTRL_PIN(75, "x_ldd[2]"), + PINCTRL_PIN(76, "x_ldd[3]"), + PINCTRL_PIN(77, "x_ldd[4]"), + PINCTRL_PIN(78, "x_cko_0"), + PINCTRL_PIN(79, "x_ldd[5]"), + PINCTRL_PIN(80, "x_ldd[6]"), + PINCTRL_PIN(81, "x_ldd[7]"), + PINCTRL_PIN(82, "x_ldd[8]"), + PINCTRL_PIN(83, "x_ldd[9]"), + PINCTRL_PIN(84, "x_ldd[10]"), + PINCTRL_PIN(85, "x_ldd[11]"), + PINCTRL_PIN(86, "x_ldd[12]"), + PINCTRL_PIN(87, "x_vip_vsync"), + PINCTRL_PIN(88, "x_vip_hsync"), + PINCTRL_PIN(89, "x_vip_pxclk"), + PINCTRL_PIN(90, "x_sda_0"), + PINCTRL_PIN(91, "x_scl_0"), + PINCTRL_PIN(92, "x_df_ry_by"), + PINCTRL_PIN(93, "x_df_cs_b[1]"), + PINCTRL_PIN(94, "x_df_cs_b[0]"), + PINCTRL_PIN(95, "x_l_pclk"), + + PINCTRL_PIN(96, "x_df_dqs"), + PINCTRL_PIN(97, "x_df_wp_b"), + PINCTRL_PIN(98, "ac97_sync"), + PINCTRL_PIN(99, "ac97_bit_clk "), + PINCTRL_PIN(100, "ac97_dout"), + PINCTRL_PIN(101, "ac97_din"), + PINCTRL_PIN(102, "x_rtc_io"), + + PINCTRL_PIN(103, "x_usb1_dp"), + PINCTRL_PIN(104, "x_usb1_dn"), +}; + +static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { + { + .group = 1, + .mask = BIT(30) | BIT(31), + }, { + .group = 2, + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + BIT(20) | BIT(21) | BIT(22) | BIT(31), + }, +}; + +static const struct sirfsoc_padmux lcd_16bits_padmux = { + .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), + .muxmask = lcd_16bits_sirfsoc_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(4), + .funcval = 0, +}; + +static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, + 84, 85, 86, 95 }; + +static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { + { + .group = 2, + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + BIT(20) | BIT(21) | BIT(22) | BIT(31), + }, { + .group = 1, + .mask = BIT(30) | BIT(31), + }, { + .group = 0, + .mask = BIT(16) | BIT(17), + }, +}; + +static const struct sirfsoc_padmux lcd_18bits_padmux = { + .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), + .muxmask = lcd_18bits_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(4) | BIT(15), + .funcval = 0, +}; + +static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, + 84, 85, 86, 95 }; + +static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { + { + .group = 2, + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + BIT(20) | BIT(21) | BIT(22) | BIT(31), + }, { + .group = 1, + .mask = BIT(30) | BIT(31), + }, { + .group = 0, + .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), + }, +}; + +static const struct sirfsoc_padmux lcd_24bits_padmux = { + .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), + .muxmask = lcd_24bits_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(4) | BIT(15), + .funcval = 0, +}; + +static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, + 80, 81, 82, 83, 84, 85, 86, 95}; + +static const struct sirfsoc_muxmask lcdrom_muxmask[] = { + { + .group = 2, + .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | + BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | + BIT(20) | BIT(21) | BIT(22) | BIT(31), + }, { + .group = 1, + .mask = BIT(30) | BIT(31), + }, { + .group = 0, + .mask = BIT(8), + }, +}; + +static const struct sirfsoc_padmux lcdrom_padmux = { + .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), + .muxmask = lcdrom_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(4), + .funcval = BIT(4), +}; + +static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, + 84, 85, 86, 95}; + +static const struct sirfsoc_muxmask uart0_muxmask[] = { + { + .group = 0, + .mask = BIT(12), + }, { + .group = 1, + .mask = BIT(23), + }, { + .group = 2, + .mask = BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux uart0_padmux = { + .muxmask_counts = ARRAY_SIZE(uart0_muxmask), + .muxmask = uart0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(9), + .funcval = BIT(9), +}; + +static const unsigned uart0_pins[] = { 12, 55, 68, 69 }; + +static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { + { + .group = 2, + .mask = BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask), + .muxmask = uart0_nostreamctrl_muxmask, +}; + +static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 }; + +static const struct sirfsoc_muxmask uart1_muxmask[] = { + { + .group = 1, + .mask = BIT(15) | BIT(17), + }, +}; + +static const struct sirfsoc_padmux uart1_padmux = { + .muxmask_counts = ARRAY_SIZE(uart1_muxmask), + .muxmask = uart1_muxmask, +}; + +static const unsigned uart1_pins[] = { 47, 49 }; + +static const struct sirfsoc_muxmask uart2_muxmask[] = { + { + .group = 0, + .mask = BIT(10) | BIT(14), + }, { + .group = 1, + .mask = BIT(16) | BIT(18), + }, +}; + +static const struct sirfsoc_padmux uart2_padmux = { + .muxmask_counts = ARRAY_SIZE(uart2_muxmask), + .muxmask = uart2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(10), + .funcval = BIT(10), +}; + +static const unsigned uart2_pins[] = { 10, 14, 48, 50 }; + +static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(16) | BIT(18), + }, +}; + +static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask), + .muxmask = uart2_nostreamctrl_muxmask, +}; + +static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; + +static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { + { + .group = 0, + .mask = BIT(30) | BIT(31), + }, { + .group = 1, + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), + }, +}; + +static const struct sirfsoc_padmux sdmmc3_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), + .muxmask = sdmmc3_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(7), + .funcval = 0, +}; + +static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; + +static const struct sirfsoc_muxmask spi0_muxmask[] = { + { + .group = 0, + .mask = BIT(30), + }, { + .group = 1, + .mask = BIT(0) | BIT(2) | BIT(3), + }, +}; + +static const struct sirfsoc_padmux spi0_padmux = { + .muxmask_counts = ARRAY_SIZE(spi0_muxmask), + .muxmask = spi0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(7), + .funcval = BIT(7), +}; + +static const unsigned spi0_pins[] = { 30, 32, 34, 35 }; + +static const struct sirfsoc_muxmask cko1_muxmask[] = { + { + .group = 1, + .mask = BIT(10), + }, +}; + +static const struct sirfsoc_padmux cko1_padmux = { + .muxmask_counts = ARRAY_SIZE(cko1_muxmask), + .muxmask = cko1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(3), + .funcval = 0, +}; + +static const unsigned cko1_pins[] = { 42 }; + +static const struct sirfsoc_muxmask i2s_muxmask[] = { + { + .group = 1, + .mask = BIT(10), + }, { + .group = 3, + .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux i2s_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_muxmask), + .muxmask = i2s_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(3), + .funcval = BIT(3), +}; + +static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 }; + +static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { + { + .group = 1, + .mask = BIT(10), + }, { + .group = 3, + .mask = BIT(2) | BIT(3) | BIT(4), + }, +}; + +static const struct sirfsoc_padmux i2s_no_din_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), + .muxmask = i2s_no_din_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(3), + .funcval = BIT(3), +}; + +static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 }; + +static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { + { + .group = 1, + .mask = BIT(10) | BIT(20) | BIT(23), + }, { + .group = 3, + .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux i2s_6chn_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), + .muxmask = i2s_6chn_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(3) | BIT(9), + .funcval = BIT(1) | BIT(3) | BIT(9), +}; + +static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 }; + +static const struct sirfsoc_muxmask ac97_muxmask[] = { + { + .group = 3, + .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux ac97_padmux = { + .muxmask_counts = ARRAY_SIZE(ac97_muxmask), + .muxmask = ac97_muxmask, +}; + +static const unsigned ac97_pins[] = { 98, 99, 100, 101 }; + +static const struct sirfsoc_muxmask spi1_muxmask[] = { + { + .group = 1, + .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), + }, +}; + +static const struct sirfsoc_padmux spi1_padmux = { + .muxmask_counts = ARRAY_SIZE(spi1_muxmask), + .muxmask = spi1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(16), + .funcval = 0, +}; + +static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; + +static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { + { + .group = 2, + .mask = BIT(2) | BIT(3), + }, +}; + +static const struct sirfsoc_padmux sdmmc1_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), + .muxmask = sdmmc1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(5), + .funcval = BIT(5), +}; + +static const unsigned sdmmc1_pins[] = { 66, 67 }; + +static const struct sirfsoc_muxmask gps_muxmask[] = { + { + .group = 0, + .mask = BIT(24) | BIT(25) | BIT(26), + }, +}; + +static const struct sirfsoc_padmux gps_padmux = { + .muxmask_counts = ARRAY_SIZE(gps_muxmask), + .muxmask = gps_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(13), + .funcval = 0, +}; + +static const unsigned gps_pins[] = { 24, 25, 26 }; + +static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { + { + .group = 0, + .mask = BIT(24) | BIT(25) | BIT(26), + }, +}; + +static const struct sirfsoc_padmux sdmmc5_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), + .muxmask = sdmmc5_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(13), + .funcval = BIT(13), +}; + +static const unsigned sdmmc5_pins[] = { 24, 25, 26 }; + +static const struct sirfsoc_muxmask usp0_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), + }, +}; + +static const struct sirfsoc_padmux usp0_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_muxmask), + .muxmask = usp0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(9), + .funcval = 0, +}; + +static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; + +static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), + }, +}; + +static const struct sirfsoc_padmux usp0_only_utfs_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask), + .muxmask = usp0_only_utfs_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(6), + .funcval = 0, +}; + +static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 }; + +static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23), + }, +}; + +static const struct sirfsoc_padmux usp0_only_urfs_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask), + .muxmask = usp0_only_urfs_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(9), + .funcval = 0, +}; + +static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 }; + +static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(20) | BIT(21), + }, +}; + +static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask), + .muxmask = usp0_uart_nostreamctrl_muxmask, +}; + +static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 }; +static const struct sirfsoc_muxmask usp1_muxmask[] = { + { + .group = 0, + .mask = BIT(15), + }, { + .group = 1, + .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), + }, +}; + +static const struct sirfsoc_padmux usp1_padmux = { + .muxmask_counts = ARRAY_SIZE(usp1_muxmask), + .muxmask = usp1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(16), + .funcval = BIT(16), +}; + +static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 }; + +static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(12) | BIT(13), + }, +}; + +static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask), + .muxmask = usp1_uart_nostreamctrl_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(16), + .funcval = BIT(16), +}; + +static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 }; + +static const struct sirfsoc_muxmask nand_muxmask[] = { + { + .group = 2, + .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), + }, { + .group = 3, + .mask = BIT(0) | BIT(1), + }, +}; + +static const struct sirfsoc_padmux nand_padmux = { + .muxmask_counts = ARRAY_SIZE(nand_muxmask), + .muxmask = nand_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(5) | BIT(19), + .funcval = 0, +}; + +static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 }; + +static const struct sirfsoc_muxmask sdmmc0_muxmask[] = { + { + .group = 3, + .mask = BIT(1), + }, +}; + +static const struct sirfsoc_padmux sdmmc0_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask), + .muxmask = sdmmc0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(5) | BIT(19), + .funcval = BIT(19), +}; + +static const unsigned sdmmc0_pins[] = { 97 }; + +static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { + { + .group = 0, + .mask = BIT(27) | BIT(28) | BIT(29), + }, +}; + +static const struct sirfsoc_padmux sdmmc2_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), + .muxmask = sdmmc2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(11), + .funcval = 0, +}; + +static const unsigned sdmmc2_pins[] = { 27, 28, 29 }; + +static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = { + { + .group = 0, + .mask = BIT(27) | BIT(28), + }, +}; + +static const struct sirfsoc_padmux sdmmc2_nowp_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask), + .muxmask = sdmmc2_nowp_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(11), + .funcval = 0, +}; + +static const unsigned sdmmc2_nowp_pins[] = { 27, 28 }; + +static const struct sirfsoc_muxmask cko0_muxmask[] = { + { + .group = 2, + .mask = BIT(14), + }, +}; + +static const struct sirfsoc_padmux cko0_padmux = { + .muxmask_counts = ARRAY_SIZE(cko0_muxmask), + .muxmask = cko0_muxmask, +}; + +static const unsigned cko0_pins[] = { 78 }; + +static const struct sirfsoc_muxmask vip_muxmask[] = { + { + .group = 1, + .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9) + | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) | + BIT(29), + }, +}; + +static const struct sirfsoc_padmux vip_padmux = { + .muxmask_counts = ARRAY_SIZE(vip_muxmask), + .muxmask = vip_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(18), + .funcval = BIT(18), +}; + +static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 }; + +static const struct sirfsoc_muxmask vip_noupli_muxmask[] = { + { + .group = 0, + .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) + | BIT(21) | BIT(22) | BIT(23), + }, { + .group = 2, + .mask = BIT(23) | BIT(24) | BIT(25), + }, +}; + +static const struct sirfsoc_padmux vip_noupli_padmux = { + .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask), + .muxmask = vip_noupli_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(15), + .funcval = BIT(15), +}; + +static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 }; + +static const struct sirfsoc_muxmask i2c0_muxmask[] = { + { + .group = 2, + .mask = BIT(26) | BIT(27), + }, +}; + +static const struct sirfsoc_padmux i2c0_padmux = { + .muxmask_counts = ARRAY_SIZE(i2c0_muxmask), + .muxmask = i2c0_muxmask, +}; + +static const unsigned i2c0_pins[] = { 90, 91 }; + +static const struct sirfsoc_muxmask i2c1_muxmask[] = { + { + .group = 0, + .mask = BIT(13) | BIT(15), + }, +}; + +static const struct sirfsoc_padmux i2c1_padmux = { + .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), + .muxmask = i2c1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(16), + .funcval = 0, +}; + +static const unsigned i2c1_pins[] = { 13, 15 }; + +static const struct sirfsoc_muxmask pwm0_muxmask[] = { + { + .group = 0, + .mask = BIT(4), + }, +}; + +static const struct sirfsoc_padmux pwm0_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), + .muxmask = pwm0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(12), + .funcval = 0, +}; + +static const unsigned pwm0_pins[] = { 4 }; + +static const struct sirfsoc_muxmask pwm1_muxmask[] = { + { + .group = 0, + .mask = BIT(5), + }, +}; + +static const struct sirfsoc_padmux pwm1_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm1_muxmask), + .muxmask = pwm1_muxmask, +}; + +static const unsigned pwm1_pins[] = { 5 }; + +static const struct sirfsoc_muxmask pwm2_muxmask[] = { + { + .group = 0, + .mask = BIT(6), + }, +}; + +static const struct sirfsoc_padmux pwm2_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm2_muxmask), + .muxmask = pwm2_muxmask, +}; + +static const unsigned pwm2_pins[] = { 6 }; + +static const struct sirfsoc_muxmask pwm3_muxmask[] = { + { + .group = 0, + .mask = BIT(7), + }, +}; + +static const struct sirfsoc_padmux pwm3_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm3_muxmask), + .muxmask = pwm3_muxmask, +}; + +static const unsigned pwm3_pins[] = { 7 }; + +static const struct sirfsoc_muxmask pwm4_muxmask[] = { + { + .group = 2, + .mask = BIT(14), + }, +}; + +static const struct sirfsoc_padmux pwm4_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm4_muxmask), + .muxmask = pwm4_muxmask, +}; + +static const unsigned pwm4_pins[] = { 78 }; + +static const struct sirfsoc_muxmask warm_rst_muxmask[] = { + { + .group = 0, + .mask = BIT(8), + }, +}; + +static const struct sirfsoc_padmux warm_rst_padmux = { + .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), + .muxmask = warm_rst_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(4), + .funcval = 0, +}; + +static const unsigned warm_rst_pins[] = { 8 }; + +static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = { + { + .group = 1, + .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) + | BIT(9) | BIT(24) | BIT(25) | BIT(26) | + BIT(27) | BIT(28) | BIT(29), + }, +}; +static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = { + .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask), + .muxmask = usb0_upli_drvbus_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(18), + .funcval = 0, +}; + +static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 }; + +static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { + { + .group = 0, + .mask = BIT(28), + }, +}; + +static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { + .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), + .muxmask = usb1_utmi_drvbus_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(11), + .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ +}; + +static const unsigned usb1_utmi_drvbus_pins[] = { 28 }; + +static const struct sirfsoc_padmux usb1_dp_dn_padmux = { + .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, + .funcmask = BIT(2), + .funcval = BIT(2), +}; + +static const unsigned usb1_dp_dn_pins[] = { 103, 104 }; + +static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = { + .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, + .funcmask = BIT(2), + .funcval = 0, +}; + +static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 }; + +static const struct sirfsoc_muxmask pulse_count_muxmask[] = { + { + .group = 0, + .mask = BIT(9) | BIT(10) | BIT(11), + }, +}; + +static const struct sirfsoc_padmux pulse_count_padmux = { + .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask), + .muxmask = pulse_count_muxmask, +}; + +static const unsigned pulse_count_pins[] = { 9, 10, 11 }; + +static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { + SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), + SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), + SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), + SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), + SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), + SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), + SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), + SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), + SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp", + usp0_uart_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins), + SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins), + SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), + SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp", + usp1_uart_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), + SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), + SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), + SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins), + SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins), + SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins), + SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins), + SIRFSOC_PIN_GROUP("vipgrp", vip_pins), + SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins), + SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), + SIRFSOC_PIN_GROUP("cko0grp", cko0_pins), + SIRFSOC_PIN_GROUP("cko1grp", cko1_pins), + SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), + SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), + SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), + SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins), + SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins), + SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), + SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins), + SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), + SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), + SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), + SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), + SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), + SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), + SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins), + SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), + SIRFSOC_PIN_GROUP("nandgrp", nand_pins), + SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), + SIRFSOC_PIN_GROUP("spi1grp", spi1_pins), + SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), +}; + +static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; +static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; +static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; +static const char * const lcdromgrp[] = { "lcdromgrp" }; +static const char * const uart0grp[] = { "uart0grp" }; +static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" }; +static const char * const uart1grp[] = { "uart1grp" }; +static const char * const uart2grp[] = { "uart2grp" }; +static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; +static const char * const usp0_uart_nostreamctrl_grp[] = { + "usp0_uart_nostreamctrl_grp" }; +static const char * const usp0grp[] = { "usp0grp" }; +static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; +static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; + +static const char * const usp1grp[] = { "usp1grp" }; +static const char * const usp1_uart_nostreamctrl_grp[] = { + "usp1_uart_nostreamctrl_grp" }; +static const char * const i2c0grp[] = { "i2c0grp" }; +static const char * const i2c1grp[] = { "i2c1grp" }; +static const char * const pwm0grp[] = { "pwm0grp" }; +static const char * const pwm1grp[] = { "pwm1grp" }; +static const char * const pwm2grp[] = { "pwm2grp" }; +static const char * const pwm3grp[] = { "pwm3grp" }; +static const char * const pwm4grp[] = { "pwm4grp" }; +static const char * const vipgrp[] = { "vipgrp" }; +static const char * const vip_noupligrp[] = { "vip_noupligrp" }; +static const char * const warm_rstgrp[] = { "warm_rstgrp" }; +static const char * const cko0grp[] = { "cko0grp" }; +static const char * const cko1grp[] = { "cko1grp" }; +static const char * const sdmmc0grp[] = { "sdmmc0grp" }; +static const char * const sdmmc1grp[] = { "sdmmc1grp" }; +static const char * const sdmmc2grp[] = { "sdmmc2grp" }; +static const char * const sdmmc3grp[] = { "sdmmc3grp" }; +static const char * const sdmmc5grp[] = { "sdmmc5grp" }; +static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" }; +static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; +static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; +static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; +static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; +static const char * const pulse_countgrp[] = { "pulse_countgrp" }; +static const char * const i2sgrp[] = { "i2sgrp" }; +static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; +static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; +static const char * const ac97grp[] = { "ac97grp" }; +static const char * const nandgrp[] = { "nandgrp" }; +static const char * const spi0grp[] = { "spi0grp" }; +static const char * const spi1grp[] = { "spi1grp" }; +static const char * const gpsgrp[] = { "gpsgrp" }; + +static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { + SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), + SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), + SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), + SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), + SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), + SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, + uart0_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), + SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), + SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), + SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", + usp0_uart_nostreamctrl_grp, + usp0_uart_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, + usp0_only_utfs_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, + usp0_only_urfs_padmux), + SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), + SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", + usp1_uart_nostreamctrl_grp, + usp1_uart_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), + SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), + SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), + SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux), + SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux), + SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux), + SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux), + SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux), + SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux), + SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux), + SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux), + SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux), + SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), + SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), + SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), + SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), + SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), + SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), + SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), + SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), + SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), + SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux), + SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), +}; + +struct sirfsoc_pinctrl_data atlas6_pinctrl_data = { + (struct pinctrl_pin_desc *)sirfsoc_pads, + ARRAY_SIZE(sirfsoc_pads), + (struct sirfsoc_pin_group *)sirfsoc_pin_groups, + ARRAY_SIZE(sirfsoc_pin_groups), + (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions, + ARRAY_SIZE(sirfsoc_pmx_functions), +}; + diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c new file mode 100644 index 00000000000..8aa76f0776d --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-prima2.c @@ -0,0 +1,1037 @@ +/* + * pinctrl pads, groups, functions for CSR SiRFprimaII + * + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/pinctrl/pinctrl.h> +#include <linux/bitops.h> + +#include "pinctrl-sirf.h" + +/* + * pad list for the pinmux subsystem + * refer to CS-131858-DC-6A.xls + */ +static const struct pinctrl_pin_desc sirfsoc_pads[] = { + PINCTRL_PIN(0, "gpio0-0"), + PINCTRL_PIN(1, "gpio0-1"), + PINCTRL_PIN(2, "gpio0-2"), + PINCTRL_PIN(3, "gpio0-3"), + PINCTRL_PIN(4, "pwm0"), + PINCTRL_PIN(5, "pwm1"), + PINCTRL_PIN(6, "pwm2"), + PINCTRL_PIN(7, "pwm3"), + PINCTRL_PIN(8, "warm_rst_b"), + PINCTRL_PIN(9, "odo_0"), + PINCTRL_PIN(10, "odo_1"), + PINCTRL_PIN(11, "dr_dir"), + PINCTRL_PIN(12, "viprom_fa"), + PINCTRL_PIN(13, "scl_1"), + PINCTRL_PIN(14, "ntrst"), + PINCTRL_PIN(15, "sda_1"), + PINCTRL_PIN(16, "x_ldd[16]"), + PINCTRL_PIN(17, "x_ldd[17]"), + PINCTRL_PIN(18, "x_ldd[18]"), + PINCTRL_PIN(19, "x_ldd[19]"), + PINCTRL_PIN(20, "x_ldd[20]"), + PINCTRL_PIN(21, "x_ldd[21]"), + PINCTRL_PIN(22, "x_ldd[22]"), + PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"), + PINCTRL_PIN(24, "gps_sgn"), + PINCTRL_PIN(25, "gps_mag"), + PINCTRL_PIN(26, "gps_clk"), + PINCTRL_PIN(27, "sd_cd_b_1"), + PINCTRL_PIN(28, "sd_vcc_on_1"), + PINCTRL_PIN(29, "sd_wp_b_1"), + PINCTRL_PIN(30, "sd_clk_3"), + PINCTRL_PIN(31, "sd_cmd_3"), + + PINCTRL_PIN(32, "x_sd_dat_3[0]"), + PINCTRL_PIN(33, "x_sd_dat_3[1]"), + PINCTRL_PIN(34, "x_sd_dat_3[2]"), + PINCTRL_PIN(35, "x_sd_dat_3[3]"), + PINCTRL_PIN(36, "x_sd_clk_4"), + PINCTRL_PIN(37, "x_sd_cmd_4"), + PINCTRL_PIN(38, "x_sd_dat_4[0]"), + PINCTRL_PIN(39, "x_sd_dat_4[1]"), + PINCTRL_PIN(40, "x_sd_dat_4[2]"), + PINCTRL_PIN(41, "x_sd_dat_4[3]"), + PINCTRL_PIN(42, "x_cko_1"), + PINCTRL_PIN(43, "x_ac97_bit_clk"), + PINCTRL_PIN(44, "x_ac97_dout"), + PINCTRL_PIN(45, "x_ac97_din"), + PINCTRL_PIN(46, "x_ac97_sync"), + PINCTRL_PIN(47, "x_txd_1"), + PINCTRL_PIN(48, "x_txd_2"), + PINCTRL_PIN(49, "x_rxd_1"), + PINCTRL_PIN(50, "x_rxd_2"), + PINCTRL_PIN(51, "x_usclk_0"), + PINCTRL_PIN(52, "x_utxd_0"), + PINCTRL_PIN(53, "x_urxd_0"), + PINCTRL_PIN(54, "x_utfs_0"), + PINCTRL_PIN(55, "x_urfs_0"), + PINCTRL_PIN(56, "x_usclk_1"), + PINCTRL_PIN(57, "x_utxd_1"), + PINCTRL_PIN(58, "x_urxd_1"), + PINCTRL_PIN(59, "x_utfs_1"), + PINCTRL_PIN(60, "x_urfs_1"), + PINCTRL_PIN(61, "x_usclk_2"), + PINCTRL_PIN(62, "x_utxd_2"), + PINCTRL_PIN(63, "x_urxd_2"), + + PINCTRL_PIN(64, "x_utfs_2"), + PINCTRL_PIN(65, "x_urfs_2"), + PINCTRL_PIN(66, "x_df_we_b"), + PINCTRL_PIN(67, "x_df_re_b"), + PINCTRL_PIN(68, "x_txd_0"), + PINCTRL_PIN(69, "x_rxd_0"), + PINCTRL_PIN(78, "x_cko_0"), + PINCTRL_PIN(79, "x_vip_pxd[7]"), + PINCTRL_PIN(80, "x_vip_pxd[6]"), + PINCTRL_PIN(81, "x_vip_pxd[5]"), + PINCTRL_PIN(82, "x_vip_pxd[4]"), + PINCTRL_PIN(83, "x_vip_pxd[3]"), + PINCTRL_PIN(84, "x_vip_pxd[2]"), + PINCTRL_PIN(85, "x_vip_pxd[1]"), + PINCTRL_PIN(86, "x_vip_pxd[0]"), + PINCTRL_PIN(87, "x_vip_vsync"), + PINCTRL_PIN(88, "x_vip_hsync"), + PINCTRL_PIN(89, "x_vip_pxclk"), + PINCTRL_PIN(90, "x_sda_0"), + PINCTRL_PIN(91, "x_scl_0"), + PINCTRL_PIN(92, "x_df_ry_by"), + PINCTRL_PIN(93, "x_df_cs_b[1]"), + PINCTRL_PIN(94, "x_df_cs_b[0]"), + PINCTRL_PIN(95, "x_l_pclk"), + + PINCTRL_PIN(96, "x_l_lck"), + PINCTRL_PIN(97, "x_l_fck"), + PINCTRL_PIN(98, "x_l_de"), + PINCTRL_PIN(99, "x_ldd[0]"), + PINCTRL_PIN(100, "x_ldd[1]"), + PINCTRL_PIN(101, "x_ldd[2]"), + PINCTRL_PIN(102, "x_ldd[3]"), + PINCTRL_PIN(103, "x_ldd[4]"), + PINCTRL_PIN(104, "x_ldd[5]"), + PINCTRL_PIN(105, "x_ldd[6]"), + PINCTRL_PIN(106, "x_ldd[7]"), + PINCTRL_PIN(107, "x_ldd[8]"), + PINCTRL_PIN(108, "x_ldd[9]"), + PINCTRL_PIN(109, "x_ldd[10]"), + PINCTRL_PIN(110, "x_ldd[11]"), + PINCTRL_PIN(111, "x_ldd[12]"), + PINCTRL_PIN(112, "x_ldd[13]"), + PINCTRL_PIN(113, "x_ldd[14]"), + PINCTRL_PIN(114, "x_ldd[15]"), + + PINCTRL_PIN(115, "x_usb1_dp"), + PINCTRL_PIN(116, "x_usb1_dn"), +}; + +static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { + { + .group = 3, + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | + BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | + BIT(17) | BIT(18), + }, { + .group = 2, + .mask = BIT(31), + }, +}; + +static const struct sirfsoc_padmux lcd_16bits_padmux = { + .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), + .muxmask = lcd_16bits_sirfsoc_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(4), + .funcval = 0, +}; + +static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; + +static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { + { + .group = 3, + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | + BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | + BIT(17) | BIT(18), + }, { + .group = 2, + .mask = BIT(31), + }, { + .group = 0, + .mask = BIT(16) | BIT(17), + }, +}; + +static const struct sirfsoc_padmux lcd_18bits_padmux = { + .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), + .muxmask = lcd_18bits_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(4), + .funcval = 0, +}; + +static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; + +static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { + { + .group = 3, + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | + BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | + BIT(17) | BIT(18), + }, { + .group = 2, + .mask = BIT(31), + }, { + .group = 0, + .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), + }, +}; + +static const struct sirfsoc_padmux lcd_24bits_padmux = { + .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), + .muxmask = lcd_24bits_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(4), + .funcval = 0, +}; + +static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; + +static const struct sirfsoc_muxmask lcdrom_muxmask[] = { + { + .group = 3, + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | + BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | + BIT(17) | BIT(18), + }, { + .group = 2, + .mask = BIT(31), + }, { + .group = 0, + .mask = BIT(23), + }, +}; + +static const struct sirfsoc_padmux lcdrom_padmux = { + .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), + .muxmask = lcdrom_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(4), + .funcval = BIT(4), +}; + +static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; + +static const struct sirfsoc_muxmask uart0_muxmask[] = { + { + .group = 2, + .mask = BIT(4) | BIT(5), + }, { + .group = 1, + .mask = BIT(23) | BIT(28), + }, +}; + +static const struct sirfsoc_padmux uart0_padmux = { + .muxmask_counts = ARRAY_SIZE(uart0_muxmask), + .muxmask = uart0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(9), + .funcval = BIT(9), +}; + +static const unsigned uart0_pins[] = { 55, 60, 68, 69 }; + +static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { + { + .group = 2, + .mask = BIT(4) | BIT(5), + }, +}; + +static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask), + .muxmask = uart0_nostreamctrl_muxmask, +}; + +static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 }; + +static const struct sirfsoc_muxmask uart1_muxmask[] = { + { + .group = 1, + .mask = BIT(15) | BIT(17), + }, +}; + +static const struct sirfsoc_padmux uart1_padmux = { + .muxmask_counts = ARRAY_SIZE(uart1_muxmask), + .muxmask = uart1_muxmask, +}; + +static const unsigned uart1_pins[] = { 47, 49 }; + +static const struct sirfsoc_muxmask uart2_muxmask[] = { + { + .group = 1, + .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27), + }, +}; + +static const struct sirfsoc_padmux uart2_padmux = { + .muxmask_counts = ARRAY_SIZE(uart2_muxmask), + .muxmask = uart2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(10), + .funcval = BIT(10), +}; + +static const unsigned uart2_pins[] = { 48, 50, 56, 59 }; + +static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(16) | BIT(18), + }, +}; + +static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask), + .muxmask = uart2_nostreamctrl_muxmask, +}; + +static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; + +static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { + { + .group = 0, + .mask = BIT(30) | BIT(31), + }, { + .group = 1, + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), + }, +}; + +static const struct sirfsoc_padmux sdmmc3_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), + .muxmask = sdmmc3_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(7), + .funcval = 0, +}; + +static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; + +static const struct sirfsoc_muxmask spi0_muxmask[] = { + { + .group = 1, + .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), + }, +}; + +static const struct sirfsoc_padmux spi0_padmux = { + .muxmask_counts = ARRAY_SIZE(spi0_muxmask), + .muxmask = spi0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(7), + .funcval = BIT(7), +}; + +static const unsigned spi0_pins[] = { 32, 33, 34, 35 }; + +static const struct sirfsoc_muxmask sdmmc4_muxmask[] = { + { + .group = 1, + .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9), + }, +}; + +static const struct sirfsoc_padmux sdmmc4_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask), + .muxmask = sdmmc4_muxmask, +}; + +static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 }; + +static const struct sirfsoc_muxmask cko1_muxmask[] = { + { + .group = 1, + .mask = BIT(10), + }, +}; + +static const struct sirfsoc_padmux cko1_padmux = { + .muxmask_counts = ARRAY_SIZE(cko1_muxmask), + .muxmask = cko1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(3), + .funcval = 0, +}; + +static const unsigned cko1_pins[] = { 42 }; + +static const struct sirfsoc_muxmask i2s_muxmask[] = { + { + .group = 1, + .mask = + BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19) + | BIT(23) | BIT(28), + }, +}; + +static const struct sirfsoc_padmux i2s_padmux = { + .muxmask_counts = ARRAY_SIZE(i2s_muxmask), + .muxmask = i2s_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(3) | BIT(9), + .funcval = BIT(3), +}; + +static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 }; + +static const struct sirfsoc_muxmask ac97_muxmask[] = { + { + .group = 1, + .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), + }, +}; + +static const struct sirfsoc_padmux ac97_padmux = { + .muxmask_counts = ARRAY_SIZE(ac97_muxmask), + .muxmask = ac97_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(8), + .funcval = 0, +}; + +static const unsigned ac97_pins[] = { 43, 44, 45, 46 }; + +static const struct sirfsoc_muxmask spi1_muxmask[] = { + { + .group = 1, + .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), + }, +}; + +static const struct sirfsoc_padmux spi1_padmux = { + .muxmask_counts = ARRAY_SIZE(spi1_muxmask), + .muxmask = spi1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(8), + .funcval = BIT(8), +}; + +static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; + +static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { + { + .group = 0, + .mask = BIT(27) | BIT(28) | BIT(29), + }, +}; + +static const struct sirfsoc_padmux sdmmc1_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), + .muxmask = sdmmc1_muxmask, +}; + +static const unsigned sdmmc1_pins[] = { 27, 28, 29 }; + +static const struct sirfsoc_muxmask gps_muxmask[] = { + { + .group = 0, + .mask = BIT(24) | BIT(25) | BIT(26), + }, +}; + +static const struct sirfsoc_padmux gps_padmux = { + .muxmask_counts = ARRAY_SIZE(gps_muxmask), + .muxmask = gps_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(12) | BIT(13) | BIT(14), + .funcval = BIT(12), +}; + +static const unsigned gps_pins[] = { 24, 25, 26 }; + +static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { + { + .group = 0, + .mask = BIT(24) | BIT(25) | BIT(26), + }, +}; + +static const struct sirfsoc_padmux sdmmc5_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), + .muxmask = sdmmc5_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(13) | BIT(14), + .funcval = BIT(13) | BIT(14), +}; + +static const unsigned sdmmc5_pins[] = { 24, 25, 26 }; + +static const struct sirfsoc_muxmask usp0_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), + }, +}; + +static const struct sirfsoc_padmux usp0_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_muxmask), + .muxmask = usp0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9), + .funcval = 0, +}; + +static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; + +static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), + }, +}; + +static const struct sirfsoc_padmux usp0_only_utfs_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask), + .muxmask = usp0_only_utfs_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(6), + .funcval = 0, +}; + +static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 }; + +static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = { + { + .group = 1, + .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23), + }, +}; + +static const struct sirfsoc_padmux usp0_only_urfs_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask), + .muxmask = usp0_only_urfs_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(2) | BIT(9), + .funcval = 0, +}; + +static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 }; + +static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(20) | BIT(21), + }, +}; + +static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask), + .muxmask = usp0_uart_nostreamctrl_muxmask, +}; + +static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 }; + +static const struct sirfsoc_muxmask usp1_muxmask[] = { + { + .group = 1, + .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28), + }, +}; + +static const struct sirfsoc_padmux usp1_padmux = { + .muxmask_counts = ARRAY_SIZE(usp1_muxmask), + .muxmask = usp1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11), + .funcval = 0, +}; + +static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 }; + +static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(25) | BIT(26), + }, +}; + +static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask), + .muxmask = usp1_uart_nostreamctrl_muxmask, +}; + +static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 }; + +static const struct sirfsoc_muxmask usp2_muxmask[] = { + { + .group = 1, + .mask = BIT(29) | BIT(30) | BIT(31), + }, { + .group = 2, + .mask = BIT(0) | BIT(1), + }, +}; + +static const struct sirfsoc_padmux usp2_padmux = { + .muxmask_counts = ARRAY_SIZE(usp2_muxmask), + .muxmask = usp2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(13) | BIT(14), + .funcval = 0, +}; + +static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 }; + +static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(30) | BIT(31), + }, +}; + +static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask), + .muxmask = usp2_uart_nostreamctrl_muxmask, +}; + +static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 }; + +static const struct sirfsoc_muxmask nand_muxmask[] = { + { + .group = 2, + .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), + }, +}; + +static const struct sirfsoc_padmux nand_padmux = { + .muxmask_counts = ARRAY_SIZE(nand_muxmask), + .muxmask = nand_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(5), + .funcval = 0, +}; + +static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 }; + +static const struct sirfsoc_padmux sdmmc0_padmux = { + .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(5), + .funcval = 0, +}; + +static const unsigned sdmmc0_pins[] = { }; + +static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { + { + .group = 2, + .mask = BIT(2) | BIT(3), + }, +}; + +static const struct sirfsoc_padmux sdmmc2_padmux = { + .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), + .muxmask = sdmmc2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(5), + .funcval = BIT(5), +}; + +static const unsigned sdmmc2_pins[] = { 66, 67 }; + +static const struct sirfsoc_muxmask cko0_muxmask[] = { + { + .group = 2, + .mask = BIT(14), + }, +}; + +static const struct sirfsoc_padmux cko0_padmux = { + .muxmask_counts = ARRAY_SIZE(cko0_muxmask), + .muxmask = cko0_muxmask, +}; + +static const unsigned cko0_pins[] = { 78 }; + +static const struct sirfsoc_muxmask vip_muxmask[] = { + { + .group = 2, + .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) + | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | + BIT(25), + }, +}; + +static const struct sirfsoc_padmux vip_padmux = { + .muxmask_counts = ARRAY_SIZE(vip_muxmask), + .muxmask = vip_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(0), + .funcval = 0, +}; + +static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; + +static const struct sirfsoc_muxmask i2c0_muxmask[] = { + { + .group = 2, + .mask = BIT(26) | BIT(27), + }, +}; + +static const struct sirfsoc_padmux i2c0_padmux = { + .muxmask_counts = ARRAY_SIZE(i2c0_muxmask), + .muxmask = i2c0_muxmask, +}; + +static const unsigned i2c0_pins[] = { 90, 91 }; + +static const struct sirfsoc_muxmask i2c1_muxmask[] = { + { + .group = 0, + .mask = BIT(13) | BIT(15), + }, +}; + +static const struct sirfsoc_padmux i2c1_padmux = { + .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), + .muxmask = i2c1_muxmask, +}; + +static const unsigned i2c1_pins[] = { 13, 15 }; + +static const struct sirfsoc_muxmask viprom_muxmask[] = { + { + .group = 2, + .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) + | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | + BIT(25), + }, { + .group = 0, + .mask = BIT(12), + }, +}; + +static const struct sirfsoc_padmux viprom_padmux = { + .muxmask_counts = ARRAY_SIZE(viprom_muxmask), + .muxmask = viprom_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(0), + .funcval = BIT(0), +}; + +static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; + +static const struct sirfsoc_muxmask pwm0_muxmask[] = { + { + .group = 0, + .mask = BIT(4), + }, +}; + +static const struct sirfsoc_padmux pwm0_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), + .muxmask = pwm0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(12), + .funcval = 0, +}; + +static const unsigned pwm0_pins[] = { 4 }; + +static const struct sirfsoc_muxmask pwm1_muxmask[] = { + { + .group = 0, + .mask = BIT(5), + }, +}; + +static const struct sirfsoc_padmux pwm1_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm1_muxmask), + .muxmask = pwm1_muxmask, +}; + +static const unsigned pwm1_pins[] = { 5 }; + +static const struct sirfsoc_muxmask pwm2_muxmask[] = { + { + .group = 0, + .mask = BIT(6), + }, +}; + +static const struct sirfsoc_padmux pwm2_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm2_muxmask), + .muxmask = pwm2_muxmask, +}; + +static const unsigned pwm2_pins[] = { 6 }; + +static const struct sirfsoc_muxmask pwm3_muxmask[] = { + { + .group = 0, + .mask = BIT(7), + }, +}; + +static const struct sirfsoc_padmux pwm3_padmux = { + .muxmask_counts = ARRAY_SIZE(pwm3_muxmask), + .muxmask = pwm3_muxmask, +}; + +static const unsigned pwm3_pins[] = { 7 }; + +static const struct sirfsoc_muxmask warm_rst_muxmask[] = { + { + .group = 0, + .mask = BIT(8), + }, +}; + +static const struct sirfsoc_padmux warm_rst_padmux = { + .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), + .muxmask = warm_rst_muxmask, +}; + +static const unsigned warm_rst_pins[] = { 8 }; + +static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = { + { + .group = 1, + .mask = BIT(22), + }, +}; +static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = { + .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask), + .muxmask = usb0_utmi_drvbus_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(6), + .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */ +}; + +static const unsigned usb0_utmi_drvbus_pins[] = { 54 }; + +static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { + { + .group = 1, + .mask = BIT(27), + }, +}; + +static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { + .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), + .muxmask = usb1_utmi_drvbus_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, + .funcmask = BIT(11), + .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ +}; + +static const unsigned usb1_utmi_drvbus_pins[] = { 59 }; + +static const struct sirfsoc_padmux usb1_dp_dn_padmux = { + .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, + .funcmask = BIT(2), + .funcval = BIT(2), +}; + +static const unsigned usb1_dp_dn_pins[] = { 115, 116 }; + +static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = { + .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, + .funcmask = BIT(2), + .funcval = 0, +}; + +static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 }; + +static const struct sirfsoc_muxmask pulse_count_muxmask[] = { + { + .group = 0, + .mask = BIT(9) | BIT(10) | BIT(11), + }, +}; + +static const struct sirfsoc_padmux pulse_count_padmux = { + .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask), + .muxmask = pulse_count_muxmask, +}; + +static const unsigned pulse_count_pins[] = { 9, 10, 11 }; + +static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { + SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), + SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), + SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), + SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), + SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), + SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), + SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), + SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), + SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp", + usp0_uart_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins), + SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins), + SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), + SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp", + usp1_uart_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("usp2grp", usp2_pins), + SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp", + usp2_uart_nostreamctrl_pins), + SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), + SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), + SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), + SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins), + SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins), + SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins), + SIRFSOC_PIN_GROUP("vipgrp", vip_pins), + SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins), + SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), + SIRFSOC_PIN_GROUP("cko0grp", cko0_pins), + SIRFSOC_PIN_GROUP("cko1grp", cko1_pins), + SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), + SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), + SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), + SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins), + SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins), + SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), + SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins), + SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), + SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), + SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), + SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), + SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), + SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), + SIRFSOC_PIN_GROUP("nandgrp", nand_pins), + SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), + SIRFSOC_PIN_GROUP("spi1grp", spi1_pins), + SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), +}; + +static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; +static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; +static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; +static const char * const lcdromgrp[] = { "lcdromgrp" }; +static const char * const uart0grp[] = { "uart0grp" }; +static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" }; +static const char * const uart1grp[] = { "uart1grp" }; +static const char * const uart2grp[] = { "uart2grp" }; +static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; +static const char * const usp0grp[] = { "usp0grp" }; +static const char * const usp0_uart_nostreamctrl_grp[] = + { "usp0_uart_nostreamctrl_grp" }; +static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; +static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; +static const char * const usp1grp[] = { "usp1grp" }; +static const char * const usp1_uart_nostreamctrl_grp[] = + { "usp1_uart_nostreamctrl_grp" }; +static const char * const usp2grp[] = { "usp2grp" }; +static const char * const usp2_uart_nostreamctrl_grp[] = + { "usp2_uart_nostreamctrl_grp" }; +static const char * const i2c0grp[] = { "i2c0grp" }; +static const char * const i2c1grp[] = { "i2c1grp" }; +static const char * const pwm0grp[] = { "pwm0grp" }; +static const char * const pwm1grp[] = { "pwm1grp" }; +static const char * const pwm2grp[] = { "pwm2grp" }; +static const char * const pwm3grp[] = { "pwm3grp" }; +static const char * const vipgrp[] = { "vipgrp" }; +static const char * const vipromgrp[] = { "vipromgrp" }; +static const char * const warm_rstgrp[] = { "warm_rstgrp" }; +static const char * const cko0grp[] = { "cko0grp" }; +static const char * const cko1grp[] = { "cko1grp" }; +static const char * const sdmmc0grp[] = { "sdmmc0grp" }; +static const char * const sdmmc1grp[] = { "sdmmc1grp" }; +static const char * const sdmmc2grp[] = { "sdmmc2grp" }; +static const char * const sdmmc3grp[] = { "sdmmc3grp" }; +static const char * const sdmmc4grp[] = { "sdmmc4grp" }; +static const char * const sdmmc5grp[] = { "sdmmc5grp" }; +static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; +static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; +static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; +static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; +static const char * const pulse_countgrp[] = { "pulse_countgrp" }; +static const char * const i2sgrp[] = { "i2sgrp" }; +static const char * const ac97grp[] = { "ac97grp" }; +static const char * const nandgrp[] = { "nandgrp" }; +static const char * const spi0grp[] = { "spi0grp" }; +static const char * const spi1grp[] = { "spi1grp" }; +static const char * const gpsgrp[] = { "gpsgrp" }; + +static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { + SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), + SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), + SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), + SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), + SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), + SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), + SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), + SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), + SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", + usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux), + SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux), + SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), + SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", + usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux), + SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl", + usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux), + SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), + SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), + SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), + SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux), + SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux), + SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux), + SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux), + SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux), + SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux), + SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux), + SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux), + SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), + SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), + SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), + SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), + SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), + SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), + SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), + SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), + SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux), + SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), +}; + +struct sirfsoc_pinctrl_data prima2_pinctrl_data = { + (struct pinctrl_pin_desc *)sirfsoc_pads, + ARRAY_SIZE(sirfsoc_pads), + (struct sirfsoc_pin_group *)sirfsoc_pin_groups, + ARRAY_SIZE(sirfsoc_pin_groups), + (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions, + ARRAY_SIZE(sirfsoc_pmx_functions), +}; + diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c new file mode 100644 index 00000000000..014f5b1fee5 --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -0,0 +1,915 @@ +/* + * pinmux driver for CSR SiRFprimaII + * + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/bitops.h> +#include <linux/gpio.h> +#include <linux/of_gpio.h> + +#include "pinctrl-sirf.h" + +#define DRIVER_NAME "pinmux-sirf" + +struct sirfsoc_gpio_bank { + int id; + int parent_irq; + spinlock_t lock; +}; + +struct sirfsoc_gpio_chip { + struct of_mm_gpio_chip chip; + bool is_marco; /* for marco, some registers are different with prima2 */ + struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; +}; + +static DEFINE_SPINLOCK(sgpio_lock); + +static struct sirfsoc_pin_group *sirfsoc_pin_groups; +static int sirfsoc_pingrp_cnt; + +static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) +{ + return sirfsoc_pingrp_cnt; +} + +static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return sirfsoc_pin_groups[selector].name; +} + +static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + *pins = sirfsoc_pin_groups[selector].pins; + *num_pins = sirfsoc_pin_groups[selector].num_pins; + return 0; +} + +static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); + struct device_node *np; + struct property *prop; + const char *function, *group; + int ret, index = 0, count = 0; + + /* calculate number of maps required */ + for_each_child_of_node(np_config, np) { + ret = of_property_read_string(np, "sirf,function", &function); + if (ret < 0) + return ret; + + ret = of_property_count_strings(np, "sirf,pins"); + if (ret < 0) + return ret; + + count += ret; + } + + if (!count) { + dev_err(spmx->dev, "No child nodes passed via DT\n"); + return -ENODEV; + } + + *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); + if (!*map) + return -ENOMEM; + + for_each_child_of_node(np_config, np) { + of_property_read_string(np, "sirf,function", &function); + of_property_for_each_string(np, "sirf,pins", prop, group) { + (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[index].data.mux.group = group; + (*map)[index].data.mux.function = function; + index++; + } + } + + *num_maps = count; + + return 0; +} + +static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned num_maps) +{ + kfree(map); +} + +static struct pinctrl_ops sirfsoc_pctrl_ops = { + .get_groups_count = sirfsoc_get_groups_count, + .get_group_name = sirfsoc_get_group_name, + .get_group_pins = sirfsoc_get_group_pins, + .pin_dbg_show = sirfsoc_pin_dbg_show, + .dt_node_to_map = sirfsoc_dt_node_to_map, + .dt_free_map = sirfsoc_dt_free_map, +}; + +static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; +static int sirfsoc_pmxfunc_cnt; + +static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, + bool enable) +{ + int i; + const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; + const struct sirfsoc_muxmask *mask = mux->muxmask; + + for (i = 0; i < mux->muxmask_counts; i++) { + u32 muxval; + if (!spmx->is_marco) { + muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); + if (enable) + muxval = muxval & ~mask[i].mask; + else + muxval = muxval | mask[i].mask; + writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); + } else { + if (enable) + writel(mask[i].mask, spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group)); + else + writel(mask[i].mask, spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(mask[i].group)); + } + } + + if (mux->funcmask && enable) { + u32 func_en_val; + + func_en_val = + readl(spmx->rsc_virtbase + mux->ctrlreg); + func_en_val = + (func_en_val & ~mux->funcmask) | (mux->funcval); + writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); + } +} + +static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, + unsigned group) +{ + struct sirfsoc_pmx *spmx; + + spmx = pinctrl_dev_get_drvdata(pmxdev); + sirfsoc_pinmux_endisable(spmx, selector, true); + + return 0; +} + +static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector, + unsigned group) +{ + struct sirfsoc_pmx *spmx; + + spmx = pinctrl_dev_get_drvdata(pmxdev); + sirfsoc_pinmux_endisable(spmx, selector, false); +} + +static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) +{ + return sirfsoc_pmxfunc_cnt; +} + +static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return sirfsoc_pmx_functions[selector].name; +} + +static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = sirfsoc_pmx_functions[selector].groups; + *num_groups = sirfsoc_pmx_functions[selector].num_groups; + return 0; +} + +static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, + struct pinctrl_gpio_range *range, unsigned offset) +{ + struct sirfsoc_pmx *spmx; + + int group = range->id; + + u32 muxval; + + spmx = pinctrl_dev_get_drvdata(pmxdev); + + if (!spmx->is_marco) { + muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); + muxval = muxval | (1 << (offset - range->pin_base)); + writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); + } else { + writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(group)); + } + + return 0; +} + +static struct pinmux_ops sirfsoc_pinmux_ops = { + .enable = sirfsoc_pinmux_enable, + .disable = sirfsoc_pinmux_disable, + .get_functions_count = sirfsoc_pinmux_get_funcs_count, + .get_function_name = sirfsoc_pinmux_get_func_name, + .get_function_groups = sirfsoc_pinmux_get_groups, + .gpio_request_enable = sirfsoc_pinmux_request_gpio, +}; + +static struct pinctrl_desc sirfsoc_pinmux_desc = { + .name = DRIVER_NAME, + .pctlops = &sirfsoc_pctrl_ops, + .pmxops = &sirfsoc_pinmux_ops, + .owner = THIS_MODULE, +}; + +static void __iomem *sirfsoc_rsc_of_iomap(void) +{ + const struct of_device_id rsc_ids[] = { + { .compatible = "sirf,prima2-rsc" }, + { .compatible = "sirf,marco-rsc" }, + {} + }; + struct device_node *np; + + np = of_find_matching_node(NULL, rsc_ids); + if (!np) + panic("unable to find compatible rsc node in dtb\n"); + + return of_iomap(np, 0); +} + +static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, + u32 *flags) +{ + if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[1]; + + return gpiospec->args[0]; +} + +static const struct of_device_id pinmux_ids[] = { + { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, + { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, + { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, }, + {} +}; + +static int sirfsoc_pinmux_probe(struct platform_device *pdev) +{ + int ret; + struct sirfsoc_pmx *spmx; + struct device_node *np = pdev->dev.of_node; + const struct sirfsoc_pinctrl_data *pdata; + + /* Create state holders etc for this driver */ + spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); + if (!spmx) + return -ENOMEM; + + spmx->dev = &pdev->dev; + + platform_set_drvdata(pdev, spmx); + + spmx->gpio_virtbase = of_iomap(np, 0); + if (!spmx->gpio_virtbase) { + dev_err(&pdev->dev, "can't map gpio registers\n"); + return -ENOMEM; + } + + spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); + if (!spmx->rsc_virtbase) { + ret = -ENOMEM; + dev_err(&pdev->dev, "can't map rsc registers\n"); + goto out_no_rsc_remap; + } + + if (of_device_is_compatible(np, "sirf,marco-pinctrl")) + spmx->is_marco = 1; + + pdata = of_match_node(pinmux_ids, np)->data; + sirfsoc_pin_groups = pdata->grps; + sirfsoc_pingrp_cnt = pdata->grps_cnt; + sirfsoc_pmx_functions = pdata->funcs; + sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; + sirfsoc_pinmux_desc.pins = pdata->pads; + sirfsoc_pinmux_desc.npins = pdata->pads_cnt; + + + /* Now register the pin controller and all pins it handles */ + spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); + if (!spmx->pmx) { + dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); + ret = -EINVAL; + goto out_no_pmx; + } + + dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); + + return 0; + +out_no_pmx: + iounmap(spmx->rsc_virtbase); +out_no_rsc_remap: + iounmap(spmx->gpio_virtbase); + return ret; +} + +#ifdef CONFIG_PM_SLEEP +static int sirfsoc_pinmux_suspend_noirq(struct device *dev) +{ + int i, j; + struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { + spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_CTRL(i, j)); + } + spmx->ints_regs[i] = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_INT_STATUS(i)); + spmx->paden_regs[i] = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(i)); + } + spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); + + for (i = 0; i < 3; i++) + spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); + + return 0; +} + +static int sirfsoc_pinmux_resume_noirq(struct device *dev) +{ + int i, j; + struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { + writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + + SIRFSOC_GPIO_CTRL(i, j)); + } + writel(spmx->ints_regs[i], spmx->gpio_virtbase + + SIRFSOC_GPIO_INT_STATUS(i)); + writel(spmx->paden_regs[i], spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(i)); + } + writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); + + for (i = 0; i < 3; i++) + writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); + + return 0; +} + +static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = { + .suspend_noirq = sirfsoc_pinmux_suspend_noirq, + .resume_noirq = sirfsoc_pinmux_resume_noirq, + .freeze_noirq = sirfsoc_pinmux_suspend_noirq, + .restore_noirq = sirfsoc_pinmux_resume_noirq, +}; +#endif + +static struct platform_driver sirfsoc_pinmux_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = pinmux_ids, +#ifdef CONFIG_PM_SLEEP + .pm = &sirfsoc_pinmux_pm_ops, +#endif + }, + .probe = sirfsoc_pinmux_probe, +}; + +static int __init sirfsoc_pinmux_init(void) +{ + return platform_driver_register(&sirfsoc_pinmux_driver); +} +arch_initcall(sirfsoc_pinmux_init); + +static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct sirfsoc_gpio_chip, chip.gc); +} + +static inline struct sirfsoc_gpio_bank * +sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset) +{ + return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE]; +} + +static inline int sirfsoc_gpio_to_bankoff(unsigned int offset) +{ + return offset % SIRFSOC_GPIO_BANK_SIZE; +} + +static void sirfsoc_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); + int idx = sirfsoc_gpio_to_bankoff(d->hwirq); + u32 val, offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + val = readl(sgpio->chip.regs + offset); + + writel(val, sgpio->chip.regs + offset); + + spin_unlock_irqrestore(&sgpio_lock, flags); +} + +static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, + struct sirfsoc_gpio_bank *bank, + int idx) +{ + u32 val, offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + val = readl(sgpio->chip.regs + offset); + val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; + val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; + writel(val, sgpio->chip.regs + offset); + + spin_unlock_irqrestore(&sgpio_lock, flags); +} + +static void sirfsoc_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); + + __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); +} + +static void sirfsoc_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); + int idx = sirfsoc_gpio_to_bankoff(d->hwirq); + u32 val, offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + val = readl(sgpio->chip.regs + offset); + val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; + val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; + writel(val, sgpio->chip.regs + offset); + + spin_unlock_irqrestore(&sgpio_lock, flags); +} + +static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); + int idx = sirfsoc_gpio_to_bankoff(d->hwirq); + u32 val, offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + val = readl(sgpio->chip.regs + offset); + val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); + + switch (type) { + case IRQ_TYPE_NONE: + break; + case IRQ_TYPE_EDGE_RISING: + val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; + val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; + break; + case IRQ_TYPE_EDGE_FALLING: + val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; + val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; + break; + case IRQ_TYPE_EDGE_BOTH: + val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | + SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; + break; + case IRQ_TYPE_LEVEL_LOW: + val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); + val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; + val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); + break; + } + + writel(val, sgpio->chip.regs + offset); + + spin_unlock_irqrestore(&sgpio_lock, flags); + + return 0; +} + +static struct irq_chip sirfsoc_irq_chip = { + .name = "sirf-gpio-irq", + .irq_ack = sirfsoc_gpio_irq_ack, + .irq_mask = sirfsoc_gpio_irq_mask, + .irq_unmask = sirfsoc_gpio_irq_unmask, + .irq_set_type = sirfsoc_gpio_irq_type, +}; + +static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); + struct sirfsoc_gpio_bank *bank; + u32 status, ctrl; + int idx = 0; + struct irq_chip *chip = irq_get_chip(irq); + int i; + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + bank = &sgpio->sgpio_bank[i]; + if (bank->parent_irq == irq) + break; + } + BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS); + + chained_irq_enter(chip, desc); + + status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); + if (!status) { + printk(KERN_WARNING + "%s: gpio id %d status %#x no interrupt is flaged\n", + __func__, bank->id, status); + handle_bad_irq(irq, desc); + return; + } + + while (status) { + ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); + + /* + * Here we must check whether the corresponding GPIO's interrupt + * has been enabled, otherwise just skip it + */ + if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { + pr_debug("%s: gpio id %d idx %d happens\n", + __func__, bank->id, idx); + generic_handle_irq(irq_find_mapping(gc->irqdomain, idx + + bank->id * SIRFSOC_GPIO_BANK_SIZE)); + } + + idx++; + status = status >> 1; + } + + chained_irq_exit(chip, desc); +} + +static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio, + unsigned ctrl_offset) +{ + u32 val; + + val = readl(sgpio->chip.regs + ctrl_offset); + val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; + writel(val, sgpio->chip.regs + ctrl_offset); +} + +static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); + unsigned long flags; + + if (pinctrl_request_gpio(chip->base + offset)) + return -ENODEV; + + spin_lock_irqsave(&bank->lock, flags); + + /* + * default status: + * set direction as input and mask irq + */ + sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); + __sirfsoc_gpio_irq_mask(sgpio, bank, offset); + + spin_unlock_irqrestore(&bank->lock, flags); + + return 0; +} + +static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); + unsigned long flags; + + spin_lock_irqsave(&bank->lock, flags); + + __sirfsoc_gpio_irq_mask(sgpio, bank, offset); + sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); + + spin_unlock_irqrestore(&bank->lock, flags); + + pinctrl_free_gpio(chip->base + offset); +} + +static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); + int idx = sirfsoc_gpio_to_bankoff(gpio); + unsigned long flags; + unsigned offset; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&bank->lock, flags); + + sirfsoc_gpio_set_input(sgpio, offset); + + spin_unlock_irqrestore(&bank->lock, flags); + + return 0; +} + +static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio, + struct sirfsoc_gpio_bank *bank, + unsigned offset, + int value) +{ + u32 out_ctrl; + unsigned long flags; + + spin_lock_irqsave(&bank->lock, flags); + + out_ctrl = readl(sgpio->chip.regs + offset); + if (value) + out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; + else + out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; + + out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; + out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; + writel(out_ctrl, sgpio->chip.regs + offset); + + spin_unlock_irqrestore(&bank->lock, flags); +} + +static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) +{ + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); + int idx = sirfsoc_gpio_to_bankoff(gpio); + u32 offset; + unsigned long flags; + + offset = SIRFSOC_GPIO_CTRL(bank->id, idx); + + spin_lock_irqsave(&sgpio_lock, flags); + + sirfsoc_gpio_set_output(sgpio, bank, offset, value); + + spin_unlock_irqrestore(&sgpio_lock, flags); + + return 0; +} + +static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&bank->lock, flags); + + val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); + + spin_unlock_irqrestore(&bank->lock, flags); + + return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); +} + +static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); + u32 ctrl; + unsigned long flags; + + spin_lock_irqsave(&bank->lock, flags); + + ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); + if (value) + ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; + else + ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; + writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); + + spin_unlock_irqrestore(&bank->lock, flags); +} + +static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio, + const u32 *pullups) +{ + int i, n; + const unsigned long *p = (const unsigned long *)pullups; + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + for_each_set_bit(n, p + i, BITS_PER_LONG) { + u32 offset = SIRFSOC_GPIO_CTRL(i, n); + u32 val = readl(sgpio->chip.regs + offset); + val |= SIRFSOC_GPIO_CTL_PULL_MASK; + val |= SIRFSOC_GPIO_CTL_PULL_HIGH; + writel(val, sgpio->chip.regs + offset); + } + } +} + +static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio, + const u32 *pulldowns) +{ + int i, n; + const unsigned long *p = (const unsigned long *)pulldowns; + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + for_each_set_bit(n, p + i, BITS_PER_LONG) { + u32 offset = SIRFSOC_GPIO_CTRL(i, n); + u32 val = readl(sgpio->chip.regs + offset); + val |= SIRFSOC_GPIO_CTL_PULL_MASK; + val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; + writel(val, sgpio->chip.regs + offset); + } + } +} + +static int sirfsoc_gpio_probe(struct device_node *np) +{ + int i, err = 0; + static struct sirfsoc_gpio_chip *sgpio; + struct sirfsoc_gpio_bank *bank; + void __iomem *regs; + struct platform_device *pdev; + bool is_marco = false; + + u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; + + pdev = of_find_device_by_node(np); + if (!pdev) + return -ENODEV; + + sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); + if (!sgpio) + return -ENOMEM; + + regs = of_iomap(np, 0); + if (!regs) + return -ENOMEM; + + if (of_device_is_compatible(np, "sirf,marco-pinctrl")) + is_marco = 1; + + sgpio->chip.gc.request = sirfsoc_gpio_request; + sgpio->chip.gc.free = sirfsoc_gpio_free; + sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; + sgpio->chip.gc.get = sirfsoc_gpio_get_value; + sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output; + sgpio->chip.gc.set = sirfsoc_gpio_set_value; + sgpio->chip.gc.base = 0; + sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; + sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); + sgpio->chip.gc.of_node = np; + sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; + sgpio->chip.gc.of_gpio_n_cells = 2; + sgpio->chip.gc.dev = &pdev->dev; + sgpio->chip.regs = regs; + sgpio->is_marco = is_marco; + + err = gpiochip_add(&sgpio->chip.gc); + if (err) { + dev_err(&pdev->dev, "%s: error in probe function with status %d\n", + np->full_name, err); + goto out; + } + + err = gpiochip_irqchip_add(&sgpio->chip.gc, + &sirfsoc_irq_chip, + 0, handle_level_irq, + IRQ_TYPE_NONE); + if (err) { + dev_err(&pdev->dev, + "could not connect irqchip to gpiochip\n"); + goto out; + } + + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + bank = &sgpio->sgpio_bank[i]; + spin_lock_init(&bank->lock); + bank->parent_irq = platform_get_irq(pdev, i); + if (bank->parent_irq < 0) { + err = bank->parent_irq; + goto out_banks; + } + + gpiochip_set_chained_irqchip(&sgpio->chip.gc, + &sirfsoc_irq_chip, + bank->parent_irq, + sirfsoc_gpio_handle_irq); + } + + err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), + 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS); + if (err) { + dev_err(&pdev->dev, + "could not add gpiochip pin range\n"); + goto out_no_range; + } + + if (!of_property_read_u32_array(np, "sirf,pullups", pullups, + SIRFSOC_GPIO_NO_OF_BANKS)) + sirfsoc_gpio_set_pullup(sgpio, pullups); + + if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, + SIRFSOC_GPIO_NO_OF_BANKS)) + sirfsoc_gpio_set_pulldown(sgpio, pulldowns); + + return 0; + +out_no_range: +out_banks: + if (gpiochip_remove(&sgpio->chip.gc)) + dev_err(&pdev->dev, "could not remove gpio chip\n"); +out: + iounmap(regs); + return err; +} + +static int __init sirfsoc_gpio_init(void) +{ + + struct device_node *np; + + np = of_find_matching_node(NULL, pinmux_ids); + + if (!np) + return -ENODEV; + + return sirfsoc_gpio_probe(np); +} +subsys_initcall(sirfsoc_gpio_init); + +MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " + "Yuping Luo <yuping.luo@csr.com>, " + "Barry Song <baohua.song@csr.com>"); +MODULE_DESCRIPTION("SIRFSOC pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h new file mode 100644 index 00000000000..d7f16b499ad --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-sirf.h @@ -0,0 +1,118 @@ +/* + * pinmux driver shared headfile for CSR SiRFsoc + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#ifndef __PINMUX_SIRF_H__ +#define __PINMUX_SIRF_H__ + +#define SIRFSOC_NUM_PADS 622 +#define SIRFSOC_RSC_USB_UART_SHARE 0 +#define SIRFSOC_RSC_PIN_MUX 0x4 + +#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) +#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90) +#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4) +#define SIRFSOC_GPIO_DSP_EN0 (0x80) +#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C) + +#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1 +#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2 +#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4 +#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8 +#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10 +#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20 +#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40 +#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80 +#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100 +#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200 +#define SIRFSOC_GPIO_CTL_DSP_INT 0x400 + +#define SIRFSOC_GPIO_NO_OF_BANKS 5 +#define SIRFSOC_GPIO_BANK_SIZE 32 +#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index)) + +/** + * @dev: a pointer back to containing device + * @virtbase: the offset to the controller in virtual memory + */ +struct sirfsoc_pmx { + struct device *dev; + struct pinctrl_dev *pmx; + void __iomem *gpio_virtbase; + void __iomem *rsc_virtbase; + u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE]; + u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS]; + u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS]; + u32 dspen_regs; + u32 rsc_regs[3]; + bool is_marco; +}; + +/* SIRFSOC_GPIO_PAD_EN set */ +struct sirfsoc_muxmask { + unsigned long group; + unsigned long mask; +}; + +struct sirfsoc_padmux { + unsigned long muxmask_counts; + const struct sirfsoc_muxmask *muxmask; + /* RSC_PIN_MUX set */ + unsigned long ctrlreg; + unsigned long funcmask; + unsigned long funcval; +}; + + /** + * struct sirfsoc_pin_group - describes a SiRFprimaII pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + */ +struct sirfsoc_pin_group { + const char *name; + const unsigned int *pins; + const unsigned num_pins; +}; + +#define SIRFSOC_PIN_GROUP(n, p) \ + { \ + .name = n, \ + .pins = p, \ + .num_pins = ARRAY_SIZE(p), \ + } + +struct sirfsoc_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; + const struct sirfsoc_padmux *padmux; +}; + +#define SIRFSOC_PMX_FUNCTION(n, g, m) \ + { \ + .name = n, \ + .groups = g, \ + .num_groups = ARRAY_SIZE(g), \ + .padmux = &m, \ + } + +struct sirfsoc_pinctrl_data { + struct pinctrl_pin_desc *pads; + int pads_cnt; + struct sirfsoc_pin_group *grps; + int grps_cnt; + struct sirfsoc_pmx_func *funcs; + int funcs_cnt; +}; + +extern struct sirfsoc_pinctrl_data prima2_pinctrl_data; +extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data; + +#endif diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 295b349a05c..ff2940e9f2a 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -15,12 +15,12 @@ #include <linux/io.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/module.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/spinlock.h> -#include <asm/mach/irq.h> #define MAX_GPIO_PER_REG 32 #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) @@ -75,7 +75,7 @@ struct plgpio { int (*o2p)(int offset); /* offset_to_pin */ u32 p2o_regs; struct plgpio_regs regs; -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP struct plgpio_regs *csave_regs; #endif }; @@ -441,7 +441,7 @@ static int spear310_p2o(int pin) return offset; } -int spear310_o2p(int offset) +static int spear310_o2p(int offset) { if (offset <= 3) return 101 - offset; @@ -528,18 +528,13 @@ static int plgpio_probe(struct platform_device *pdev) struct resource *res; int ret, irq, i; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n"); - return -EBUSY; - } - plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); if (!plgpio) { dev_err(&pdev->dev, "memory allocation fail\n"); return -ENOMEM; } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); plgpio->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(plgpio->base)) return PTR_ERR(plgpio->base); @@ -554,7 +549,7 @@ static int plgpio_probe(struct platform_device *pdev) if (IS_ERR(plgpio->clk)) dev_warn(&pdev->dev, "clk_get() failed, work without it\n"); -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP plgpio->csave_regs = devm_kzalloc(&pdev->dev, sizeof(*plgpio->csave_regs) * DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG), @@ -641,7 +636,7 @@ unprepare_clk: return ret; } -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int plgpio_suspend(struct device *dev) { struct plgpio *plgpio = dev_get_drvdata(dev); @@ -740,7 +735,7 @@ static struct platform_driver plgpio_driver = { .owner = THIS_MODULE, .name = "spear-plgpio", .pm = &plgpio_dev_pm_ops, - .of_match_table = of_match_ptr(plgpio_of_match), + .of_match_table = plgpio_of_match, }, }; diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index 116da0412c4..58bf6867aa1 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -367,21 +367,16 @@ int spear_pinctrl_probe(struct platform_device *pdev, if (!machdata) return -ENODEV; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; - pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); if (!pmx) { dev_err(&pdev->dev, "Can't alloc spear_pmx\n"); return -ENOMEM; } - pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (!pmx->vbase) { - dev_err(&pdev->dev, "Couldn't ioremap at index 0\n"); - return -ENODEV; - } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pmx->vbase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmx->vbase)) + return PTR_ERR(pmx->vbase); pmx->dev = &pdev->dev; pmx->machdata = machdata; diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c index 06c7e6f1c7f..ed1d3608f48 100644 --- a/drivers/pinctrl/spear/pinctrl-spear310.c +++ b/drivers/pinctrl/spear/pinctrl-spear310.c @@ -430,4 +430,4 @@ module_exit(spear310_pinctrl_exit); MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match); +MODULE_DEVICE_TABLE(of, spear310_pinctrl_of_match); diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig new file mode 100644 index 00000000000..73e0a305ea1 --- /dev/null +++ b/drivers/pinctrl/sunxi/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SUNXI + +config PINCTRL_SUNXI + bool + +config PINCTRL_SUNXI_COMMON + bool + select PINMUX + select GENERIC_PINCONF + +config PINCTRL_SUN4I_A10 + def_bool PINCTRL_SUNXI || MACH_SUN4I + select PINCTRL_SUNXI_COMMON + +config PINCTRL_SUN5I_A10S + def_bool PINCTRL_SUNXI || MACH_SUN5I + select PINCTRL_SUNXI_COMMON + +config PINCTRL_SUN5I_A13 + def_bool PINCTRL_SUNXI || MACH_SUN5I + select PINCTRL_SUNXI_COMMON + +config PINCTRL_SUN6I_A31 + def_bool PINCTRL_SUNXI || MACH_SUN6I + select PINCTRL_SUNXI_COMMON + +config PINCTRL_SUN6I_A31_R + def_bool PINCTRL_SUNXI || MACH_SUN6I + depends on RESET_CONTROLLER + select PINCTRL_SUNXI_COMMON + +config PINCTRL_SUN7I_A20 + def_bool PINCTRL_SUNXI || MACH_SUN7I + select PINCTRL_SUNXI_COMMON + +endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile new file mode 100644 index 00000000000..0f4461cbe11 --- /dev/null +++ b/drivers/pinctrl/sunxi/Makefile @@ -0,0 +1,10 @@ +# Core +obj-$(CONFIG_PINCTRL_SUNXI_COMMON) += pinctrl-sunxi.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o +obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o +obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o +obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o +obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o +obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c new file mode 100644 index 00000000000..fa1ff7c7e35 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -0,0 +1,1039 @@ +/* + * Allwinner A10 SoCs pinctrl driver. + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun4i_a10_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x4, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ + SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x4, "uart2")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ + SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ + SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ + SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ + SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ + SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ + SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ + SUNXI_FUNCTION(0x3, "uart6"), /* TX */ + SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ + SUNXI_FUNCTION(0x3, "uart6"), /* RX */ + SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ + SUNXI_FUNCTION(0x3, "uart7"), /* TX */ + SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ + SUNXI_FUNCTION(0x3, "uart7"), /* RX */ + SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ + SUNXI_FUNCTION(0x3, "can"), /* TX */ + SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ + SUNXI_FUNCTION(0x3, "can"), /* RX */ + SUNXI_FUNCTION(0x4, "uart1")), /* RING */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ + SUNXI_FUNCTION(0x3, "ac97")), /* DO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DI */ + SUNXI_FUNCTION(0x3, "ac97")), /* DI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION(0x3, "ir1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "ir1")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ + SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ + SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "sim")), /* DET */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "sim")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "sim")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "sim")), /* SDA */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi0")), /* CK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ + SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi1"), /* CK */ + SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ + SUNXI_FUNCTION(0x4, "uart5"), /* TX */ + SUNXI_FUNCTION(0x5, "ms"), /* BS */ + SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ + SUNXI_FUNCTION(0x4, "uart5"), /* RX */ + SUNXI_FUNCTION(0x5, "ms"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ + SUNXI_FUNCTION(0x5, "ms"), /* D0 */ + SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ + SUNXI_FUNCTION(0x5, "ms"), /* D1 */ + SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ + SUNXI_FUNCTION(0x5, "ms"), /* D2 */ + SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ + SUNXI_FUNCTION(0x5, "ms"), /* D3 */ + SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ + SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ + SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ + SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ + SUNXI_FUNCTION(0x5, "sim"), /* RST */ + SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ + SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ + SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ + SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ + SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ + SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ + SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ + SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ + SUNXI_FUNCTION(0x5, "sim"), /* SCK */ + SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ + SUNXI_FUNCTION(0x5, "sim"), /* SDA */ + SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ + SUNXI_FUNCTION(0x4, "can"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ + SUNXI_FUNCTION(0x4, "can"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ + SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ + SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ + SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ + SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart5"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart5"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart6"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart6"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ + SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ + SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ + SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ + SUNXI_FUNCTION(0x3, "uart7"), /* TX */ + SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ + SUNXI_FUNCTION(0x3, "uart7"), /* RX */ + SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ +}; + +static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { + .pins = sun4i_a10_pins, + .npins = ARRAY_SIZE(sun4i_a10_pins), +}; + +static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun4i_a10_pinctrl_data); +} + +static struct of_device_id sun4i_a10_pinctrl_match[] = { + { .compatible = "allwinner,sun4i-a10-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun4i_a10_pinctrl_match); + +static struct platform_driver sun4i_a10_pinctrl_driver = { + .probe = sun4i_a10_pinctrl_probe, + .driver = { + .name = "sun4i-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun4i_a10_pinctrl_match, + }, +}; +module_platform_driver(sun4i_a10_pinctrl_driver); + +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); +MODULE_DESCRIPTION("Allwinner A10 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c new file mode 100644 index 00000000000..164d743f526 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c @@ -0,0 +1,690 @@ +/* + * Allwinner A10s SoCs pinctrl driver. + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun5i_a10s_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ + SUNXI_FUNCTION(0x3, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ + SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ + SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ + SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ + SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ + SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ + SUNXI_FUNCTION(0x3, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RING */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ + SUNXI_FUNCTION(0x3, "uart1"), /* TX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ + SUNXI_FUNCTION(0x3, "uart1"), /* RX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ + SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ + SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ + SUNXI_FUNCTION(0x3, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */ + SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ + SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ + SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DO */ + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DI */ + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWP */ + SUNXI_FUNCTION(0x4, "uart3")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */ + SUNXI_FUNCTION(0x4, "uart3")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION(0x4, "uart3")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart2")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "emac")), /* ECRS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "emac")), /* ECOL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "emac")), /* EMDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi0"), /* PCK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ + SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi0"), /* CK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* SIGN */ + SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* MAG */ + SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* DO */ + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x5, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x5, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x5, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */ + SUNXI_FUNCTION(0x5, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ +}; + +static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = { + .pins = sun5i_a10s_pins, + .npins = ARRAY_SIZE(sun5i_a10s_pins), +}; + +static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun5i_a10s_pinctrl_data); +} + +static struct of_device_id sun5i_a10s_pinctrl_match[] = { + { .compatible = "allwinner,sun5i-a10s-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun5i_a10s_pinctrl_match); + +static struct platform_driver sun5i_a10s_pinctrl_driver = { + .probe = sun5i_a10s_pinctrl_probe, + .driver = { + .name = "sun5i-a10s-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun5i_a10s_pinctrl_match, + }, +}; +module_platform_driver(sun5i_a10s_pinctrl_driver); + +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); +MODULE_DESCRIPTION("Allwinner A10s pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c new file mode 100644 index 00000000000..1188a2b7b98 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c @@ -0,0 +1,411 @@ +/* + * Allwinner A13 SoCs pinctrl driver. + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun5i_a13_pins[] = { + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm"), + SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ + SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ + SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ +}; + +static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { + .pins = sun5i_a13_pins, + .npins = ARRAY_SIZE(sun5i_a13_pins), +}; + +static int sun5i_a13_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun5i_a13_pinctrl_data); +} + +static struct of_device_id sun5i_a13_pinctrl_match[] = { + { .compatible = "allwinner,sun5i-a13-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun5i_a13_pinctrl_match); + +static struct platform_driver sun5i_a13_pinctrl_driver = { + .probe = sun5i_a13_pinctrl_probe, + .driver = { + .name = "sun5i-a13-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun5i_a13_pinctrl_match, + }, +}; +module_platform_driver(sun5i_a13_pinctrl_driver); + +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); +MODULE_DESCRIPTION("Allwinner A13 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c new file mode 100644 index 00000000000..8fcba48e0a4 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c @@ -0,0 +1,141 @@ +/* + * Allwinner A31 SoCs special pins pinctrl driver. + * + * Copyright (C) 2014 Boris Brezillon + * Boris Brezillon <boris.brezillon@free-electrons.com> + * + * Copyright (C) 2014 Maxime Ripard + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/reset.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun6i_a31_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */ + SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */ + SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_ir")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "1wire")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */ +}; + +static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = { + .pins = sun6i_a31_r_pins, + .npins = ARRAY_SIZE(sun6i_a31_r_pins), + .pin_base = PL_BASE, +}; + +static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev) +{ + struct reset_control *rstc; + int ret; + + rstc = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(rstc)) { + dev_err(&pdev->dev, "Reset controller missing\n"); + return PTR_ERR(rstc); + } + + ret = reset_control_deassert(rstc); + if (ret) + return ret; + + ret = sunxi_pinctrl_init(pdev, + &sun6i_a31_r_pinctrl_data); + + if (ret) + reset_control_assert(rstc); + + return ret; +} + +static struct of_device_id sun6i_a31_r_pinctrl_match[] = { + { .compatible = "allwinner,sun6i-a31-r-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun6i_a31_r_pinctrl_match); + +static struct platform_driver sun6i_a31_r_pinctrl_driver = { + .probe = sun6i_a31_r_pinctrl_probe, + .driver = { + .name = "sun6i-a31-r-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun6i_a31_r_pinctrl_match, + }, +}; +module_platform_driver(sun6i_a31_r_pinctrl_driver); + +MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com"); +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); +MODULE_DESCRIPTION("Allwinner A31 R_PIO pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c new file mode 100644 index 00000000000..8dea5856458 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -0,0 +1,865 @@ +/* + * Allwinner A31 SoCs pinctrl driver. + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun6i_a31_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */ + SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */ + SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */ + SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RING */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */ + SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */ + SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */ + SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */ + SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */ + SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */ + SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */ + SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ + SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ + SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ + SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ + SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */ + SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */ + SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */ + SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */ + SUNXI_FUNCTION(0x4, "spi3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* COL */ + SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */ + SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* CRS */ + SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */ + SUNXI_FUNCTION(0x4, "spi3")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */ + SUNXI_FUNCTION(0x3, "lcd1"), /* DE */ + SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ + SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */ + SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ + SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s0")), /* DI */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ + SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */ + SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */ + SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */ + SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */ + SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */ + SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */ + SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */ + SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */ + SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */ + SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2"), /* RST */ + SUNXI_FUNCTION(0x4, "mmc3")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "ts")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ts")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "ts")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "ts")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "uart5")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "uart5")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "uart5")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart5")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "ts")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "ts")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "ts")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "ts")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D8 */ + SUNXI_FUNCTION(0x3, "ts")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D9 */ + SUNXI_FUNCTION(0x3, "ts")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D10 */ + SUNXI_FUNCTION(0x3, "ts")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D11 */ + SUNXI_FUNCTION(0x3, "ts")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ + SUNXI_FUNCTION(0x3, "usb")), /* DP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ + SUNXI_FUNCTION(0x3, "usb")), /* DM3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart4")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart4")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* WE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* ALE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* CLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* RE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* DQS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ + SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ + SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ + SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ + SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 29), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 30), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */ +}; + +static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = { + .pins = sun6i_a31_pins, + .npins = ARRAY_SIZE(sun6i_a31_pins), +}; + +static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun6i_a31_pinctrl_data); +} + +static struct of_device_id sun6i_a31_pinctrl_match[] = { + { .compatible = "allwinner,sun6i-a31-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun6i_a31_pinctrl_match); + +static struct platform_driver sun6i_a31_pinctrl_driver = { + .probe = sun6i_a31_pinctrl_probe, + .driver = { + .name = "sun6i-a31-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun6i_a31_pinctrl_match, + }, +}; +module_platform_driver(sun6i_a31_pinctrl_driver); + +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); +MODULE_DESCRIPTION("Allwinner A31 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c new file mode 100644 index 00000000000..d8577ce5f1a --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c @@ -0,0 +1,1065 @@ +/* + * Allwinner A20 SoCs pinctrl driver. + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun7i_a20_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x4, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x4, "uart2"), /* TX */ + SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ + SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x4, "uart2"), /* RX */ + SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ + SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */ + SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ + SUNXI_FUNCTION(0x3, "spi3"), /* CLK */ + SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ + SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */ + SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ + SUNXI_FUNCTION(0x3, "spi3"), /* MISO */ + SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ + SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */ + SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */ + SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ + SUNXI_FUNCTION(0x3, "uart6"), /* TX */ + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ + SUNXI_FUNCTION(0x3, "uart6"), /* RX */ + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ + SUNXI_FUNCTION(0x3, "uart7"), /* TX */ + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ + SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */ + SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ + SUNXI_FUNCTION(0x3, "uart7"), /* RX */ + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ + SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */ + SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ + SUNXI_FUNCTION(0x3, "can"), /* TX */ + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ + SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */ + SUNXI_FUNCTION(0x6, "i2s1")), /* DO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ + SUNXI_FUNCTION(0x3, "can"), /* RX */ + SUNXI_FUNCTION(0x4, "uart1"), /* RING */ + SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */ + SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* TX */ + SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ + SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ + SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */ + SUNXI_FUNCTION(0x3, "ac97")), /* DO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DI */ + SUNXI_FUNCTION(0x3, "ac97"), /* DI */ + SUNXI_FUNCTION(0x4, "spdif")), /* DI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ + SUNXI_FUNCTION(0x4, "spdif")), /* DO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION(0x3, "ir1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "ir1")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ + SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */ + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ + SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ + SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ + SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ + SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ + SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "sim")), /* DET */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "sim")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "sim")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "sim")), /* SDA */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi0")), /* CK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ + SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi1"), /* CK */ + SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart5"), /* TX */ + SUNXI_FUNCTION(0x5, "ms"), /* BS */ + SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart5"), /* RX */ + SUNXI_FUNCTION(0x5, "ms"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ + SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ + SUNXI_FUNCTION(0x5, "ms"), /* D0 */ + SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ + SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ + SUNXI_FUNCTION(0x5, "ms"), /* D1 */ + SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ + SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ + SUNXI_FUNCTION(0x5, "ms"), /* D2 */ + SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ + SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ + SUNXI_FUNCTION(0x5, "ms"), /* D3 */ + SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ + SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ + SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ + SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ + SUNXI_FUNCTION(0x5, "sim"), /* RST */ + SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ + SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ + SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ + SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ + SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ + SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ + SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ + SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ + SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ + SUNXI_FUNCTION(0x3, "emac"), /* ETXD1 */ + SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ + SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ + SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ + SUNXI_FUNCTION(0x3, "emac"), /* ETXD0 */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ + SUNXI_FUNCTION(0x5, "sim"), /* SCK */ + SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ + SUNXI_FUNCTION(0x3, "emac"), /* ERXERR */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ + SUNXI_FUNCTION(0x5, "sim"), /* SDA */ + SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ + SUNXI_FUNCTION(0x3, "emac"), /* ERXDV */ + SUNXI_FUNCTION(0x4, "can"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ + SUNXI_FUNCTION(0x3, "emac"), /* EMDC */ + SUNXI_FUNCTION(0x4, "can"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */ + SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ + SUNXI_FUNCTION(0x3, "emac"), /* EMDIO */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ + SUNXI_FUNCTION(0x3, "emac"), /* ETXEN */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ + SUNXI_FUNCTION(0x3, "emac"), /* ETXCK */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ + SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ + SUNXI_FUNCTION(0x3, "emac"), /* ECRS */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ + SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "emac"), /* ECOL */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "emac"), /* ETXERR */ + SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ + SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */ + SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart5"), /* TX */ + SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart5"), /* RX */ + SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart6"), /* TX */ + SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */ + SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart6"), /* RX */ + SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */ + SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ + SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ + SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ + SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ + SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ + SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ + SUNXI_FUNCTION(0x3, "uart7"), /* TX */ + SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ + SUNXI_FUNCTION(0x3, "uart7"), /* RX */ + SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ +}; + +static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = { + .pins = sun7i_a20_pins, + .npins = ARRAY_SIZE(sun7i_a20_pins), +}; + +static int sun7i_a20_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun7i_a20_pinctrl_data); +} + +static struct of_device_id sun7i_a20_pinctrl_match[] = { + { .compatible = "allwinner,sun7i-a20-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun7i_a20_pinctrl_match); + +static struct platform_driver sun7i_a20_pinctrl_driver = { + .probe = sun7i_a20_pinctrl_probe, + .driver = { + .name = "sun7i-a20-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun7i_a20_pinctrl_match, + }, +}; +module_platform_driver(sun7i_a20_pinctrl_driver); + +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); +MODULE_DESCRIPTION("Allwinner A20 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c new file mode 100644 index 00000000000..5f38c7f6783 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -0,0 +1,925 @@ +/* + * Allwinner A1X SoCs pinctrl driver. + * + * Copyright (C) 2012 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "../core.h" +#include "pinctrl-sunxi.h" + +static struct sunxi_pinctrl_group * +sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) +{ + int i; + + for (i = 0; i < pctl->ngroups; i++) { + struct sunxi_pinctrl_group *grp = pctl->groups + i; + + if (!strcmp(grp->name, group)) + return grp; + } + + return NULL; +} + +static struct sunxi_pinctrl_function * +sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, + const char *name) +{ + struct sunxi_pinctrl_function *func = pctl->functions; + int i; + + for (i = 0; i < pctl->nfunctions; i++) { + if (!func[i].name) + break; + + if (!strcmp(func[i].name, name)) + return func + i; + } + + return NULL; +} + +static struct sunxi_desc_function * +sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, + const char *pin_name, + const char *func_name) +{ + int i; + + for (i = 0; i < pctl->desc->npins; i++) { + const struct sunxi_desc_pin *pin = pctl->desc->pins + i; + + if (!strcmp(pin->pin.name, pin_name)) { + struct sunxi_desc_function *func = pin->functions; + + while (func->name) { + if (!strcmp(func->name, func_name)) + return func; + + func++; + } + } + } + + return NULL; +} + +static struct sunxi_desc_function * +sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, + const u16 pin_num, + const char *func_name) +{ + int i; + + for (i = 0; i < pctl->desc->npins; i++) { + const struct sunxi_desc_pin *pin = pctl->desc->pins + i; + + if (pin->pin.number == pin_num) { + struct sunxi_desc_function *func = pin->functions; + + while (func->name) { + if (!strcmp(func->name, func_name)) + return func; + + func++; + } + } + } + + return NULL; +} + +static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->ngroups; +} + +static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->groups[group].name; +} + +static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned *)&pctl->groups[group].pin; + *num_pins = 1; + + return 0; +} + +static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + unsigned long *pinconfig; + struct property *prop; + const char *function; + const char *group; + int ret, nmaps, i = 0; + u32 val; + + *map = NULL; + *num_maps = 0; + + ret = of_property_read_string(node, "allwinner,function", &function); + if (ret) { + dev_err(pctl->dev, + "missing allwinner,function property in node %s\n", + node->name); + return -EINVAL; + } + + nmaps = of_property_count_strings(node, "allwinner,pins") * 2; + if (nmaps < 0) { + dev_err(pctl->dev, + "missing allwinner,pins property in node %s\n", + node->name); + return -EINVAL; + } + + *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); + if (!*map) + return -ENOMEM; + + of_property_for_each_string(node, "allwinner,pins", prop, group) { + struct sunxi_pinctrl_group *grp = + sunxi_pinctrl_find_group_by_name(pctl, group); + int j = 0, configlen = 0; + + if (!grp) { + dev_err(pctl->dev, "unknown pin %s", group); + continue; + } + + if (!sunxi_pinctrl_desc_find_function_by_name(pctl, + grp->name, + function)) { + dev_err(pctl->dev, "unsupported function %s on pin %s", + function, group); + continue; + } + + (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[i].data.mux.group = group; + (*map)[i].data.mux.function = function; + + i++; + + (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; + (*map)[i].data.configs.group_or_pin = group; + + if (of_find_property(node, "allwinner,drive", NULL)) + configlen++; + if (of_find_property(node, "allwinner,pull", NULL)) + configlen++; + + pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); + if (!pinconfig) { + kfree(*map); + return -ENOMEM; + } + + if (!of_property_read_u32(node, "allwinner,drive", &val)) { + u16 strength = (val + 1) * 10; + pinconfig[j++] = + pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, + strength); + } + + if (!of_property_read_u32(node, "allwinner,pull", &val)) { + enum pin_config_param pull = PIN_CONFIG_END; + if (val == 1) + pull = PIN_CONFIG_BIAS_PULL_UP; + else if (val == 2) + pull = PIN_CONFIG_BIAS_PULL_DOWN; + pinconfig[j++] = pinconf_to_config_packed(pull, 0); + } + + (*map)[i].data.configs.configs = pinconfig; + (*map)[i].data.configs.num_configs = configlen; + + i++; + } + + *num_maps = nmaps; + + return 0; +} + +static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) { + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + } + + kfree(map); +} + +static const struct pinctrl_ops sunxi_pctrl_ops = { + .dt_node_to_map = sunxi_pctrl_dt_node_to_map, + .dt_free_map = sunxi_pctrl_dt_free_map, + .get_groups_count = sunxi_pctrl_get_groups_count, + .get_group_name = sunxi_pctrl_get_group_name, + .get_group_pins = sunxi_pctrl_get_group_pins, +}; + +static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *config = pctl->groups[group].config; + + return 0; +} + +static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *configs, + unsigned num_configs) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sunxi_pinctrl_group *g = &pctl->groups[group]; + unsigned long flags; + unsigned pin = g->pin - pctl->desc->pin_base; + u32 val, mask; + u16 strength; + u8 dlevel; + int i; + + spin_lock_irqsave(&pctl->lock, flags); + + for (i = 0; i < num_configs; i++) { + switch (pinconf_to_config_param(configs[i])) { + case PIN_CONFIG_DRIVE_STRENGTH: + strength = pinconf_to_config_argument(configs[i]); + if (strength > 40) { + spin_unlock_irqrestore(&pctl->lock, flags); + return -EINVAL; + } + /* + * We convert from mA to what the register expects: + * 0: 10mA + * 1: 20mA + * 2: 30mA + * 3: 40mA + */ + dlevel = strength / 10 - 1; + val = readl(pctl->membase + sunxi_dlevel_reg(pin)); + mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); + writel((val & ~mask) + | dlevel << sunxi_dlevel_offset(pin), + pctl->membase + sunxi_dlevel_reg(pin)); + break; + case PIN_CONFIG_BIAS_PULL_UP: + val = readl(pctl->membase + sunxi_pull_reg(pin)); + mask = PULL_PINS_MASK << sunxi_pull_offset(pin); + writel((val & ~mask) | 1 << sunxi_pull_offset(pin), + pctl->membase + sunxi_pull_reg(pin)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + val = readl(pctl->membase + sunxi_pull_reg(pin)); + mask = PULL_PINS_MASK << sunxi_pull_offset(pin); + writel((val & ~mask) | 2 << sunxi_pull_offset(pin), + pctl->membase + sunxi_pull_reg(pin)); + break; + default: + break; + } + /* cache the config value */ + g->config = configs[i]; + } /* for each config */ + + spin_unlock_irqrestore(&pctl->lock, flags); + + return 0; +} + +static const struct pinconf_ops sunxi_pconf_ops = { + .pin_config_group_get = sunxi_pconf_group_get, + .pin_config_group_set = sunxi_pconf_group_set, +}; + +static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->nfunctions; +} + +static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->functions[function].name; +} + +static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->functions[function].groups; + *num_groups = pctl->functions[function].ngroups; + + return 0; +} + +static void sunxi_pmx_set(struct pinctrl_dev *pctldev, + unsigned pin, + u8 config) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + u32 val, mask; + + spin_lock_irqsave(&pctl->lock, flags); + + pin -= pctl->desc->pin_base; + val = readl(pctl->membase + sunxi_mux_reg(pin)); + mask = MUX_PINS_MASK << sunxi_mux_offset(pin); + writel((val & ~mask) | config << sunxi_mux_offset(pin), + pctl->membase + sunxi_mux_reg(pin)); + + spin_unlock_irqrestore(&pctl->lock, flags); +} + +static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sunxi_pinctrl_group *g = pctl->groups + group; + struct sunxi_pinctrl_function *func = pctl->functions + function; + struct sunxi_desc_function *desc = + sunxi_pinctrl_desc_find_function_by_name(pctl, + g->name, + func->name); + + if (!desc) + return -EINVAL; + + sunxi_pmx_set(pctldev, g->pin, desc->muxval); + + return 0; +} + +static int +sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, + bool input) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sunxi_desc_function *desc; + const char *func; + + if (input) + func = "gpio_in"; + else + func = "gpio_out"; + + desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); + if (!desc) + return -EINVAL; + + sunxi_pmx_set(pctldev, offset, desc->muxval); + + return 0; +} + +static const struct pinmux_ops sunxi_pmx_ops = { + .get_functions_count = sunxi_pmx_get_funcs_cnt, + .get_function_name = sunxi_pmx_get_func_name, + .get_function_groups = sunxi_pmx_get_func_groups, + .enable = sunxi_pmx_enable, + .gpio_set_direction = sunxi_pmx_gpio_set_direction, +}; + +static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); + + u32 reg = sunxi_data_reg(offset); + u8 index = sunxi_data_offset(offset); + u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; + + return val; +} + +static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); + u32 reg = sunxi_data_reg(offset); + u8 index = sunxi_data_offset(offset); + unsigned long flags; + u32 regval; + + spin_lock_irqsave(&pctl->lock, flags); + + regval = readl(pctl->membase + reg); + + if (value) + regval |= BIT(index); + else + regval &= ~(BIT(index)); + + writel(regval, pctl->membase + reg); + + spin_unlock_irqrestore(&pctl->lock, flags); +} + +static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + sunxi_pinctrl_gpio_set(chip, offset, value); + return pinctrl_gpio_direction_output(chip->base + offset); +} + +static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, + u32 *flags) +{ + int pin, base; + + base = PINS_PER_BANK * gpiospec->args[0]; + pin = base + gpiospec->args[1]; + + if (pin > (gc->base + gc->ngpio)) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[2]; + + return pin; +} + +static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); + struct sunxi_desc_function *desc; + + if (offset >= chip->ngpio) + return -ENXIO; + + desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); + if (!desc) + return -EINVAL; + + dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", + chip->label, offset + chip->base, desc->irqnum); + + return irq_find_mapping(pctl->domain, desc->irqnum); +} + + +static int sunxi_pinctrl_irq_set_type(struct irq_data *d, + unsigned int type) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + u32 reg = sunxi_irq_cfg_reg(d->hwirq); + u8 index = sunxi_irq_cfg_offset(d->hwirq); + unsigned long flags; + u32 regval; + u8 mode; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + mode = IRQ_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + mode = IRQ_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + mode = IRQ_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + mode = IRQ_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + mode = IRQ_LEVEL_LOW; + break; + default: + return -EINVAL; + } + + spin_lock_irqsave(&pctl->lock, flags); + + regval = readl(pctl->membase + reg); + regval &= ~(IRQ_CFG_IRQ_MASK << index); + writel(regval | (mode << index), pctl->membase + reg); + + spin_unlock_irqrestore(&pctl->lock, flags); + + return 0; +} + +static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq); + u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq); + u32 status_reg = sunxi_irq_status_reg(d->hwirq); + u8 status_idx = sunxi_irq_status_offset(d->hwirq); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&pctl->lock, flags); + + /* Mask the IRQ */ + val = readl(pctl->membase + ctrl_reg); + writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg); + + /* Clear the IRQ */ + writel(1 << status_idx, pctl->membase + status_reg); + + spin_unlock_irqrestore(&pctl->lock, flags); +} + +static void sunxi_pinctrl_irq_mask(struct irq_data *d) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + u32 reg = sunxi_irq_ctrl_reg(d->hwirq); + u8 idx = sunxi_irq_ctrl_offset(d->hwirq); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&pctl->lock, flags); + + /* Mask the IRQ */ + val = readl(pctl->membase + reg); + writel(val & ~(1 << idx), pctl->membase + reg); + + spin_unlock_irqrestore(&pctl->lock, flags); +} + +static void sunxi_pinctrl_irq_unmask(struct irq_data *d) +{ + struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); + struct sunxi_desc_function *func; + u32 reg = sunxi_irq_ctrl_reg(d->hwirq); + u8 idx = sunxi_irq_ctrl_offset(d->hwirq); + unsigned long flags; + u32 val; + + func = sunxi_pinctrl_desc_find_function_by_pin(pctl, + pctl->irq_array[d->hwirq], + "irq"); + + /* Change muxing to INT mode */ + sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); + + spin_lock_irqsave(&pctl->lock, flags); + + /* Unmask the IRQ */ + val = readl(pctl->membase + reg); + writel(val | (1 << idx), pctl->membase + reg); + + spin_unlock_irqrestore(&pctl->lock, flags); +} + +static struct irq_chip sunxi_pinctrl_irq_chip = { + .irq_mask = sunxi_pinctrl_irq_mask, + .irq_mask_ack = sunxi_pinctrl_irq_mask_ack, + .irq_unmask = sunxi_pinctrl_irq_unmask, + .irq_set_type = sunxi_pinctrl_irq_set_type, +}; + +static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); + const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); + + /* Clear all interrupts */ + writel(reg, pctl->membase + IRQ_STATUS_REG); + + if (reg) { + int irqoffset; + + chained_irq_enter(chip, desc); + for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) { + int pin_irq = irq_find_mapping(pctl->domain, irqoffset); + generic_handle_irq(pin_irq); + } + chained_irq_exit(chip, desc); + } +} + +static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, + const char *name) +{ + struct sunxi_pinctrl_function *func = pctl->functions; + + while (func->name) { + /* function already there */ + if (strcmp(func->name, name) == 0) { + func->ngroups++; + return -EEXIST; + } + func++; + } + + func->name = name; + func->ngroups = 1; + + pctl->nfunctions++; + + return 0; +} + +static int sunxi_pinctrl_build_state(struct platform_device *pdev) +{ + struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); + int i; + + pctl->ngroups = pctl->desc->npins; + + /* Allocate groups */ + pctl->groups = devm_kzalloc(&pdev->dev, + pctl->ngroups * sizeof(*pctl->groups), + GFP_KERNEL); + if (!pctl->groups) + return -ENOMEM; + + for (i = 0; i < pctl->desc->npins; i++) { + const struct sunxi_desc_pin *pin = pctl->desc->pins + i; + struct sunxi_pinctrl_group *group = pctl->groups + i; + + group->name = pin->pin.name; + group->pin = pin->pin.number; + } + + /* + * We suppose that we won't have any more functions than pins, + * we'll reallocate that later anyway + */ + pctl->functions = devm_kzalloc(&pdev->dev, + pctl->desc->npins * sizeof(*pctl->functions), + GFP_KERNEL); + if (!pctl->functions) + return -ENOMEM; + + /* Count functions and their associated groups */ + for (i = 0; i < pctl->desc->npins; i++) { + const struct sunxi_desc_pin *pin = pctl->desc->pins + i; + struct sunxi_desc_function *func = pin->functions; + + while (func->name) { + /* Create interrupt mapping while we're at it */ + if (!strcmp(func->name, "irq")) + pctl->irq_array[func->irqnum] = pin->pin.number; + sunxi_pinctrl_add_function(pctl, func->name); + func++; + } + } + + pctl->functions = krealloc(pctl->functions, + pctl->nfunctions * sizeof(*pctl->functions), + GFP_KERNEL); + + for (i = 0; i < pctl->desc->npins; i++) { + const struct sunxi_desc_pin *pin = pctl->desc->pins + i; + struct sunxi_desc_function *func = pin->functions; + + while (func->name) { + struct sunxi_pinctrl_function *func_item; + const char **func_grp; + + func_item = sunxi_pinctrl_find_function_by_name(pctl, + func->name); + if (!func_item) + return -EINVAL; + + if (!func_item->groups) { + func_item->groups = + devm_kzalloc(&pdev->dev, + func_item->ngroups * sizeof(*func_item->groups), + GFP_KERNEL); + if (!func_item->groups) + return -ENOMEM; + } + + func_grp = func_item->groups; + while (*func_grp) + func_grp++; + + *func_grp = pin->pin.name; + func++; + } + } + + return 0; +} + +int sunxi_pinctrl_init(struct platform_device *pdev, + const struct sunxi_pinctrl_desc *desc) +{ + struct device_node *node = pdev->dev.of_node; + struct pinctrl_desc *pctrl_desc; + struct pinctrl_pin_desc *pins; + struct sunxi_pinctrl *pctl; + struct resource *res; + int i, ret, last_pin; + struct clk *clk; + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + platform_set_drvdata(pdev, pctl); + + spin_lock_init(&pctl->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pctl->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctl->membase)) + return PTR_ERR(pctl->membase); + + pctl->dev = &pdev->dev; + pctl->desc = desc; + + ret = sunxi_pinctrl_build_state(pdev); + if (ret) { + dev_err(&pdev->dev, "dt probe failed: %d\n", ret); + return ret; + } + + pins = devm_kzalloc(&pdev->dev, + pctl->desc->npins * sizeof(*pins), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < pctl->desc->npins; i++) + pins[i] = pctl->desc->pins[i].pin; + + pctrl_desc = devm_kzalloc(&pdev->dev, + sizeof(*pctrl_desc), + GFP_KERNEL); + if (!pctrl_desc) + return -ENOMEM; + + pctrl_desc->name = dev_name(&pdev->dev); + pctrl_desc->owner = THIS_MODULE; + pctrl_desc->pins = pins; + pctrl_desc->npins = pctl->desc->npins; + pctrl_desc->confops = &sunxi_pconf_ops; + pctrl_desc->pctlops = &sunxi_pctrl_ops; + pctrl_desc->pmxops = &sunxi_pmx_ops; + + pctl->pctl_dev = pinctrl_register(pctrl_desc, + &pdev->dev, pctl); + if (!pctl->pctl_dev) { + dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); + return -EINVAL; + } + + pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); + if (!pctl->chip) { + ret = -ENOMEM; + goto pinctrl_error; + } + + last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; + pctl->chip->owner = THIS_MODULE; + pctl->chip->request = sunxi_pinctrl_gpio_request, + pctl->chip->free = sunxi_pinctrl_gpio_free, + pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, + pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, + pctl->chip->get = sunxi_pinctrl_gpio_get, + pctl->chip->set = sunxi_pinctrl_gpio_set, + pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, + pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, + pctl->chip->of_gpio_n_cells = 3, + pctl->chip->can_sleep = false, + pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - + pctl->desc->pin_base; + pctl->chip->label = dev_name(&pdev->dev); + pctl->chip->dev = &pdev->dev; + pctl->chip->base = pctl->desc->pin_base; + + ret = gpiochip_add(pctl->chip); + if (ret) + goto pinctrl_error; + + for (i = 0; i < pctl->desc->npins; i++) { + const struct sunxi_desc_pin *pin = pctl->desc->pins + i; + + ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), + pin->pin.number, + pin->pin.number, 1); + if (ret) + goto gpiochip_error; + } + + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto gpiochip_error; + } + + ret = clk_prepare_enable(clk); + if (ret) + goto gpiochip_error; + + pctl->irq = irq_of_parse_and_map(node, 0); + if (!pctl->irq) { + ret = -EINVAL; + goto clk_error; + } + + pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, + &irq_domain_simple_ops, NULL); + if (!pctl->domain) { + dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); + ret = -ENOMEM; + goto clk_error; + } + + for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { + int irqno = irq_create_mapping(pctl->domain, i); + + irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, + handle_simple_irq); + irq_set_chip_data(irqno, pctl); + }; + + irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); + irq_set_handler_data(pctl->irq, pctl); + + dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); + + return 0; + +clk_error: + clk_disable_unprepare(clk); +gpiochip_error: + if (gpiochip_remove(pctl->chip)) + dev_err(&pdev->dev, "failed to remove gpio chip\n"); +pinctrl_error: + pinctrl_unregister(pctl->pctl_dev); + return ret; +} diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h new file mode 100644 index 00000000000..8169ba59887 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -0,0 +1,258 @@ +/* + * Allwinner A1X SoCs pinctrl driver. + * + * Copyright (C) 2012 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PINCTRL_SUNXI_H +#define __PINCTRL_SUNXI_H + +#include <linux/kernel.h> +#include <linux/spinlock.h> + +#define PA_BASE 0 +#define PB_BASE 32 +#define PC_BASE 64 +#define PD_BASE 96 +#define PE_BASE 128 +#define PF_BASE 160 +#define PG_BASE 192 +#define PH_BASE 224 +#define PI_BASE 256 +#define PL_BASE 352 +#define PM_BASE 384 + +#define SUNXI_PINCTRL_PIN(bank, pin) \ + PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) + +#define SUNXI_PIN_NAME_MAX_LEN 5 + +#define BANK_MEM_SIZE 0x24 +#define MUX_REGS_OFFSET 0x0 +#define DATA_REGS_OFFSET 0x10 +#define DLEVEL_REGS_OFFSET 0x14 +#define PULL_REGS_OFFSET 0x1c + +#define PINS_PER_BANK 32 +#define MUX_PINS_PER_REG 8 +#define MUX_PINS_BITS 4 +#define MUX_PINS_MASK 0x0f +#define DATA_PINS_PER_REG 32 +#define DATA_PINS_BITS 1 +#define DATA_PINS_MASK 0x01 +#define DLEVEL_PINS_PER_REG 16 +#define DLEVEL_PINS_BITS 2 +#define DLEVEL_PINS_MASK 0x03 +#define PULL_PINS_PER_REG 16 +#define PULL_PINS_BITS 2 +#define PULL_PINS_MASK 0x03 + +#define SUNXI_IRQ_NUMBER 32 + +#define IRQ_CFG_REG 0x200 +#define IRQ_CFG_IRQ_PER_REG 8 +#define IRQ_CFG_IRQ_BITS 4 +#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) +#define IRQ_CTRL_REG 0x210 +#define IRQ_CTRL_IRQ_PER_REG 32 +#define IRQ_CTRL_IRQ_BITS 1 +#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) +#define IRQ_STATUS_REG 0x214 +#define IRQ_STATUS_IRQ_PER_REG 32 +#define IRQ_STATUS_IRQ_BITS 1 +#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) + +#define IRQ_EDGE_RISING 0x00 +#define IRQ_EDGE_FALLING 0x01 +#define IRQ_LEVEL_HIGH 0x02 +#define IRQ_LEVEL_LOW 0x03 +#define IRQ_EDGE_BOTH 0x04 + +struct sunxi_desc_function { + const char *name; + u8 muxval; + u8 irqnum; +}; + +struct sunxi_desc_pin { + struct pinctrl_pin_desc pin; + struct sunxi_desc_function *functions; +}; + +struct sunxi_pinctrl_desc { + const struct sunxi_desc_pin *pins; + int npins; + unsigned pin_base; +}; + +struct sunxi_pinctrl_function { + const char *name; + const char **groups; + unsigned ngroups; +}; + +struct sunxi_pinctrl_group { + const char *name; + unsigned long config; + unsigned pin; +}; + +struct sunxi_pinctrl { + void __iomem *membase; + struct gpio_chip *chip; + const struct sunxi_pinctrl_desc *desc; + struct device *dev; + struct irq_domain *domain; + struct sunxi_pinctrl_function *functions; + unsigned nfunctions; + struct sunxi_pinctrl_group *groups; + unsigned ngroups; + int irq; + int irq_array[SUNXI_IRQ_NUMBER]; + spinlock_t lock; + struct pinctrl_dev *pctl_dev; +}; + +#define SUNXI_PIN(_pin, ...) \ + { \ + .pin = _pin, \ + .functions = (struct sunxi_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define SUNXI_FUNCTION(_val, _name) \ + { \ + .name = _name, \ + .muxval = _val, \ + } + +#define SUNXI_FUNCTION_IRQ(_val, _irq) \ + { \ + .name = "irq", \ + .muxval = _val, \ + .irqnum = _irq, \ + } + +/* + * The sunXi PIO registers are organized as is: + * 0x00 - 0x0c Muxing values. + * 8 pins per register, each pin having a 4bits value + * 0x10 Pin values + * 32 bits per register, each pin corresponding to one bit + * 0x14 - 0x18 Drive level + * 16 pins per register, each pin having a 2bits value + * 0x1c - 0x20 Pull-Up values + * 16 pins per register, each pin having a 2bits value + * + * This is for the first bank. Each bank will have the same layout, + * with an offset being a multiple of 0x24. + * + * The following functions calculate from the pin number the register + * and the bit offset that we should access. + */ +static inline u32 sunxi_mux_reg(u16 pin) +{ + u8 bank = pin / PINS_PER_BANK; + u32 offset = bank * BANK_MEM_SIZE; + offset += MUX_REGS_OFFSET; + offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; + return round_down(offset, 4); +} + +static inline u32 sunxi_mux_offset(u16 pin) +{ + u32 pin_num = pin % MUX_PINS_PER_REG; + return pin_num * MUX_PINS_BITS; +} + +static inline u32 sunxi_data_reg(u16 pin) +{ + u8 bank = pin / PINS_PER_BANK; + u32 offset = bank * BANK_MEM_SIZE; + offset += DATA_REGS_OFFSET; + offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; + return round_down(offset, 4); +} + +static inline u32 sunxi_data_offset(u16 pin) +{ + u32 pin_num = pin % DATA_PINS_PER_REG; + return pin_num * DATA_PINS_BITS; +} + +static inline u32 sunxi_dlevel_reg(u16 pin) +{ + u8 bank = pin / PINS_PER_BANK; + u32 offset = bank * BANK_MEM_SIZE; + offset += DLEVEL_REGS_OFFSET; + offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; + return round_down(offset, 4); +} + +static inline u32 sunxi_dlevel_offset(u16 pin) +{ + u32 pin_num = pin % DLEVEL_PINS_PER_REG; + return pin_num * DLEVEL_PINS_BITS; +} + +static inline u32 sunxi_pull_reg(u16 pin) +{ + u8 bank = pin / PINS_PER_BANK; + u32 offset = bank * BANK_MEM_SIZE; + offset += PULL_REGS_OFFSET; + offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; + return round_down(offset, 4); +} + +static inline u32 sunxi_pull_offset(u16 pin) +{ + u32 pin_num = pin % PULL_PINS_PER_REG; + return pin_num * PULL_PINS_BITS; +} + +static inline u32 sunxi_irq_cfg_reg(u16 irq) +{ + u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04; + return reg + IRQ_CFG_REG; +} + +static inline u32 sunxi_irq_cfg_offset(u16 irq) +{ + u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; + return irq_num * IRQ_CFG_IRQ_BITS; +} + +static inline u32 sunxi_irq_ctrl_reg(u16 irq) +{ + u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04; + return reg + IRQ_CTRL_REG; +} + +static inline u32 sunxi_irq_ctrl_offset(u16 irq) +{ + u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; + return irq_num * IRQ_CTRL_IRQ_BITS; +} + +static inline u32 sunxi_irq_status_reg(u16 irq) +{ + u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04; + return reg + IRQ_STATUS_REG; +} + +static inline u32 sunxi_irq_status_offset(u16 irq) +{ + u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; + return irq_num * IRQ_STATUS_IRQ_BITS; +} + +int sunxi_pinctrl_init(struct platform_device *pdev, + const struct sunxi_pinctrl_desc *desc); + +#endif /* __PINCTRL_SUNXI_H */ diff --git a/drivers/pinctrl/vt8500/Kconfig b/drivers/pinctrl/vt8500/Kconfig new file mode 100644 index 00000000000..55724a73d94 --- /dev/null +++ b/drivers/pinctrl/vt8500/Kconfig @@ -0,0 +1,52 @@ +# +# VIA/Wondermedia PINCTRL drivers +# + +if ARCH_VT8500 + +config PINCTRL_WMT + bool + select PINMUX + select GENERIC_PINCONF + +config PINCTRL_VT8500 + bool "VIA VT8500 pin controller driver" + depends on ARCH_WM8505 + select PINCTRL_WMT + help + Say yes here to support the gpio/pin control module on + VIA VT8500 SoCs. + +config PINCTRL_WM8505 + bool "Wondermedia WM8505 pin controller driver" + depends on ARCH_WM8505 + select PINCTRL_WMT + help + Say yes here to support the gpio/pin control module on + Wondermedia WM8505 SoCs. + +config PINCTRL_WM8650 + bool "Wondermedia WM8650 pin controller driver" + depends on ARCH_WM8505 + select PINCTRL_WMT + help + Say yes here to support the gpio/pin control module on + Wondermedia WM8650 SoCs. + +config PINCTRL_WM8750 + bool "Wondermedia WM8750 pin controller driver" + depends on ARCH_WM8750 + select PINCTRL_WMT + help + Say yes here to support the gpio/pin control module on + Wondermedia WM8750 SoCs. + +config PINCTRL_WM8850 + bool "Wondermedia WM8850 pin controller driver" + depends on ARCH_WM8850 + select PINCTRL_WMT + help + Say yes here to support the gpio/pin control module on + Wondermedia WM8850 SoCs. + +endif diff --git a/drivers/pinctrl/vt8500/Makefile b/drivers/pinctrl/vt8500/Makefile new file mode 100644 index 00000000000..24ec45dd0d8 --- /dev/null +++ b/drivers/pinctrl/vt8500/Makefile @@ -0,0 +1,8 @@ +# VIA/Wondermedia pinctrl support + +obj-$(CONFIG_PINCTRL_WMT) += pinctrl-wmt.o +obj-$(CONFIG_PINCTRL_VT8500) += pinctrl-vt8500.o +obj-$(CONFIG_PINCTRL_WM8505) += pinctrl-wm8505.o +obj-$(CONFIG_PINCTRL_WM8650) += pinctrl-wm8650.o +obj-$(CONFIG_PINCTRL_WM8750) += pinctrl-wm8750.o +obj-$(CONFIG_PINCTRL_WM8850) += pinctrl-wm8850.o diff --git a/drivers/pinctrl/vt8500/pinctrl-vt8500.c b/drivers/pinctrl/vt8500/pinctrl-vt8500.c new file mode 100644 index 00000000000..f2fe9f85cfa --- /dev/null +++ b/drivers/pinctrl/vt8500/pinctrl-vt8500.c @@ -0,0 +1,501 @@ +/* + * Pinctrl data for VIA VT8500 SoC + * + * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "pinctrl-wmt.h" + +/* + * Describe the register offsets within the GPIO memory space + * The dedicated external GPIO's should always be listed in bank 0 + * so they are exported in the 0..31 range which is what users + * expect. + * + * Do not reorder these banks as it will change the pin numbering + */ +static const struct wmt_pinctrl_bank_registers vt8500_banks[] = { + WMT_PINCTRL_BANK(NO_REG, 0x3C, 0x5C, 0x7C, NO_REG, NO_REG), /* 0 */ + WMT_PINCTRL_BANK(0x00, 0x20, 0x40, 0x60, NO_REG, NO_REG), /* 1 */ + WMT_PINCTRL_BANK(0x04, 0x24, 0x44, 0x64, NO_REG, NO_REG), /* 2 */ + WMT_PINCTRL_BANK(0x08, 0x28, 0x48, 0x68, NO_REG, NO_REG), /* 3 */ + WMT_PINCTRL_BANK(0x0C, 0x2C, 0x4C, 0x6C, NO_REG, NO_REG), /* 4 */ + WMT_PINCTRL_BANK(0x10, 0x30, 0x50, 0x70, NO_REG, NO_REG), /* 5 */ + WMT_PINCTRL_BANK(0x14, 0x34, 0x54, 0x74, NO_REG, NO_REG), /* 6 */ +}; + +/* Please keep sorted by bank/bit */ +#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0) +#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1) +#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2) +#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3) +#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4) +#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5) +#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6) +#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7) +#define WMT_PIN_EXTGPIO8 WMT_PIN(0, 8) +#define WMT_PIN_UART0RTS WMT_PIN(1, 0) +#define WMT_PIN_UART0TXD WMT_PIN(1, 1) +#define WMT_PIN_UART0CTS WMT_PIN(1, 2) +#define WMT_PIN_UART0RXD WMT_PIN(1, 3) +#define WMT_PIN_UART1RTS WMT_PIN(1, 4) +#define WMT_PIN_UART1TXD WMT_PIN(1, 5) +#define WMT_PIN_UART1CTS WMT_PIN(1, 6) +#define WMT_PIN_UART1RXD WMT_PIN(1, 7) +#define WMT_PIN_SPI0CLK WMT_PIN(1, 8) +#define WMT_PIN_SPI0SS WMT_PIN(1, 9) +#define WMT_PIN_SPI0MISO WMT_PIN(1, 10) +#define WMT_PIN_SPI0MOSI WMT_PIN(1, 11) +#define WMT_PIN_SPI1CLK WMT_PIN(1, 12) +#define WMT_PIN_SPI1SS WMT_PIN(1, 13) +#define WMT_PIN_SPI1MISO WMT_PIN(1, 14) +#define WMT_PIN_SPI1MOSI WMT_PIN(1, 15) +#define WMT_PIN_SPI2CLK WMT_PIN(1, 16) +#define WMT_PIN_SPI2SS WMT_PIN(1, 17) +#define WMT_PIN_SPI2MISO WMT_PIN(1, 18) +#define WMT_PIN_SPI2MOSI WMT_PIN(1, 19) +#define WMT_PIN_SDDATA0 WMT_PIN(2, 0) +#define WMT_PIN_SDDATA1 WMT_PIN(2, 1) +#define WMT_PIN_SDDATA2 WMT_PIN(2, 2) +#define WMT_PIN_SDDATA3 WMT_PIN(2, 3) +#define WMT_PIN_MMCDATA0 WMT_PIN(2, 4) +#define WMT_PIN_MMCDATA1 WMT_PIN(2, 5) +#define WMT_PIN_MMCDATA2 WMT_PIN(2, 6) +#define WMT_PIN_MMCDATA3 WMT_PIN(2, 7) +#define WMT_PIN_SDCLK WMT_PIN(2, 8) +#define WMT_PIN_SDWP WMT_PIN(2, 9) +#define WMT_PIN_SDCMD WMT_PIN(2, 10) +#define WMT_PIN_MSDATA0 WMT_PIN(2, 16) +#define WMT_PIN_MSDATA1 WMT_PIN(2, 17) +#define WMT_PIN_MSDATA2 WMT_PIN(2, 18) +#define WMT_PIN_MSDATA3 WMT_PIN(2, 19) +#define WMT_PIN_MSCLK WMT_PIN(2, 20) +#define WMT_PIN_MSBS WMT_PIN(2, 21) +#define WMT_PIN_MSINS WMT_PIN(2, 22) +#define WMT_PIN_I2C0SCL WMT_PIN(2, 24) +#define WMT_PIN_I2C0SDA WMT_PIN(2, 25) +#define WMT_PIN_I2C1SCL WMT_PIN(2, 26) +#define WMT_PIN_I2C1SDA WMT_PIN(2, 27) +#define WMT_PIN_MII0RXD0 WMT_PIN(3, 0) +#define WMT_PIN_MII0RXD1 WMT_PIN(3, 1) +#define WMT_PIN_MII0RXD2 WMT_PIN(3, 2) +#define WMT_PIN_MII0RXD3 WMT_PIN(3, 3) +#define WMT_PIN_MII0RXCLK WMT_PIN(3, 4) +#define WMT_PIN_MII0RXDV WMT_PIN(3, 5) +#define WMT_PIN_MII0RXERR WMT_PIN(3, 6) +#define WMT_PIN_MII0PHYRST WMT_PIN(3, 7) +#define WMT_PIN_MII0TXD0 WMT_PIN(3, 8) +#define WMT_PIN_MII0TXD1 WMT_PIN(3, 9) +#define WMT_PIN_MII0TXD2 WMT_PIN(3, 10) +#define WMT_PIN_MII0TXD3 WMT_PIN(3, 11) +#define WMT_PIN_MII0TXCLK WMT_PIN(3, 12) +#define WMT_PIN_MII0TXEN WMT_PIN(3, 13) +#define WMT_PIN_MII0TXERR WMT_PIN(3, 14) +#define WMT_PIN_MII0PHYPD WMT_PIN(3, 15) +#define WMT_PIN_MII0COL WMT_PIN(3, 16) +#define WMT_PIN_MII0CRS WMT_PIN(3, 17) +#define WMT_PIN_MII0MDIO WMT_PIN(3, 18) +#define WMT_PIN_MII0MDC WMT_PIN(3, 19) +#define WMT_PIN_SEECS WMT_PIN(3, 20) +#define WMT_PIN_SEECK WMT_PIN(3, 21) +#define WMT_PIN_SEEDI WMT_PIN(3, 22) +#define WMT_PIN_SEEDO WMT_PIN(3, 23) +#define WMT_PIN_IDEDREQ0 WMT_PIN(3, 24) +#define WMT_PIN_IDEDREQ1 WMT_PIN(3, 25) +#define WMT_PIN_IDEIOW WMT_PIN(3, 26) +#define WMT_PIN_IDEIOR WMT_PIN(3, 27) +#define WMT_PIN_IDEDACK WMT_PIN(3, 28) +#define WMT_PIN_IDEIORDY WMT_PIN(3, 29) +#define WMT_PIN_IDEINTRQ WMT_PIN(3, 30) +#define WMT_PIN_VDIN0 WMT_PIN(4, 0) +#define WMT_PIN_VDIN1 WMT_PIN(4, 1) +#define WMT_PIN_VDIN2 WMT_PIN(4, 2) +#define WMT_PIN_VDIN3 WMT_PIN(4, 3) +#define WMT_PIN_VDIN4 WMT_PIN(4, 4) +#define WMT_PIN_VDIN5 WMT_PIN(4, 5) +#define WMT_PIN_VDIN6 WMT_PIN(4, 6) +#define WMT_PIN_VDIN7 WMT_PIN(4, 7) +#define WMT_PIN_VDOUT0 WMT_PIN(4, 8) +#define WMT_PIN_VDOUT1 WMT_PIN(4, 9) +#define WMT_PIN_VDOUT2 WMT_PIN(4, 10) +#define WMT_PIN_VDOUT3 WMT_PIN(4, 11) +#define WMT_PIN_VDOUT4 WMT_PIN(4, 12) +#define WMT_PIN_VDOUT5 WMT_PIN(4, 13) +#define WMT_PIN_NANDCLE0 WMT_PIN(4, 14) +#define WMT_PIN_NANDCLE1 WMT_PIN(4, 15) +#define WMT_PIN_VDOUT6_7 WMT_PIN(4, 16) +#define WMT_PIN_VHSYNC WMT_PIN(4, 17) +#define WMT_PIN_VVSYNC WMT_PIN(4, 18) +#define WMT_PIN_TSDIN0 WMT_PIN(5, 8) +#define WMT_PIN_TSDIN1 WMT_PIN(5, 9) +#define WMT_PIN_TSDIN2 WMT_PIN(5, 10) +#define WMT_PIN_TSDIN3 WMT_PIN(5, 11) +#define WMT_PIN_TSDIN4 WMT_PIN(5, 12) +#define WMT_PIN_TSDIN5 WMT_PIN(5, 13) +#define WMT_PIN_TSDIN6 WMT_PIN(5, 14) +#define WMT_PIN_TSDIN7 WMT_PIN(5, 15) +#define WMT_PIN_TSSYNC WMT_PIN(5, 16) +#define WMT_PIN_TSVALID WMT_PIN(5, 17) +#define WMT_PIN_TSCLK WMT_PIN(5, 18) +#define WMT_PIN_LCDD0 WMT_PIN(6, 0) +#define WMT_PIN_LCDD1 WMT_PIN(6, 1) +#define WMT_PIN_LCDD2 WMT_PIN(6, 2) +#define WMT_PIN_LCDD3 WMT_PIN(6, 3) +#define WMT_PIN_LCDD4 WMT_PIN(6, 4) +#define WMT_PIN_LCDD5 WMT_PIN(6, 5) +#define WMT_PIN_LCDD6 WMT_PIN(6, 6) +#define WMT_PIN_LCDD7 WMT_PIN(6, 7) +#define WMT_PIN_LCDD8 WMT_PIN(6, 8) +#define WMT_PIN_LCDD9 WMT_PIN(6, 9) +#define WMT_PIN_LCDD10 WMT_PIN(6, 10) +#define WMT_PIN_LCDD11 WMT_PIN(6, 11) +#define WMT_PIN_LCDD12 WMT_PIN(6, 12) +#define WMT_PIN_LCDD13 WMT_PIN(6, 13) +#define WMT_PIN_LCDD14 WMT_PIN(6, 14) +#define WMT_PIN_LCDD15 WMT_PIN(6, 15) +#define WMT_PIN_LCDD16 WMT_PIN(6, 16) +#define WMT_PIN_LCDD17 WMT_PIN(6, 17) +#define WMT_PIN_LCDCLK WMT_PIN(6, 18) +#define WMT_PIN_LCDDEN WMT_PIN(6, 19) +#define WMT_PIN_LCDLINE WMT_PIN(6, 20) +#define WMT_PIN_LCDFRM WMT_PIN(6, 21) +#define WMT_PIN_LCDBIAS WMT_PIN(6, 22) + +static const struct pinctrl_pin_desc vt8500_pins[] = { + PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"), + PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"), + PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"), + PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"), + PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"), + PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"), + PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"), + PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"), + PINCTRL_PIN(WMT_PIN_EXTGPIO8, "extgpio8"), + PINCTRL_PIN(WMT_PIN_UART0RTS, "uart0_rts"), + PINCTRL_PIN(WMT_PIN_UART0TXD, "uart0_txd"), + PINCTRL_PIN(WMT_PIN_UART0CTS, "uart0_cts"), + PINCTRL_PIN(WMT_PIN_UART0RXD, "uart0_rxd"), + PINCTRL_PIN(WMT_PIN_UART1RTS, "uart1_rts"), + PINCTRL_PIN(WMT_PIN_UART1TXD, "uart1_txd"), + PINCTRL_PIN(WMT_PIN_UART1CTS, "uart1_cts"), + PINCTRL_PIN(WMT_PIN_UART1RXD, "uart1_rxd"), + PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"), + PINCTRL_PIN(WMT_PIN_SPI0SS, "spi0_ss"), + PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"), + PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"), + PINCTRL_PIN(WMT_PIN_SPI1CLK, "spi1_clk"), + PINCTRL_PIN(WMT_PIN_SPI1SS, "spi1_ss"), + PINCTRL_PIN(WMT_PIN_SPI1MISO, "spi1_miso"), + PINCTRL_PIN(WMT_PIN_SPI1MOSI, "spi1_mosi"), + PINCTRL_PIN(WMT_PIN_SPI2CLK, "spi2_clk"), + PINCTRL_PIN(WMT_PIN_SPI2SS, "spi2_ss"), + PINCTRL_PIN(WMT_PIN_SPI2MISO, "spi2_miso"), + PINCTRL_PIN(WMT_PIN_SPI2MOSI, "spi2_mosi"), + PINCTRL_PIN(WMT_PIN_SDDATA0, "sd_data0"), + PINCTRL_PIN(WMT_PIN_SDDATA1, "sd_data1"), + PINCTRL_PIN(WMT_PIN_SDDATA2, "sd_data2"), + PINCTRL_PIN(WMT_PIN_SDDATA3, "sd_data3"), + PINCTRL_PIN(WMT_PIN_MMCDATA0, "mmc_data0"), + PINCTRL_PIN(WMT_PIN_MMCDATA1, "mmc_data1"), + PINCTRL_PIN(WMT_PIN_MMCDATA2, "mmc_data2"), + PINCTRL_PIN(WMT_PIN_MMCDATA3, "mmc_data3"), + PINCTRL_PIN(WMT_PIN_SDCLK, "sd_clk"), + PINCTRL_PIN(WMT_PIN_SDWP, "sd_wp"), + PINCTRL_PIN(WMT_PIN_SDCMD, "sd_cmd"), + PINCTRL_PIN(WMT_PIN_MSDATA0, "ms_data0"), + PINCTRL_PIN(WMT_PIN_MSDATA1, "ms_data1"), + PINCTRL_PIN(WMT_PIN_MSDATA2, "ms_data2"), + PINCTRL_PIN(WMT_PIN_MSDATA3, "ms_data3"), + PINCTRL_PIN(WMT_PIN_MSCLK, "ms_clk"), + PINCTRL_PIN(WMT_PIN_MSBS, "ms_bs"), + PINCTRL_PIN(WMT_PIN_MSINS, "ms_ins"), + PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"), + PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"), + PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"), + PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"), + PINCTRL_PIN(WMT_PIN_MII0RXD0, "mii0_rxd0"), + PINCTRL_PIN(WMT_PIN_MII0RXD1, "mii0_rxd1"), + PINCTRL_PIN(WMT_PIN_MII0RXD2, "mii0_rxd2"), + PINCTRL_PIN(WMT_PIN_MII0RXD3, "mii0_rxd3"), + PINCTRL_PIN(WMT_PIN_MII0RXCLK, "mii0_rxclk"), + PINCTRL_PIN(WMT_PIN_MII0RXDV, "mii0_rxdv"), + PINCTRL_PIN(WMT_PIN_MII0RXERR, "mii0_rxerr"), + PINCTRL_PIN(WMT_PIN_MII0PHYRST, "mii0_phyrst"), + PINCTRL_PIN(WMT_PIN_MII0TXD0, "mii0_txd0"), + PINCTRL_PIN(WMT_PIN_MII0TXD1, "mii0_txd1"), + PINCTRL_PIN(WMT_PIN_MII0TXD2, "mii0_txd2"), + PINCTRL_PIN(WMT_PIN_MII0TXD3, "mii0_txd3"), + PINCTRL_PIN(WMT_PIN_MII0TXCLK, "mii0_txclk"), + PINCTRL_PIN(WMT_PIN_MII0TXEN, "mii0_txen"), + PINCTRL_PIN(WMT_PIN_MII0TXERR, "mii0_txerr"), + PINCTRL_PIN(WMT_PIN_MII0PHYPD, "mii0_phypd"), + PINCTRL_PIN(WMT_PIN_MII0COL, "mii0_col"), + PINCTRL_PIN(WMT_PIN_MII0CRS, "mii0_crs"), + PINCTRL_PIN(WMT_PIN_MII0MDIO, "mii0_mdio"), + PINCTRL_PIN(WMT_PIN_MII0MDC, "mii0_mdc"), + PINCTRL_PIN(WMT_PIN_SEECS, "see_cs"), + PINCTRL_PIN(WMT_PIN_SEECK, "see_ck"), + PINCTRL_PIN(WMT_PIN_SEEDI, "see_di"), + PINCTRL_PIN(WMT_PIN_SEEDO, "see_do"), + PINCTRL_PIN(WMT_PIN_IDEDREQ0, "ide_dreq0"), + PINCTRL_PIN(WMT_PIN_IDEDREQ1, "ide_dreq1"), + PINCTRL_PIN(WMT_PIN_IDEIOW, "ide_iow"), + PINCTRL_PIN(WMT_PIN_IDEIOR, "ide_ior"), + PINCTRL_PIN(WMT_PIN_IDEDACK, "ide_dack"), + PINCTRL_PIN(WMT_PIN_IDEIORDY, "ide_iordy"), + PINCTRL_PIN(WMT_PIN_IDEINTRQ, "ide_intrq"), + PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"), + PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"), + PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"), + PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"), + PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"), + PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"), + PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"), + PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"), + PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"), + PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"), + PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"), + PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"), + PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"), + PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"), + PINCTRL_PIN(WMT_PIN_NANDCLE0, "nand_cle0"), + PINCTRL_PIN(WMT_PIN_NANDCLE1, "nand_cle1"), + PINCTRL_PIN(WMT_PIN_VDOUT6_7, "vdout6_7"), + PINCTRL_PIN(WMT_PIN_VHSYNC, "vhsync"), + PINCTRL_PIN(WMT_PIN_VVSYNC, "vvsync"), + PINCTRL_PIN(WMT_PIN_TSDIN0, "tsdin0"), + PINCTRL_PIN(WMT_PIN_TSDIN1, "tsdin1"), + PINCTRL_PIN(WMT_PIN_TSDIN2, "tsdin2"), + PINCTRL_PIN(WMT_PIN_TSDIN3, "tsdin3"), + PINCTRL_PIN(WMT_PIN_TSDIN4, "tsdin4"), + PINCTRL_PIN(WMT_PIN_TSDIN5, "tsdin5"), + PINCTRL_PIN(WMT_PIN_TSDIN6, "tsdin6"), + PINCTRL_PIN(WMT_PIN_TSDIN7, "tsdin7"), + PINCTRL_PIN(WMT_PIN_TSSYNC, "tssync"), + PINCTRL_PIN(WMT_PIN_TSVALID, "tsvalid"), + PINCTRL_PIN(WMT_PIN_TSCLK, "tsclk"), + PINCTRL_PIN(WMT_PIN_LCDD0, "lcd_d0"), + PINCTRL_PIN(WMT_PIN_LCDD1, "lcd_d1"), + PINCTRL_PIN(WMT_PIN_LCDD2, "lcd_d2"), + PINCTRL_PIN(WMT_PIN_LCDD3, "lcd_d3"), + PINCTRL_PIN(WMT_PIN_LCDD4, "lcd_d4"), + PINCTRL_PIN(WMT_PIN_LCDD5, "lcd_d5"), + PINCTRL_PIN(WMT_PIN_LCDD6, "lcd_d6"), + PINCTRL_PIN(WMT_PIN_LCDD7, "lcd_d7"), + PINCTRL_PIN(WMT_PIN_LCDD8, "lcd_d8"), + PINCTRL_PIN(WMT_PIN_LCDD9, "lcd_d9"), + PINCTRL_PIN(WMT_PIN_LCDD10, "lcd_d10"), + PINCTRL_PIN(WMT_PIN_LCDD11, "lcd_d11"), + PINCTRL_PIN(WMT_PIN_LCDD12, "lcd_d12"), + PINCTRL_PIN(WMT_PIN_LCDD13, "lcd_d13"), + PINCTRL_PIN(WMT_PIN_LCDD14, "lcd_d14"), + PINCTRL_PIN(WMT_PIN_LCDD15, "lcd_d15"), + PINCTRL_PIN(WMT_PIN_LCDD16, "lcd_d16"), + PINCTRL_PIN(WMT_PIN_LCDD17, "lcd_d17"), + PINCTRL_PIN(WMT_PIN_LCDCLK, "lcd_clk"), + PINCTRL_PIN(WMT_PIN_LCDDEN, "lcd_den"), + PINCTRL_PIN(WMT_PIN_LCDLINE, "lcd_line"), + PINCTRL_PIN(WMT_PIN_LCDFRM, "lcd_frm"), + PINCTRL_PIN(WMT_PIN_LCDBIAS, "lcd_bias"), +}; + +/* Order of these names must match the above list */ +static const char * const vt8500_groups[] = { + "extgpio0", + "extgpio1", + "extgpio2", + "extgpio3", + "extgpio4", + "extgpio5", + "extgpio6", + "extgpio7", + "extgpio8", + "uart0_rts", + "uart0_txd", + "uart0_cts", + "uart0_rxd", + "uart1_rts", + "uart1_txd", + "uart1_cts", + "uart1_rxd", + "spi0_clk", + "spi0_ss", + "spi0_miso", + "spi0_mosi", + "spi1_clk", + "spi1_ss", + "spi1_miso", + "spi1_mosi", + "spi2_clk", + "spi2_ss", + "spi2_miso", + "spi2_mosi", + "sd_data0", + "sd_data1", + "sd_data2", + "sd_data3", + "mmc_data0", + "mmc_data1", + "mmc_data2", + "mmc_data3", + "sd_clk", + "sd_wp", + "sd_cmd", + "ms_data0", + "ms_data1", + "ms_data2", + "ms_data3", + "ms_clk", + "ms_bs", + "ms_ins", + "i2c0_scl", + "i2c0_sda", + "i2c1_scl", + "i2c1_sda", + "mii0_rxd0", + "mii0_rxd1", + "mii0_rxd2", + "mii0_rxd3", + "mii0_rxclk", + "mii0_rxdv", + "mii0_rxerr", + "mii0_phyrst", + "mii0_txd0", + "mii0_txd1", + "mii0_txd2", + "mii0_txd3", + "mii0_txclk", + "mii0_txen", + "mii0_txerr", + "mii0_phypd", + "mii0_col", + "mii0_crs", + "mii0_mdio", + "mii0_mdc", + "see_cs", + "see_ck", + "see_di", + "see_do", + "ide_dreq0", + "ide_dreq1", + "ide_iow", + "ide_ior", + "ide_dack", + "ide_iordy", + "ide_intrq", + "vdin0", + "vdin1", + "vdin2", + "vdin3", + "vdin4", + "vdin5", + "vdin6", + "vdin7", + "vdout0", + "vdout1", + "vdout2", + "vdout3", + "vdout4", + "vdout5", + "nand_cle0", + "nand_cle1", + "vdout6_7", + "vhsync", + "vvsync", + "tsdin0", + "tsdin1", + "tsdin2", + "tsdin3", + "tsdin4", + "tsdin5", + "tsdin6", + "tsdin7", + "tssync", + "tsvalid", + "tsclk", + "lcd_d0", + "lcd_d1", + "lcd_d2", + "lcd_d3", + "lcd_d4", + "lcd_d5", + "lcd_d6", + "lcd_d7", + "lcd_d8", + "lcd_d9", + "lcd_d10", + "lcd_d11", + "lcd_d12", + "lcd_d13", + "lcd_d14", + "lcd_d15", + "lcd_d16", + "lcd_d17", + "lcd_clk", + "lcd_den", + "lcd_line", + "lcd_frm", + "lcd_bias", +}; + +static int vt8500_pinctrl_probe(struct platform_device *pdev) +{ + struct wmt_pinctrl_data *data; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) { + dev_err(&pdev->dev, "failed to allocate data\n"); + return -ENOMEM; + } + + data->banks = vt8500_banks; + data->nbanks = ARRAY_SIZE(vt8500_banks); + data->pins = vt8500_pins; + data->npins = ARRAY_SIZE(vt8500_pins); + data->groups = vt8500_groups; + data->ngroups = ARRAY_SIZE(vt8500_groups); + + return wmt_pinctrl_probe(pdev, data); +} + +static int vt8500_pinctrl_remove(struct platform_device *pdev) +{ + return wmt_pinctrl_remove(pdev); +} + +static struct of_device_id wmt_pinctrl_of_match[] = { + { .compatible = "via,vt8500-pinctrl" }, + { /* sentinel */ }, +}; + +static struct platform_driver wmt_pinctrl_driver = { + .probe = vt8500_pinctrl_probe, + .remove = vt8500_pinctrl_remove, + .driver = { + .name = "pinctrl-vt8500", + .owner = THIS_MODULE, + .of_match_table = wmt_pinctrl_of_match, + }, +}; + +module_platform_driver(wmt_pinctrl_driver); + +MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); +MODULE_DESCRIPTION("VIA VT8500 Pincontrol driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match); diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8505.c b/drivers/pinctrl/vt8500/pinctrl-wm8505.c new file mode 100644 index 00000000000..483ba732694 --- /dev/null +++ b/drivers/pinctrl/vt8500/pinctrl-wm8505.c @@ -0,0 +1,532 @@ +/* + * Pinctrl data for Wondermedia WM8505 SoC + * + * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "pinctrl-wmt.h" + +/* + * Describe the register offsets within the GPIO memory space + * The dedicated external GPIO's should always be listed in bank 0 + * so they are exported in the 0..31 range which is what users + * expect. + * + * Do not reorder these banks as it will change the pin numbering + */ +static const struct wmt_pinctrl_bank_registers wm8505_banks[] = { + WMT_PINCTRL_BANK(0x64, 0x8C, 0xB4, 0xDC, NO_REG, NO_REG), /* 0 */ + WMT_PINCTRL_BANK(0x40, 0x68, 0x90, 0xB8, NO_REG, NO_REG), /* 1 */ + WMT_PINCTRL_BANK(0x44, 0x6C, 0x94, 0xBC, NO_REG, NO_REG), /* 2 */ + WMT_PINCTRL_BANK(0x48, 0x70, 0x98, 0xC0, NO_REG, NO_REG), /* 3 */ + WMT_PINCTRL_BANK(0x4C, 0x74, 0x9C, 0xC4, NO_REG, NO_REG), /* 4 */ + WMT_PINCTRL_BANK(0x50, 0x78, 0xA0, 0xC8, NO_REG, NO_REG), /* 5 */ + WMT_PINCTRL_BANK(0x54, 0x7C, 0xA4, 0xD0, NO_REG, NO_REG), /* 6 */ + WMT_PINCTRL_BANK(0x58, 0x80, 0xA8, 0xD4, NO_REG, NO_REG), /* 7 */ + WMT_PINCTRL_BANK(0x5C, 0x84, 0xAC, 0xD8, NO_REG, NO_REG), /* 8 */ + WMT_PINCTRL_BANK(0x60, 0x88, 0xB0, 0xDC, NO_REG, NO_REG), /* 9 */ + WMT_PINCTRL_BANK(0x500, 0x504, 0x508, 0x50C, NO_REG, NO_REG), /* 10 */ +}; + +/* Please keep sorted by bank/bit */ +#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0) +#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1) +#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2) +#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3) +#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4) +#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5) +#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6) +#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7) +#define WMT_PIN_WAKEUP0 WMT_PIN(0, 16) +#define WMT_PIN_WAKEUP1 WMT_PIN(0, 17) +#define WMT_PIN_WAKEUP2 WMT_PIN(0, 18) +#define WMT_PIN_WAKEUP3 WMT_PIN(0, 19) +#define WMT_PIN_SUSGPIO0 WMT_PIN(0, 21) +#define WMT_PIN_SDDATA0 WMT_PIN(1, 0) +#define WMT_PIN_SDDATA1 WMT_PIN(1, 1) +#define WMT_PIN_SDDATA2 WMT_PIN(1, 2) +#define WMT_PIN_SDDATA3 WMT_PIN(1, 3) +#define WMT_PIN_MMCDATA0 WMT_PIN(1, 4) +#define WMT_PIN_MMCDATA1 WMT_PIN(1, 5) +#define WMT_PIN_MMCDATA2 WMT_PIN(1, 6) +#define WMT_PIN_MMCDATA3 WMT_PIN(1, 7) +#define WMT_PIN_VDIN0 WMT_PIN(2, 0) +#define WMT_PIN_VDIN1 WMT_PIN(2, 1) +#define WMT_PIN_VDIN2 WMT_PIN(2, 2) +#define WMT_PIN_VDIN3 WMT_PIN(2, 3) +#define WMT_PIN_VDIN4 WMT_PIN(2, 4) +#define WMT_PIN_VDIN5 WMT_PIN(2, 5) +#define WMT_PIN_VDIN6 WMT_PIN(2, 6) +#define WMT_PIN_VDIN7 WMT_PIN(2, 7) +#define WMT_PIN_VDOUT0 WMT_PIN(2, 8) +#define WMT_PIN_VDOUT1 WMT_PIN(2, 9) +#define WMT_PIN_VDOUT2 WMT_PIN(2, 10) +#define WMT_PIN_VDOUT3 WMT_PIN(2, 11) +#define WMT_PIN_VDOUT4 WMT_PIN(2, 12) +#define WMT_PIN_VDOUT5 WMT_PIN(2, 13) +#define WMT_PIN_VDOUT6 WMT_PIN(2, 14) +#define WMT_PIN_VDOUT7 WMT_PIN(2, 15) +#define WMT_PIN_VDOUT8 WMT_PIN(2, 16) +#define WMT_PIN_VDOUT9 WMT_PIN(2, 17) +#define WMT_PIN_VDOUT10 WMT_PIN(2, 18) +#define WMT_PIN_VDOUT11 WMT_PIN(2, 19) +#define WMT_PIN_VDOUT12 WMT_PIN(2, 20) +#define WMT_PIN_VDOUT13 WMT_PIN(2, 21) +#define WMT_PIN_VDOUT14 WMT_PIN(2, 22) +#define WMT_PIN_VDOUT15 WMT_PIN(2, 23) +#define WMT_PIN_VDOUT16 WMT_PIN(2, 24) +#define WMT_PIN_VDOUT17 WMT_PIN(2, 25) +#define WMT_PIN_VDOUT18 WMT_PIN(2, 26) +#define WMT_PIN_VDOUT19 WMT_PIN(2, 27) +#define WMT_PIN_VDOUT20 WMT_PIN(2, 28) +#define WMT_PIN_VDOUT21 WMT_PIN(2, 29) +#define WMT_PIN_VDOUT22 WMT_PIN(2, 30) +#define WMT_PIN_VDOUT23 WMT_PIN(2, 31) +#define WMT_PIN_VHSYNC WMT_PIN(3, 0) +#define WMT_PIN_VVSYNC WMT_PIN(3, 1) +#define WMT_PIN_VGAHSYNC WMT_PIN(3, 2) +#define WMT_PIN_VGAVSYNC WMT_PIN(3, 3) +#define WMT_PIN_VDHSYNC WMT_PIN(3, 4) +#define WMT_PIN_VDVSYNC WMT_PIN(3, 5) +#define WMT_PIN_NORD0 WMT_PIN(4, 0) +#define WMT_PIN_NORD1 WMT_PIN(4, 1) +#define WMT_PIN_NORD2 WMT_PIN(4, 2) +#define WMT_PIN_NORD3 WMT_PIN(4, 3) +#define WMT_PIN_NORD4 WMT_PIN(4, 4) +#define WMT_PIN_NORD5 WMT_PIN(4, 5) +#define WMT_PIN_NORD6 WMT_PIN(4, 6) +#define WMT_PIN_NORD7 WMT_PIN(4, 7) +#define WMT_PIN_NORD8 WMT_PIN(4, 8) +#define WMT_PIN_NORD9 WMT_PIN(4, 9) +#define WMT_PIN_NORD10 WMT_PIN(4, 10) +#define WMT_PIN_NORD11 WMT_PIN(4, 11) +#define WMT_PIN_NORD12 WMT_PIN(4, 12) +#define WMT_PIN_NORD13 WMT_PIN(4, 13) +#define WMT_PIN_NORD14 WMT_PIN(4, 14) +#define WMT_PIN_NORD15 WMT_PIN(4, 15) +#define WMT_PIN_NORA0 WMT_PIN(5, 0) +#define WMT_PIN_NORA1 WMT_PIN(5, 1) +#define WMT_PIN_NORA2 WMT_PIN(5, 2) +#define WMT_PIN_NORA3 WMT_PIN(5, 3) +#define WMT_PIN_NORA4 WMT_PIN(5, 4) +#define WMT_PIN_NORA5 WMT_PIN(5, 5) +#define WMT_PIN_NORA6 WMT_PIN(5, 6) +#define WMT_PIN_NORA7 WMT_PIN(5, 7) +#define WMT_PIN_NORA8 WMT_PIN(5, 8) +#define WMT_PIN_NORA9 WMT_PIN(5, 9) +#define WMT_PIN_NORA10 WMT_PIN(5, 10) +#define WMT_PIN_NORA11 WMT_PIN(5, 11) +#define WMT_PIN_NORA12 WMT_PIN(5, 12) +#define WMT_PIN_NORA13 WMT_PIN(5, 13) +#define WMT_PIN_NORA14 WMT_PIN(5, 14) +#define WMT_PIN_NORA15 WMT_PIN(5, 15) +#define WMT_PIN_NORA16 WMT_PIN(5, 16) +#define WMT_PIN_NORA17 WMT_PIN(5, 17) +#define WMT_PIN_NORA18 WMT_PIN(5, 18) +#define WMT_PIN_NORA19 WMT_PIN(5, 19) +#define WMT_PIN_NORA20 WMT_PIN(5, 20) +#define WMT_PIN_NORA21 WMT_PIN(5, 21) +#define WMT_PIN_NORA22 WMT_PIN(5, 22) +#define WMT_PIN_NORA23 WMT_PIN(5, 23) +#define WMT_PIN_NORA24 WMT_PIN(5, 24) +#define WMT_PIN_AC97SDI WMT_PIN(6, 0) +#define WMT_PIN_AC97SYNC WMT_PIN(6, 1) +#define WMT_PIN_AC97SDO WMT_PIN(6, 2) +#define WMT_PIN_AC97BCLK WMT_PIN(6, 3) +#define WMT_PIN_AC97RST WMT_PIN(6, 4) +#define WMT_PIN_SFDO WMT_PIN(7, 0) +#define WMT_PIN_SFCS0 WMT_PIN(7, 1) +#define WMT_PIN_SFCS1 WMT_PIN(7, 2) +#define WMT_PIN_SFCLK WMT_PIN(7, 3) +#define WMT_PIN_SFDI WMT_PIN(7, 4) +#define WMT_PIN_SPI0CLK WMT_PIN(8, 0) +#define WMT_PIN_SPI0MISO WMT_PIN(8, 1) +#define WMT_PIN_SPI0MOSI WMT_PIN(8, 2) +#define WMT_PIN_SPI0SS WMT_PIN(8, 3) +#define WMT_PIN_SPI1CLK WMT_PIN(8, 4) +#define WMT_PIN_SPI1MISO WMT_PIN(8, 5) +#define WMT_PIN_SPI1MOSI WMT_PIN(8, 6) +#define WMT_PIN_SPI1SS WMT_PIN(8, 7) +#define WMT_PIN_SPI2CLK WMT_PIN(8, 8) +#define WMT_PIN_SPI2MISO WMT_PIN(8, 9) +#define WMT_PIN_SPI2MOSI WMT_PIN(8, 10) +#define WMT_PIN_SPI2SS WMT_PIN(8, 11) +#define WMT_PIN_UART0_RTS WMT_PIN(9, 0) +#define WMT_PIN_UART0_TXD WMT_PIN(9, 1) +#define WMT_PIN_UART0_CTS WMT_PIN(9, 2) +#define WMT_PIN_UART0_RXD WMT_PIN(9, 3) +#define WMT_PIN_UART1_RTS WMT_PIN(9, 4) +#define WMT_PIN_UART1_TXD WMT_PIN(9, 5) +#define WMT_PIN_UART1_CTS WMT_PIN(9, 6) +#define WMT_PIN_UART1_RXD WMT_PIN(9, 7) +#define WMT_PIN_UART2_RTS WMT_PIN(9, 8) +#define WMT_PIN_UART2_TXD WMT_PIN(9, 9) +#define WMT_PIN_UART2_CTS WMT_PIN(9, 10) +#define WMT_PIN_UART2_RXD WMT_PIN(9, 11) +#define WMT_PIN_UART3_RTS WMT_PIN(9, 12) +#define WMT_PIN_UART3_TXD WMT_PIN(9, 13) +#define WMT_PIN_UART3_CTS WMT_PIN(9, 14) +#define WMT_PIN_UART3_RXD WMT_PIN(9, 15) +#define WMT_PIN_I2C0SCL WMT_PIN(10, 0) +#define WMT_PIN_I2C0SDA WMT_PIN(10, 1) +#define WMT_PIN_I2C1SCL WMT_PIN(10, 2) +#define WMT_PIN_I2C1SDA WMT_PIN(10, 3) +#define WMT_PIN_I2C2SCL WMT_PIN(10, 4) +#define WMT_PIN_I2C2SDA WMT_PIN(10, 5) + +static const struct pinctrl_pin_desc wm8505_pins[] = { + PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"), + PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"), + PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"), + PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"), + PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"), + PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"), + PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"), + PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"), + PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"), + PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"), + PINCTRL_PIN(WMT_PIN_WAKEUP2, "wakeup2"), + PINCTRL_PIN(WMT_PIN_WAKEUP3, "wakeup3"), + PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"), + PINCTRL_PIN(WMT_PIN_SDDATA0, "sd_data0"), + PINCTRL_PIN(WMT_PIN_SDDATA1, "sd_data1"), + PINCTRL_PIN(WMT_PIN_SDDATA2, "sd_data2"), + PINCTRL_PIN(WMT_PIN_SDDATA3, "sd_data3"), + PINCTRL_PIN(WMT_PIN_MMCDATA0, "mmc_data0"), + PINCTRL_PIN(WMT_PIN_MMCDATA1, "mmc_data1"), + PINCTRL_PIN(WMT_PIN_MMCDATA2, "mmc_data2"), + PINCTRL_PIN(WMT_PIN_MMCDATA3, "mmc_data3"), + PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"), + PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"), + PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"), + PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"), + PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"), + PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"), + PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"), + PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"), + PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"), + PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"), + PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"), + PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"), + PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"), + PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"), + PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"), + PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"), + PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"), + PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"), + PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"), + PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"), + PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"), + PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"), + PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"), + PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"), + PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"), + PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"), + PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"), + PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"), + PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"), + PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"), + PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"), + PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"), + PINCTRL_PIN(WMT_PIN_VHSYNC, "v_hsync"), + PINCTRL_PIN(WMT_PIN_VVSYNC, "v_vsync"), + PINCTRL_PIN(WMT_PIN_VGAHSYNC, "vga_hsync"), + PINCTRL_PIN(WMT_PIN_VGAVSYNC, "vga_vsync"), + PINCTRL_PIN(WMT_PIN_VDHSYNC, "vd_hsync"), + PINCTRL_PIN(WMT_PIN_VDVSYNC, "vd_vsync"), + PINCTRL_PIN(WMT_PIN_NORD0, "nor_d0"), + PINCTRL_PIN(WMT_PIN_NORD1, "nor_d1"), + PINCTRL_PIN(WMT_PIN_NORD2, "nor_d2"), + PINCTRL_PIN(WMT_PIN_NORD3, "nor_d3"), + PINCTRL_PIN(WMT_PIN_NORD4, "nor_d4"), + PINCTRL_PIN(WMT_PIN_NORD5, "nor_d5"), + PINCTRL_PIN(WMT_PIN_NORD6, "nor_d6"), + PINCTRL_PIN(WMT_PIN_NORD7, "nor_d7"), + PINCTRL_PIN(WMT_PIN_NORD8, "nor_d8"), + PINCTRL_PIN(WMT_PIN_NORD9, "nor_d9"), + PINCTRL_PIN(WMT_PIN_NORD10, "nor_d10"), + PINCTRL_PIN(WMT_PIN_NORD11, "nor_d11"), + PINCTRL_PIN(WMT_PIN_NORD12, "nor_d12"), + PINCTRL_PIN(WMT_PIN_NORD13, "nor_d13"), + PINCTRL_PIN(WMT_PIN_NORD14, "nor_d14"), + PINCTRL_PIN(WMT_PIN_NORD15, "nor_d15"), + PINCTRL_PIN(WMT_PIN_NORA0, "nor_a0"), + PINCTRL_PIN(WMT_PIN_NORA1, "nor_a1"), + PINCTRL_PIN(WMT_PIN_NORA2, "nor_a2"), + PINCTRL_PIN(WMT_PIN_NORA3, "nor_a3"), + PINCTRL_PIN(WMT_PIN_NORA4, "nor_a4"), + PINCTRL_PIN(WMT_PIN_NORA5, "nor_a5"), + PINCTRL_PIN(WMT_PIN_NORA6, "nor_a6"), + PINCTRL_PIN(WMT_PIN_NORA7, "nor_a7"), + PINCTRL_PIN(WMT_PIN_NORA8, "nor_a8"), + PINCTRL_PIN(WMT_PIN_NORA9, "nor_a9"), + PINCTRL_PIN(WMT_PIN_NORA10, "nor_a10"), + PINCTRL_PIN(WMT_PIN_NORA11, "nor_a11"), + PINCTRL_PIN(WMT_PIN_NORA12, "nor_a12"), + PINCTRL_PIN(WMT_PIN_NORA13, "nor_a13"), + PINCTRL_PIN(WMT_PIN_NORA14, "nor_a14"), + PINCTRL_PIN(WMT_PIN_NORA15, "nor_a15"), + PINCTRL_PIN(WMT_PIN_NORA16, "nor_a16"), + PINCTRL_PIN(WMT_PIN_NORA17, "nor_a17"), + PINCTRL_PIN(WMT_PIN_NORA18, "nor_a18"), + PINCTRL_PIN(WMT_PIN_NORA19, "nor_a19"), + PINCTRL_PIN(WMT_PIN_NORA20, "nor_a20"), + PINCTRL_PIN(WMT_PIN_NORA21, "nor_a21"), + PINCTRL_PIN(WMT_PIN_NORA22, "nor_a22"), + PINCTRL_PIN(WMT_PIN_NORA23, "nor_a23"), + PINCTRL_PIN(WMT_PIN_NORA24, "nor_a24"), + PINCTRL_PIN(WMT_PIN_AC97SDI, "ac97_sdi"), + PINCTRL_PIN(WMT_PIN_AC97SYNC, "ac97_sync"), + PINCTRL_PIN(WMT_PIN_AC97SDO, "ac97_sdo"), + PINCTRL_PIN(WMT_PIN_AC97BCLK, "ac97_bclk"), + PINCTRL_PIN(WMT_PIN_AC97RST, "ac97_rst"), + PINCTRL_PIN(WMT_PIN_SFDO, "sf_do"), + PINCTRL_PIN(WMT_PIN_SFCS0, "sf_cs0"), + PINCTRL_PIN(WMT_PIN_SFCS1, "sf_cs1"), + PINCTRL_PIN(WMT_PIN_SFCLK, "sf_clk"), + PINCTRL_PIN(WMT_PIN_SFDI, "sf_di"), + PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"), + PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"), + PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"), + PINCTRL_PIN(WMT_PIN_SPI0SS, "spi0_ss"), + PINCTRL_PIN(WMT_PIN_SPI1CLK, "spi1_clk"), + PINCTRL_PIN(WMT_PIN_SPI1MISO, "spi1_miso"), + PINCTRL_PIN(WMT_PIN_SPI1MOSI, "spi1_mosi"), + PINCTRL_PIN(WMT_PIN_SPI1SS, "spi1_ss"), + PINCTRL_PIN(WMT_PIN_SPI2CLK, "spi2_clk"), + PINCTRL_PIN(WMT_PIN_SPI2MISO, "spi2_miso"), + PINCTRL_PIN(WMT_PIN_SPI2MOSI, "spi2_mosi"), + PINCTRL_PIN(WMT_PIN_SPI2SS, "spi2_ss"), + PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"), + PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"), + PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"), + PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"), + PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"), + PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"), + PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"), + PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"), + PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"), + PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"), + PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"), + PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"), + PINCTRL_PIN(WMT_PIN_UART3_RTS, "uart3_rts"), + PINCTRL_PIN(WMT_PIN_UART3_TXD, "uart3_txd"), + PINCTRL_PIN(WMT_PIN_UART3_CTS, "uart3_cts"), + PINCTRL_PIN(WMT_PIN_UART3_RXD, "uart3_rxd"), + PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"), + PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"), + PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"), + PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"), + PINCTRL_PIN(WMT_PIN_I2C2SCL, "i2c2_scl"), + PINCTRL_PIN(WMT_PIN_I2C2SDA, "i2c2_sda"), +}; + +/* Order of these names must match the above list */ +static const char * const wm8505_groups[] = { + "extgpio0", + "extgpio1", + "extgpio2", + "extgpio3", + "extgpio4", + "extgpio5", + "extgpio6", + "extgpio7", + "wakeup0", + "wakeup1", + "wakeup2", + "wakeup3", + "susgpio0", + "sd_data0", + "sd_data1", + "sd_data2", + "sd_data3", + "mmc_data0", + "mmc_data1", + "mmc_data2", + "mmc_data3", + "vdin0", + "vdin1", + "vdin2", + "vdin3", + "vdin4", + "vdin5", + "vdin6", + "vdin7", + "vdout0", + "vdout1", + "vdout2", + "vdout3", + "vdout4", + "vdout5", + "vdout6", + "vdout7", + "vdout8", + "vdout9", + "vdout10", + "vdout11", + "vdout12", + "vdout13", + "vdout14", + "vdout15", + "vdout16", + "vdout17", + "vdout18", + "vdout19", + "vdout20", + "vdout21", + "vdout22", + "vdout23", + "v_hsync", + "v_vsync", + "vga_hsync", + "vga_vsync", + "vd_hsync", + "vd_vsync", + "nor_d0", + "nor_d1", + "nor_d2", + "nor_d3", + "nor_d4", + "nor_d5", + "nor_d6", + "nor_d7", + "nor_d8", + "nor_d9", + "nor_d10", + "nor_d11", + "nor_d12", + "nor_d13", + "nor_d14", + "nor_d15", + "nor_a0", + "nor_a1", + "nor_a2", + "nor_a3", + "nor_a4", + "nor_a5", + "nor_a6", + "nor_a7", + "nor_a8", + "nor_a9", + "nor_a10", + "nor_a11", + "nor_a12", + "nor_a13", + "nor_a14", + "nor_a15", + "nor_a16", + "nor_a17", + "nor_a18", + "nor_a19", + "nor_a20", + "nor_a21", + "nor_a22", + "nor_a23", + "nor_a24", + "ac97_sdi", + "ac97_sync", + "ac97_sdo", + "ac97_bclk", + "ac97_rst", + "sf_do", + "sf_cs0", + "sf_cs1", + "sf_clk", + "sf_di", + "spi0_clk", + "spi0_miso", + "spi0_mosi", + "spi0_ss", + "spi1_clk", + "spi1_miso", + "spi1_mosi", + "spi1_ss", + "spi2_clk", + "spi2_miso", + "spi2_mosi", + "spi2_ss", + "uart0_rts", + "uart0_txd", + "uart0_cts", + "uart0_rxd", + "uart1_rts", + "uart1_txd", + "uart1_cts", + "uart1_rxd", + "uart2_rts", + "uart2_txd", + "uart2_cts", + "uart2_rxd", + "uart3_rts", + "uart3_txd", + "uart3_cts", + "uart3_rxd", + "i2c0_scl", + "i2c0_sda", + "i2c1_scl", + "i2c1_sda", + "i2c2_scl", + "i2c2_sda", +}; + +static int wm8505_pinctrl_probe(struct platform_device *pdev) +{ + struct wmt_pinctrl_data *data; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) { + dev_err(&pdev->dev, "failed to allocate data\n"); + return -ENOMEM; + } + + data->banks = wm8505_banks; + data->nbanks = ARRAY_SIZE(wm8505_banks); + data->pins = wm8505_pins; + data->npins = ARRAY_SIZE(wm8505_pins); + data->groups = wm8505_groups; + data->ngroups = ARRAY_SIZE(wm8505_groups); + + return wmt_pinctrl_probe(pdev, data); +} + +static int wm8505_pinctrl_remove(struct platform_device *pdev) +{ + return wmt_pinctrl_remove(pdev); +} + +static struct of_device_id wmt_pinctrl_of_match[] = { + { .compatible = "wm,wm8505-pinctrl" }, + { /* sentinel */ }, +}; + +static struct platform_driver wmt_pinctrl_driver = { + .probe = wm8505_pinctrl_probe, + .remove = wm8505_pinctrl_remove, + .driver = { + .name = "pinctrl-wm8505", + .owner = THIS_MODULE, + .of_match_table = wmt_pinctrl_of_match, + }, +}; + +module_platform_driver(wmt_pinctrl_driver); + +MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); +MODULE_DESCRIPTION("Wondermedia WM8505 Pincontrol driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match); diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8650.c b/drivers/pinctrl/vt8500/pinctrl-wm8650.c new file mode 100644 index 00000000000..7de57f06315 --- /dev/null +++ b/drivers/pinctrl/vt8500/pinctrl-wm8650.c @@ -0,0 +1,370 @@ +/* + * Pinctrl data for Wondermedia WM8650 SoC + * + * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "pinctrl-wmt.h" + +/* + * Describe the register offsets within the GPIO memory space + * The dedicated external GPIO's should always be listed in bank 0 + * so they are exported in the 0..31 range which is what users + * expect. + * + * Do not reorder these banks as it will change the pin numbering + */ +static const struct wmt_pinctrl_bank_registers wm8650_banks[] = { + WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0), /* 0 */ + WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4), /* 1 */ + WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8), /* 2 */ + WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC), /* 3 */ + WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0), /* 4 */ + WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4), /* 5 */ + WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8), /* 6 */ + WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC), /* 7 */ +}; + +/* Please keep sorted by bank/bit */ +#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0) +#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1) +#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2) +#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3) +#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4) +#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5) +#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6) +#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7) +#define WMT_PIN_WAKEUP0 WMT_PIN(0, 16) +#define WMT_PIN_WAKEUP1 WMT_PIN(0, 17) +#define WMT_PIN_SUSGPIO0 WMT_PIN(0, 21) +#define WMT_PIN_SD0CD WMT_PIN(0, 28) +#define WMT_PIN_SD1CD WMT_PIN(0, 29) +#define WMT_PIN_VDOUT0 WMT_PIN(1, 0) +#define WMT_PIN_VDOUT1 WMT_PIN(1, 1) +#define WMT_PIN_VDOUT2 WMT_PIN(1, 2) +#define WMT_PIN_VDOUT3 WMT_PIN(1, 3) +#define WMT_PIN_VDOUT4 WMT_PIN(1, 4) +#define WMT_PIN_VDOUT5 WMT_PIN(1, 5) +#define WMT_PIN_VDOUT6 WMT_PIN(1, 6) +#define WMT_PIN_VDOUT7 WMT_PIN(1, 7) +#define WMT_PIN_VDOUT8 WMT_PIN(1, 8) +#define WMT_PIN_VDOUT9 WMT_PIN(1, 9) +#define WMT_PIN_VDOUT10 WMT_PIN(1, 10) +#define WMT_PIN_VDOUT11 WMT_PIN(1, 11) +#define WMT_PIN_VDOUT12 WMT_PIN(1, 12) +#define WMT_PIN_VDOUT13 WMT_PIN(1, 13) +#define WMT_PIN_VDOUT14 WMT_PIN(1, 14) +#define WMT_PIN_VDOUT15 WMT_PIN(1, 15) +#define WMT_PIN_VDOUT16 WMT_PIN(1, 16) +#define WMT_PIN_VDOUT17 WMT_PIN(1, 17) +#define WMT_PIN_VDOUT18 WMT_PIN(1, 18) +#define WMT_PIN_VDOUT19 WMT_PIN(1, 19) +#define WMT_PIN_VDOUT20 WMT_PIN(1, 20) +#define WMT_PIN_VDOUT21 WMT_PIN(1, 21) +#define WMT_PIN_VDOUT22 WMT_PIN(1, 22) +#define WMT_PIN_VDOUT23 WMT_PIN(1, 23) +#define WMT_PIN_VDIN0 WMT_PIN(2, 0) +#define WMT_PIN_VDIN1 WMT_PIN(2, 1) +#define WMT_PIN_VDIN2 WMT_PIN(2, 2) +#define WMT_PIN_VDIN3 WMT_PIN(2, 3) +#define WMT_PIN_VDIN4 WMT_PIN(2, 4) +#define WMT_PIN_VDIN5 WMT_PIN(2, 5) +#define WMT_PIN_VDIN6 WMT_PIN(2, 6) +#define WMT_PIN_VDIN7 WMT_PIN(2, 7) +#define WMT_PIN_I2C1SCL WMT_PIN(2, 12) +#define WMT_PIN_I2C1SDA WMT_PIN(2, 13) +#define WMT_PIN_SPI0MOSI WMT_PIN(2, 24) +#define WMT_PIN_SPI0MISO WMT_PIN(2, 25) +#define WMT_PIN_SPI0SS0 WMT_PIN(2, 26) +#define WMT_PIN_SPI0CLK WMT_PIN(2, 27) +#define WMT_PIN_SD0DATA0 WMT_PIN(3, 8) +#define WMT_PIN_SD0DATA1 WMT_PIN(3, 9) +#define WMT_PIN_SD0DATA2 WMT_PIN(3, 10) +#define WMT_PIN_SD0DATA3 WMT_PIN(3, 11) +#define WMT_PIN_SD0CLK WMT_PIN(3, 12) +#define WMT_PIN_SD0WP WMT_PIN(3, 13) +#define WMT_PIN_SD0CMD WMT_PIN(3, 14) +#define WMT_PIN_SD1DATA0 WMT_PIN(3, 24) +#define WMT_PIN_SD1DATA1 WMT_PIN(3, 25) +#define WMT_PIN_SD1DATA2 WMT_PIN(3, 26) +#define WMT_PIN_SD1DATA3 WMT_PIN(3, 27) +#define WMT_PIN_SD1DATA4 WMT_PIN(3, 28) +#define WMT_PIN_SD1DATA5 WMT_PIN(3, 29) +#define WMT_PIN_SD1DATA6 WMT_PIN(3, 30) +#define WMT_PIN_SD1DATA7 WMT_PIN(3, 31) +#define WMT_PIN_I2C0SCL WMT_PIN(5, 8) +#define WMT_PIN_I2C0SDA WMT_PIN(5, 9) +#define WMT_PIN_UART0RTS WMT_PIN(5, 16) +#define WMT_PIN_UART0TXD WMT_PIN(5, 17) +#define WMT_PIN_UART0CTS WMT_PIN(5, 18) +#define WMT_PIN_UART0RXD WMT_PIN(5, 19) +#define WMT_PIN_UART1RTS WMT_PIN(5, 20) +#define WMT_PIN_UART1TXD WMT_PIN(5, 21) +#define WMT_PIN_UART1CTS WMT_PIN(5, 22) +#define WMT_PIN_UART1RXD WMT_PIN(5, 23) +#define WMT_PIN_UART2RTS WMT_PIN(5, 24) +#define WMT_PIN_UART2TXD WMT_PIN(5, 25) +#define WMT_PIN_UART2CTS WMT_PIN(5, 26) +#define WMT_PIN_UART2RXD WMT_PIN(5, 27) +#define WMT_PIN_UART3RTS WMT_PIN(5, 28) +#define WMT_PIN_UART3TXD WMT_PIN(5, 29) +#define WMT_PIN_UART3CTS WMT_PIN(5, 30) +#define WMT_PIN_UART3RXD WMT_PIN(5, 31) +#define WMT_PIN_KPADROW0 WMT_PIN(6, 16) +#define WMT_PIN_KPADROW1 WMT_PIN(6, 17) +#define WMT_PIN_KPADCOL0 WMT_PIN(6, 18) +#define WMT_PIN_KPADCOL1 WMT_PIN(6, 19) +#define WMT_PIN_SD1CLK WMT_PIN(7, 0) +#define WMT_PIN_SD1CMD WMT_PIN(7, 1) +#define WMT_PIN_SD1WP WMT_PIN(7, 13) + +static const struct pinctrl_pin_desc wm8650_pins[] = { + PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"), + PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"), + PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"), + PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"), + PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"), + PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"), + PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"), + PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"), + PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"), + PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"), + PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"), + PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"), + PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"), + PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"), + PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"), + PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"), + PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"), + PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"), + PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"), + PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"), + PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"), + PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"), + PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"), + PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"), + PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"), + PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"), + PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"), + PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"), + PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"), + PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"), + PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"), + PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"), + PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"), + PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"), + PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"), + PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"), + PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"), + PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"), + PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"), + PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"), + PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"), + PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"), + PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"), + PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"), + PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"), + PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"), + PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"), + PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"), + PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"), + PINCTRL_PIN(WMT_PIN_SPI0SS0, "spi0_ss0"), + PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"), + PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"), + PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"), + PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"), + PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"), + PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"), + PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"), + PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"), + PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"), + PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"), + PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"), + PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"), + PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"), + PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"), + PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"), + PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"), + PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"), + PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"), + PINCTRL_PIN(WMT_PIN_UART0RTS, "uart0_rts"), + PINCTRL_PIN(WMT_PIN_UART0TXD, "uart0_txd"), + PINCTRL_PIN(WMT_PIN_UART0CTS, "uart0_cts"), + PINCTRL_PIN(WMT_PIN_UART0RXD, "uart0_rxd"), + PINCTRL_PIN(WMT_PIN_UART1RTS, "uart1_rts"), + PINCTRL_PIN(WMT_PIN_UART1TXD, "uart1_txd"), + PINCTRL_PIN(WMT_PIN_UART1CTS, "uart1_cts"), + PINCTRL_PIN(WMT_PIN_UART1RXD, "uart1_rxd"), + PINCTRL_PIN(WMT_PIN_UART2RTS, "uart2_rts"), + PINCTRL_PIN(WMT_PIN_UART2TXD, "uart2_txd"), + PINCTRL_PIN(WMT_PIN_UART2CTS, "uart2_cts"), + PINCTRL_PIN(WMT_PIN_UART2RXD, "uart2_rxd"), + PINCTRL_PIN(WMT_PIN_UART3RTS, "uart3_rts"), + PINCTRL_PIN(WMT_PIN_UART3TXD, "uart3_txd"), + PINCTRL_PIN(WMT_PIN_UART3CTS, "uart3_cts"), + PINCTRL_PIN(WMT_PIN_UART3RXD, "uart3_rxd"), + PINCTRL_PIN(WMT_PIN_KPADROW0, "kpadrow0"), + PINCTRL_PIN(WMT_PIN_KPADROW1, "kpadrow1"), + PINCTRL_PIN(WMT_PIN_KPADCOL0, "kpadcol0"), + PINCTRL_PIN(WMT_PIN_KPADCOL1, "kpadcol1"), + PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"), + PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"), + PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"), +}; + +/* Order of these names must match the above list */ +static const char * const wm8650_groups[] = { + "extgpio0", + "extgpio1", + "extgpio2", + "extgpio3", + "extgpio4", + "extgpio5", + "extgpio6", + "extgpio7", + "wakeup0", + "wakeup1", + "susgpio0", + "sd0_cd", + "sd1_cd", + "vdout0", + "vdout1", + "vdout2", + "vdout3", + "vdout4", + "vdout5", + "vdout6", + "vdout7", + "vdout8", + "vdout9", + "vdout10", + "vdout11", + "vdout12", + "vdout13", + "vdout14", + "vdout15", + "vdout16", + "vdout17", + "vdout18", + "vdout19", + "vdout20", + "vdout21", + "vdout22", + "vdout23", + "vdin0", + "vdin1", + "vdin2", + "vdin3", + "vdin4", + "vdin5", + "vdin6", + "vdin7", + "i2c1_scl", + "i2c1_sda", + "spi0_mosi", + "spi0_miso", + "spi0_ss0", + "spi0_clk", + "sd0_data0", + "sd0_data1", + "sd0_data2", + "sd0_data3", + "sd0_clk", + "sd0_wp", + "sd0_cmd", + "sd1_data0", + "sd1_data1", + "sd1_data2", + "sd1_data3", + "sd1_data4", + "sd1_data5", + "sd1_data6", + "sd1_data7", + "i2c0_scl", + "i2c0_sda", + "uart0_rts", + "uart0_txd", + "uart0_cts", + "uart0_rxd", + "uart1_rts", + "uart1_txd", + "uart1_cts", + "uart1_rxd", + "uart2_rts", + "uart2_txd", + "uart2_cts", + "uart2_rxd", + "uart3_rts", + "uart3_txd", + "uart3_cts", + "uart3_rxd", + "kpadrow0", + "kpadrow1", + "kpadcol0", + "kpadcol1", + "sd1_clk", + "sd1_cmd", + "sd1_wp", +}; + +static int wm8650_pinctrl_probe(struct platform_device *pdev) +{ + struct wmt_pinctrl_data *data; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) { + dev_err(&pdev->dev, "failed to allocate data\n"); + return -ENOMEM; + } + + data->banks = wm8650_banks; + data->nbanks = ARRAY_SIZE(wm8650_banks); + data->pins = wm8650_pins; + data->npins = ARRAY_SIZE(wm8650_pins); + data->groups = wm8650_groups; + data->ngroups = ARRAY_SIZE(wm8650_groups); + + return wmt_pinctrl_probe(pdev, data); +} + +static int wm8650_pinctrl_remove(struct platform_device *pdev) +{ + return wmt_pinctrl_remove(pdev); +} + +static struct of_device_id wmt_pinctrl_of_match[] = { + { .compatible = "wm,wm8650-pinctrl" }, + { /* sentinel */ }, +}; + +static struct platform_driver wmt_pinctrl_driver = { + .probe = wm8650_pinctrl_probe, + .remove = wm8650_pinctrl_remove, + .driver = { + .name = "pinctrl-wm8650", + .owner = THIS_MODULE, + .of_match_table = wmt_pinctrl_of_match, + }, +}; + +module_platform_driver(wmt_pinctrl_driver); + +MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); +MODULE_DESCRIPTION("Wondermedia WM8650 Pincontrol driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match); diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8750.c b/drivers/pinctrl/vt8500/pinctrl-wm8750.c new file mode 100644 index 00000000000..de43262398d --- /dev/null +++ b/drivers/pinctrl/vt8500/pinctrl-wm8750.c @@ -0,0 +1,409 @@ +/* + * Pinctrl data for Wondermedia WM8750 SoC + * + * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "pinctrl-wmt.h" + +/* + * Describe the register offsets within the GPIO memory space + * The dedicated external GPIO's should always be listed in bank 0 + * so they are exported in the 0..31 range which is what users + * expect. + * + * Do not reorder these banks as it will change the pin numbering + */ +static const struct wmt_pinctrl_bank_registers wm8750_banks[] = { + WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0), /* 0 */ + WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4), /* 1 */ + WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8), /* 2 */ + WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC), /* 3 */ + WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0), /* 4 */ + WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4), /* 5 */ + WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8), /* 6 */ + WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC), /* 7 */ + WMT_PINCTRL_BANK(0x60, 0xA0, 0xE0, 0x20, 0x4A0, 0x4E0), /* 8 */ + WMT_PINCTRL_BANK(0x70, 0xB0, 0xF0, 0x30, 0x4B0, 0x4F0), /* 9 */ + WMT_PINCTRL_BANK(0x7C, 0xBC, 0xDC, 0x3C, 0x4BC, 0x4FC), /* 10 */ +}; + +/* Please keep sorted by bank/bit */ +#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0) +#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1) +#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2) +#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3) +#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4) +#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5) +#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6) +#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7) +#define WMT_PIN_WAKEUP0 WMT_PIN(0, 16) +#define WMT_PIN_WAKEUP1 WMT_PIN(0, 17) +#define WMT_PIN_SD0CD WMT_PIN(0, 28) +#define WMT_PIN_VDOUT0 WMT_PIN(1, 0) +#define WMT_PIN_VDOUT1 WMT_PIN(1, 1) +#define WMT_PIN_VDOUT2 WMT_PIN(1, 2) +#define WMT_PIN_VDOUT3 WMT_PIN(1, 3) +#define WMT_PIN_VDOUT4 WMT_PIN(1, 4) +#define WMT_PIN_VDOUT5 WMT_PIN(1, 5) +#define WMT_PIN_VDOUT6 WMT_PIN(1, 6) +#define WMT_PIN_VDOUT7 WMT_PIN(1, 7) +#define WMT_PIN_VDOUT8 WMT_PIN(1, 8) +#define WMT_PIN_VDOUT9 WMT_PIN(1, 9) +#define WMT_PIN_VDOUT10 WMT_PIN(1, 10) +#define WMT_PIN_VDOUT11 WMT_PIN(1, 11) +#define WMT_PIN_VDOUT12 WMT_PIN(1, 12) +#define WMT_PIN_VDOUT13 WMT_PIN(1, 13) +#define WMT_PIN_VDOUT14 WMT_PIN(1, 14) +#define WMT_PIN_VDOUT15 WMT_PIN(1, 15) +#define WMT_PIN_VDOUT16 WMT_PIN(1, 16) +#define WMT_PIN_VDOUT17 WMT_PIN(1, 17) +#define WMT_PIN_VDOUT18 WMT_PIN(1, 18) +#define WMT_PIN_VDOUT19 WMT_PIN(1, 19) +#define WMT_PIN_VDOUT20 WMT_PIN(1, 20) +#define WMT_PIN_VDOUT21 WMT_PIN(1, 21) +#define WMT_PIN_VDOUT22 WMT_PIN(1, 22) +#define WMT_PIN_VDOUT23 WMT_PIN(1, 23) +#define WMT_PIN_VDIN0 WMT_PIN(2, 0) +#define WMT_PIN_VDIN1 WMT_PIN(2, 1) +#define WMT_PIN_VDIN2 WMT_PIN(2, 2) +#define WMT_PIN_VDIN3 WMT_PIN(2, 3) +#define WMT_PIN_VDIN4 WMT_PIN(2, 4) +#define WMT_PIN_VDIN5 WMT_PIN(2, 5) +#define WMT_PIN_VDIN6 WMT_PIN(2, 6) +#define WMT_PIN_VDIN7 WMT_PIN(2, 7) +#define WMT_PIN_SPI0_MOSI WMT_PIN(2, 24) +#define WMT_PIN_SPI0_MISO WMT_PIN(2, 25) +#define WMT_PIN_SPI0_SS WMT_PIN(2, 26) +#define WMT_PIN_SPI0_CLK WMT_PIN(2, 27) +#define WMT_PIN_SPI0_SSB WMT_PIN(2, 28) +#define WMT_PIN_SD0CLK WMT_PIN(3, 17) +#define WMT_PIN_SD0CMD WMT_PIN(3, 18) +#define WMT_PIN_SD0WP WMT_PIN(3, 19) +#define WMT_PIN_SD0DATA0 WMT_PIN(3, 20) +#define WMT_PIN_SD0DATA1 WMT_PIN(3, 21) +#define WMT_PIN_SD0DATA2 WMT_PIN(3, 22) +#define WMT_PIN_SD0DATA3 WMT_PIN(3, 23) +#define WMT_PIN_SD1DATA0 WMT_PIN(3, 24) +#define WMT_PIN_SD1DATA1 WMT_PIN(3, 25) +#define WMT_PIN_SD1DATA2 WMT_PIN(3, 26) +#define WMT_PIN_SD1DATA3 WMT_PIN(3, 27) +#define WMT_PIN_SD1DATA4 WMT_PIN(3, 28) +#define WMT_PIN_SD1DATA5 WMT_PIN(3, 29) +#define WMT_PIN_SD1DATA6 WMT_PIN(3, 30) +#define WMT_PIN_SD1DATA7 WMT_PIN(3, 31) +#define WMT_PIN_I2C0_SCL WMT_PIN(5, 8) +#define WMT_PIN_I2C0_SDA WMT_PIN(5, 9) +#define WMT_PIN_I2C1_SCL WMT_PIN(5, 10) +#define WMT_PIN_I2C1_SDA WMT_PIN(5, 11) +#define WMT_PIN_I2C2_SCL WMT_PIN(5, 12) +#define WMT_PIN_I2C2_SDA WMT_PIN(5, 13) +#define WMT_PIN_UART0_RTS WMT_PIN(5, 16) +#define WMT_PIN_UART0_TXD WMT_PIN(5, 17) +#define WMT_PIN_UART0_CTS WMT_PIN(5, 18) +#define WMT_PIN_UART0_RXD WMT_PIN(5, 19) +#define WMT_PIN_UART1_RTS WMT_PIN(5, 20) +#define WMT_PIN_UART1_TXD WMT_PIN(5, 21) +#define WMT_PIN_UART1_CTS WMT_PIN(5, 22) +#define WMT_PIN_UART1_RXD WMT_PIN(5, 23) +#define WMT_PIN_UART2_RTS WMT_PIN(5, 24) +#define WMT_PIN_UART2_TXD WMT_PIN(5, 25) +#define WMT_PIN_UART2_CTS WMT_PIN(5, 26) +#define WMT_PIN_UART2_RXD WMT_PIN(5, 27) +#define WMT_PIN_UART3_RTS WMT_PIN(5, 28) +#define WMT_PIN_UART3_TXD WMT_PIN(5, 29) +#define WMT_PIN_UART3_CTS WMT_PIN(5, 30) +#define WMT_PIN_UART3_RXD WMT_PIN(5, 31) +#define WMT_PIN_SD2CD WMT_PIN(6, 0) +#define WMT_PIN_SD2DATA3 WMT_PIN(6, 1) +#define WMT_PIN_SD2DATA0 WMT_PIN(6, 2) +#define WMT_PIN_SD2WP WMT_PIN(6, 3) +#define WMT_PIN_SD2DATA1 WMT_PIN(6, 4) +#define WMT_PIN_SD2DATA2 WMT_PIN(6, 5) +#define WMT_PIN_SD2CMD WMT_PIN(6, 6) +#define WMT_PIN_SD2CLK WMT_PIN(6, 7) +#define WMT_PIN_SD2PWR WMT_PIN(6, 9) +#define WMT_PIN_SD1CLK WMT_PIN(7, 0) +#define WMT_PIN_SD1CMD WMT_PIN(7, 1) +#define WMT_PIN_SD1PWR WMT_PIN(7, 10) +#define WMT_PIN_SD1WP WMT_PIN(7, 11) +#define WMT_PIN_SD1CD WMT_PIN(7, 12) +#define WMT_PIN_SPI0SS3 WMT_PIN(7, 24) +#define WMT_PIN_SPI0SS2 WMT_PIN(7, 25) +#define WMT_PIN_PWMOUT1 WMT_PIN(7, 26) +#define WMT_PIN_PWMOUT0 WMT_PIN(7, 27) + +static const struct pinctrl_pin_desc wm8750_pins[] = { + PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"), + PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"), + PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"), + PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"), + PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"), + PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"), + PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"), + PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"), + PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"), + PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"), + PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"), + PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"), + PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"), + PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"), + PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"), + PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"), + PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"), + PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"), + PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"), + PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"), + PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"), + PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"), + PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"), + PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"), + PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"), + PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"), + PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"), + PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"), + PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"), + PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"), + PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"), + PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"), + PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"), + PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"), + PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"), + PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"), + PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"), + PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"), + PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"), + PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"), + PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"), + PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"), + PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"), + PINCTRL_PIN(WMT_PIN_SPI0_MOSI, "spi0_mosi"), + PINCTRL_PIN(WMT_PIN_SPI0_MISO, "spi0_miso"), + PINCTRL_PIN(WMT_PIN_SPI0_SS, "spi0_ss"), + PINCTRL_PIN(WMT_PIN_SPI0_CLK, "spi0_clk"), + PINCTRL_PIN(WMT_PIN_SPI0_SSB, "spi0_ssb"), + PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"), + PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"), + PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"), + PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"), + PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"), + PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"), + PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"), + PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"), + PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"), + PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"), + PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"), + PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"), + PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"), + PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"), + PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"), + PINCTRL_PIN(WMT_PIN_I2C0_SCL, "i2c0_scl"), + PINCTRL_PIN(WMT_PIN_I2C0_SDA, "i2c0_sda"), + PINCTRL_PIN(WMT_PIN_I2C1_SCL, "i2c1_scl"), + PINCTRL_PIN(WMT_PIN_I2C1_SDA, "i2c1_sda"), + PINCTRL_PIN(WMT_PIN_I2C2_SCL, "i2c2_scl"), + PINCTRL_PIN(WMT_PIN_I2C2_SDA, "i2c2_sda"), + PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"), + PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"), + PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"), + PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"), + PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"), + PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"), + PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"), + PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"), + PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"), + PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"), + PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"), + PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"), + PINCTRL_PIN(WMT_PIN_UART3_RTS, "uart3_rts"), + PINCTRL_PIN(WMT_PIN_UART3_TXD, "uart3_txd"), + PINCTRL_PIN(WMT_PIN_UART3_CTS, "uart3_cts"), + PINCTRL_PIN(WMT_PIN_UART3_RXD, "uart3_rxd"), + PINCTRL_PIN(WMT_PIN_SD2CD, "sd2_cd"), + PINCTRL_PIN(WMT_PIN_SD2DATA3, "sd2_data3"), + PINCTRL_PIN(WMT_PIN_SD2DATA0, "sd2_data0"), + PINCTRL_PIN(WMT_PIN_SD2WP, "sd2_wp"), + PINCTRL_PIN(WMT_PIN_SD2DATA1, "sd2_data1"), + PINCTRL_PIN(WMT_PIN_SD2DATA2, "sd2_data2"), + PINCTRL_PIN(WMT_PIN_SD2CMD, "sd2_cmd"), + PINCTRL_PIN(WMT_PIN_SD2CLK, "sd2_clk"), + PINCTRL_PIN(WMT_PIN_SD2PWR, "sd2_pwr"), + PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"), + PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"), + PINCTRL_PIN(WMT_PIN_SD1PWR, "sd1_pwr"), + PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"), + PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"), + PINCTRL_PIN(WMT_PIN_SPI0SS3, "spi0_ss3"), + PINCTRL_PIN(WMT_PIN_SPI0SS2, "spi0_ss2"), + PINCTRL_PIN(WMT_PIN_PWMOUT1, "pwmout1"), + PINCTRL_PIN(WMT_PIN_PWMOUT0, "pwmout0"), +}; + +/* Order of these names must match the above list */ +static const char * const wm8750_groups[] = { + "extgpio0", + "extgpio1", + "extgpio2", + "extgpio3", + "extgpio4", + "extgpio5", + "extgpio6", + "extgpio7", + "wakeup0", + "wakeup1", + "sd0_cd", + "vdout0", + "vdout1", + "vdout2", + "vdout3", + "vdout4", + "vdout5", + "vdout6", + "vdout7", + "vdout8", + "vdout9", + "vdout10", + "vdout11", + "vdout12", + "vdout13", + "vdout14", + "vdout15", + "vdout16", + "vdout17", + "vdout18", + "vdout19", + "vdout20", + "vdout21", + "vdout22", + "vdout23", + "vdin0", + "vdin1", + "vdin2", + "vdin3", + "vdin4", + "vdin5", + "vdin6", + "vdin7", + "spi0_mosi", + "spi0_miso", + "spi0_ss", + "spi0_clk", + "spi0_ssb", + "sd0_clk", + "sd0_cmd", + "sd0_wp", + "sd0_data0", + "sd0_data1", + "sd0_data2", + "sd0_data3", + "sd1_data0", + "sd1_data1", + "sd1_data2", + "sd1_data3", + "sd1_data4", + "sd1_data5", + "sd1_data6", + "sd1_data7", + "i2c0_scl", + "i2c0_sda", + "i2c1_scl", + "i2c1_sda", + "i2c2_scl", + "i2c2_sda", + "uart0_rts", + "uart0_txd", + "uart0_cts", + "uart0_rxd", + "uart1_rts", + "uart1_txd", + "uart1_cts", + "uart1_rxd", + "uart2_rts", + "uart2_txd", + "uart2_cts", + "uart2_rxd", + "uart3_rts", + "uart3_txd", + "uart3_cts", + "uart3_rxd", + "sd2_cd", + "sd2_data3", + "sd2_data0", + "sd2_wp", + "sd2_data1", + "sd2_data2", + "sd2_cmd", + "sd2_clk", + "sd2_pwr", + "sd1_clk", + "sd1_cmd", + "sd1_pwr", + "sd1_wp", + "sd1_cd", + "spi0_ss3", + "spi0_ss2", + "pwmout1", + "pwmout0", +}; + +static int wm8750_pinctrl_probe(struct platform_device *pdev) +{ + struct wmt_pinctrl_data *data; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) { + dev_err(&pdev->dev, "failed to allocate data\n"); + return -ENOMEM; + } + + data->banks = wm8750_banks; + data->nbanks = ARRAY_SIZE(wm8750_banks); + data->pins = wm8750_pins; + data->npins = ARRAY_SIZE(wm8750_pins); + data->groups = wm8750_groups; + data->ngroups = ARRAY_SIZE(wm8750_groups); + + return wmt_pinctrl_probe(pdev, data); +} + +static int wm8750_pinctrl_remove(struct platform_device *pdev) +{ + return wmt_pinctrl_remove(pdev); +} + +static struct of_device_id wmt_pinctrl_of_match[] = { + { .compatible = "wm,wm8750-pinctrl" }, + { /* sentinel */ }, +}; + +static struct platform_driver wmt_pinctrl_driver = { + .probe = wm8750_pinctrl_probe, + .remove = wm8750_pinctrl_remove, + .driver = { + .name = "pinctrl-wm8750", + .owner = THIS_MODULE, + .of_match_table = wmt_pinctrl_of_match, + }, +}; + +module_platform_driver(wmt_pinctrl_driver); + +MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); +MODULE_DESCRIPTION("Wondermedia WM8750 Pincontrol driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match); diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8850.c b/drivers/pinctrl/vt8500/pinctrl-wm8850.c new file mode 100644 index 00000000000..ecadce9c91d --- /dev/null +++ b/drivers/pinctrl/vt8500/pinctrl-wm8850.c @@ -0,0 +1,388 @@ +/* + * Pinctrl data for Wondermedia WM8850 SoC + * + * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "pinctrl-wmt.h" + +/* + * Describe the register offsets within the GPIO memory space + * The dedicated external GPIO's should always be listed in bank 0 + * so they are exported in the 0..31 range which is what users + * expect. + * + * Do not reorder these banks as it will change the pin numbering + */ +static const struct wmt_pinctrl_bank_registers wm8850_banks[] = { + WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0), /* 0 */ + WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4), /* 1 */ + WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8), /* 2 */ + WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC), /* 3 */ + WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0), /* 4 */ + WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4), /* 5 */ + WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8), /* 6 */ + WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC), /* 7 */ + WMT_PINCTRL_BANK(0x60, 0xA0, 0xE0, 0x20, 0x4A0, 0x4E0), /* 8 */ + WMT_PINCTRL_BANK(0x70, 0xB0, 0xF0, 0x30, 0x4B0, 0x4F0), /* 9 */ + WMT_PINCTRL_BANK(0x7C, 0xBC, 0xDC, 0x3C, 0x4BC, 0x4FC), /* 10 */ +}; + +/* Please keep sorted by bank/bit */ +#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0) +#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1) +#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2) +#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3) +#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4) +#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5) +#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6) +#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7) +#define WMT_PIN_WAKEUP0 WMT_PIN(0, 16) +#define WMT_PIN_WAKEUP1 WMT_PIN(0, 17) +#define WMT_PIN_WAKEUP2 WMT_PIN(0, 18) +#define WMT_PIN_WAKEUP3 WMT_PIN(0, 19) +#define WMT_PIN_SUSGPIO0 WMT_PIN(0, 21) +#define WMT_PIN_SUSGPIO1 WMT_PIN(0, 22) +#define WMT_PIN_SD0CD WMT_PIN(0, 28) +#define WMT_PIN_VDOUT0 WMT_PIN(1, 0) +#define WMT_PIN_VDOUT1 WMT_PIN(1, 1) +#define WMT_PIN_VDOUT2 WMT_PIN(1, 2) +#define WMT_PIN_VDOUT3 WMT_PIN(1, 3) +#define WMT_PIN_VDOUT4 WMT_PIN(1, 4) +#define WMT_PIN_VDOUT5 WMT_PIN(1, 5) +#define WMT_PIN_VDOUT6 WMT_PIN(1, 6) +#define WMT_PIN_VDOUT7 WMT_PIN(1, 7) +#define WMT_PIN_VDOUT8 WMT_PIN(1, 8) +#define WMT_PIN_VDOUT9 WMT_PIN(1, 9) +#define WMT_PIN_VDOUT10 WMT_PIN(1, 10) +#define WMT_PIN_VDOUT11 WMT_PIN(1, 11) +#define WMT_PIN_VDOUT12 WMT_PIN(1, 12) +#define WMT_PIN_VDOUT13 WMT_PIN(1, 13) +#define WMT_PIN_VDOUT14 WMT_PIN(1, 14) +#define WMT_PIN_VDOUT15 WMT_PIN(1, 15) +#define WMT_PIN_VDOUT16 WMT_PIN(1, 16) +#define WMT_PIN_VDOUT17 WMT_PIN(1, 17) +#define WMT_PIN_VDOUT18 WMT_PIN(1, 18) +#define WMT_PIN_VDOUT19 WMT_PIN(1, 19) +#define WMT_PIN_VDOUT20 WMT_PIN(1, 20) +#define WMT_PIN_VDOUT21 WMT_PIN(1, 21) +#define WMT_PIN_VDOUT22 WMT_PIN(1, 22) +#define WMT_PIN_VDOUT23 WMT_PIN(1, 23) +#define WMT_PIN_VDIN0 WMT_PIN(2, 0) +#define WMT_PIN_VDIN1 WMT_PIN(2, 1) +#define WMT_PIN_VDIN2 WMT_PIN(2, 2) +#define WMT_PIN_VDIN3 WMT_PIN(2, 3) +#define WMT_PIN_VDIN4 WMT_PIN(2, 4) +#define WMT_PIN_VDIN5 WMT_PIN(2, 5) +#define WMT_PIN_VDIN6 WMT_PIN(2, 6) +#define WMT_PIN_VDIN7 WMT_PIN(2, 7) +#define WMT_PIN_SPI0_MOSI WMT_PIN(2, 24) +#define WMT_PIN_SPI0_MISO WMT_PIN(2, 25) +#define WMT_PIN_SPI0_SS WMT_PIN(2, 26) +#define WMT_PIN_SPI0_CLK WMT_PIN(2, 27) +#define WMT_PIN_SPI0_SSB WMT_PIN(2, 28) +#define WMT_PIN_SD0CLK WMT_PIN(3, 17) +#define WMT_PIN_SD0CMD WMT_PIN(3, 18) +#define WMT_PIN_SD0WP WMT_PIN(3, 19) +#define WMT_PIN_SD0DATA0 WMT_PIN(3, 20) +#define WMT_PIN_SD0DATA1 WMT_PIN(3, 21) +#define WMT_PIN_SD0DATA2 WMT_PIN(3, 22) +#define WMT_PIN_SD0DATA3 WMT_PIN(3, 23) +#define WMT_PIN_SD1DATA0 WMT_PIN(3, 24) +#define WMT_PIN_SD1DATA1 WMT_PIN(3, 25) +#define WMT_PIN_SD1DATA2 WMT_PIN(3, 26) +#define WMT_PIN_SD1DATA3 WMT_PIN(3, 27) +#define WMT_PIN_SD1DATA4 WMT_PIN(3, 28) +#define WMT_PIN_SD1DATA5 WMT_PIN(3, 29) +#define WMT_PIN_SD1DATA6 WMT_PIN(3, 30) +#define WMT_PIN_SD1DATA7 WMT_PIN(3, 31) +#define WMT_PIN_I2C0_SCL WMT_PIN(5, 8) +#define WMT_PIN_I2C0_SDA WMT_PIN(5, 9) +#define WMT_PIN_I2C1_SCL WMT_PIN(5, 10) +#define WMT_PIN_I2C1_SDA WMT_PIN(5, 11) +#define WMT_PIN_I2C2_SCL WMT_PIN(5, 12) +#define WMT_PIN_I2C2_SDA WMT_PIN(5, 13) +#define WMT_PIN_UART0_RTS WMT_PIN(5, 16) +#define WMT_PIN_UART0_TXD WMT_PIN(5, 17) +#define WMT_PIN_UART0_CTS WMT_PIN(5, 18) +#define WMT_PIN_UART0_RXD WMT_PIN(5, 19) +#define WMT_PIN_UART1_RTS WMT_PIN(5, 20) +#define WMT_PIN_UART1_TXD WMT_PIN(5, 21) +#define WMT_PIN_UART1_CTS WMT_PIN(5, 22) +#define WMT_PIN_UART1_RXD WMT_PIN(5, 23) +#define WMT_PIN_UART2_RTS WMT_PIN(5, 24) +#define WMT_PIN_UART2_TXD WMT_PIN(5, 25) +#define WMT_PIN_UART2_CTS WMT_PIN(5, 26) +#define WMT_PIN_UART2_RXD WMT_PIN(5, 27) +#define WMT_PIN_SD2WP WMT_PIN(6, 3) +#define WMT_PIN_SD2CMD WMT_PIN(6, 6) +#define WMT_PIN_SD2CLK WMT_PIN(6, 7) +#define WMT_PIN_SD2PWR WMT_PIN(6, 9) +#define WMT_PIN_SD1CLK WMT_PIN(7, 0) +#define WMT_PIN_SD1CMD WMT_PIN(7, 1) +#define WMT_PIN_SD1PWR WMT_PIN(7, 10) +#define WMT_PIN_SD1WP WMT_PIN(7, 11) +#define WMT_PIN_SD1CD WMT_PIN(7, 12) +#define WMT_PIN_PWMOUT1 WMT_PIN(7, 26) +#define WMT_PIN_PWMOUT0 WMT_PIN(7, 27) + +static const struct pinctrl_pin_desc wm8850_pins[] = { + PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"), + PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"), + PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"), + PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"), + PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"), + PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"), + PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"), + PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"), + PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"), + PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"), + PINCTRL_PIN(WMT_PIN_WAKEUP2, "wakeup2"), + PINCTRL_PIN(WMT_PIN_WAKEUP3, "wakeup3"), + PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"), + PINCTRL_PIN(WMT_PIN_SUSGPIO1, "susgpio1"), + PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"), + PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"), + PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"), + PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"), + PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"), + PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"), + PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"), + PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"), + PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"), + PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"), + PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"), + PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"), + PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"), + PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"), + PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"), + PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"), + PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"), + PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"), + PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"), + PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"), + PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"), + PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"), + PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"), + PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"), + PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"), + PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"), + PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"), + PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"), + PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"), + PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"), + PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"), + PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"), + PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"), + PINCTRL_PIN(WMT_PIN_SPI0_MOSI, "spi0_mosi"), + PINCTRL_PIN(WMT_PIN_SPI0_MISO, "spi0_miso"), + PINCTRL_PIN(WMT_PIN_SPI0_SS, "spi0_ss"), + PINCTRL_PIN(WMT_PIN_SPI0_CLK, "spi0_clk"), + PINCTRL_PIN(WMT_PIN_SPI0_SSB, "spi0_ssb"), + PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"), + PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"), + PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"), + PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"), + PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"), + PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"), + PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"), + PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"), + PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"), + PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"), + PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"), + PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"), + PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"), + PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"), + PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"), + PINCTRL_PIN(WMT_PIN_I2C0_SCL, "i2c0_scl"), + PINCTRL_PIN(WMT_PIN_I2C0_SDA, "i2c0_sda"), + PINCTRL_PIN(WMT_PIN_I2C1_SCL, "i2c1_scl"), + PINCTRL_PIN(WMT_PIN_I2C1_SDA, "i2c1_sda"), + PINCTRL_PIN(WMT_PIN_I2C2_SCL, "i2c2_scl"), + PINCTRL_PIN(WMT_PIN_I2C2_SDA, "i2c2_sda"), + PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"), + PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"), + PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"), + PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"), + PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"), + PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"), + PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"), + PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"), + PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"), + PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"), + PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"), + PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"), + PINCTRL_PIN(WMT_PIN_SD2WP, "sd2_wp"), + PINCTRL_PIN(WMT_PIN_SD2CMD, "sd2_cmd"), + PINCTRL_PIN(WMT_PIN_SD2CLK, "sd2_clk"), + PINCTRL_PIN(WMT_PIN_SD2PWR, "sd2_pwr"), + PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"), + PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"), + PINCTRL_PIN(WMT_PIN_SD1PWR, "sd1_pwr"), + PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"), + PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"), + PINCTRL_PIN(WMT_PIN_PWMOUT1, "pwmout1"), + PINCTRL_PIN(WMT_PIN_PWMOUT0, "pwmout0"), +}; + +/* Order of these names must match the above list */ +static const char * const wm8850_groups[] = { + "extgpio0", + "extgpio1", + "extgpio2", + "extgpio3", + "extgpio4", + "extgpio5", + "extgpio6", + "extgpio7", + "wakeup0", + "wakeup1", + "wakeup2", + "wakeup3", + "susgpio0", + "susgpio1", + "sd0_cd", + "vdout0", + "vdout1", + "vdout2", + "vdout3", + "vdout4", + "vdout5", + "vdout6", + "vdout7", + "vdout8", + "vdout9", + "vdout10", + "vdout11", + "vdout12", + "vdout13", + "vdout14", + "vdout15", + "vdout16", + "vdout17", + "vdout18", + "vdout19", + "vdout20", + "vdout21", + "vdout22", + "vdout23", + "vdin0", + "vdin1", + "vdin2", + "vdin3", + "vdin4", + "vdin5", + "vdin6", + "vdin7", + "spi0_mosi", + "spi0_miso", + "spi0_ss", + "spi0_clk", + "spi0_ssb", + "sd0_clk", + "sd0_cmd", + "sd0_wp", + "sd0_data0", + "sd0_data1", + "sd0_data2", + "sd0_data3", + "sd1_data0", + "sd1_data1", + "sd1_data2", + "sd1_data3", + "sd1_data4", + "sd1_data5", + "sd1_data6", + "sd1_data7", + "i2c0_scl", + "i2c0_sda", + "i2c1_scl", + "i2c1_sda", + "i2c2_scl", + "i2c2_sda", + "uart0_rts", + "uart0_txd", + "uart0_cts", + "uart0_rxd", + "uart1_rts", + "uart1_txd", + "uart1_cts", + "uart1_rxd", + "uart2_rts", + "uart2_txd", + "uart2_cts", + "uart2_rxd", + "sd2_wp", + "sd2_cmd", + "sd2_clk", + "sd2_pwr", + "sd1_clk", + "sd1_cmd", + "sd1_pwr", + "sd1_wp", + "sd1_cd", + "pwmout1", + "pwmout0", +}; + +static int wm8850_pinctrl_probe(struct platform_device *pdev) +{ + struct wmt_pinctrl_data *data; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) { + dev_err(&pdev->dev, "failed to allocate data\n"); + return -ENOMEM; + } + + data->banks = wm8850_banks; + data->nbanks = ARRAY_SIZE(wm8850_banks); + data->pins = wm8850_pins; + data->npins = ARRAY_SIZE(wm8850_pins); + data->groups = wm8850_groups; + data->ngroups = ARRAY_SIZE(wm8850_groups); + + return wmt_pinctrl_probe(pdev, data); +} + +static int wm8850_pinctrl_remove(struct platform_device *pdev) +{ + return wmt_pinctrl_remove(pdev); +} + +static struct of_device_id wmt_pinctrl_of_match[] = { + { .compatible = "wm,wm8850-pinctrl" }, + { /* sentinel */ }, +}; + +static struct platform_driver wmt_pinctrl_driver = { + .probe = wm8850_pinctrl_probe, + .remove = wm8850_pinctrl_remove, + .driver = { + .name = "pinctrl-wm8850", + .owner = THIS_MODULE, + .of_match_table = wmt_pinctrl_of_match, + }, +}; + +module_platform_driver(wmt_pinctrl_driver); + +MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); +MODULE_DESCRIPTION("Wondermedia WM8850 Pincontrol driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match); diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c new file mode 100644 index 00000000000..2c61281bebd --- /dev/null +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -0,0 +1,649 @@ +/* + * Pinctrl driver for the Wondermedia SoC's + * + * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "pinctrl-wmt.h" + +static inline void wmt_setbits(struct wmt_pinctrl_data *data, u32 reg, + u32 mask) +{ + u32 val; + + val = readl_relaxed(data->base + reg); + val |= mask; + writel_relaxed(val, data->base + reg); +} + +static inline void wmt_clearbits(struct wmt_pinctrl_data *data, u32 reg, + u32 mask) +{ + u32 val; + + val = readl_relaxed(data->base + reg); + val &= ~mask; + writel_relaxed(val, data->base + reg); +} + +enum wmt_func_sel { + WMT_FSEL_GPIO_IN = 0, + WMT_FSEL_GPIO_OUT = 1, + WMT_FSEL_ALT = 2, + WMT_FSEL_COUNT = 3, +}; + +static const char * const wmt_functions[WMT_FSEL_COUNT] = { + [WMT_FSEL_GPIO_IN] = "gpio_in", + [WMT_FSEL_GPIO_OUT] = "gpio_out", + [WMT_FSEL_ALT] = "alt", +}; + +static int wmt_pmx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return WMT_FSEL_COUNT; +} + +static const char *wmt_pmx_get_function_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return wmt_functions[selector]; +} + +static int wmt_pmx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + + /* every pin does every function */ + *groups = data->groups; + *num_groups = data->ngroups; + + return 0; +} + +static int wmt_set_pinmux(struct wmt_pinctrl_data *data, unsigned func, + unsigned pin) +{ + u32 bank = WMT_BANK_FROM_PIN(pin); + u32 bit = WMT_BIT_FROM_PIN(pin); + u32 reg_en = data->banks[bank].reg_en; + u32 reg_dir = data->banks[bank].reg_dir; + + if (reg_dir == NO_REG) { + dev_err(data->dev, "pin:%d no direction register defined\n", + pin); + return -EINVAL; + } + + /* + * If reg_en == NO_REG, we assume it is a dedicated GPIO and cannot be + * disabled (as on VT8500) and that no alternate function is available. + */ + switch (func) { + case WMT_FSEL_GPIO_IN: + if (reg_en != NO_REG) + wmt_setbits(data, reg_en, BIT(bit)); + wmt_clearbits(data, reg_dir, BIT(bit)); + break; + case WMT_FSEL_GPIO_OUT: + if (reg_en != NO_REG) + wmt_setbits(data, reg_en, BIT(bit)); + wmt_setbits(data, reg_dir, BIT(bit)); + break; + case WMT_FSEL_ALT: + if (reg_en == NO_REG) { + dev_err(data->dev, "pin:%d no alt function available\n", + pin); + return -EINVAL; + } + wmt_clearbits(data, reg_en, BIT(bit)); + } + + return 0; +} + +static int wmt_pmx_enable(struct pinctrl_dev *pctldev, + unsigned func_selector, + unsigned group_selector) +{ + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + u32 pinnum = data->pins[group_selector].number; + + return wmt_set_pinmux(data, func_selector, pinnum); +} + +static void wmt_pmx_disable(struct pinctrl_dev *pctldev, + unsigned func_selector, + unsigned group_selector) +{ + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + u32 pinnum = data->pins[group_selector].number; + + /* disable by setting GPIO_IN */ + wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, pinnum); +} + +static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + + /* disable by setting GPIO_IN */ + wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, offset); +} + +static int wmt_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, + bool input) +{ + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + + wmt_set_pinmux(data, (input ? WMT_FSEL_GPIO_IN : WMT_FSEL_GPIO_OUT), + offset); + + return 0; +} + +static struct pinmux_ops wmt_pinmux_ops = { + .get_functions_count = wmt_pmx_get_functions_count, + .get_function_name = wmt_pmx_get_function_name, + .get_function_groups = wmt_pmx_get_function_groups, + .enable = wmt_pmx_enable, + .disable = wmt_pmx_disable, + .gpio_disable_free = wmt_pmx_gpio_disable_free, + .gpio_set_direction = wmt_pmx_gpio_set_direction, +}; + +static int wmt_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + + return data->ngroups; +} + +static const char *wmt_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + + return data->groups[selector]; +} + +static int wmt_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + + *pins = &data->pins[selector].number; + *num_pins = 1; + + return 0; +} + +static int wmt_pctl_find_group_by_pin(struct wmt_pinctrl_data *data, u32 pin) +{ + int i; + + for (i = 0; i < data->npins; i++) { + if (data->pins[i].number == pin) + return i; + } + + return -EINVAL; +} + +static int wmt_pctl_dt_node_to_map_func(struct wmt_pinctrl_data *data, + struct device_node *np, + u32 pin, u32 fnum, + struct pinctrl_map **maps) +{ + int group; + struct pinctrl_map *map = *maps; + + if (fnum >= ARRAY_SIZE(wmt_functions)) { + dev_err(data->dev, "invalid wm,function %d\n", fnum); + return -EINVAL; + } + + group = wmt_pctl_find_group_by_pin(data, pin); + if (group < 0) { + dev_err(data->dev, "unable to match pin %d to group\n", pin); + return group; + } + + map->type = PIN_MAP_TYPE_MUX_GROUP; + map->data.mux.group = data->groups[group]; + map->data.mux.function = wmt_functions[fnum]; + (*maps)++; + + return 0; +} + +static int wmt_pctl_dt_node_to_map_pull(struct wmt_pinctrl_data *data, + struct device_node *np, + u32 pin, u32 pull, + struct pinctrl_map **maps) +{ + int group; + unsigned long *configs; + struct pinctrl_map *map = *maps; + + if (pull > 2) { + dev_err(data->dev, "invalid wm,pull %d\n", pull); + return -EINVAL; + } + + group = wmt_pctl_find_group_by_pin(data, pin); + if (group < 0) { + dev_err(data->dev, "unable to match pin %d to group\n", pin); + return group; + } + + configs = kzalloc(sizeof(*configs), GFP_KERNEL); + if (!configs) + return -ENOMEM; + + switch (pull) { + case 0: + configs[0] = PIN_CONFIG_BIAS_DISABLE; + break; + case 1: + configs[0] = PIN_CONFIG_BIAS_PULL_DOWN; + break; + case 2: + configs[0] = PIN_CONFIG_BIAS_PULL_UP; + break; + default: + configs[0] = PIN_CONFIG_BIAS_DISABLE; + dev_err(data->dev, "invalid pull state %d - disabling\n", pull); + } + + map->type = PIN_MAP_TYPE_CONFIGS_PIN; + map->data.configs.group_or_pin = data->groups[group]; + map->data.configs.configs = configs; + map->data.configs.num_configs = 1; + (*maps)++; + + return 0; +} + +static void wmt_pctl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *maps, + unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(maps[i].data.configs.configs); + + kfree(maps); +} + +static int wmt_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct pinctrl_map *maps, *cur_map; + struct property *pins, *funcs, *pulls; + u32 pin, func, pull; + int num_pins, num_funcs, num_pulls, maps_per_pin; + int i, err; + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + + pins = of_find_property(np, "wm,pins", NULL); + if (!pins) { + dev_err(data->dev, "missing wmt,pins property\n"); + return -EINVAL; + } + + funcs = of_find_property(np, "wm,function", NULL); + pulls = of_find_property(np, "wm,pull", NULL); + + if (!funcs && !pulls) { + dev_err(data->dev, "neither wm,function nor wm,pull specified\n"); + return -EINVAL; + } + + /* + * The following lines calculate how many values are defined for each + * of the properties. + */ + num_pins = pins->length / sizeof(u32); + num_funcs = funcs ? (funcs->length / sizeof(u32)) : 0; + num_pulls = pulls ? (pulls->length / sizeof(u32)) : 0; + + if (num_funcs > 1 && num_funcs != num_pins) { + dev_err(data->dev, "wm,function must have 1 or %d entries\n", + num_pins); + return -EINVAL; + } + + if (num_pulls > 1 && num_pulls != num_pins) { + dev_err(data->dev, "wm,pull must have 1 or %d entries\n", + num_pins); + return -EINVAL; + } + + maps_per_pin = 0; + if (num_funcs) + maps_per_pin++; + if (num_pulls) + maps_per_pin++; + + cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps), + GFP_KERNEL); + if (!maps) + return -ENOMEM; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(np, "wm,pins", i, &pin); + if (err) + goto fail; + + if (pin >= (data->nbanks * 32)) { + dev_err(data->dev, "invalid wm,pins value\n"); + err = -EINVAL; + goto fail; + } + + if (num_funcs) { + err = of_property_read_u32_index(np, "wm,function", + (num_funcs > 1 ? i : 0), &func); + if (err) + goto fail; + + err = wmt_pctl_dt_node_to_map_func(data, np, pin, func, + &cur_map); + if (err) + goto fail; + } + + if (num_pulls) { + err = of_property_read_u32_index(np, "wm,pull", + (num_pulls > 1 ? i : 0), &pull); + if (err) + goto fail; + + err = wmt_pctl_dt_node_to_map_pull(data, np, pin, pull, + &cur_map); + if (err) + goto fail; + } + } + *map = maps; + *num_maps = num_pins * maps_per_pin; + return 0; + +/* + * The fail path removes any maps that have been allocated. The fail path is + * only called from code after maps has been kzalloc'd. It is also safe to + * pass 'num_pins * maps_per_pin' as the map count even though we probably + * failed before all the mappings were read as all maps are allocated at once, + * and configs are only allocated for .type = PIN_MAP_TYPE_CONFIGS_PIN - there + * is no failpath where a config can be allocated without .type being set. + */ +fail: + wmt_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); + return err; +} + +static struct pinctrl_ops wmt_pctl_ops = { + .get_groups_count = wmt_get_groups_count, + .get_group_name = wmt_get_group_name, + .get_group_pins = wmt_get_group_pins, + .dt_node_to_map = wmt_pctl_dt_node_to_map, + .dt_free_map = wmt_pctl_dt_free_map, +}; + +static int wmt_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + return -ENOTSUPP; +} + +static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) +{ + struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + u16 arg; + u32 bank = WMT_BANK_FROM_PIN(pin); + u32 bit = WMT_BIT_FROM_PIN(pin); + u32 reg_pull_en = data->banks[bank].reg_pull_en; + u32 reg_pull_cfg = data->banks[bank].reg_pull_cfg; + int i; + + if ((reg_pull_en == NO_REG) || (reg_pull_cfg == NO_REG)) { + dev_err(data->dev, "bias functions not supported on pin %d\n", + pin); + return -EINVAL; + } + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + if ((param == PIN_CONFIG_BIAS_PULL_DOWN) || + (param == PIN_CONFIG_BIAS_PULL_UP)) { + if (arg == 0) + param = PIN_CONFIG_BIAS_DISABLE; + } + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + wmt_clearbits(data, reg_pull_en, BIT(bit)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + wmt_clearbits(data, reg_pull_cfg, BIT(bit)); + wmt_setbits(data, reg_pull_en, BIT(bit)); + break; + case PIN_CONFIG_BIAS_PULL_UP: + wmt_setbits(data, reg_pull_cfg, BIT(bit)); + wmt_setbits(data, reg_pull_en, BIT(bit)); + break; + default: + dev_err(data->dev, "unknown pinconf param\n"); + return -EINVAL; + } + } /* for each config */ + + return 0; +} + +static struct pinconf_ops wmt_pinconf_ops = { + .pin_config_get = wmt_pinconf_get, + .pin_config_set = wmt_pinconf_set, +}; + +static struct pinctrl_desc wmt_desc = { + .owner = THIS_MODULE, + .name = "pinctrl-wmt", + .pctlops = &wmt_pctl_ops, + .pmxops = &wmt_pinmux_ops, + .confops = &wmt_pinconf_ops, +}; + +static int wmt_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void wmt_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int wmt_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev); + u32 bank = WMT_BANK_FROM_PIN(offset); + u32 bit = WMT_BIT_FROM_PIN(offset); + u32 reg_dir = data->banks[bank].reg_dir; + u32 val; + + val = readl_relaxed(data->base + reg_dir); + if (val & BIT(bit)) + return GPIOF_DIR_OUT; + else + return GPIOF_DIR_IN; +} + +static int wmt_gpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev); + u32 bank = WMT_BANK_FROM_PIN(offset); + u32 bit = WMT_BIT_FROM_PIN(offset); + u32 reg_data_in = data->banks[bank].reg_data_in; + + if (reg_data_in == NO_REG) { + dev_err(data->dev, "no data in register defined\n"); + return -EINVAL; + } + + return !!(readl_relaxed(data->base + reg_data_in) & BIT(bit)); +} + +static void wmt_gpio_set_value(struct gpio_chip *chip, unsigned offset, + int val) +{ + struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev); + u32 bank = WMT_BANK_FROM_PIN(offset); + u32 bit = WMT_BIT_FROM_PIN(offset); + u32 reg_data_out = data->banks[bank].reg_data_out; + + if (reg_data_out == NO_REG) { + dev_err(data->dev, "no data out register defined\n"); + return; + } + + if (val) + wmt_setbits(data, reg_data_out, BIT(bit)); + else + wmt_clearbits(data, reg_data_out, BIT(bit)); +} + +static int wmt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int wmt_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + wmt_gpio_set_value(chip, offset, value); + return pinctrl_gpio_direction_output(chip->base + offset); +} + +static struct gpio_chip wmt_gpio_chip = { + .label = "gpio-wmt", + .owner = THIS_MODULE, + .request = wmt_gpio_request, + .free = wmt_gpio_free, + .get_direction = wmt_gpio_get_direction, + .direction_input = wmt_gpio_direction_input, + .direction_output = wmt_gpio_direction_output, + .get = wmt_gpio_get_value, + .set = wmt_gpio_set_value, + .can_sleep = false, +}; + +int wmt_pinctrl_probe(struct platform_device *pdev, + struct wmt_pinctrl_data *data) +{ + int err; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + + wmt_desc.pins = data->pins; + wmt_desc.npins = data->npins; + + data->gpio_chip = wmt_gpio_chip; + data->gpio_chip.dev = &pdev->dev; + data->gpio_chip.of_node = pdev->dev.of_node; + data->gpio_chip.ngpio = data->nbanks * 32; + + platform_set_drvdata(pdev, data); + + data->dev = &pdev->dev; + + data->pctl_dev = pinctrl_register(&wmt_desc, &pdev->dev, data); + if (!data->pctl_dev) { + dev_err(&pdev->dev, "Failed to register pinctrl\n"); + return -EINVAL; + } + + err = gpiochip_add(&data->gpio_chip); + if (err) { + dev_err(&pdev->dev, "could not add GPIO chip\n"); + goto fail_gpio; + } + + err = gpiochip_add_pin_range(&data->gpio_chip, dev_name(data->dev), + 0, 0, data->nbanks * 32); + if (err) + goto fail_range; + + dev_info(&pdev->dev, "Pin controller initialized\n"); + + return 0; + +fail_range: + if (gpiochip_remove(&data->gpio_chip)) + dev_err(&pdev->dev, "failed to remove gpio chip\n"); +fail_gpio: + pinctrl_unregister(data->pctl_dev); + return err; +} + +int wmt_pinctrl_remove(struct platform_device *pdev) +{ + struct wmt_pinctrl_data *data = platform_get_drvdata(pdev); + int err; + + err = gpiochip_remove(&data->gpio_chip); + if (err) + dev_err(&pdev->dev, "failed to remove gpio chip\n"); + + pinctrl_unregister(data->pctl_dev); + + return 0; +} diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.h b/drivers/pinctrl/vt8500/pinctrl-wmt.h new file mode 100644 index 00000000000..41f5f2deb5d --- /dev/null +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.h @@ -0,0 +1,79 @@ +/* + * Pinctrl driver for the Wondermedia SoC's + * + * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/gpio.h> + +/* VT8500 has no enable register in the extgpio bank. */ +#define NO_REG 0xFFFF + +#define WMT_PINCTRL_BANK(__en, __dir, __dout, __din, __pen, __pcfg) \ +{ \ + .reg_en = __en, \ + .reg_dir = __dir, \ + .reg_data_out = __dout, \ + .reg_data_in = __din, \ + .reg_pull_en = __pen, \ + .reg_pull_cfg = __pcfg, \ +} + +/* Encode/decode the bank/bit pairs into a pin value */ +#define WMT_PIN(__bank, __offset) ((__bank << 5) | __offset) +#define WMT_BANK_FROM_PIN(__pin) (__pin >> 5) +#define WMT_BIT_FROM_PIN(__pin) (__pin & 0x1f) + +#define WMT_GROUP(__name, __data) \ +{ \ + .name = __name, \ + .pins = __data, \ + .npins = ARRAY_SIZE(__data), \ +} + +struct wmt_pinctrl_bank_registers { + u32 reg_en; + u32 reg_dir; + u32 reg_data_out; + u32 reg_data_in; + + u32 reg_pull_en; + u32 reg_pull_cfg; +}; + +struct wmt_pinctrl_group { + const char *name; + const unsigned int *pins; + const unsigned npins; +}; + +struct wmt_pinctrl_data { + struct device *dev; + struct pinctrl_dev *pctl_dev; + + /* must be initialized before calling wmt_pinctrl_probe */ + void __iomem *base; + const struct wmt_pinctrl_bank_registers *banks; + const struct pinctrl_pin_desc *pins; + const char * const *groups; + + u32 nbanks; + u32 npins; + u32 ngroups; + + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range gpio_range; +}; + +int wmt_pinctrl_probe(struct platform_device *pdev, + struct wmt_pinctrl_data *data); +int wmt_pinctrl_remove(struct platform_device *pdev); |