diff options
Diffstat (limited to 'drivers/pinctrl')
32 files changed, 2695 insertions, 382 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index a84334a2223..0042ccb46b9 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -188,6 +188,13 @@ config PINCTRL_IMX6SL help Say Y here to enable the imx6sl pinctrl driver +config PINCTRL_IMX6SX + bool "IMX6SX pinctrl driver" + depends on SOC_IMX6SX + select PINCTRL_IMX + help + Say Y here to enable the imx6sx pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 @@ -224,6 +231,7 @@ config PINCTRL_MSM select PINMUX select PINCONF select GENERIC_PINCONF + select GPIOLIB_IRQCHIP config PINCTRL_APQ8064 tristate "Qualcomm APQ8064 pin controller driver" @@ -385,6 +393,7 @@ config PINCTRL_S3C64XX depends on ARCH_S3C64XX select PINCTRL_SAMSUNG +source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index c2621438785..c4b5d405b8f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o +obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o @@ -69,6 +70,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o +obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_PLAT_ORION) += mvebu/ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ obj-$(CONFIG_SUPERH) += sh-pfc/ diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig new file mode 100644 index 00000000000..b18322bc7bf --- /dev/null +++ b/drivers/pinctrl/berlin/Kconfig @@ -0,0 +1,20 @@ +if ARCH_BERLIN + +config PINCTRL_BERLIN + bool + select PINMUX + select REGMAP_MMIO + +config PINCTRL_BERLIN_BG2 + bool + select PINCTRL_BERLIN + +config PINCTRL_BERLIN_BG2CD + bool + select PINCTRL_BERLIN + +config PINCTRL_BERLIN_BG2Q + bool + select PINCTRL_BERLIN + +endif diff --git a/drivers/pinctrl/berlin/Makefile b/drivers/pinctrl/berlin/Makefile new file mode 100644 index 00000000000..deb0c6baf31 --- /dev/null +++ b/drivers/pinctrl/berlin/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_PINCTRL_BERLIN) += berlin.o +obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o +obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o +obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o diff --git a/drivers/pinctrl/berlin/berlin-bg2.c b/drivers/pinctrl/berlin/berlin-bg2.c new file mode 100644 index 00000000000..dcd4f6a4fc5 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin-bg2.c @@ -0,0 +1,274 @@ +/* + * Marvell Berlin BG2 pinctrl driver. + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "berlin.h" + +static const struct berlin_desc_group berlin2_soc_pinctrl_groups[] = { + /* G */ + BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "usb1")), + BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s0")), + BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "soc"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s1")), + BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "pwm")), + BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + /* + * Mode 0x3 mux i2s2 mclk *and* i2s3 mclk: + * add two functions so it can be used with other groups + * within the same subnode in the device tree + */ + BERLIN_PINCTRL_FUNCTION(0x3, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s3")), + BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x2, "et")), + BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + BERLIN_PINCTRL_FUNCTION(0x3, "vdac")), + BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "sata_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "sata_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16, + BERLIN_PINCTRL_FUNCTION(0x0, "soc"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi0"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "ptp")), + BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "soc"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "eddc")), + BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a, + BERLIN_PINCTRL_FUNCTION(0x0, "sts2"), + BERLIN_PINCTRL_FUNCTION(0x1, "sata"), + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), + BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sata"), + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), + BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "et"), + BERLIN_PINCTRL_FUNCTION(0x3, "osco")), + BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp")), + BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp")), + BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "pll"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s0")), + BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d, + BERLIN_PINCTRL_FUNCTION(0x0, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), + BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION(0x0, "spdif"), + BERLIN_PINCTRL_FUNCTION(0x1, "arc")), + BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "adac_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "pdm_a"), /* gpio17..19,pdm */ + BERLIN_PINCTRL_FUNCTION(0x7, "pdm_b")), /* gpio12..14,pdm */ + BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "twsi0"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), + BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "vclki"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x7, "pdm")), + BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1")), + BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "nand"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s2")), + BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), + BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "nand")), + BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e, + BERLIN_PINCTRL_FUNCTION(0x0, "dvo"), + BERLIN_PINCTRL_FUNCTION(0x2, "sp")), +}; + +static const struct berlin_desc_group berlin2_sysmgr_pinctrl_groups[] = { + /* GSM */ + BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), + BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), + BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "twsi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), + BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */ + BERLIN_PINCTRL_FUNCTION(0x2, "uart2"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x3, "twsi2")), + BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x1, "irda0")), + BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x2, "irda1"), + BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")), + BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "clki")), + BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x10, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), + BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x11, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), + BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), +}; + +static const struct berlin_pinctrl_desc berlin2_soc_pinctrl_data = { + .groups = berlin2_soc_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2_soc_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin2_sysmgr_pinctrl_data = { + .groups = berlin2_sysmgr_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2_sysmgr_pinctrl_groups), +}; + +static const struct of_device_id berlin2_pinctrl_match[] = { + { + .compatible = "marvell,berlin2-chip-ctrl", + .data = &berlin2_soc_pinctrl_data + }, + { + .compatible = "marvell,berlin2-system-ctrl", + .data = &berlin2_sysmgr_pinctrl_data + }, + {} +}; +MODULE_DEVICE_TABLE(of, berlin2_pinctrl_match); + +static int berlin2_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match = + of_match_device(berlin2_pinctrl_match, &pdev->dev); + struct regmap_config *rmconfig; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); + if (!rmconfig) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rmconfig->reg_bits = 32, + rmconfig->val_bits = 32, + rmconfig->reg_stride = 4, + rmconfig->max_register = resource_size(res); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe(pdev, match->data); +} + +static struct platform_driver berlin2_pinctrl_driver = { + .probe = berlin2_pinctrl_probe, + .driver = { + .name = "berlin-bg2-pinctrl", + .owner = THIS_MODULE, + .of_match_table = berlin2_pinctrl_match, + }, +}; +module_platform_driver(berlin2_pinctrl_driver); + +MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Berlin BG2 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c new file mode 100644 index 00000000000..89d585ef7da --- /dev/null +++ b/drivers/pinctrl/berlin/berlin-bg2cd.c @@ -0,0 +1,217 @@ +/* + * Marvell Berlin BG2CD pinctrl driver. + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "berlin.h" + +static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { + /* G */ + BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "led"), + BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), + BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fe"), + BERLIN_PINCTRL_FUNCTION(0x3, "pll"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "twsi2"), + BERLIN_PINCTRL_FUNCTION(0x3, "pll"), + BERLIN_PINCTRL_FUNCTION(0x4, "fe"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), + BERLIN_PINCTRL_FUNCTION(0x3, "pll"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), + BERLIN_PINCTRL_FUNCTION(0x3, "arc"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d, + BERLIN_PINCTRL_FUNCTION(0x0, "eddc"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10, + BERLIN_PINCTRL_FUNCTION(0x0, "ss0"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "twsi0")), + BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a, + BERLIN_PINCTRL_FUNCTION(0x0, "usb1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x1, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x2, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), +}; + +static const struct berlin_desc_group berlin2cd_sysmgr_pinctrl_groups[] = { + /* GSM */ + BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0f, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x10, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x11, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x12, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), +}; + +static const struct berlin_pinctrl_desc berlin2cd_soc_pinctrl_data = { + .groups = berlin2cd_soc_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2cd_soc_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin2cd_sysmgr_pinctrl_data = { + .groups = berlin2cd_sysmgr_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2cd_sysmgr_pinctrl_groups), +}; + +static const struct of_device_id berlin2cd_pinctrl_match[] = { + { + .compatible = "marvell,berlin2cd-chip-ctrl", + .data = &berlin2cd_soc_pinctrl_data + }, + { + .compatible = "marvell,berlin2cd-system-ctrl", + .data = &berlin2cd_sysmgr_pinctrl_data + }, + {} +}; +MODULE_DEVICE_TABLE(of, berlin2cd_pinctrl_match); + +static int berlin2cd_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match = + of_match_device(berlin2cd_pinctrl_match, &pdev->dev); + struct regmap_config *rmconfig; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); + if (!rmconfig) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rmconfig->reg_bits = 32, + rmconfig->val_bits = 32, + rmconfig->reg_stride = 4, + rmconfig->max_register = resource_size(res); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe(pdev, match->data); +} + +static struct platform_driver berlin2cd_pinctrl_driver = { + .probe = berlin2cd_pinctrl_probe, + .driver = { + .name = "berlin-bg2cd-pinctrl", + .owner = THIS_MODULE, + .of_match_table = berlin2cd_pinctrl_match, + }, +}; +module_platform_driver(berlin2cd_pinctrl_driver); + +MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Berlin BG2CD pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin-bg2q.c b/drivers/pinctrl/berlin/berlin-bg2q.c new file mode 100644 index 00000000000..9fcf9836045 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin-bg2q.c @@ -0,0 +1,436 @@ +/* + * Marvell Berlin BG2Q pinctrl driver + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "berlin.h" + +static const struct berlin_desc_group berlin2q_soc_pinctrl_groups[] = { + /* G */ + BERLIN_PINCTRL_GROUP("G0", 0x18, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x1, "mmc"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G1", 0x18, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G2", 0x18, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "arc"), + BERLIN_PINCTRL_FUNCTION(0x3, "lvds")), + BERLIN_PINCTRL_GROUP("G3", 0x18, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x3, "lvds")), + BERLIN_PINCTRL_GROUP("G4", 0x18, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "pll"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata_dbg"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G5", 0x18, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata_dbg"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G6", 0x18, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi0"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G7", 0x18, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "eddc")), + BERLIN_PINCTRL_GROUP("G8", 0x18, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G9", 0x18, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata")), + BERLIN_PINCTRL_GROUP("G10", 0x1c, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata")), + BERLIN_PINCTRL_GROUP("G11", 0x1c, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x5, "sata")), + BERLIN_PINCTRL_GROUP("G12", 0x1c, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "agc"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), + BERLIN_PINCTRL_GROUP("G13", 0x1c, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G14", 0x1c, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G15", 0x1c, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x5, "vdac"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G16", 0x1c, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x5, "osco"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G17", 0x1c, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x3, "spdif"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), + BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), + BERLIN_PINCTRL_GROUP("G18", 0x1c, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1")), + BERLIN_PINCTRL_GROUP("G19", 0x1c, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x4, "sts1"), + BERLIN_PINCTRL_FUNCTION(0x5, "osco")), + BERLIN_PINCTRL_GROUP("G20", 0x20, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "demod"), + /* + * Mode 0x4 mux usb2_dbg *and* usb3_dbg: + * add two functions so it can be used with other groups + * within the same subnode in the device tree + */ + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb3_dbg")), + BERLIN_PINCTRL_GROUP("G21", 0x20, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "sts2"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "demod")), + BERLIN_PINCTRL_GROUP("G22", 0x20, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G23", 0x20, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "avif"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")), + BERLIN_PINCTRL_GROUP("G24", 0x20, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "demod"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")), + BERLIN_PINCTRL_GROUP("G25", 0x20, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "vga"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "avif"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")), + BERLIN_PINCTRL_GROUP("G26", 0x20, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "lvds"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G27", 0x20, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "agc"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G28", 0x20, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x3, "avif"), + BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")), + BERLIN_PINCTRL_GROUP("G29", 0x20, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G30", 0x24, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "scrd1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G31", 0x24, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("G32", 0x24, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "cam"), + BERLIN_PINCTRL_FUNCTION(0x1, "sd1"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + /* GAV */ + BERLIN_PINCTRL_GROUP("GAV0", 0x24, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "lvds")), + BERLIN_PINCTRL_GROUP("GAV1", 0x24, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "vga")), + BERLIN_PINCTRL_GROUP("GAV2", 0x24, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x4, "pdm"), + BERLIN_PINCTRL_FUNCTION(0x6, "adac")), + BERLIN_PINCTRL_GROUP("GAV3", 0x24, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x6, "adac")), + BERLIN_PINCTRL_GROUP("GAV4", 0x24, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x6, "adac")), + BERLIN_PINCTRL_GROUP("GAV5", 0x24, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "spdif")), + BERLIN_PINCTRL_GROUP("GAV6", 0x24, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s2")), + BERLIN_PINCTRL_GROUP("GAV7", 0x28, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dvio"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s3")), + BERLIN_PINCTRL_GROUP("GAV8", 0x28, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), + BERLIN_PINCTRL_GROUP("GAV9", 0x28, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), + BERLIN_PINCTRL_GROUP("GAV10", 0x28, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x4, "agc")), + BERLIN_PINCTRL_GROUP("GAV11", 0x28, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "dv0"), + BERLIN_PINCTRL_FUNCTION(0x2, "fp"), + BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x5, "vclki")), + BERLIN_PINCTRL_GROUP("GAV12", 0x28, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")), + BERLIN_PINCTRL_GROUP("GAV13", 0x28, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2")), + BERLIN_PINCTRL_GROUP("GAV14", 0x28, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")), + BERLIN_PINCTRL_GROUP("GAV15", 0x28, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")), + BERLIN_PINCTRL_GROUP("GAV16", 0x28, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), + BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")), + BERLIN_PINCTRL_GROUP("GAV17", 0x2c, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "i2s0"), + BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"), + BERLIN_PINCTRL_FUNCTION(0x3, "pwm"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), + BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")), + BERLIN_PINCTRL_GROUP("GAV18", 0x2c, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spdif"), + BERLIN_PINCTRL_FUNCTION(0x2, "arc")), + BERLIN_PINCTRL_GROUP("GAV19", 0x2c, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "avio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spdif"), + BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"), + BERLIN_PINCTRL_FUNCTION(0x5, "pdm")), +}; + +static const struct berlin_desc_group berlin2q_sysmgr_pinctrl_groups[] = { + /* GSM */ + BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), + BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), + BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eddc")), + BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x2, "eddc")), + BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x1, 0x08, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x1, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x1, 0x0a, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x0d, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), + BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x0e, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), + BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "led")), + BERLIN_PINCTRL_GROUP("GSM12", 0x40, 0x2, 0x10, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x1, "irda0"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("GSM13", 0x40, 0x2, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */ + BERLIN_PINCTRL_FUNCTION(0x2, "uart1"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x3, "twsi2")), + BERLIN_PINCTRL_GROUP("GSM14", 0x40, 0x2, 0x14, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RX/TX */ + BERLIN_PINCTRL_FUNCTION(0x2, "irda1"), + BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")), + BERLIN_PINCTRL_GROUP("GSM15", 0x40, 0x2, 0x16, + BERLIN_PINCTRL_FUNCTION(0x0, "pwr"), + BERLIN_PINCTRL_FUNCTION(0x1, "led"), + BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), + BERLIN_PINCTRL_GROUP("GSM16", 0x40, 0x1, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "eddc")), + BERLIN_PINCTRL_GROUP("GSM17", 0x40, 0x1, 0x19, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "eddc")), + BERLIN_PINCTRL_GROUP("GSM18", 0x40, 0x1, 0x1a, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), + BERLIN_PINCTRL_FUNCTION(0x1, "eddc")), +}; + +static const struct berlin_pinctrl_desc berlin2q_soc_pinctrl_data = { + .groups = berlin2q_soc_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2q_soc_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin2q_sysmgr_pinctrl_data = { + .groups = berlin2q_sysmgr_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin2q_sysmgr_pinctrl_groups), +}; + +static const struct of_device_id berlin2q_pinctrl_match[] = { + { + .compatible = "marvell,berlin2q-chip-ctrl", + .data = &berlin2q_soc_pinctrl_data, + }, + { + .compatible = "marvell,berlin2q-system-ctrl", + .data = &berlin2q_sysmgr_pinctrl_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, berlin2q_pinctrl_match); + +static int berlin2q_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match = + of_match_device(berlin2q_pinctrl_match, &pdev->dev); + struct regmap_config *rmconfig; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); + if (!rmconfig) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rmconfig->reg_bits = 32, + rmconfig->val_bits = 32, + rmconfig->reg_stride = 4, + rmconfig->max_register = resource_size(res); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe(pdev, match->data); +} + +static struct platform_driver berlin2q_pinctrl_driver = { + .probe = berlin2q_pinctrl_probe, + .driver = { + .name = "berlin-bg2q-pinctrl", + .owner = THIS_MODULE, + .of_match_table = berlin2q_pinctrl_match, + }, +}; +module_platform_driver(berlin2q_pinctrl_driver); + +MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Berlin BG2Q pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c new file mode 100644 index 00000000000..86db2235ab0 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin.c @@ -0,0 +1,348 @@ +/* + * Marvell Berlin SoC pinctrl core driver + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "berlin.h" + +struct berlin_pinctrl { + struct regmap *regmap; + struct device *dev; + const struct berlin_pinctrl_desc *desc; + struct berlin_pinctrl_function *functions; + unsigned nfunctions; + struct pinctrl_dev *pctrl_dev; +}; + +static int berlin_pinctrl_get_group_count(struct pinctrl_dev *pctrl_dev) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pctrl->desc->ngroups; +} + +static const char *berlin_pinctrl_get_group_name(struct pinctrl_dev *pctrl_dev, + unsigned group) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pctrl->desc->groups[group].name; +} + +static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + struct property *prop; + const char *function_name, *group_name; + unsigned reserved_maps = 0; + int ret, ngroups; + + *map = NULL; + *num_maps = 0; + + ret = of_property_read_string(node, "function", &function_name); + if (ret) { + dev_err(pctrl->dev, + "missing function property in node %s\n", + node->name); + return -EINVAL; + } + + ngroups = of_property_count_strings(node, "groups"); + if (ngroups < 0) { + dev_err(pctrl->dev, + "missing groups property in node %s\n", + node->name); + return -EINVAL; + } + + ret = pinctrl_utils_reserve_map(pctrl_dev, map, &reserved_maps, + num_maps, ngroups); + if (ret) { + dev_err(pctrl->dev, "can't reserve map: %d\n", ret); + return ret; + } + + of_property_for_each_string(node, "groups", prop, group_name) { + ret = pinctrl_utils_add_map_mux(pctrl_dev, map, &reserved_maps, + num_maps, group_name, + function_name); + if (ret) { + dev_err(pctrl->dev, "can't add map: %d\n", ret); + return ret; + } + } + + return 0; +} + +static void berlin_pinctrl_dt_free_map(struct pinctrl_dev *pctrl_dev, + struct pinctrl_map *map, + unsigned nmaps) +{ + int i; + + for (i = 0; i < nmaps; i++) { + if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) { + kfree(map[i].data.mux.group); + + /* a function can be applied to multiple groups */ + if (i == 0) + kfree(map[i].data.mux.function); + } + } + + kfree(map); +} + +static const struct pinctrl_ops berlin_pinctrl_ops = { + .get_groups_count = &berlin_pinctrl_get_group_count, + .get_group_name = &berlin_pinctrl_get_group_name, + .dt_node_to_map = &berlin_pinctrl_dt_node_to_map, + .dt_free_map = &berlin_pinctrl_dt_free_map, +}; + +static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pctrl->nfunctions; +} + +static const char *berlin_pinmux_get_function_name(struct pinctrl_dev *pctrl_dev, + unsigned function) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + return pctrl->functions[function].name; +} + +static int berlin_pinmux_get_function_groups(struct pinctrl_dev *pctrl_dev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + + *groups = pctrl->functions[function].groups; + *num_groups = pctrl->functions[function].ngroups; + + return 0; +} + +static struct berlin_desc_function * +berlin_pinctrl_find_function_by_name(struct berlin_pinctrl *pctrl, + const struct berlin_desc_group *group, + const char *fname) +{ + struct berlin_desc_function *function = group->functions; + + while (function->name) { + if (!strcmp(function->name, fname)) + return function; + + function++; + } + + return NULL; +} + +static int berlin_pinmux_enable(struct pinctrl_dev *pctrl_dev, + unsigned function, + unsigned group) +{ + struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); + const struct berlin_desc_group *group_desc = pctrl->desc->groups + group; + struct berlin_pinctrl_function *func = pctrl->functions + function; + struct berlin_desc_function *function_desc = + berlin_pinctrl_find_function_by_name(pctrl, group_desc, + func->name); + u32 mask, val; + + if (!function_desc) + return -EINVAL; + + mask = GENMASK(group_desc->lsb + group_desc->bit_width - 1, + group_desc->lsb); + val = function_desc->muxval << group_desc->lsb; + regmap_update_bits(pctrl->regmap, group_desc->offset, mask, val); + + return 0; +} + +static const struct pinmux_ops berlin_pinmux_ops = { + .get_functions_count = &berlin_pinmux_get_functions_count, + .get_function_name = &berlin_pinmux_get_function_name, + .get_function_groups = &berlin_pinmux_get_function_groups, + .enable = &berlin_pinmux_enable, +}; + +static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl, + const char *name) +{ + struct berlin_pinctrl_function *function = pctrl->functions; + + while (function->name) { + if (!strcmp(function->name, name)) { + function->ngroups++; + return -EEXIST; + } + function++; + } + + function->name = name; + function->ngroups = 1; + + pctrl->nfunctions++; + + return 0; +} + +static int berlin_pinctrl_build_state(struct platform_device *pdev) +{ + struct berlin_pinctrl *pctrl = platform_get_drvdata(pdev); + struct berlin_desc_group const *desc_group; + struct berlin_desc_function const *desc_function; + int i, max_functions = 0; + + pctrl->nfunctions = 0; + + for (i = 0; i < pctrl->desc->ngroups; i++) { + desc_group = pctrl->desc->groups + i; + /* compute the maxiumum number of functions a group can have */ + max_functions += 1 << (desc_group->bit_width + 1); + } + + /* we will reallocate later */ + pctrl->functions = devm_kzalloc(&pdev->dev, + max_functions * sizeof(*pctrl->functions), + GFP_KERNEL); + if (!pctrl->functions) + return -ENOMEM; + + /* register all functions */ + for (i = 0; i < pctrl->desc->ngroups; i++) { + desc_group = pctrl->desc->groups + i; + desc_function = desc_group->functions; + + while (desc_function->name) { + berlin_pinctrl_add_function(pctrl, desc_function->name); + desc_function++; + } + } + + pctrl->functions = krealloc(pctrl->functions, + pctrl->nfunctions * sizeof(*pctrl->functions), + GFP_KERNEL); + + /* map functions to theirs groups */ + for (i = 0; i < pctrl->desc->ngroups; i++) { + desc_group = pctrl->desc->groups + i; + desc_function = desc_group->functions; + + while (desc_function->name) { + struct berlin_pinctrl_function + *function = pctrl->functions; + const char **groups; + bool found = false; + + while (function->name) { + if (!strcmp(desc_function->name, function->name)) { + found = true; + break; + } + function++; + } + + if (!found) + return -EINVAL; + + if (!function->groups) { + function->groups = + devm_kzalloc(&pdev->dev, + function->ngroups * sizeof(char *), + GFP_KERNEL); + + if (!function->groups) + return -ENOMEM; + } + + groups = function->groups; + while (*groups) + groups++; + + *groups = desc_group->name; + + desc_function++; + } + } + + return 0; +} + +static struct pinctrl_desc berlin_pctrl_desc = { + .name = "berlin-pinctrl", + .pctlops = &berlin_pinctrl_ops, + .pmxops = &berlin_pinmux_ops, + .owner = THIS_MODULE, +}; + +int berlin_pinctrl_probe(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc) +{ + struct device *dev = &pdev->dev; + struct berlin_pinctrl *pctrl; + struct regmap *regmap; + int ret; + + regmap = dev_get_regmap(&pdev->dev, NULL); + if (!regmap) + return -ENODEV; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctrl); + + pctrl->regmap = regmap; + pctrl->dev = &pdev->dev; + pctrl->desc = desc; + + ret = berlin_pinctrl_build_state(pdev); + if (ret) { + dev_err(dev, "cannot build driver state: %d\n", ret); + return ret; + } + + pctrl->pctrl_dev = pinctrl_register(&berlin_pctrl_desc, dev, pctrl); + if (!pctrl->pctrl_dev) { + dev_err(dev, "failed to register pinctrl driver\n"); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h new file mode 100644 index 00000000000..e1aa8414519 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin.h @@ -0,0 +1,61 @@ +/* + * Marvell Berlin SoC pinctrl driver. + * + * Copyright (C) 2014 Marvell Technology Group Ltd. + * + * Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PINCTRL_BERLIN_H +#define __PINCTRL_BERLIN_H + +struct berlin_desc_function { + const char *name; + u8 muxval; +}; + +struct berlin_desc_group { + const char *name; + u8 offset; + u8 bit_width; + u8 lsb; + struct berlin_desc_function *functions; +}; + +struct berlin_pinctrl_desc { + const struct berlin_desc_group *groups; + unsigned ngroups; +}; + +struct berlin_pinctrl_function { + const char *name; + const char **groups; + unsigned ngroups; +}; + +#define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ + { \ + .name = _name, \ + .offset = _offset, \ + .bit_width = _width, \ + .lsb = _lsb, \ + .functions = (struct berlin_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define BERLIN_PINCTRL_FUNCTION(_muxval, _name) \ + { \ + .name = _name, \ + .muxval = _muxval, \ + } + +#define BERLIN_PINCTRL_FUNCTION_UNKNOWN {} + +int berlin_pinctrl_probe(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc); + +#endif /* __PINCTRL_BERLIN_H */ diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 3d9a999fb69..29ff77f90fc 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -166,6 +166,7 @@ static struct pinconf_generic_dt_params dt_params[] = { { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, { "output-low", PIN_CONFIG_OUTPUT, 0, }, @@ -228,13 +229,12 @@ int pinconf_generic_parse_dt_config(struct device_node *np, * Now limit the number of configs to the real number of * found properties. */ - *configs = kzalloc(ncfg * sizeof(unsigned long), GFP_KERNEL); + *configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL); if (!*configs) { ret = -ENOMEM; goto out; } - memcpy(*configs, cfg, ncfg * sizeof(unsigned long)); *nconfigs = ncfg; out: diff --git a/drivers/pinctrl/pinctrl-apq8064.c b/drivers/pinctrl/pinctrl-apq8064.c index 7c2a8baaea8..519f7886b0f 100644 --- a/drivers/pinctrl/pinctrl-apq8064.c +++ b/drivers/pinctrl/pinctrl-apq8064.c @@ -109,6 +109,13 @@ static const struct pinctrl_pin_desc apq8064_pins[] = { PINCTRL_PIN(87, "GPIO_87"), PINCTRL_PIN(88, "GPIO_88"), PINCTRL_PIN(89, "GPIO_89"), + + PINCTRL_PIN(90, "SDC1_CLK"), + PINCTRL_PIN(91, "SDC1_CMD"), + PINCTRL_PIN(92, "SDC1_DATA"), + PINCTRL_PIN(93, "SDC3_CLK"), + PINCTRL_PIN(94, "SDC3_CMD"), + PINCTRL_PIN(95, "SDC3_DATA"), }; #define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } @@ -203,6 +210,13 @@ DECLARE_APQ_GPIO_PINS(87); DECLARE_APQ_GPIO_PINS(88); DECLARE_APQ_GPIO_PINS(89); +static const unsigned int sdc1_clk_pins[] = { 90 }; +static const unsigned int sdc1_cmd_pins[] = { 91 }; +static const unsigned int sdc1_data_pins[] = { 92 }; +static const unsigned int sdc3_clk_pins[] = { 93 }; +static const unsigned int sdc3_cmd_pins[] = { 94 }; +static const unsigned int sdc3_data_pins[] = { 95 }; + #define FUNCTION(fname) \ [APQ_MUX_##fname] = { \ .name = #fname, \ @@ -250,6 +264,31 @@ DECLARE_APQ_GPIO_PINS(89); .intr_detection_width = 1, \ } +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + enum apq8064_functions { APQ_MUX_cam_mclk, APQ_MUX_codec_mic_i2s, @@ -514,6 +553,14 @@ static const struct msm_pingroup apq8064_groups[] = { PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(88, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(89, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), }; #define NUM_GPIO_PINGROUPS 90 diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c index 92ed4b2e3c0..c862f9c0e9c 100644 --- a/drivers/pinctrl/pinctrl-as3722.c +++ b/drivers/pinctrl/pinctrl-as3722.c @@ -64,7 +64,6 @@ struct as3722_pin_function { }; struct as3722_gpio_pin_control { - bool enable_gpio_invert; unsigned mode_prop; int io_function; }; @@ -320,10 +319,8 @@ static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev, return mode; } - if (as_pci->gpio_control[offset].enable_gpio_invert) - mode |= AS3722_GPIO_INV; - - return as3722_write(as3722, AS3722_GPIOn_CONTROL_REG(offset), mode); + return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset), + AS3722_GPIO_MODE_MASK, mode); } static const struct pinmux_ops as3722_pinmux_ops = { @@ -496,10 +493,18 @@ static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset, { struct as3722_pctrl_info *as_pci = to_as_pci(chip); struct as3722 *as3722 = as_pci->as3722; - int en_invert = as_pci->gpio_control[offset].enable_gpio_invert; + int en_invert; u32 val; int ret; + ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val); + if (ret < 0) { + dev_err(as_pci->dev, + "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret); + return; + } + en_invert = !!(val & AS3722_GPIO_INV); + if (value) val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset); else diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 84a9594a0ca..421493cb490 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1453,6 +1453,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) break; at91_gpio = at91_gpio->next; pio = at91_gpio->regbase; + gpio_chip = &at91_gpio->chip; continue; } @@ -1468,6 +1469,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) static int at91_gpio_of_irq_setup(struct device_node *node, struct at91_gpio_chip *at91_gpio) { + struct at91_gpio_chip *prev = NULL; struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); int ret; @@ -1493,6 +1495,17 @@ static int at91_gpio_of_irq_setup(struct device_node *node, panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", at91_gpio->pioc_idx); + /* Setup chained handler */ + if (at91_gpio->pioc_idx) + prev = gpio_chips[at91_gpio->pioc_idx - 1]; + + /* The top level handler handles one bank of GPIOs, except + * on some SoC it can handle up to three... + * We only set up the handler for the first of the list. + */ + if (prev && prev->next == at91_gpio) + return 0; + /* Then register the chain on the parent IRQ */ gpiochip_set_chained_irqchip(&at91_gpio->chip, &gpio_irqchip, diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c index 6e8301f7718..975572e2f26 100644 --- a/drivers/pinctrl/pinctrl-baytrail.c +++ b/drivers/pinctrl/pinctrl-baytrail.c @@ -43,9 +43,20 @@ #define BYT_INT_STAT_REG 0x800 /* BYT_CONF0_REG register bits */ +#define BYT_IODEN BIT(31) #define BYT_TRIG_NEG BIT(26) #define BYT_TRIG_POS BIT(25) #define BYT_TRIG_LVL BIT(24) +#define BYT_PULL_STR_SHIFT 9 +#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) +#define BYT_PULL_ASSIGN_SHIFT 7 +#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT) +#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) +#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) #define BYT_PIN_MUX 0x07 /* BYT_VAL_REG register bits */ @@ -321,6 +332,8 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) spin_lock_irqsave(&vg->lock, flags); for (i = 0; i < vg->chip.ngpio; i++) { + const char *pull_str = NULL; + const char *pull = NULL; const char *label; offs = vg->range->pins[i] * 16; conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); @@ -330,8 +343,32 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) if (!label) label = "Unrequested"; + switch (conf0 & BYT_PULL_ASSIGN_MASK) { + case BYT_PULL_ASSIGN_UP: + pull = "up"; + break; + case BYT_PULL_ASSIGN_DOWN: + pull = "down"; + break; + } + + switch (conf0 & BYT_PULL_STR_MASK) { + case BYT_PULL_STR_2K: + pull_str = "2k"; + break; + case BYT_PULL_STR_10K: + pull_str = "10k"; + break; + case BYT_PULL_STR_20K: + pull_str = "20k"; + break; + case BYT_PULL_STR_40K: + pull_str = "40k"; + break; + } + seq_printf(s, - " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n", + " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", i, label, val & BYT_INPUT_EN ? " " : "in", @@ -339,9 +376,19 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) val & BYT_LEVEL ? "hi" : "lo", vg->range->pins[i], offs, conf0 & 0x7, - conf0 & BYT_TRIG_NEG ? " fall" : "", - conf0 & BYT_TRIG_POS ? " rise" : "", - conf0 & BYT_TRIG_LVL ? " level" : ""); + conf0 & BYT_TRIG_NEG ? " fall" : " ", + conf0 & BYT_TRIG_POS ? " rise" : " ", + conf0 & BYT_TRIG_LVL ? " level" : " "); + + if (pull && pull_str) + seq_printf(s, " %-4s %-3s", pull, pull_str); + else + seq_puts(s, " "); + + if (conf0 & BYT_IODEN) + seq_puts(s, " open-drain"); + + seq_puts(s, "\n"); } spin_unlock_irqrestore(&vg->lock, flags); } @@ -527,12 +574,6 @@ static int byt_gpio_probe(struct platform_device *pdev) gc->can_sleep = false; gc->dev = dev; - ret = gpiochip_add(gc); - if (ret) { - dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); - return ret; - } - /* set up interrupts */ irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (irq_rc && irq_rc->start) { @@ -550,6 +591,12 @@ static int byt_gpio_probe(struct platform_device *pdev) irq_set_chained_handler(hwirq, byt_gpio_irq_handler); } + ret = gpiochip_add(gc); + if (ret) { + dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); + return ret; + } + pm_runtime_enable(dev); return 0; @@ -572,6 +619,7 @@ static const struct dev_pm_ops byt_gpio_pm_ops = { static const struct acpi_device_id byt_gpio_acpi_match[] = { { "INT33B2", 0 }, + { "INT33FC", 0 }, { } }; MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); diff --git a/drivers/pinctrl/pinctrl-imx6sx.c b/drivers/pinctrl/pinctrl-imx6sx.c new file mode 100644 index 00000000000..09758a56b9d --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx6sx.c @@ -0,0 +1,407 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum imx6sx_pads { + MX6Sx_PAD_RESERVE0 = 0, + MX6Sx_PAD_RESERVE1 = 1, + MX6Sx_PAD_RESERVE2 = 2, + MX6Sx_PAD_RESERVE3 = 3, + MX6Sx_PAD_RESERVE4 = 4, + MX6SX_PAD_GPIO1_IO00 = 5, + MX6SX_PAD_GPIO1_IO01 = 6, + MX6SX_PAD_GPIO1_IO02 = 7, + MX6SX_PAD_GPIO1_IO03 = 8, + MX6SX_PAD_GPIO1_IO04 = 9, + MX6SX_PAD_GPIO1_IO05 = 10, + MX6SX_PAD_GPIO1_IO06 = 11, + MX6SX_PAD_GPIO1_IO07 = 12, + MX6SX_PAD_GPIO1_IO08 = 13, + MX6SX_PAD_GPIO1_IO09 = 14, + MX6SX_PAD_GPIO1_IO10 = 15, + MX6SX_PAD_GPIO1_IO11 = 16, + MX6SX_PAD_GPIO1_IO12 = 17, + MX6SX_PAD_GPIO1_IO13 = 18, + MX6SX_PAD_CSI_DATA00 = 19, + MX6SX_PAD_CSI_DATA01 = 20, + MX6SX_PAD_CSI_DATA02 = 21, + MX6SX_PAD_CSI_DATA03 = 22, + MX6SX_PAD_CSI_DATA04 = 23, + MX6SX_PAD_CSI_DATA05 = 24, + MX6SX_PAD_CSI_DATA06 = 25, + MX6SX_PAD_CSI_DATA07 = 26, + MX6SX_PAD_CSI_HSYNC = 27, + MX6SX_PAD_CSI_MCLK = 28, + MX6SX_PAD_CSI_PIXCLK = 29, + MX6SX_PAD_CSI_VSYNC = 30, + MX6SX_PAD_ENET1_COL = 31, + MX6SX_PAD_ENET1_CRS = 32, + MX6SX_PAD_ENET1_MDC = 33, + MX6SX_PAD_ENET1_MDIO = 34, + MX6SX_PAD_ENET1_RX_CLK = 35, + MX6SX_PAD_ENET1_TX_CLK = 36, + MX6SX_PAD_ENET2_COL = 37, + MX6SX_PAD_ENET2_CRS = 38, + MX6SX_PAD_ENET2_RX_CLK = 39, + MX6SX_PAD_ENET2_TX_CLK = 40, + MX6SX_PAD_KEY_COL0 = 41, + MX6SX_PAD_KEY_COL1 = 42, + MX6SX_PAD_KEY_COL2 = 43, + MX6SX_PAD_KEY_COL3 = 44, + MX6SX_PAD_KEY_COL4 = 45, + MX6SX_PAD_KEY_ROW0 = 46, + MX6SX_PAD_KEY_ROW1 = 47, + MX6SX_PAD_KEY_ROW2 = 48, + MX6SX_PAD_KEY_ROW3 = 49, + MX6SX_PAD_KEY_ROW4 = 50, + MX6SX_PAD_LCD1_CLK = 51, + MX6SX_PAD_LCD1_DATA00 = 52, + MX6SX_PAD_LCD1_DATA01 = 53, + MX6SX_PAD_LCD1_DATA02 = 54, + MX6SX_PAD_LCD1_DATA03 = 55, + MX6SX_PAD_LCD1_DATA04 = 56, + MX6SX_PAD_LCD1_DATA05 = 57, + MX6SX_PAD_LCD1_DATA06 = 58, + MX6SX_PAD_LCD1_DATA07 = 59, + MX6SX_PAD_LCD1_DATA08 = 60, + MX6SX_PAD_LCD1_DATA09 = 61, + MX6SX_PAD_LCD1_DATA10 = 62, + MX6SX_PAD_LCD1_DATA11 = 63, + MX6SX_PAD_LCD1_DATA12 = 64, + MX6SX_PAD_LCD1_DATA13 = 65, + MX6SX_PAD_LCD1_DATA14 = 66, + MX6SX_PAD_LCD1_DATA15 = 67, + MX6SX_PAD_LCD1_DATA16 = 68, + MX6SX_PAD_LCD1_DATA17 = 69, + MX6SX_PAD_LCD1_DATA18 = 70, + MX6SX_PAD_LCD1_DATA19 = 71, + MX6SX_PAD_LCD1_DATA20 = 72, + MX6SX_PAD_LCD1_DATA21 = 73, + MX6SX_PAD_LCD1_DATA22 = 74, + MX6SX_PAD_LCD1_DATA23 = 75, + MX6SX_PAD_LCD1_ENABLE = 76, + MX6SX_PAD_LCD1_HSYNC = 77, + MX6SX_PAD_LCD1_RESET = 78, + MX6SX_PAD_LCD1_VSYNC = 79, + MX6SX_PAD_NAND_ALE = 80, + MX6SX_PAD_NAND_CE0_B = 81, + MX6SX_PAD_NAND_CE1_B = 82, + MX6SX_PAD_NAND_CLE = 83, + MX6SX_PAD_NAND_DATA00 = 84 , + MX6SX_PAD_NAND_DATA01 = 85, + MX6SX_PAD_NAND_DATA02 = 86, + MX6SX_PAD_NAND_DATA03 = 87, + MX6SX_PAD_NAND_DATA04 = 88, + MX6SX_PAD_NAND_DATA05 = 89, + MX6SX_PAD_NAND_DATA06 = 90, + MX6SX_PAD_NAND_DATA07 = 91, + MX6SX_PAD_NAND_RE_B = 92, + MX6SX_PAD_NAND_READY_B = 93, + MX6SX_PAD_NAND_WE_B = 94, + MX6SX_PAD_NAND_WP_B = 95, + MX6SX_PAD_QSPI1A_DATA0 = 96, + MX6SX_PAD_QSPI1A_DATA1 = 97, + MX6SX_PAD_QSPI1A_DATA2 = 98, + MX6SX_PAD_QSPI1A_DATA3 = 99, + MX6SX_PAD_QSPI1A_DQS = 100, + MX6SX_PAD_QSPI1A_SCLK = 101, + MX6SX_PAD_QSPI1A_SS0_B = 102, + MX6SX_PAD_QSPI1A_SS1_B = 103, + MX6SX_PAD_QSPI1B_DATA0 = 104, + MX6SX_PAD_QSPI1B_DATA1 = 105, + MX6SX_PAD_QSPI1B_DATA2 = 106, + MX6SX_PAD_QSPI1B_DATA3 = 107, + MX6SX_PAD_QSPI1B_DQS = 108, + MX6SX_PAD_QSPI1B_SCLK = 109, + MX6SX_PAD_QSPI1B_SS0_B = 110, + MX6SX_PAD_QSPI1B_SS1_B = 111, + MX6SX_PAD_RGMII1_RD0 = 112, + MX6SX_PAD_RGMII1_RD1 = 113, + MX6SX_PAD_RGMII1_RD2 = 114, + MX6SX_PAD_RGMII1_RD3 = 115, + MX6SX_PAD_RGMII1_RX_CTL = 116, + MX6SX_PAD_RGMII1_RXC = 117, + MX6SX_PAD_RGMII1_TD0 = 118, + MX6SX_PAD_RGMII1_TD1 = 119, + MX6SX_PAD_RGMII1_TD2 = 120, + MX6SX_PAD_RGMII1_TD3 = 121, + MX6SX_PAD_RGMII1_TX_CTL = 122, + MX6SX_PAD_RGMII1_TXC = 123, + MX6SX_PAD_RGMII2_RD0 = 124, + MX6SX_PAD_RGMII2_RD1 = 125, + MX6SX_PAD_RGMII2_RD2 = 126, + MX6SX_PAD_RGMII2_RD3 = 127, + MX6SX_PAD_RGMII2_RX_CTL = 128, + MX6SX_PAD_RGMII2_RXC = 129, + MX6SX_PAD_RGMII2_TD0 = 130, + MX6SX_PAD_RGMII2_TD1 = 131, + MX6SX_PAD_RGMII2_TD2 = 132, + MX6SX_PAD_RGMII2_TD3 = 133, + MX6SX_PAD_RGMII2_TX_CTL = 134, + MX6SX_PAD_RGMII2_TXC = 135, + MX6SX_PAD_SD1_CLK = 136, + MX6SX_PAD_SD1_CMD = 137, + MX6SX_PAD_SD1_DATA0 = 138, + MX6SX_PAD_SD1_DATA1 = 139, + MX6SX_PAD_SD1_DATA2 = 140, + MX6SX_PAD_SD1_DATA3 = 141, + MX6SX_PAD_SD2_CLK = 142, + MX6SX_PAD_SD2_CMD = 143, + MX6SX_PAD_SD2_DATA0 = 144, + MX6SX_PAD_SD2_DATA1 = 145, + MX6SX_PAD_SD2_DATA2 = 146, + MX6SX_PAD_SD2_DATA3 = 147, + MX6SX_PAD_SD3_CLK = 148, + MX6SX_PAD_SD3_CMD = 149, + MX6SX_PAD_SD3_DATA0 = 150, + MX6SX_PAD_SD3_DATA1 = 151, + MX6SX_PAD_SD3_DATA2 = 152, + MX6SX_PAD_SD3_DATA3 = 153, + MX6SX_PAD_SD3_DATA4 = 154, + MX6SX_PAD_SD3_DATA5 = 155, + MX6SX_PAD_SD3_DATA6 = 156, + MX6SX_PAD_SD3_DATA7 = 157, + MX6SX_PAD_SD4_CLK = 158, + MX6SX_PAD_SD4_CMD = 159, + MX6SX_PAD_SD4_DATA0 = 160, + MX6SX_PAD_SD4_DATA1 = 161, + MX6SX_PAD_SD4_DATA2 = 162, + MX6SX_PAD_SD4_DATA3 = 163, + MX6SX_PAD_SD4_DATA4 = 164, + MX6SX_PAD_SD4_DATA5 = 165, + MX6SX_PAD_SD4_DATA6 = 166, + MX6SX_PAD_SD4_DATA7 = 167, + MX6SX_PAD_SD4_RESET_B = 168, + MX6SX_PAD_USB_H_DATA = 169, + MX6SX_PAD_USB_H_STROBE = 170, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12), + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3), + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET), + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B), + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B), + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL), + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6), + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7), + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B), + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA), + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE), +}; + +static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = { + .pins = imx6sx_pinctrl_pads, + .npins = ARRAY_SIZE(imx6sx_pinctrl_pads), +}; + +static struct of_device_id imx6sx_pinctrl_of_match[] = { + { .compatible = "fsl,imx6sx-iomuxc", }, + { /* sentinel */ } +}; + +static int imx6sx_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info); +} + +static struct platform_driver imx6sx_pinctrl_driver = { + .driver = { + .name = "imx6sx-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match), + }, + .probe = imx6sx_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6sx_pinctrl_init(void) +{ + return platform_driver_register(&imx6sx_pinctrl_driver); +} +arch_initcall(imx6sx_pinctrl_init); + +static void __exit imx6sx_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6sx_pinctrl_driver); +} +module_exit(imx6sx_pinctrl_exit); + +MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>"); +MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-ipq8064.c b/drivers/pinctrl/pinctrl-ipq8064.c index 54aba9f1129..acafea4c3a3 100644 --- a/drivers/pinctrl/pinctrl-ipq8064.c +++ b/drivers/pinctrl/pinctrl-ipq8064.c @@ -366,7 +366,7 @@ static const char * const sdc1_groups[] = { }; static const char * const spdif_groups[] = { - "gpio_10", "gpio_48", + "gpio10", "gpio48", }; static const char * const nand_groups[] = { diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c index 5fa9341cc58..df6dda4ce80 100644 --- a/drivers/pinctrl/pinctrl-msm.c +++ b/drivers/pinctrl/pinctrl-msm.c @@ -13,7 +13,6 @@ */ #include <linux/err.h> -#include <linux/irqdomain.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> @@ -26,8 +25,6 @@ #include <linux/slab.h> #include <linux/gpio.h> #include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/irqchip/chained_irq.h> #include <linux/spinlock.h> #include "core.h" @@ -41,7 +38,6 @@ * struct msm_pinctrl - state for a pinctrl-msm device * @dev: device handle. * @pctrl: pinctrl handle. - * @domain: irqdomain handle. * @chip: gpiochip handle. * @irq: parent irq for the TLMM irq_chip. * @lock: Spinlock to protect register resources as well @@ -55,7 +51,6 @@ struct msm_pinctrl { struct device *dev; struct pinctrl_dev *pctrl; - struct irq_domain *domain; struct gpio_chip chip; int irq; @@ -68,6 +63,11 @@ struct msm_pinctrl { void __iomem *regs; }; +static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) +{ + return container_of(gc, struct msm_pinctrl, chip); +} + static int msm_get_groups_count(struct pinctrl_dev *pctldev) { struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -480,13 +480,6 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) spin_unlock_irqrestore(&pctrl->lock, flags); } -static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - - return irq_find_mapping(pctrl->domain, offset); -} - static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) { int gpio = chip->base + offset; @@ -556,7 +549,6 @@ static struct gpio_chip msm_gpio_template = { .direction_output = msm_gpio_direction_output, .get = msm_gpio_get, .set = msm_gpio_set, - .to_irq = msm_gpio_to_irq, .request = msm_gpio_request, .free = msm_gpio_free, .dbg_show = msm_gpio_dbg_show, @@ -608,12 +600,12 @@ static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, static void msm_gpio_irq_mask(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); const struct msm_pingroup *g; - struct msm_pinctrl *pctrl; unsigned long flags; u32 val; - pctrl = irq_data_get_irq_chip_data(d); g = &pctrl->soc->groups[d->hwirq]; spin_lock_irqsave(&pctrl->lock, flags); @@ -629,12 +621,12 @@ static void msm_gpio_irq_mask(struct irq_data *d) static void msm_gpio_irq_unmask(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); const struct msm_pingroup *g; - struct msm_pinctrl *pctrl; unsigned long flags; u32 val; - pctrl = irq_data_get_irq_chip_data(d); g = &pctrl->soc->groups[d->hwirq]; spin_lock_irqsave(&pctrl->lock, flags); @@ -654,12 +646,12 @@ static void msm_gpio_irq_unmask(struct irq_data *d) static void msm_gpio_irq_ack(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); const struct msm_pingroup *g; - struct msm_pinctrl *pctrl; unsigned long flags; u32 val; - pctrl = irq_data_get_irq_chip_data(d); g = &pctrl->soc->groups[d->hwirq]; spin_lock_irqsave(&pctrl->lock, flags); @@ -681,12 +673,12 @@ static void msm_gpio_irq_ack(struct irq_data *d) static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); const struct msm_pingroup *g; - struct msm_pinctrl *pctrl; unsigned long flags; u32 val; - pctrl = irq_data_get_irq_chip_data(d); g = &pctrl->soc->groups[d->hwirq]; spin_lock_irqsave(&pctrl->lock, flags); @@ -775,11 +767,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { - struct msm_pinctrl *pctrl; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); unsigned long flags; - pctrl = irq_data_get_irq_chip_data(d); - spin_lock_irqsave(&pctrl->lock, flags); irq_set_irq_wake(pctrl->irq, on); @@ -789,25 +780,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) return 0; } -static int msm_gpio_irq_reqres(struct irq_data *d) -{ - struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); - - if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) { - dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n", - d->hwirq); - return -EINVAL; - } - return 0; -} - -static void msm_gpio_irq_relres(struct irq_data *d) -{ - struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); - - gpio_unlock_as_irq(&pctrl->chip, d->hwirq); -} - static struct irq_chip msm_gpio_irq_chip = { .name = "msmgpio", .irq_mask = msm_gpio_irq_mask, @@ -815,14 +787,13 @@ static struct irq_chip msm_gpio_irq_chip = { .irq_ack = msm_gpio_irq_ack, .irq_set_type = msm_gpio_irq_set_type, .irq_set_wake = msm_gpio_irq_set_wake, - .irq_request_resources = msm_gpio_irq_reqres, - .irq_release_resources = msm_gpio_irq_relres, }; static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { + struct gpio_chip *gc = irq_desc_get_handler_data(desc); const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); struct irq_chip *chip = irq_get_chip(irq); int irq_pin; int handled = 0; @@ -839,7 +810,7 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) g = &pctrl->soc->groups[i]; val = readl(pctrl->regs + g->intr_status_reg); if (val & BIT(g->intr_status_bit)) { - irq_pin = irq_find_mapping(pctrl->domain, i); + irq_pin = irq_find_mapping(gc->irqdomain, i); generic_handle_irq(irq_pin); handled++; } @@ -852,19 +823,10 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) chained_irq_exit(chip, desc); } -/* - * This lock class tells lockdep that GPIO irqs are in a different - * category than their parents, so it won't report false recursion. - */ -static struct lock_class_key gpio_lock_class; - static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; - int irq; int ret; - int i; - int r; unsigned ngpio = pctrl->soc->ngpios; if (WARN_ON(ngpio > MAX_NR_GPIO)) @@ -890,23 +852,18 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) return ret; } - pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio, - &irq_domain_simple_ops, NULL); - if (!pctrl->domain) { - dev_err(pctrl->dev, "Failed to register irq domain\n"); - r = gpiochip_remove(&pctrl->chip); + ret = gpiochip_irqchip_add(chip, + &msm_gpio_irq_chip, + 0, + handle_edge_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); return -ENOSYS; } - for (i = 0; i < chip->ngpio; i++) { - irq = irq_create_mapping(pctrl->domain, i); - irq_set_lockdep_class(irq, &gpio_lock_class); - irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq); - irq_set_chip_data(irq, pctrl); - } - - irq_set_handler_data(pctrl->irq, pctrl); - irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler); + gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, + msm_gpio_irq_handler); return 0; } @@ -974,8 +931,6 @@ int msm_pinctrl_remove(struct platform_device *pdev) return ret; } - irq_set_chained_handler(pctrl->irq, NULL); - irq_domain_remove(pctrl->domain); pinctrl_unregister(pctrl->pctrl); return 0; diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c index 57766d56e25..418306911a6 100644 --- a/drivers/pinctrl/pinctrl-msm8x74.c +++ b/drivers/pinctrl/pinctrl-msm8x74.c @@ -402,169 +402,568 @@ static const unsigned int sdc2_data_pins[] = { 151 }; * the pingroup table below. */ enum msm8x74_functions { + MSM_MUX_cci_i2c0, + MSM_MUX_cci_i2c1, + MSM_MUX_blsp_i2c1, MSM_MUX_blsp_i2c2, + MSM_MUX_blsp_i2c3, + MSM_MUX_blsp_i2c4, + MSM_MUX_blsp_i2c5, MSM_MUX_blsp_i2c6, + MSM_MUX_blsp_i2c7, + MSM_MUX_blsp_i2c8, + MSM_MUX_blsp_i2c9, + MSM_MUX_blsp_i2c10, MSM_MUX_blsp_i2c11, + MSM_MUX_blsp_i2c12, MSM_MUX_blsp_spi1, + MSM_MUX_blsp_spi1_cs1, + MSM_MUX_blsp_spi1_cs2, + MSM_MUX_blsp_spi1_cs3, + MSM_MUX_blsp_spi2, + MSM_MUX_blsp_spi2_cs1, + MSM_MUX_blsp_spi2_cs2, + MSM_MUX_blsp_spi2_cs3, + MSM_MUX_blsp_spi3, + MSM_MUX_blsp_spi4, + MSM_MUX_blsp_spi5, + MSM_MUX_blsp_spi6, + MSM_MUX_blsp_spi7, MSM_MUX_blsp_spi8, + MSM_MUX_blsp_spi9, + MSM_MUX_blsp_spi10, + MSM_MUX_blsp_spi10_cs1, + MSM_MUX_blsp_spi10_cs2, + MSM_MUX_blsp_spi10_cs3, + MSM_MUX_blsp_spi11, + MSM_MUX_blsp_spi12, + MSM_MUX_blsp_uart1, MSM_MUX_blsp_uart2, + MSM_MUX_blsp_uart3, + MSM_MUX_blsp_uart4, + MSM_MUX_blsp_uart5, + MSM_MUX_blsp_uart6, + MSM_MUX_blsp_uart7, MSM_MUX_blsp_uart8, + MSM_MUX_blsp_uart9, + MSM_MUX_blsp_uart10, + MSM_MUX_blsp_uart11, + MSM_MUX_blsp_uart12, + MSM_MUX_blsp_uim1, + MSM_MUX_blsp_uim2, + MSM_MUX_blsp_uim3, + MSM_MUX_blsp_uim4, + MSM_MUX_blsp_uim5, + MSM_MUX_blsp_uim6, + MSM_MUX_blsp_uim7, + MSM_MUX_blsp_uim8, + MSM_MUX_blsp_uim9, + MSM_MUX_blsp_uim10, + MSM_MUX_blsp_uim11, + MSM_MUX_blsp_uim12, + MSM_MUX_uim1, + MSM_MUX_uim2, + MSM_MUX_uim_batt_alarm, + MSM_MUX_sdc3, + MSM_MUX_sdc4, + MSM_MUX_gcc_gp_clk1, + MSM_MUX_gcc_gp_clk2, + MSM_MUX_gcc_gp_clk3, + MSM_MUX_qua_mi2s, + MSM_MUX_pri_mi2s, + MSM_MUX_spkr_mi2s, + MSM_MUX_ter_mi2s, + MSM_MUX_sec_mi2s, + MSM_MUX_hdmi_cec, + MSM_MUX_hdmi_ddc, + MSM_MUX_hdmi_hpd, + MSM_MUX_edp_hpd, + MSM_MUX_mdp_vsync, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_cam_mclk2, + MSM_MUX_cam_mclk3, + MSM_MUX_cci_timer0, + MSM_MUX_cci_timer1, + MSM_MUX_cci_timer2, + MSM_MUX_cci_timer3, + MSM_MUX_cci_timer4, + MSM_MUX_cci_async_in0, + MSM_MUX_cci_async_in1, + MSM_MUX_cci_async_in2, + MSM_MUX_gp_pdm0, + MSM_MUX_gp_pdm1, + MSM_MUX_gp_pdm2, + MSM_MUX_gp0_clk, + MSM_MUX_gp1_clk, + MSM_MUX_gp_mn, + MSM_MUX_tsif1, + MSM_MUX_tsif2, + MSM_MUX_hsic, + MSM_MUX_grfc, + MSM_MUX_audio_ref_clk, + MSM_MUX_bt, + MSM_MUX_fm, + MSM_MUX_wlan, MSM_MUX_slimbus, MSM_MUX_NA, }; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi1_cs1_groups[] = { "gpio8" }; +static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" }; +static const char * const blsp_spi1_cs3_groups[] = { "gpio10" }; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" }; +static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" }; +static const char * const blsp_spi2_cs3_groups[] = { "gpio66" }; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" }; +static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" }; + +static const char * const blsp_uart4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; +static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" }; +static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" }; +static const char * const blsp_spi4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; + +static const char * const blsp_uart5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; +static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" }; +static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" }; +static const char * const blsp_spi5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; + +static const char * const blsp_uart6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; +static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" }; static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; -static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; -static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" }; +static const char * const blsp_spi6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; + +static const char * const blsp_uart7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" }; +static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" }; +static const char * const blsp_spi7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const char * const blsp_uart8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; +static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" }; +static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" }; static const char * const blsp_spi8_groups[] = { "gpio45", "gpio46", "gpio47", "gpio48" }; -static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" }; -static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" }; + +static const char * const blsp_uart9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" }; +static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" }; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const blsp_uart10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" }; +static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" }; +static const char * const blsp_spi10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" }; +static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" }; +static const char * const blsp_spi10_cs3_groups[] = { "gpio90" }; + +static const char * const blsp_uart11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; +static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" }; +static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; +static const char * const blsp_spi11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; + +static const char * const blsp_uart12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; +static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" }; +static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" }; +static const char * const blsp_spi12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const char * const uim1_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100" +}; + +static const char * const uim2_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const uim_batt_alarm_groups[] = { "gpio101" }; + +static const char * const sdc3_groups[] = { + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + +static const char * const sdc4_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const gp0_clk_groups[] = { "gpio26" }; +static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" }; +static const char * const gp_mn_groups[] = { "gpio29" }; +static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" }; +static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" }; +static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" }; + +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; + +static const char * const spkr_mi2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; + +static const char * const ter_mi2s_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77" +}; + +static const char * const sec_mi2s_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; + +static const char * const hdmi_cec_groups[] = { "gpio31" }; +static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" }; +static const char * const hdmi_hpd_groups[] = { "gpio34" }; +static const char * const edp_hpd_groups[] = { "gpio102" }; + +static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" }; +static const char * const cam_mclk0_groups[] = { "gpio15" }; +static const char * const cam_mclk1_groups[] = { "gpio16" }; +static const char * const cam_mclk2_groups[] = { "gpio17" }; +static const char * const cam_mclk3_groups[] = { "gpio18" }; + +static const char * const cci_timer0_groups[] = { "gpio23" }; +static const char * const cci_timer1_groups[] = { "gpio24" }; +static const char * const cci_timer2_groups[] = { "gpio25" }; +static const char * const cci_timer3_groups[] = { "gpio26" }; +static const char * const cci_timer4_groups[] = { "gpio27" }; +static const char * const cci_async_in0_groups[] = { "gpio28" }; +static const char * const cci_async_in1_groups[] = { "gpio26" }; +static const char * const cci_async_in2_groups[] = { "gpio27" }; + +static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" }; +static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" }; +static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" }; + +static const char * const tsif1_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92" +}; + +static const char * const tsif2_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const hsic_groups[] = { "gpio144", "gpio145" }; +static const char * const grfc_groups[] = { + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", + "gpio128", "gpio136", "gpio137", "gpio141", "gpio143" +}; + +static const char * const audio_ref_clk_groups[] = { "gpio69" }; + +static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" }; + +static const char * const fm_groups[] = { "gpio41", "gpio42" }; + +static const char * const wlan_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; static const struct msm_function msm8x74_functions[] = { + FUNCTION(cci_i2c0), + FUNCTION(cci_i2c1), + FUNCTION(uim1), + FUNCTION(uim2), + FUNCTION(uim_batt_alarm), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(blsp_uim3), + FUNCTION(blsp_uim4), + FUNCTION(blsp_uim5), + FUNCTION(blsp_uim6), + FUNCTION(blsp_uim7), + FUNCTION(blsp_uim8), + FUNCTION(blsp_uim9), + FUNCTION(blsp_uim10), + FUNCTION(blsp_uim11), + FUNCTION(blsp_uim12), + FUNCTION(blsp_i2c1), FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_i2c5), FUNCTION(blsp_i2c6), + FUNCTION(blsp_i2c7), + FUNCTION(blsp_i2c8), + FUNCTION(blsp_i2c9), + FUNCTION(blsp_i2c10), FUNCTION(blsp_i2c11), + FUNCTION(blsp_i2c12), FUNCTION(blsp_spi1), + FUNCTION(blsp_spi1_cs1), + FUNCTION(blsp_spi1_cs2), + FUNCTION(blsp_spi1_cs3), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi2_cs1), + FUNCTION(blsp_spi2_cs2), + FUNCTION(blsp_spi2_cs3), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_spi7), FUNCTION(blsp_spi8), + FUNCTION(blsp_spi9), + FUNCTION(blsp_spi10), + FUNCTION(blsp_spi10_cs1), + FUNCTION(blsp_spi10_cs2), + FUNCTION(blsp_spi10_cs3), + FUNCTION(blsp_spi11), + FUNCTION(blsp_spi12), + FUNCTION(blsp_uart1), FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(blsp_uart5), + FUNCTION(blsp_uart6), + FUNCTION(blsp_uart7), FUNCTION(blsp_uart8), + FUNCTION(blsp_uart9), + FUNCTION(blsp_uart10), + FUNCTION(blsp_uart11), + FUNCTION(blsp_uart12), + FUNCTION(sdc3), + FUNCTION(sdc4), + FUNCTION(gcc_gp_clk1), + FUNCTION(gcc_gp_clk2), + FUNCTION(gcc_gp_clk3), + FUNCTION(qua_mi2s), + FUNCTION(pri_mi2s), + FUNCTION(spkr_mi2s), + FUNCTION(ter_mi2s), + FUNCTION(sec_mi2s), + FUNCTION(mdp_vsync), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(cam_mclk2), + FUNCTION(cam_mclk3), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cci_async_in0), + FUNCTION(cci_async_in1), + FUNCTION(cci_async_in2), + FUNCTION(hdmi_cec), + FUNCTION(hdmi_ddc), + FUNCTION(hdmi_hpd), + FUNCTION(edp_hpd), + FUNCTION(gp_pdm0), + FUNCTION(gp_pdm1), + FUNCTION(gp_pdm2), + FUNCTION(gp0_clk), + FUNCTION(gp1_clk), + FUNCTION(gp_mn), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(hsic), + FUNCTION(grfc), + FUNCTION(audio_ref_clk), + FUNCTION(bt), + FUNCTION(fm), + FUNCTION(wlan), FUNCTION(slimbus), }; static const struct msm_pingroup msm8x74_groups[] = { - PINGROUP(0, blsp_spi1, NA, NA, NA, NA, NA, NA), - PINGROUP(1, blsp_spi1, NA, NA, NA, NA, NA, NA), - PINGROUP(2, blsp_spi1, NA, NA, NA, NA, NA, NA), - PINGROUP(3, blsp_spi1, NA, NA, NA, NA, NA, NA), - PINGROUP(4, NA, blsp_uart2, NA, NA, NA, NA, NA), - PINGROUP(5, NA, blsp_uart2, NA, NA, NA, NA, NA), - PINGROUP(6, NA, NA, blsp_i2c2, NA, NA, NA, NA), - PINGROUP(7, NA, NA, blsp_i2c2, NA, NA, NA, NA), - PINGROUP(8, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(9, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(10, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(11, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(12, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(13, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(14, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(15, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(16, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(17, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(18, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(19, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(20, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(21, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(22, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(23, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(24, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(25, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(26, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(27, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(28, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(29, NA, NA, blsp_i2c6, NA, NA, NA, NA), - PINGROUP(30, NA, NA, blsp_i2c6, NA, NA, NA, NA), - PINGROUP(31, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(32, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(33, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(35, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(36, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(37, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(38, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(39, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(40, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(41, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(42, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(43, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(44, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA), - PINGROUP(46, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA), - PINGROUP(47, blsp_spi8, NA, NA, NA, NA, NA, NA), - PINGROUP(48, blsp_spi8, NA, NA, NA, NA, NA, NA), - PINGROUP(49, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(50, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(51, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(52, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(53, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(54, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(55, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(56, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(57, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(58, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(59, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(60, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(61, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(62, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(63, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(66, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(69, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(70, slimbus, NA, NA, NA, NA, NA, NA), - PINGROUP(71, slimbus, NA, NA, NA, NA, NA, NA), - PINGROUP(72, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(73, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(74, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(75, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(76, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(77, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(78, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(79, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(80, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(81, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(82, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(83, NA, NA, blsp_i2c11, NA, NA, NA, NA), - PINGROUP(84, NA, NA, blsp_i2c11, NA, NA, NA, NA), - PINGROUP(85, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(86, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(87, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(88, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(89, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(90, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(91, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(92, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(93, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(94, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(95, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(96, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(97, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(98, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(99, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(100, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(101, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(102, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA), + PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA), + PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA), + PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA), + PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA), + PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA), + PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA), + PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA), + PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA), + PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA), + PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA), + PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA), + PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA), + PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA), + PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA), + PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA), + PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA), + PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA), + PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA), + PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA), + PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA), + PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA), + PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA), + PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA), + PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA), + PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA), + PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA), + PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA), + PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA), + PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA), PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(104, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(105, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(106, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(107, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(108, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(109, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(110, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(111, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(112, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(113, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(114, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(115, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(116, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(117, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(118, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(119, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(120, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(121, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(122, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(123, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(124, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(125, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(126, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(127, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(128, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA), PINGROUP(129, NA, NA, NA, NA, NA, NA, NA), PINGROUP(130, NA, NA, NA, NA, NA, NA, NA), PINGROUP(131, NA, NA, NA, NA, NA, NA, NA), @@ -572,16 +971,16 @@ static const struct msm_pingroup msm8x74_groups[] = { PINGROUP(133, NA, NA, NA, NA, NA, NA, NA), PINGROUP(134, NA, NA, NA, NA, NA, NA, NA), PINGROUP(135, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(136, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(137, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA), PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), PINGROUP(140, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(141, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(143, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(143, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(144, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(145, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA), + PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA), SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 81075f2a1d3..2960557bfed 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -810,6 +810,7 @@ static const struct pinconf_ops pcs_pinconf_ops = { static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, unsigned pin_pos) { + struct pcs_soc_data *pcs_soc = &pcs->socdata; struct pinctrl_pin_desc *pin; struct pcs_name *pn; int i; @@ -821,6 +822,18 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, return -ENOMEM; } + if (pcs_soc->irq_enable_mask) { + unsigned val; + + val = pcs->read(pcs->base + offset); + if (val & pcs_soc->irq_enable_mask) { + dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", + (unsigned long)pcs->res->start + offset, val); + val &= ~pcs_soc->irq_enable_mask; + pcs->write(val, pcs->base + offset); + } + } + pin = &pcs->pins.pa[i]; pn = &pcs->names[i]; sprintf(pn->name, "%lx.%d", diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 1bd6363bc95..9f43916637c 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1431,7 +1431,7 @@ static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) status = readl(info->irqmux_base); - for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK) + for_each_set_bit(n, &status, info->nbanks) __gpio_irq_handler(&info->banks[n]); chained_irq_exit(chip, desc); diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index c5e0f6973a3..26ca6855f47 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -629,9 +629,8 @@ static int tb10x_gpio_request_enable(struct pinctrl_dev *pctl, */ for (i = 0; i < state->pinfuncgrpcnt; i++) { const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i]; - unsigned int port = pfg->port; unsigned int mode = pfg->mode; - int j; + int j, port = pfg->port; /* * Skip pin groups which are always mapped and don't need diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index d39ca87353e..ce9fb7aa8ba 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -20,7 +20,10 @@ #include <linux/io.h> #include <linux/kernel.h> #include <linux/pinctrl/pinconf-generic.h> + +#ifndef CONFIG_ARCH_MULTIPLATFORM #include <mach/irqs.h> +#endif #include "core.h" #include "sh_pfc.h" diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 6c83ce43a94..e4c1ef47705 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -22,7 +22,9 @@ #include <linux/kernel.h> #include <linux/pinctrl/pinconf-generic.h> +#ifndef CONFIG_ARCH_MULTIPLATFORM #include <mach/irqs.h> +#endif #include "core.h" #include "sh_pfc.h" diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index d79e0ba365a..9a179c94b4d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -4928,8 +4928,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_MSIOF0_SCK_B, 0, /* IP5_23_21 [3] */ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, - FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, - FN_IERX_C, 0, + FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, /* IP5_20_18 [3] */ FN_WE0_N, FN_IECLK, FN_CAN_CLK, FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 8be969a8ff9..2e688dc4a3c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -5680,7 +5680,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SCIF3 [2] */ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, /* SEL_IEB [2] */ - FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, /* SEL_MMC [1] */ FN_SEL_MMC_0, FN_SEL_MMC_1, /* SEL_SCIF5 [1] */ diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 6f6ba100994..ee370de4609 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -26,7 +26,9 @@ #include <linux/regulator/machine.h> #include <linux/slab.h> +#ifndef CONFIG_ARCH_MULTIPLATFORM #include <mach/irqs.h> +#endif #include "core.h" #include "sh_pfc.h" diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index ab8fd258d9e..d482c40b012 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -98,8 +98,13 @@ struct pinmux_irq { const short *gpios; }; +#ifdef CONFIG_ARCH_MULTIPLATFORM +#define PINMUX_IRQ(irq_nr, ids...) \ + { .gpios = (const short []) { ids, -1 } } +#else #define PINMUX_IRQ(irq_nr, ids...) \ { .irq = irq_nr, .gpios = (const short []) { ids, -1 } } +#endif struct pinmux_range { u16 begin; diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index c03dcc7729e..014f5b1fee5 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -42,7 +42,6 @@ struct sirfsoc_gpio_chip { struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; }; -static struct sirfsoc_gpio_chip sgpio_chip; static DEFINE_SPINLOCK(sgpio_lock); static struct sirfsoc_pin_group *sirfsoc_pin_groups; @@ -255,17 +254,6 @@ static struct pinctrl_desc sirfsoc_pinmux_desc = { .owner = THIS_MODULE, }; -/* - * Todo: bind irq_chip to every pinctrl_gpio_range - */ -static struct pinctrl_gpio_range sirfsoc_gpio_ranges = { - .name = "sirfsoc-gpio*", - .id = 0, - .base = 0, - .pin_base = 0, - .npins = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS, -}; - static void __iomem *sirfsoc_rsc_of_iomap(void) { const struct of_device_id rsc_ids[] = { @@ -289,9 +277,6 @@ static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) return -EINVAL; - if (gc != &sgpio_chip.chip.gc) - return -EINVAL; - if (flags) *flags = gpiospec->args[1]; @@ -354,9 +339,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev) goto out_no_pmx; } - sirfsoc_gpio_ranges.gc = &sgpio_chip.chip.gc; - pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges); - dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); return 0; @@ -441,20 +423,28 @@ static int __init sirfsoc_pinmux_init(void) } arch_initcall(sirfsoc_pinmux_init); -static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio) +static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct sirfsoc_gpio_chip, chip.gc); +} + +static inline struct sirfsoc_gpio_bank * +sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset) { - return &sgpio_chip.sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE]; + return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE]; } -static inline int sirfsoc_gpio_to_bankoff(unsigned int gpio) +static inline int sirfsoc_gpio_to_bankoff(unsigned int offset) { - return gpio % SIRFSOC_GPIO_BANK_SIZE; + return offset % SIRFSOC_GPIO_BANK_SIZE; } static void sirfsoc_gpio_irq_ack(struct irq_data *d) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq); - int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); + int idx = sirfsoc_gpio_to_bankoff(d->hwirq); u32 val, offset; unsigned long flags; @@ -462,14 +452,16 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d) spin_lock_irqsave(&sgpio_lock, flags); - val = readl(sgpio_chip.chip.regs + offset); + val = readl(sgpio->chip.regs + offset); - writel(val, sgpio_chip.chip.regs + offset); + writel(val, sgpio->chip.regs + offset); spin_unlock_irqrestore(&sgpio_lock, flags); } -static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx) +static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, + struct sirfsoc_gpio_bank *bank, + int idx) { u32 val, offset; unsigned long flags; @@ -478,25 +470,29 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx) spin_lock_irqsave(&sgpio_lock, flags); - val = readl(sgpio_chip.chip.regs + offset); + val = readl(sgpio->chip.regs + offset); val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; - writel(val, sgpio_chip.chip.regs + offset); + writel(val, sgpio->chip.regs + offset); spin_unlock_irqrestore(&sgpio_lock, flags); } static void sirfsoc_gpio_irq_mask(struct irq_data *d) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); - __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); + __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); } static void sirfsoc_gpio_irq_unmask(struct irq_data *d) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq); - int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); + int idx = sirfsoc_gpio_to_bankoff(d->hwirq); u32 val, offset; unsigned long flags; @@ -504,18 +500,20 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d) spin_lock_irqsave(&sgpio_lock, flags); - val = readl(sgpio_chip.chip.regs + offset); + val = readl(sgpio->chip.regs + offset); val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; - writel(val, sgpio_chip.chip.regs + offset); + writel(val, sgpio->chip.regs + offset); spin_unlock_irqrestore(&sgpio_lock, flags); } static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq); - int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); + int idx = sirfsoc_gpio_to_bankoff(d->hwirq); u32 val, offset; unsigned long flags; @@ -523,7 +521,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) spin_lock_irqsave(&sgpio_lock, flags); - val = readl(sgpio_chip.chip.regs + offset); + val = readl(sgpio->chip.regs + offset); val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); switch (type) { @@ -551,7 +549,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) break; } - writel(val, sgpio_chip.chip.regs + offset); + writel(val, sgpio->chip.regs + offset); spin_unlock_irqrestore(&sgpio_lock, flags); @@ -568,22 +566,24 @@ static struct irq_chip sirfsoc_irq_chip = { static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) { + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); struct sirfsoc_gpio_bank *bank; u32 status, ctrl; int idx = 0; struct irq_chip *chip = irq_get_chip(irq); int i; - for (i = 0; i < SIRFSOC_GPIO_BANK_SIZE; i++) { - bank = &sgpio_chip.sgpio_bank[i]; + for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { + bank = &sgpio->sgpio_bank[i]; if (bank->parent_irq == irq) break; } - BUG_ON (i == SIRFSOC_GPIO_BANK_SIZE); + BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS); chained_irq_enter(chip, desc); - status = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); + status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); if (!status) { printk(KERN_WARNING "%s: gpio id %d status %#x no interrupt is flaged\n", @@ -593,7 +593,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) } while (status) { - ctrl = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); + ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); /* * Here we must check whether the corresponding GPIO's interrupt @@ -602,7 +602,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { pr_debug("%s: gpio id %d idx %d happens\n", __func__, bank->id, idx); - generic_handle_irq(irq_find_mapping(sgpio_chip.chip.gc.irqdomain, idx + + generic_handle_irq(irq_find_mapping(gc->irqdomain, idx + bank->id * SIRFSOC_GPIO_BANK_SIZE)); } @@ -613,18 +613,20 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) chained_irq_exit(chip, desc); } -static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset) +static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio, + unsigned ctrl_offset) { u32 val; - val = readl(sgpio_chip.chip.regs + ctrl_offset); + val = readl(sgpio->chip.regs + ctrl_offset); val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; - writel(val, sgpio_chip.chip.regs + ctrl_offset); + writel(val, sgpio->chip.regs + ctrl_offset); } static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); unsigned long flags; if (pinctrl_request_gpio(chip->base + offset)) @@ -636,8 +638,8 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) * default status: * set direction as input and mask irq */ - sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); - __sirfsoc_gpio_irq_mask(bank, offset); + sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); + __sirfsoc_gpio_irq_mask(sgpio, bank, offset); spin_unlock_irqrestore(&bank->lock, flags); @@ -646,13 +648,14 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); unsigned long flags; spin_lock_irqsave(&bank->lock, flags); - __sirfsoc_gpio_irq_mask(bank, offset); - sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); + __sirfsoc_gpio_irq_mask(sgpio, bank, offset); + sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); spin_unlock_irqrestore(&bank->lock, flags); @@ -661,7 +664,8 @@ static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); int idx = sirfsoc_gpio_to_bankoff(gpio); unsigned long flags; unsigned offset; @@ -670,22 +674,24 @@ static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) spin_lock_irqsave(&bank->lock, flags); - sirfsoc_gpio_set_input(bank, offset); + sirfsoc_gpio_set_input(sgpio, offset); spin_unlock_irqrestore(&bank->lock, flags); return 0; } -static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset, - int value) +static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio, + struct sirfsoc_gpio_bank *bank, + unsigned offset, + int value) { u32 out_ctrl; unsigned long flags; spin_lock_irqsave(&bank->lock, flags); - out_ctrl = readl(sgpio_chip.chip.regs + offset); + out_ctrl = readl(sgpio->chip.regs + offset); if (value) out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; else @@ -693,14 +699,15 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsig out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; - writel(out_ctrl, sgpio_chip.chip.regs + offset); + writel(out_ctrl, sgpio->chip.regs + offset); spin_unlock_irqrestore(&bank->lock, flags); } static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); int idx = sirfsoc_gpio_to_bankoff(gpio); u32 offset; unsigned long flags; @@ -709,7 +716,7 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, spin_lock_irqsave(&sgpio_lock, flags); - sirfsoc_gpio_set_output(bank, offset, value); + sirfsoc_gpio_set_output(sgpio, bank, offset, value); spin_unlock_irqrestore(&sgpio_lock, flags); @@ -718,13 +725,14 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); u32 val; unsigned long flags; spin_lock_irqsave(&bank->lock, flags); - val = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); + val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); spin_unlock_irqrestore(&bank->lock, flags); @@ -734,23 +742,25 @@ static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value) { - struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset); + struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); + struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); u32 ctrl; unsigned long flags; spin_lock_irqsave(&bank->lock, flags); - ctrl = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); + ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); if (value) ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; else ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; - writel(ctrl, sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); + writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); spin_unlock_irqrestore(&bank->lock, flags); } -static void sirfsoc_gpio_set_pullup(const u32 *pullups) +static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio, + const u32 *pullups) { int i, n; const unsigned long *p = (const unsigned long *)pullups; @@ -758,15 +768,16 @@ static void sirfsoc_gpio_set_pullup(const u32 *pullups) for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { for_each_set_bit(n, p + i, BITS_PER_LONG) { u32 offset = SIRFSOC_GPIO_CTRL(i, n); - u32 val = readl(sgpio_chip.chip.regs + offset); + u32 val = readl(sgpio->chip.regs + offset); val |= SIRFSOC_GPIO_CTL_PULL_MASK; val |= SIRFSOC_GPIO_CTL_PULL_HIGH; - writel(val, sgpio_chip.chip.regs + offset); + writel(val, sgpio->chip.regs + offset); } } } -static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns) +static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio, + const u32 *pulldowns) { int i, n; const unsigned long *p = (const unsigned long *)pulldowns; @@ -774,10 +785,10 @@ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns) for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { for_each_set_bit(n, p + i, BITS_PER_LONG) { u32 offset = SIRFSOC_GPIO_CTRL(i, n); - u32 val = readl(sgpio_chip.chip.regs + offset); + u32 val = readl(sgpio->chip.regs + offset); val |= SIRFSOC_GPIO_CTL_PULL_MASK; val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; - writel(val, sgpio_chip.chip.regs + offset); + writel(val, sgpio->chip.regs + offset); } } } @@ -785,6 +796,7 @@ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns) static int sirfsoc_gpio_probe(struct device_node *np) { int i, err = 0; + static struct sirfsoc_gpio_chip *sgpio; struct sirfsoc_gpio_bank *bank; void __iomem *regs; struct platform_device *pdev; @@ -796,6 +808,10 @@ static int sirfsoc_gpio_probe(struct device_node *np) if (!pdev) return -ENODEV; + sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); + if (!sgpio) + return -ENOMEM; + regs = of_iomap(np, 0); if (!regs) return -ENOMEM; @@ -803,30 +819,30 @@ static int sirfsoc_gpio_probe(struct device_node *np) if (of_device_is_compatible(np, "sirf,marco-pinctrl")) is_marco = 1; - sgpio_chip.chip.gc.request = sirfsoc_gpio_request; - sgpio_chip.chip.gc.free = sirfsoc_gpio_free; - sgpio_chip.chip.gc.direction_input = sirfsoc_gpio_direction_input; - sgpio_chip.chip.gc.get = sirfsoc_gpio_get_value; - sgpio_chip.chip.gc.direction_output = sirfsoc_gpio_direction_output; - sgpio_chip.chip.gc.set = sirfsoc_gpio_set_value; - sgpio_chip.chip.gc.base = 0; - sgpio_chip.chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; - sgpio_chip.chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); - sgpio_chip.chip.gc.of_node = np; - sgpio_chip.chip.gc.of_xlate = sirfsoc_gpio_of_xlate; - sgpio_chip.chip.gc.of_gpio_n_cells = 2; - sgpio_chip.chip.gc.dev = &pdev->dev; - sgpio_chip.chip.regs = regs; - sgpio_chip.is_marco = is_marco; - - err = gpiochip_add(&sgpio_chip.chip.gc); + sgpio->chip.gc.request = sirfsoc_gpio_request; + sgpio->chip.gc.free = sirfsoc_gpio_free; + sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; + sgpio->chip.gc.get = sirfsoc_gpio_get_value; + sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output; + sgpio->chip.gc.set = sirfsoc_gpio_set_value; + sgpio->chip.gc.base = 0; + sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; + sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); + sgpio->chip.gc.of_node = np; + sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; + sgpio->chip.gc.of_gpio_n_cells = 2; + sgpio->chip.gc.dev = &pdev->dev; + sgpio->chip.regs = regs; + sgpio->is_marco = is_marco; + + err = gpiochip_add(&sgpio->chip.gc); if (err) { dev_err(&pdev->dev, "%s: error in probe function with status %d\n", np->full_name, err); goto out; } - err = gpiochip_irqchip_add(&sgpio_chip.chip.gc, + err = gpiochip_irqchip_add(&sgpio->chip.gc, &sirfsoc_irq_chip, 0, handle_level_irq, IRQ_TYPE_NONE); @@ -837,30 +853,42 @@ static int sirfsoc_gpio_probe(struct device_node *np) } for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { - bank = &sgpio_chip.sgpio_bank[i]; + bank = &sgpio->sgpio_bank[i]; spin_lock_init(&bank->lock); bank->parent_irq = platform_get_irq(pdev, i); if (bank->parent_irq < 0) { err = bank->parent_irq; - goto out; + goto out_banks; } - gpiochip_set_chained_irqchip(&sgpio_chip.chip.gc, + gpiochip_set_chained_irqchip(&sgpio->chip.gc, &sirfsoc_irq_chip, bank->parent_irq, sirfsoc_gpio_handle_irq); } + err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), + 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS); + if (err) { + dev_err(&pdev->dev, + "could not add gpiochip pin range\n"); + goto out_no_range; + } + if (!of_property_read_u32_array(np, "sirf,pullups", pullups, SIRFSOC_GPIO_NO_OF_BANKS)) - sirfsoc_gpio_set_pullup(pullups); + sirfsoc_gpio_set_pullup(sgpio, pullups); if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, SIRFSOC_GPIO_NO_OF_BANKS)) - sirfsoc_gpio_set_pulldown(pulldowns); + sirfsoc_gpio_set_pulldown(sgpio, pulldowns); return 0; +out_no_range: +out_banks: + if (gpiochip_remove(&sgpio->chip.gc)) + dev_err(&pdev->dev, "could not remove gpio chip\n"); out: iounmap(regs); return err; diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 3940d098d6c..73e0a305ea1 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -2,31 +2,35 @@ if ARCH_SUNXI config PINCTRL_SUNXI bool + +config PINCTRL_SUNXI_COMMON + bool select PINMUX select GENERIC_PINCONF config PINCTRL_SUN4I_A10 - bool - select PINCTRL_SUNXI + def_bool PINCTRL_SUNXI || MACH_SUN4I + select PINCTRL_SUNXI_COMMON config PINCTRL_SUN5I_A10S - bool - select PINCTRL_SUNXI + def_bool PINCTRL_SUNXI || MACH_SUN5I + select PINCTRL_SUNXI_COMMON config PINCTRL_SUN5I_A13 - bool - select PINCTRL_SUNXI + def_bool PINCTRL_SUNXI || MACH_SUN5I + select PINCTRL_SUNXI_COMMON config PINCTRL_SUN6I_A31 - bool - select PINCTRL_SUNXI + def_bool PINCTRL_SUNXI || MACH_SUN6I + select PINCTRL_SUNXI_COMMON config PINCTRL_SUN6I_A31_R - bool - select PINCTRL_SUNXI + def_bool PINCTRL_SUNXI || MACH_SUN6I + depends on RESET_CONTROLLER + select PINCTRL_SUNXI_COMMON config PINCTRL_SUN7I_A20 - bool - select PINCTRL_SUNXI + def_bool PINCTRL_SUNXI || MACH_SUN7I + select PINCTRL_SUNXI_COMMON endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 8e23a15e695..0f4461cbe11 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -1,5 +1,5 @@ # Core -obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o +obj-$(CONFIG_PINCTRL_SUNXI_COMMON) += pinctrl-sunxi.o # SoC Drivers obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index f6522b54ece..5f38c7f6783 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -211,6 +211,10 @@ static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, configlen++; pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); + if (!pinconfig) { + kfree(*map); + return -ENOMEM; + } if (!of_property_read_u32(node, "allwinner,drive", &val)) { u16 strength = (val + 1) * 10; @@ -280,6 +284,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct sunxi_pinctrl_group *g = &pctl->groups[group]; unsigned long flags; + unsigned pin = g->pin - pctl->desc->pin_base; u32 val, mask; u16 strength; u8 dlevel; @@ -303,23 +308,23 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, * 3: 40mA */ dlevel = strength / 10 - 1; - val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); - mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); + val = readl(pctl->membase + sunxi_dlevel_reg(pin)); + mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); writel((val & ~mask) - | dlevel << sunxi_dlevel_offset(g->pin), - pctl->membase + sunxi_dlevel_reg(g->pin)); + | dlevel << sunxi_dlevel_offset(pin), + pctl->membase + sunxi_dlevel_reg(pin)); break; case PIN_CONFIG_BIAS_PULL_UP: - val = readl(pctl->membase + sunxi_pull_reg(g->pin)); - mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); - writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), - pctl->membase + sunxi_pull_reg(g->pin)); + val = readl(pctl->membase + sunxi_pull_reg(pin)); + mask = PULL_PINS_MASK << sunxi_pull_offset(pin); + writel((val & ~mask) | 1 << sunxi_pull_offset(pin), + pctl->membase + sunxi_pull_reg(pin)); break; case PIN_CONFIG_BIAS_PULL_DOWN: - val = readl(pctl->membase + sunxi_pull_reg(g->pin)); - mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); - writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), - pctl->membase + sunxi_pull_reg(g->pin)); + val = readl(pctl->membase + sunxi_pull_reg(pin)); + mask = PULL_PINS_MASK << sunxi_pull_offset(pin); + writel((val & ~mask) | 2 << sunxi_pull_offset(pin), + pctl->membase + sunxi_pull_reg(pin)); break; default: break; @@ -376,6 +381,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pctl->lock, flags); + pin -= pctl->desc->pin_base; val = readl(pctl->membase + sunxi_mux_reg(pin)); mask = MUX_PINS_MASK << sunxi_mux_offset(pin); writel((val & ~mask) | config << sunxi_mux_offset(pin), @@ -436,12 +442,6 @@ static const struct pinmux_ops sunxi_pmx_ops = { .gpio_set_direction = sunxi_pmx_gpio_set_direction, }; -static struct pinctrl_desc sunxi_pctrl_desc = { - .confops = &sunxi_pconf_ops, - .pctlops = &sunxi_pctrl_ops, - .pmxops = &sunxi_pmx_ops, -}; - static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) { return pinctrl_request_gpio(chip->base + offset); @@ -529,8 +529,6 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) if (!desc) return -EINVAL; - pctl->irq_array[desc->irqnum] = offset; - dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", chip->label, offset + chip->base, desc->irqnum); @@ -731,6 +729,9 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev) struct sunxi_desc_function *func = pin->functions; while (func->name) { + /* Create interrupt mapping while we're at it */ + if (!strcmp(func->name, "irq")) + pctl->irq_array[func->irqnum] = pin->pin.number; sunxi_pinctrl_add_function(pctl, func->name); func++; } @@ -778,6 +779,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev, const struct sunxi_pinctrl_desc *desc) { struct device_node *node = pdev->dev.of_node; + struct pinctrl_desc *pctrl_desc; struct pinctrl_pin_desc *pins; struct sunxi_pinctrl *pctl; struct resource *res; @@ -796,6 +798,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev, if (IS_ERR(pctl->membase)) return PTR_ERR(pctl->membase); + pctl->dev = &pdev->dev; pctl->desc = desc; ret = sunxi_pinctrl_build_state(pdev); @@ -813,12 +816,21 @@ int sunxi_pinctrl_init(struct platform_device *pdev, for (i = 0; i < pctl->desc->npins; i++) pins[i] = pctl->desc->pins[i].pin; - sunxi_pctrl_desc.name = dev_name(&pdev->dev); - sunxi_pctrl_desc.owner = THIS_MODULE; - sunxi_pctrl_desc.pins = pins; - sunxi_pctrl_desc.npins = pctl->desc->npins; - pctl->dev = &pdev->dev; - pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc, + pctrl_desc = devm_kzalloc(&pdev->dev, + sizeof(*pctrl_desc), + GFP_KERNEL); + if (!pctrl_desc) + return -ENOMEM; + + pctrl_desc->name = dev_name(&pdev->dev); + pctrl_desc->owner = THIS_MODULE; + pctrl_desc->pins = pins; + pctrl_desc->npins = pctl->desc->npins; + pctrl_desc->confops = &sunxi_pconf_ops; + pctrl_desc->pctlops = &sunxi_pctrl_ops; + pctrl_desc->pmxops = &sunxi_pmx_ops; + + pctl->pctl_dev = pinctrl_register(pctrl_desc, &pdev->dev, pctl); if (!pctl->pctl_dev) { dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index 9802b67040c..2c61281bebd 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -523,17 +523,6 @@ static int wmt_gpio_get_direction(struct gpio_chip *chip, unsigned offset) return GPIOF_DIR_IN; } -static int wmt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - return pinctrl_gpio_direction_input(chip->base + offset); -} - -static int wmt_gpio_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - return pinctrl_gpio_direction_output(chip->base + offset); -} - static int wmt_gpio_get_value(struct gpio_chip *chip, unsigned offset) { struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev); @@ -568,6 +557,18 @@ static void wmt_gpio_set_value(struct gpio_chip *chip, unsigned offset, wmt_clearbits(data, reg_data_out, BIT(bit)); } +static int wmt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int wmt_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + wmt_gpio_set_value(chip, offset, value); + return pinctrl_gpio_direction_output(chip->base + offset); +} + static struct gpio_chip wmt_gpio_chip = { .label = "gpio-wmt", .owner = THIS_MODULE, |