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-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c154
-rw-r--r--drivers/pinctrl/sirf/pinctrl-prima2.c168
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c352
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.h6
4 files changed, 483 insertions, 197 deletions
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index 1fa39a44417..c4dd3d5cf9c 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -1,7 +1,8 @@
/*
* pinctrl pads, groups, functions for CSR SiRFatlasVI
*
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
+ * company.
*
* Licensed under GPLv2 or later.
*/
@@ -122,6 +123,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
PINCTRL_PIN(100, "ac97_dout"),
PINCTRL_PIN(101, "ac97_din"),
PINCTRL_PIN(102, "x_rtc_io"),
+
+ PINCTRL_PIN(103, "x_usb1_dp"),
+ PINCTRL_PIN(104, "x_usb1_dn"),
};
static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
@@ -139,6 +143,7 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
static const struct sirfsoc_padmux lcd_16bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
.muxmask = lcd_16bits_sirfsoc_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
@@ -164,6 +169,7 @@ static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
static const struct sirfsoc_padmux lcd_18bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
.muxmask = lcd_18bits_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4) | BIT(15),
.funcval = 0,
};
@@ -189,6 +195,7 @@ static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
static const struct sirfsoc_padmux lcd_24bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
.muxmask = lcd_24bits_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4) | BIT(15),
.funcval = 0,
};
@@ -214,6 +221,7 @@ static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
static const struct sirfsoc_padmux lcdrom_padmux = {
.muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
.muxmask = lcdrom_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = BIT(4),
};
@@ -237,6 +245,7 @@ static const struct sirfsoc_muxmask uart0_muxmask[] = {
static const struct sirfsoc_padmux uart0_padmux = {
.muxmask_counts = ARRAY_SIZE(uart0_muxmask),
.muxmask = uart0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(9),
.funcval = BIT(9),
};
@@ -284,6 +293,7 @@ static const struct sirfsoc_muxmask uart2_muxmask[] = {
static const struct sirfsoc_padmux uart2_padmux = {
.muxmask_counts = ARRAY_SIZE(uart2_muxmask),
.muxmask = uart2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(10),
.funcval = BIT(10),
};
@@ -317,6 +327,7 @@ static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
static const struct sirfsoc_padmux sdmmc3_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
.muxmask = sdmmc3_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = 0,
};
@@ -336,6 +347,7 @@ static const struct sirfsoc_muxmask spi0_muxmask[] = {
static const struct sirfsoc_padmux spi0_padmux = {
.muxmask_counts = ARRAY_SIZE(spi0_muxmask),
.muxmask = spi0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = BIT(7),
};
@@ -352,6 +364,7 @@ static const struct sirfsoc_muxmask cko1_muxmask[] = {
static const struct sirfsoc_padmux cko1_padmux = {
.muxmask_counts = ARRAY_SIZE(cko1_muxmask),
.muxmask = cko1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = 0,
};
@@ -371,6 +384,7 @@ static const struct sirfsoc_muxmask i2s_muxmask[] = {
static const struct sirfsoc_padmux i2s_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
@@ -390,6 +404,7 @@ static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
static const struct sirfsoc_padmux i2s_no_din_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
.muxmask = i2s_no_din_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
@@ -409,6 +424,7 @@ static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
static const struct sirfsoc_padmux i2s_6chn_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
.muxmask = i2s_6chn_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(3) | BIT(9),
.funcval = BIT(1) | BIT(3) | BIT(9),
};
@@ -439,6 +455,7 @@ static const struct sirfsoc_muxmask spi1_muxmask[] = {
static const struct sirfsoc_padmux spi1_padmux = {
.muxmask_counts = ARRAY_SIZE(spi1_muxmask),
.muxmask = spi1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = 0,
};
@@ -455,6 +472,7 @@ static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
static const struct sirfsoc_padmux sdmmc1_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
.muxmask = sdmmc1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = BIT(5),
};
@@ -471,6 +489,7 @@ static const struct sirfsoc_muxmask gps_muxmask[] = {
static const struct sirfsoc_padmux gps_padmux = {
.muxmask_counts = ARRAY_SIZE(gps_muxmask),
.muxmask = gps_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13),
.funcval = 0,
};
@@ -487,6 +506,7 @@ static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
static const struct sirfsoc_padmux sdmmc5_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
.muxmask = sdmmc5_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13),
.funcval = BIT(13),
};
@@ -496,19 +516,67 @@ static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask usp0_muxmask[] = {
{
.group = 1,
- .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
+ .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
},
};
static const struct sirfsoc_padmux usp0_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_muxmask),
.muxmask = usp0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(1) | BIT(2) | BIT(9),
+ .funcval = 0,
+};
+
+static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
+
+static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
+ },
+};
+
+static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
+ .muxmask = usp0_only_utfs_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(1) | BIT(2) | BIT(6),
+ .funcval = 0,
+};
+
+static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
+
+static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
+ },
+};
+
+static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
+ .muxmask = usp0_only_urfs_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(9),
.funcval = 0,
};
-static const unsigned usp0_pins[] = { 51, 52, 53, 54 };
+static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
+static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(20) | BIT(21),
+ },
+};
+
+static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
+ .muxmask = usp0_uart_nostreamctrl_muxmask,
+};
+
+static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
static const struct sirfsoc_muxmask usp1_muxmask[] = {
{
.group = 0,
@@ -522,12 +590,30 @@ static const struct sirfsoc_muxmask usp1_muxmask[] = {
static const struct sirfsoc_padmux usp1_padmux = {
.muxmask_counts = ARRAY_SIZE(usp1_muxmask),
.muxmask = usp1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = BIT(16),
};
static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
+static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(12) | BIT(13),
+ },
+};
+
+static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
+ .muxmask = usp1_uart_nostreamctrl_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(16),
+ .funcval = BIT(16),
+};
+
+static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
+
static const struct sirfsoc_muxmask nand_muxmask[] = {
{
.group = 2,
@@ -541,6 +627,7 @@ static const struct sirfsoc_muxmask nand_muxmask[] = {
static const struct sirfsoc_padmux nand_padmux = {
.muxmask_counts = ARRAY_SIZE(nand_muxmask),
.muxmask = nand_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5) | BIT(19),
.funcval = 0,
};
@@ -557,6 +644,7 @@ static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
static const struct sirfsoc_padmux sdmmc0_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
.muxmask = sdmmc0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5) | BIT(19),
.funcval = BIT(19),
};
@@ -573,6 +661,7 @@ static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
static const struct sirfsoc_padmux sdmmc2_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
.muxmask = sdmmc2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = 0,
};
@@ -589,6 +678,7 @@ static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
.muxmask = sdmmc2_nowp_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = 0,
};
@@ -621,6 +711,7 @@ static const struct sirfsoc_muxmask vip_muxmask[] = {
static const struct sirfsoc_padmux vip_padmux = {
.muxmask_counts = ARRAY_SIZE(vip_muxmask),
.muxmask = vip_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(18),
.funcval = BIT(18),
};
@@ -641,6 +732,7 @@ static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
static const struct sirfsoc_padmux vip_noupli_padmux = {
.muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
.muxmask = vip_noupli_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(15),
.funcval = BIT(15),
};
@@ -671,6 +763,7 @@ static const struct sirfsoc_muxmask i2c1_muxmask[] = {
static const struct sirfsoc_padmux i2c1_padmux = {
.muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
.muxmask = i2c1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = 0,
};
@@ -687,6 +780,7 @@ static const struct sirfsoc_muxmask pwm0_muxmask[] = {
static const struct sirfsoc_padmux pwm0_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
.muxmask = pwm0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(12),
.funcval = 0,
};
@@ -759,6 +853,7 @@ static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
static const struct sirfsoc_padmux warm_rst_padmux = {
.muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
.muxmask = warm_rst_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
@@ -776,6 +871,7 @@ static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
.muxmask = usb0_upli_drvbus_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(18),
.funcval = 0,
};
@@ -792,12 +888,31 @@ static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
.muxmask = usb1_utmi_drvbus_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
};
static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
+static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
+ .muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
+ .funcmask = BIT(2),
+ .funcval = BIT(2),
+};
+
+static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
+
+static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
+ .muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
+ .funcmask = BIT(2),
+ .funcval = 0,
+};
+
+static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
+
static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
{
.group = 0,
@@ -818,11 +933,18 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
+ SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
+ SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
+ usp0_uart_nostreamctrl_pins),
+ SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
+ SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
+ SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
+ usp1_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
@@ -843,6 +965,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
+ SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
+ SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
@@ -859,11 +983,19 @@ static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
static const char * const lcdromgrp[] = { "lcdromgrp" };
static const char * const uart0grp[] = { "uart0grp" };
+static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
static const char * const uart1grp[] = { "uart1grp" };
static const char * const uart2grp[] = { "uart2grp" };
static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
+static const char * const usp0_uart_nostreamctrl_grp[] = {
+ "usp0_uart_nostreamctrl_grp" };
static const char * const usp0grp[] = { "usp0grp" };
+static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
+static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
+
static const char * const usp1grp[] = { "usp1grp" };
+static const char * const usp1_uart_nostreamctrl_grp[] = {
+ "usp1_uart_nostreamctrl_grp" };
static const char * const i2c0grp[] = { "i2c0grp" };
static const char * const i2c1grp[] = { "i2c1grp" };
static const char * const pwm0grp[] = { "pwm0grp" };
@@ -884,6 +1016,8 @@ static const char * const sdmmc5grp[] = { "sdmmc5grp" };
static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
+static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
+static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
@@ -900,11 +1034,23 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
+ SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
+ uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
+ SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
+ usp0_uart_nostreamctrl_grp,
+ usp0_uart_nostreamctrl_padmux),
+ SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
+ usp0_only_utfs_padmux),
+ SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
+ usp0_only_urfs_padmux),
SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
+ SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
+ usp1_uart_nostreamctrl_grp,
+ usp1_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
@@ -925,6 +1071,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
+ SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
+ SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
index 1f0ad1ef5a3..8aa76f0776d 100644
--- a/drivers/pinctrl/sirf/pinctrl-prima2.c
+++ b/drivers/pinctrl/sirf/pinctrl-prima2.c
@@ -1,7 +1,8 @@
/*
* pinctrl pads, groups, functions for CSR SiRFprimaII
*
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
+ * company.
*
* Licensed under GPLv2 or later.
*/
@@ -126,6 +127,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
PINCTRL_PIN(112, "x_ldd[13]"),
PINCTRL_PIN(113, "x_ldd[14]"),
PINCTRL_PIN(114, "x_ldd[15]"),
+
+ PINCTRL_PIN(115, "x_usb1_dp"),
+ PINCTRL_PIN(116, "x_usb1_dn"),
};
static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
@@ -143,6 +147,7 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
static const struct sirfsoc_padmux lcd_16bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
.muxmask = lcd_16bits_sirfsoc_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
@@ -168,6 +173,7 @@ static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
static const struct sirfsoc_padmux lcd_18bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
.muxmask = lcd_18bits_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
@@ -193,6 +199,7 @@ static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
static const struct sirfsoc_padmux lcd_24bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
.muxmask = lcd_24bits_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
@@ -218,6 +225,7 @@ static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
static const struct sirfsoc_padmux lcdrom_padmux = {
.muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
.muxmask = lcdrom_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = BIT(4),
};
@@ -238,6 +246,7 @@ static const struct sirfsoc_muxmask uart0_muxmask[] = {
static const struct sirfsoc_padmux uart0_padmux = {
.muxmask_counts = ARRAY_SIZE(uart0_muxmask),
.muxmask = uart0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(9),
.funcval = BIT(9),
};
@@ -282,6 +291,7 @@ static const struct sirfsoc_muxmask uart2_muxmask[] = {
static const struct sirfsoc_padmux uart2_padmux = {
.muxmask_counts = ARRAY_SIZE(uart2_muxmask),
.muxmask = uart2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(10),
.funcval = BIT(10),
};
@@ -315,6 +325,7 @@ static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
static const struct sirfsoc_padmux sdmmc3_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
.muxmask = sdmmc3_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = 0,
};
@@ -331,6 +342,7 @@ static const struct sirfsoc_muxmask spi0_muxmask[] = {
static const struct sirfsoc_padmux spi0_padmux = {
.muxmask_counts = ARRAY_SIZE(spi0_muxmask),
.muxmask = spi0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = BIT(7),
};
@@ -361,6 +373,7 @@ static const struct sirfsoc_muxmask cko1_muxmask[] = {
static const struct sirfsoc_padmux cko1_padmux = {
.muxmask_counts = ARRAY_SIZE(cko1_muxmask),
.muxmask = cko1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = 0,
};
@@ -379,6 +392,7 @@ static const struct sirfsoc_muxmask i2s_muxmask[] = {
static const struct sirfsoc_padmux i2s_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3) | BIT(9),
.funcval = BIT(3),
};
@@ -395,11 +409,12 @@ static const struct sirfsoc_muxmask ac97_muxmask[] = {
static const struct sirfsoc_padmux ac97_padmux = {
.muxmask_counts = ARRAY_SIZE(ac97_muxmask),
.muxmask = ac97_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(8),
.funcval = 0,
};
-static const unsigned ac97_pins[] = { 33, 34, 35, 36 };
+static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
static const struct sirfsoc_muxmask spi1_muxmask[] = {
{
@@ -411,6 +426,7 @@ static const struct sirfsoc_muxmask spi1_muxmask[] = {
static const struct sirfsoc_padmux spi1_padmux = {
.muxmask_counts = ARRAY_SIZE(spi1_muxmask),
.muxmask = spi1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(8),
.funcval = BIT(8),
};
@@ -441,6 +457,7 @@ static const struct sirfsoc_muxmask gps_muxmask[] = {
static const struct sirfsoc_padmux gps_padmux = {
.muxmask_counts = ARRAY_SIZE(gps_muxmask),
.muxmask = gps_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(12) | BIT(13) | BIT(14),
.funcval = BIT(12),
};
@@ -451,23 +468,18 @@ static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
{
.group = 0,
.mask = BIT(24) | BIT(25) | BIT(26),
- }, {
- .group = 1,
- .mask = BIT(29),
- }, {
- .group = 2,
- .mask = BIT(0) | BIT(1),
},
};
static const struct sirfsoc_padmux sdmmc5_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
.muxmask = sdmmc5_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13) | BIT(14),
.funcval = BIT(13) | BIT(14),
};
-static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 };
+static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask usp0_muxmask[] = {
{
@@ -479,12 +491,61 @@ static const struct sirfsoc_muxmask usp0_muxmask[] = {
static const struct sirfsoc_padmux usp0_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_muxmask),
.muxmask = usp0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
.funcval = 0,
};
static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
+static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
+ },
+};
+
+static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
+ .muxmask = usp0_only_utfs_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(1) | BIT(2) | BIT(6),
+ .funcval = 0,
+};
+
+static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
+
+static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
+ },
+};
+
+static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
+ .muxmask = usp0_only_urfs_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(1) | BIT(2) | BIT(9),
+ .funcval = 0,
+};
+
+static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
+
+static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(20) | BIT(21),
+ },
+};
+
+static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
+ .muxmask = usp0_uart_nostreamctrl_muxmask,
+};
+
+static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
+
static const struct sirfsoc_muxmask usp1_muxmask[] = {
{
.group = 1,
@@ -495,12 +556,27 @@ static const struct sirfsoc_muxmask usp1_muxmask[] = {
static const struct sirfsoc_padmux usp1_padmux = {
.muxmask_counts = ARRAY_SIZE(usp1_muxmask),
.muxmask = usp1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
.funcval = 0,
};
static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
+static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(25) | BIT(26),
+ },
+};
+
+static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
+ .muxmask = usp1_uart_nostreamctrl_muxmask,
+};
+
+static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
+
static const struct sirfsoc_muxmask usp2_muxmask[] = {
{
.group = 1,
@@ -514,12 +590,27 @@ static const struct sirfsoc_muxmask usp2_muxmask[] = {
static const struct sirfsoc_padmux usp2_padmux = {
.muxmask_counts = ARRAY_SIZE(usp2_muxmask),
.muxmask = usp2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13) | BIT(14),
.funcval = 0,
};
static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
+static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(30) | BIT(31),
+ },
+};
+
+static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
+ .muxmask = usp2_uart_nostreamctrl_muxmask,
+};
+
+static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
+
static const struct sirfsoc_muxmask nand_muxmask[] = {
{
.group = 2,
@@ -530,6 +621,7 @@ static const struct sirfsoc_muxmask nand_muxmask[] = {
static const struct sirfsoc_padmux nand_padmux = {
.muxmask_counts = ARRAY_SIZE(nand_muxmask),
.muxmask = nand_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = 0,
};
@@ -538,6 +630,7 @@ static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
static const struct sirfsoc_padmux sdmmc0_padmux = {
.muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = 0,
};
@@ -554,6 +647,7 @@ static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
static const struct sirfsoc_padmux sdmmc2_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
.muxmask = sdmmc2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = BIT(5),
};
@@ -586,6 +680,7 @@ static const struct sirfsoc_muxmask vip_muxmask[] = {
static const struct sirfsoc_padmux vip_padmux = {
.muxmask_counts = ARRAY_SIZE(vip_muxmask),
.muxmask = vip_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(0),
.funcval = 0,
};
@@ -635,6 +730,7 @@ static const struct sirfsoc_muxmask viprom_muxmask[] = {
static const struct sirfsoc_padmux viprom_padmux = {
.muxmask_counts = ARRAY_SIZE(viprom_muxmask),
.muxmask = viprom_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(0),
.funcval = BIT(0),
};
@@ -651,6 +747,7 @@ static const struct sirfsoc_muxmask pwm0_muxmask[] = {
static const struct sirfsoc_padmux pwm0_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
.muxmask = pwm0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(12),
.funcval = 0,
};
@@ -722,6 +819,7 @@ static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
.muxmask = usb0_utmi_drvbus_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(6),
.funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
};
@@ -738,12 +836,31 @@ static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
.muxmask = usb1_utmi_drvbus_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
};
static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
+static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
+ .muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
+ .funcmask = BIT(2),
+ .funcval = BIT(2),
+};
+
+static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
+
+static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
+ .muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
+ .funcmask = BIT(2),
+ .funcval = 0,
+};
+
+static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
+
static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
{
.group = 0,
@@ -764,12 +881,21 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
+ SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
+ SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
+ usp0_uart_nostreamctrl_pins),
+ SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
+ SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
+ SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
+ usp1_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
+ SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
+ usp2_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
@@ -789,6 +915,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
+ SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
+ SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
@@ -803,12 +931,21 @@ static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
static const char * const lcdromgrp[] = { "lcdromgrp" };
static const char * const uart0grp[] = { "uart0grp" };
+static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
static const char * const uart1grp[] = { "uart1grp" };
static const char * const uart2grp[] = { "uart2grp" };
static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
static const char * const usp0grp[] = { "usp0grp" };
+static const char * const usp0_uart_nostreamctrl_grp[] =
+ { "usp0_uart_nostreamctrl_grp" };
+static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
+static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
static const char * const usp1grp[] = { "usp1grp" };
+static const char * const usp1_uart_nostreamctrl_grp[] =
+ { "usp1_uart_nostreamctrl_grp" };
static const char * const usp2grp[] = { "usp2grp" };
+static const char * const usp2_uart_nostreamctrl_grp[] =
+ { "usp2_uart_nostreamctrl_grp" };
static const char * const i2c0grp[] = { "i2c0grp" };
static const char * const i2c1grp[] = { "i2c1grp" };
static const char * const pwm0grp[] = { "pwm0grp" };
@@ -828,6 +965,8 @@ static const char * const sdmmc4grp[] = { "sdmmc4grp" };
static const char * const sdmmc5grp[] = { "sdmmc5grp" };
static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
+static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
+static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
static const char * const ac97grp[] = { "ac97grp" };
@@ -842,12 +981,21 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
+ SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
+ SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
+ usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
+ SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux),
+ SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux),
SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
+ SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
+ usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
+ SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
+ usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
@@ -867,6 +1015,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
+ SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
+ SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 0677e198db6..014f5b1fee5 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -1,7 +1,8 @@
/*
* pinmux driver for CSR SiRFprimaII
*
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
+ * company.
*
* Licensed under GPLv2 or later.
*/
@@ -13,8 +14,6 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip/chained_irq.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
@@ -26,22 +25,23 @@
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
-#include <asm/mach/irq.h>
#include "pinctrl-sirf.h"
#define DRIVER_NAME "pinmux-sirf"
struct sirfsoc_gpio_bank {
- struct of_mm_gpio_chip chip;
- struct irq_domain *domain;
int id;
int parent_irq;
spinlock_t lock;
+};
+
+struct sirfsoc_gpio_chip {
+ struct of_mm_gpio_chip chip;
bool is_marco; /* for marco, some registers are different with prima2 */
+ struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
};
-static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
static DEFINE_SPINLOCK(sgpio_lock);
static struct sirfsoc_pin_group *sirfsoc_pin_groups;
@@ -166,12 +166,12 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector
if (mux->funcmask && enable) {
u32 func_en_val;
+
func_en_val =
- readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
+ readl(spmx->rsc_virtbase + mux->ctrlreg);
func_en_val =
- (func_en_val & ~mux->funcmask) | (mux->
- funcval);
- writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
+ (func_en_val & ~mux->funcmask) | (mux->funcval);
+ writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
}
}
@@ -254,37 +254,6 @@ static struct pinctrl_desc sirfsoc_pinmux_desc = {
.owner = THIS_MODULE,
};
-/*
- * Todo: bind irq_chip to every pinctrl_gpio_range
- */
-static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
- {
- .name = "sirfsoc-gpio*",
- .id = 0,
- .base = 0,
- .pin_base = 0,
- .npins = 32,
- }, {
- .name = "sirfsoc-gpio*",
- .id = 1,
- .base = 32,
- .pin_base = 32,
- .npins = 32,
- }, {
- .name = "sirfsoc-gpio*",
- .id = 2,
- .base = 64,
- .pin_base = 64,
- .npins = 32,
- }, {
- .name = "sirfsoc-gpio*",
- .id = 3,
- .base = 96,
- .pin_base = 96,
- .npins = 19,
- },
-};
-
static void __iomem *sirfsoc_rsc_of_iomap(void)
{
const struct of_device_id rsc_ids[] = {
@@ -302,19 +271,16 @@ static void __iomem *sirfsoc_rsc_of_iomap(void)
}
static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
- const struct of_phandle_args *gpiospec,
- u32 *flags)
+ const struct of_phandle_args *gpiospec,
+ u32 *flags)
{
- if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
- return -EINVAL;
-
- if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
- return -EINVAL;
+ if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
+ return -EINVAL;
- if (flags)
- *flags = gpiospec->args[1];
+ if (flags)
+ *flags = gpiospec->args[1];
- return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
+ return gpiospec->args[0];
}
static const struct of_device_id pinmux_ids[] = {
@@ -330,7 +296,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev)
struct sirfsoc_pmx *spmx;
struct device_node *np = pdev->dev.of_node;
const struct sirfsoc_pinctrl_data *pdata;
- int i;
/* Create state holders etc for this driver */
spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
@@ -374,11 +339,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev)
goto out_no_pmx;
}
- for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
- sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
- pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
- }
-
dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
return 0;
@@ -440,6 +400,8 @@ static int sirfsoc_pinmux_resume_noirq(struct device *dev)
static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
.suspend_noirq = sirfsoc_pinmux_suspend_noirq,
.resume_noirq = sirfsoc_pinmux_resume_noirq,
+ .freeze_noirq = sirfsoc_pinmux_suspend_noirq,
+ .restore_noirq = sirfsoc_pinmux_resume_noirq,
};
#endif
@@ -461,33 +423,28 @@ static int __init sirfsoc_pinmux_init(void)
}
arch_initcall(sirfsoc_pinmux_init);
-static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
- struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
- struct sirfsoc_gpio_bank, chip);
-
- return irq_create_mapping(bank->domain, offset);
-}
-
-static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
+static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc)
{
- return gpio % SIRFSOC_GPIO_BANK_SIZE;
+ return container_of(gc, struct sirfsoc_gpio_chip, chip.gc);
}
-static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
+static inline struct sirfsoc_gpio_bank *
+sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
{
- return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
+ return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
}
-static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
+static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
{
- return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
+ return offset % SIRFSOC_GPIO_BANK_SIZE;
}
static void sirfsoc_gpio_irq_ack(struct irq_data *d)
{
- struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
- int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
+ int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
u32 val, offset;
unsigned long flags;
@@ -495,14 +452,16 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d)
spin_lock_irqsave(&sgpio_lock, flags);
- val = readl(bank->chip.regs + offset);
+ val = readl(sgpio->chip.regs + offset);
- writel(val, bank->chip.regs + offset);
+ writel(val, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&sgpio_lock, flags);
}
-static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
+static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
+ struct sirfsoc_gpio_bank *bank,
+ int idx)
{
u32 val, offset;
unsigned long flags;
@@ -511,25 +470,29 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
spin_lock_irqsave(&sgpio_lock, flags);
- val = readl(bank->chip.regs + offset);
+ val = readl(sgpio->chip.regs + offset);
val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
- writel(val, bank->chip.regs + offset);
+ writel(val, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&sgpio_lock, flags);
}
static void sirfsoc_gpio_irq_mask(struct irq_data *d)
{
- struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
- __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
+ __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
}
static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
{
- struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
- int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
+ int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
u32 val, offset;
unsigned long flags;
@@ -537,18 +500,20 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
spin_lock_irqsave(&sgpio_lock, flags);
- val = readl(bank->chip.regs + offset);
+ val = readl(sgpio->chip.regs + offset);
val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
- writel(val, bank->chip.regs + offset);
+ writel(val, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&sgpio_lock, flags);
}
static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
{
- struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
- int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
+ int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
u32 val, offset;
unsigned long flags;
@@ -556,8 +521,8 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
spin_lock_irqsave(&sgpio_lock, flags);
- val = readl(bank->chip.regs + offset);
- val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
+ val = readl(sgpio->chip.regs + offset);
+ val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
switch (type) {
case IRQ_TYPE_NONE:
@@ -584,7 +549,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
break;
}
- writel(val, bank->chip.regs + offset);
+ writel(val, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&sgpio_lock, flags);
@@ -601,14 +566,24 @@ static struct irq_chip sirfsoc_irq_chip = {
static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
{
- struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
+ struct sirfsoc_gpio_bank *bank;
u32 status, ctrl;
int idx = 0;
struct irq_chip *chip = irq_get_chip(irq);
+ int i;
+
+ for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
+ bank = &sgpio->sgpio_bank[i];
+ if (bank->parent_irq == irq)
+ break;
+ }
+ BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
chained_irq_enter(chip, desc);
- status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
+ status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
if (!status) {
printk(KERN_WARNING
"%s: gpio id %d status %#x no interrupt is flaged\n",
@@ -618,7 +593,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
}
while (status) {
- ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
+ ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
/*
* Here we must check whether the corresponding GPIO's interrupt
@@ -627,7 +602,8 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
pr_debug("%s: gpio id %d idx %d happens\n",
__func__, bank->id, idx);
- generic_handle_irq(irq_find_mapping(bank->domain, idx));
+ generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
+ bank->id * SIRFSOC_GPIO_BANK_SIZE));
}
idx++;
@@ -637,18 +613,20 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
+static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
+ unsigned ctrl_offset)
{
u32 val;
- val = readl(bank->chip.regs + ctrl_offset);
+ val = readl(sgpio->chip.regs + ctrl_offset);
val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
- writel(val, bank->chip.regs + ctrl_offset);
+ writel(val, sgpio->chip.regs + ctrl_offset);
}
static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
{
- struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
unsigned long flags;
if (pinctrl_request_gpio(chip->base + offset))
@@ -660,8 +638,8 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
* default status:
* set direction as input and mask irq
*/
- sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
- __sirfsoc_gpio_irq_mask(bank, offset);
+ sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
+ __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
spin_unlock_irqrestore(&bank->lock, flags);
@@ -670,13 +648,14 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
{
- struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
- __sirfsoc_gpio_irq_mask(bank, offset);
- sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
+ __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
+ sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
spin_unlock_irqrestore(&bank->lock, flags);
@@ -685,8 +664,9 @@ static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
- struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
- int idx = sirfsoc_gpio_to_offset(gpio);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
+ int idx = sirfsoc_gpio_to_bankoff(gpio);
unsigned long flags;
unsigned offset;
@@ -694,22 +674,24 @@ static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
spin_lock_irqsave(&bank->lock, flags);
- sirfsoc_gpio_set_input(bank, offset);
+ sirfsoc_gpio_set_input(sgpio, offset);
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
-static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
- int value)
+static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
+ struct sirfsoc_gpio_bank *bank,
+ unsigned offset,
+ int value)
{
u32 out_ctrl;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
- out_ctrl = readl(bank->chip.regs + offset);
+ out_ctrl = readl(sgpio->chip.regs + offset);
if (value)
out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
else
@@ -717,15 +699,16 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsig
out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
- writel(out_ctrl, bank->chip.regs + offset);
+ writel(out_ctrl, sgpio->chip.regs + offset);
spin_unlock_irqrestore(&bank->lock, flags);
}
static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
{
- struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
- int idx = sirfsoc_gpio_to_offset(gpio);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
+ int idx = sirfsoc_gpio_to_bankoff(gpio);
u32 offset;
unsigned long flags;
@@ -733,7 +716,7 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
spin_lock_irqsave(&sgpio_lock, flags);
- sirfsoc_gpio_set_output(bank, offset, value);
+ sirfsoc_gpio_set_output(sgpio, bank, offset, value);
spin_unlock_irqrestore(&sgpio_lock, flags);
@@ -742,13 +725,14 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
{
- struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
u32 val;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
- val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
+ val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
spin_unlock_irqrestore(&bank->lock, flags);
@@ -758,44 +742,25 @@ static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
int value)
{
- struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+ struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
+ struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
u32 ctrl;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
- ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
+ ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
if (value)
ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
else
ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
- writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
+ writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
spin_unlock_irqrestore(&bank->lock, flags);
}
-static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hwirq)
-{
- struct sirfsoc_gpio_bank *bank = d->host_data;
-
- if (!bank)
- return -EINVAL;
-
- irq_set_chip(irq, &sirfsoc_irq_chip);
- irq_set_handler(irq, handle_level_irq);
- irq_set_chip_data(irq, bank);
- set_irq_flags(irq, IRQF_VALID);
-
- return 0;
-}
-
-static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
- .map = sirfsoc_gpio_irq_map,
- .xlate = irq_domain_xlate_twocell,
-};
-
-static void sirfsoc_gpio_set_pullup(const u32 *pullups)
+static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
+ const u32 *pullups)
{
int i, n;
const unsigned long *p = (const unsigned long *)pullups;
@@ -803,15 +768,16 @@ static void sirfsoc_gpio_set_pullup(const u32 *pullups)
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
for_each_set_bit(n, p + i, BITS_PER_LONG) {
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
- u32 val = readl(sgpio_bank[i].chip.regs + offset);
+ u32 val = readl(sgpio->chip.regs + offset);
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
- writel(val, sgpio_bank[i].chip.regs + offset);
+ writel(val, sgpio->chip.regs + offset);
}
}
}
-static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
+static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
+ const u32 *pulldowns)
{
int i, n;
const unsigned long *p = (const unsigned long *)pulldowns;
@@ -819,10 +785,10 @@ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
for_each_set_bit(n, p + i, BITS_PER_LONG) {
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
- u32 val = readl(sgpio_bank[i].chip.regs + offset);
+ u32 val = readl(sgpio->chip.regs + offset);
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
- writel(val, sgpio_bank[i].chip.regs + offset);
+ writel(val, sgpio->chip.regs + offset);
}
}
}
@@ -830,8 +796,9 @@ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
static int sirfsoc_gpio_probe(struct device_node *np)
{
int i, err = 0;
+ static struct sirfsoc_gpio_chip *sgpio;
struct sirfsoc_gpio_bank *bank;
- void *regs;
+ void __iomem *regs;
struct platform_device *pdev;
bool is_marco = false;
@@ -841,6 +808,10 @@ static int sirfsoc_gpio_probe(struct device_node *np)
if (!pdev)
return -ENODEV;
+ sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
+ if (!sgpio)
+ return -ENOMEM;
+
regs = of_iomap(np, 0);
if (!regs)
return -ENOMEM;
@@ -848,61 +819,76 @@ static int sirfsoc_gpio_probe(struct device_node *np)
if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
is_marco = 1;
+ sgpio->chip.gc.request = sirfsoc_gpio_request;
+ sgpio->chip.gc.free = sirfsoc_gpio_free;
+ sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
+ sgpio->chip.gc.get = sirfsoc_gpio_get_value;
+ sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
+ sgpio->chip.gc.set = sirfsoc_gpio_set_value;
+ sgpio->chip.gc.base = 0;
+ sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
+ sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
+ sgpio->chip.gc.of_node = np;
+ sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
+ sgpio->chip.gc.of_gpio_n_cells = 2;
+ sgpio->chip.gc.dev = &pdev->dev;
+ sgpio->chip.regs = regs;
+ sgpio->is_marco = is_marco;
+
+ err = gpiochip_add(&sgpio->chip.gc);
+ if (err) {
+ dev_err(&pdev->dev, "%s: error in probe function with status %d\n",
+ np->full_name, err);
+ goto out;
+ }
+
+ err = gpiochip_irqchip_add(&sgpio->chip.gc,
+ &sirfsoc_irq_chip,
+ 0, handle_level_irq,
+ IRQ_TYPE_NONE);
+ if (err) {
+ dev_err(&pdev->dev,
+ "could not connect irqchip to gpiochip\n");
+ goto out;
+ }
+
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
- bank = &sgpio_bank[i];
+ bank = &sgpio->sgpio_bank[i];
spin_lock_init(&bank->lock);
- bank->chip.gc.request = sirfsoc_gpio_request;
- bank->chip.gc.free = sirfsoc_gpio_free;
- bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
- bank->chip.gc.get = sirfsoc_gpio_get_value;
- bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
- bank->chip.gc.set = sirfsoc_gpio_set_value;
- bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
- bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
- bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
- bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
- bank->chip.gc.of_node = np;
- bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
- bank->chip.gc.of_gpio_n_cells = 2;
- bank->chip.regs = regs;
- bank->id = i;
- bank->is_marco = is_marco;
bank->parent_irq = platform_get_irq(pdev, i);
if (bank->parent_irq < 0) {
err = bank->parent_irq;
- goto out;
+ goto out_banks;
}
- err = gpiochip_add(&bank->chip.gc);
- if (err) {
- pr_err("%s: error in probe function with status %d\n",
- np->full_name, err);
- goto out;
- }
-
- bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
- &sirfsoc_gpio_irq_simple_ops, bank);
-
- if (!bank->domain) {
- pr_err("%s: Failed to create irqdomain\n", np->full_name);
- err = -ENOSYS;
- goto out;
- }
+ gpiochip_set_chained_irqchip(&sgpio->chip.gc,
+ &sirfsoc_irq_chip,
+ bank->parent_irq,
+ sirfsoc_gpio_handle_irq);
+ }
- irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
- irq_set_handler_data(bank->parent_irq, bank);
+ err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
+ 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
+ if (err) {
+ dev_err(&pdev->dev,
+ "could not add gpiochip pin range\n");
+ goto out_no_range;
}
if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
SIRFSOC_GPIO_NO_OF_BANKS))
- sirfsoc_gpio_set_pullup(pullups);
+ sirfsoc_gpio_set_pullup(sgpio, pullups);
if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
SIRFSOC_GPIO_NO_OF_BANKS))
- sirfsoc_gpio_set_pulldown(pulldowns);
+ sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
return 0;
+out_no_range:
+out_banks:
+ if (gpiochip_remove(&sgpio->chip.gc))
+ dev_err(&pdev->dev, "could not remove gpio chip\n");
out:
iounmap(regs);
return err;
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h
index 17cc108510b..d7f16b499ad 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.h
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.h
@@ -9,8 +9,9 @@
#ifndef __PINMUX_SIRF_H__
#define __PINMUX_SIRF_H__
-#define SIRFSOC_NUM_PADS 622
-#define SIRFSOC_RSC_PIN_MUX 0x4
+#define SIRFSOC_NUM_PADS 622
+#define SIRFSOC_RSC_USB_UART_SHARE 0
+#define SIRFSOC_RSC_PIN_MUX 0x4
#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
@@ -61,6 +62,7 @@ struct sirfsoc_padmux {
unsigned long muxmask_counts;
const struct sirfsoc_muxmask *muxmask;
/* RSC_PIN_MUX set */
+ unsigned long ctrlreg;
unsigned long funcmask;
unsigned long funcval;
};
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-11-10 01:24:56 +0000