diff options
Diffstat (limited to 'drivers/net/wan/ixp4xx_hss.c')
| -rw-r--r-- | drivers/net/wan/ixp4xx_hss.c | 158 |
1 files changed, 123 insertions, 35 deletions
diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c index 765a7f5d6aa..e7bbdb7af53 100644 --- a/drivers/net/wan/ixp4xx_hss.c +++ b/drivers/net/wan/ixp4xx_hss.c @@ -8,6 +8,9 @@ * as published by the Free Software Foundation. */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/module.h> #include <linux/bitops.h> #include <linux/cdev.h> #include <linux/dma-mapping.h> @@ -18,6 +21,7 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/poll.h> +#include <linux/slab.h> #include <mach/npe.h> #include <mach/qmgr.h> @@ -166,6 +170,29 @@ #define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023) #define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047) +/* + * HSS_CONFIG_CLOCK_CR register consists of 3 parts: + * A (10 bits), B (10 bits) and C (12 bits). + * IXP42x HSS clock generator operation (verified with an oscilloscope): + * Each clock bit takes 7.5 ns (1 / 133.xx MHz). + * The clock sequence consists of (C - B) states of 0s and 1s, each state is + * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is + * (A + 1) bits wide. + * + * The resulting average clock frequency (assuming 33.333 MHz oscillator) is: + * freq = 66.666 MHz / (A + (B + 1) / (C + 1)) + * minimum freq = 66.666 MHz / (A + 1) + * maximum freq = 66.666 MHz / A + * + * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7 + * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s). + * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples). + * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits + * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats). + * The sequence consists of 4 complete clock periods, thus the average + * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s). + * (max specified clock rate for IXP42x HSS is 8.192 Mb/s). + */ /* hss_config, LUT entries */ #define TDMMAP_UNASSIGNED 0 @@ -206,7 +233,7 @@ #define PKT_PIPE_MODE_WRITE 0x57 /* HDLC packet status values - desc->status */ -#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */ +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */ #define ERR_HDLC_ALIGN 2 /* HDLC alignment error */ #define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */ #define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving @@ -239,6 +266,7 @@ struct port { unsigned int clock_type, clock_rate, loopback; unsigned int initialized, carrier; u8 hdlc_cfg; + u32 clock_reg; }; /* NPE message structure */ @@ -333,9 +361,8 @@ static void hss_npe_send(struct port *port, struct msg *msg, const char* what) { u32 *val = (u32*)msg; if (npe_send_message(port->npe, msg, what)) { - printk(KERN_CRIT "HSS-%i: unable to send command [%08X:%08X]" - " to %s\n", port->id, val[0], val[1], - npe_name(port->npe)); + pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n", + port->id, val[0], val[1], npe_name(port->npe)); BUG(); } } @@ -371,7 +398,7 @@ static void hss_config(struct port *port) msg.cmd = PORT_CONFIG_WRITE; msg.hss_port = port->id; msg.index = HSS_CONFIG_TX_PCR; - msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN | + msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN | PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT; if (port->clock_type == CLOCK_INT) msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT; @@ -393,7 +420,7 @@ static void hss_config(struct port *port) msg.cmd = PORT_CONFIG_WRITE; msg.hss_port = port->id; msg.index = HSS_CONFIG_CLOCK_CR; - msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */; + msg.data32 = port->clock_reg; hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR"); memset(&msg, 0, sizeof(msg)); @@ -422,8 +449,7 @@ static void hss_config(struct port *port) if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") || /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */ msg.cmd != PORT_CONFIG_LOAD || msg.data32) { - printk(KERN_CRIT "HSS-%i: HSS_LOAD_CONFIG failed\n", - port->id); + pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id); BUG(); } @@ -452,8 +478,7 @@ static u32 hss_get_status(struct port *port) msg.hss_port = port->id; hss_npe_send(port, &msg, "PORT_ERROR_READ"); if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) { - printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", - port->id); + pr_crit("HSS-%i: unable to read HSS status\n", port->id); BUG(); } @@ -579,7 +604,8 @@ static inline void queue_put_desc(unsigned int queue, u32 phys, debug_desc(phys, desc); BUG_ON(phys & 0x1F); qmgr_put_entry(queue, phys); - BUG_ON(qmgr_stat_overflow(queue)); + /* Don't check for queue overflow here, we've allocated sufficient + length and queues >= 32 don't support this check anyway. */ } @@ -710,9 +736,8 @@ static int hss_hdlc_poll(struct napi_struct *napi, int budget) dev->stats.rx_errors++; break; default: /* FIXME - remove printk */ - printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X" - " errors %u\n", dev->name, desc->status, - desc->error_count); + netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n", + desc->status, desc->error_count); dev->stats.rx_errors++; } @@ -731,8 +756,8 @@ static int hss_hdlc_poll(struct napi_struct *napi, int budget) dma_unmap_single(&dev->dev, desc->data, RX_SIZE, DMA_FROM_DEVICE); #else - dma_sync_single(&dev->dev, desc->data, - RX_SIZE, DMA_FROM_DEVICE); + dma_sync_single_for_cpu(&dev->dev, desc->data, + RX_SIZE, DMA_FROM_DEVICE); memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], ALIGN(desc->pkt_len, 4) / 4); #endif @@ -789,10 +814,10 @@ static void hss_hdlc_txdone_irq(void *pdev) free_buffer_irq(port->tx_buff_tab[n_desc]); port->tx_buff_tab[n_desc] = NULL; - start = qmgr_stat_empty(port->plat->txreadyq); + start = qmgr_stat_below_low_watermark(port->plat->txreadyq); queue_put_desc(port->plat->txreadyq, tx_desc_phys(port, n_desc), desc); - if (start) { + if (start) { /* TX-ready queue was empty */ #if DEBUG_TX printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit" " ready\n", dev->name); @@ -865,15 +890,14 @@ static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev) wmb(); queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc); - dev->trans_start = jiffies; - if (qmgr_stat_empty(txreadyq)) { + if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ #if DEBUG_TX printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name); #endif netif_stop_queue(dev); /* we could miss TX ready interrupt */ - if (!qmgr_stat_empty(txreadyq)) { + if (!qmgr_stat_below_low_watermark(txreadyq)) { #if DEBUG_TX printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n", dev->name); @@ -945,10 +969,12 @@ static int init_hdlc_queues(struct port *port) { int i; - if (!ports_open) - if (!(dma_pool = dma_pool_create(DRV_NAME, NULL, - POOL_ALLOC_SIZE, 32, 0))) + if (!ports_open) { + dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, + POOL_ALLOC_SIZE, 32, 0); + if (!dma_pool) return -ENOMEM; + } if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, &port->desc_tab_phys))) @@ -1102,8 +1128,8 @@ static int hss_hdlc_close(struct net_device *dev) buffs--; if (buffs) - printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" - " left in NPE\n", dev->name, buffs); + netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n", + buffs); buffs = TX_DESCS; while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0) @@ -1118,8 +1144,8 @@ static int hss_hdlc_close(struct net_device *dev) } while (++i < MAX_CLOSE_WAIT); if (buffs) - printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " - "left in NPE\n", dev->name, buffs); + netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n", + buffs); #if DEBUG_CLOSE if (!buffs) printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); @@ -1159,6 +1185,62 @@ static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding, } } +static u32 check_clock(u32 rate, u32 a, u32 b, u32 c, + u32 *best, u32 *best_diff, u32 *reg) +{ + /* a is 10-bit, b is 10-bit, c is 12-bit */ + u64 new_rate; + u32 new_diff; + + new_rate = ixp4xx_timer_freq * (u64)(c + 1); + do_div(new_rate, a * (c + 1) + b + 1); + new_diff = abs((u32)new_rate - rate); + + if (new_diff < *best_diff) { + *best = new_rate; + *best_diff = new_diff; + *reg = (a << 22) | (b << 12) | c; + } + return new_diff; +} + +static void find_best_clock(u32 rate, u32 *best, u32 *reg) +{ + u32 a, b, diff = 0xFFFFFFFF; + + a = ixp4xx_timer_freq / rate; + + if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */ + check_clock(rate, 0x3FF, 1, 1, best, &diff, reg); + return; + } + if (a == 0) { /* > 66.666 MHz */ + a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */ + rate = ixp4xx_timer_freq; + } + + if (rate * a == ixp4xx_timer_freq) { /* don't divide by 0 later */ + check_clock(rate, a - 1, 1, 1, best, &diff, reg); + return; + } + + for (b = 0; b < 0x400; b++) { + u64 c = (b + 1) * (u64)rate; + do_div(c, ixp4xx_timer_freq - rate * a); + c--; + if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */ + if (b == 0 && /* also try a bit higher rate */ + !check_clock(rate, a - 1, 1, 1, best, &diff, reg)) + return; + check_clock(rate, a, b, 0xFFF, best, &diff, reg); + return; + } + if (!check_clock(rate, a, b, c, best, &diff, reg)) + return; + if (!check_clock(rate, a, b, c + 1, best, &diff, reg)) + return; + } +} static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { @@ -1181,7 +1263,7 @@ static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) } memset(&new_line, 0, sizeof(new_line)); new_line.clock_type = port->clock_type; - new_line.clock_rate = 2048000; /* FIXME */ + new_line.clock_rate = port->clock_rate; new_line.loopback = port->loopback; if (copy_to_user(line, &new_line, size)) return -EFAULT; @@ -1205,7 +1287,13 @@ static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) return -EINVAL; port->clock_type = clk; /* Update settings */ - /* FIXME port->clock_rate = new_line.clock_rate */; + if (clk == CLOCK_INT) + find_best_clock(new_line.clock_rate, &port->clock_rate, + &port->clock_reg); + else { + port->clock_rate = 0; + port->clock_reg = CLK42X_SPEED_2048KHZ; + } port->loopback = new_line.loopback; spin_lock_irqsave(&npe_lock, flags); @@ -1238,7 +1326,7 @@ static const struct net_device_ops hss_hdlc_ops = { .ndo_do_ioctl = hss_hdlc_ioctl, }; -static int __devinit hss_init_one(struct platform_device *pdev) +static int hss_init_one(struct platform_device *pdev) { struct port *port; struct net_device *dev; @@ -1265,7 +1353,8 @@ static int __devinit hss_init_one(struct platform_device *pdev) dev->netdev_ops = &hss_hdlc_ops; dev->tx_queue_len = 100; port->clock_type = CLOCK_EXT; - port->clock_rate = 2048000; + port->clock_rate = 0; + port->clock_reg = CLK42X_SPEED_2048KHZ; port->id = pdev->id; port->dev = &pdev->dev; port->plat = pdev->dev.platform_data; @@ -1276,7 +1365,7 @@ static int __devinit hss_init_one(struct platform_device *pdev) platform_set_drvdata(pdev, port); - printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id); + netdev_info(dev, "initialized\n"); return 0; err_free_netdev: @@ -1288,14 +1377,13 @@ err_free: return err; } -static int __devexit hss_remove_one(struct platform_device *pdev) +static int hss_remove_one(struct platform_device *pdev) { struct port *port = platform_get_drvdata(pdev); unregister_hdlc_device(port->netdev); free_netdev(port->netdev); npe_release(port->npe); - platform_set_drvdata(pdev, NULL); kfree(port); return 0; } |