diff options
Diffstat (limited to 'drivers/net/s2io.h')
| -rw-r--r-- | drivers/net/s2io.h | 364 | 
1 files changed, 249 insertions, 115 deletions
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h index 1711c8c3dc9..5d9270730ca 100644 --- a/drivers/net/s2io.h +++ b/drivers/net/s2io.h @@ -31,6 +31,9 @@  #define SUCCESS 0  #define FAILURE -1 +/* Maximum time to flicker LED when asked to identify NIC using ethtool */ +#define MAX_FLICKER_TIME	60000 /* 60 Secs */ +  /* Maximum outstanding splits to be configured into xena. */  typedef enum xena_max_outstanding_splits {  	XENA_ONE_SPLIT_TRANSACTION = 0, @@ -45,10 +48,10 @@ typedef enum xena_max_outstanding_splits {  #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)  /*  OS concerned variables and constants */ -#define WATCH_DOG_TIMEOUT   	5*HZ -#define EFILL       			0x1234 -#define ALIGN_SIZE  			127 -#define	PCIX_COMMAND_REGISTER	0x62 +#define WATCH_DOG_TIMEOUT		15*HZ +#define EFILL				0x1234 +#define ALIGN_SIZE			127 +#define	PCIX_COMMAND_REGISTER		0x62  /*   * Debug related variables. @@ -61,7 +64,7 @@ typedef enum xena_max_outstanding_splits {  #define	INTR_DBG	4  /* Global variable that defines the present debug level of the driver. */ -static int debug_level = ERR_DBG;	/* Default level. */ +int debug_level = ERR_DBG;	/* Default level. */  /* DEBUG message print. */  #define DBG_PRINT(dbg_level, args...)  if(!(debug_level<dbg_level)) printk(args) @@ -71,6 +74,12 @@ static int debug_level = ERR_DBG;	/* Default level. */  #define L4_CKSUM_OK 0xFFFF  #define S2IO_JUMBO_SIZE 9600 +/* Driver statistics maintained by driver */ +typedef struct { +	unsigned long long single_ecc_errs; +	unsigned long long double_ecc_errs; +} swStat_t; +  /* The statistics block of Xena */  typedef struct stat_block {  /* Tx MAC statistics counters. */ @@ -186,12 +195,90 @@ typedef struct stat_block {  	u32 rxd_rd_cnt;  	u32 rxf_wr_cnt;  	u32 txf_rd_cnt; + +/* Tx MAC statistics overflow counters. */ +	u32 tmac_data_octets_oflow; +	u32 tmac_frms_oflow; +	u32 tmac_bcst_frms_oflow; +	u32 tmac_mcst_frms_oflow; +	u32 tmac_ucst_frms_oflow; +	u32 tmac_ttl_octets_oflow; +	u32 tmac_any_err_frms_oflow; +	u32 tmac_nucst_frms_oflow; +	u64 tmac_vlan_frms; +	u32 tmac_drop_ip_oflow; +	u32 tmac_vld_ip_oflow; +	u32 tmac_rst_tcp_oflow; +	u32 tmac_icmp_oflow; +	u32 tpa_unknown_protocol; +	u32 tmac_udp_oflow; +	u32 reserved_10; +	u32 tpa_parse_failure; + +/* Rx MAC Statistics overflow counters. */ +	u32 rmac_data_octets_oflow; +	u32 rmac_vld_frms_oflow; +	u32 rmac_vld_bcst_frms_oflow; +	u32 rmac_vld_mcst_frms_oflow; +	u32 rmac_accepted_ucst_frms_oflow; +	u32 rmac_ttl_octets_oflow; +	u32 rmac_discarded_frms_oflow; +	u32 rmac_accepted_nucst_frms_oflow; +	u32 rmac_usized_frms_oflow; +	u32 rmac_drop_events_oflow; +	u32 rmac_frag_frms_oflow; +	u32 rmac_osized_frms_oflow; +	u32 rmac_ip_oflow; +	u32 rmac_jabber_frms_oflow; +	u32 rmac_icmp_oflow; +	u32 rmac_drop_ip_oflow; +	u32 rmac_err_drp_udp_oflow; +	u32 rmac_udp_oflow; +	u32 reserved_11; +	u32 rmac_pause_cnt_oflow; +	u64 rmac_ttl_1519_4095_frms; +	u64 rmac_ttl_4096_8191_frms; +	u64 rmac_ttl_8192_max_frms; +	u64 rmac_ttl_gt_max_frms; +	u64 rmac_osized_alt_frms; +	u64 rmac_jabber_alt_frms; +	u64 rmac_gt_max_alt_frms; +	u64 rmac_vlan_frms; +	u32 rmac_len_discard; +	u32 rmac_fcs_discard; +	u32 rmac_pf_discard; +	u32 rmac_da_discard; +	u32 rmac_red_discard; +	u32 rmac_rts_discard; +	u32 reserved_12; +	u32 rmac_ingm_full_discard; +	u32 reserved_13; +	u32 rmac_accepted_ip_oflow; +	u32 reserved_14; +	u32 link_fault_cnt; +	swStat_t sw_stat;  } StatInfo_t; -/* Structures representing different init time configuration +/* + * Structures representing different init time configuration   * parameters of the NIC.   */ +#define MAX_TX_FIFOS 8 +#define MAX_RX_RINGS 8 + +/* FIFO mappings for all possible number of fifos configured */ +int fifo_map[][MAX_TX_FIFOS] = { +	{0, 0, 0, 0, 0, 0, 0, 0}, +	{0, 0, 0, 0, 1, 1, 1, 1}, +	{0, 0, 0, 1, 1, 1, 2, 2}, +	{0, 0, 1, 1, 2, 2, 3, 3}, +	{0, 0, 1, 1, 2, 2, 3, 4}, +	{0, 0, 1, 1, 2, 3, 4, 5}, +	{0, 0, 1, 2, 3, 4, 5, 6}, +	{0, 1, 2, 3, 4, 5, 6, 7}, +}; +  /* Maintains Per FIFO related information. */  typedef struct tx_fifo_config {  #define	MAX_AVAILABLE_TXDS	8192 @@ -237,14 +324,14 @@ typedef struct rx_ring_config {  #define NO_SNOOP_RXD_BUFFER         0x02  } rx_ring_config_t; -/* This structure provides contains values of the tunable parameters  - * of the H/W  +/* This structure provides contains values of the tunable parameters + * of the H/W   */  struct config_param {  /* Tx Side */  	u32 tx_fifo_num;	/*Number of Tx FIFOs */ -#define MAX_TX_FIFOS 8 +	u8 fifo_mapping[MAX_TX_FIFOS];  	tx_fifo_config_t tx_cfg[MAX_TX_FIFOS];	/*Per-Tx FIFO config */  	u32 max_txds;		/*Max no. of Tx buffer descriptor per TxDL */  	u64 tx_intr_type; @@ -252,10 +339,10 @@ struct config_param {  /* Rx Side */  	u32 rx_ring_num;	/*Number of receive rings */ -#define MAX_RX_RINGS 8  #define MAX_RX_BLOCKS_PER_RING  150  	rx_ring_config_t rx_cfg[MAX_RX_RINGS];	/*Per-Rx Ring config */ +	u8 bimodal;		/*Flag for setting bimodal interrupts*/  #define HEADER_ETHERNET_II_802_3_SIZE 14  #define HEADER_802_2_SIZE              3 @@ -269,6 +356,7 @@ struct config_param {  #define MAX_PYLD_JUMBO              9600  #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)  #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22) +	u16 bus_speed;  };  /* Structure representing MAC Addrs */ @@ -277,7 +365,7 @@ typedef struct mac_addr {  } macaddr_t;  /* Structure that represent every FIFO element in the BAR1 - * Address location.  + * Address location.   */  typedef struct _TxFIFO_element {  	u64 TxDL_Pointer; @@ -339,6 +427,7 @@ typedef struct _RxD_t {  #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)  #define RXD_FRAME_PROTO_IPV4    BIT(27)  #define RXD_FRAME_PROTO_IPV6    BIT(28) +#define RXD_FRAME_IP_FRAG	BIT(29)  #define RXD_FRAME_PROTO_TCP     BIT(30)  #define RXD_FRAME_PROTO_UDP     BIT(31)  #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP) @@ -346,11 +435,15 @@ typedef struct _RxD_t {  #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)  	u64 Control_2; +#define	THE_RXD_MARK		0x3 +#define	SET_RXD_MARKER		vBIT(THE_RXD_MARK, 0, 2) +#define	GET_RXD_MARKER(ctrl)	((ctrl & SET_RXD_MARKER) >> 62) +  #ifndef CONFIG_2BUFF_MODE -#define MASK_BUFFER0_SIZE       vBIT(0xFFFF,0,16) -#define SET_BUFFER0_SIZE(val)   vBIT(val,0,16) +#define MASK_BUFFER0_SIZE       vBIT(0x3FFF,2,14) +#define SET_BUFFER0_SIZE(val)   vBIT(val,2,14)  #else -#define MASK_BUFFER0_SIZE       vBIT(0xFF,0,16) +#define MASK_BUFFER0_SIZE       vBIT(0xFF,2,14)  #define MASK_BUFFER1_SIZE       vBIT(0xFFFF,16,16)  #define MASK_BUFFER2_SIZE       vBIT(0xFFFF,32,16)  #define SET_BUFFER0_SIZE(val)   vBIT(val,8,8) @@ -363,7 +456,7 @@ typedef struct _RxD_t {  #define SET_NUM_TAG(val)       vBIT(val,16,32)  #ifndef CONFIG_2BUFF_MODE -#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16))) +#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))  #else  #define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \  							>> 48) @@ -382,7 +475,7 @@ typedef struct _RxD_t {  #endif  } RxD_t; -/* Structure that represents the Rx descriptor block which contains  +/* Structure that represents the Rx descriptor block which contains   * 128 Rx descriptors.   */  #ifndef CONFIG_2BUFF_MODE @@ -392,11 +485,11 @@ typedef struct _RxD_block {  	u64 reserved_0;  #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL -	u64 reserved_1;		/* 0xFEFFFFFFFFFFFFFF to mark last  +	u64 reserved_1;		/* 0xFEFFFFFFFFFFFFFF to mark last  				 * Rxd in this blk */  	u64 reserved_2_pNext_RxD_block;	/* Logical ptr to next */  	u64 pNext_RxD_Blk_physical;	/* Buff0_ptr.In a 32 bit arch -					 * the upper 32 bits should  +					 * the upper 32 bits should  					 * be 0 */  } RxD_block_t;  #else @@ -405,13 +498,13 @@ typedef struct _RxD_block {  	RxD_t rxd[MAX_RXDS_PER_BLOCK];  #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL -	u64 reserved_1;		/* 0xFEFFFFFFFFFFFFFF to mark last Rxd  +	u64 reserved_1;		/* 0xFEFFFFFFFFFFFFFF to mark last Rxd  				 * in this blk */  	u64 pNext_RxD_Blk_physical;	/* Phy ponter to next blk. */  } RxD_block_t;  #define SIZE_OF_BLOCK	4096 -/* Structure to hold virtual addresses of Buf0 and Buf1 in  +/* Structure to hold virtual addresses of Buf0 and Buf1 in   * 2buf mode. */  typedef struct bufAdd {  	void *ba_0_org; @@ -423,8 +516,8 @@ typedef struct bufAdd {  /* Structure which stores all the MAC control parameters */ -/* This structure stores the offset of the RxD in the ring  - * from which the Rx Interrupt processor can start picking  +/* This structure stores the offset of the RxD in the ring + * from which the Rx Interrupt processor can start picking   * up the RxDs for processing.   */  typedef struct _rx_curr_get_info_t { @@ -436,7 +529,7 @@ typedef struct _rx_curr_get_info_t {  typedef rx_curr_get_info_t rx_curr_put_info_t;  /* This structure stores the offset of the TxDl in the FIFO - * from which the Tx Interrupt processor can start picking  + * from which the Tx Interrupt processor can start picking   * up the TxDLs for send complete interrupt processing.   */  typedef struct { @@ -446,32 +539,96 @@ typedef struct {  typedef tx_curr_get_info_t tx_curr_put_info_t; -/* Infomation related to the Tx and Rx FIFOs and Rings of Xena - * is maintained in this structure. - */ -typedef struct mac_info { -/* rx side stuff */ -	/* Put pointer info which indictes which RxD has to be replenished  +/* Structure that holds the Phy and virt addresses of the Blocks */ +typedef struct rx_block_info { +	RxD_t *block_virt_addr; +	dma_addr_t block_dma_addr; +} rx_block_info_t; + +/* pre declaration of the nic structure */ +typedef struct s2io_nic nic_t; + +/* Ring specific structure */ +typedef struct ring_info { +	/* The ring number */ +	int ring_no; + +	/* +	 *  Place holders for the virtual and physical addresses of +	 *  all the Rx Blocks +	 */ +	rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING]; +	int block_count; +	int pkt_cnt; + +	/* +	 * Put pointer info which indictes which RxD has to be replenished  	 * with a new buffer.  	 */ -	rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS]; +	rx_curr_put_info_t rx_curr_put_info; -	/* Get pointer info which indictes which is the last RxD that was  +	/* +	 * Get pointer info which indictes which is the last RxD that was  	 * processed by the driver.  	 */ -	rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS]; +	rx_curr_get_info_t rx_curr_get_info; -	u16 rmac_pause_time; -	u16 mc_pause_threshold_q0q3; -	u16 mc_pause_threshold_q4q7; +#ifndef CONFIG_S2IO_NAPI +	/* Index to the absolute position of the put pointer of Rx ring */ +	int put_pos; +#endif + +#ifdef CONFIG_2BUFF_MODE +	/* Buffer Address store. */ +	buffAdd_t **ba; +#endif +	nic_t *nic; +} ring_info_t; +/* Fifo specific structure */ +typedef struct fifo_info { +	/* FIFO number */ +	int fifo_no; + +	/* Maximum TxDs per TxDL */ +	int max_txds; + +	/* Place holder of all the TX List's Phy and Virt addresses. */ +	list_info_hold_t *list_info; + +	/* +	 * Current offset within the tx FIFO where driver would write +	 * new Tx frame +	 */ +	tx_curr_put_info_t tx_curr_put_info; + +	/* +	 * Current offset within tx FIFO from where the driver would start freeing +	 * the buffers +	 */ +	tx_curr_get_info_t tx_curr_get_info; + +	nic_t *nic; +}fifo_info_t; + +/* Infomation related to the Tx and Rx FIFOs and Rings of Xena + * is maintained in this structure. + */ +typedef struct mac_info {  /* tx side stuff */  	/* logical pointer of start of each Tx FIFO */  	TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS]; -/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/ -	tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS]; -	tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS]; +	/* Fifo specific structure */ +	fifo_info_t fifos[MAX_TX_FIFOS]; + +/* rx side stuff */ +	/* Ring specific structure */ +	ring_info_t rings[MAX_RX_RINGS]; + +	u16 rmac_pause_time; +	u16 mc_pause_threshold_q0q3; +	u16 mc_pause_threshold_q4q7;  	void *stats_mem;	/* orignal pointer to allocated mem */  	dma_addr_t stats_mem_phy;	/* Physical address of the stat block */ @@ -485,12 +642,6 @@ typedef struct {  	int usage_cnt;  } usr_addr_t; -/* Structure that holds the Phy and virt addresses of the Blocks */ -typedef struct rx_block_info { -	RxD_t *block_virt_addr; -	dma_addr_t block_dma_addr; -} rx_block_info_t; -  /* Default Tunable parameters of the NIC. */  #define DEFAULT_FIFO_LEN 4096  #define SMALL_RXD_CNT	30 * (MAX_RXDS_PER_BLOCK+1) @@ -499,7 +650,20 @@ typedef struct rx_block_info {  #define LARGE_BLK_CNT	100  /* Structure representing one instance of the NIC */ -typedef struct s2io_nic { +struct s2io_nic { +#ifdef CONFIG_S2IO_NAPI +	/* +	 * Count of packets to be processed in a given iteration, it will be indicated +	 * by the quota field of the device structure when NAPI is enabled. +	 */ +	int pkts_to_process; +#endif +	struct net_device *dev; +	mac_info_t mac_control; +	struct config_param config; +	struct pci_dev *pdev; +	void __iomem *bar0; +	void __iomem *bar1;  #define MAX_MAC_SUPPORTED   16  #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED @@ -507,33 +671,20 @@ typedef struct s2io_nic {  	macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];  	struct net_device_stats stats; -	void __iomem *bar0; -	void __iomem *bar1; -	struct config_param config; -	mac_info_t mac_control;  	int high_dma_flag;  	int device_close_flag;  	int device_enabled_once; -	char name[32]; +	char name[50];  	struct tasklet_struct task;  	volatile unsigned long tasklet_status; -	struct timer_list timer; -	struct net_device *dev; -	struct pci_dev *pdev; -	u16 vendor_id; -	u16 device_id; -	u16 ccmd; -	u32 cbar0_1; -	u32 cbar0_2; -	u32 cbar1_1; -	u32 cbar1_2; -	u32 cirq; -	u8 cache_line; -	u32 rom_expansion; -	u16 pcix_cmd; -	u32 irq; +	/* Timer that handles I/O errors/exceptions */ +	struct timer_list alarm_timer; + +	/* Space to back up the PCI config space */ +	u32 config_space[256 / sizeof(u32)]; +  	atomic_t rx_bufs_left[MAX_RX_RINGS];  	spinlock_t tx_lock; @@ -558,27 +709,11 @@ typedef struct s2io_nic {  	u16 tx_err_count;  	u16 rx_err_count; -#ifndef CONFIG_S2IO_NAPI -	/* Index to the absolute position of the put pointer of Rx ring. */ -	int put_pos[MAX_RX_RINGS]; -#endif - -	/* -	 *  Place holders for the virtual and physical addresses of  -	 *  all the Rx Blocks -	 */ -	rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING]; -	int block_count[MAX_RX_RINGS]; -	int pkt_cnt[MAX_RX_RINGS]; - -	/* Place holder of all the TX List's Phy and Virt addresses. */ -	list_info_hold_t *list_info[MAX_TX_FIFOS]; -  	/*  Id timer, used to blink NIC to physically identify NIC. */  	struct timer_list id_timer;  	/*  Restart timer, used to restart NIC if the device is stuck and -	 *  a schedule task that will set the correct Link state once the  +	 *  a schedule task that will set the correct Link state once the  	 *  NIC's PHY has stabilized after a state change.  	 */  #ifdef INIT_TQUEUE @@ -589,12 +724,12 @@ typedef struct s2io_nic {  	struct work_struct set_link_task;  #endif -	/* Flag that can be used to turn on or turn off the Rx checksum  +	/* Flag that can be used to turn on or turn off the Rx checksum  	 * offload feature.  	 */  	int rx_csum; -	/*  after blink, the adapter must be restored with original  +	/*  after blink, the adapter must be restored with original  	 *  values.  	 */  	u64 adapt_ctrl_org; @@ -604,16 +739,19 @@ typedef struct s2io_nic {  #define	LINK_DOWN	1  #define	LINK_UP		2 -#ifdef CONFIG_2BUFF_MODE -	/* Buffer Address store. */ -	buffAdd_t **ba[MAX_RX_RINGS]; -#endif  	int task_flag;  #define CARD_DOWN 1  #define CARD_UP 2  	atomic_t card_state;  	volatile unsigned long link_state; -} nic_t; +	struct vlan_group *vlgrp; +#define XFRAME_I_DEVICE		1 +#define XFRAME_II_DEVICE	2 +	u8 device_type; + +	spinlock_t	rx_lock; +	atomic_t	isr_cnt; +};  #define RESET_ERROR 1;  #define CMD_ERROR   2; @@ -622,9 +760,10 @@ typedef struct s2io_nic {  #ifndef readq  static inline u64 readq(void __iomem *addr)  { -	u64 ret = readl(addr + 4); -	ret <<= 32; -	ret |= readl(addr); +	u64 ret = 0; +	ret = readl(addr + 4); +	(u64) ret <<= 32; +	(u64) ret |= readl(addr);  	return ret;  } @@ -637,10 +776,10 @@ static inline void writeq(u64 val, void __iomem *addr)  	writel((u32) (val >> 32), (addr + 4));  } -/* In 32 bit modes, some registers have to be written in a  +/* In 32 bit modes, some registers have to be written in a   * particular order to expect correct hardware operation. The - * macro SPECIAL_REG_WRITE is used to perform such ordered  - * writes. Defines UF (Upper First) and LF (Lower First) will  + * macro SPECIAL_REG_WRITE is used to perform such ordered + * writes. Defines UF (Upper First) and LF (Lower First) will   * be used to specify the required write order.   */  #define UF	1 @@ -716,6 +855,7 @@ static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)  #define	PCC_FB_ECC_ERR	   vBIT(0xff, 16, 8)	/* Interrupt to indicate  						   PCC_FB_ECC Error. */ +#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)  /*   * Prototype declaration.   */ @@ -725,36 +865,30 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev);  static int init_shared_mem(struct s2io_nic *sp);  static void free_shared_mem(struct s2io_nic *sp);  static int init_nic(struct s2io_nic *nic); -#ifndef CONFIG_S2IO_NAPI -static void rx_intr_handler(struct s2io_nic *sp); -#endif -static void tx_intr_handler(struct s2io_nic *sp); +static void rx_intr_handler(ring_info_t *ring_data); +static void tx_intr_handler(fifo_info_t *fifo_data);  static void alarm_intr_handler(struct s2io_nic *sp);  static int s2io_starter(void); -static void s2io_closer(void); +void s2io_closer(void);  static void s2io_tx_watchdog(struct net_device *dev);  static void s2io_tasklet(unsigned long dev_addr);  static void s2io_set_multicast(struct net_device *dev); -#ifndef CONFIG_2BUFF_MODE -static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no); -#else -static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no, -			  buffAdd_t * ba); -#endif -static void s2io_link(nic_t * sp, int link); -static void s2io_reset(nic_t * sp); -#ifdef CONFIG_S2IO_NAPI +static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp); +void s2io_link(nic_t * sp, int link); +void s2io_reset(nic_t * sp); +#if defined(CONFIG_S2IO_NAPI)  static int s2io_poll(struct net_device *dev, int *budget);  #endif  static void s2io_init_pci(nic_t * sp); -static int s2io_set_mac_addr(struct net_device *dev, u8 * addr); +int s2io_set_mac_addr(struct net_device *dev, u8 * addr); +static void s2io_alarm_handle(unsigned long data);  static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs); -static int verify_xena_quiescence(u64 val64, int flag); +static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);  static struct ethtool_ops netdev_ethtool_ops;  static void s2io_set_link(unsigned long data); -static int s2io_set_swapper(nic_t * sp); -static void s2io_card_down(nic_t * nic); -static int s2io_card_up(nic_t * nic); - +int s2io_set_swapper(nic_t * sp); +static void s2io_card_down(nic_t *nic); +static int s2io_card_up(nic_t *nic); +int get_xena_rev_id(struct pci_dev *pdev);  #endif				/* _S2IO_H */  | 
