diff options
Diffstat (limited to 'drivers/mtd/maps/dc21285.c')
| -rw-r--r-- | drivers/mtd/maps/dc21285.c | 78 |
1 files changed, 28 insertions, 50 deletions
diff --git a/drivers/mtd/maps/dc21285.c b/drivers/mtd/maps/dc21285.c index 938c41f2f05..f8a7dd14cee 100644 --- a/drivers/mtd/maps/dc21285.c +++ b/drivers/mtd/maps/dc21285.c @@ -1,18 +1,16 @@ /* * MTD map driver for flash on the DC21285 (the StrongARM-110 companion chip) * - * (C) 2000 Nicolas Pitre <nico@cam.org> + * (C) 2000 Nicolas Pitre <nico@fluxnic.net> * * This code is GPL - * - * $Id: dc21285.c,v 1.22 2004/11/01 13:39:21 rmk Exp $ */ -#include <linux/config.h> #include <linux/module.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/delay.h> +#include <linux/slab.h> #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> @@ -26,24 +24,23 @@ static struct mtd_info *dc21285_mtd; #ifdef CONFIG_ARCH_NETWINDER -/* +/* * This is really ugly, but it seams to be the only - * realiable way to do it, as the cpld state machine + * realiable way to do it, as the cpld state machine * is unpredictible. So we have a 25us penalty per * write access. */ static void nw_en_write(void) { - extern spinlock_t gpio_lock; unsigned long flags; /* * we want to write a bit pattern XXX1 to Xilinx to enable * the write gate, which will be open for about the next 2ms. */ - spin_lock_irqsave(&gpio_lock, flags); - cpld_modify(1, 1); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE); + spin_unlock_irqrestore(&nw_gpio_lock, flags); /* * let the ISA bus to catch on... @@ -109,8 +106,9 @@ static void dc21285_copy_to_32(struct map_info *map, unsigned long to, const voi { while (len > 0) { map_word d; - d.x[0] = *((uint32_t*)from)++; + d.x[0] = *((uint32_t*)from); dc21285_write32(map, d, to); + from += 4; to += 4; len -= 4; } @@ -120,8 +118,9 @@ static void dc21285_copy_to_16(struct map_info *map, unsigned long to, const voi { while (len > 0) { map_word d; - d.x[0] = *((uint16_t*)from)++; + d.x[0] = *((uint16_t*)from); dc21285_write16(map, d, to); + from += 2; to += 2; len -= 2; } @@ -130,8 +129,9 @@ static void dc21285_copy_to_16(struct map_info *map, unsigned long to, const voi static void dc21285_copy_to_8(struct map_info *map, unsigned long to, const void *from, ssize_t len) { map_word d; - d.x[0] = *((uint8_t*)from)++; + d.x[0] = *((uint8_t*)from); dc21285_write8(map, d, to); + from++; to++; len--; } @@ -143,36 +143,27 @@ static struct map_info dc21285_map = { .copy_from = dc21285_copy_from, }; - /* Partition stuff */ -#ifdef CONFIG_MTD_PARTITIONS -static struct mtd_partition *dc21285_parts; -static const char *probes[] = { "RedBoot", "cmdlinepart", NULL }; -#endif - +static const char * const probes[] = { "RedBoot", "cmdlinepart", NULL }; + static int __init init_dc21285(void) { - -#ifdef CONFIG_MTD_PARTITIONS - int nrparts; -#endif - /* Determine bankwidth */ switch (*CSR_SA110_CNTL & (3<<14)) { - case SA110_CNTL_ROMWIDTH_8: + case SA110_CNTL_ROMWIDTH_8: dc21285_map.bankwidth = 1; dc21285_map.read = dc21285_read8; dc21285_map.write = dc21285_write8; dc21285_map.copy_to = dc21285_copy_to_8; break; - case SA110_CNTL_ROMWIDTH_16: - dc21285_map.bankwidth = 2; + case SA110_CNTL_ROMWIDTH_16: + dc21285_map.bankwidth = 2; dc21285_map.read = dc21285_read16; dc21285_map.write = dc21285_write16; dc21285_map.copy_to = dc21285_copy_to_16; break; - case SA110_CNTL_ROMWIDTH_32: - dc21285_map.bankwidth = 4; + case SA110_CNTL_ROMWIDTH_32: + dc21285_map.bankwidth = 4; dc21285_map.read = dc21285_read32; dc21285_map.write = dc21285_write32; dc21285_map.copy_to = dc21285_copy_to_32; @@ -200,20 +191,14 @@ static int __init init_dc21285(void) if (!dc21285_mtd) { iounmap(dc21285_map.virt); return -ENXIO; - } - + } + dc21285_mtd->owner = THIS_MODULE; -#ifdef CONFIG_MTD_PARTITIONS - nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, 0); - if (nrparts > 0) - add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts); - else -#endif - add_mtd_device(dc21285_mtd); - + mtd_device_parse_register(dc21285_mtd, probes, NULL, NULL, 0); + if(machine_is_ebsa285()) { - /* + /* * Flash timing is determined with bits 19-16 of the * CSR_SA110_CNTL. The value is the number of wait cycles, or * 0 for 16 cycles (the default). Cycles are 20 ns. @@ -226,20 +211,13 @@ static int __init init_dc21285(void) /* tristate time */ *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24)); } - + return 0; } static void __exit cleanup_dc21285(void) { -#ifdef CONFIG_MTD_PARTITIONS - if (dc21285_parts) { - del_mtd_partitions(dc21285_mtd); - kfree(dc21285_parts); - } else -#endif - del_mtd_device(dc21285_mtd); - + mtd_device_unregister(dc21285_mtd); map_destroy(dc21285_mtd); iounmap(dc21285_map.virt); } @@ -249,5 +227,5 @@ module_exit(cleanup_dc21285); MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Nicolas Pitre <nico@cam.org>"); +MODULE_AUTHOR("Nicolas Pitre <nico@fluxnic.net>"); MODULE_DESCRIPTION("MTD map driver for DC21285 boards"); |