diff options
Diffstat (limited to 'drivers/dma/fsldma.h')
| -rw-r--r-- | drivers/dma/fsldma.h | 98 |
1 files changed, 57 insertions, 41 deletions
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index fddd6aee2a6..d56e8359982 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. * * Author: * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 @@ -36,8 +36,16 @@ #define FSL_DMA_MR_DAHE 0x00002000 #define FSL_DMA_MR_SAHE 0x00001000 +/* + * Bandwidth/pause control determines how many bytes a given + * channel is allowed to transfer before the DMA engine pauses + * the current channel and switches to the next channel + */ +#define FSL_DMA_MR_BWC 0x0A000000 + /* Special MR definition for MPC8349 */ #define FSL_DMA_MR_EOTIE 0x00000080 +#define FSL_DMA_MR_PRC_RM 0x00000800 #define FSL_DMA_SR_CH 0x00000020 #define FSL_DMA_SR_PE 0x00000010 @@ -75,45 +83,47 @@ #define FSL_DMA_DGSR_EOSI 0x02 #define FSL_DMA_DGSR_EOLSI 0x01 +typedef u64 __bitwise v64; +typedef u32 __bitwise v32; + struct fsl_dma_ld_hw { - u64 __bitwise src_addr; - u64 __bitwise dst_addr; - u64 __bitwise next_ln_addr; - u32 __bitwise count; - u32 __bitwise reserve; + v64 src_addr; + v64 dst_addr; + v64 next_ln_addr; + v32 count; + v32 reserve; } __attribute__((aligned(32))); struct fsl_desc_sw { struct fsl_dma_ld_hw hw; struct list_head node; + struct list_head tx_list; struct dma_async_tx_descriptor async_tx; - struct list_head *ld; - void *priv; } __attribute__((aligned(32))); -struct fsl_dma_chan_regs { - u32 __bitwise mr; /* 0x00 - Mode Register */ - u32 __bitwise sr; /* 0x04 - Status Register */ - u64 __bitwise cdar; /* 0x08 - Current descriptor address register */ - u64 __bitwise sar; /* 0x10 - Source Address Register */ - u64 __bitwise dar; /* 0x18 - Destination Address Register */ - u32 __bitwise bcr; /* 0x20 - Byte Count Register */ - u64 __bitwise ndar; /* 0x24 - Next Descriptor Address Register */ +struct fsldma_chan_regs { + u32 mr; /* 0x00 - Mode Register */ + u32 sr; /* 0x04 - Status Register */ + u64 cdar; /* 0x08 - Current descriptor address register */ + u64 sar; /* 0x10 - Source Address Register */ + u64 dar; /* 0x18 - Destination Address Register */ + u32 bcr; /* 0x20 - Byte Count Register */ + u64 ndar; /* 0x24 - Next Descriptor Address Register */ }; -struct fsl_dma_chan; -#define FSL_DMA_MAX_CHANS_PER_DEVICE 4 +struct fsldma_chan; +#define FSL_DMA_MAX_CHANS_PER_DEVICE 8 -struct fsl_dma_device { - void __iomem *reg_base; /* DGSR register base */ - struct resource reg; /* Resource for register */ +struct fsldma_device { + void __iomem *regs; /* DGSR register base */ struct device *dev; struct dma_device common; - struct fsl_dma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; + struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; u32 feature; /* The same as DMA channels */ + int irq; /* Channel IRQ */ }; -/* Define macros for fsl_dma_chan->feature property */ +/* Define macros for fsldma_chan->feature property */ #define FSL_DMA_LITTLE_ENDIAN 0x00000000 #define FSL_DMA_BIG_ENDIAN 0x00000001 @@ -124,52 +134,56 @@ struct fsl_dma_device { #define FSL_DMA_CHAN_PAUSE_EXT 0x00001000 #define FSL_DMA_CHAN_START_EXT 0x00002000 -struct fsl_dma_chan { - struct fsl_dma_chan_regs __iomem *reg_base; - dma_cookie_t completed_cookie; /* The maximum cookie completed */ +struct fsldma_chan { + char name[8]; /* Channel name */ + struct fsldma_chan_regs __iomem *regs; spinlock_t desc_lock; /* Descriptor operation lock */ - struct list_head ld_queue; /* Link descriptors queue */ + struct list_head ld_pending; /* Link descriptors queue */ + struct list_head ld_running; /* Link descriptors queue */ struct dma_chan common; /* DMA common channel */ struct dma_pool *desc_pool; /* Descriptors pool */ struct device *dev; /* Channel device */ - struct resource reg; /* Resource for register */ int irq; /* Channel IRQ */ int id; /* Raw id of this channel */ struct tasklet_struct tasklet; u32 feature; + bool idle; /* DMA controller is idle */ - void (*toggle_ext_pause)(struct fsl_dma_chan *fsl_chan, int size); - void (*toggle_ext_start)(struct fsl_dma_chan *fsl_chan, int enable); - void (*set_src_loop_size)(struct fsl_dma_chan *fsl_chan, int size); - void (*set_dest_loop_size)(struct fsl_dma_chan *fsl_chan, int size); + void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable); + void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable); + void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size); + void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size); + void (*set_request_count)(struct fsldma_chan *fsl_chan, int size); }; -#define to_fsl_chan(chan) container_of(chan, struct fsl_dma_chan, common) +#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common) #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node) #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx) #ifndef __powerpc64__ static u64 in_be64(const u64 __iomem *addr) { - return ((u64)in_be32((u32 *)addr) << 32) | (in_be32((u32 *)addr + 1)); + return ((u64)in_be32((u32 __iomem *)addr) << 32) | + (in_be32((u32 __iomem *)addr + 1)); } static void out_be64(u64 __iomem *addr, u64 val) { - out_be32((u32 *)addr, val >> 32); - out_be32((u32 *)addr + 1, (u32)val); + out_be32((u32 __iomem *)addr, val >> 32); + out_be32((u32 __iomem *)addr + 1, (u32)val); } /* There is no asm instructions for 64 bits reverse loads and stores */ static u64 in_le64(const u64 __iomem *addr) { - return ((u64)in_le32((u32 *)addr + 1) << 32) | (in_le32((u32 *)addr)); + return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) | + (in_le32((u32 __iomem *)addr)); } static void out_le64(u64 __iomem *addr, u64 val) { - out_le32((u32 *)addr + 1, val >> 32); - out_le32((u32 *)addr, (u32)val); + out_le32((u32 __iomem *)addr + 1, val >> 32); + out_le32((u32 __iomem *)addr, (u32)val); } #endif @@ -182,9 +196,11 @@ static void out_le64(u64 __iomem *addr, u64 val) #define DMA_TO_CPU(fsl_chan, d, width) \ (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ - be##width##_to_cpu(d) : le##width##_to_cpu(d)) + be##width##_to_cpu((__force __be##width)(v##width)d) : \ + le##width##_to_cpu((__force __le##width)(v##width)d)) #define CPU_TO_DMA(fsl_chan, c, width) \ (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ - cpu_to_be##width(c) : cpu_to_le##width(c)) + (__force v##width)cpu_to_be##width(c) : \ + (__force v##width)cpu_to_le##width(c)) #endif /* __DMA_FSLDMA_H */ |