diff options
Diffstat (limited to 'drivers/dma/dw_dmac_regs.h')
| -rw-r--r-- | drivers/dma/dw_dmac_regs.h | 223 |
1 files changed, 0 insertions, 223 deletions
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h deleted file mode 100644 index b252b202c5c..00000000000 --- a/drivers/dma/dw_dmac_regs.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Driver for the Synopsys DesignWare AHB DMA Controller - * - * Copyright (C) 2005-2007 Atmel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/dw_dmac.h> - -#define DW_DMA_MAX_NR_CHANNELS 8 - -/* - * Redefine this macro to handle differences between 32- and 64-bit - * addressing, big vs. little endian, etc. - */ -#define DW_REG(name) u32 name; u32 __pad_##name - -/* Hardware register definitions. */ -struct dw_dma_chan_regs { - DW_REG(SAR); /* Source Address Register */ - DW_REG(DAR); /* Destination Address Register */ - DW_REG(LLP); /* Linked List Pointer */ - u32 CTL_LO; /* Control Register Low */ - u32 CTL_HI; /* Control Register High */ - DW_REG(SSTAT); - DW_REG(DSTAT); - DW_REG(SSTATAR); - DW_REG(DSTATAR); - u32 CFG_LO; /* Configuration Register Low */ - u32 CFG_HI; /* Configuration Register High */ - DW_REG(SGR); - DW_REG(DSR); -}; - -struct dw_dma_irq_regs { - DW_REG(XFER); - DW_REG(BLOCK); - DW_REG(SRC_TRAN); - DW_REG(DST_TRAN); - DW_REG(ERROR); -}; - -struct dw_dma_regs { - /* per-channel registers */ - struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS]; - - /* irq handling */ - struct dw_dma_irq_regs RAW; /* r */ - struct dw_dma_irq_regs STATUS; /* r (raw & mask) */ - struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */ - struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */ - - DW_REG(STATUS_INT); /* r */ - - /* software handshaking */ - DW_REG(REQ_SRC); - DW_REG(REQ_DST); - DW_REG(SGL_REQ_SRC); - DW_REG(SGL_REQ_DST); - DW_REG(LAST_SRC); - DW_REG(LAST_DST); - - /* miscellaneous */ - DW_REG(CFG); - DW_REG(CH_EN); - DW_REG(ID); - DW_REG(TEST); - - /* optional encoded params, 0x3c8..0x3 */ -}; - -/* Bitfields in CTL_LO */ -#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ -#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */ -#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4) -#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */ -#define DWC_CTLL_DST_DEC (1<<7) -#define DWC_CTLL_DST_FIX (2<<7) -#define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */ -#define DWC_CTLL_SRC_DEC (1<<9) -#define DWC_CTLL_SRC_FIX (2<<9) -#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */ -#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) -#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ -#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ -#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ -#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ -#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ -#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */ -/* plus 4 transfer types for peripheral-as-flow-controller */ -#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */ -#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */ -#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ -#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */ - -/* Bitfields in CTL_HI */ -#define DWC_CTLH_DONE 0x00001000 -#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff - -/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */ -#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ -#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ -#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ -#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */ -#define DWC_CFGL_MAX_BURST(x) ((x) << 20) -#define DWC_CFGL_RELOAD_SAR (1 << 30) -#define DWC_CFGL_RELOAD_DAR (1 << 31) - -/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */ -#define DWC_CFGH_DS_UPD_EN (1 << 5) -#define DWC_CFGH_SS_UPD_EN (1 << 6) - -/* Bitfields in SGR */ -#define DWC_SGR_SGI(x) ((x) << 0) -#define DWC_SGR_SGC(x) ((x) << 20) - -/* Bitfields in DSR */ -#define DWC_DSR_DSI(x) ((x) << 0) -#define DWC_DSR_DSC(x) ((x) << 20) - -/* Bitfields in CFG */ -#define DW_CFG_DMA_EN (1 << 0) - -#define DW_REGLEN 0x400 - -struct dw_dma_chan { - struct dma_chan chan; - void __iomem *ch_regs; - u8 mask; - - spinlock_t lock; - - /* these other elements are all protected by lock */ - dma_cookie_t completed; - struct list_head active_list; - struct list_head queue; - struct list_head free_list; - - unsigned int descs_allocated; -}; - -static inline struct dw_dma_chan_regs __iomem * -__dwc_regs(struct dw_dma_chan *dwc) -{ - return dwc->ch_regs; -} - -#define channel_readl(dwc, name) \ - __raw_readl(&(__dwc_regs(dwc)->name)) -#define channel_writel(dwc, name, val) \ - __raw_writel((val), &(__dwc_regs(dwc)->name)) - -static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) -{ - return container_of(chan, struct dw_dma_chan, chan); -} - - -struct dw_dma { - struct dma_device dma; - void __iomem *regs; - struct tasklet_struct tasklet; - struct clk *clk; - - u8 all_chan_mask; - - struct dw_dma_chan chan[0]; -}; - -static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) -{ - return dw->regs; -} - -#define dma_readl(dw, name) \ - __raw_readl(&(__dw_regs(dw)->name)) -#define dma_writel(dw, name, val) \ - __raw_writel((val), &(__dw_regs(dw)->name)) - -#define channel_set_bit(dw, reg, mask) \ - dma_writel(dw, reg, ((mask) << 8) | (mask)) -#define channel_clear_bit(dw, reg, mask) \ - dma_writel(dw, reg, ((mask) << 8) | 0) - -static inline struct dw_dma *to_dw_dma(struct dma_device *ddev) -{ - return container_of(ddev, struct dw_dma, dma); -} - -/* LLI == Linked List Item; a.k.a. DMA block descriptor */ -struct dw_lli { - /* values that are not changed by hardware */ - dma_addr_t sar; - dma_addr_t dar; - dma_addr_t llp; /* chain to next lli */ - u32 ctllo; - /* values that may get written back: */ - u32 ctlhi; - /* sstat and dstat can snapshot peripheral register state. - * silicon config may discard either or both... - */ - u32 sstat; - u32 dstat; -}; - -struct dw_desc { - /* FIRST values the hardware uses */ - struct dw_lli lli; - - /* THEN values for driver housekeeping */ - struct list_head desc_node; - struct dma_async_tx_descriptor txd; - size_t len; -}; - -static inline struct dw_desc * -txd_to_dw_desc(struct dma_async_tx_descriptor *txd) -{ - return container_of(txd, struct dw_desc, txd); -} |