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-rw-r--r--drivers/devfreq/Kconfig73
1 files changed, 45 insertions, 28 deletions
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 643b055ed3c..49e74c1fc63 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -1,43 +1,36 @@
-config ARCH_HAS_DEVFREQ
- bool
- depends on ARCH_HAS_OPP
- help
- Denotes that the architecture supports DEVFREQ. If the architecture
- supports multiple OPP entries per device and the frequency of the
- devices with OPPs may be altered dynamically, the architecture
- supports DEVFREQ.
-
menuconfig PM_DEVFREQ
bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
- depends on PM_OPP && ARCH_HAS_DEVFREQ
help
- With OPP support, a device may have a list of frequencies and
- voltages available. DEVFREQ, a generic DVFS framework can be
- registered for a device with OPP support in order to let the
- governor provided to DEVFREQ choose an operating frequency
- based on the OPP's list and the policy given with DEVFREQ.
+ A device may have a list of frequencies and voltages available.
+ devfreq, a generic DVFS framework can be registered for a device
+ in order to let the governor provided to devfreq choose an
+ operating frequency based on the device driver's policy.
- Each device may have its own governor and policy. DEVFREQ can
+ Each device may have its own governor and policy. Devfreq can
reevaluate the device state periodically and/or based on the
- OPP list changes (each frequency/voltage pair in OPP may be
- disabled or enabled).
+ notification to "nb", a notifier block, of devfreq.
- Like some CPUs with CPUFREQ, a device may have multiple clocks.
+ Like some CPUs with CPUfreq, a device may have multiple clocks.
However, because the clock frequencies of a single device are
- determined by the single device's state, an instance of DEVFREQ
+ determined by the single device's state, an instance of devfreq
is attached to a single device and returns a "representative"
- clock frequency from the OPP of the device, which is also attached
- to a device by 1-to-1. The device registering DEVFREQ takes the
- responsiblity to "interpret" the frequency listed in OPP and
+ clock frequency of the device, which is also attached
+ to a device by 1-to-1. The device registering devfreq takes the
+ responsibility to "interpret" the representative frequency and
to set its every clock accordingly with the "target" callback
- given to DEVFREQ.
+ given to devfreq.
+
+ When OPP is used with the devfreq device, it is recommended to
+ register devfreq's nb to the OPP's notifier head. If OPP is
+ used with the devfreq device, you may use OPP helper
+ functions defined in devfreq.h.
if PM_DEVFREQ
comment "DEVFREQ Governors"
config DEVFREQ_GOV_SIMPLE_ONDEMAND
- bool "Simple Ondemand"
+ tristate "Simple Ondemand"
help
Chooses frequency based on the recent load on the device. Works
similar as ONDEMAND governor of CPUFREQ does. A device with
@@ -46,7 +39,7 @@ config DEVFREQ_GOV_SIMPLE_ONDEMAND
values to the governor with data field at devfreq_add_device().
config DEVFREQ_GOV_PERFORMANCE
- bool "Performance"
+ tristate "Performance"
help
Sets the frequency at the maximum available frequency.
This governor always returns UINT_MAX as frequency so that
@@ -54,7 +47,7 @@ config DEVFREQ_GOV_PERFORMANCE
at any time.
config DEVFREQ_GOV_POWERSAVE
- bool "Powersave"
+ tristate "Powersave"
help
Sets the frequency at the minimum available frequency.
This governor always returns 0 as frequency so that
@@ -62,7 +55,7 @@ config DEVFREQ_GOV_POWERSAVE
at any time.
config DEVFREQ_GOV_USERSPACE
- bool "Userspace"
+ tristate "Userspace"
help
Sets the frequency at the user specified one.
This governor returns the user configured frequency if there
@@ -72,4 +65,28 @@ config DEVFREQ_GOV_USERSPACE
comment "DEVFREQ Drivers"
+config ARM_EXYNOS4_BUS_DEVFREQ
+ bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
+ depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
+ select ARCH_HAS_OPP
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select PM_OPP
+ help
+ This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
+ and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
+ It reads PPMU counters of memory controllers and adjusts
+ the operating frequencies and voltages with OPP support.
+ This does not yet operate with optimal voltages.
+
+config ARM_EXYNOS5_BUS_DEVFREQ
+ bool "ARM Exynos5250 Bus DEVFREQ Driver"
+ depends on SOC_EXYNOS5250
+ select ARCH_HAS_OPP
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select PM_OPP
+ help
+ This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int).
+ It reads PPMU counters of memory controllers and adjusts the
+ operating frequencies and voltages with OPP support.
+
endif # PM_DEVFREQ