diff options
Diffstat (limited to 'drivers/ata/sata_rcar.c')
| -rw-r--r-- | drivers/ata/sata_rcar.c | 275 |
1 files changed, 184 insertions, 91 deletions
diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c index 249c8a289bf..61eb6d77dac 100644 --- a/drivers/ata/sata_rcar.c +++ b/drivers/ata/sata_rcar.c @@ -15,6 +15,7 @@ #include <linux/module.h> #include <linux/ata.h> #include <linux/libata.h> +#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/err.h> @@ -121,48 +122,101 @@ /* Descriptor table word 0 bit (when DTA32M = 1) */ #define SATA_RCAR_DTEND BIT(0) +#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL + +/* Gen2 Physical Layer Control Registers */ +#define RCAR_GEN2_PHY_CTL1_REG 0x1704 +#define RCAR_GEN2_PHY_CTL1 0x34180002 +#define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */ + +#define RCAR_GEN2_PHY_CTL2_REG 0x170C +#define RCAR_GEN2_PHY_CTL2 0x00002303 + +#define RCAR_GEN2_PHY_CTL3_REG 0x171C +#define RCAR_GEN2_PHY_CTL3 0x000B0194 + +#define RCAR_GEN2_PHY_CTL4_REG 0x1724 +#define RCAR_GEN2_PHY_CTL4 0x00030994 + +#define RCAR_GEN2_PHY_CTL5_REG 0x1740 +#define RCAR_GEN2_PHY_CTL5 0x03004001 +#define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */ +#define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */ + +enum sata_rcar_type { + RCAR_GEN1_SATA, + RCAR_GEN2_SATA, +}; + struct sata_rcar_priv { void __iomem *base; struct clk *clk; + enum sata_rcar_type type; }; -static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv) +static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv) { + void __iomem *base = priv->base; + /* idle state */ - iowrite32(0, priv->base + SATAPHYADDR_REG); + iowrite32(0, base + SATAPHYADDR_REG); /* reset */ - iowrite32(SATAPHYRESET_PHYRST, priv->base + SATAPHYRESET_REG); + iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); udelay(10); /* deassert reset */ - iowrite32(0, priv->base + SATAPHYRESET_REG); + iowrite32(0, base + SATAPHYRESET_REG); } -static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val, - int group) +static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg, + u32 val, int group) { + void __iomem *base = priv->base; int timeout; /* deassert reset */ - iowrite32(0, priv->base + SATAPHYRESET_REG); + iowrite32(0, base + SATAPHYRESET_REG); /* lane 1 */ - iowrite32(SATAPHYACCEN_PHYLANE, priv->base + SATAPHYACCEN_REG); + iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); /* write phy register value */ - iowrite32(val, priv->base + SATAPHYWDATA_REG); + iowrite32(val, base + SATAPHYWDATA_REG); /* set register group */ if (group) reg |= SATAPHYADDR_PHYRATEMODE; /* write command */ - iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, priv->base + SATAPHYADDR_REG); + iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); /* wait for ack */ for (timeout = 0; timeout < 100; timeout++) { - val = ioread32(priv->base + SATAPHYACK_REG); + val = ioread32(base + SATAPHYACK_REG); if (val & SATAPHYACK_PHYACK) break; } if (timeout >= 100) pr_err("%s timeout\n", __func__); /* idle state */ - iowrite32(0, priv->base + SATAPHYADDR_REG); + iowrite32(0, base + SATAPHYADDR_REG); +} + +static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv) +{ + sata_rcar_gen1_phy_preinit(priv); + sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); + sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); + sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); + sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); + sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); + sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); +} + +static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv) +{ + void __iomem *base = priv->base; + + iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG); + iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG); + iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG); + iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG); + iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC | + RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG); } static void sata_rcar_freeze(struct ata_port *ap) @@ -178,14 +232,15 @@ static void sata_rcar_freeze(struct ata_port *ap) static void sata_rcar_thaw(struct ata_port *ap) { struct sata_rcar_priv *priv = ap->host->private_data; + void __iomem *base = priv->base; /* ack */ - iowrite32(~SATA_RCAR_INT_MASK, priv->base + SATAINTSTAT_REG); + iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); ata_sff_thaw(ap); /* unmask */ - iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, priv->base + SATAINTMASK_REG); + iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); } static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) @@ -474,11 +529,10 @@ static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) struct ata_port *ap = qc->ap; struct ata_bmdma_prd *prd = ap->bmdma_prd; struct scatterlist *sg; - unsigned int si, pi; + unsigned int si; - pi = 0; for_each_sg(qc->sg, sg, qc->n_elem, si) { - u32 addr, sg_len, len; + u32 addr, sg_len; /* * Note: h/w doesn't support 64-bit, so we unconditionally @@ -487,24 +541,13 @@ static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) addr = (u32)sg_dma_address(sg); sg_len = sg_dma_len(sg); - /* H/w transfer count is only 29 bits long, let's be careful */ - while (sg_len) { - len = sg_len; - if (len > 0x1ffffffe) - len = 0x1ffffffe; - - prd[pi].addr = cpu_to_le32(addr); - prd[pi].flags_len = cpu_to_le32(len); - VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); - - pi++; - sg_len -= len; - addr += len; - } + prd[si].addr = cpu_to_le32(addr); + prd[si].flags_len = cpu_to_le32(sg_len); + VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len); } /* end-of-table flag */ - prd[pi - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); + prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); } static void sata_rcar_qc_prep(struct ata_queued_cmd *qc) @@ -519,15 +562,16 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; - u32 dmactl; struct sata_rcar_priv *priv = ap->host->private_data; + void __iomem *base = priv->base; + u32 dmactl; /* load PRD table addr. */ mb(); /* make sure PRD table writes are visible to controller */ - iowrite32(ap->bmdma_prd_dma, priv->base + ATAPI_DTB_ADR_REG); + iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); /* specify data direction, triple-check start bit is clear */ - dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); + dmactl = ioread32(base + ATAPI_CONTROL1_REG); dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); if (dmactl & ATAPI_CONTROL1_START) { dmactl &= ~ATAPI_CONTROL1_START; @@ -535,7 +579,7 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) } if (!rw) dmactl |= ATAPI_CONTROL1_RW; - iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); + iowrite32(dmactl, base + ATAPI_CONTROL1_REG); /* issue r/w command */ ap->ops->sff_exec_command(ap, &qc->tf); @@ -544,28 +588,30 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; - u32 dmactl; struct sata_rcar_priv *priv = ap->host->private_data; + void __iomem *base = priv->base; + u32 dmactl; /* start host DMA transaction */ - dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); + dmactl = ioread32(base + ATAPI_CONTROL1_REG); dmactl &= ~ATAPI_CONTROL1_STOP; dmactl |= ATAPI_CONTROL1_START; - iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); + iowrite32(dmactl, base + ATAPI_CONTROL1_REG); } static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct sata_rcar_priv *priv = ap->host->private_data; + void __iomem *base = priv->base; u32 dmactl; /* force termination of DMA transfer if active */ - dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); + dmactl = ioread32(base + ATAPI_CONTROL1_REG); if (dmactl & ATAPI_CONTROL1_START) { dmactl &= ~ATAPI_CONTROL1_START; dmactl |= ATAPI_CONTROL1_STOP; - iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); + iowrite32(dmactl, base + ATAPI_CONTROL1_REG); } /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ @@ -575,8 +621,8 @@ static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) static u8 sata_rcar_bmdma_status(struct ata_port *ap) { struct sata_rcar_priv *priv = ap->host->private_data; - u32 status; u8 host_stat = 0; + u32 status; status = ioread32(priv->base + ATAPI_STATUS_REG); if (status & ATAPI_STATUS_DEVINT) @@ -588,7 +634,14 @@ static u8 sata_rcar_bmdma_status(struct ata_port *ap) } static struct scsi_host_template sata_rcar_sht = { - ATA_BMDMA_SHT(DRV_NAME), + ATA_BASE_SHT(DRV_NAME), + /* + * This controller allows transfer chunks up to 512MB which cross 64KB + * boundaries, therefore the DMA limits are more relaxed than standard + * ATA SFF. + */ + .sg_tablesize = ATA_MAX_PRD, + .dma_boundary = SATA_RCAR_DMA_BOUNDARY, }; static struct ata_port_operations sata_rcar_port_ops = { @@ -668,19 +721,20 @@ static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) { struct ata_host *host = dev_instance; struct sata_rcar_priv *priv = host->private_data; - struct ata_port *ap; + void __iomem *base = priv->base; unsigned int handled = 0; + struct ata_port *ap; u32 sataintstat; unsigned long flags; spin_lock_irqsave(&host->lock, flags); - sataintstat = ioread32(priv->base + SATAINTSTAT_REG); + sataintstat = ioread32(base + SATAINTSTAT_REG); sataintstat &= SATA_RCAR_INT_MASK; if (!sataintstat) goto done; /* ack */ - iowrite32(~sataintstat & 0x7ff, priv->base + SATAINTSTAT_REG); + iowrite32(~sataintstat & 0x7ff, base + SATAINTSTAT_REG); ap = host->ports[0]; @@ -702,15 +756,16 @@ static void sata_rcar_setup_port(struct ata_host *host) struct ata_port *ap = host->ports[0]; struct ata_ioports *ioaddr = &ap->ioaddr; struct sata_rcar_priv *priv = host->private_data; + void __iomem *base = priv->base; ap->ops = &sata_rcar_port_ops; ap->pio_mask = ATA_PIO4; ap->udma_mask = ATA_UDMA6; ap->flags |= ATA_FLAG_SATA; - ioaddr->cmd_addr = priv->base + SDATA_REG; - ioaddr->ctl_addr = priv->base + SSDEVCON_REG; - ioaddr->scr_addr = priv->base + SCRSSTS_REG; + ioaddr->cmd_addr = base + SDATA_REG; + ioaddr->ctl_addr = base + SSDEVCON_REG; + ioaddr->scr_addr = base + SCRSSTS_REG; ioaddr->altstatus_addr = ioaddr->ctl_addr; ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); @@ -728,53 +783,86 @@ static void sata_rcar_setup_port(struct ata_host *host) static void sata_rcar_init_controller(struct ata_host *host) { struct sata_rcar_priv *priv = host->private_data; + void __iomem *base = priv->base; u32 val; /* reset and setup phy */ - sata_rcar_phy_initialize(priv); - sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); - sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); - sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); - sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); - sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); - sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); + switch (priv->type) { + case RCAR_GEN1_SATA: + sata_rcar_gen1_phy_init(priv); + break; + case RCAR_GEN2_SATA: + sata_rcar_gen2_phy_init(priv); + break; + default: + dev_warn(host->dev, "SATA phy is not initialized\n"); + break; + } /* SATA-IP reset state */ - val = ioread32(priv->base + ATAPI_CONTROL1_REG); + val = ioread32(base + ATAPI_CONTROL1_REG); val |= ATAPI_CONTROL1_RESET; - iowrite32(val, priv->base + ATAPI_CONTROL1_REG); + iowrite32(val, base + ATAPI_CONTROL1_REG); /* ISM mode, PRD mode, DTEND flag at bit 0 */ - val = ioread32(priv->base + ATAPI_CONTROL1_REG); + val = ioread32(base + ATAPI_CONTROL1_REG); val |= ATAPI_CONTROL1_ISM; val |= ATAPI_CONTROL1_DESE; val |= ATAPI_CONTROL1_DTA32M; - iowrite32(val, priv->base + ATAPI_CONTROL1_REG); + iowrite32(val, base + ATAPI_CONTROL1_REG); /* Release the SATA-IP from the reset state */ - val = ioread32(priv->base + ATAPI_CONTROL1_REG); + val = ioread32(base + ATAPI_CONTROL1_REG); val &= ~ATAPI_CONTROL1_RESET; - iowrite32(val, priv->base + ATAPI_CONTROL1_REG); + iowrite32(val, base + ATAPI_CONTROL1_REG); /* ack and mask */ - iowrite32(0, priv->base + SATAINTSTAT_REG); - iowrite32(0x7ff, priv->base + SATAINTMASK_REG); + iowrite32(0, base + SATAINTSTAT_REG); + iowrite32(0x7ff, base + SATAINTMASK_REG); /* enable interrupts */ - iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); + iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); } +static struct of_device_id sata_rcar_match[] = { + { + /* Deprecated by "renesas,sata-r8a7779" */ + .compatible = "renesas,rcar-sata", + .data = (void *)RCAR_GEN1_SATA, + }, + { + .compatible = "renesas,sata-r8a7779", + .data = (void *)RCAR_GEN1_SATA, + }, + { + .compatible = "renesas,sata-r8a7790", + .data = (void *)RCAR_GEN2_SATA + }, + { + .compatible = "renesas,sata-r8a7791", + .data = (void *)RCAR_GEN2_SATA + }, + { }, +}; +MODULE_DEVICE_TABLE(of, sata_rcar_match); + +static const struct platform_device_id sata_rcar_id_table[] = { + { "sata_rcar", RCAR_GEN1_SATA }, /* Deprecated by "sata-r8a7779" */ + { "sata-r8a7779", RCAR_GEN1_SATA }, + { "sata-r8a7790", RCAR_GEN2_SATA }, + { "sata-r8a7791", RCAR_GEN2_SATA }, + { }, +}; +MODULE_DEVICE_TABLE(platform, sata_rcar_id_table); + static int sata_rcar_probe(struct platform_device *pdev) { + const struct of_device_id *of_id; struct ata_host *host; struct sata_rcar_priv *priv; struct resource *mem; int irq; int ret = 0; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (mem == NULL) - return -EINVAL; - irq = platform_get_irq(pdev, 0); if (irq <= 0) return -EINVAL; @@ -784,12 +872,18 @@ static int sata_rcar_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; + of_id = of_match_device(sata_rcar_match, &pdev->dev); + if (of_id) + priv->type = (enum sata_rcar_type)of_id->data; + else + priv->type = platform_get_device_id(pdev)->driver_data; + priv->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, "failed to get access to sata clock\n"); return PTR_ERR(priv->clk); } - clk_enable(priv->clk); + clk_prepare_enable(priv->clk); host = ata_host_alloc(&pdev->dev, 1); if (!host) { @@ -800,6 +894,7 @@ static int sata_rcar_probe(struct platform_device *pdev) host->private_data = priv; + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); priv->base = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(priv->base)) { ret = PTR_ERR(priv->base); @@ -818,44 +913,46 @@ static int sata_rcar_probe(struct platform_device *pdev) return 0; cleanup: - clk_disable(priv->clk); + clk_disable_unprepare(priv->clk); return ret; } static int sata_rcar_remove(struct platform_device *pdev) { - struct ata_host *host = dev_get_drvdata(&pdev->dev); + struct ata_host *host = platform_get_drvdata(pdev); struct sata_rcar_priv *priv = host->private_data; + void __iomem *base = priv->base; ata_host_detach(host); /* disable interrupts */ - iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); + iowrite32(0, base + ATAPI_INT_ENABLE_REG); /* ack and mask */ - iowrite32(0, priv->base + SATAINTSTAT_REG); - iowrite32(0x7ff, priv->base + SATAINTMASK_REG); + iowrite32(0, base + SATAINTSTAT_REG); + iowrite32(0x7ff, base + SATAINTMASK_REG); - clk_disable(priv->clk); + clk_disable_unprepare(priv->clk); return 0; } -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int sata_rcar_suspend(struct device *dev) { struct ata_host *host = dev_get_drvdata(dev); struct sata_rcar_priv *priv = host->private_data; + void __iomem *base = priv->base; int ret; ret = ata_host_suspend(host, PMSG_SUSPEND); if (!ret) { /* disable interrupts */ - iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); + iowrite32(0, base + ATAPI_INT_ENABLE_REG); /* mask */ - iowrite32(0x7ff, priv->base + SATAINTMASK_REG); + iowrite32(0x7ff, base + SATAINTMASK_REG); - clk_disable(priv->clk); + clk_disable_unprepare(priv->clk); } return ret; @@ -865,14 +962,15 @@ static int sata_rcar_resume(struct device *dev) { struct ata_host *host = dev_get_drvdata(dev); struct sata_rcar_priv *priv = host->private_data; + void __iomem *base = priv->base; - clk_enable(priv->clk); + clk_prepare_enable(priv->clk); /* ack and mask */ - iowrite32(0, priv->base + SATAINTSTAT_REG); - iowrite32(0x7ff, priv->base + SATAINTMASK_REG); + iowrite32(0, base + SATAINTSTAT_REG); + iowrite32(0x7ff, base + SATAINTMASK_REG); /* enable interrupts */ - iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); + iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); ata_host_resume(host); @@ -885,20 +983,15 @@ static const struct dev_pm_ops sata_rcar_pm_ops = { }; #endif -static struct of_device_id sata_rcar_match[] = { - { .compatible = "renesas,rcar-sata", }, - {}, -}; -MODULE_DEVICE_TABLE(of, sata_rcar_match); - static struct platform_driver sata_rcar_driver = { .probe = sata_rcar_probe, .remove = sata_rcar_remove, + .id_table = sata_rcar_id_table, .driver = { .name = DRV_NAME, .owner = THIS_MODULE, .of_match_table = sata_rcar_match, -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP .pm = &sata_rcar_pm_ops, #endif }, |