diff options
Diffstat (limited to 'arch/sh/boards')
165 files changed, 12423 insertions, 5239 deletions
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig new file mode 100644 index 00000000000..e331e5373b8 --- /dev/null +++ b/arch/sh/boards/Kconfig @@ -0,0 +1,383 @@ +menu "Board support" + +config SOLUTION_ENGINE + bool + +config SH_ALPHA_BOARD + bool + +config SH_SOLUTION_ENGINE + bool "SolutionEngine" + select SOLUTION_ENGINE + select CPU_HAS_IPR_IRQ + depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \ + CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \ + CPU_SUBTYPE_SH7750R + help + Select SolutionEngine if configuring for a Hitachi SH7705, SH7709, + SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board. + +config SH_7206_SOLUTION_ENGINE + bool "SolutionEngine7206" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7206 + help + Select 7206 SolutionEngine if configuring for a Hitachi SH7206 + evaluation board. + +config SH_7619_SOLUTION_ENGINE + bool "SolutionEngine7619" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7619 + help + Select 7619 SolutionEngine if configuring for a Hitachi SH7619 + evaluation board. + +config SH_7721_SOLUTION_ENGINE + bool "SolutionEngine7721" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7721 + help + Select 7721 SolutionEngine if configuring for a Hitachi SH7721 + evaluation board. + +config SH_7722_SOLUTION_ENGINE + bool "SolutionEngine7722" + select SOLUTION_ENGINE + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + depends on CPU_SUBTYPE_SH7722 + help + Select 7722 SolutionEngine if configuring for a Hitachi SH772 + evaluation board. + +config SH_7724_SOLUTION_ENGINE + bool "SolutionEngine7724" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7724 + select ARCH_REQUIRE_GPIOLIB + select SND_SOC_AK4642 if SND_SIMPLE_CARD + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select 7724 SolutionEngine if configuring for a Hitachi SH7724 + evaluation board. + +config SH_7751_SOLUTION_ENGINE + bool "SolutionEngine7751" + select SOLUTION_ENGINE + select CPU_HAS_IPR_IRQ + depends on CPU_SUBTYPE_SH7751 + help + Select 7751 SolutionEngine if configuring for a Hitachi SH7751 + evaluation board. + +config SH_7780_SOLUTION_ENGINE + bool "SolutionEngine7780" + select SOLUTION_ENGINE + select SYS_SUPPORTS_PCI + depends on CPU_SUBTYPE_SH7780 + help + Select 7780 SolutionEngine if configuring for a Renesas SH7780 + evaluation board. + +config SH_7343_SOLUTION_ENGINE + bool "SolutionEngine7343" + select SOLUTION_ENGINE + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + depends on CPU_SUBTYPE_SH7343 + help + Select 7343 SolutionEngine if configuring for a Hitachi + SH7343 (SH-Mobile 3AS) evaluation board. + +config SH_HP6XX + bool "HP6XX" + select SYS_SUPPORTS_APM_EMULATION + select HD6446X_SERIES + depends on CPU_SUBTYPE_SH7709 + help + Select HP6XX if configuring for a HP jornada HP6xx. + More information (hardware only) at + <http://www.hp.com/jornada/>. + +config SH_DREAMCAST + bool "Dreamcast" + select SYS_SUPPORTS_PCI + depends on CPU_SUBTYPE_SH7091 + help + Select Dreamcast if configuring for a SEGA Dreamcast. + More information at <http://www.linux-sh.org> + +config SH_SH03 + bool "Interface CTP/PCI-SH03" + depends on CPU_SUBTYPE_SH7751 + select CPU_HAS_IPR_IRQ + select SYS_SUPPORTS_PCI + help + CTP/PCI-SH03 is a CPU module computer that is produced + by Interface Corporation. + More information at <http://www.interface.co.jp> + +config SH_SECUREEDGE5410 + bool "SecureEdge5410" + depends on CPU_SUBTYPE_SH7751R + select CPU_HAS_IPR_IRQ + select SYS_SUPPORTS_PCI + help + Select SecureEdge5410 if configuring for a SnapGear SH board. + This includes both the OEM SecureEdge products as well as the + SME product line. + +config SH_RTS7751R2D + bool "RTS7751R2D" + depends on CPU_SUBTYPE_SH7751R + select SYS_SUPPORTS_PCI + select IO_TRAPPED if MMU + help + Select RTS7751R2D if configuring for a Renesas Technology + Sales SH-Graphics board. + +config SH_RSK + bool "Renesas Starter Kit" + depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \ + CPU_SUBTYPE_SH7264 || CPU_SUBTYPE_SH7269 + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select this option if configuring for any of the RSK+ MCU + evaluation platforms. + +config SH_SDK7780 + bool "SDK7780R3" + depends on CPU_SUBTYPE_SH7780 + select SYS_SUPPORTS_PCI + help + Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3 + evaluation board. + +config SH_SDK7786 + bool "SDK7786" + depends on CPU_SUBTYPE_SH7786 + select SYS_SUPPORTS_PCI + select NO_IOPORT_MAP if !PCI + select ARCH_WANT_OPTIONAL_GPIOLIB + select HAVE_SRAM_POOL + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select SDK7786 if configuring for a Renesas Technology Europe + SH7786-65nm board. + +config SH_HIGHLANDER + bool "Highlander" + depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 + select SYS_SUPPORTS_PCI + select IO_TRAPPED if MMU + +config SH_SH7757LCR + bool "SH7757LCR" + depends on CPU_SUBTYPE_SH7757 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + +config SH_SH7785LCR + bool "SH7785LCR" + depends on CPU_SUBTYPE_SH7785 + select SYS_SUPPORTS_PCI + +config SH_SH7785LCR_29BIT_PHYSMAPS + bool "SH7785LCR 29bit physmaps" + depends on SH_SH7785LCR && 29BIT + default y + help + This board has 2 physical memory maps. It can be changed with + DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, + you can access all on-board device in 29bit address mode. + +config SH_SH7785LCR_PT + bool "SH7785LCR prototype board on 32-bit MMU mode" + depends on SH_SH7785LCR && 32BIT + default n + help + If you use prototype board, this option is enabled. + +config SH_URQUELL + bool "Urquell" + depends on CPU_SUBTYPE_SH7786 + select ARCH_REQUIRE_GPIOLIB + select SYS_SUPPORTS_PCI + select NO_IOPORT_MAP if !PCI + +config SH_MIGOR + bool "Migo-R" + depends on CPU_SUBTYPE_SH7722 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select Migo-R if configuring for the SH7722 Migo-R platform + by Renesas System Solutions Asia Pte. Ltd. + +config SH_AP325RXA + bool "AP-325RXA" + depends on CPU_SUBTYPE_SH7723 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Renesas "AP-325RXA" support. + Compatible with ALGO SYSTEM CO.,LTD. "AP-320A" + +config SH_KFR2R09 + bool "KFR2R09" + depends on CPU_SUBTYPE_SH7724 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + "Kit For R2R for 2009" support. + +config SH_ECOVEC + bool "EcoVec" + depends on CPU_SUBTYPE_SH7724 + select ARCH_REQUIRE_GPIOLIB + select SND_SOC_DA7210 if SND_SIMPLE_CARD + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Renesas "R0P7724LC0011/21RL (EcoVec)" support. + +config SH_SH7763RDP + bool "SH7763RDP" + depends on CPU_SUBTYPE_SH7763 + help + Select SH7763RDP if configuring for a Renesas SH7763 + evaluation board. + +config SH_ESPT + bool "ESPT" + depends on CPU_SUBTYPE_SH7763 + help + Select ESPT if configuring for a Renesas SH7763 + with gigabit ether evaluation board. + +config SH_EDOSK7705 + bool "EDOSK7705" + depends on CPU_SUBTYPE_SH7705 + +config SH_EDOSK7760 + bool "EDOSK7760" + depends on CPU_SUBTYPE_SH7760 + help + Select if configuring for a Renesas EDOSK7760 + evaluation board. + +config SH_SH4202_MICRODEV + bool "SH4-202 MicroDev" + depends on CPU_SUBTYPE_SH4_202 + help + Select SH4-202 MicroDev if configuring for a SuperH MicroDev board + with an SH4-202 CPU. + +config SH_LANDISK + bool "LANDISK" + depends on CPU_SUBTYPE_SH7751R + select SYS_SUPPORTS_PCI + help + I-O DATA DEVICE, INC. "LANDISK Series" support. + +config SH_TITAN + bool "TITAN" + depends on CPU_SUBTYPE_SH7751R + select CPU_HAS_IPR_IRQ + select SYS_SUPPORTS_PCI + help + Select Titan if you are configuring for a Nimble Microsystems + NetEngine NP51R. + +config SH_SHMIN + bool "SHMIN" + depends on CPU_SUBTYPE_SH7706 + select CPU_HAS_IPR_IRQ + help + Select SHMIN if configuring for the SHMIN board. + +config SH_LBOX_RE2 + bool "L-BOX RE2" + depends on CPU_SUBTYPE_SH7751R + select SYS_SUPPORTS_PCI + help + Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2. + +config SH_X3PROTO + bool "SH-X3 Prototype board" + depends on CPU_SUBTYPE_SHX3 + select NO_IOPORT_MAP if !PCI + select IRQ_DOMAIN + +config SH_MAGIC_PANEL_R2 + bool "Magic Panel R2" + depends on CPU_SUBTYPE_SH7720 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select Magic Panel R2 if configuring for Magic Panel R2. + +config SH_CAYMAN + bool "Hitachi Cayman" + depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103 + select SYS_SUPPORTS_PCI + select ARCH_MIGHT_HAVE_PC_SERIO + +config SH_POLARIS + bool "SMSC Polaris" + select CPU_HAS_IPR_IRQ + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7709 + help + Select if configuring for an SMSC Polaris development board + +config SH_SH2007 + bool "SH-2007 board" + select NO_IOPORT_MAP + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7780 + help + SH-2007 is a single-board computer based around SH7780 chip + intended for embedded applications. + It has an Ethernet interface (SMC9118), direct connected + Compact Flash socket, two serial ports and PC-104 bus. + More information at <http://sh2000.sh-linux.org>. + +config SH_APSH4A3A + bool "AP-SH4A-3A" + select SH_ALPHA_BOARD + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7785 + help + Select AP-SH4A-3A if configuring for an ALPHAPROJECT AP-SH4A-3A. + +config SH_APSH4AD0A + bool "AP-SH4AD-0A" + select SH_ALPHA_BOARD + select SYS_SUPPORTS_PCI + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7786 + help + Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. + +source "arch/sh/boards/mach-r2d/Kconfig" +source "arch/sh/boards/mach-highlander/Kconfig" +source "arch/sh/boards/mach-sdk7780/Kconfig" +source "arch/sh/boards/mach-migor/Kconfig" +source "arch/sh/boards/mach-rsk/Kconfig" + +if SH_MAGIC_PANEL_R2 + +menu "Magic Panel R2 options" + +config SH_MAGIC_PANEL_R2_VERSION + int SH_MAGIC_PANEL_R2_VERSION + default "3" + help + Set the version of the Magic Panel R2 + +endmenu + +endif + +endmenu diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile new file mode 100644 index 00000000000..975a0f64ff2 --- /dev/null +++ b/arch/sh/boards/Makefile @@ -0,0 +1,17 @@ +# +# Specific board support, not covered by a mach group. +# +obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o +obj-$(CONFIG_SH_SECUREEDGE5410) += board-secureedge5410.o +obj-$(CONFIG_SH_SH2007) += board-sh2007.o +obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o +obj-$(CONFIG_SH_URQUELL) += board-urquell.o +obj-$(CONFIG_SH_SHMIN) += board-shmin.o +obj-$(CONFIG_SH_EDOSK7705) += board-edosk7705.o +obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o +obj-$(CONFIG_SH_ESPT) += board-espt.o +obj-$(CONFIG_SH_POLARIS) += board-polaris.o +obj-$(CONFIG_SH_TITAN) += board-titan.o +obj-$(CONFIG_SH_SH7757LCR) += board-sh7757lcr.o +obj-$(CONFIG_SH_APSH4A3A) += board-apsh4a3a.o +obj-$(CONFIG_SH_APSH4AD0A) += board-apsh4ad0a.o diff --git a/arch/sh/boards/board-apsh4a3a.c b/arch/sh/boards/board-apsh4a3a.c new file mode 100644 index 00000000000..0a39c241628 --- /dev/null +++ b/arch/sh/boards/board-apsh4a3a.c @@ -0,0 +1,185 @@ +/* + * ALPHAPROJECT AP-SH4A-3A Support. + * + * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd. + * Copyright (C) 2008 Yoshihiro Shimoda + * Copyright (C) 2009 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/mtd/physmap.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/smsc911x.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <asm/machvec.h> +#include <asm/sizes.h> +#include <asm/clock.h> + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 4, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x01000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = 0xA4000000, + .end = 0xA4000000 + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = evt2irq(0x200), + .end = evt2irq(0x200), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *apsh4a3a_devices[] __initdata = { + &nor_flash_device, + &smsc911x_device, +}; + +static int __init apsh4a3a_devices_setup(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + return platform_add_devices(apsh4a3a_devices, + ARRAY_SIZE(apsh4a3a_devices)); +} +device_initcall(apsh4a3a_devices_setup); + +static int apsh4a3a_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333000); + clk_put(clk); + + return ret; +} + +/* Initialize the board */ +static void __init apsh4a3a_setup(char **cmdline_p) +{ + printk(KERN_INFO "Alpha Project AP-SH4A-3A support:\n"); +} + +static void __init apsh4a3a_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); +} + +/* Return the board specific boot mode pin configuration */ +static int apsh4a3a_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of SW1 and SW2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value &= ~MODE_PIN0; /* Clock Mode 16 */ + value &= ~MODE_PIN1; + value &= ~MODE_PIN2; + value &= ~MODE_PIN3; + value |= MODE_PIN4; + value &= ~MODE_PIN5; /* 16-bit Area0 bus width */ + value |= MODE_PIN6; /* Area 0 SRAM interface */ + value |= MODE_PIN7; + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Master Mode */ + value |= MODE_PIN10; /* Crystal resonator */ + value |= MODE_PIN11; /* Display Unit */ + value |= MODE_PIN12; + value &= ~MODE_PIN13; /* 29-bit address mode */ + value |= MODE_PIN14; /* No PLL step-up */ + + return value; +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_apsh4a3a __initmv = { + .mv_name = "AP-SH4A-3A", + .mv_setup = apsh4a3a_setup, + .mv_clk_init = apsh4a3a_clk_init, + .mv_init_irq = apsh4a3a_init_irq, + .mv_mode_pins = apsh4a3a_mode_pins, +}; diff --git a/arch/sh/boards/board-apsh4ad0a.c b/arch/sh/boards/board-apsh4ad0a.c new file mode 100644 index 00000000000..92eac3a9918 --- /dev/null +++ b/arch/sh/boards/board-apsh4ad0a.c @@ -0,0 +1,135 @@ +/* + * ALPHAPROJECT AP-SH4AD-0A Support. + * + * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd. + * Copyright (C) 2010 Matt Fleming + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/smsc911x.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <asm/machvec.h> +#include <asm/sizes.h> + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = 0xA4000000, + .end = 0xA4000000 + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = evt2irq(0x200), + .end = evt2irq(0x200), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *apsh4ad0a_devices[] __initdata = { + &smsc911x_device, +}; + +static int __init apsh4ad0a_devices_setup(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + return platform_add_devices(apsh4ad0a_devices, + ARRAY_SIZE(apsh4ad0a_devices)); +} +device_initcall(apsh4ad0a_devices_setup); + +static int apsh4ad0a_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of SW1 and SW2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN0; /* Clock Mode 3 */ + value |= MODE_PIN1; + value &= ~MODE_PIN2; + value &= ~MODE_PIN3; + value &= ~MODE_PIN4; /* 16-bit Area0 bus width */ + value |= MODE_PIN5; + value |= MODE_PIN6; + value |= MODE_PIN7; /* Normal mode */ + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Crystal resonator */ + value &= ~MODE_PIN10; /* 29-bit address mode */ + value &= ~MODE_PIN11; /* PCI-E Root port */ + value &= ~MODE_PIN12; /* 4 lane + 1 lane */ + value |= MODE_PIN13; /* AUD Enable */ + value &= ~MODE_PIN14; /* Normal Operation */ + + return value; +} + +static int apsh4ad0a_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333000); + clk_put(clk); + + return ret; +} + +/* Initialize the board */ +static void __init apsh4ad0a_setup(char **cmdline_p) +{ + pr_info("Alpha Project AP-SH4AD-0A support:\n"); +} + +static void __init apsh4ad0a_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_apsh4ad0a __initmv = { + .mv_name = "AP-SH4AD-0A", + .mv_setup = apsh4ad0a_setup, + .mv_mode_pins = apsh4ad0a_mode_pins, + .mv_clk_init = apsh4ad0a_clk_init, + .mv_init_irq = apsh4ad0a_init_irq, +}; diff --git a/arch/sh/boards/board-edosk7705.c b/arch/sh/boards/board-edosk7705.c new file mode 100644 index 00000000000..5e24c17bbda --- /dev/null +++ b/arch/sh/boards/board-edosk7705.c @@ -0,0 +1,78 @@ +/* + * arch/sh/boards/renesas/edosk7705/setup.c + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine Support. + * + * Modified for edosk7705 development + * board by S. Dunn, 2003. + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/smc91x.h> +#include <linux/sh_intc.h> +#include <asm/machvec.h> +#include <asm/sizes.h> + +#define SMC_IOBASE 0xA2000000 +#define SMC_IO_OFFSET 0x300 +#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET) + +#define ETHERNET_IRQ evt2irq(0x320) + +static void __init sh_edosk7705_init_irq(void) +{ + make_imask_irq(ETHERNET_IRQ); +} + +/* eth initialization functions */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL, +}; + +static struct resource smc91x_res[] = { + [0] = { + .start = SMC_IOADDR, + .end = SMC_IOADDR + SZ_32 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ETHERNET_IRQ, + .end = ETHERNET_IRQ, + .flags = IORESOURCE_IRQ , + } +}; + +static struct platform_device smc91x_dev = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_res), + .resource = smc91x_res, + + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* platform init code */ +static struct platform_device *edosk7705_devices[] __initdata = { + &smc91x_dev, +}; + +static int __init init_edosk7705_devices(void) +{ + return platform_add_devices(edosk7705_devices, + ARRAY_SIZE(edosk7705_devices)); +} +device_initcall(init_edosk7705_devices); + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_edosk7705 __initmv = { + .mv_name = "EDOSK7705", + .mv_init_irq = sh_edosk7705_init_irq, +}; diff --git a/arch/sh/boards/board-edosk7760.c b/arch/sh/boards/board-edosk7760.c new file mode 100644 index 00000000000..bab5b951390 --- /dev/null +++ b/arch/sh/boards/board-edosk7760.c @@ -0,0 +1,191 @@ +/* + * Renesas Europe EDOSK7760 Board Support + * + * Copyright (C) 2008 SPES Societa' Progettazione Elettronica e Software Ltd. + * Author: Luca Santini <luca.santini@spesonline.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <linux/init.h> +#include <linux/types.h> +#include <linux/platform_device.h> +#include <linux/smc91x.h> +#include <linux/interrupt.h> +#include <linux/sh_intc.h> +#include <linux/i2c.h> +#include <linux/mtd/physmap.h> +#include <asm/machvec.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/delay.h> +#include <asm/i2c-sh7760.h> +#include <asm/sizes.h> + +/* Bus state controller registers for CS4 area */ +#define BSC_CS4BCR 0xA4FD0010 +#define BSC_CS4WCR 0xA4FD0030 + +#define SMC_IOBASE 0xA2000000 +#define SMC_IO_OFFSET 0x300 +#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET) + +/* NOR flash */ +static struct mtd_partition edosk7760_nor_flash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + }, { + .name = "fs", + .offset = MTDPART_OFS_APPEND, + .size = (26 << 20), + }, { + .name = "other", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data edosk7760_nor_flash_data = { + .width = 4, + .parts = edosk7760_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(edosk7760_nor_flash_partitions), +}; + +static struct resource edosk7760_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x00000000 + SZ_32M - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device edosk7760_nor_flash_device = { + .name = "physmap-flash", + .resource = edosk7760_nor_flash_resources, + .num_resources = ARRAY_SIZE(edosk7760_nor_flash_resources), + .dev = { + .platform_data = &edosk7760_nor_flash_data, + }, +}; + +/* i2c initialization functions */ +static struct sh7760_i2c_platdata i2c_pd = { + .speed_khz = 400, +}; + +static struct resource sh7760_i2c1_res[] = { + { + .start = SH7760_I2C1_MMIO, + .end = SH7760_I2C1_MMIOEND, + .flags = IORESOURCE_MEM, + },{ + .start = evt2irq(0x9e0), + .end = evt2irq(0x9e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh7760_i2c1_dev = { + .dev = { + .platform_data = &i2c_pd, + }, + + .name = SH7760_I2C_DEVNAME, + .id = 1, + .resource = sh7760_i2c1_res, + .num_resources = ARRAY_SIZE(sh7760_i2c1_res), +}; + +static struct resource sh7760_i2c0_res[] = { + { + .start = SH7760_I2C0_MMIO, + .end = SH7760_I2C0_MMIOEND, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x9c0), + .end = evt2irq(0x9c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh7760_i2c0_dev = { + .dev = { + .platform_data = &i2c_pd, + }, + .name = SH7760_I2C_DEVNAME, + .id = 0, + .resource = sh7760_i2c0_res, + .num_resources = ARRAY_SIZE(sh7760_i2c0_res), +}; + +/* eth initialization functions */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL, +}; + +static struct resource smc91x_res[] = { + [0] = { + .start = SMC_IOADDR, + .end = SMC_IOADDR + SZ_32 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x2a0), + .end = evt2irq(0x2a0), + .flags = IORESOURCE_IRQ , + } +}; + +static struct platform_device smc91x_dev = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_res), + .resource = smc91x_res, + + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* platform init code */ +static struct platform_device *edosk7760_devices[] __initdata = { + &smc91x_dev, + &edosk7760_nor_flash_device, + &sh7760_i2c0_dev, + &sh7760_i2c1_dev, +}; + +static int __init init_edosk7760_devices(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); + + return platform_add_devices(edosk7760_devices, + ARRAY_SIZE(edosk7760_devices)); +} +device_initcall(init_edosk7760_devices); + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_edosk7760 __initmv = { + .mv_name = "EDOSK7760", +}; diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c new file mode 100644 index 00000000000..7291e2f11a4 --- /dev/null +++ b/arch/sh/boards/board-espt.c @@ -0,0 +1,109 @@ +/* + * Data Technology Inc. ESPT-GIGA board support + * + * Copyright (C) 2008, 2009 Renesas Solutions Corp. + * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/mtd/physmap.h> +#include <linux/io.h> +#include <linux/sh_eth.h> +#include <linux/sh_intc.h> +#include <asm/machvec.h> +#include <asm/sizes.h> + +/* NOR Flash */ +static struct mtd_partition espt_nor_flash_partitions[] = { + { + .name = "U-Boot", + .offset = 0, + .size = (2 * SZ_128K), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "Linux-Kernel", + .offset = MTDPART_OFS_APPEND, + .size = (20 * SZ_128K), + }, { + .name = "Root Filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data espt_nor_flash_data = { + .width = 2, + .parts = espt_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(espt_nor_flash_partitions), +}; + +static struct resource espt_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0, + .end = SZ_8M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device espt_nor_flash_device = { + .name = "physmap-flash", + .resource = espt_nor_flash_resources, + .num_resources = ARRAY_SIZE(espt_nor_flash_resources), + .dev = { + .platform_data = &espt_nor_flash_data, + }, +}; + +/* SH-Ether */ +static struct resource sh_eth_resources[] = { + { + .start = 0xFEE00800, /* use eth1 */ + .end = 0xFEE00F7C - 1, + .flags = IORESOURCE_MEM, + }, { + .start = 0xFEE01800, /* TSU */ + .end = 0xFEE01FFF, + .flags = IORESOURCE_MEM, + }, { + + .start = evt2irq(0x920), /* irq number */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7763_eth_pdata = { + .phy = 0, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device espt_eth_device = { + .name = "sh7763-gether", + .resource = sh_eth_resources, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .dev = { + .platform_data = &sh7763_eth_pdata, + }, +}; + +static struct platform_device *espt_devices[] __initdata = { + &espt_nor_flash_device, + &espt_eth_device, +}; + +static int __init espt_devices_setup(void) +{ + return platform_add_devices(espt_devices, + ARRAY_SIZE(espt_devices)); +} +device_initcall(espt_devices_setup); + +static struct sh_machine_vector mv_espt __initmv = { + .mv_name = "ESPT-GIGA", +}; diff --git a/arch/sh/boards/magicpanelr2/setup.c b/arch/sh/boards/board-magicpanelr2.c index f3b8b07ea5d..20500858b56 100644 --- a/arch/sh/boards/magicpanelr2/setup.c +++ b/arch/sh/boards/board-magicpanelr2.c @@ -13,17 +13,26 @@ #include <linux/irq.h> #include <linux/platform_device.h> #include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/smsc911x.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/mtd/map.h> -#include <asm/magicpanelr2.h> +#include <linux/sh_intc.h> +#include <mach/magicpanelr2.h> #include <asm/heartbeat.h> +#include <cpu/sh7720.h> -#define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL) +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; -/* Prefer cmdline over RedBoot */ -static const char *probes[] = { "cmdlinepart", "RedBoot", NULL }; +#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) /* Wait until reset finished. Timeout is 100ms. */ static int __init ethernet_reset_finished(void) @@ -57,33 +66,33 @@ static void __init setup_chip_select(void) { /* CS2: LAN (0x08000000 - 0x0bffffff) */ /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x36db0400, CS2BCR); + __raw_writel(0x36db0400, CS2BCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - ctrl_outl(0x000003c0, CS2WCR); + __raw_writel(0x000003c0, CS2WCR); /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x00000200, CS4BCR); + __raw_writel(0x00000200, CS4BCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - ctrl_outl(0x00100981, CS4WCR); + __raw_writel(0x00100981, CS4WCR); /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x00000200, CS5ABCR); + __raw_writel(0x00000200, CS5ABCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - ctrl_outl(0x00100981, CS5AWCR); + __raw_writel(0x00100981, CS5AWCR); /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x00000200, CS5BBCR); + __raw_writel(0x00000200, CS5BBCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - ctrl_outl(0x00100981, CS5BWCR); + __raw_writel(0x00100981, CS5BWCR); /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x00000200, CS6ABCR); + __raw_writel(0x00000200, CS6ABCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ - ctrl_outl(0x001009C1, CS6AWCR); + __raw_writel(0x001009C1, CS6AWCR); } static void __init setup_port_multiplexing(void) @@ -91,71 +100,71 @@ static void __init setup_port_multiplexing(void) /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */ - ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ + __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */ - ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ + __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */ - ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ + __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */ - ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ + __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */ - ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ + __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */ - ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ + __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */ - ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ + __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */ - ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ + __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */ - ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ + __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ /* K7 (x); K6 (x); K5 (x); K4 (x); * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) */ - ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ + __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; * L3 TCK; L2 (x); L1 (x); L0 (x); */ - ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ + __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); * M1 CS5B(CAN3_CS); M0 GPI+(nc); */ - ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ + __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, * LAN_RESET=off, BUZZER=off, LCD_BL=off */ #if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 - ctrl_outb(0x30, PORT_PMDR); + __raw_writeb(0x30, PORT_PMDR); #elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 - ctrl_outb(0xF0, PORT_PMDR); + __raw_writeb(0xF0, PORT_PMDR); #else #error Unknown revision of PLATFORM_MP_R2 #endif @@ -164,61 +173,66 @@ static void __init setup_port_multiplexing(void) * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) */ - ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ - ctrl_outb(0x10, PORT_PPDR); + __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ + __raw_writeb(0x10, PORT_PPDR); /* R7 A25; R6 A24; R5 A23; R4 A22; * R3 A21; R2 A20; R1 A19; R0 A0; */ - ctrl_outw(0x0000, PORT_PRCR); /* 00 00 00 00 00 00 00 00 */ + gpio_request(GPIO_FN_A25, NULL); + gpio_request(GPIO_FN_A24, NULL); + gpio_request(GPIO_FN_A23, NULL); + gpio_request(GPIO_FN_A22, NULL); + gpio_request(GPIO_FN_A21, NULL); + gpio_request(GPIO_FN_A20, NULL); + gpio_request(GPIO_FN_A19, NULL); + gpio_request(GPIO_FN_A0, NULL); /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */ - ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ + __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) */ - ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ + __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */ - ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ + __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */ - ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ + __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ } static void __init mpr2_setup(char **cmdline_p) { - __set_io_port_base(0xa0000000); - /* set Pin Select Register A: * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */ - ctrl_outw(0xAABC, PORT_PSELA); + __raw_writew(0xAABC, PORT_PSELA); /* set Pin Select Register B: * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */ - ctrl_outw(0x3C00, PORT_PSELB); + __raw_writew(0x3C00, PORT_PSELB); /* set Pin Select Register C: * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */ - ctrl_outw(0x0000, PORT_PSELC); + __raw_writew(0x0000, PORT_PSELC); /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */ - ctrl_outw(0x0000, PORT_PSELD); + __raw_writew(0x0000, PORT_PSELD); /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ - ctrl_outw(0x0101, PORT_UTRCTL); + __raw_writew(0x0101, PORT_UTRCTL); /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ - ctrl_outw(0xA5C0, PORT_UCLKCR_W); + __raw_writew(0xA5C0, PORT_UCLKCR_W); setup_chip_select(); @@ -233,24 +247,34 @@ static void __init mpr2_setup(char **cmdline_p) printk(KERN_WARNING "Ethernet not ready\n"); } -static struct resource smc911x_resources[] = { +static struct resource smsc911x_resources[] = { [0] = { .start = 0xa8000000, .end = 0xabffffff, .flags = IORESOURCE_MEM, }, [1] = { - .start = 35, - .end = 35, + .start = evt2irq(0x660), + .end = evt2irq(0x660), .flags = IORESOURCE_IRQ, }, }; -static struct platform_device smc911x_device = { - .name = "smc911x", +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", .id = -1, - .num_resources = ARRAY_SIZE(smc911x_resources), - .resource = smc911x_resources, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, }; static struct resource heartbeat_resources[] = { @@ -275,8 +299,6 @@ static struct platform_device heartbeat_device = { .resource = heartbeat_resources, }; -static struct mtd_partition *parsed_partitions; - static struct mtd_partition mpr2_partitions[] = { /* Reserved for bootloader, read-only */ { @@ -300,6 +322,8 @@ static struct mtd_partition mpr2_partitions[] = { }; static struct physmap_flash_data flash_data = { + .parts = mpr2_partitions, + .nr_parts = ARRAY_SIZE(mpr2_partitions), .width = 2, }; @@ -319,46 +343,21 @@ static struct platform_device flash_device = { }, }; -static struct mtd_info *flash_mtd; - -static struct map_info mpr2_flash_map = { - .name = "Magic Panel R2 Flash", - .size = 0x2000000UL, - .bankwidth = 2, -}; - -static void __init set_mtd_partitions(void) -{ - int nr_parts = 0; - - simple_map_init(&mpr2_flash_map); - flash_mtd = do_map_probe("cfi_probe", &mpr2_flash_map); - nr_parts = parse_mtd_partitions(flash_mtd, probes, - &parsed_partitions, 0); - /* If there is no partition table, used the hard coded table */ - if (nr_parts <= 0) { - flash_data.parts = mpr2_partitions; - flash_data.nr_parts = ARRAY_SIZE(mpr2_partitions); - } else { - flash_data.nr_parts = nr_parts; - flash_data.parts = parsed_partitions; - } -} - /* * Add all resources to the platform_device */ static struct platform_device *mpr2_devices[] __initdata = { &heartbeat_device, - &smc911x_device, + &smsc911x_device, &flash_device, }; static int __init mpr2_devices_setup(void) { - set_mtd_partitions(); + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); } device_initcall(mpr2_devices_setup); @@ -370,17 +369,17 @@ static void __init init_mpr2_IRQ(void) { plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ - set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ - set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ - set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ - set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ - set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ - set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ - - intc_set_priority(32, 13); /* IRQ0 CAN1 */ - intc_set_priority(33, 13); /* IRQ0 CAN2 */ - intc_set_priority(34, 13); /* IRQ0 CAN3 */ - intc_set_priority(35, 6); /* IRQ3 SMSC9115 */ + irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ + irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ + irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ + irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ + irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ + irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ + + intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */ + intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */ + intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */ + intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */ } /* diff --git a/arch/sh/boards/board-polaris.c b/arch/sh/boards/board-polaris.c new file mode 100644 index 00000000000..37a08d09472 --- /dev/null +++ b/arch/sh/boards/board-polaris.c @@ -0,0 +1,155 @@ +/* + * June 2006 Steve Glendinning <steve.glendinning@shawell.net> + * + * Polaris-specific resource declaration + * + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/smsc911x.h> +#include <linux/io.h> +#include <asm/irq.h> +#include <asm/machvec.h> +#include <asm/heartbeat.h> +#include <cpu/gpio.h> +#include <mach-se/mach/se.h> + +#define BCR2 (0xFFFFFF62) +#define WCR2 (0xFFFFFF66) +#define AREA5_WAIT_CTRL (0x1C00) +#define WAIT_STATES_10 (0x7) + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = PA_EXT5, + .end = PA_EXT5 + 0x1fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = IRQ0_IRQ, + .end = IRQ0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), +}; + +static struct resource heartbeat_resource = { + .start = PORT_PCDR, + .end = PORT_PCDR, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +static struct platform_device *polaris_devices[] __initdata = { + &smsc911x_device, + &heartbeat_device, +}; + +static int __init polaris_initialise(void) +{ + u16 wcr, bcr_mask; + + printk(KERN_INFO "Configuring Polaris external bus\n"); + + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + /* Configure area 5 with 2 wait states */ + wcr = __raw_readw(WCR2); + wcr &= (~AREA5_WAIT_CTRL); + wcr |= (WAIT_STATES_10 << 10); + __raw_writew(wcr, WCR2); + + /* Configure area 5 for 32-bit access */ + bcr_mask = __raw_readw(BCR2); + bcr_mask |= 1 << 10; + __raw_writew(bcr_mask, BCR2); + + return platform_add_devices(polaris_devices, + ARRAY_SIZE(polaris_devices)); +} +arch_initcall(polaris_initialise); + +static struct ipr_data ipr_irq_table[] = { + /* External IRQs */ + { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */ + { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */ +}; + +static unsigned long ipr_offsets[] = { + INTC_IPRC +}; + +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + .chip = { + .name = "sh7709-ext", + }, +}; + +static void __init init_polaris_irq(void) +{ + /* Disable all interrupts */ + __raw_writew(0, BCR_ILCRA); + __raw_writew(0, BCR_ILCRB); + __raw_writew(0, BCR_ILCRC); + __raw_writew(0, BCR_ILCRD); + __raw_writew(0, BCR_ILCRE); + __raw_writew(0, BCR_ILCRF); + __raw_writew(0, BCR_ILCRG); + + register_ipr_controller(&ipr_irq_desc); +} + +static struct sh_machine_vector mv_polaris __initmv = { + .mv_name = "Polaris", + .mv_init_irq = init_polaris_irq, +}; diff --git a/arch/sh/boards/snapgear/setup.c b/arch/sh/boards/board-secureedge5410.c index 7022483f98e..98b36205aa7 100644 --- a/arch/sh/boards/snapgear/setup.c +++ b/arch/sh/boards/board-secureedge5410.c @@ -1,6 +1,4 @@ /* - * linux/arch/sh/boards/snapgear/setup.c - * * Copyright (C) 2002 David McCullough <davidm@snapgear.com> * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org> * @@ -19,19 +17,18 @@ #include <linux/module.h> #include <linux/sched.h> #include <asm/machvec.h> -#include <asm/snapgear.h> +#include <mach/secureedge5410.h> #include <asm/irq.h> #include <asm/io.h> -#include <asm/cpu/timer.h> +#include <cpu/timer.h> + +unsigned short secureedge5410_ioport; /* * EraseConfig handling functions */ - static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id) { - (void)ctrl_inb(0xb8000000); /* dummy read */ - printk("SnapGear: erase switch interrupt!\n"); return IRQ_HANDLED; @@ -39,21 +36,21 @@ static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id) static int __init eraseconfig_init(void) { + unsigned int irq = evt2irq(0x240); + printk("SnapGear: EraseConfig init\n"); + /* Setup "EraseConfig" switch on external IRQ 0 */ - if (request_irq(IRL0_IRQ, eraseconfig_interrupt, IRQF_DISABLED, - "Erase Config", NULL)) + if (request_irq(irq, eraseconfig_interrupt, 0, "Erase Config", NULL)) printk("SnapGear: failed to register IRQ%d for Reset witch\n", - IRL0_IRQ); + irq); else printk("SnapGear: registered EraseConfig switch on IRQ%d\n", - IRL0_IRQ); - return(0); + irq); + return 0; } - module_init(eraseconfig_init); -/****************************************************************************/ /* * Initialize IRQ setting * @@ -62,7 +59,6 @@ module_init(eraseconfig_init); * IRL2 = eth1 * IRL3 = crypto */ - static void __init init_snapgear_IRQ(void) { printk("Setup SnapGear IRQ/IPR ...\n"); @@ -75,21 +71,5 @@ static void __init init_snapgear_IRQ(void) */ static struct sh_machine_vector mv_snapgear __initmv = { .mv_name = "SnapGear SecureEdge5410", - .mv_nr_irqs = 72, - - .mv_inb = snapgear_inb, - .mv_inw = snapgear_inw, - .mv_inl = snapgear_inl, - .mv_outb = snapgear_outb, - .mv_outw = snapgear_outw, - .mv_outl = snapgear_outl, - - .mv_inb_p = snapgear_inb_p, - .mv_inw_p = snapgear_inw, - .mv_inl_p = snapgear_inl, - .mv_outb_p = snapgear_outb_p, - .mv_outw_p = snapgear_outw, - .mv_outl_p = snapgear_outl, - .mv_init_irq = init_snapgear_IRQ, }; diff --git a/arch/sh/boards/board-sh2007.c b/arch/sh/boards/board-sh2007.c new file mode 100644 index 00000000000..1980bb7e578 --- /dev/null +++ b/arch/sh/boards/board-sh2007.c @@ -0,0 +1,145 @@ +/* + * SH-2007 board support. + * + * Copyright (C) 2003, 2004 SUGIOKA Toshinobu + * Copyright (C) 2010 Hitoshi Mitake <mitake@dcl.info.waseda.ac.jp> + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/smsc911x.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/io.h> +#include <asm/machvec.h> +#include <mach/sh2007.h> + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), + REGULATOR_SUPPLY("vddvario", "smsc911x.1"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.1"), +}; + +struct smsc911x_platform_config smc911x_info = { + .flags = SMSC911X_USE_32BIT, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct resource smsc9118_0_resources[] = { + [0] = { + .start = SMC0_BASE, + .end = SMC0_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x240), + .end = evt2irq(0x240), + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource smsc9118_1_resources[] = { + [0] = { + .start = SMC1_BASE, + .end = SMC1_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x280), + .end = evt2irq(0x280), + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smsc9118_0_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc9118_0_resources), + .resource = smsc9118_0_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct platform_device smsc9118_1_device = { + .name = "smsc911x", + .id = 1, + .num_resources = ARRAY_SIZE(smsc9118_1_resources), + .resource = smsc9118_1_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct resource cf_resources[] = { + [0] = { + .start = CF_BASE + CF_OFFSET, + .end = CF_BASE + CF_OFFSET + 0x0f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CF_BASE + CF_OFFSET + 0x206, + .end = CF_BASE + CF_OFFSET + 0x20f, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = evt2irq(0x2c0), + .end = evt2irq(0x2c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_device = { + .name = "pata_platform", + .id = 0, + .num_resources = ARRAY_SIZE(cf_resources), + .resource = cf_resources, +}; + +static struct platform_device *sh2007_devices[] __initdata = { + &smsc9118_0_device, + &smsc9118_1_device, + &cf_device, +}; + +static int __init sh2007_io_init(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + platform_add_devices(sh2007_devices, ARRAY_SIZE(sh2007_devices)); + return 0; +} +subsys_initcall(sh2007_io_init); + +static void __init sh2007_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +/* + * Initialize the board + */ +static void __init sh2007_setup(char **cmdline_p) +{ + printk(KERN_INFO "SH-2007 Setup..."); + + /* setup wait control registers for area 5 */ + __raw_writel(CS5BCR_D, CS5BCR); + __raw_writel(CS5WCR_D, CS5WCR); + __raw_writel(CS5PCR_D, CS5PCR); + + printk(KERN_INFO " done.\n"); +} + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_sh2007 __initmv = { + .mv_setup = sh2007_setup, + .mv_name = "sh2007", + .mv_init_irq = sh2007_init_irq, +}; diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c new file mode 100644 index 00000000000..669df51a82e --- /dev/null +++ b/arch/sh/boards/board-sh7757lcr.c @@ -0,0 +1,611 @@ +/* + * Renesas R0P7757LC0012RL Support. + * + * Copyright (C) 2009 - 2010 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/io.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> +#include <linux/mmc/sh_mobile_sdhi.h> +#include <linux/sh_eth.h> +#include <linux/sh_intc.h> +#include <linux/usb/renesas_usbhs.h> +#include <cpu/sh7757.h> +#include <asm/heartbeat.h> + +static struct resource heartbeat_resource = { + .start = 0xffec005c, /* PUDR */ + .end = 0xffec005c, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), + .flags = HEARTBEAT_INVERTED, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* Fast Ethernet */ +#define GBECONT 0xffc10100 +#define GBECONT_RMII1 BIT(17) +#define GBECONT_RMII0 BIT(16) +static void sh7757_eth_set_mdio_gate(void *addr) +{ + if (((unsigned long)addr & 0x00000fff) < 0x0800) + writel(readl(GBECONT) | GBECONT_RMII0, GBECONT); + else + writel(readl(GBECONT) | GBECONT_RMII1, GBECONT); +} + +static struct resource sh_eth0_resources[] = { + { + .start = 0xfef00000, + .end = 0xfef001ff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth0_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .set_mdio_gate = sh7757_eth_set_mdio_gate, +}; + +static struct platform_device sh7757_eth0_device = { + .name = "sh7757-ether", + .resource = sh_eth0_resources, + .id = 0, + .num_resources = ARRAY_SIZE(sh_eth0_resources), + .dev = { + .platform_data = &sh7757_eth0_pdata, + }, +}; + +static struct resource sh_eth1_resources[] = { + { + .start = 0xfef00800, + .end = 0xfef009ff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth1_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .set_mdio_gate = sh7757_eth_set_mdio_gate, +}; + +static struct platform_device sh7757_eth1_device = { + .name = "sh7757-ether", + .resource = sh_eth1_resources, + .id = 1, + .num_resources = ARRAY_SIZE(sh_eth1_resources), + .dev = { + .platform_data = &sh7757_eth1_pdata, + }, +}; + +static void sh7757_eth_giga_set_mdio_gate(void *addr) +{ + if (((unsigned long)addr & 0x00000fff) < 0x0800) { + gpio_set_value(GPIO_PTT4, 1); + writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT); + } else { + gpio_set_value(GPIO_PTT4, 0); + writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT); + } +} + +static struct resource sh_eth_giga0_resources[] = { + { + .start = 0xfee00000, + .end = 0xfee007ff, + .flags = IORESOURCE_MEM, + }, { + /* TSU */ + .start = 0xfee01800, + .end = 0xfee01fff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x2960), + .end = evt2irq(0x2960), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth_giga0_pdata = { + .phy = 18, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, +}; + +static struct platform_device sh7757_eth_giga0_device = { + .name = "sh7757-gether", + .resource = sh_eth_giga0_resources, + .id = 2, + .num_resources = ARRAY_SIZE(sh_eth_giga0_resources), + .dev = { + .platform_data = &sh7757_eth_giga0_pdata, + }, +}; + +static struct resource sh_eth_giga1_resources[] = { + { + .start = 0xfee00800, + .end = 0xfee00fff, + .flags = IORESOURCE_MEM, + }, { + /* TSU */ + .start = 0xfee01800, + .end = 0xfee01fff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x2980), + .end = evt2irq(0x2980), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth_giga1_pdata = { + .phy = 19, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, +}; + +static struct platform_device sh7757_eth_giga1_device = { + .name = "sh7757-gether", + .resource = sh_eth_giga1_resources, + .id = 3, + .num_resources = ARRAY_SIZE(sh_eth_giga1_resources), + .dev = { + .platform_data = &sh7757_eth_giga1_pdata, + }, +}; + +/* Fixed 3.3V regulator to be used by SDHI0, MMCIF */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), +}; + +/* SH_MMCIF */ +static struct resource sh_mmcif_resources[] = { + [0] = { + .start = 0xffcb0000, + .end = 0xffcb00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x1c60), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = evt2irq(0x1c80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_plat_data sh_mmcif_plat = { + .sup_pclk = 0x0f, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | + MMC_CAP_NONREMOVABLE, + .ocr = MMC_VDD_32_33 | MMC_VDD_33_34, + .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, + .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, +}; + +static struct platform_device sh_mmcif_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .platform_data = &sh_mmcif_plat, + }, + .num_resources = ARRAY_SIZE(sh_mmcif_resources), + .resource = sh_mmcif_resources, +}; + +/* SDHI0 */ +static struct sh_mobile_sdhi_info sdhi_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI_RX, + .tmio_caps = MMC_CAP_SD_HIGHSPEED, +}; + +static struct resource sdhi_resources[] = { + [0] = { + .start = 0xffe50000, + .end = 0xffe500ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x480), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi_resources), + .resource = sdhi_resources, + .id = 0, + .dev = { + .platform_data = &sdhi_info, + }, +}; + +static int usbhs0_get_id(struct platform_device *pdev) +{ + return USBHS_GADGET; +} + +static struct renesas_usbhs_platform_info usb0_data = { + .platform_callback = { + .get_id = usbhs0_get_id, + }, + .driver_param = { + .buswait_bwait = 5, + } +}; + +static struct resource usb0_resources[] = { + [0] = { + .start = 0xfe450000, + .end = 0xfe4501ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x840), + .end = evt2irq(0x840), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb0_device = { + .name = "renesas_usbhs", + .id = 0, + .dev = { + .platform_data = &usb0_data, + }, + .num_resources = ARRAY_SIZE(usb0_resources), + .resource = usb0_resources, +}; + +static struct platform_device *sh7757lcr_devices[] __initdata = { + &heartbeat_device, + &sh7757_eth0_device, + &sh7757_eth1_device, + &sh7757_eth_giga0_device, + &sh7757_eth_giga1_device, + &sh_mmcif_device, + &sdhi_device, + &usb0_device, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "m25p80", + .type = "m25px64", +}; + +static struct spi_board_info spi_board_info[] = { + { + .modalias = "m25p80", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &spi_flash_data, + }, +}; + +static int __init sh7757lcr_devices_setup(void) +{ + regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + + /* RGMII (PTA) */ + gpio_request(GPIO_FN_ET0_MDC, NULL); + gpio_request(GPIO_FN_ET0_MDIO, NULL); + gpio_request(GPIO_FN_ET1_MDC, NULL); + gpio_request(GPIO_FN_ET1_MDIO, NULL); + + /* ONFI (PTB, PTZ) */ + gpio_request(GPIO_FN_ON_NRE, NULL); + gpio_request(GPIO_FN_ON_NWE, NULL); + gpio_request(GPIO_FN_ON_NWP, NULL); + gpio_request(GPIO_FN_ON_NCE0, NULL); + gpio_request(GPIO_FN_ON_R_B0, NULL); + gpio_request(GPIO_FN_ON_ALE, NULL); + gpio_request(GPIO_FN_ON_CLE, NULL); + + gpio_request(GPIO_FN_ON_DQ7, NULL); + gpio_request(GPIO_FN_ON_DQ6, NULL); + gpio_request(GPIO_FN_ON_DQ5, NULL); + gpio_request(GPIO_FN_ON_DQ4, NULL); + gpio_request(GPIO_FN_ON_DQ3, NULL); + gpio_request(GPIO_FN_ON_DQ2, NULL); + gpio_request(GPIO_FN_ON_DQ1, NULL); + gpio_request(GPIO_FN_ON_DQ0, NULL); + + /* IRQ8 to 0 (PTB, PTC) */ + gpio_request(GPIO_FN_IRQ8, NULL); + gpio_request(GPIO_FN_IRQ7, NULL); + gpio_request(GPIO_FN_IRQ6, NULL); + gpio_request(GPIO_FN_IRQ5, NULL); + gpio_request(GPIO_FN_IRQ4, NULL); + gpio_request(GPIO_FN_IRQ3, NULL); + gpio_request(GPIO_FN_IRQ2, NULL); + gpio_request(GPIO_FN_IRQ1, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + /* SPI0 (PTD) */ + gpio_request(GPIO_FN_SP0_MOSI, NULL); + gpio_request(GPIO_FN_SP0_MISO, NULL); + gpio_request(GPIO_FN_SP0_SCK, NULL); + gpio_request(GPIO_FN_SP0_SCK_FB, NULL); + gpio_request(GPIO_FN_SP0_SS0, NULL); + gpio_request(GPIO_FN_SP0_SS1, NULL); + gpio_request(GPIO_FN_SP0_SS2, NULL); + gpio_request(GPIO_FN_SP0_SS3, NULL); + + /* RMII 0/1 (PTE, PTF) */ + gpio_request(GPIO_FN_RMII0_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII0_TXD1, NULL); + gpio_request(GPIO_FN_RMII0_TXD0, NULL); + gpio_request(GPIO_FN_RMII0_TXEN, NULL); + gpio_request(GPIO_FN_RMII0_REFCLK, NULL); + gpio_request(GPIO_FN_RMII0_RXD1, NULL); + gpio_request(GPIO_FN_RMII0_RXD0, NULL); + gpio_request(GPIO_FN_RMII0_RX_ER, NULL); + gpio_request(GPIO_FN_RMII1_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII1_TXD1, NULL); + gpio_request(GPIO_FN_RMII1_TXD0, NULL); + gpio_request(GPIO_FN_RMII1_TXEN, NULL); + gpio_request(GPIO_FN_RMII1_REFCLK, NULL); + gpio_request(GPIO_FN_RMII1_RXD1, NULL); + gpio_request(GPIO_FN_RMII1_RXD0, NULL); + gpio_request(GPIO_FN_RMII1_RX_ER, NULL); + + /* eMMC (PTG) */ + gpio_request(GPIO_FN_MMCCLK, NULL); + gpio_request(GPIO_FN_MMCCMD, NULL); + gpio_request(GPIO_FN_MMCDAT7, NULL); + gpio_request(GPIO_FN_MMCDAT6, NULL); + gpio_request(GPIO_FN_MMCDAT5, NULL); + gpio_request(GPIO_FN_MMCDAT4, NULL); + gpio_request(GPIO_FN_MMCDAT3, NULL); + gpio_request(GPIO_FN_MMCDAT2, NULL); + gpio_request(GPIO_FN_MMCDAT1, NULL); + gpio_request(GPIO_FN_MMCDAT0, NULL); + + /* LPC (PTG, PTH, PTQ, PTU) */ + gpio_request(GPIO_FN_SERIRQ, NULL); + gpio_request(GPIO_FN_LPCPD, NULL); + gpio_request(GPIO_FN_LDRQ, NULL); + gpio_request(GPIO_FN_WP, NULL); + gpio_request(GPIO_FN_FMS0, NULL); + gpio_request(GPIO_FN_LAD3, NULL); + gpio_request(GPIO_FN_LAD2, NULL); + gpio_request(GPIO_FN_LAD1, NULL); + gpio_request(GPIO_FN_LAD0, NULL); + gpio_request(GPIO_FN_LFRAME, NULL); + gpio_request(GPIO_FN_LRESET, NULL); + gpio_request(GPIO_FN_LCLK, NULL); + gpio_request(GPIO_FN_LGPIO7, NULL); + gpio_request(GPIO_FN_LGPIO6, NULL); + gpio_request(GPIO_FN_LGPIO5, NULL); + gpio_request(GPIO_FN_LGPIO4, NULL); + + /* SPI1 (PTH) */ + gpio_request(GPIO_FN_SP1_MOSI, NULL); + gpio_request(GPIO_FN_SP1_MISO, NULL); + gpio_request(GPIO_FN_SP1_SCK, NULL); + gpio_request(GPIO_FN_SP1_SCK_FB, NULL); + gpio_request(GPIO_FN_SP1_SS0, NULL); + gpio_request(GPIO_FN_SP1_SS1, NULL); + + /* SDHI (PTI) */ + gpio_request(GPIO_FN_SD_WP, NULL); + gpio_request(GPIO_FN_SD_CD, NULL); + gpio_request(GPIO_FN_SD_CLK, NULL); + gpio_request(GPIO_FN_SD_CMD, NULL); + gpio_request(GPIO_FN_SD_D3, NULL); + gpio_request(GPIO_FN_SD_D2, NULL); + gpio_request(GPIO_FN_SD_D1, NULL); + gpio_request(GPIO_FN_SD_D0, NULL); + + /* SCIF3/4 (PTJ, PTW) */ + gpio_request(GPIO_FN_RTS3, NULL); + gpio_request(GPIO_FN_CTS3, NULL); + gpio_request(GPIO_FN_TXD3, NULL); + gpio_request(GPIO_FN_RXD3, NULL); + gpio_request(GPIO_FN_RTS4, NULL); + gpio_request(GPIO_FN_RXD4, NULL); + gpio_request(GPIO_FN_TXD4, NULL); + gpio_request(GPIO_FN_CTS4, NULL); + + /* SERMUX (PTK, PTL, PTO, PTV) */ + gpio_request(GPIO_FN_COM2_TXD, NULL); + gpio_request(GPIO_FN_COM2_RXD, NULL); + gpio_request(GPIO_FN_COM2_RTS, NULL); + gpio_request(GPIO_FN_COM2_CTS, NULL); + gpio_request(GPIO_FN_COM2_DTR, NULL); + gpio_request(GPIO_FN_COM2_DSR, NULL); + gpio_request(GPIO_FN_COM2_DCD, NULL); + gpio_request(GPIO_FN_COM2_RI, NULL); + gpio_request(GPIO_FN_RAC_RXD, NULL); + gpio_request(GPIO_FN_RAC_RTS, NULL); + gpio_request(GPIO_FN_RAC_CTS, NULL); + gpio_request(GPIO_FN_RAC_DTR, NULL); + gpio_request(GPIO_FN_RAC_DSR, NULL); + gpio_request(GPIO_FN_RAC_DCD, NULL); + gpio_request(GPIO_FN_RAC_TXD, NULL); + gpio_request(GPIO_FN_COM1_TXD, NULL); + gpio_request(GPIO_FN_COM1_RXD, NULL); + gpio_request(GPIO_FN_COM1_RTS, NULL); + gpio_request(GPIO_FN_COM1_CTS, NULL); + + writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */ + + /* IIC (PTM, PTR, PTS) */ + gpio_request(GPIO_FN_SDA7, NULL); + gpio_request(GPIO_FN_SCL7, NULL); + gpio_request(GPIO_FN_SDA6, NULL); + gpio_request(GPIO_FN_SCL6, NULL); + gpio_request(GPIO_FN_SDA5, NULL); + gpio_request(GPIO_FN_SCL5, NULL); + gpio_request(GPIO_FN_SDA4, NULL); + gpio_request(GPIO_FN_SCL4, NULL); + gpio_request(GPIO_FN_SDA3, NULL); + gpio_request(GPIO_FN_SCL3, NULL); + gpio_request(GPIO_FN_SDA2, NULL); + gpio_request(GPIO_FN_SCL2, NULL); + gpio_request(GPIO_FN_SDA1, NULL); + gpio_request(GPIO_FN_SCL1, NULL); + gpio_request(GPIO_FN_SDA0, NULL); + gpio_request(GPIO_FN_SCL0, NULL); + + /* USB (PTN) */ + gpio_request(GPIO_FN_VBUS_EN, NULL); + gpio_request(GPIO_FN_VBUS_OC, NULL); + + /* SGPIO1/0 (PTN, PTO) */ + gpio_request(GPIO_FN_SGPIO1_CLK, NULL); + gpio_request(GPIO_FN_SGPIO1_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO1_DI, NULL); + gpio_request(GPIO_FN_SGPIO1_DO, NULL); + gpio_request(GPIO_FN_SGPIO0_CLK, NULL); + gpio_request(GPIO_FN_SGPIO0_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO0_DI, NULL); + gpio_request(GPIO_FN_SGPIO0_DO, NULL); + + /* WDT (PTN) */ + gpio_request(GPIO_FN_SUB_CLKIN, NULL); + + /* System (PTT) */ + gpio_request(GPIO_FN_STATUS1, NULL); + gpio_request(GPIO_FN_STATUS0, NULL); + + /* PWMX (PTT) */ + gpio_request(GPIO_FN_PWMX1, NULL); + gpio_request(GPIO_FN_PWMX0, NULL); + + /* R-SPI (PTV) */ + gpio_request(GPIO_FN_R_SPI_MOSI, NULL); + gpio_request(GPIO_FN_R_SPI_MISO, NULL); + gpio_request(GPIO_FN_R_SPI_RSPCK, NULL); + gpio_request(GPIO_FN_R_SPI_SSL0, NULL); + gpio_request(GPIO_FN_R_SPI_SSL1, NULL); + + /* EVC (PTV, PTW) */ + gpio_request(GPIO_FN_EVENT7, NULL); + gpio_request(GPIO_FN_EVENT6, NULL); + gpio_request(GPIO_FN_EVENT5, NULL); + gpio_request(GPIO_FN_EVENT4, NULL); + gpio_request(GPIO_FN_EVENT3, NULL); + gpio_request(GPIO_FN_EVENT2, NULL); + gpio_request(GPIO_FN_EVENT1, NULL); + gpio_request(GPIO_FN_EVENT0, NULL); + + /* LED for heartbeat */ + gpio_request(GPIO_PTU3, NULL); + gpio_direction_output(GPIO_PTU3, 1); + gpio_request(GPIO_PTU2, NULL); + gpio_direction_output(GPIO_PTU2, 1); + gpio_request(GPIO_PTU1, NULL); + gpio_direction_output(GPIO_PTU1, 1); + gpio_request(GPIO_PTU0, NULL); + gpio_direction_output(GPIO_PTU0, 1); + + /* control for MDIO of Gigabit Ethernet */ + gpio_request(GPIO_PTT4, NULL); + gpio_direction_output(GPIO_PTT4, 1); + + /* control for eMMC */ + gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */ + gpio_direction_output(GPIO_PTT7, 0); + gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */ + gpio_direction_output(GPIO_PTT6, 0); + gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */ + gpio_direction_output(GPIO_PTT5, 1); + + /* register SPI device information */ + spi_register_board_info(spi_board_info, + ARRAY_SIZE(spi_board_info)); + + /* General platform */ + return platform_add_devices(sh7757lcr_devices, + ARRAY_SIZE(sh7757lcr_devices)); +} +arch_initcall(sh7757lcr_devices_setup); + +/* Initialize IRQ setting */ +void __init init_sh7757lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +/* Initialize the board */ +static void __init sh7757lcr_setup(char **cmdline_p) +{ + printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n"); +} + +static int sh7757lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S3 (Low active). + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN0; /* Clock Mode: 1 */ + + return value; +} + +/* The Machine Vector */ +static struct sh_machine_vector mv_sh7757lcr __initmv = { + .mv_name = "SH7757LCR", + .mv_setup = sh7757lcr_setup, + .mv_init_irq = init_sh7757lcr_IRQ, + .mv_mode_pins = sh7757lcr_mode_pins, +}; + diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c new file mode 100644 index 00000000000..2c4771ee84c --- /dev/null +++ b/arch/sh/boards/board-sh7785lcr.c @@ -0,0 +1,378 @@ +/* + * Renesas Technology Corp. R0P7785LC0011RL Support. + * + * Copyright (C) 2008 Yoshihiro Shimoda + * Copyright (C) 2009 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/sm501.h> +#include <linux/sm501-regs.h> +#include <linux/fb.h> +#include <linux/mtd/physmap.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <linux/i2c-pca-platform.h> +#include <linux/i2c-algo-pca.h> +#include <linux/usb/r8a66597.h> +#include <linux/sh_intc.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/errno.h> +#include <mach/sh7785lcr.h> +#include <cpu/sh7785.h> +#include <asm/heartbeat.h> +#include <asm/clock.h> +#include <asm/bl_bit.h> + +/* + * NOTE: This board has 2 physical memory maps. + * Please look at include/asm-sh/sh7785lcr.h or hardware manual. + */ +static struct resource heartbeat_resource = { + .start = PLD_LEDCR, + .end = PLD_LEDCR, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 4, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = NOR_FLASH_ADDR, + .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct r8a66597_platdata r8a66597_data = { + .xtal = R8A66597_PLATDATA_XTAL_12MHZ, + .vif = 1, +}; + +static struct resource r8a66597_usb_host_resources[] = { + [0] = { + .start = R8A66597_ADDR, + .end = R8A66597_ADDR + R8A66597_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x240), + .end = evt2irq(0x240), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device r8a66597_usb_host_device = { + .name = "r8a66597_hcd", + .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, + }, + .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), + .resource = r8a66597_usb_host_resources, +}; + +static struct resource sm501_resources[] = { + [0] = { + .start = SM107_MEM_ADDR, + .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SM107_REG_ADDR, + .end = SM107_REG_ADDR + SM107_REG_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = evt2irq(0x340), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fb_videomode sm501_default_mode_crt = { + .pixclock = 35714, /* 28MHz */ + .xres = 640, + .yres = 480, + .left_margin = 105, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +}; + +static struct fb_videomode sm501_default_mode_pnl = { + .pixclock = 40000, /* 25MHz */ + .xres = 640, + .yres = 480, + .left_margin = 2, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = 0, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_pnl, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT | + SM501FB_FLAG_PANEL_NO_VBIASEN, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_crt, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT, +}; + +static struct sm501_platdata_fb sm501_fb_pdata = { + .fb_route = SM501_FB_OWN, + .fb_crt = &sm501_pdata_fbsub_crt, + .fb_pnl = &sm501_pdata_fbsub_pnl, +}; + +static struct sm501_initdata sm501_initdata = { + .gpio_high = { + .set = 0x00001fe0, + .mask = 0x0, + }, + .devices = 0, + .mclk = 84 * 1000000, + .m1xclk = 112 * 1000000, +}; + +static struct sm501_platdata sm501_platform_data = { + .init = &sm501_initdata, + .fb = &sm501_fb_pdata, +}; + +static struct platform_device sm501_device = { + .name = "sm501", + .id = -1, + .dev = { + .platform_data = &sm501_platform_data, + }, + .num_resources = ARRAY_SIZE(sm501_resources), + .resource = sm501_resources, +}; + +static struct resource i2c_proto_resources[] = { + [0] = { + .start = PCA9564_PROTO_32BIT_ADDR, + .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = evt2irq(0x380), + .end = evt2irq(0x380), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource i2c_resources[] = { + [0] = { + .start = PCA9564_ADDR, + .end = PCA9564_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = evt2irq(0x380), + .end = evt2irq(0x380), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct i2c_pca9564_pf_platform_data i2c_platform_data = { + .gpio = 0, + .i2c_clock_speed = I2C_PCA_CON_330kHz, + .timeout = HZ, +}; + +static struct platform_device i2c_device = { + .name = "i2c-pca-platform", + .id = -1, + .dev = { + .platform_data = &i2c_platform_data, + }, + .num_resources = ARRAY_SIZE(i2c_resources), + .resource = i2c_resources, +}; + +static struct platform_device *sh7785lcr_devices[] __initdata = { + &heartbeat_device, + &nor_flash_device, + &r8a66597_usb_host_device, + &sm501_device, + &i2c_device, +}; + +static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = { + { + I2C_BOARD_INFO("r2025sd", 0x32), + }, +}; + +static int __init sh7785lcr_devices_setup(void) +{ + i2c_register_board_info(0, sh7785lcr_i2c_devices, + ARRAY_SIZE(sh7785lcr_i2c_devices)); + + if (mach_is_sh7785lcr_pt()) { + i2c_device.resource = i2c_proto_resources; + i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources); + } + + return platform_add_devices(sh7785lcr_devices, + ARRAY_SIZE(sh7785lcr_devices)); +} +device_initcall(sh7785lcr_devices_setup); + +/* Initialize IRQ setting */ +void __init init_sh7785lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +static int sh7785lcr_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333333); + clk_put(clk); + + return ret; +} + +static void sh7785lcr_power_off(void) +{ + unsigned char *p; + + p = ioremap(PLD_POFCR, PLD_POFCR + 1); + if (!p) { + printk(KERN_ERR "%s: ioremap error.\n", __func__); + return; + } + *p = 0x01; + iounmap(p); + set_bl_bit(); + while (1) + cpu_relax(); +} + +/* Initialize the board */ +static void __init sh7785lcr_setup(char **cmdline_p) +{ + void __iomem *sm501_reg; + + printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n"); + + pm_power_off = sh7785lcr_power_off; + + /* sm501 DRAM configuration */ + sm501_reg = ioremap_nocache(SM107_REG_ADDR, SM501_DRAM_CONTROL); + if (!sm501_reg) { + printk(KERN_ERR "%s: ioremap error.\n", __func__); + return; + } + + writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL); + iounmap(sm501_reg); +} + +/* Return the board specific boot mode pin configuration */ +static int sh7785lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S1 and S2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN4; /* Clock Mode 16 */ + value |= MODE_PIN5; /* 32-bit Area0 bus width */ + value |= MODE_PIN6; /* 32-bit Area0 bus width */ + value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */ + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Master Mode */ + value |= MODE_PIN14; /* No PLL step-up */ + + return value; +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_sh7785lcr __initmv = { + .mv_name = "SH7785LCR", + .mv_setup = sh7785lcr_setup, + .mv_clk_init = sh7785lcr_clk_init, + .mv_init_irq = init_sh7785lcr_IRQ, + .mv_mode_pins = sh7785lcr_mode_pins, +}; + diff --git a/arch/sh/boards/shmin/setup.c b/arch/sh/boards/board-shmin.c index 16e5dae8ecf..325bed53b87 100644 --- a/arch/sh/boards/shmin/setup.c +++ b/arch/sh/boards/board-shmin.c @@ -8,7 +8,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <asm/machvec.h> -#include <asm/shmin.h> +#include <mach/shmin.h> #include <asm/clock.h> #include <asm/io.h> @@ -17,26 +17,18 @@ static void __init init_shmin_irq(void) { - ctrl_outw(0x2a00, PFC_PHCR); // IRQ0-3=IRQ - ctrl_outw(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active. + __raw_writew(0x2a00, PFC_PHCR); // IRQ0-3=IRQ + __raw_writew(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active. plat_irq_setup_pins(IRQ_MODE_IRQ); } -static void __iomem *shmin_ioport_map(unsigned long port, unsigned int size) +static void __init shmin_setup(char **cmdline_p) { - static int dummy; - - if ((port & ~0x1f) == SHMIN_NE_BASE) - return (void __iomem *)(SHMIN_IO_BASE + port); - - dummy = 0; - - return &dummy; - + __set_io_port_base(SHMIN_IO_BASE); } static struct sh_machine_vector mv_shmin __initmv = { .mv_name = "SHMIN", + .mv_setup = shmin_setup, .mv_init_irq = init_shmin_irq, - .mv_ioport_map = shmin_ioport_map, }; diff --git a/arch/sh/boards/titan/setup.c b/arch/sh/boards/board-titan.c index 5de3b2ad71a..94c36c7bc0b 100644 --- a/arch/sh/boards/titan/setup.c +++ b/arch/sh/boards/board-titan.c @@ -9,7 +9,7 @@ */ #include <linux/init.h> #include <linux/irq.h> -#include <asm/titan.h> +#include <mach/titan.h> #include <asm/io.h> static void __init init_titan_irq(void) @@ -19,26 +19,6 @@ static void __init init_titan_irq(void) } static struct sh_machine_vector mv_titan __initmv = { - .mv_name = "Titan", - - .mv_inb = titan_inb, - .mv_inw = titan_inw, - .mv_inl = titan_inl, - .mv_outb = titan_outb, - .mv_outw = titan_outw, - .mv_outl = titan_outl, - - .mv_inb_p = titan_inb_p, - .mv_inw_p = titan_inw, - .mv_inl_p = titan_inl, - .mv_outb_p = titan_outb_p, - .mv_outw_p = titan_outw, - .mv_outl_p = titan_outl, - - .mv_insl = titan_insl, - .mv_outsl = titan_outsl, - - .mv_ioport_map = titan_ioport_map, - - .mv_init_irq = init_titan_irq, + .mv_name = "Titan", + .mv_init_irq = init_titan_irq, }; diff --git a/arch/sh/boards/board-urquell.c b/arch/sh/boards/board-urquell.c new file mode 100644 index 00000000000..b52abcc5259 --- /dev/null +++ b/arch/sh/boards/board-urquell.c @@ -0,0 +1,221 @@ +/* + * Renesas Technology Corp. SH7786 Urquell Support. + * + * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> + * Copyright (C) 2009, 2010 Paul Mundt + * + * Based on board-sh7785lcr.c + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/fb.h> +#include <linux/smc91x.h> +#include <linux/mtd/physmap.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/sh_intc.h> +#include <mach/urquell.h> +#include <cpu/sh7786.h> +#include <asm/heartbeat.h> +#include <asm/sizes.h> +#include <asm/smp-ops.h> + +/* + * bit 1234 5678 + *---------------------------- + * SW1 0101 0010 -> Pck 33MHz version + * (1101 0010) Pck 66MHz version + * SW2 0x1x xxxx -> little endian + * 29bit mode + * SW47 0001 1000 -> CS0 : on-board flash + * CS1 : SRAM, registers, LAN, PCMCIA + * 38400 bps for SCIF1 + * + * Address + * 0x00000000 - 0x04000000 (CS0) Nor Flash + * 0x04000000 - 0x04200000 (CS1) SRAM + * 0x05000000 - 0x05800000 (CS1) on board register + * 0x05800000 - 0x06000000 (CS1) LAN91C111 + * 0x06000000 - 0x06400000 (CS1) PCMCIA + * 0x08000000 - 0x10000000 (CS2-CS3) DDR3 + * 0x10000000 - 0x14000000 (CS4) PCIe + * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM + * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM + * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash + * 0x1C000000 - (CS7) SH7786 Control register + */ + +/* HeartBeat */ +static struct resource heartbeat_resource = { + .start = BOARDREG(SLEDR), + .end = BOARDREG(SLEDR), + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* LAN91C111 */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, +}; + +static struct resource smc91x_eth_resources[] = { + [0] = { + .name = "SMC91C111" , + .start = 0x05800300, + .end = 0x0580030f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x360), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_eth_device = { + .name = "smc91x", + .num_resources = ARRAY_SIZE(smc91x_eth_resources), + .resource = smc91x_eth_resources, + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* Nor Flash */ +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = NOR_FLASH_ADDR, + .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct platform_device *urquell_devices[] __initdata = { + &heartbeat_device, + &smc91x_eth_device, + &nor_flash_device, +}; + +static int __init urquell_devices_setup(void) +{ + /* USB */ + gpio_request(GPIO_FN_USB_OVC0, NULL); + gpio_request(GPIO_FN_USB_PENC0, NULL); + + /* enable LAN */ + __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001, + UBOARDREG(IRL2MSKR)); + + return platform_add_devices(urquell_devices, + ARRAY_SIZE(urquell_devices)); +} +device_initcall(urquell_devices_setup); + +static void urquell_power_off(void) +{ + __raw_writew(0xa5a5, UBOARDREG(SRSTR)); +} + +static void __init urquell_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK); +} + +static int urquell_mode_pins(void) +{ + return __raw_readw(UBOARDREG(MDSWMR)); +} + +static int urquell_clk_init(void) +{ + struct clk *clk; + int ret; + + /* + * Only handle the EXTAL case, anyone interfacing a crystal + * resonator will need to provide their own input clock. + */ + if (test_mode_pin(MODE_PIN9)) + return -EINVAL; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333333); + clk_put(clk); + + return ret; +} + +/* Initialize the board */ +static void __init urquell_setup(char **cmdline_p) +{ + printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n"); + + pm_power_off = urquell_power_off; + + register_smp_ops(&shx3_smp_ops); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_urquell __initmv = { + .mv_name = "Urquell", + .mv_setup = urquell_setup, + .mv_init_irq = urquell_init_irq, + .mv_mode_pins = urquell_mode_pins, + .mv_clk_init = urquell_clk_init, +}; diff --git a/arch/sh/boards/cayman/led.c b/arch/sh/boards/cayman/led.c deleted file mode 100644 index a808eac4ecd..00000000000 --- a/arch/sh/boards/cayman/led.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * arch/sh/boards/cayman/led.c - * - * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com> - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * Flash the LEDs - */ -#include <asm/io.h> - -/* -** It is supposed these functions to be used for a low level -** debugging (via Cayman LEDs), hence to be available as soon -** as possible. -** Unfortunately Cayman LEDs relies on Cayman EPLD to be mapped -** (this happen when IRQ are initialized... quite late). -** These triky dependencies should be removed. Temporary, it -** may be enough to NOP until EPLD is mapped. -*/ - -extern unsigned long epld_virt; - -#define LED_ADDR (epld_virt + 0x008) -#define HDSP2534_ADDR (epld_virt + 0x100) - -void mach_led(int position, int value) -{ - if (!epld_virt) - return; - - if (value) - ctrl_outl(0, LED_ADDR); - else - ctrl_outl(1, LED_ADDR); - -} - -void mach_alphanum(int position, unsigned char value) -{ - if (!epld_virt) - return; - - ctrl_outb(value, HDSP2534_ADDR + 0xe0 + (position << 2)); -} - -void mach_alphanum_brightness(int setting) -{ - ctrl_outb(setting & 7, HDSP2534_ADDR + 0xc0); -} diff --git a/arch/sh/boards/dreamcast/irq.c b/arch/sh/boards/dreamcast/irq.c deleted file mode 100644 index 9d0673a9092..00000000000 --- a/arch/sh/boards/dreamcast/irq.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * arch/sh/boards/dreamcast/irq.c - * - * Holly IRQ support for the Sega Dreamcast. - * - * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> - * - * This file is part of the LinuxDC project (www.linuxdc.org) - * Released under the terms of the GNU GPL v2.0 - */ - -#include <linux/irq.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/dreamcast/sysasic.h> - -/* Dreamcast System ASIC Hardware Events - - - The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving - hardware events from system peripherals and triggering an SH7750 IRQ. - Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are - set in the Event Mask Registers (EMRs). When a hardware event is - triggered, it's corresponding bit in the Event Status Registers (ESRs) - is set, and that bit should be rewritten to the ESR to acknowledge that - event. - - There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event - types can be found in include/asm-sh/dreamcast/sysasic.h. There are three - groups of EMRs that parallel the ESRs. Each EMR group corresponds to an - IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928 - triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9. - - In the kernel, these events are mapped to virtual IRQs so that drivers can - respond to them as they would a normal interrupt. In order to keep this - mapping simple, the events are mapped as: - - 6900/6910 - Events 0-31, IRQ 13 - 6904/6924 - Events 32-63, IRQ 11 - 6908/6938 - Events 64-95, IRQ 9 - -*/ - -#define ESR_BASE 0x005f6900 /* Base event status register */ -#define EMR_BASE 0x005f6910 /* Base event mask register */ - -/* Helps us determine the EMR group that this event belongs to: 0 = 0x6910, - 1 = 0x6920, 2 = 0x6930; also determine the event offset */ -#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) - -/* Return the hardware event's bit positon within the EMR/ESR */ -#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) - -/* For each of these *_irq routines, the IRQ passed in is the virtual IRQ - (logically mapped to the corresponding bit for the hardware event). */ - -/* Disable the hardware event by masking its bit in its EMR */ -static inline void disable_systemasic_irq(unsigned int irq) -{ - __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); - __u32 mask; - - mask = inl(emr); - mask &= ~(1 << EVENT_BIT(irq)); - outl(mask, emr); -} - -/* Enable the hardware event by setting its bit in its EMR */ -static inline void enable_systemasic_irq(unsigned int irq) -{ - __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); - __u32 mask; - - mask = inl(emr); - mask |= (1 << EVENT_BIT(irq)); - outl(mask, emr); -} - -/* Acknowledge a hardware event by writing its bit back to its ESR */ -static void ack_systemasic_irq(unsigned int irq) -{ - __u32 esr = ESR_BASE + (LEVEL(irq) << 2); - disable_systemasic_irq(irq); - outl((1 << EVENT_BIT(irq)), esr); -} - -/* After a IRQ has been ack'd and responded to, it needs to be renabled */ -static void end_systemasic_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_systemasic_irq(irq); -} - -static unsigned int startup_systemasic_irq(unsigned int irq) -{ - enable_systemasic_irq(irq); - - return 0; -} - -static void shutdown_systemasic_irq(unsigned int irq) -{ - disable_systemasic_irq(irq); -} - -struct hw_interrupt_type systemasic_int = { - .typename = "System ASIC", - .startup = startup_systemasic_irq, - .shutdown = shutdown_systemasic_irq, - .enable = enable_systemasic_irq, - .disable = disable_systemasic_irq, - .ack = ack_systemasic_irq, - .end = end_systemasic_irq, -}; - -/* - * Map the hardware event indicated by the processor IRQ to a virtual IRQ. - */ -int systemasic_irq_demux(int irq) -{ - __u32 emr, esr, status, level; - __u32 j, bit; - - switch (irq) { - case 13: - level = 0; - break; - case 11: - level = 1; - break; - case 9: - level = 2; - break; - default: - return irq; - } - emr = EMR_BASE + (level << 4) + (level << 2); - esr = ESR_BASE + (level << 2); - - /* Mask the ESR to filter any spurious, unwanted interrupts */ - status = inl(esr); - status &= inl(emr); - - /* Now scan and find the first set bit as the event to map */ - for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { - if (status & bit) { - irq = HW_EVENT_IRQ_BASE + j + (level << 5); - return irq; - } - } - - /* Not reached */ - return irq; -} diff --git a/arch/sh/boards/hp6xx/pm.c b/arch/sh/boards/hp6xx/pm.c deleted file mode 100644 index d22f6eac9cc..00000000000 --- a/arch/sh/boards/hp6xx/pm.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * hp6x0 Power Management Routines - * - * Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License. - */ -#include <linux/init.h> -#include <linux/suspend.h> -#include <linux/errno.h> -#include <linux/time.h> -#include <asm/io.h> -#include <asm/hd64461.h> -#include <asm/hp6xx.h> -#include <asm/cpu/dac.h> -#include <asm/pm.h> - -#define STBCR 0xffffff82 -#define STBCR2 0xffffff88 - -static int hp6x0_pm_enter(suspend_state_t state) -{ - u8 stbcr, stbcr2; -#ifdef CONFIG_HD64461_ENABLER - u8 scr; - u16 hd64461_stbcr; -#endif - -#ifdef CONFIG_HD64461_ENABLER - outb(0, HD64461_PCC1CSCIER); - - scr = inb(HD64461_PCC1SCR); - scr |= HD64461_PCCSCR_VCC1; - outb(scr, HD64461_PCC1SCR); - - hd64461_stbcr = inw(HD64461_STBCR); - hd64461_stbcr |= HD64461_STBCR_SPC1ST; - outw(hd64461_stbcr, HD64461_STBCR); -#endif - - ctrl_outb(0x1f, DACR); - - stbcr = ctrl_inb(STBCR); - ctrl_outb(0x01, STBCR); - - stbcr2 = ctrl_inb(STBCR2); - ctrl_outb(0x7f , STBCR2); - - outw(0xf07f, HD64461_SCPUCR); - - pm_enter(); - - outw(0, HD64461_SCPUCR); - ctrl_outb(stbcr, STBCR); - ctrl_outb(stbcr2, STBCR2); - -#ifdef CONFIG_HD64461_ENABLER - hd64461_stbcr = inw(HD64461_STBCR); - hd64461_stbcr &= ~HD64461_STBCR_SPC1ST; - outw(hd64461_stbcr, HD64461_STBCR); - - outb(0x4c, HD64461_PCC1CSCIER); - outb(0x00, HD64461_PCC1CSCR); -#endif - - return 0; -} - -static struct platform_suspend_ops hp6x0_pm_ops = { - .enter = hp6x0_pm_enter, - .valid = suspend_valid_only_mem, -}; - -static int __init hp6x0_pm_init(void) -{ - suspend_set_ops(&hp6x0_pm_ops); - return 0; -} - -late_initcall(hp6x0_pm_init); diff --git a/arch/sh/boards/landisk/irq.c b/arch/sh/boards/landisk/irq.c deleted file mode 100644 index 258649491d4..00000000000 --- a/arch/sh/boards/landisk/irq.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * arch/sh/boards/landisk/irq.c - * - * I-O DATA Device, Inc. LANDISK Support - * - * Copyright (C) 2005-2007 kogiidena - * - * Copyright (C) 2001 Ian da Silva, Jeremy Siegel - * Based largely on io_se.c. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <asm/landisk/iodata_landisk.h> - -static void disable_landisk_irq(unsigned int irq) -{ - unsigned char mask = 0xff ^ (0x01 << (irq - 5)); - - ctrl_outb(ctrl_inb(PA_IMASK) & mask, PA_IMASK); -} - -static void enable_landisk_irq(unsigned int irq) -{ - unsigned char value = (0x01 << (irq - 5)); - - ctrl_outb(ctrl_inb(PA_IMASK) | value, PA_IMASK); -} - -static struct irq_chip landisk_irq_chip __read_mostly = { - .name = "LANDISK", - .mask = disable_landisk_irq, - .unmask = enable_landisk_irq, - .mask_ack = disable_landisk_irq, -}; - -/* - * Initialize IRQ setting - */ -void __init init_landisk_IRQ(void) -{ - int i; - - for (i = 5; i < 14; i++) { - disable_irq_nosync(i); - set_irq_chip_and_handler_name(i, &landisk_irq_chip, - handle_level_irq, "level"); - enable_landisk_irq(i); - } - ctrl_outb(0x00, PA_PWRINT_CLR); -} diff --git a/arch/sh/boards/mach-ap325rxa/Makefile b/arch/sh/boards/mach-ap325rxa/Makefile new file mode 100644 index 00000000000..4cf1774d261 --- /dev/null +++ b/arch/sh/boards/mach-ap325rxa/Makefile @@ -0,0 +1,2 @@ +obj-y := setup.o sdram.o + diff --git a/arch/sh/boards/mach-ap325rxa/sdram.S b/arch/sh/boards/mach-ap325rxa/sdram.S new file mode 100644 index 00000000000..db24fbed4fc --- /dev/null +++ b/arch/sh/boards/mach-ap325rxa/sdram.S @@ -0,0 +1,69 @@ +/* + * AP325RXA sdram self/auto-refresh setup code + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/sys.h> +#include <linux/errno.h> +#include <linux/linkage.h> +#include <asm/asm-offsets.h> +#include <asm/suspend.h> +#include <asm/romimage-macros.h> + +/* code to enter and leave self-refresh. must be self-contained. + * this code will be copied to on-chip memory and executed from there. + */ + .balign 4 +ENTRY(ap325rxa_sdram_enter_start) + + /* SBSC: disable power down and put in self-refresh mode */ + mov.l 1f, r4 + mov.l 2f, r1 + mov.l @r4, r2 + or r1, r2 + mov.l 3f, r3 + and r3, r2 + mov.l r2, @r4 + + rts + nop + + .balign 4 +1: .long 0xfe400008 /* SDCR0 */ +2: .long 0x00000400 +3: .long 0xffff7fff +ENTRY(ap325rxa_sdram_enter_end) + + .balign 4 +ENTRY(ap325rxa_sdram_leave_start) + + /* SBSC: set auto-refresh mode */ + mov.l 1f, r4 + mov.l @r4, r0 + mov.l 4f, r1 + and r1, r0 + mov.l r0, @r4 + mov.l 6f, r4 + mov.l 8f, r0 + mov.l @r4, r1 + mov #-1, r4 + add r4, r1 + or r1, r0 + mov.l 7f, r1 + mov.l r0, @r1 + + rts + nop + + .balign 4 +1: .long 0xfe400008 /* SDCR0 */ +4: .long 0xfffffbff +6: .long 0xfe40001c /* RTCOR */ +7: .long 0xfe400018 /* RTCNT */ +8: .long 0xa55a0000 +ENTRY(ap325rxa_sdram_leave_end) diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c new file mode 100644 index 00000000000..5620e33c18a --- /dev/null +++ b/arch/sh/boards/mach-ap325rxa/setup.c @@ -0,0 +1,695 @@ +/* + * Renesas - AP-325RXA + * (Compatible with Algo System ., LTD. - AP-320A) + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Author : Yusuke Goda <goda.yuske@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/sh_flctl.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/smsc911x.h> +#include <linux/gpio.h> +#include <linux/videodev2.h> +#include <linux/sh_intc.h> +#include <media/ov772x.h> +#include <media/soc_camera.h> +#include <media/soc_camera_platform.h> +#include <media/sh_mobile_ceu.h> +#include <video/sh_mobile_lcdc.h> +#include <asm/io.h> +#include <asm/clock.h> +#include <asm/suspend.h> +#include <cpu/sh7723.h> + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT, +}; + +static struct resource smsc9118_resources[] = { + [0] = { + .start = 0xb6080000, + .end = 0xb60fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x660), + .end = evt2irq(0x660), + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smsc9118_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc9118_resources), + .resource = smsc9118_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +/* + * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF). + * If this area erased, this board can not boot. + */ +static struct mtd_partition ap325rxa_nor_flash_partitions[] = { + { + .name = "uboot", + .offset = 0, + .size = (1 * 1024 * 1024), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = (2 * 1024 * 1024), + }, { + .name = "free-area0", + .offset = MTDPART_OFS_APPEND, + .size = ((7 * 1024 * 1024) + (512 * 1024)), + }, { + .name = "CPLD-Data", + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + .size = (1024 * 128 * 2), + }, { + .name = "free-area1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data ap325rxa_nor_flash_data = { + .width = 2, + .parts = ap325rxa_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions), +}; + +static struct resource ap325rxa_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x00ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device ap325rxa_nor_flash_device = { + .name = "physmap-flash", + .resource = ap325rxa_nor_flash_resources, + .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources), + .dev = { + .platform_data = &ap325rxa_nor_flash_data, + }, +}; + +static struct mtd_partition nand_partition_info[] = { + { + .name = "nand_data", + .offset = 0, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct resource nand_flash_resources[] = { + [0] = { + .start = 0xa4530000, + .end = 0xa45300ff, + .flags = IORESOURCE_MEM, + } +}; + +static struct sh_flctl_platform_data nand_flash_data = { + .parts = nand_partition_info, + .nr_parts = ARRAY_SIZE(nand_partition_info), + .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E, + .has_hwecc = 1, +}; + +static struct platform_device nand_flash_device = { + .name = "sh_flctl", + .resource = nand_flash_resources, + .num_resources = ARRAY_SIZE(nand_flash_resources), + .dev = { + .platform_data = &nand_flash_data, + }, +}; + +#define FPGA_LCDREG 0xB4100180 +#define FPGA_BKLREG 0xB4100212 +#define FPGA_LCDREG_VAL 0x0018 +#define PORT_MSELCRB 0xA4050182 +#define PORT_HIZCRC 0xA405015C +#define PORT_DRVCRA 0xA405018A +#define PORT_DRVCRB 0xA405018C + +static int ap320_wvga_set_brightness(int brightness) +{ + if (brightness) { + gpio_set_value(GPIO_PTS3, 0); + __raw_writew(0x100, FPGA_BKLREG); + } else { + __raw_writew(0, FPGA_BKLREG); + gpio_set_value(GPIO_PTS3, 1); + } + + return 0; +} + +static void ap320_wvga_power_on(void) +{ + msleep(100); + + /* ASD AP-320/325 LCD ON */ + __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG); +} + +static void ap320_wvga_power_off(void) +{ + /* ASD AP-320/325 LCD OFF */ + __raw_writew(0, FPGA_LCDREG); +} + +static const struct fb_videomode ap325rxa_lcdc_modes[] = { + { + .name = "LB070WV1", + .xres = 800, + .yres = 480, + .left_margin = 32, + .right_margin = 160, + .hsync_len = 8, + .upper_margin = 63, + .lower_margin = 80, + .vsync_len = 1, + .sync = 0, /* hsync and vsync are active low */ + }, +}; + +static struct sh_mobile_lcdc_info lcdc_info = { + .clock_source = LCDC_CLK_EXTERNAL, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .fourcc = V4L2_PIX_FMT_RGB565, + .interface_type = RGB18, + .clock_divider = 1, + .lcd_modes = ap325rxa_lcdc_modes, + .num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes), + .panel_cfg = { + .width = 152, /* 7.0 inch */ + .height = 91, + .display_on = ap320_wvga_power_on, + .display_off = ap320_wvga_power_off, + }, + .bl_info = { + .name = "sh_mobile_lcdc_bl", + .max_brightness = 1, + .set_brightness = ap320_wvga_set_brightness, + }, + } +}; + +static struct resource lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, /* P4-only space */ + .end = 0xfe942fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x580), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(lcdc_resources), + .resource = lcdc_resources, + .dev = { + .platform_data = &lcdc_info, + }, +}; + +static void camera_power(int val) +{ + gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */ + mdelay(10); +} + +#ifdef CONFIG_I2C +/* support for the old ncm03j camera */ +static unsigned char camera_ncm03j_magic[] = +{ + 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, + 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36, + 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F, + 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55, + 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12, + 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0, + 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F, + 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A, + 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A, + 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A, + 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56, + 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37, + 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A, + 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56, + 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC, + 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, +}; + +static int camera_probe(void) +{ + struct i2c_adapter *a = i2c_get_adapter(0); + struct i2c_msg msg; + int ret; + + if (!a) + return -ENODEV; + + camera_power(1); + msg.addr = 0x6e; + msg.buf = camera_ncm03j_magic; + msg.len = 2; + msg.flags = 0; + ret = i2c_transfer(a, &msg, 1); + camera_power(0); + + return ret; +} + +static int camera_set_capture(struct soc_camera_platform_info *info, + int enable) +{ + struct i2c_adapter *a = i2c_get_adapter(0); + struct i2c_msg msg; + int ret = 0; + int i; + + camera_power(0); + if (!enable) + return 0; /* no disable for now */ + + camera_power(1); + for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) { + u_int8_t buf[8]; + + msg.addr = 0x6e; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + + buf[0] = camera_ncm03j_magic[i]; + buf[1] = camera_ncm03j_magic[i + 1]; + + ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); + } + + return ret; +} + +static int ap325rxa_camera_add(struct soc_camera_device *icd); +static void ap325rxa_camera_del(struct soc_camera_device *icd); + +static struct soc_camera_platform_info camera_info = { + .format_name = "UYVY", + .format_depth = 16, + .format = { + .code = V4L2_MBUS_FMT_UYVY8_2X8, + .colorspace = V4L2_COLORSPACE_SMPTE170M, + .field = V4L2_FIELD_NONE, + .width = 640, + .height = 480, + }, + .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | + V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH | + V4L2_MBUS_DATA_ACTIVE_HIGH, + .mbus_type = V4L2_MBUS_PARALLEL, + .set_capture = camera_set_capture, +}; + +static struct soc_camera_link camera_link = { + .bus_id = 0, + .add_device = ap325rxa_camera_add, + .del_device = ap325rxa_camera_del, + .module_name = "soc_camera_platform", + .priv = &camera_info, +}; + +static struct platform_device *camera_device; + +static void ap325rxa_camera_release(struct device *dev) +{ + soc_camera_platform_release(&camera_device); +} + +static int ap325rxa_camera_add(struct soc_camera_device *icd) +{ + int ret = soc_camera_platform_add(icd, &camera_device, &camera_link, + ap325rxa_camera_release, 0); + if (ret < 0) + return ret; + + ret = camera_probe(); + if (ret < 0) + soc_camera_platform_del(icd, camera_device, &camera_link); + + return ret; +} + +static void ap325rxa_camera_del(struct soc_camera_device *icd) +{ + soc_camera_platform_del(icd, camera_device, &camera_link); +} +#endif /* CONFIG_I2C */ + +static int ov7725_power(struct device *dev, int mode) +{ + camera_power(0); + if (mode) + camera_power(1); + + return 0; +} + +static struct sh_mobile_ceu_info sh_mobile_ceu_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource ceu_resources[] = { + [0] = { + .name = "CEU", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x880), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu_device = { + .name = "sh_mobile_ceu", + .id = 0, /* "ceu0" clock */ + .num_resources = ARRAY_SIZE(ceu_resources), + .resource = ceu_resources, + .dev = { + .platform_data = &sh_mobile_ceu_info, + }, +}; + +/* Fixed 3.3V regulators to be used by SDHI0, SDHI1 */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), +}; + +static struct resource sdhi0_cn3_resources[] = { + [0] = { + .name = "SDHI0", + .start = 0x04ce0000, + .end = 0x04ce00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xe80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mobile_sdhi_info sdhi0_cn3_data = { + .tmio_caps = MMC_CAP_SDIO_IRQ, +}; + +static struct platform_device sdhi0_cn3_device = { + .name = "sh_mobile_sdhi", + .id = 0, /* "sdhi0" clock */ + .num_resources = ARRAY_SIZE(sdhi0_cn3_resources), + .resource = sdhi0_cn3_resources, + .dev = { + .platform_data = &sdhi0_cn3_data, + }, +}; + +static struct resource sdhi1_cn7_resources[] = { + [0] = { + .name = "SDHI1", + .start = 0x04cf0000, + .end = 0x04cf00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x4e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mobile_sdhi_info sdhi1_cn7_data = { + .tmio_caps = MMC_CAP_SDIO_IRQ, +}; + +static struct platform_device sdhi1_cn7_device = { + .name = "sh_mobile_sdhi", + .id = 1, /* "sdhi1" clock */ + .num_resources = ARRAY_SIZE(sdhi1_cn7_resources), + .resource = sdhi1_cn7_resources, + .dev = { + .platform_data = &sdhi1_cn7_data, + }, +}; + +static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, +}; + +static struct i2c_board_info ap325rxa_i2c_camera[] = { + { + I2C_BOARD_INFO("ov772x", 0x21), + }, +}; + +static struct ov772x_camera_info ov7725_info = { + .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP, + .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0), +}; + +static struct soc_camera_link ov7725_link = { + .bus_id = 0, + .power = ov7725_power, + .board_info = &ap325rxa_i2c_camera[0], + .i2c_adapter_id = 0, + .priv = &ov7725_info, +}; + +static struct platform_device ap325rxa_camera[] = { + { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &ov7725_link, + }, + }, { + .name = "soc-camera-pdrv", + .id = 1, + .dev = { + .platform_data = &camera_link, + }, + }, +}; + +static struct platform_device *ap325rxa_devices[] __initdata = { + &smsc9118_device, + &ap325rxa_nor_flash_device, + &lcdc_device, + &ceu_device, + &nand_flash_device, + &sdhi0_cn3_device, + &sdhi1_cn7_device, + &ap325rxa_camera[0], + &ap325rxa_camera[1], +}; + +extern char ap325rxa_sdram_enter_start; +extern char ap325rxa_sdram_enter_end; +extern char ap325rxa_sdram_leave_start; +extern char ap325rxa_sdram_leave_end; + +static int __init ap325rxa_devices_setup(void) +{ + /* register board specific self-refresh code */ + sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, + &ap325rxa_sdram_enter_start, + &ap325rxa_sdram_enter_end, + &ap325rxa_sdram_leave_start, + &ap325rxa_sdram_leave_end); + + regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + /* LD3 and LD4 LEDs */ + gpio_request(GPIO_PTX5, NULL); /* RUN */ + gpio_direction_output(GPIO_PTX5, 1); + gpio_export(GPIO_PTX5, 0); + + gpio_request(GPIO_PTX4, NULL); /* INDICATOR */ + gpio_direction_output(GPIO_PTX4, 0); + gpio_export(GPIO_PTX4, 0); + + /* SW1 input */ + gpio_request(GPIO_PTF7, NULL); /* MODE */ + gpio_direction_input(GPIO_PTF7); + gpio_export(GPIO_PTF7, 0); + + /* LCDC */ + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDLCLK_PTR, NULL); + gpio_request(GPIO_FN_LCDDCK, NULL); + gpio_request(GPIO_FN_LCDVEPWC, NULL); + gpio_request(GPIO_FN_LCDVCPWC, NULL); + gpio_request(GPIO_FN_LCDVSYN, NULL); + gpio_request(GPIO_FN_LCDHSYN, NULL); + gpio_request(GPIO_FN_LCDDISP, NULL); + gpio_request(GPIO_FN_LCDDON, NULL); + + /* LCD backlight */ + gpio_request(GPIO_PTS3, NULL); + gpio_direction_output(GPIO_PTS3, 1); + + /* CEU */ + gpio_request(GPIO_FN_VIO_CLK2, NULL); + gpio_request(GPIO_FN_VIO_VD2, NULL); + gpio_request(GPIO_FN_VIO_HD2, NULL); + gpio_request(GPIO_FN_VIO_FLD, NULL); + gpio_request(GPIO_FN_VIO_CKO, NULL); + gpio_request(GPIO_FN_VIO_D15, NULL); + gpio_request(GPIO_FN_VIO_D14, NULL); + gpio_request(GPIO_FN_VIO_D13, NULL); + gpio_request(GPIO_FN_VIO_D12, NULL); + gpio_request(GPIO_FN_VIO_D11, NULL); + gpio_request(GPIO_FN_VIO_D10, NULL); + gpio_request(GPIO_FN_VIO_D9, NULL); + gpio_request(GPIO_FN_VIO_D8, NULL); + + gpio_request(GPIO_PTZ7, NULL); + gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */ + gpio_request(GPIO_PTZ6, NULL); + gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */ + gpio_request(GPIO_PTZ5, NULL); + gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */ + gpio_request(GPIO_PTZ4, NULL); + gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */ + + __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); + + /* FLCTL */ + gpio_request(GPIO_FN_FCE, NULL); + gpio_request(GPIO_FN_NAF7, NULL); + gpio_request(GPIO_FN_NAF6, NULL); + gpio_request(GPIO_FN_NAF5, NULL); + gpio_request(GPIO_FN_NAF4, NULL); + gpio_request(GPIO_FN_NAF3, NULL); + gpio_request(GPIO_FN_NAF2, NULL); + gpio_request(GPIO_FN_NAF1, NULL); + gpio_request(GPIO_FN_NAF0, NULL); + gpio_request(GPIO_FN_FCDE, NULL); + gpio_request(GPIO_FN_FOE, NULL); + gpio_request(GPIO_FN_FSC, NULL); + gpio_request(GPIO_FN_FWE, NULL); + gpio_request(GPIO_FN_FRB, NULL); + + __raw_writew(0, PORT_HIZCRC); + __raw_writew(0xFFFF, PORT_DRVCRA); + __raw_writew(0xFFFF, PORT_DRVCRB); + + platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); + + /* SDHI0 - CN3 - SD CARD */ + gpio_request(GPIO_FN_SDHI0CD_PTD, NULL); + gpio_request(GPIO_FN_SDHI0WP_PTD, NULL); + gpio_request(GPIO_FN_SDHI0D3_PTD, NULL); + gpio_request(GPIO_FN_SDHI0D2_PTD, NULL); + gpio_request(GPIO_FN_SDHI0D1_PTD, NULL); + gpio_request(GPIO_FN_SDHI0D0_PTD, NULL); + gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL); + gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL); + + /* SDHI1 - CN7 - MICRO SD CARD */ + gpio_request(GPIO_FN_SDHI1CD, NULL); + gpio_request(GPIO_FN_SDHI1D3, NULL); + gpio_request(GPIO_FN_SDHI1D2, NULL); + gpio_request(GPIO_FN_SDHI1D1, NULL); + gpio_request(GPIO_FN_SDHI1D0, NULL); + gpio_request(GPIO_FN_SDHI1CMD, NULL); + gpio_request(GPIO_FN_SDHI1CLK, NULL); + + i2c_register_board_info(0, ap325rxa_i2c_devices, + ARRAY_SIZE(ap325rxa_i2c_devices)); + + return platform_add_devices(ap325rxa_devices, + ARRAY_SIZE(ap325rxa_devices)); +} +arch_initcall(ap325rxa_devices_setup); + +/* Return the board specific boot mode pin configuration */ +static int ap325rxa_mode_pins(void) +{ + /* MD0=0, MD1=0, MD2=0: Clock Mode 0 + * MD3=0: 16-bit Area0 Bus Width + * MD5=1: Little Endian + * TSTMD=1, MD8=1: Test Mode Disabled + */ + return MODE_PIN5 | MODE_PIN8; +} + +static struct sh_machine_vector mv_ap325rxa __initmv = { + .mv_name = "AP-325RXA", + .mv_mode_pins = ap325rxa_mode_pins, +}; diff --git a/arch/sh/boards/cayman/Makefile b/arch/sh/boards/mach-cayman/Makefile index 489a8f86736..00fa3eaecb1 100644 --- a/arch/sh/boards/cayman/Makefile +++ b/arch/sh/boards/mach-cayman/Makefile @@ -1,5 +1,4 @@ # # Makefile for the Hitachi Cayman specific parts of the kernel # -obj-y := setup.o irq.o -obj-$(CONFIG_HEARTBEAT) += led.o +obj-y := setup.o irq.o panic.o diff --git a/arch/sh/boards/cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c index 30ec7bebfaf..724e8b7271f 100644 --- a/arch/sh/boards/cayman/irq.c +++ b/arch/sh/boards/mach-cayman/irq.c @@ -13,7 +13,7 @@ #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/signal.h> -#include <asm/cpu/irq.h> +#include <cpu/irq.h> #include <asm/page.h> /* Setup for the SMSC FDC37C935 / LAN91C100FD */ @@ -46,17 +46,16 @@ static irqreturn_t cayman_interrupt_pci2(int irq, void *dev_id) static struct irqaction cayman_action_smsc = { .name = "Cayman SMSC Mux", .handler = cayman_interrupt_smsc, - .flags = IRQF_DISABLED, }; static struct irqaction cayman_action_pci2 = { .name = "Cayman PCI2 Mux", .handler = cayman_interrupt_pci2, - .flags = IRQF_DISABLED, }; -static void enable_cayman_irq(unsigned int irq) +static void enable_cayman_irq(struct irq_data *data) { + unsigned int irq = data->irq; unsigned long flags; unsigned long mask; unsigned int reg; @@ -66,14 +65,15 @@ static void enable_cayman_irq(unsigned int irq) reg = EPLD_MASK_BASE + ((irq / 8) << 2); bit = 1<<(irq % 8); local_irq_save(flags); - mask = ctrl_inl(reg); + mask = __raw_readl(reg); mask |= bit; - ctrl_outl(mask, reg); + __raw_writel(mask, reg); local_irq_restore(flags); } -void disable_cayman_irq(unsigned int irq) +static void disable_cayman_irq(struct irq_data *data) { + unsigned int irq = data->irq; unsigned long flags; unsigned long mask; unsigned int reg; @@ -83,42 +83,16 @@ void disable_cayman_irq(unsigned int irq) reg = EPLD_MASK_BASE + ((irq / 8) << 2); bit = 1<<(irq % 8); local_irq_save(flags); - mask = ctrl_inl(reg); + mask = __raw_readl(reg); mask &= ~bit; - ctrl_outl(mask, reg); + __raw_writel(mask, reg); local_irq_restore(flags); } -static void ack_cayman_irq(unsigned int irq) -{ - disable_cayman_irq(irq); -} - -static void end_cayman_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_cayman_irq(irq); -} - -static unsigned int startup_cayman_irq(unsigned int irq) -{ - enable_cayman_irq(irq); - return 0; /* never anything pending */ -} - -static void shutdown_cayman_irq(unsigned int irq) -{ - disable_cayman_irq(irq); -} - -struct hw_interrupt_type cayman_irq_type = { - .typename = "Cayman-IRQ", - .startup = startup_cayman_irq, - .shutdown = shutdown_cayman_irq, - .enable = enable_cayman_irq, - .disable = disable_cayman_irq, - .ack = ack_cayman_irq, - .end = end_cayman_irq, +struct irq_chip cayman_irq_type = { + .name = "Cayman-IRQ", + .irq_unmask = enable_cayman_irq, + .irq_mask = disable_cayman_irq, }; int cayman_irq_demux(int evt) @@ -129,8 +103,8 @@ int cayman_irq_demux(int evt) unsigned long status; int i; - status = ctrl_inl(EPLD_STATUS_BASE) & - ctrl_inl(EPLD_MASK_BASE) & 0xff; + status = __raw_readl(EPLD_STATUS_BASE) & + __raw_readl(EPLD_MASK_BASE) & 0xff; if (status == 0) { irq = -1; } else { @@ -146,8 +120,8 @@ int cayman_irq_demux(int evt) unsigned long status; int i; - status = ctrl_inl(EPLD_STATUS_BASE + 3 * sizeof(u32)) & - ctrl_inl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff; + status = __raw_readl(EPLD_STATUS_BASE + 3 * sizeof(u32)) & + __raw_readl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff; if (status == 0) { irq = -1; } else { @@ -162,33 +136,19 @@ int cayman_irq_demux(int evt) return irq; } -#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL) -int cayman_irq_describe(char* p, int irq) -{ - if (irq < NR_INTC_IRQS) { - return intc_irq_describe(p, irq); - } else if (irq < NR_INTC_IRQS + 8) { - return sprintf(p, "(SMSC %d)", irq - NR_INTC_IRQS); - } else if ((irq >= NR_INTC_IRQS + 24) && (irq < NR_INTC_IRQS + 32)) { - return sprintf(p, "(PCI2 %d)", irq - (NR_INTC_IRQS + 24)); - } - - return 0; -} -#endif - void init_cayman_irq(void) { int i; - epld_virt = onchip_remap(EPLD_BASE, 1024, "EPLD"); + epld_virt = (unsigned long)ioremap_nocache(EPLD_BASE, 1024); if (!epld_virt) { printk(KERN_ERR "Cayman IRQ: Unable to remap EPLD\n"); return; } - for (i=0; i<NR_EXT_IRQS; i++) { - irq_desc[START_EXT_IRQS + i].chip = &cayman_irq_type; + for (i = 0; i < NR_EXT_IRQS; i++) { + irq_set_chip_and_handler(START_EXT_IRQS + i, + &cayman_irq_type, handle_level_irq); } /* Setup the SMSC interrupt */ diff --git a/arch/sh/boards/mach-cayman/panic.c b/arch/sh/boards/mach-cayman/panic.c new file mode 100644 index 00000000000..d1e67306d07 --- /dev/null +++ b/arch/sh/boards/mach-cayman/panic.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2003 Richard Curnow, SuperH UK Limited + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <cpu/registers.h> + +/* THIS IS A PHYSICAL ADDRESS */ +#define HDSP2534_ADDR (0x04002100) + +static void poor_mans_delay(void) +{ + int i; + + for (i = 0; i < 2500000; i++) + cpu_relax(); +} + +static void show_value(unsigned long x) +{ + int i; + unsigned nibble; + for (i = 0; i < 8; i++) { + nibble = ((x >> (i * 4)) & 0xf); + + __raw_writeb(nibble + ((nibble > 9) ? 55 : 48), + HDSP2534_ADDR + 0xe0 + ((7 - i) << 2)); + } +} + +void +panic_handler(unsigned long panicPC, unsigned long panicSSR, + unsigned long panicEXPEVT) +{ + while (1) { + /* This piece of code displays the PC on the LED display */ + show_value(panicPC); + poor_mans_delay(); + show_value(panicSSR); + poor_mans_delay(); + show_value(panicEXPEVT); + poor_mans_delay(); + } +} diff --git a/arch/sh/boards/cayman/setup.c b/arch/sh/boards/mach-cayman/setup.c index 8c9fa472d8f..340fd40b381 100644 --- a/arch/sh/boards/cayman/setup.c +++ b/arch/sh/boards/mach-cayman/setup.c @@ -13,7 +13,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> -#include <asm/cpu/irq.h> +#include <cpu/irq.h> /* * Platform Dependent Interrupt Priorities. @@ -102,7 +102,7 @@ static int __init smsc_superio_setup(void) { unsigned char devid, devrev; - smsc_superio_virt = onchip_remap(SMSC_SUPERIO_BASE, 1024, "SMSC SuperIO"); + smsc_superio_virt = (unsigned long)ioremap_nocache(SMSC_SUPERIO_BASE, 1024); if (!smsc_superio_virt) { panic("Unable to remap SMSC SuperIO\n"); } @@ -165,7 +165,7 @@ static int __init smsc_superio_setup(void) return 0; } -__initcall(smsc_superio_setup); +device_initcall(smsc_superio_setup); static void __iomem *cayman_ioport_map(unsigned long port, unsigned int len) { @@ -181,7 +181,6 @@ extern void init_cayman_irq(void); static struct sh_machine_vector mv_cayman __initmv = { .mv_name = "Hitachi Cayman", - .mv_nr_irqs = 64, .mv_ioport_map = cayman_ioport_map, .mv_init_irq = init_cayman_irq, }; diff --git a/arch/sh/boards/dreamcast/Makefile b/arch/sh/boards/mach-dreamcast/Makefile index 7b97546c7e5..7b97546c7e5 100644 --- a/arch/sh/boards/dreamcast/Makefile +++ b/arch/sh/boards/mach-dreamcast/Makefile diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c new file mode 100644 index 00000000000..2789647abeb --- /dev/null +++ b/arch/sh/boards/mach-dreamcast/irq.c @@ -0,0 +1,156 @@ +/* + * arch/sh/boards/dreamcast/irq.c + * + * Holly IRQ support for the Sega Dreamcast. + * + * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> + * + * This file is part of the LinuxDC project (www.linuxdc.org) + * Released under the terms of the GNU GPL v2.0 + */ +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/export.h> +#include <linux/err.h> +#include <mach/sysasic.h> + +/* + * Dreamcast System ASIC Hardware Events - + * + * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving + * hardware events from system peripherals and triggering an SH7750 IRQ. + * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are + * set in the Event Mask Registers (EMRs). When a hardware event is + * triggered, its corresponding bit in the Event Status Registers (ESRs) + * is set, and that bit should be rewritten to the ESR to acknowledge that + * event. + * + * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event + * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h. + * There are three groups of EMRs that parallel the ESRs. Each EMR group + * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, + * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 + * triggers IRQ 9. + * + * In the kernel, these events are mapped to virtual IRQs so that drivers can + * respond to them as they would a normal interrupt. In order to keep this + * mapping simple, the events are mapped as: + * + * 6900/6910 - Events 0-31, IRQ 13 + * 6904/6924 - Events 32-63, IRQ 11 + * 6908/6938 - Events 64-95, IRQ 9 + * + */ + +#define ESR_BASE 0x005f6900 /* Base event status register */ +#define EMR_BASE 0x005f6910 /* Base event mask register */ + +/* + * Helps us determine the EMR group that this event belongs to: 0 = 0x6910, + * 1 = 0x6920, 2 = 0x6930; also determine the event offset. + */ +#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) + +/* Return the hardware event's bit position within the EMR/ESR */ +#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) + +/* + * For each of these *_irq routines, the IRQ passed in is the virtual IRQ + * (logically mapped to the corresponding bit for the hardware event). + */ + +/* Disable the hardware event by masking its bit in its EMR */ +static inline void disable_systemasic_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); + __u32 mask; + + mask = inl(emr); + mask &= ~(1 << EVENT_BIT(irq)); + outl(mask, emr); +} + +/* Enable the hardware event by setting its bit in its EMR */ +static inline void enable_systemasic_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); + __u32 mask; + + mask = inl(emr); + mask |= (1 << EVENT_BIT(irq)); + outl(mask, emr); +} + +/* Acknowledge a hardware event by writing its bit back to its ESR */ +static void mask_ack_systemasic_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + __u32 esr = ESR_BASE + (LEVEL(irq) << 2); + disable_systemasic_irq(data); + outl((1 << EVENT_BIT(irq)), esr); +} + +struct irq_chip systemasic_int = { + .name = "System ASIC", + .irq_mask = disable_systemasic_irq, + .irq_mask_ack = mask_ack_systemasic_irq, + .irq_unmask = enable_systemasic_irq, +}; + +/* + * Map the hardware event indicated by the processor IRQ to a virtual IRQ. + */ +int systemasic_irq_demux(int irq) +{ + __u32 emr, esr, status, level; + __u32 j, bit; + + switch (irq) { + case 13: + level = 0; + break; + case 11: + level = 1; + break; + case 9: + level = 2; + break; + default: + return irq; + } + emr = EMR_BASE + (level << 4) + (level << 2); + esr = ESR_BASE + (level << 2); + + /* Mask the ESR to filter any spurious, unwanted interrupts */ + status = inl(esr); + status &= inl(emr); + + /* Now scan and find the first set bit as the event to map */ + for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { + if (status & bit) { + irq = HW_EVENT_IRQ_BASE + j + (level << 5); + return irq; + } + } + + /* Not reached */ + return irq; +} + +void systemasic_irq_init(void) +{ + int irq_base, i; + + irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE, + HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1); + if (IS_ERR_VALUE(irq_base)) { + pr_err("%s: failed hooking irqs\n", __func__); + return; + } + + for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) + irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq); +} diff --git a/arch/sh/boards/dreamcast/rtc.c b/arch/sh/boards/mach-dreamcast/rtc.c index b3a876a3b85..061d65714fc 100644 --- a/arch/sh/boards/dreamcast/rtc.c +++ b/arch/sh/boards/mach-dreamcast/rtc.c @@ -30,16 +30,16 @@ * * Grabs the current RTC seconds counter and adjusts it to the Unix Epoch. */ -void aica_rtc_gettimeofday(struct timespec *ts) +static void aica_rtc_gettimeofday(struct timespec *ts) { unsigned long val1, val2; do { - val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | - (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); + val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (__raw_readl(AICA_RTC_SECS_L) & 0xffff); - val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | - (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); + val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (__raw_readl(AICA_RTC_SECS_L) & 0xffff); } while (val1 != val2); ts->tv_sec = val1 - TWENTY_YEARS; @@ -54,20 +54,20 @@ void aica_rtc_gettimeofday(struct timespec *ts) * * Adjusts the given @tv to the AICA Epoch and sets the RTC seconds counter. */ -int aica_rtc_settimeofday(const time_t secs) +static int aica_rtc_settimeofday(const time_t secs) { unsigned long val1, val2; unsigned long adj = secs + TWENTY_YEARS; do { - ctrl_outl((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); - ctrl_outl((adj & 0xffff), AICA_RTC_SECS_L); + __raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); + __raw_writel((adj & 0xffff), AICA_RTC_SECS_L); - val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | - (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); + val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (__raw_readl(AICA_RTC_SECS_L) & 0xffff); - val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | - (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); + val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (__raw_readl(AICA_RTC_SECS_L) & 0xffff); } while (val1 != val2); return 0; diff --git a/arch/sh/boards/dreamcast/setup.c b/arch/sh/boards/mach-dreamcast/setup.c index 2581c8cd5df..ad1a4db72e0 100644 --- a/arch/sh/boards/dreamcast/setup.c +++ b/arch/sh/boards/mach-dreamcast/setup.c @@ -26,39 +26,16 @@ #include <asm/irq.h> #include <asm/rtc.h> #include <asm/machvec.h> -#include <asm/mach/sysasic.h> - -extern struct hw_interrupt_type systemasic_int; -extern void aica_time_init(void); -extern int gapspci_init(void); -extern int systemasic_irq_demux(int); +#include <mach/sysasic.h> static void __init dreamcast_setup(char **cmdline_p) { - int i; - - /* Mask all hardware events */ - /* XXX */ - - /* Acknowledge any previous events */ - /* XXX */ - - __set_io_port_base(0xa0000000); - - /* Assign all virtual IRQs to the System ASIC int. handler */ - for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) - irq_desc[i].chip = &systemasic_int; - board_time_init = aica_time_init; - -#ifdef CONFIG_PCI - if (gapspci_init() < 0) - printk(KERN_WARNING "GAPSPCI was not detected.\n"); -#endif } static struct sh_machine_vector mv_dreamcast __initmv = { .mv_name = "Sega Dreamcast", .mv_setup = dreamcast_setup, .mv_irq_demux = systemasic_irq_demux, + .mv_init_irq = systemasic_irq_init, }; diff --git a/arch/sh/boards/mach-ecovec24/Makefile b/arch/sh/boards/mach-ecovec24/Makefile new file mode 100644 index 00000000000..e69bc82208f --- /dev/null +++ b/arch/sh/boards/mach-ecovec24/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the R0P7724LC0011/21RL (EcoVec) +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# + +obj-y := setup.o sdram.o
\ No newline at end of file diff --git a/arch/sh/boards/mach-ecovec24/sdram.S b/arch/sh/boards/mach-ecovec24/sdram.S new file mode 100644 index 00000000000..3963c6f23d5 --- /dev/null +++ b/arch/sh/boards/mach-ecovec24/sdram.S @@ -0,0 +1,111 @@ +/* + * Ecovec24 sdram self/auto-refresh setup code + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/sys.h> +#include <linux/errno.h> +#include <linux/linkage.h> +#include <asm/asm-offsets.h> +#include <asm/suspend.h> +#include <asm/romimage-macros.h> + +/* code to enter and leave self-refresh. must be self-contained. + * this code will be copied to on-chip memory and executed from there. + */ + .balign 4 +ENTRY(ecovec24_sdram_enter_start) + + /* DBSC: put memory in self-refresh mode */ + + ED 0xFD000010, 0x00000000 /* DBEN */ + ED 0xFD000040, 0x00000000 /* DBRFPDN0 */ + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000040, 0x00000001 /* DBRFPDN0 */ + + rts + nop + +ENTRY(ecovec24_sdram_enter_end) + + .balign 4 +ENTRY(ecovec24_sdram_leave_start) + + mov.l @(SH_SLEEP_MODE, r5), r0 + tst #SUSP_SH_RSTANDBY, r0 + bf resume_rstandby + + /* DBSC: put memory in auto-refresh mode */ + + ED 0xFD000040, 0x00000000 /* DBRFPDN0 */ + WAIT 1 + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000010, 0x00000001 /* DBEN */ + ED 0xFD000040, 0x00010000 /* DBRFPDN0 */ + + rts + nop + +resume_rstandby: + + /* DBSC: re-initialize and put in auto-refresh */ + + ED 0xFD000108, 0x00000181 /* DBPDCNT0 */ + ED 0xFD000020, 0x015B0002 /* DBCONF */ + ED 0xFD000030, 0x03071502 /* DBTR0 */ + ED 0xFD000034, 0x02020102 /* DBTR1 */ + ED 0xFD000038, 0x01090405 /* DBTR2 */ + ED 0xFD00003C, 0x00000002 /* DBTR3 */ + ED 0xFD000008, 0x00000005 /* DBKIND */ + ED 0xFD000040, 0x00000001 /* DBRFPDN0 */ + ED 0xFD000040, 0x00000000 /* DBRFPDN0 */ + ED 0xFD000018, 0x00000001 /* DBCKECNT */ + + mov #100,r0 +WAIT_400NS: + dt r0 + bf WAIT_400NS + + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000060, 0x00020000 /* DBMRCNT (EMR2) */ + ED 0xFD000060, 0x00030000 /* DBMRCNT (EMR3) */ + ED 0xFD000060, 0x00010004 /* DBMRCNT (EMR) */ + ED 0xFD000060, 0x00000532 /* DBMRCNT (MRS) */ + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000060, 0x00000432 /* DBMRCNT (MRS) */ + ED 0xFD000060, 0x000103c0 /* DBMRCNT (EMR) */ + ED 0xFD000060, 0x00010040 /* DBMRCNT (EMR) */ + + mov #100,r0 +WAIT_400NS_2: + dt r0 + bf WAIT_400NS_2 + + ED 0xFD000010, 0x00000001 /* DBEN */ + ED 0xFD000044, 0x0000050f /* DBRFPDN1 */ + ED 0xFD000048, 0x236800e6 /* DBRFPDN2 */ + + mov.l DUMMY,r0 + mov.l @r0, r1 /* force single dummy read */ + + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000108, 0x00000080 /* DBPDCNT0 */ + ED 0xFD000040, 0x00010000 /* DBRFPDN0 */ + + rts + nop + + .balign 4 +DUMMY: .long 0xac400000 + +ENTRY(ecovec24_sdram_leave_end) diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c new file mode 100644 index 00000000000..85d5255d259 --- /dev/null +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -0,0 +1,1448 @@ +/* + * Copyright (C) 2009 Renesas Solutions Corp. + * + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> +#include <linux/mmc/sh_mobile_sdhi.h> +#include <linux/mtd/physmap.h> +#include <linux/mfd/tmio.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/usb/r8a66597.h> +#include <linux/usb/renesas_usbhs.h> +#include <linux/i2c.h> +#include <linux/i2c/tsc2007.h> +#include <linux/spi/spi.h> +#include <linux/spi/sh_msiof.h> +#include <linux/spi/mmc_spi.h> +#include <linux/input.h> +#include <linux/input/sh_keysc.h> +#include <linux/platform_data/gpio_backlight.h> +#include <linux/sh_eth.h> +#include <linux/sh_intc.h> +#include <linux/videodev2.h> +#include <video/sh_mobile_lcdc.h> +#include <sound/sh_fsi.h> +#include <sound/simple_card.h> +#include <media/sh_mobile_ceu.h> +#include <media/soc_camera.h> +#include <media/tw9910.h> +#include <media/mt9t112.h> +#include <asm/heartbeat.h> +#include <asm/clock.h> +#include <asm/suspend.h> +#include <cpu/sh7724.h> + +/* + * Address Interface BusWidth + *----------------------------------------- + * 0x0000_0000 uboot 16bit + * 0x0004_0000 Linux romImage 16bit + * 0x0014_0000 MTD for Linux 16bit + * 0x0400_0000 Internal I/O 16/32bit + * 0x0800_0000 DRAM 32bit + * 0x1800_0000 MFI 16bit + */ + +/* SWITCH + *------------------------------ + * DS2[1] = FlashROM write protect ON : write protect + * OFF : No write protect + * DS2[2] = RMII / TS, SCIF ON : RMII + * OFF : TS, SCIF3 + * DS2[3] = Camera / Video ON : Camera + * OFF : NTSC/PAL (IN) + * DS2[5] = NTSC_OUT Clock ON : On board OSC + * OFF : SH7724 DV_CLK + * DS2[6-7] = MMC / SD ON-OFF : SD + * OFF-ON : MMC + */ + +/* + * FSI - DA7210 + * + * it needs amixer settings for playing + * + * amixer set 'HeadPhone' 80 + * amixer set 'Out Mixer Left DAC Left' on + * amixer set 'Out Mixer Right DAC Right' on + */ + +/* Heartbeat */ +static unsigned char led_pos[] = { 0, 1, 2, 3 }; + +static struct heartbeat_data heartbeat_data = { + .nr_bits = 4, + .bit_pos = led_pos, +}; + +static struct resource heartbeat_resource = { + .start = 0xA405012C, /* PTG */ + .end = 0xA405012E - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* MTD */ +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "boot loader", + .offset = 0, + .size = (5 * 1024 * 1024), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "free-area", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x03ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .resource = nor_flash_resources, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .dev = { + .platform_data = &nor_flash_data, + }, +}; + +/* SH Eth */ +#define SH_ETH_ADDR (0xA4600000) +static struct resource sh_eth_resources[] = { + [0] = { + .start = SH_ETH_ADDR, + .end = SH_ETH_ADDR + 0x1FC, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xd60), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct sh_eth_plat_data sh_eth_plat = { + .phy = 0x1f, /* SMSC LAN8700 */ + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .phy_interface = PHY_INTERFACE_MODE_MII, + .ether_link_active_low = 1 +}; + +static struct platform_device sh_eth_device = { + .name = "sh7724-ether", + .id = 0, + .dev = { + .platform_data = &sh_eth_plat, + }, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .resource = sh_eth_resources, +}; + +/* USB0 host */ +static void usb0_port_power(int port, int power) +{ + gpio_set_value(GPIO_PTB4, power); +} + +static struct r8a66597_platdata usb0_host_data = { + .on_chip = 1, + .port_power = usb0_port_power, +}; + +static struct resource usb0_host_resources[] = { + [0] = { + .start = 0xa4d80000, + .end = 0xa4d80124 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device usb0_host_device = { + .name = "r8a66597_hcd", + .id = 0, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &usb0_host_data, + }, + .num_resources = ARRAY_SIZE(usb0_host_resources), + .resource = usb0_host_resources, +}; + +/* USB1 host/function */ +static void usb1_port_power(int port, int power) +{ + gpio_set_value(GPIO_PTB5, power); +} + +static struct r8a66597_platdata usb1_common_data = { + .on_chip = 1, + .port_power = usb1_port_power, +}; + +static struct resource usb1_common_resources[] = { + [0] = { + .start = 0xa4d90000, + .end = 0xa4d90124 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xa40), + .end = evt2irq(0xa40), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device usb1_common_device = { + /* .name will be added in arch_setup */ + .id = 1, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &usb1_common_data, + }, + .num_resources = ARRAY_SIZE(usb1_common_resources), + .resource = usb1_common_resources, +}; + +/* + * USBHS + */ +static int usbhs_get_id(struct platform_device *pdev) +{ + return gpio_get_value(GPIO_PTB3); +} + +static int usbhs_phy_reset(struct platform_device *pdev) +{ + /* enable vbus if HOST */ + if (!gpio_get_value(GPIO_PTB3)) + gpio_set_value(GPIO_PTB5, 1); + + return 0; +} + +static struct renesas_usbhs_platform_info usbhs_info = { + .platform_callback = { + .get_id = usbhs_get_id, + .phy_reset = usbhs_phy_reset, + }, + .driver_param = { + .buswait_bwait = 4, + .detection_delay = 5, + .d0_tx_id = SHDMA_SLAVE_USB1D0_TX, + .d0_rx_id = SHDMA_SLAVE_USB1D0_RX, + .d1_tx_id = SHDMA_SLAVE_USB1D1_TX, + .d1_rx_id = SHDMA_SLAVE_USB1D1_RX, + }, +}; + +static struct resource usbhs_resources[] = { + [0] = { + .start = 0xa4d90000, + .end = 0xa4d90124 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xa40), + .end = evt2irq(0xa40), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usbhs_device = { + .name = "renesas_usbhs", + .id = 1, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &usbhs_info, + }, + .num_resources = ARRAY_SIZE(usbhs_resources), + .resource = usbhs_resources, +}; + +/* LCDC and backlight */ +static const struct fb_videomode ecovec_lcd_modes[] = { + { + .name = "Panel", + .xres = 800, + .yres = 480, + .left_margin = 220, + .right_margin = 110, + .hsync_len = 70, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + .sync = 0, /* hsync and vsync are active low */ + }, +}; + +static const struct fb_videomode ecovec_dvi_modes[] = { + { + .name = "DVI", + .xres = 1280, + .yres = 720, + .left_margin = 220, + .right_margin = 110, + .hsync_len = 40, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + .sync = 0, /* hsync and vsync are active low */ + }, +}; + +static struct sh_mobile_lcdc_info lcdc_info = { + .ch[0] = { + .interface_type = RGB18, + .chan = LCDC_CHAN_MAINLCD, + .fourcc = V4L2_PIX_FMT_RGB565, + .panel_cfg = { /* 7.0 inch */ + .width = 152, + .height = 91, + }, + } +}; + +static struct resource lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, + .end = 0xfe942fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xf40), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(lcdc_resources), + .resource = lcdc_resources, + .dev = { + .platform_data = &lcdc_info, + }, +}; + +static struct gpio_backlight_platform_data gpio_backlight_data = { + .fbdev = &lcdc_device.dev, + .gpio = GPIO_PTR1, + .def_value = 1, + .name = "backlight", +}; + +static struct platform_device gpio_backlight_device = { + .name = "gpio-backlight", + .dev = { + .platform_data = &gpio_backlight_data, + }, +}; + +/* CEU0 */ +static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource ceu0_resources[] = { + [0] = { + .name = "CEU0", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x880), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu0_device = { + .name = "sh_mobile_ceu", + .id = 0, /* "ceu0" clock */ + .num_resources = ARRAY_SIZE(ceu0_resources), + .resource = ceu0_resources, + .dev = { + .platform_data = &sh_mobile_ceu0_info, + }, +}; + +/* CEU1 */ +static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource ceu1_resources[] = { + [0] = { + .name = "CEU1", + .start = 0xfe914000, + .end = 0xfe91409f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x9e0), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu1_device = { + .name = "sh_mobile_ceu", + .id = 1, /* "ceu1" clock */ + .num_resources = ARRAY_SIZE(ceu1_resources), + .resource = ceu1_resources, + .dev = { + .platform_data = &sh_mobile_ceu1_info, + }, +}; + +/* I2C device */ +static struct i2c_board_info i2c0_devices[] = { + { + I2C_BOARD_INFO("da7210", 0x1a), + }, +}; + +static struct i2c_board_info i2c1_devices[] = { + { + I2C_BOARD_INFO("r2025sd", 0x32), + }, + { + I2C_BOARD_INFO("lis3lv02d", 0x1c), + .irq = evt2irq(0x620), + } +}; + +/* KEYSC */ +static struct sh_keysc_info keysc_info = { + .mode = SH_KEYSC_MODE_1, + .scan_timing = 3, + .delay = 50, + .kycr2_delay = 100, + .keycodes = { KEY_1, 0, 0, 0, 0, + KEY_2, 0, 0, 0, 0, + KEY_3, 0, 0, 0, 0, + KEY_4, 0, 0, 0, 0, + KEY_5, 0, 0, 0, 0, + KEY_6, 0, 0, 0, 0, }, +}; + +static struct resource keysc_resources[] = { + [0] = { + .name = "KEYSC", + .start = 0x044b0000, + .end = 0x044b000f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xbe0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device keysc_device = { + .name = "sh_keysc", + .id = 0, /* keysc0 clock */ + .num_resources = ARRAY_SIZE(keysc_resources), + .resource = keysc_resources, + .dev = { + .platform_data = &keysc_info, + }, +}; + +/* TouchScreen */ +#define IRQ0 evt2irq(0x600) + +static int ts_get_pendown_state(struct device *dev) +{ + int val = 0; + gpio_free(GPIO_FN_INTC_IRQ0); + gpio_request(GPIO_PTZ0, NULL); + gpio_direction_input(GPIO_PTZ0); + + val = gpio_get_value(GPIO_PTZ0); + + gpio_free(GPIO_PTZ0); + gpio_request(GPIO_FN_INTC_IRQ0, NULL); + + return val ? 0 : 1; +} + +static int ts_init(void) +{ + gpio_request(GPIO_FN_INTC_IRQ0, NULL); + return 0; +} + +static struct tsc2007_platform_data tsc2007_info = { + .model = 2007, + .x_plate_ohms = 180, + .get_pendown_state = ts_get_pendown_state, + .init_platform_hw = ts_init, +}; + +static struct i2c_board_info ts_i2c_clients = { + I2C_BOARD_INFO("tsc2007", 0x48), + .type = "tsc2007", + .platform_data = &tsc2007_info, + .irq = IRQ0, +}; + +static struct regulator_consumer_supply cn12_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), +}; + +static struct regulator_init_data cn12_power_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(cn12_power_consumers), + .consumer_supplies = cn12_power_consumers, +}; + +static struct fixed_voltage_config cn12_power_info = { + .supply_name = "CN12 SD/MMC Vdd", + .microvolts = 3300000, + .gpio = GPIO_PTB7, + .enable_high = 1, + .init_data = &cn12_power_init_data, +}; + +static struct platform_device cn12_power = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &cn12_power_info, + }, +}; + +#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE) +/* SDHI0 */ +static struct regulator_consumer_supply sdhi0_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +}; + +static struct regulator_init_data sdhi0_power_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(sdhi0_power_consumers), + .consumer_supplies = sdhi0_power_consumers, +}; + +static struct fixed_voltage_config sdhi0_power_info = { + .supply_name = "CN11 SD/MMC Vdd", + .microvolts = 3300000, + .gpio = GPIO_PTB6, + .enable_high = 1, + .init_data = &sdhi0_power_init_data, +}; + +static struct platform_device sdhi0_power = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &sdhi0_power_info, + }, +}; + +static struct sh_mobile_sdhi_info sdhi0_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, + .tmio_caps = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD | + MMC_CAP_NEEDS_POLL, + .tmio_flags = TMIO_MMC_USE_GPIO_CD, + .cd_gpio = GPIO_PTY7, +}; + +static struct resource sdhi0_resources[] = { + [0] = { + .name = "SDHI0", + .start = 0x04ce0000, + .end = 0x04ce00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xe80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi0_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi0_resources), + .resource = sdhi0_resources, + .id = 0, + .dev = { + .platform_data = &sdhi0_info, + }, +}; + +#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) +/* SDHI1 */ +static struct sh_mobile_sdhi_info sdhi1_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, + .tmio_caps = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD | + MMC_CAP_NEEDS_POLL, + .tmio_flags = TMIO_MMC_USE_GPIO_CD, + .cd_gpio = GPIO_PTW7, +}; + +static struct resource sdhi1_resources[] = { + [0] = { + .name = "SDHI1", + .start = 0x04cf0000, + .end = 0x04cf00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x4e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi1_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi1_resources), + .resource = sdhi1_resources, + .id = 1, + .dev = { + .platform_data = &sdhi1_info, + }, +}; +#endif /* CONFIG_MMC_SH_MMCIF */ + +#else + +/* MMC SPI */ +static void mmc_spi_setpower(struct device *dev, unsigned int maskval) +{ + gpio_set_value(GPIO_PTB6, maskval ? 1 : 0); +} + +static struct mmc_spi_platform_data mmc_spi_info = { + .caps = MMC_CAP_NEEDS_POLL, + .caps2 = MMC_CAP2_RO_ACTIVE_HIGH, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */ + .setpower = mmc_spi_setpower, + .flags = MMC_SPI_USE_CD_GPIO | MMC_SPI_USE_RO_GPIO, + .cd_gpio = GPIO_PTY7, + .ro_gpio = GPIO_PTY6, +}; + +static struct spi_board_info spi_bus[] = { + { + .modalias = "mmc_spi", + .platform_data = &mmc_spi_info, + .max_speed_hz = 5000000, + .mode = SPI_MODE_0, + .controller_data = (void *) GPIO_PTM4, + }, +}; + +/* MSIOF0 */ +static struct sh_msiof_spi_info msiof0_data = { + .num_chipselect = 1, +}; + +static struct resource msiof0_resources[] = { + [0] = { + .name = "MSIOF0", + .start = 0xa4c40000, + .end = 0xa4c40063, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xc80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device msiof0_device = { + .name = "spi_sh_msiof", + .id = 0, /* MSIOF0 */ + .dev = { + .platform_data = &msiof0_data, + }, + .num_resources = ARRAY_SIZE(msiof0_resources), + .resource = msiof0_resources, +}; + +#endif + +/* I2C Video/Camera */ +static struct i2c_board_info i2c_camera[] = { + { + I2C_BOARD_INFO("tw9910", 0x45), + }, + { + /* 1st camera */ + I2C_BOARD_INFO("mt9t112", 0x3c), + }, + { + /* 2nd camera */ + I2C_BOARD_INFO("mt9t112", 0x3c), + }, +}; + +/* tw9910 */ +static int tw9910_power(struct device *dev, int mode) +{ + int val = mode ? 0 : 1; + + gpio_set_value(GPIO_PTU2, val); + if (mode) + mdelay(100); + + return 0; +} + +static struct tw9910_video_info tw9910_info = { + .buswidth = SOCAM_DATAWIDTH_8, + .mpout = TW9910_MPO_FIELD, +}; + +static struct soc_camera_link tw9910_link = { + .i2c_adapter_id = 0, + .bus_id = 1, + .power = tw9910_power, + .board_info = &i2c_camera[0], + .priv = &tw9910_info, +}; + +/* mt9t112 */ +static int mt9t112_power1(struct device *dev, int mode) +{ + gpio_set_value(GPIO_PTA3, mode); + if (mode) + mdelay(100); + + return 0; +} + +static struct mt9t112_camera_info mt9t112_info1 = { + .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8, + .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */ +}; + +static struct soc_camera_link mt9t112_link1 = { + .i2c_adapter_id = 0, + .power = mt9t112_power1, + .bus_id = 0, + .board_info = &i2c_camera[1], + .priv = &mt9t112_info1, +}; + +static int mt9t112_power2(struct device *dev, int mode) +{ + gpio_set_value(GPIO_PTA4, mode); + if (mode) + mdelay(100); + + return 0; +} + +static struct mt9t112_camera_info mt9t112_info2 = { + .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8, + .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */ +}; + +static struct soc_camera_link mt9t112_link2 = { + .i2c_adapter_id = 1, + .power = mt9t112_power2, + .bus_id = 1, + .board_info = &i2c_camera[2], + .priv = &mt9t112_info2, +}; + +static struct platform_device camera_devices[] = { + { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &tw9910_link, + }, + }, + { + .name = "soc-camera-pdrv", + .id = 1, + .dev = { + .platform_data = &mt9t112_link1, + }, + }, + { + .name = "soc-camera-pdrv", + .id = 2, + .dev = { + .platform_data = &mt9t112_link2, + }, + }, +}; + +/* FSI */ +static struct resource fsi_resources[] = { + [0] = { + .name = "FSI", + .start = 0xFE3C0000, + .end = 0xFE3C021d, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xf80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device fsi_device = { + .name = "sh_fsi", + .id = 0, + .num_resources = ARRAY_SIZE(fsi_resources), + .resource = fsi_resources, +}; + +static struct asoc_simple_card_info fsi_da7210_info = { + .name = "DA7210", + .card = "FSIB-DA7210", + .codec = "da7210.0-001a", + .platform = "sh_fsi.0", + .daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, + .cpu_dai = { + .name = "fsib-dai", + }, + .codec_dai = { + .name = "da7210-hifi", + }, +}; + +static struct platform_device fsi_da7210_device = { + .name = "asoc-simple-card", + .dev = { + .platform_data = &fsi_da7210_info, + }, +}; + + +/* IrDA */ +static struct resource irda_resources[] = { + [0] = { + .name = "IrDA", + .start = 0xA45D0000, + .end = 0xA45D0049, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x480), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device irda_device = { + .name = "sh_sir", + .num_resources = ARRAY_SIZE(irda_resources), + .resource = irda_resources, +}; + +#include <media/ak881x.h> +#include <media/sh_vou.h> + +static struct ak881x_pdata ak881x_pdata = { + .flags = AK881X_IF_MODE_SLAVE, +}; + +static struct i2c_board_info ak8813 = { + I2C_BOARD_INFO("ak8813", 0x20), + .platform_data = &ak881x_pdata, +}; + +static struct sh_vou_pdata sh_vou_pdata = { + .bus_fmt = SH_VOU_BUS_8BIT, + .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, + .board_info = &ak8813, + .i2c_adap = 0, +}; + +static struct resource sh_vou_resources[] = { + [0] = { + .start = 0xfe960000, + .end = 0xfe962043, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x8e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vou_device = { + .name = "sh-vou", + .id = -1, + .num_resources = ARRAY_SIZE(sh_vou_resources), + .resource = sh_vou_resources, + .dev = { + .platform_data = &sh_vou_pdata, + }, +}; + +#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE) +/* SH_MMCIF */ +static struct resource sh_mmcif_resources[] = { + [0] = { + .name = "SH_MMCIF", + .start = 0xA4CA0000, + .end = 0xA4CA00FF, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* MMC2I */ + .start = evt2irq(0x5a0), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* MMC3I */ + .start = evt2irq(0x5c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_plat_data sh_mmcif_plat = { + .sup_pclk = 0, /* SH7724: Max Pclk/2 */ + .caps = MMC_CAP_4_BIT_DATA | + MMC_CAP_8_BIT_DATA | + MMC_CAP_NEEDS_POLL, + .ocr = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static struct platform_device sh_mmcif_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .platform_data = &sh_mmcif_plat, + }, + .num_resources = ARRAY_SIZE(sh_mmcif_resources), + .resource = sh_mmcif_resources, +}; +#endif + +static struct platform_device *ecovec_devices[] __initdata = { + &heartbeat_device, + &nor_flash_device, + &sh_eth_device, + &usb0_host_device, + &usb1_common_device, + &usbhs_device, + &lcdc_device, + &gpio_backlight_device, + &ceu0_device, + &ceu1_device, + &keysc_device, + &cn12_power, +#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE) + &sdhi0_power, + &sdhi0_device, +#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) + &sdhi1_device, +#endif +#else + &msiof0_device, +#endif + &camera_devices[0], + &camera_devices[1], + &camera_devices[2], + &fsi_device, + &fsi_da7210_device, + &irda_device, + &vou_device, +#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE) + &sh_mmcif_device, +#endif +}; + +#ifdef CONFIG_I2C +#define EEPROM_ADDR 0x50 +static u8 mac_read(struct i2c_adapter *a, u8 command) +{ + struct i2c_msg msg[2]; + u8 buf; + int ret; + + msg[0].addr = EEPROM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &command; + + msg[1].addr = EEPROM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf; + + ret = i2c_transfer(a, msg, 2); + if (ret < 0) { + printk(KERN_ERR "error %d\n", ret); + buf = 0xff; + } + + return buf; +} + +static void __init sh_eth_init(struct sh_eth_plat_data *pd) +{ + struct i2c_adapter *a = i2c_get_adapter(1); + int i; + + if (!a) { + pr_err("can not get I2C 1\n"); + return; + } + + /* read MAC address from EEPROM */ + for (i = 0; i < sizeof(pd->mac_addr); i++) { + pd->mac_addr[i] = mac_read(a, 0x10 + i); + msleep(10); + } + + i2c_put_adapter(a); +} +#else +static void __init sh_eth_init(struct sh_eth_plat_data *pd) +{ + pr_err("unable to read sh_eth MAC address\n"); +} +#endif + +#define PORT_HIZA 0xA4050158 +#define IODRIVEA 0xA405018A + +extern char ecovec24_sdram_enter_start; +extern char ecovec24_sdram_enter_end; +extern char ecovec24_sdram_leave_start; +extern char ecovec24_sdram_leave_end; + +static int __init arch_setup(void) +{ + struct clk *clk; + bool cn12_enabled = false; + + /* register board specific self-refresh code */ + sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | + SUSP_SH_RSTANDBY, + &ecovec24_sdram_enter_start, + &ecovec24_sdram_enter_end, + &ecovec24_sdram_leave_start, + &ecovec24_sdram_leave_end); + + /* enable STATUS0, STATUS2 and PDSTATUS */ + gpio_request(GPIO_FN_STATUS0, NULL); + gpio_request(GPIO_FN_STATUS2, NULL); + gpio_request(GPIO_FN_PDSTATUS, NULL); + + /* enable SCIFA0 */ + gpio_request(GPIO_FN_SCIF0_TXD, NULL); + gpio_request(GPIO_FN_SCIF0_RXD, NULL); + + /* enable debug LED */ + gpio_request(GPIO_PTG0, NULL); + gpio_request(GPIO_PTG1, NULL); + gpio_request(GPIO_PTG2, NULL); + gpio_request(GPIO_PTG3, NULL); + gpio_direction_output(GPIO_PTG0, 0); + gpio_direction_output(GPIO_PTG1, 0); + gpio_direction_output(GPIO_PTG2, 0); + gpio_direction_output(GPIO_PTG3, 0); + __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA); + + /* enable SH-Eth */ + gpio_request(GPIO_PTA1, NULL); + gpio_direction_output(GPIO_PTA1, 1); + mdelay(20); + + gpio_request(GPIO_FN_RMII_RXD0, NULL); + gpio_request(GPIO_FN_RMII_RXD1, NULL); + gpio_request(GPIO_FN_RMII_TXD0, NULL); + gpio_request(GPIO_FN_RMII_TXD1, NULL); + gpio_request(GPIO_FN_RMII_REF_CLK, NULL); + gpio_request(GPIO_FN_RMII_TX_EN, NULL); + gpio_request(GPIO_FN_RMII_RX_ER, NULL); + gpio_request(GPIO_FN_RMII_CRS_DV, NULL); + gpio_request(GPIO_FN_MDIO, NULL); + gpio_request(GPIO_FN_MDC, NULL); + gpio_request(GPIO_FN_LNKSTA, NULL); + + /* enable USB */ + __raw_writew(0x0000, 0xA4D80000); + __raw_writew(0x0000, 0xA4D90000); + gpio_request(GPIO_PTB3, NULL); + gpio_request(GPIO_PTB4, NULL); + gpio_request(GPIO_PTB5, NULL); + gpio_direction_input(GPIO_PTB3); + gpio_direction_output(GPIO_PTB4, 0); + gpio_direction_output(GPIO_PTB5, 0); + __raw_writew(0x0600, 0xa40501d4); + __raw_writew(0x0600, 0xa4050192); + + if (gpio_get_value(GPIO_PTB3)) { + printk(KERN_INFO "USB1 function is selected\n"); + usb1_common_device.name = "r8a66597_udc"; + } else { + printk(KERN_INFO "USB1 host is selected\n"); + usb1_common_device.name = "r8a66597_hcd"; + } + + /* enable LCDC */ + gpio_request(GPIO_FN_LCDD23, NULL); + gpio_request(GPIO_FN_LCDD22, NULL); + gpio_request(GPIO_FN_LCDD21, NULL); + gpio_request(GPIO_FN_LCDD20, NULL); + gpio_request(GPIO_FN_LCDD19, NULL); + gpio_request(GPIO_FN_LCDD18, NULL); + gpio_request(GPIO_FN_LCDD17, NULL); + gpio_request(GPIO_FN_LCDD16, NULL); + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDDISP, NULL); + gpio_request(GPIO_FN_LCDHSYN, NULL); + gpio_request(GPIO_FN_LCDDCK, NULL); + gpio_request(GPIO_FN_LCDVSYN, NULL); + gpio_request(GPIO_FN_LCDDON, NULL); + gpio_request(GPIO_FN_LCDLCLK, NULL); + __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); + + gpio_request(GPIO_PTE6, NULL); + gpio_request(GPIO_PTU1, NULL); + gpio_request(GPIO_PTA2, NULL); + gpio_direction_input(GPIO_PTE6); + gpio_direction_output(GPIO_PTU1, 0); + gpio_direction_output(GPIO_PTA2, 0); + + /* I/O buffer drive ability is high */ + __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA); + + if (gpio_get_value(GPIO_PTE6)) { + /* DVI */ + lcdc_info.clock_source = LCDC_CLK_EXTERNAL; + lcdc_info.ch[0].clock_divider = 1; + lcdc_info.ch[0].lcd_modes = ecovec_dvi_modes; + lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_dvi_modes); + + /* No backlight */ + gpio_backlight_data.fbdev = NULL; + + gpio_set_value(GPIO_PTA2, 1); + gpio_set_value(GPIO_PTU1, 1); + } else { + /* Panel */ + lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; + lcdc_info.ch[0].clock_divider = 2; + lcdc_info.ch[0].lcd_modes = ecovec_lcd_modes; + lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_lcd_modes); + + /* FIXME + * + * LCDDON control is needed for Panel, + * but current sh_mobile_lcdc driver doesn't control it. + * It is temporary correspondence + */ + gpio_request(GPIO_PTF4, NULL); + gpio_direction_output(GPIO_PTF4, 1); + + /* enable TouchScreen */ + i2c_register_board_info(0, &ts_i2c_clients, 1); + irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); + } + + /* enable CEU0 */ + gpio_request(GPIO_FN_VIO0_D15, NULL); + gpio_request(GPIO_FN_VIO0_D14, NULL); + gpio_request(GPIO_FN_VIO0_D13, NULL); + gpio_request(GPIO_FN_VIO0_D12, NULL); + gpio_request(GPIO_FN_VIO0_D11, NULL); + gpio_request(GPIO_FN_VIO0_D10, NULL); + gpio_request(GPIO_FN_VIO0_D9, NULL); + gpio_request(GPIO_FN_VIO0_D8, NULL); + gpio_request(GPIO_FN_VIO0_D7, NULL); + gpio_request(GPIO_FN_VIO0_D6, NULL); + gpio_request(GPIO_FN_VIO0_D5, NULL); + gpio_request(GPIO_FN_VIO0_D4, NULL); + gpio_request(GPIO_FN_VIO0_D3, NULL); + gpio_request(GPIO_FN_VIO0_D2, NULL); + gpio_request(GPIO_FN_VIO0_D1, NULL); + gpio_request(GPIO_FN_VIO0_D0, NULL); + gpio_request(GPIO_FN_VIO0_VD, NULL); + gpio_request(GPIO_FN_VIO0_CLK, NULL); + gpio_request(GPIO_FN_VIO0_FLD, NULL); + gpio_request(GPIO_FN_VIO0_HD, NULL); + platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); + + /* enable CEU1 */ + gpio_request(GPIO_FN_VIO1_D7, NULL); + gpio_request(GPIO_FN_VIO1_D6, NULL); + gpio_request(GPIO_FN_VIO1_D5, NULL); + gpio_request(GPIO_FN_VIO1_D4, NULL); + gpio_request(GPIO_FN_VIO1_D3, NULL); + gpio_request(GPIO_FN_VIO1_D2, NULL); + gpio_request(GPIO_FN_VIO1_D1, NULL); + gpio_request(GPIO_FN_VIO1_D0, NULL); + gpio_request(GPIO_FN_VIO1_FLD, NULL); + gpio_request(GPIO_FN_VIO1_HD, NULL); + gpio_request(GPIO_FN_VIO1_VD, NULL); + gpio_request(GPIO_FN_VIO1_CLK, NULL); + platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); + + /* enable KEYSC */ + gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); + gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYIN0, NULL); + + /* enable user debug switch */ + gpio_request(GPIO_PTR0, NULL); + gpio_request(GPIO_PTR4, NULL); + gpio_request(GPIO_PTR5, NULL); + gpio_request(GPIO_PTR6, NULL); + gpio_direction_input(GPIO_PTR0); + gpio_direction_input(GPIO_PTR4); + gpio_direction_input(GPIO_PTR5); + gpio_direction_input(GPIO_PTR6); + + /* SD-card slot CN11 */ +#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE) + /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */ + gpio_request(GPIO_FN_SDHI0WP, NULL); + gpio_request(GPIO_FN_SDHI0CMD, NULL); + gpio_request(GPIO_FN_SDHI0CLK, NULL); + gpio_request(GPIO_FN_SDHI0D3, NULL); + gpio_request(GPIO_FN_SDHI0D2, NULL); + gpio_request(GPIO_FN_SDHI0D1, NULL); + gpio_request(GPIO_FN_SDHI0D0, NULL); +#else + /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */ + gpio_request(GPIO_FN_MSIOF0_TXD, NULL); + gpio_request(GPIO_FN_MSIOF0_RXD, NULL); + gpio_request(GPIO_FN_MSIOF0_TSCK, NULL); + gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */ + gpio_direction_output(GPIO_PTM4, 1); /* active low CS */ + gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */ + gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */ + + spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus)); +#endif + + /* MMC/SD-card slot CN12 */ +#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE) + /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */ + gpio_request(GPIO_FN_MMC_D7, NULL); + gpio_request(GPIO_FN_MMC_D6, NULL); + gpio_request(GPIO_FN_MMC_D5, NULL); + gpio_request(GPIO_FN_MMC_D4, NULL); + gpio_request(GPIO_FN_MMC_D3, NULL); + gpio_request(GPIO_FN_MMC_D2, NULL); + gpio_request(GPIO_FN_MMC_D1, NULL); + gpio_request(GPIO_FN_MMC_D0, NULL); + gpio_request(GPIO_FN_MMC_CLK, NULL); + gpio_request(GPIO_FN_MMC_CMD, NULL); + + cn12_enabled = true; +#elif defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE) + /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */ + gpio_request(GPIO_FN_SDHI1WP, NULL); + gpio_request(GPIO_FN_SDHI1CMD, NULL); + gpio_request(GPIO_FN_SDHI1CLK, NULL); + gpio_request(GPIO_FN_SDHI1D3, NULL); + gpio_request(GPIO_FN_SDHI1D2, NULL); + gpio_request(GPIO_FN_SDHI1D1, NULL); + gpio_request(GPIO_FN_SDHI1D0, NULL); + + cn12_enabled = true; +#endif + + if (cn12_enabled) + /* I/O buffer drive ability is high for CN12 */ + __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000, + IODRIVEA); + + /* enable Video */ + gpio_request(GPIO_PTU2, NULL); + gpio_direction_output(GPIO_PTU2, 1); + + /* enable Camera */ + gpio_request(GPIO_PTA3, NULL); + gpio_request(GPIO_PTA4, NULL); + gpio_direction_output(GPIO_PTA3, 0); + gpio_direction_output(GPIO_PTA4, 0); + + /* enable FSI */ + gpio_request(GPIO_FN_FSIMCKB, NULL); + gpio_request(GPIO_FN_FSIIBSD, NULL); + gpio_request(GPIO_FN_FSIOBSD, NULL); + gpio_request(GPIO_FN_FSIIBBCK, NULL); + gpio_request(GPIO_FN_FSIIBLRCK, NULL); + gpio_request(GPIO_FN_FSIOBBCK, NULL); + gpio_request(GPIO_FN_FSIOBLRCK, NULL); + gpio_request(GPIO_FN_CLKAUDIOBO, NULL); + + /* set SPU2 clock to 83.4 MHz */ + clk = clk_get(NULL, "spu_clk"); + if (!IS_ERR(clk)) { + clk_set_rate(clk, clk_round_rate(clk, 83333333)); + clk_put(clk); + } + + /* change parent of FSI B */ + clk = clk_get(NULL, "fsib_clk"); + if (!IS_ERR(clk)) { + /* 48kHz dummy clock was used to make sure 1/1 divide */ + clk_set_rate(&sh7724_fsimckb_clk, 48000); + clk_set_parent(clk, &sh7724_fsimckb_clk); + clk_set_rate(clk, 48000); + clk_put(clk); + } + + gpio_request(GPIO_PTU0, NULL); + gpio_direction_output(GPIO_PTU0, 0); + mdelay(20); + + /* enable motion sensor */ + gpio_request(GPIO_FN_INTC_IRQ1, NULL); + gpio_direction_input(GPIO_FN_INTC_IRQ1); + + /* set VPU clock to 166 MHz */ + clk = clk_get(NULL, "vpu_clk"); + if (!IS_ERR(clk)) { + clk_set_rate(clk, clk_round_rate(clk, 166000000)); + clk_put(clk); + } + + /* enable IrDA */ + gpio_request(GPIO_FN_IRDA_OUT, NULL); + gpio_request(GPIO_FN_IRDA_IN, NULL); + gpio_request(GPIO_PTU5, NULL); + gpio_direction_output(GPIO_PTU5, 0); + + /* enable I2C device */ + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); + + i2c_register_board_info(1, i2c1_devices, + ARRAY_SIZE(i2c1_devices)); + +#if defined(CONFIG_VIDEO_SH_VOU) || defined(CONFIG_VIDEO_SH_VOU_MODULE) + /* VOU */ + gpio_request(GPIO_FN_DV_D15, NULL); + gpio_request(GPIO_FN_DV_D14, NULL); + gpio_request(GPIO_FN_DV_D13, NULL); + gpio_request(GPIO_FN_DV_D12, NULL); + gpio_request(GPIO_FN_DV_D11, NULL); + gpio_request(GPIO_FN_DV_D10, NULL); + gpio_request(GPIO_FN_DV_D9, NULL); + gpio_request(GPIO_FN_DV_D8, NULL); + gpio_request(GPIO_FN_DV_CLKI, NULL); + gpio_request(GPIO_FN_DV_CLK, NULL); + gpio_request(GPIO_FN_DV_VSYNC, NULL); + gpio_request(GPIO_FN_DV_HSYNC, NULL); + + /* AK8813 power / reset sequence */ + gpio_request(GPIO_PTG4, NULL); + gpio_request(GPIO_PTU3, NULL); + /* Reset */ + gpio_direction_output(GPIO_PTG4, 0); + /* Power down */ + gpio_direction_output(GPIO_PTU3, 1); + + udelay(10); + + /* Power up, reset */ + gpio_set_value(GPIO_PTU3, 0); + + udelay(10); + + /* Remove reset */ + gpio_set_value(GPIO_PTG4, 1); +#endif + + return platform_add_devices(ecovec_devices, + ARRAY_SIZE(ecovec_devices)); +} +arch_initcall(arch_setup); + +static int __init devices_setup(void) +{ + sh_eth_init(&sh_eth_plat); + return 0; +} +device_initcall(devices_setup); + +static struct sh_machine_vector mv_ecovec __initmv = { + .mv_name = "R0P7724 (EcoVec)", +}; diff --git a/arch/sh/boards/renesas/r7780rp/Kconfig b/arch/sh/boards/mach-highlander/Kconfig index fc8f28e04ba..def49cc0a7b 100644 --- a/arch/sh/boards/renesas/r7780rp/Kconfig +++ b/arch/sh/boards/mach-highlander/Kconfig @@ -18,6 +18,7 @@ config SH_R7780MP config SH_R7785RP bool "R7785RP board support" depends on CPU_SUBTYPE_SH7785 + select ARCH_REQUIRE_GPIOLIB endchoice diff --git a/arch/sh/boards/mach-highlander/Makefile b/arch/sh/boards/mach-highlander/Makefile new file mode 100644 index 00000000000..d93aaf88013 --- /dev/null +++ b/arch/sh/boards/mach-highlander/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for the Highlander specific parts of the kernel +# +obj-y := setup.o +obj-$(CONFIG_SH_R7780RP) += irq-r7780rp.o +obj-$(CONFIG_SH_R7780MP) += irq-r7780mp.o +obj-$(CONFIG_SH_R7785RP) += irq-r7785rp.o pinmux-r7785rp.o + +ifneq ($(CONFIG_SH_R7785RP),y) +obj-$(CONFIG_PUSH_SWITCH) += psw.o +endif diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c b/arch/sh/boards/mach-highlander/irq-r7780mp.c index 1f8f073f27b..9893fd3a135 100644 --- a/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c +++ b/arch/sh/boards/mach-highlander/irq-r7780mp.c @@ -12,46 +12,59 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/io.h> -#include <asm/r7780rp.h> +#include <mach/highlander.h> enum { UNUSED = 0, /* board specific interrupt sources */ - AX88796, /* Ethernet controller */ - CF, /* Compact Flash */ - PSW, /* Push Switch */ - EXT1, /* EXT1n IRQ */ - EXT4, /* EXT4n IRQ */ + CF, /* Compact Flash */ + TP, /* Touch panel */ + SCIF1, /* FPGA SCIF1 */ + SCIF0, /* FPGA SCIF0 */ + SMBUS, /* SMBUS */ + RTC, /* RTC Alarm */ + AX88796, /* Ethernet controller */ + PSW, /* Push Switch */ + + /* external bus connector */ + EXT1, EXT2, EXT4, EXT5, EXT6, }; static struct intc_vect vectors[] __initdata = { INTC_IRQ(CF, IRQ_CF), - INTC_IRQ(PSW, IRQ_PSW), + INTC_IRQ(TP, IRQ_TP), + INTC_IRQ(SCIF1, IRQ_SCIF1), + INTC_IRQ(SCIF0, IRQ_SCIF0), + INTC_IRQ(SMBUS, IRQ_SMBUS), + INTC_IRQ(RTC, IRQ_RTC), INTC_IRQ(AX88796, IRQ_AX88796), - INTC_IRQ(EXT1, IRQ_EXT1), - INTC_IRQ(EXT4, IRQ_EXT4), + INTC_IRQ(PSW, IRQ_PSW), + + INTC_IRQ(EXT1, IRQ_EXT1), INTC_IRQ(EXT2, IRQ_EXT2), + INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5), + INTC_IRQ(EXT6, IRQ_EXT6), }; static struct intc_mask_reg mask_registers[] __initdata = { { 0xa4000000, 0, 16, /* IRLMSK */ - { 0, 0, 0, 0, CF, 0, 0, 0, - 0, 0, 0, EXT4, 0, EXT1, PSW, AX88796 } }, + { SCIF0, SCIF1, RTC, 0, CF, 0, TP, SMBUS, + 0, EXT6, EXT5, EXT4, EXT2, EXT1, PSW, AX88796 } }, }; static unsigned char irl2irq[HL_NR_IRL] __initdata = { - 0, IRQ_CF, 0, 0, - 0, 0, 0, 0, - 0, IRQ_EXT4, 0, IRQ_EXT1, + 0, IRQ_CF, IRQ_TP, IRQ_SCIF1, + IRQ_SCIF0, IRQ_SMBUS, IRQ_RTC, IRQ_EXT6, + IRQ_EXT5, IRQ_EXT4, IRQ_EXT2, IRQ_EXT1, 0, IRQ_AX88796, IRQ_PSW, }; static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors, NULL, mask_registers, NULL, NULL); -unsigned char * __init highlander_init_irq_r7780mp(void) +unsigned char * __init highlander_plat_irq_setup(void) { - if ((ctrl_inw(0xa4000700) & 0xf000) == 0x2000) { + if ((__raw_readw(0xa4000700) & 0xf000) == 0x2000) { printk(KERN_INFO "Using r7780mp interrupt controller.\n"); register_intc_controller(&intc_desc); return irl2irq; diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7780rp.c b/arch/sh/boards/mach-highlander/irq-r7780rp.c index bd34048ed0e..0805b215145 100644 --- a/arch/sh/boards/renesas/r7780rp/irq-r7780rp.c +++ b/arch/sh/boards/mach-highlander/irq-r7780rp.c @@ -12,7 +12,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/io.h> -#include <asm/r7780rp.h> +#include <mach/highlander.h> enum { UNUSED = 0, @@ -55,9 +55,9 @@ static unsigned char irl2irq[HL_NR_IRL] __initdata = { static DECLARE_INTC_DESC(intc_desc, "r7780rp", vectors, NULL, mask_registers, NULL, NULL); -unsigned char * __init highlander_init_irq_r7780rp(void) +unsigned char * __init highlander_plat_irq_setup(void) { - if (ctrl_inw(0xa5000600)) { + if (__raw_readw(0xa5000600)) { printk(KERN_INFO "Using r7780rp interrupt controller.\n"); register_intc_controller(&intc_desc); return irl2irq; diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c b/arch/sh/boards/mach-highlander/irq-r7785rp.c index bf7ec107fbc..558b2486277 100644 --- a/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c +++ b/arch/sh/boards/mach-highlander/irq-r7785rp.c @@ -12,7 +12,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/io.h> -#include <asm/r7780rp.h> +#include <mach/highlander.h> enum { UNUSED = 0, @@ -64,22 +64,22 @@ static unsigned char irl2irq[HL_NR_IRL] __initdata = { static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors, NULL, mask_registers, NULL, NULL); -unsigned char * __init highlander_init_irq_r7785rp(void) +unsigned char * __init highlander_plat_irq_setup(void) { - if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000) + if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000) return NULL; printk(KERN_INFO "Using r7785rp interrupt controller.\n"); - ctrl_outw(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */ + __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */ /* Setup the FPGA IRL */ - ctrl_outw(0x0000, PA_IRLPRA); /* FPGA IRLA */ - ctrl_outw(0xe598, PA_IRLPRB); /* FPGA IRLB */ - ctrl_outw(0x7060, PA_IRLPRC); /* FPGA IRLC */ - ctrl_outw(0x0000, PA_IRLPRD); /* FPGA IRLD */ - ctrl_outw(0x4321, PA_IRLPRE); /* FPGA IRLE */ - ctrl_outw(0xdcba, PA_IRLPRF); /* FPGA IRLF */ + __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */ + __raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */ + __raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */ + __raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */ + __raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */ + __raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */ register_intc_controller(&intc_desc); return irl2irq; diff --git a/arch/sh/boards/mach-highlander/pinmux-r7785rp.c b/arch/sh/boards/mach-highlander/pinmux-r7785rp.c new file mode 100644 index 00000000000..c77a2bea8f2 --- /dev/null +++ b/arch/sh/boards/mach-highlander/pinmux-r7785rp.c @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2008 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/gpio.h> +#include <cpu/sh7785.h> + +void __init highlander_plat_pinmux_setup(void) +{ + /* SCIF0 */ + gpio_request(GPIO_FN_SCIF0_CTS, NULL); + gpio_request(GPIO_FN_SCIF0_RTS, NULL); + gpio_request(GPIO_FN_SCIF0_SCK, NULL); + gpio_request(GPIO_FN_SCIF0_RXD, NULL); + gpio_request(GPIO_FN_SCIF0_TXD, NULL); +} diff --git a/arch/sh/boards/renesas/r7780rp/psw.c b/arch/sh/boards/mach-highlander/psw.c index c844dfa5d58..522786318d3 100644 --- a/arch/sh/boards/renesas/r7780rp/psw.c +++ b/arch/sh/boards/mach-highlander/psw.c @@ -13,7 +13,7 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/platform_device.h> -#include <asm/mach/r7780rp.h> +#include <mach/highlander.h> #include <asm/push-switch.h> static irqreturn_t psw_irq_handler(int irq, void *arg) @@ -24,7 +24,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg) unsigned int l, mask; int ret = 0; - l = ctrl_inw(PA_DBSW); + l = __raw_readw(PA_DBSW); /* Nothing to do if there's no state change */ if (psw->state) { @@ -45,7 +45,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg) out: /* Clear the switch IRQs */ l |= (0x7 << 12); - ctrl_outw(l, PA_DBSW); + __raw_writew(l, PA_DBSW); return IRQ_RETVAL(ret); } diff --git a/arch/sh/boards/renesas/r7780rp/setup.c b/arch/sh/boards/mach-highlander/setup.c index 2f68bea7890..4a52590fe3d 100644 --- a/arch/sh/boards/renesas/r7780rp/setup.c +++ b/arch/sh/boards/mach-highlander/setup.c @@ -4,7 +4,7 @@ * Renesas Solutions Highlander Support. * * Copyright (C) 2002 Atom Create Engineering Co., Ltd. - * Copyright (C) 2005 - 2007 Paul Mundt + * Copyright (C) 2005 - 2008 Paul Mundt * * This contains support for the R7780RP-1, R7780MP, and R7785RP * Highlander modules. @@ -14,29 +14,40 @@ * for more details. */ #include <linux/init.h> +#include <linux/io.h> #include <linux/platform_device.h> #include <linux/ata_platform.h> #include <linux/types.h> +#include <linux/mtd/physmap.h> +#include <linux/i2c.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/usb/r8a66597.h> +#include <linux/usb/m66592.h> +#include <linux/clkdev.h> #include <net/ax88796.h> #include <asm/machvec.h> -#include <asm/r7780rp.h> +#include <mach/highlander.h> #include <asm/clock.h> #include <asm/heartbeat.h> #include <asm/io.h> #include <asm/io_trapped.h> +static struct r8a66597_platdata r8a66597_data = { + .xtal = R8A66597_PLATDATA_XTAL_12MHZ, + .vif = 1, +}; + static struct resource r8a66597_usb_host_resources[] = { [0] = { - .name = "r8a66597_hcd", .start = 0xA4200000, .end = 0xA42000FF, .flags = IORESOURCE_MEM, }, [1] = { - .name = "r8a66597_hcd", .start = IRQ_EXT1, /* irq number */ .end = IRQ_EXT1, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, }, }; @@ -46,11 +57,17 @@ static struct platform_device r8a66597_usb_host_device = { .dev = { .dma_mask = NULL, /* don't use dma */ .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, }, .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), .resource = r8a66597_usb_host_resources, }; +static struct m66592_platdata usbf_platdata = { + .xtal = M66592_PLATDATA_XTAL_24MHZ, + .vif = 1, +}; + static struct resource m66592_usb_peripheral_resources[] = { [0] = { .name = "m66592_udc", @@ -72,6 +89,7 @@ static struct platform_device m66592_usb_peripheral_device = { .dev = { .dma_mask = NULL, /* don't use dma */ .coherent_dma_mask = 0xffffffff, + .platform_data = &usbf_platdata, }, .num_resources = ARRAY_SIZE(m66592_usb_peripheral_resources), .resource = m66592_usb_peripheral_resources, @@ -176,11 +194,85 @@ static struct platform_device ax88796_device = { .resource = ax88796_resources, }; +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 4, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +/* This config is flash board for mass production. */ +static struct resource nor_flash_resources[] = { + [0] = { + .start = PA_NORFLASH_ADDR, + .end = PA_NORFLASH_ADDR + PA_NORFLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct resource smbus_resources[] = { + [0] = { + .start = PA_SMCR, + .end = PA_SMCR + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SMBUS, + .end = IRQ_SMBUS, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smbus_device = { + .name = "i2c-highlander", + .id = 0, + .num_resources = ARRAY_SIZE(smbus_resources), + .resource = smbus_resources, +}; + +static struct i2c_board_info __initdata highlander_i2c_devices[] = { + { + I2C_BOARD_INFO("r2025sd", 0x32), + }, +}; static struct platform_device *r7780rp_devices[] __initdata = { &r8a66597_usb_host_device, &m66592_usb_peripheral_device, &heartbeat_device, + &smbus_device, + &nor_flash_device, #ifndef CONFIG_SH_R7780RP &ax88796_device, #endif @@ -199,35 +291,43 @@ static struct trapped_io cf_trapped_io = { static int __init r7780rp_devices_setup(void) { + int ret = 0; + #ifndef CONFIG_SH_R7780RP if (register_trapped_io(&cf_trapped_io) == 0) - platform_device_register(&cf_ide_device); + ret |= platform_device_register(&cf_ide_device); #endif - return platform_add_devices(r7780rp_devices, + + ret |= platform_add_devices(r7780rp_devices, ARRAY_SIZE(r7780rp_devices)); + + ret |= i2c_register_board_info(0, highlander_i2c_devices, + ARRAY_SIZE(highlander_i2c_devices)); + + return ret; } device_initcall(r7780rp_devices_setup); /* * Platform specific clocks */ -static void ivdr_clk_enable(struct clk *clk) +static int ivdr_clk_enable(struct clk *clk) { - ctrl_outw(ctrl_inw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL); + __raw_writew(__raw_readw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL); + return 0; } static void ivdr_clk_disable(struct clk *clk) { - ctrl_outw(ctrl_inw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL); + __raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL); } -static struct clk_ops ivdr_clk_ops = { +static struct sh_clk_ops ivdr_clk_ops = { .enable = ivdr_clk_enable, .disable = ivdr_clk_disable, }; static struct clk ivdr_clk = { - .name = "ivdr_clk", .ops = &ivdr_clk_ops, }; @@ -235,10 +335,15 @@ static struct clk *r7780rp_clocks[] = { &ivdr_clk, }; +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("ivdr_clk", &ivdr_clk), +}; + static void r7780rp_power_off(void) { if (mach_is_r7780mp() || mach_is_r7785rp()) - ctrl_outw(0x0001, PA_POFF); + __raw_writew(0x0001, PA_POFF); } /* @@ -246,7 +351,7 @@ static void r7780rp_power_off(void) */ static void __init highlander_setup(char **cmdline_p) { - u16 ver = ctrl_inw(PA_VERREG); + u16 ver = __raw_readw(PA_VERREG); int i; printk(KERN_INFO "Renesas Solutions Highlander %s support.\n", @@ -259,6 +364,8 @@ static void __init highlander_setup(char **cmdline_p) (ver >> 12) & 0xf, (ver >> 8) & 0xf, (ver >> 4) & 0xf, ver & 0xf); + highlander_plat_pinmux_setup(); + /* * Enable the important clocks right away.. */ @@ -269,47 +376,31 @@ static void __init highlander_setup(char **cmdline_p) clk_enable(clk); } - ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */ + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + __raw_writew(0x0000, PA_OBLED); /* Clear LED. */ if (mach_is_r7780rp()) - ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */ + __raw_writew(0x0001, PA_SDPOW); /* SD Power ON */ - ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */ + __raw_writew(__raw_readw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */ pm_power_off = r7780rp_power_off; } static unsigned char irl2irq[HL_NR_IRL]; -int highlander_irq_demux(int irq) +static int highlander_irq_demux(int irq) { - if (irq >= HL_NR_IRL || !irl2irq[irq]) + if (irq >= HL_NR_IRL || irq < 0 || !irl2irq[irq]) return irq; return irl2irq[irq]; } -void __init highlander_init_irq(void) +static void __init highlander_init_irq(void) { - unsigned char *ucp = NULL; - - do { -#ifdef CONFIG_SH_R7780MP - ucp = highlander_init_irq_r7780mp(); - if (ucp) - break; -#endif -#ifdef CONFIG_SH_R7785RP - ucp = highlander_init_irq_r7785rp(); - if (ucp) - break; -#endif -#ifdef CONFIG_SH_R7780RP - ucp = highlander_init_irq_r7780rp(); - if (ucp) - break; -#endif - } while (0); + unsigned char *ucp = highlander_plat_irq_setup(); if (ucp) { plat_irq_setup_pins(IRQ_MODE_IRL3210); diff --git a/arch/sh/boards/hp6xx/Makefile b/arch/sh/boards/mach-hp6xx/Makefile index b3124278247..b3124278247 100644 --- a/arch/sh/boards/hp6xx/Makefile +++ b/arch/sh/boards/mach-hp6xx/Makefile diff --git a/arch/sh/boards/hp6xx/hp6xx_apm.c b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c index 177f4f028e0..865d8d6e823 100644 --- a/arch/sh/boards/hp6xx/hp6xx_apm.c +++ b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c @@ -14,7 +14,7 @@ #include <linux/apm-emulation.h> #include <linux/io.h> #include <asm/adc.h> -#include <asm/hp6xx.h> +#include <mach/hp6xx.h> /* percentage values */ #define APM_CRITICAL 10 @@ -53,7 +53,7 @@ static void hp6x0_apm_get_power_status(struct apm_power_info *info) info->ac_line_status = (battery > HP680_BATTERY_AC_ON) ? APM_AC_ONLINE : APM_AC_OFFLINE; - pgdr = ctrl_inb(PGDR); + pgdr = __raw_readb(PGDR); if (pgdr & PGDR_MAIN_BATTERY_OUT) { info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT; info->battery_flag = 0x80; @@ -86,7 +86,7 @@ static int __init hp6x0_apm_init(void) int ret; ret = request_irq(HP680_BTN_IRQ, hp6x0_apm_interrupt, - IRQF_DISABLED, MODNAME, NULL); + 0, MODNAME, NULL); if (unlikely(ret < 0)) { printk(KERN_ERR MODNAME ": IRQ %d request failed\n", HP680_BTN_IRQ); diff --git a/arch/sh/boards/mach-hp6xx/pm.c b/arch/sh/boards/mach-hp6xx/pm.c new file mode 100644 index 00000000000..8b50cf763c0 --- /dev/null +++ b/arch/sh/boards/mach-hp6xx/pm.c @@ -0,0 +1,158 @@ +/* + * hp6x0 Power Management Routines + * + * Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License. + */ +#include <linux/init.h> +#include <linux/suspend.h> +#include <linux/errno.h> +#include <linux/time.h> +#include <linux/delay.h> +#include <linux/gfp.h> +#include <asm/io.h> +#include <asm/hd64461.h> +#include <asm/bl_bit.h> +#include <mach/hp6xx.h> +#include <cpu/dac.h> +#include <asm/freq.h> +#include <asm/watchdog.h> + +#define INTR_OFFSET 0x600 + +#define STBCR 0xffffff82 +#define STBCR2 0xffffff88 + +#define STBCR_STBY 0x80 +#define STBCR_MSTP2 0x04 + +#define MCR 0xffffff68 +#define RTCNT 0xffffff70 + +#define MCR_RMODE 2 +#define MCR_RFSH 4 + +extern u8 wakeup_start; +extern u8 wakeup_end; + +static void pm_enter(void) +{ + u8 stbcr, csr; + u16 frqcr, mcr; + u32 vbr_new, vbr_old; + + set_bl_bit(); + + /* set wdt */ + csr = sh_wdt_read_csr(); + csr &= ~WTCSR_TME; + csr |= WTCSR_CKS_4096; + sh_wdt_write_csr(csr); + csr = sh_wdt_read_csr(); + sh_wdt_write_cnt(0); + + /* disable PLL1 */ + frqcr = __raw_readw(FRQCR); + frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY); + __raw_writew(frqcr, FRQCR); + + /* enable standby */ + stbcr = __raw_readb(STBCR); + __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR); + + /* set self-refresh */ + mcr = __raw_readw(MCR); + __raw_writew(mcr & ~MCR_RFSH, MCR); + + /* set interrupt handler */ + asm volatile("stc vbr, %0" : "=r" (vbr_old)); + vbr_new = get_zeroed_page(GFP_ATOMIC); + udelay(50); + memcpy((void*)(vbr_new + INTR_OFFSET), + &wakeup_start, &wakeup_end - &wakeup_start); + asm volatile("ldc %0, vbr" : : "r" (vbr_new)); + + __raw_writew(0, RTCNT); + __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR); + + cpu_sleep(); + + asm volatile("ldc %0, vbr" : : "r" (vbr_old)); + + free_page(vbr_new); + + /* enable PLL1 */ + frqcr = __raw_readw(FRQCR); + frqcr |= FRQCR_PSTBY; + __raw_writew(frqcr, FRQCR); + udelay(50); + frqcr |= FRQCR_PLLEN; + __raw_writew(frqcr, FRQCR); + + __raw_writeb(stbcr, STBCR); + + clear_bl_bit(); +} + +static int hp6x0_pm_enter(suspend_state_t state) +{ + u8 stbcr, stbcr2; +#ifdef CONFIG_HD64461_ENABLER + u8 scr; + u16 hd64461_stbcr; +#endif + +#ifdef CONFIG_HD64461_ENABLER + outb(0, HD64461_PCC1CSCIER); + + scr = inb(HD64461_PCC1SCR); + scr |= HD64461_PCCSCR_VCC1; + outb(scr, HD64461_PCC1SCR); + + hd64461_stbcr = inw(HD64461_STBCR); + hd64461_stbcr |= HD64461_STBCR_SPC1ST; + outw(hd64461_stbcr, HD64461_STBCR); +#endif + + __raw_writeb(0x1f, DACR); + + stbcr = __raw_readb(STBCR); + __raw_writeb(0x01, STBCR); + + stbcr2 = __raw_readb(STBCR2); + __raw_writeb(0x7f , STBCR2); + + outw(0xf07f, HD64461_SCPUCR); + + pm_enter(); + + outw(0, HD64461_SCPUCR); + __raw_writeb(stbcr, STBCR); + __raw_writeb(stbcr2, STBCR2); + +#ifdef CONFIG_HD64461_ENABLER + hd64461_stbcr = inw(HD64461_STBCR); + hd64461_stbcr &= ~HD64461_STBCR_SPC1ST; + outw(hd64461_stbcr, HD64461_STBCR); + + outb(0x4c, HD64461_PCC1CSCIER); + outb(0x00, HD64461_PCC1CSCR); +#endif + + return 0; +} + +static const struct platform_suspend_ops hp6x0_pm_ops = { + .enter = hp6x0_pm_enter, + .valid = suspend_valid_only_mem, +}; + +static int __init hp6x0_pm_init(void) +{ + suspend_set_ops(&hp6x0_pm_ops); + return 0; +} + +late_initcall(hp6x0_pm_init); diff --git a/arch/sh/boards/hp6xx/pm_wakeup.S b/arch/sh/boards/mach-hp6xx/pm_wakeup.S index 45e9bf0b911..4f18d44e054 100644 --- a/arch/sh/boards/hp6xx/pm_wakeup.S +++ b/arch/sh/boards/mach-hp6xx/pm_wakeup.S @@ -8,49 +8,34 @@ */ #include <linux/linkage.h> -#include <asm/cpu/mmu_context.h> - -#define k0 r0 -#define k1 r1 -#define k2 r2 -#define k3 r3 -#define k4 r4 +#include <cpu/mmu_context.h> /* * Kernel mode register usage: * k0 scratch * k1 scratch - * k2 scratch (Exception code) - * k3 scratch (Return address) - * k4 scratch - * k5 reserved - * k6 Global Interrupt Mask (0--15 << 4) - * k7 CURRENT_THREAD_INFO (pointer to current thread info) + * For more details, please have a look at entry.S */ +#define k0 r0 +#define k1 r1 + ENTRY(wakeup_start) ! clear STBY bit - mov #-126, k2 + mov #-126, k1 and #127, k0 - mov.b k0, @k2 + mov.b k0, @k1 ! enable refresh mov.l 5f, k1 mov.w 6f, k0 mov.w k0, @k1 ! jump to handler - mov.l 2f, k2 - mov.l 3f, k3 - mov.l @k2, k2 - mov.l 4f, k1 jmp @k1 - nop + nop .align 2 -1: .long EXPEVT -2: .long INTEVT -3: .long ret_from_irq -4: .long handle_exception +4: .long handle_interrupt 5: .long 0xffffff68 6: .word 0x0524 diff --git a/arch/sh/boards/hp6xx/setup.c b/arch/sh/boards/mach-hp6xx/setup.c index 2f414ac3c69..05797b33f68 100644 --- a/arch/sh/boards/hp6xx/setup.c +++ b/arch/sh/boards/mach-hp6xx/setup.c @@ -12,11 +12,13 @@ #include <linux/types.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/sh_intc.h> +#include <sound/sh_dac_audio.h> #include <asm/hd64461.h> #include <asm/io.h> -#include <asm/irq.h> -#include <asm/hp6xx.h> -#include <asm/cpu/dac.h> +#include <mach/hp6xx.h> +#include <cpu/dac.h> #define SCPCR 0xa4000116 #define SCPDR 0xa4000136 @@ -34,7 +36,7 @@ static struct resource cf_ide_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = 77, + .start = evt2irq(0xba0), .flags = IORESOURCE_IRQ, }, }; @@ -51,9 +53,63 @@ static struct platform_device jornadakbd_device = { .id = -1, }; +static void dac_audio_start(struct dac_audio_pdata *pdata) +{ + u16 v; + u8 v8; + + /* HP Jornada 680/690 speaker on */ + v = inw(HD64461_GPADR); + v &= ~HD64461_GPADR_SPEAKER; + outw(v, HD64461_GPADR); + + /* HP Palmtop 620lx/660lx speaker on */ + v8 = inb(PKDR); + v8 &= ~PKDR_SPEAKER; + outb(v8, PKDR); + + sh_dac_enable(pdata->channel); +} + +static void dac_audio_stop(struct dac_audio_pdata *pdata) +{ + u16 v; + u8 v8; + + /* HP Jornada 680/690 speaker off */ + v = inw(HD64461_GPADR); + v |= HD64461_GPADR_SPEAKER; + outw(v, HD64461_GPADR); + + /* HP Palmtop 620lx/660lx speaker off */ + v8 = inb(PKDR); + v8 |= PKDR_SPEAKER; + outb(v8, PKDR); + + sh_dac_output(0, pdata->channel); + sh_dac_disable(pdata->channel); +} + +static struct dac_audio_pdata dac_audio_platform_data = { + .buffer_size = 64000, + .channel = 1, + .start = dac_audio_start, + .stop = dac_audio_stop, +}; + +static struct platform_device dac_audio_device = { + .name = "dac_audio", + .id = -1, + .dev = { + .platform_data = &dac_audio_platform_data, + } + +}; + static struct platform_device *hp6xx_devices[] __initdata = { &cf_ide_device, &jornadakbd_device, + &dac_audio_device, }; static void __init hp6xx_init_irq(void) @@ -94,28 +150,25 @@ static void __init hp6xx_setup(char **cmdline_p) sh_dac_output(0, DAC_SPEAKER_VOLUME); sh_dac_disable(DAC_SPEAKER_VOLUME); - v8 = ctrl_inb(DACR); + v8 = __raw_readb(DACR); v8 &= ~DACR_DAE; - ctrl_outb(v8,DACR); + __raw_writeb(v8,DACR); - v8 = ctrl_inb(SCPDR); + v8 = __raw_readb(SCPDR); v8 |= SCPDR_TS_SCAN_X | SCPDR_TS_SCAN_Y; v8 &= ~SCPDR_TS_SCAN_ENABLE; - ctrl_outb(v8, SCPDR); + __raw_writeb(v8, SCPDR); - v = ctrl_inw(SCPCR); + v = __raw_readw(SCPCR); v &= ~SCPCR_TS_MASK; v |= SCPCR_TS_ENABLE; - ctrl_outw(v, SCPCR); + __raw_writew(v, SCPCR); } device_initcall(hp6xx_devices_setup); static struct sh_machine_vector mv_hp6xx __initmv = { .mv_name = "hp6xx", .mv_setup = hp6xx_setup, - /* IRQ's : CPU(64) + CCHIP(16) + FREE_TO_USE(6) */ - .mv_nr_irqs = HD64461_IRQBASE + HD64461_IRQ_NUM + 6, - .mv_irq_demux = hd64461_irq_demux, /* Enable IRQ0 -> IRQ3 in IRQ_MODE */ .mv_init_irq = hp6xx_init_irq, }; diff --git a/arch/sh/boards/mach-kfr2r09/Makefile b/arch/sh/boards/mach-kfr2r09/Makefile new file mode 100644 index 00000000000..60dd63f4a42 --- /dev/null +++ b/arch/sh/boards/mach-kfr2r09/Makefile @@ -0,0 +1,4 @@ +obj-y := setup.o sdram.o +ifneq ($(CONFIG_FB_SH_MOBILE_LCDC),) +obj-y += lcd_wqvga.o +endif diff --git a/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c new file mode 100644 index 00000000000..355a78a3b31 --- /dev/null +++ b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c @@ -0,0 +1,278 @@ +/* + * KFR2R09 LCD panel support + * + * Copyright (C) 2009 Magnus Damm + * + * Register settings based on the out-of-tree t33fb.c driver + * Copyright (C) 2008 Lineo Solutions, Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/fb.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/gpio.h> +#include <video/sh_mobile_lcdc.h> +#include <mach/kfr2r09.h> +#include <cpu/sh7724.h> + +/* The on-board LCD module is a Hitachi TX07D34VM0AAA. This module is made + * up of a 240x400 LCD hooked up to a R61517 driver IC. The driver IC is + * communicating with the main port of the LCDC using an 18-bit SYS interface. + * + * The device code for this LCD module is 0x01221517. + */ + +static const unsigned char data_frame_if[] = { + 0x02, /* WEMODE: 1=cont, 0=one-shot */ + 0x00, 0x00, + 0x00, /* EPF, DFM */ + 0x02, /* RIM[1] : 1 (18bpp) */ +}; + +static const unsigned char data_panel[] = { + 0x0b, + 0x63, /* 400 lines */ + 0x04, 0x00, 0x00, 0x04, 0x11, 0x00, 0x00, +}; + +static const unsigned char data_timing[] = { + 0x00, 0x00, 0x13, 0x08, 0x08, +}; + +static const unsigned char data_timing_src[] = { + 0x11, 0x01, 0x00, 0x01, +}; + +static const unsigned char data_gamma[] = { + 0x01, 0x02, 0x08, 0x23, 0x03, 0x0c, 0x00, 0x06, 0x00, 0x00, + 0x01, 0x00, 0x0c, 0x23, 0x03, 0x08, 0x02, 0x06, 0x00, 0x00, +}; + +static const unsigned char data_power[] = { + 0x07, 0xc5, 0xdc, 0x02, 0x33, 0x0a, +}; + +static unsigned long read_reg(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + return so->read_data(sohandle); +} + +static void write_reg(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so, + int i, unsigned long v) +{ + if (i) + so->write_data(sohandle, v); /* PTH4/LCDRS High [param, 17:0] */ + else + so->write_index(sohandle, v); /* PTH4/LCDRS Low [cmd, 7:0] */ +} + +static void write_data(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so, + unsigned char const *data, int no_data) +{ + int i; + + for (i = 0; i < no_data; i++) + write_reg(sohandle, so, 1, data[i]); +} + +static unsigned long read_device_code(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + unsigned long device_code; + + /* access protect OFF */ + write_reg(sohandle, so, 0, 0xb0); + write_reg(sohandle, so, 1, 0x00); + + /* deep standby OFF */ + write_reg(sohandle, so, 0, 0xb1); + write_reg(sohandle, so, 1, 0x00); + + /* device code command */ + write_reg(sohandle, so, 0, 0xbf); + mdelay(50); + + /* dummy read */ + read_reg(sohandle, so); + + /* read device code */ + device_code = ((read_reg(sohandle, so) & 0xff) << 24); + device_code |= ((read_reg(sohandle, so) & 0xff) << 16); + device_code |= ((read_reg(sohandle, so) & 0xff) << 8); + device_code |= (read_reg(sohandle, so) & 0xff); + + return device_code; +} + +static void write_memory_start(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + write_reg(sohandle, so, 0, 0x2c); +} + +static void clear_memory(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + int i; + + /* write start */ + write_memory_start(sohandle, so); + + /* paint it black */ + for (i = 0; i < (240 * 400); i++) + write_reg(sohandle, so, 1, 0x00); +} + +static void display_on(void *sohandle, + struct sh_mobile_lcdc_sys_bus_ops *so) +{ + /* access protect off */ + write_reg(sohandle, so, 0, 0xb0); + write_reg(sohandle, so, 1, 0x00); + + /* exit deep standby mode */ + write_reg(sohandle, so, 0, 0xb1); + write_reg(sohandle, so, 1, 0x00); + + /* frame memory I/F */ + write_reg(sohandle, so, 0, 0xb3); + write_data(sohandle, so, data_frame_if, ARRAY_SIZE(data_frame_if)); + + /* display mode and frame memory write mode */ + write_reg(sohandle, so, 0, 0xb4); + write_reg(sohandle, so, 1, 0x00); /* DBI, internal clock */ + + /* panel */ + write_reg(sohandle, so, 0, 0xc0); + write_data(sohandle, so, data_panel, ARRAY_SIZE(data_panel)); + + /* timing (normal) */ + write_reg(sohandle, so, 0, 0xc1); + write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing)); + + /* timing (partial) */ + write_reg(sohandle, so, 0, 0xc2); + write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing)); + + /* timing (idle) */ + write_reg(sohandle, so, 0, 0xc3); + write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing)); + + /* timing (source/VCOM/gate driving) */ + write_reg(sohandle, so, 0, 0xc4); + write_data(sohandle, so, data_timing_src, ARRAY_SIZE(data_timing_src)); + + /* gamma (red) */ + write_reg(sohandle, so, 0, 0xc8); + write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma)); + + /* gamma (green) */ + write_reg(sohandle, so, 0, 0xc9); + write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma)); + + /* gamma (blue) */ + write_reg(sohandle, so, 0, 0xca); + write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma)); + + /* power (common) */ + write_reg(sohandle, so, 0, 0xd0); + write_data(sohandle, so, data_power, ARRAY_SIZE(data_power)); + + /* VCOM */ + write_reg(sohandle, so, 0, 0xd1); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x0f); + write_reg(sohandle, so, 1, 0x02); + + /* power (normal) */ + write_reg(sohandle, so, 0, 0xd2); + write_reg(sohandle, so, 1, 0x63); + write_reg(sohandle, so, 1, 0x24); + + /* power (partial) */ + write_reg(sohandle, so, 0, 0xd3); + write_reg(sohandle, so, 1, 0x63); + write_reg(sohandle, so, 1, 0x24); + + /* power (idle) */ + write_reg(sohandle, so, 0, 0xd4); + write_reg(sohandle, so, 1, 0x63); + write_reg(sohandle, so, 1, 0x24); + + write_reg(sohandle, so, 0, 0xd8); + write_reg(sohandle, so, 1, 0x77); + write_reg(sohandle, so, 1, 0x77); + + /* TE signal */ + write_reg(sohandle, so, 0, 0x35); + write_reg(sohandle, so, 1, 0x00); + + /* TE signal line */ + write_reg(sohandle, so, 0, 0x44); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x00); + + /* column address */ + write_reg(sohandle, so, 0, 0x2a); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0xef); + + /* page address */ + write_reg(sohandle, so, 0, 0x2b); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x00); + write_reg(sohandle, so, 1, 0x01); + write_reg(sohandle, so, 1, 0x8f); + + /* exit sleep mode */ + write_reg(sohandle, so, 0, 0x11); + + mdelay(120); + + /* clear vram */ + clear_memory(sohandle, so); + + /* display ON */ + write_reg(sohandle, so, 0, 0x29); + mdelay(1); + + write_memory_start(sohandle, so); +} + +int kfr2r09_lcd_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so) +{ + /* power on */ + gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */ + gpio_set_value(GPIO_PTE4, 0); /* LCD_RST/ -> L */ + gpio_set_value(GPIO_PTF4, 1); /* PROTECT/ -> H */ + udelay(1100); + gpio_set_value(GPIO_PTE4, 1); /* LCD_RST/ -> H */ + udelay(10); + gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */ + mdelay(20); + + if (read_device_code(sohandle, so) != 0x01221517) + return -ENODEV; + + pr_info("KFR2R09 WQVGA LCD Module detected.\n"); + + display_on(sohandle, so); + return 0; +} + +void kfr2r09_lcd_start(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so) +{ + write_memory_start(sohandle, so); +} diff --git a/arch/sh/boards/mach-kfr2r09/sdram.S b/arch/sh/boards/mach-kfr2r09/sdram.S new file mode 100644 index 00000000000..0c9f55bec2f --- /dev/null +++ b/arch/sh/boards/mach-kfr2r09/sdram.S @@ -0,0 +1,80 @@ +/* + * KFR2R09 sdram self/auto-refresh setup code + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/sys.h> +#include <linux/errno.h> +#include <linux/linkage.h> +#include <asm/asm-offsets.h> +#include <asm/suspend.h> +#include <asm/romimage-macros.h> + +/* code to enter and leave self-refresh. must be self-contained. + * this code will be copied to on-chip memory and executed from there. + */ + .balign 4 +ENTRY(kfr2r09_sdram_enter_start) + + /* DBSC: put memory in self-refresh mode */ + + ED 0xFD000010, 0x00000000 /* DBEN */ + ED 0xFD000040, 0x00000000 /* DBRFPDN0 */ + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000040, 0x00000001 /* DBRFPDN0 */ + + rts + nop + +ENTRY(kfr2r09_sdram_enter_end) + + .balign 4 +ENTRY(kfr2r09_sdram_leave_start) + + /* DBSC: put memory in auto-refresh mode */ + + mov.l @(SH_SLEEP_MODE, r5), r0 + tst #SUSP_SH_RSTANDBY, r0 + bf resume_rstandby + + ED 0xFD000040, 0x00000000 /* DBRFPDN0 */ + WAIT 1 + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000010, 0x00000001 /* DBEN */ + ED 0xFD000040, 0x00010000 /* DBRFPDN0 */ + + rts + nop + +resume_rstandby: + + /* DBSC: re-initialize and put in auto-refresh */ + + ED 0xFD000108, 0x40000301 /* DBPDCNT0 */ + ED 0xFD000020, 0x011B0002 /* DBCONF */ + ED 0xFD000030, 0x03060E02 /* DBTR0 */ + ED 0xFD000034, 0x01020102 /* DBTR1 */ + ED 0xFD000038, 0x01090406 /* DBTR2 */ + ED 0xFD000008, 0x00000004 /* DBKIND */ + ED 0xFD000040, 0x00000001 /* DBRFPDN0 */ + ED 0xFD000040, 0x00000000 /* DBRFPDN0 */ + ED 0xFD000018, 0x00000001 /* DBCKECNT */ + WAIT 1 + ED 0xFD000010, 0x00000001 /* DBEN */ + ED 0xFD000044, 0x000004AF /* DBRFPDN1 */ + ED 0xFD000048, 0x20CF0037 /* DBRFPDN2 */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000108, 0x40000300 /* DBPDCNT0 */ + ED 0xFD000040, 0x00010000 /* DBRFPDN0 */ + + rts + nop + +ENTRY(kfr2r09_sdram_leave_end) diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c new file mode 100644 index 00000000000..1df4398f837 --- /dev/null +++ b/arch/sh/boards/mach-kfr2r09/setup.c @@ -0,0 +1,661 @@ +/* + * KFR2R09 board support code + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> +#include <linux/mfd/tmio.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/onenand.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/input/sh_keysc.h> +#include <linux/i2c.h> +#include <linux/platform_data/lv5207lp.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/usb/r8a66597.h> +#include <linux/videodev2.h> +#include <linux/sh_intc.h> +#include <media/rj54n1cb0c.h> +#include <media/soc_camera.h> +#include <media/sh_mobile_ceu.h> +#include <video/sh_mobile_lcdc.h> +#include <asm/suspend.h> +#include <asm/clock.h> +#include <asm/machvec.h> +#include <asm/io.h> +#include <cpu/sh7724.h> +#include <mach/kfr2r09.h> + +static struct mtd_partition kfr2r09_nor_flash_partitions[] = +{ + { + .name = "boot", + .offset = 0, + .size = (4 * 1024 * 1024), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, + { + .name = "other", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data kfr2r09_nor_flash_data = { + .width = 2, + .parts = kfr2r09_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(kfr2r09_nor_flash_partitions), +}; + +static struct resource kfr2r09_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x03ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device kfr2r09_nor_flash_device = { + .name = "physmap-flash", + .resource = kfr2r09_nor_flash_resources, + .num_resources = ARRAY_SIZE(kfr2r09_nor_flash_resources), + .dev = { + .platform_data = &kfr2r09_nor_flash_data, + }, +}; + +static struct resource kfr2r09_nand_flash_resources[] = { + [0] = { + .name = "NAND Flash", + .start = 0x10000000, + .end = 0x1001ffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device kfr2r09_nand_flash_device = { + .name = "onenand-flash", + .resource = kfr2r09_nand_flash_resources, + .num_resources = ARRAY_SIZE(kfr2r09_nand_flash_resources), +}; + +static struct sh_keysc_info kfr2r09_sh_keysc_info = { + .mode = SH_KEYSC_MODE_1, /* KEYOUT0->4, KEYIN0->4 */ + .scan_timing = 3, + .delay = 10, + .keycodes = { + KEY_PHONE, KEY_CLEAR, KEY_MAIL, KEY_WWW, KEY_ENTER, + KEY_1, KEY_2, KEY_3, 0, KEY_UP, + KEY_4, KEY_5, KEY_6, 0, KEY_LEFT, + KEY_7, KEY_8, KEY_9, KEY_PROG1, KEY_RIGHT, + KEY_S, KEY_0, KEY_P, KEY_PROG2, KEY_DOWN, + 0, 0, 0, 0, 0 + }, +}; + +static struct resource kfr2r09_sh_keysc_resources[] = { + [0] = { + .name = "KEYSC", + .start = 0x044b0000, + .end = 0x044b000f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xbe0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kfr2r09_sh_keysc_device = { + .name = "sh_keysc", + .id = 0, /* "keysc0" clock */ + .num_resources = ARRAY_SIZE(kfr2r09_sh_keysc_resources), + .resource = kfr2r09_sh_keysc_resources, + .dev = { + .platform_data = &kfr2r09_sh_keysc_info, + }, +}; + +static const struct fb_videomode kfr2r09_lcdc_modes[] = { + { + .name = "TX07D34VM0AAA", + .xres = 240, + .yres = 400, + .left_margin = 0, + .right_margin = 16, + .hsync_len = 8, + .upper_margin = 0, + .lower_margin = 1, + .vsync_len = 1, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + }, +}; + +static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = { + .clock_source = LCDC_CLK_BUS, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .fourcc = V4L2_PIX_FMT_RGB565, + .interface_type = SYS18, + .clock_divider = 6, + .flags = LCDC_FLAGS_DWPOL, + .lcd_modes = kfr2r09_lcdc_modes, + .num_modes = ARRAY_SIZE(kfr2r09_lcdc_modes), + .panel_cfg = { + .width = 35, + .height = 58, + .setup_sys = kfr2r09_lcd_setup, + .start_transfer = kfr2r09_lcd_start, + }, + .sys_bus_cfg = { + .ldmt2r = 0x07010904, + .ldmt3r = 0x14012914, + /* set 1s delay to encourage fsync() */ + .deferred_io_msec = 1000, + }, + } +}; + +static struct resource kfr2r09_sh_lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, /* P4-only space */ + .end = 0xfe942fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xf40), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kfr2r09_sh_lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(kfr2r09_sh_lcdc_resources), + .resource = kfr2r09_sh_lcdc_resources, + .dev = { + .platform_data = &kfr2r09_sh_lcdc_info, + }, +}; + +static struct lv5207lp_platform_data kfr2r09_backlight_data = { + .fbdev = &kfr2r09_sh_lcdc_device.dev, + .def_value = 13, + .max_value = 13, +}; + +static struct i2c_board_info kfr2r09_backlight_board_info = { + I2C_BOARD_INFO("lv5207lp", 0x75), + .platform_data = &kfr2r09_backlight_data, +}; + +static struct r8a66597_platdata kfr2r09_usb0_gadget_data = { + .on_chip = 1, +}; + +static struct resource kfr2r09_usb0_gadget_resources[] = { + [0] = { + .start = 0x04d80000, + .end = 0x04d80123, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device kfr2r09_usb0_gadget_device = { + .name = "r8a66597_udc", + .id = 0, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &kfr2r09_usb0_gadget_data, + }, + .num_resources = ARRAY_SIZE(kfr2r09_usb0_gadget_resources), + .resource = kfr2r09_usb0_gadget_resources, +}; + +static struct sh_mobile_ceu_info sh_mobile_ceu_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource kfr2r09_ceu_resources[] = { + [0] = { + .name = "CEU", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x880), + .end = evt2irq(0x880), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device kfr2r09_ceu_device = { + .name = "sh_mobile_ceu", + .id = 0, /* "ceu0" clock */ + .num_resources = ARRAY_SIZE(kfr2r09_ceu_resources), + .resource = kfr2r09_ceu_resources, + .dev = { + .platform_data = &sh_mobile_ceu_info, + }, +}; + +static struct i2c_board_info kfr2r09_i2c_camera = { + I2C_BOARD_INFO("rj54n1cb0c", 0x50), +}; + +static struct clk *camera_clk; + +/* set VIO_CKO clock to 25MHz */ +#define CEU_MCLK_FREQ 25000000 + +#define DRVCRB 0xA405018C +static int camera_power(struct device *dev, int mode) +{ + int ret; + + if (mode) { + long rate; + + camera_clk = clk_get(NULL, "video_clk"); + if (IS_ERR(camera_clk)) + return PTR_ERR(camera_clk); + + rate = clk_round_rate(camera_clk, CEU_MCLK_FREQ); + ret = clk_set_rate(camera_clk, rate); + if (ret < 0) + goto eclkrate; + + /* set DRVCRB + * + * use 1.8 V for VccQ_VIO + * use 2.85V for VccQ_SR + */ + __raw_writew((__raw_readw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB); + + /* reset clear */ + ret = gpio_request(GPIO_PTB4, NULL); + if (ret < 0) + goto eptb4; + ret = gpio_request(GPIO_PTB7, NULL); + if (ret < 0) + goto eptb7; + + ret = gpio_direction_output(GPIO_PTB4, 1); + if (!ret) + ret = gpio_direction_output(GPIO_PTB7, 1); + if (ret < 0) + goto egpioout; + msleep(1); + + ret = clk_enable(camera_clk); /* start VIO_CKO */ + if (ret < 0) + goto eclkon; + + return 0; + } + + ret = 0; + + clk_disable(camera_clk); +eclkon: + gpio_set_value(GPIO_PTB7, 0); +egpioout: + gpio_set_value(GPIO_PTB4, 0); + gpio_free(GPIO_PTB7); +eptb7: + gpio_free(GPIO_PTB4); +eptb4: +eclkrate: + clk_put(camera_clk); + return ret; +} + +static struct rj54n1_pdata rj54n1_priv = { + .mclk_freq = CEU_MCLK_FREQ, + .ioctl_high = false, +}; + +static struct soc_camera_link rj54n1_link = { + .power = camera_power, + .board_info = &kfr2r09_i2c_camera, + .i2c_adapter_id = 1, + .priv = &rj54n1_priv, +}; + +static struct platform_device kfr2r09_camera = { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &rj54n1_link, + }, +}; + +/* Fixed 3.3V regulator to be used by SDHI0 */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +}; + +static struct resource kfr2r09_sh_sdhi0_resources[] = { + [0] = { + .name = "SDHI0", + .start = 0x04ce0000, + .end = 0x04ce00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xe80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mobile_sdhi_info sh7724_sdhi0_data = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, + .tmio_caps = MMC_CAP_SDIO_IRQ, +}; + +static struct platform_device kfr2r09_sh_sdhi0_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(kfr2r09_sh_sdhi0_resources), + .resource = kfr2r09_sh_sdhi0_resources, + .dev = { + .platform_data = &sh7724_sdhi0_data, + }, +}; + +static struct platform_device *kfr2r09_devices[] __initdata = { + &kfr2r09_nor_flash_device, + &kfr2r09_nand_flash_device, + &kfr2r09_sh_keysc_device, + &kfr2r09_sh_lcdc_device, + &kfr2r09_ceu_device, + &kfr2r09_camera, + &kfr2r09_sh_sdhi0_device, +}; + +#define BSC_CS0BCR 0xfec10004 +#define BSC_CS0WCR 0xfec10024 +#define BSC_CS4BCR 0xfec10010 +#define BSC_CS4WCR 0xfec10030 +#define PORT_MSELCRB 0xa4050182 + +#ifdef CONFIG_I2C +static int kfr2r09_usb0_gadget_i2c_setup(void) +{ + struct i2c_adapter *a; + struct i2c_msg msg; + unsigned char buf[2]; + int ret; + + a = i2c_get_adapter(0); + if (!a) + return -ENODEV; + + /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */ + buf[0] = 0x13; + msg.addr = 0x09; + msg.buf = buf; + msg.len = 1; + msg.flags = 0; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + buf[0] = 0; + msg.addr = 0x09; + msg.buf = buf; + msg.len = 1; + msg.flags = I2C_M_RD; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + buf[1] = buf[0] | (1 << 1); + buf[0] = 0x13; + msg.addr = 0x09; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + return 0; +} + +static int kfr2r09_serial_i2c_setup(void) +{ + struct i2c_adapter *a; + struct i2c_msg msg; + unsigned char buf[2]; + int ret; + + a = i2c_get_adapter(0); + if (!a) + return -ENODEV; + + /* set bit 6 (the 7th bit) of chip at 0x09, register 0x13 */ + buf[0] = 0x13; + msg.addr = 0x09; + msg.buf = buf; + msg.len = 1; + msg.flags = 0; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + buf[0] = 0; + msg.addr = 0x09; + msg.buf = buf; + msg.len = 1; + msg.flags = I2C_M_RD; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + buf[1] = buf[0] | (1 << 6); + buf[0] = 0x13; + msg.addr = 0x09; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + ret = i2c_transfer(a, &msg, 1); + if (ret != 1) + return -ENODEV; + + return 0; +} +#else +static int kfr2r09_usb0_gadget_i2c_setup(void) +{ + return -ENODEV; +} + +static int kfr2r09_serial_i2c_setup(void) +{ + return -ENODEV; +} +#endif + +static int kfr2r09_usb0_gadget_setup(void) +{ + int plugged_in; + + gpio_request(GPIO_PTN4, NULL); /* USB_DET */ + gpio_direction_input(GPIO_PTN4); + plugged_in = gpio_get_value(GPIO_PTN4); + if (!plugged_in) + return -ENODEV; /* no cable plugged in */ + + if (kfr2r09_usb0_gadget_i2c_setup() != 0) + return -ENODEV; /* unable to configure using i2c */ + + __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); + gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */ + gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */ + gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */ + msleep(20); /* wait 20ms to let the clock settle */ + clk_enable(clk_get(NULL, "usb0")); + __raw_writew(0x0600, 0xa40501d4); + + return 0; +} + +extern char kfr2r09_sdram_enter_start; +extern char kfr2r09_sdram_enter_end; +extern char kfr2r09_sdram_leave_start; +extern char kfr2r09_sdram_leave_end; + +static int __init kfr2r09_devices_setup(void) +{ + /* register board specific self-refresh code */ + sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | + SUSP_SH_RSTANDBY, + &kfr2r09_sdram_enter_start, + &kfr2r09_sdram_enter_end, + &kfr2r09_sdram_leave_start, + &kfr2r09_sdram_leave_end); + + regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + + /* enable SCIF1 serial port for YC401 console support */ + gpio_request(GPIO_FN_SCIF1_RXD, NULL); + gpio_request(GPIO_FN_SCIF1_TXD, NULL); + kfr2r09_serial_i2c_setup(); /* ECONTMSK(bit6=L10ONEN) set 1 */ + gpio_request(GPIO_PTG3, NULL); /* HPON_ON */ + gpio_direction_output(GPIO_PTG3, 1); /* HPON_ON = H */ + + /* setup NOR flash at CS0 */ + __raw_writel(0x36db0400, BSC_CS0BCR); + __raw_writel(0x00000500, BSC_CS0WCR); + + /* setup NAND flash at CS4 */ + __raw_writel(0x36db0400, BSC_CS4BCR); + __raw_writel(0x00000500, BSC_CS4WCR); + + /* setup KEYSC pins */ + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); + gpio_request(GPIO_FN_KEYIN0, NULL); + gpio_request(GPIO_FN_KEYIN1, NULL); + gpio_request(GPIO_FN_KEYIN2, NULL); + gpio_request(GPIO_FN_KEYIN3, NULL); + gpio_request(GPIO_FN_KEYIN4, NULL); + gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); + + /* setup LCDC pins for SYS panel */ + gpio_request(GPIO_FN_LCDD17, NULL); + gpio_request(GPIO_FN_LCDD16, NULL); + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDRS, NULL); /* LCD_RS */ + gpio_request(GPIO_FN_LCDCS, NULL); /* LCD_CS/ */ + gpio_request(GPIO_FN_LCDRD, NULL); /* LCD_RD/ */ + gpio_request(GPIO_FN_LCDWR, NULL); /* LCD_WR/ */ + gpio_request(GPIO_FN_LCDVSYN, NULL); /* LCD_VSYNC */ + gpio_request(GPIO_PTE4, NULL); /* LCD_RST/ */ + gpio_direction_output(GPIO_PTE4, 1); + gpio_request(GPIO_PTF4, NULL); /* PROTECT/ */ + gpio_direction_output(GPIO_PTF4, 1); + gpio_request(GPIO_PTU0, NULL); /* LEDSTDBY/ */ + gpio_direction_output(GPIO_PTU0, 1); + + /* setup USB function */ + if (kfr2r09_usb0_gadget_setup() == 0) + platform_device_register(&kfr2r09_usb0_gadget_device); + + /* CEU */ + gpio_request(GPIO_FN_VIO_CKO, NULL); + gpio_request(GPIO_FN_VIO0_CLK, NULL); + gpio_request(GPIO_FN_VIO0_VD, NULL); + gpio_request(GPIO_FN_VIO0_HD, NULL); + gpio_request(GPIO_FN_VIO0_FLD, NULL); + gpio_request(GPIO_FN_VIO0_D7, NULL); + gpio_request(GPIO_FN_VIO0_D6, NULL); + gpio_request(GPIO_FN_VIO0_D5, NULL); + gpio_request(GPIO_FN_VIO0_D4, NULL); + gpio_request(GPIO_FN_VIO0_D3, NULL); + gpio_request(GPIO_FN_VIO0_D2, NULL); + gpio_request(GPIO_FN_VIO0_D1, NULL); + gpio_request(GPIO_FN_VIO0_D0, NULL); + + platform_resource_setup_memory(&kfr2r09_ceu_device, "ceu", 4 << 20); + + /* SDHI0 connected to yc304 */ + gpio_request(GPIO_FN_SDHI0CD, NULL); + gpio_request(GPIO_FN_SDHI0D3, NULL); + gpio_request(GPIO_FN_SDHI0D2, NULL); + gpio_request(GPIO_FN_SDHI0D1, NULL); + gpio_request(GPIO_FN_SDHI0D0, NULL); + gpio_request(GPIO_FN_SDHI0CMD, NULL); + gpio_request(GPIO_FN_SDHI0CLK, NULL); + + i2c_register_board_info(0, &kfr2r09_backlight_board_info, 1); + + return platform_add_devices(kfr2r09_devices, + ARRAY_SIZE(kfr2r09_devices)); +} +device_initcall(kfr2r09_devices_setup); + +/* Return the board specific boot mode pin configuration */ +static int kfr2r09_mode_pins(void) +{ + /* MD0=1, MD1=1, MD2=0: Clock Mode 3 + * MD3=0: 16-bit Area0 Bus Width + * MD5=1: Little Endian + * MD8=1: Test Mode Disabled + */ + return MODE_PIN0 | MODE_PIN1 | MODE_PIN5 | MODE_PIN8; +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_kfr2r09 __initmv = { + .mv_name = "kfr2r09", + .mv_mode_pins = kfr2r09_mode_pins, +}; diff --git a/arch/sh/boards/landisk/Makefile b/arch/sh/boards/mach-landisk/Makefile index a696b4277fa..a696b4277fa 100644 --- a/arch/sh/boards/landisk/Makefile +++ b/arch/sh/boards/mach-landisk/Makefile diff --git a/arch/sh/boards/landisk/gio.c b/arch/sh/boards/mach-landisk/gio.c index 17025080db3..8132dff078f 100644 --- a/arch/sh/boards/landisk/gio.c +++ b/arch/sh/boards/mach-landisk/gio.c @@ -19,8 +19,8 @@ #include <linux/fs.h> #include <asm/io.h> #include <asm/uaccess.h> -#include <asm/landisk/gio.h> -#include <asm/landisk/iodata_landisk.h> +#include <mach-landisk/mach/gio.h> +#include <mach-landisk/mach/iodata_landisk.h> #define DEVCOUNT 4 #define GIO_MINOR 2 /* GIO minor no. */ @@ -32,17 +32,20 @@ static int openCnt; static int gio_open(struct inode *inode, struct file *filp) { int minor; + int ret = -ENOENT; + preempt_disable(); minor = MINOR(inode->i_rdev); if (minor < DEVCOUNT) { if (openCnt > 0) { - return -EALREADY; + ret = -EALREADY; } else { openCnt++; - return 0; + ret = 0; } } - return -ENOENT; + preempt_enable(); + return ret; } static int gio_close(struct inode *inode, struct file *filp) @@ -56,8 +59,7 @@ static int gio_close(struct inode *inode, struct file *filp) return 0; } -static int gio_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) +static long gio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { unsigned int data; static unsigned int addr = 0; @@ -74,39 +76,39 @@ static int gio_ioctl(struct inode *inode, struct file *filp, break; case GIODRV_IOCSGIODATA1: /* write byte */ - ctrl_outb((unsigned char)(0x0ff & data), addr); + __raw_writeb((unsigned char)(0x0ff & data), addr); break; case GIODRV_IOCSGIODATA2: /* write word */ if (addr & 0x01) { return -EFAULT; } - ctrl_outw((unsigned short int)(0x0ffff & data), addr); + __raw_writew((unsigned short int)(0x0ffff & data), addr); break; case GIODRV_IOCSGIODATA4: /* write long */ if (addr & 0x03) { return -EFAULT; } - ctrl_outl(data, addr); + __raw_writel(data, addr); break; case GIODRV_IOCGGIODATA1: /* read byte */ - data = ctrl_inb(addr); + data = __raw_readb(addr); break; case GIODRV_IOCGGIODATA2: /* read word */ if (addr & 0x01) { return -EFAULT; } - data = ctrl_inw(addr); + data = __raw_readw(addr); break; case GIODRV_IOCGGIODATA4: /* read long */ if (addr & 0x03) { return -EFAULT; } - data = ctrl_inl(addr); + data = __raw_readl(addr); break; default: return -EFAULT; @@ -125,7 +127,8 @@ static const struct file_operations gio_fops = { .owner = THIS_MODULE, .open = gio_open, /* open */ .release = gio_close, /* release */ - .ioctl = gio_ioctl, /* ioctl */ + .unlocked_ioctl = gio_ioctl, + .llseek = noop_llseek, }; static int __init gio_init(void) diff --git a/arch/sh/boards/mach-landisk/irq.c b/arch/sh/boards/mach-landisk/irq.c new file mode 100644 index 00000000000..c00ace38db3 --- /dev/null +++ b/arch/sh/boards/mach-landisk/irq.c @@ -0,0 +1,66 @@ +/* + * arch/sh/boards/mach-landisk/irq.c + * + * I-O DATA Device, Inc. LANDISK Support + * + * Copyright (C) 2005-2007 kogiidena + * Copyright (C) 2011 Nobuhiro Iwamatsu + * + * Copyright (C) 2001 Ian da Silva, Jeremy Siegel + * Based largely on io_se.c. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <mach-landisk/mach/iodata_landisk.h> + +enum { + UNUSED = 0, + + PCI_INTA, /* PCI int A */ + PCI_INTB, /* PCI int B */ + PCI_INTC, /* PCI int C */ + PCI_INTD, /* PCI int D */ + ATA, /* ATA */ + FATA, /* CF */ + POWER, /* Power swtich */ + BUTTON, /* Button swtich */ +}; + +/* Vectors for LANDISK */ +static struct intc_vect vectors_landisk[] __initdata = { + INTC_IRQ(PCI_INTA, IRQ_PCIINTA), + INTC_IRQ(PCI_INTB, IRQ_PCIINTB), + INTC_IRQ(PCI_INTC, IRQ_PCIINTC), + INTC_IRQ(PCI_INTD, IRQ_PCIINTD), + INTC_IRQ(ATA, IRQ_ATA), + INTC_IRQ(FATA, IRQ_FATA), + INTC_IRQ(POWER, IRQ_POWER), + INTC_IRQ(BUTTON, IRQ_BUTTON), +}; + +/* IRLMSK mask register layout for LANDISK */ +static struct intc_mask_reg mask_registers_landisk[] __initdata = { + { PA_IMASK, 0, 8, /* IRLMSK */ + { BUTTON, POWER, FATA, ATA, + PCI_INTD, PCI_INTC, PCI_INTB, PCI_INTA, + } + }, +}; + +static DECLARE_INTC_DESC(intc_desc_landisk, "landisk", vectors_landisk, NULL, + mask_registers_landisk, NULL, NULL); +/* + * Initialize IRQ setting + */ +void __init init_landisk_IRQ(void) +{ + register_intc_controller(&intc_desc_landisk); + __raw_writeb(0x00, PA_PWRINT_CLR); +} diff --git a/arch/sh/boards/landisk/psw.c b/arch/sh/boards/mach-landisk/psw.c index 5a9b70b5dec..bef83522f95 100644 --- a/arch/sh/boards/landisk/psw.c +++ b/arch/sh/boards/mach-landisk/psw.c @@ -14,7 +14,7 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/platform_device.h> -#include <asm/landisk/iodata_landisk.h> +#include <mach-landisk/mach/iodata_landisk.h> #include <asm/push-switch.h> static irqreturn_t psw_irq_handler(int irq, void *arg) @@ -25,7 +25,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg) unsigned int sw_value; int ret = 0; - sw_value = (0x0ff & (~ctrl_inb(PA_STATUS))); + sw_value = (0x0ff & (~__raw_readb(PA_STATUS))); /* Nothing to do if there's no state change */ if (psw->state) { @@ -42,7 +42,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg) out: /* Clear the switch IRQs */ - ctrl_outb(0x00, PA_PWRINT_CLR); + __raw_writeb(0x00, PA_PWRINT_CLR); return IRQ_RETVAL(ret); } diff --git a/arch/sh/boards/landisk/setup.c b/arch/sh/boards/mach-landisk/setup.c index 2b708ec7255..f1147caebac 100644 --- a/arch/sh/boards/landisk/setup.c +++ b/arch/sh/boards/mach-landisk/setup.c @@ -18,14 +18,12 @@ #include <linux/pm.h> #include <linux/mm.h> #include <asm/machvec.h> -#include <asm/landisk/iodata_landisk.h> +#include <mach-landisk/mach/iodata_landisk.h> #include <asm/io.h> -void init_landisk_IRQ(void); - static void landisk_power_off(void) { - ctrl_outb(0x01, PA_SHUTDOWN); + __raw_writeb(0x01, PA_SHUTDOWN); } static struct resource cf_ide_resources[3]; @@ -63,7 +61,7 @@ static int __init landisk_devices_setup(void) /* open I/O area window */ paddrbase = virt_to_phys((void *)PA_AREA5_IO); prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16); - cf_ide_base = p3_ioremap(paddrbase, PAGE_SIZE, prot.pgprot); + cf_ide_base = ioremap_prot(paddrbase, PAGE_SIZE, pgprot_val(prot)); if (!cf_ide_base) { printk("allocate_cf_area : can't open CF I/O window!\n"); return -ENOMEM; @@ -83,12 +81,12 @@ static int __init landisk_devices_setup(void) ARRAY_SIZE(landisk_devices)); } -__initcall(landisk_devices_setup); +device_initcall(landisk_devices_setup); static void __init landisk_setup(char **cmdline_p) { - /* LED ON */ - ctrl_outb(ctrl_inb(PA_LED) | 0x03, PA_LED); + /* LED ON */ + __raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED); printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n"); pm_power_off = landisk_power_off; @@ -99,7 +97,6 @@ static void __init landisk_setup(char **cmdline_p) */ static struct sh_machine_vector mv_landisk __initmv = { .mv_name = "LANDISK", - .mv_nr_irqs = 72, .mv_setup = landisk_setup, .mv_init_irq = init_landisk_IRQ, }; diff --git a/arch/sh/boards/lboxre2/Makefile b/arch/sh/boards/mach-lboxre2/Makefile index e9ed140c06f..e9ed140c06f 100644 --- a/arch/sh/boards/lboxre2/Makefile +++ b/arch/sh/boards/mach-lboxre2/Makefile diff --git a/arch/sh/boards/lboxre2/irq.c b/arch/sh/boards/mach-lboxre2/irq.c index 5a1c3bbe7b5..8aa171ab833 100644 --- a/arch/sh/boards/lboxre2/irq.c +++ b/arch/sh/boards/mach-lboxre2/irq.c @@ -15,7 +15,7 @@ #include <linux/irq.h> #include <asm/irq.h> #include <asm/io.h> -#include <asm/lboxre2.h> +#include <mach/lboxre2.h> /* * Initialize IRQ setting diff --git a/arch/sh/boards/lboxre2/setup.c b/arch/sh/boards/mach-lboxre2/setup.c index c74440d38ee..6660622aa45 100644 --- a/arch/sh/boards/lboxre2/setup.c +++ b/arch/sh/boards/mach-lboxre2/setup.c @@ -16,7 +16,7 @@ #include <linux/ata_platform.h> #include <asm/machvec.h> #include <asm/addrspace.h> -#include <asm/lboxre2.h> +#include <mach/lboxre2.h> #include <asm/io.h> static struct resource cf_ide_resources[] = { @@ -56,8 +56,8 @@ static int __init lboxre2_devices_setup(void) /* open I/O area window */ paddrbase = virt_to_phys((void*)PA_AREA5_IO); psize = PAGE_SIZE; - prot = PAGE_KERNEL_PCC( 1 , _PAGE_PCC_IO16); - cf0_io_base = (u32)p3_ioremap(paddrbase, psize, prot.pgprot); + prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16); + cf0_io_base = (u32)ioremap_prot(paddrbase, psize, pgprot_val(prot)); if (!cf0_io_base) { printk(KERN_ERR "%s : can't open CF I/O window!\n" , __func__ ); return -ENOMEM; @@ -79,6 +79,5 @@ device_initcall(lboxre2_devices_setup); */ static struct sh_machine_vector mv_lboxre2 __initmv = { .mv_name = "L-BOX RE2", - .mv_nr_irqs = 72, .mv_init_irq = init_lboxre2_IRQ, }; diff --git a/arch/sh/boards/superh/microdev/Makefile b/arch/sh/boards/mach-microdev/Makefile index 1387dd6c85e..4e3588e8806 100644 --- a/arch/sh/boards/superh/microdev/Makefile +++ b/arch/sh/boards/mach-microdev/Makefile @@ -2,7 +2,4 @@ # Makefile for the SuperH MicroDev specific parts of the kernel # -obj-y := setup.o irq.o io.o - -obj-$(CONFIG_HEARTBEAT) += led.o - +obj-y := setup.o irq.o io.o fdc37c93xapm.o diff --git a/arch/sh/boards/mach-microdev/fdc37c93xapm.c b/arch/sh/boards/mach-microdev/fdc37c93xapm.c new file mode 100644 index 00000000000..458a7cf5fb4 --- /dev/null +++ b/arch/sh/boards/mach-microdev/fdc37c93xapm.c @@ -0,0 +1,160 @@ +/* + * + * Setup for the SMSC FDC37C93xAPM + * + * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) + * Copyright (C) 2003, 2004 SuperH, Inc. + * Copyright (C) 2004, 2005 Paul Mundt + * + * SuperH SH4-202 MicroDev board support. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + */ +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/io.h> +#include <linux/err.h> +#include <mach/microdev.h> + +#define SMSC_CONFIG_PORT_ADDR (0x3F0) +#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR +#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1) + +#define SMSC_ENTER_CONFIG_KEY 0x55 +#define SMSC_EXIT_CONFIG_KEY 0xaa + +#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */ +#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */ +#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */ +#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */ +#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */ +#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */ +#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */ +#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */ +#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */ +#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */ + +#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */ +#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */ +#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */ +#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */ +#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */ +#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */ +#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */ + +#define SMSC_READ_INDEXED(index) ({ \ + outb((index), SMSC_INDEX_PORT_ADDR); \ + inb(SMSC_DATA_PORT_ADDR); }) +#define SMSC_WRITE_INDEXED(val, index) ({ \ + outb((index), SMSC_INDEX_PORT_ADDR); \ + outb((val), SMSC_DATA_PORT_ADDR); }) + +#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */ +#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */ +#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */ +#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */ + +#define SERIAL1_PRIMARY_BASE 0x03f8 +#define SERIAL2_PRIMARY_BASE 0x02f8 + +#define MSB(x) ( (x) >> 8 ) +#define LSB(x) ( (x) & 0xff ) + + /* General-Purpose base address on CPU-board FPGA */ +#define MICRODEV_FPGA_GP_BASE 0xa6100000ul + +static int __init smsc_superio_setup(void) +{ + + unsigned char devid, devrev; + + /* Initially the chip is in run state */ + /* Put it into configuration state */ + outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); + + /* Read device ID info */ + devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX); + devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX); + + if ((devid == 0x30) && (devrev == 0x01)) + printk("SMSC FDC37C93xAPM SuperIO device detected\n"); + else + return -ENODEV; + + /* Select the keyboard device */ + SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* enable the interrupts */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX); + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX); + + /* Select the Serial #1 device */ + SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* program with port addresses */ + SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); + /* enable the interrupts */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX); + + /* Select the Serial #2 device */ + SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* program with port addresses */ + SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); + /* enable the interrupts */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX); + + /* Select the IDE#1 device */ + SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* program with port addresses */ + SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX); + SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX); + /* select the interrupt */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX); + + /* Select the IDE#2 device */ + SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX); + /* enable it */ + SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); + /* program with port addresses */ + SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); + SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); + SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); + /* select the interrupt */ + SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX); + + /* Select the configuration registers */ + SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX); + /* enable the appropriate GPIO pins for IDE functionality: + * bit[0] In/Out 1==input; 0==output + * bit[1] Polarity 1==invert; 0==no invert + * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable + * bit[3:4] Function Select 00==original; 01==Alternate Function #1 + */ + SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */ + SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */ + SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */ + SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */ + SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */ + + /* Exit the configuration state */ + outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); + + return 0; +} +device_initcall(smsc_superio_setup); diff --git a/arch/sh/boards/mach-microdev/io.c b/arch/sh/boards/mach-microdev/io.c new file mode 100644 index 00000000000..acdafb0c640 --- /dev/null +++ b/arch/sh/boards/mach-microdev/io.c @@ -0,0 +1,125 @@ +/* + * linux/arch/sh/boards/superh/microdev/io.c + * + * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) + * Copyright (C) 2003, 2004 SuperH, Inc. + * Copyright (C) 2004 Paul Mundt + * + * SuperH SH4-202 MicroDev board support. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + */ + +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/wait.h> +#include <asm/io.h> +#include <mach/microdev.h> + + /* + * we need to have a 'safe' address to re-direct all I/O requests + * that we do not explicitly wish to handle. This safe address + * must have the following properies: + * + * * writes are ignored (no exception) + * * reads are benign (no side-effects) + * * accesses of width 1, 2 and 4-bytes are all valid. + * + * The Processor Version Register (PVR) has these properties. + */ +#define PVR 0xff000030 /* Processor Version Register */ + + +#define IO_IDE2_BASE 0x170ul /* I/O base for SMSC FDC37C93xAPM IDE #2 */ +#define IO_IDE1_BASE 0x1f0ul /* I/O base for SMSC FDC37C93xAPM IDE #1 */ +#define IO_ISP1161_BASE 0x290ul /* I/O port for Philips ISP1161x USB chip */ +#define IO_SERIAL2_BASE 0x2f8ul /* I/O base for SMSC FDC37C93xAPM Serial #2 */ +#define IO_LAN91C111_BASE 0x300ul /* I/O base for SMSC LAN91C111 Ethernet chip */ +#define IO_IDE2_MISC 0x376ul /* I/O misc for SMSC FDC37C93xAPM IDE #2 */ +#define IO_SUPERIO_BASE 0x3f0ul /* I/O base for SMSC FDC37C93xAPM SuperIO chip */ +#define IO_IDE1_MISC 0x3f6ul /* I/O misc for SMSC FDC37C93xAPM IDE #1 */ +#define IO_SERIAL1_BASE 0x3f8ul /* I/O base for SMSC FDC37C93xAPM Serial #1 */ + +#define IO_ISP1161_EXTENT 0x04ul /* I/O extent for Philips ISP1161x USB chip */ +#define IO_LAN91C111_EXTENT 0x10ul /* I/O extent for SMSC LAN91C111 Ethernet chip */ +#define IO_SUPERIO_EXTENT 0x02ul /* I/O extent for SMSC FDC37C93xAPM SuperIO chip */ +#define IO_IDE_EXTENT 0x08ul /* I/O extent for IDE Task Register set */ +#define IO_SERIAL_EXTENT 0x10ul + +#define IO_LAN91C111_PHYS 0xa7500000ul /* Physical address of SMSC LAN91C111 Ethernet chip */ +#define IO_ISP1161_PHYS 0xa7700000ul /* Physical address of Philips ISP1161x USB chip */ +#define IO_SUPERIO_PHYS 0xa7800000ul /* Physical address of SMSC FDC37C93xAPM SuperIO chip */ + +/* + * map I/O ports to memory-mapped addresses + */ +void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len) +{ + unsigned long result; + + if ((offset >= IO_LAN91C111_BASE) && + (offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) { + /* + * SMSC LAN91C111 Ethernet chip + */ + result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE; + } else if ((offset >= IO_SUPERIO_BASE) && + (offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) { + /* + * SMSC FDC37C93xAPM SuperIO chip + * + * Configuration Registers + */ + result = IO_SUPERIO_PHYS + (offset << 1); + } else if (((offset >= IO_IDE1_BASE) && + (offset < IO_IDE1_BASE + IO_IDE_EXTENT)) || + (offset == IO_IDE1_MISC)) { + /* + * SMSC FDC37C93xAPM SuperIO chip + * + * IDE #1 + */ + result = IO_SUPERIO_PHYS + (offset << 1); + } else if (((offset >= IO_IDE2_BASE) && + (offset < IO_IDE2_BASE + IO_IDE_EXTENT)) || + (offset == IO_IDE2_MISC)) { + /* + * SMSC FDC37C93xAPM SuperIO chip + * + * IDE #2 + */ + result = IO_SUPERIO_PHYS + (offset << 1); + } else if ((offset >= IO_SERIAL1_BASE) && + (offset < IO_SERIAL1_BASE + IO_SERIAL_EXTENT)) { + /* + * SMSC FDC37C93xAPM SuperIO chip + * + * Serial #1 + */ + result = IO_SUPERIO_PHYS + (offset << 1); + } else if ((offset >= IO_SERIAL2_BASE) && + (offset < IO_SERIAL2_BASE + IO_SERIAL_EXTENT)) { + /* + * SMSC FDC37C93xAPM SuperIO chip + * + * Serial #2 + */ + result = IO_SUPERIO_PHYS + (offset << 1); + } else if ((offset >= IO_ISP1161_BASE) && + (offset < IO_ISP1161_BASE + IO_ISP1161_EXTENT)) { + /* + * Philips USB ISP1161x chip + */ + result = IO_ISP1161_PHYS + offset - IO_ISP1161_BASE; + } else { + /* + * safe default. + */ + printk("Warning: unexpected port in %s( offset = 0x%lx )\n", + __func__, offset); + result = PVR; + } + + return (void __iomem *)result; +} diff --git a/arch/sh/boards/superh/microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c index 4d335077a3f..9a8aff33961 100644 --- a/arch/sh/boards/superh/microdev/irq.c +++ b/arch/sh/boards/mach-microdev/irq.c @@ -12,9 +12,8 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/interrupt.h> -#include <asm/system.h> #include <asm/io.h> -#include <asm/microdev.h> +#include <mach/microdev.h> #define NUM_EXTERNAL_IRQS 16 /* IRL0 .. IRL15 */ @@ -65,33 +64,9 @@ static const struct { # error Inconsistancy in defining the IRQ# for primary IDE! #endif -static void enable_microdev_irq(unsigned int irq); -static void disable_microdev_irq(unsigned int irq); - - /* shutdown is same as "disable" */ -#define shutdown_microdev_irq disable_microdev_irq - -static void mask_and_ack_microdev(unsigned int); -static void end_microdev_irq(unsigned int irq); - -static unsigned int startup_microdev_irq(unsigned int irq) -{ - enable_microdev_irq(irq); - return 0; /* never anything pending */ -} - -static struct hw_interrupt_type microdev_irq_type = { - .typename = "MicroDev-IRQ", - .startup = startup_microdev_irq, - .shutdown = shutdown_microdev_irq, - .enable = enable_microdev_irq, - .disable = disable_microdev_irq, - .ack = mask_and_ack_microdev, - .end = end_microdev_irq -}; - -static void disable_microdev_irq(unsigned int irq) +static void disable_microdev_irq(struct irq_data *data) { + unsigned int irq = data->irq; unsigned int fpgaIrq; if (irq >= NUM_EXTERNAL_IRQS) @@ -102,11 +77,12 @@ static void disable_microdev_irq(unsigned int irq) fpgaIrq = fpgaIrqTable[irq].fpgaIrq; /* disable interrupts on the FPGA INTC register */ - ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG); + __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG); } -static void enable_microdev_irq(unsigned int irq) +static void enable_microdev_irq(struct irq_data *data) { + unsigned int irq = data->irq; unsigned long priorityReg, priorities, pri; unsigned int fpgaIrq; @@ -121,40 +97,35 @@ static void enable_microdev_irq(unsigned int irq) priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq); /* set priority for the interrupt */ - priorities = ctrl_inl(priorityReg); + priorities = __raw_readl(priorityReg); priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq); priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri); - ctrl_outl(priorities, priorityReg); + __raw_writel(priorities, priorityReg); /* enable interrupts on the FPGA INTC register */ - ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG); + __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG); } - /* This functions sets the desired irq handler to be a MicroDev type */ +static struct irq_chip microdev_irq_type = { + .name = "MicroDev-IRQ", + .irq_unmask = enable_microdev_irq, + .irq_mask = disable_microdev_irq, +}; + +/* This function sets the desired irq handler to be a MicroDev type */ static void __init make_microdev_irq(unsigned int irq) { disable_irq_nosync(irq); - irq_desc[irq].chip = µdev_irq_type; - disable_microdev_irq(irq); -} - -static void mask_and_ack_microdev(unsigned int irq) -{ - disable_microdev_irq(irq); -} - -static void end_microdev_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_microdev_irq(irq); + irq_set_chip_and_handler(irq, µdev_irq_type, handle_level_irq); + disable_microdev_irq(irq_get_irq_data(irq)); } extern void __init init_microdev_irq(void) { int i; - /* disable interrupts on the FPGA INTC register */ - ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG); + /* disable interrupts on the FPGA INTC register */ + __raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG); for (i = 0; i < NUM_EXTERNAL_IRQS; i++) make_microdev_irq(i); @@ -179,5 +150,3 @@ extern void microdev_print_fpga_intc_status(void) printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria); printk("-------------------------------------------------------------------------------\n"); } - - diff --git a/arch/sh/boards/mach-microdev/setup.c b/arch/sh/boards/mach-microdev/setup.c new file mode 100644 index 00000000000..6c66ee4d842 --- /dev/null +++ b/arch/sh/boards/mach-microdev/setup.c @@ -0,0 +1,199 @@ +/* + * arch/sh/boards/superh/microdev/setup.c + * + * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) + * Copyright (C) 2003, 2004 SuperH, Inc. + * Copyright (C) 2004, 2005 Paul Mundt + * + * SuperH SH4-202 MicroDev board support. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ioport.h> +#include <video/s1d13xxxfb.h> +#include <mach/microdev.h> +#include <asm/io.h> +#include <asm/machvec.h> +#include <asm/sizes.h> + +static struct resource smc91x_resources[] = { + [0] = { + .start = 0x300, + .end = 0x300 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MICRODEV_LINUX_IRQ_ETHERNET, + .end = MICRODEV_LINUX_IRQ_ETHERNET, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct s1d13xxxfb_regval s1d13806_initregs[] = { + { S1DREG_MISC, 0x00 }, + { S1DREG_COM_DISP_MODE, 0x00 }, + { S1DREG_GPIO_CNF0, 0x00 }, + { S1DREG_GPIO_CNF1, 0x00 }, + { S1DREG_GPIO_CTL0, 0x00 }, + { S1DREG_GPIO_CTL1, 0x00 }, + { S1DREG_CLK_CNF, 0x02 }, + { S1DREG_LCD_CLK_CNF, 0x01 }, + { S1DREG_CRT_CLK_CNF, 0x03 }, + { S1DREG_MPLUG_CLK_CNF, 0x03 }, + { S1DREG_CPU2MEM_WST_SEL, 0x02 }, + { S1DREG_SDRAM_REF_RATE, 0x03 }, + { S1DREG_SDRAM_TC0, 0x00 }, + { S1DREG_SDRAM_TC1, 0x01 }, + { S1DREG_MEM_CNF, 0x80 }, + { S1DREG_PANEL_TYPE, 0x25 }, + { S1DREG_MOD_RATE, 0x00 }, + { S1DREG_LCD_DISP_HWIDTH, 0x63 }, + { S1DREG_LCD_NDISP_HPER, 0x1e }, + { S1DREG_TFT_FPLINE_START, 0x06 }, + { S1DREG_TFT_FPLINE_PWIDTH, 0x03 }, + { S1DREG_LCD_DISP_VHEIGHT0, 0x57 }, + { S1DREG_LCD_DISP_VHEIGHT1, 0x02 }, + { S1DREG_LCD_NDISP_VPER, 0x00 }, + { S1DREG_TFT_FPFRAME_START, 0x0a }, + { S1DREG_TFT_FPFRAME_PWIDTH, 0x81 }, + { S1DREG_LCD_DISP_MODE, 0x03 }, + { S1DREG_LCD_MISC, 0x00 }, + { S1DREG_LCD_DISP_START0, 0x00 }, + { S1DREG_LCD_DISP_START1, 0x00 }, + { S1DREG_LCD_DISP_START2, 0x00 }, + { S1DREG_LCD_MEM_OFF0, 0x90 }, + { S1DREG_LCD_MEM_OFF1, 0x01 }, + { S1DREG_LCD_PIX_PAN, 0x00 }, + { S1DREG_LCD_DISP_FIFO_HTC, 0x00 }, + { S1DREG_LCD_DISP_FIFO_LTC, 0x00 }, + { S1DREG_CRT_DISP_HWIDTH, 0x63 }, + { S1DREG_CRT_NDISP_HPER, 0x1f }, + { S1DREG_CRT_HRTC_START, 0x04 }, + { S1DREG_CRT_HRTC_PWIDTH, 0x8f }, + { S1DREG_CRT_DISP_VHEIGHT0, 0x57 }, + { S1DREG_CRT_DISP_VHEIGHT1, 0x02 }, + { S1DREG_CRT_NDISP_VPER, 0x1b }, + { S1DREG_CRT_VRTC_START, 0x00 }, + { S1DREG_CRT_VRTC_PWIDTH, 0x83 }, + { S1DREG_TV_OUT_CTL, 0x10 }, + { S1DREG_CRT_DISP_MODE, 0x05 }, + { S1DREG_CRT_DISP_START0, 0x00 }, + { S1DREG_CRT_DISP_START1, 0x00 }, + { S1DREG_CRT_DISP_START2, 0x00 }, + { S1DREG_CRT_MEM_OFF0, 0x20 }, + { S1DREG_CRT_MEM_OFF1, 0x03 }, + { S1DREG_CRT_PIX_PAN, 0x00 }, + { S1DREG_CRT_DISP_FIFO_HTC, 0x00 }, + { S1DREG_CRT_DISP_FIFO_LTC, 0x00 }, + { S1DREG_LCD_CUR_CTL, 0x00 }, + { S1DREG_LCD_CUR_START, 0x01 }, + { S1DREG_LCD_CUR_XPOS0, 0x00 }, + { S1DREG_LCD_CUR_XPOS1, 0x00 }, + { S1DREG_LCD_CUR_YPOS0, 0x00 }, + { S1DREG_LCD_CUR_YPOS1, 0x00 }, + { S1DREG_LCD_CUR_BCTL0, 0x00 }, + { S1DREG_LCD_CUR_GCTL0, 0x00 }, + { S1DREG_LCD_CUR_RCTL0, 0x00 }, + { S1DREG_LCD_CUR_BCTL1, 0x1f }, + { S1DREG_LCD_CUR_GCTL1, 0x3f }, + { S1DREG_LCD_CUR_RCTL1, 0x1f }, + { S1DREG_LCD_CUR_FIFO_HTC, 0x00 }, + { S1DREG_CRT_CUR_CTL, 0x00 }, + { S1DREG_CRT_CUR_START, 0x01 }, + { S1DREG_CRT_CUR_XPOS0, 0x00 }, + { S1DREG_CRT_CUR_XPOS1, 0x00 }, + { S1DREG_CRT_CUR_YPOS0, 0x00 }, + { S1DREG_CRT_CUR_YPOS1, 0x00 }, + { S1DREG_CRT_CUR_BCTL0, 0x00 }, + { S1DREG_CRT_CUR_GCTL0, 0x00 }, + { S1DREG_CRT_CUR_RCTL0, 0x00 }, + { S1DREG_CRT_CUR_BCTL1, 0x1f }, + { S1DREG_CRT_CUR_GCTL1, 0x3f }, + { S1DREG_CRT_CUR_RCTL1, 0x1f }, + { S1DREG_CRT_CUR_FIFO_HTC, 0x00 }, + { S1DREG_BBLT_CTL0, 0x00 }, + { S1DREG_BBLT_CTL1, 0x00 }, + { S1DREG_BBLT_CC_EXP, 0x00 }, + { S1DREG_BBLT_OP, 0x00 }, + { S1DREG_BBLT_SRC_START0, 0x00 }, + { S1DREG_BBLT_SRC_START1, 0x00 }, + { S1DREG_BBLT_SRC_START2, 0x00 }, + { S1DREG_BBLT_DST_START0, 0x00 }, + { S1DREG_BBLT_DST_START1, 0x00 }, + { S1DREG_BBLT_DST_START2, 0x00 }, + { S1DREG_BBLT_MEM_OFF0, 0x00 }, + { S1DREG_BBLT_MEM_OFF1, 0x00 }, + { S1DREG_BBLT_WIDTH0, 0x00 }, + { S1DREG_BBLT_WIDTH1, 0x00 }, + { S1DREG_BBLT_HEIGHT0, 0x00 }, + { S1DREG_BBLT_HEIGHT1, 0x00 }, + { S1DREG_BBLT_BGC0, 0x00 }, + { S1DREG_BBLT_BGC1, 0x00 }, + { S1DREG_BBLT_FGC0, 0x00 }, + { S1DREG_BBLT_FGC1, 0x00 }, + { S1DREG_LKUP_MODE, 0x00 }, + { S1DREG_LKUP_ADDR, 0x00 }, + { S1DREG_PS_CNF, 0x10 }, + { S1DREG_PS_STATUS, 0x00 }, + { S1DREG_CPU2MEM_WDOGT, 0x00 }, + { S1DREG_COM_DISP_MODE, 0x02 }, +}; + +static struct s1d13xxxfb_pdata s1d13806_platform_data = { + .initregs = s1d13806_initregs, + .initregssize = ARRAY_SIZE(s1d13806_initregs), +}; + +static struct resource s1d13806_resources[] = { + [0] = { + .start = 0x07200000, + .end = 0x07200000 + SZ_2M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0x07000000, + .end = 0x07000000 + SZ_2M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device s1d13806_device = { + .name = "s1d13806fb", + .id = -1, + .num_resources = ARRAY_SIZE(s1d13806_resources), + .resource = s1d13806_resources, + + .dev = { + .platform_data = &s1d13806_platform_data, + }, +}; + +static struct platform_device *microdev_devices[] __initdata = { + &smc91x_device, + &s1d13806_device, +}; + +static int __init microdev_devices_setup(void) +{ + return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices)); +} +device_initcall(microdev_devices_setup); + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_sh4202_microdev __initmv = { + .mv_name = "SH4-202 MicroDev", + .mv_ioport_map = microdev_ioport_map, + .mv_init_irq = init_microdev_irq, +}; diff --git a/arch/sh/boards/mach-migor/Kconfig b/arch/sh/boards/mach-migor/Kconfig new file mode 100644 index 00000000000..a7b3b728ec3 --- /dev/null +++ b/arch/sh/boards/mach-migor/Kconfig @@ -0,0 +1,15 @@ +if SH_MIGOR + +choice + prompt "Migo-R LCD Panel Board Selection" + default SH_MIGOR_QVGA + +config SH_MIGOR_QVGA + bool "QVGA (320x240)" + +config SH_MIGOR_RTA_WVGA + bool "RTA WVGA (800x480)" + +endchoice + +endif diff --git a/arch/sh/boards/mach-migor/Makefile b/arch/sh/boards/mach-migor/Makefile new file mode 100644 index 00000000000..4601a89e5ac --- /dev/null +++ b/arch/sh/boards/mach-migor/Makefile @@ -0,0 +1,2 @@ +obj-y := setup.o sdram.o +obj-$(CONFIG_SH_MIGOR_QVGA) += lcd_qvga.o diff --git a/arch/sh/boards/mach-migor/lcd_qvga.c b/arch/sh/boards/mach-migor/lcd_qvga.c new file mode 100644 index 00000000000..8bccd345b69 --- /dev/null +++ b/arch/sh/boards/mach-migor/lcd_qvga.c @@ -0,0 +1,166 @@ +/* + * Support for SuperH MigoR Quarter VGA LCD Panel + * + * Copyright (C) 2008 Magnus Damm + * + * Based on lcd_powertip.c from Kenati Technologies Pvt Ltd. + * Copyright (c) 2007 Ujjwal Pande <ujjwal@kenati.com>, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/fb.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/gpio.h> +#include <video/sh_mobile_lcdc.h> +#include <cpu/sh7722.h> +#include <mach/migor.h> + +/* LCD Module is a PH240320T according to board schematics. This module + * is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?) + * Driver IC. This IC is connected to the SH7722 built-in LCDC using a + * SYS-80 interface configured in 16 bit mode. + * + * Index 0: "Device Code Read" returns 0x1505. + */ + +static void reset_lcd_module(void) +{ + gpio_set_value(GPIO_PTH2, 0); + mdelay(2); + gpio_set_value(GPIO_PTH2, 1); + mdelay(1); +} + +/* DB0-DB7 are connected to D1-D8, and DB8-DB15 to D10-D17 */ + +static unsigned long adjust_reg18(unsigned short data) +{ + unsigned long tmp1, tmp2; + + tmp1 = (data<<1 | 0x00000001) & 0x000001FF; + tmp2 = (data<<2 | 0x00000200) & 0x0003FE00; + return tmp1 | tmp2; +} + +static void write_reg(void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops, + unsigned short reg, unsigned short data) +{ + sys_ops->write_index(sys_ops_handle, adjust_reg18(reg << 8 | data)); +} + +static void write_reg16(void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops, + unsigned short reg, unsigned short data) +{ + sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); + sys_ops->write_data(sys_ops_handle, adjust_reg18(data)); +} + +static unsigned long read_reg16(void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops, + unsigned short reg) +{ + unsigned long data; + + sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); + data = sys_ops->read_data(sys_ops_handle); + return ((data >> 1) & 0xff) | ((data >> 2) & 0xff00); +} + +static void migor_lcd_qvga_seq(void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops, + unsigned short const *data, int no_data) +{ + int i; + + for (i = 0; i < no_data; i += 2) + write_reg16(sys_ops_handle, sys_ops, data[i], data[i + 1]); +} + +static const unsigned short sync_data[] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +}; + +static const unsigned short magic0_data[] = { + 0x0060, 0x2700, 0x0008, 0x0808, 0x0090, 0x001A, 0x0007, 0x0001, + 0x0017, 0x0001, 0x0019, 0x0000, 0x0010, 0x17B0, 0x0011, 0x0116, + 0x0012, 0x0198, 0x0013, 0x1400, 0x0029, 0x000C, 0x0012, 0x01B8, +}; + +static const unsigned short magic1_data[] = { + 0x0030, 0x0307, 0x0031, 0x0303, 0x0032, 0x0603, 0x0033, 0x0202, + 0x0034, 0x0202, 0x0035, 0x0202, 0x0036, 0x1F1F, 0x0037, 0x0303, + 0x0038, 0x0303, 0x0039, 0x0603, 0x003A, 0x0202, 0x003B, 0x0102, + 0x003C, 0x0204, 0x003D, 0x0000, 0x0001, 0x0100, 0x0002, 0x0300, + 0x0003, 0x5028, 0x0020, 0x00ef, 0x0021, 0x0000, 0x0004, 0x0000, + 0x0009, 0x0000, 0x000A, 0x0008, 0x000C, 0x0000, 0x000D, 0x0000, + 0x0015, 0x8000, +}; + +static const unsigned short magic2_data[] = { + 0x0061, 0x0001, 0x0092, 0x0100, 0x0093, 0x0001, 0x0007, 0x0021, +}; + +static const unsigned short magic3_data[] = { + 0x0010, 0x16B0, 0x0011, 0x0111, 0x0007, 0x0061, +}; + +int migor_lcd_qvga_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so) +{ + unsigned long xres = 320; + unsigned long yres = 240; + int k; + + reset_lcd_module(); + migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data)); + + if (read_reg16(sohandle, so, 0) != 0x1505) + return -ENODEV; + + pr_info("Migo-R QVGA LCD Module detected.\n"); + + migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data)); + write_reg16(sohandle, so, 0x00A4, 0x0001); + mdelay(10); + + migor_lcd_qvga_seq(sohandle, so, magic0_data, ARRAY_SIZE(magic0_data)); + mdelay(100); + + migor_lcd_qvga_seq(sohandle, so, magic1_data, ARRAY_SIZE(magic1_data)); + write_reg16(sohandle, so, 0x0050, 0xef - (yres - 1)); + write_reg16(sohandle, so, 0x0051, 0x00ef); + write_reg16(sohandle, so, 0x0052, 0x0000); + write_reg16(sohandle, so, 0x0053, xres - 1); + + migor_lcd_qvga_seq(sohandle, so, magic2_data, ARRAY_SIZE(magic2_data)); + mdelay(10); + + migor_lcd_qvga_seq(sohandle, so, magic3_data, ARRAY_SIZE(magic3_data)); + mdelay(40); + + /* clear GRAM to avoid displaying garbage */ + + write_reg16(sohandle, so, 0x0020, 0x0000); /* horiz addr */ + write_reg16(sohandle, so, 0x0021, 0x0000); /* vert addr */ + + for (k = 0; k < (xres * 256); k++) /* yes, 256 words per line */ + write_reg16(sohandle, so, 0x0022, 0x0000); + + write_reg16(sohandle, so, 0x0020, 0x0000); /* reset horiz addr */ + write_reg16(sohandle, so, 0x0021, 0x0000); /* reset vert addr */ + write_reg16(sohandle, so, 0x0007, 0x0173); + mdelay(40); + + /* enable display */ + write_reg(sohandle, so, 0x00, 0x22); + mdelay(100); + return 0; +} diff --git a/arch/sh/boards/mach-migor/sdram.S b/arch/sh/boards/mach-migor/sdram.S new file mode 100644 index 00000000000..614aa3a1398 --- /dev/null +++ b/arch/sh/boards/mach-migor/sdram.S @@ -0,0 +1,69 @@ +/* + * Migo-R sdram self/auto-refresh setup code + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/sys.h> +#include <linux/errno.h> +#include <linux/linkage.h> +#include <asm/asm-offsets.h> +#include <asm/suspend.h> +#include <asm/romimage-macros.h> + +/* code to enter and leave self-refresh. must be self-contained. + * this code will be copied to on-chip memory and executed from there. + */ + .balign 4 +ENTRY(migor_sdram_enter_start) + + /* SBSC: disable power down and put in self-refresh mode */ + mov.l 1f, r4 + mov.l 2f, r1 + mov.l @r4, r2 + or r1, r2 + mov.l 3f, r3 + and r3, r2 + mov.l r2, @r4 + + rts + nop + + .balign 4 +1: .long 0xfe400008 /* SDCR0 */ +2: .long 0x00000400 +3: .long 0xffff7fff +ENTRY(migor_sdram_enter_end) + + .balign 4 +ENTRY(migor_sdram_leave_start) + + /* SBSC: set auto-refresh mode */ + mov.l 1f, r4 + mov.l @r4, r0 + mov.l 4f, r1 + and r1, r0 + mov.l r0, @r4 + mov.l 6f, r4 + mov.l 8f, r0 + mov.l @r4, r1 + mov #-1, r4 + add r4, r1 + or r1, r0 + mov.l 7f, r1 + mov.l r0, @r1 + + rts + nop + + .balign 4 +1: .long 0xfe400008 /* SDCR0 */ +4: .long 0xfffffbff +6: .long 0xfe40001c /* RTCOR */ +7: .long 0xfe400018 /* RTCNT */ +8: .long 0xa55a0000 +ENTRY(migor_sdram_leave_end) diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c new file mode 100644 index 00000000000..8b73194ed2c --- /dev/null +++ b/arch/sh/boards/mach-migor/setup.c @@ -0,0 +1,674 @@ +/* + * Renesas System Solutions Asia Pte. Ltd - Migo-R + * + * Copyright (C) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/input.h> +#include <linux/input/sh_keysc.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/nand.h> +#include <linux/i2c.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/smc91x.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/videodev2.h> +#include <linux/sh_intc.h> +#include <video/sh_mobile_lcdc.h> +#include <media/sh_mobile_ceu.h> +#include <media/ov772x.h> +#include <media/soc_camera.h> +#include <media/tw9910.h> +#include <asm/clock.h> +#include <asm/machvec.h> +#include <asm/io.h> +#include <asm/suspend.h> +#include <mach/migor.h> +#include <cpu/sh7722.h> + +/* Address IRQ Size Bus Description + * 0x00000000 64MB 16 NOR Flash (SP29PL256N) + * 0x0c000000 64MB 64 SDRAM (2xK4M563233G) + * 0x10000000 IRQ0 16 Ethernet (SMC91C111) + * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596) + * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A) + */ + +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, +}; + +static struct resource smc91x_eth_resources[] = { + [0] = { + .name = "SMC91C111" , + .start = 0x10000300, + .end = 0x1000030f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x600), /* IRQ0 */ + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct platform_device smc91x_eth_device = { + .name = "smc91x", + .num_resources = ARRAY_SIZE(smc91x_eth_resources), + .resource = smc91x_eth_resources, + .dev = { + .platform_data = &smc91x_info, + }, +}; + +static struct sh_keysc_info sh_keysc_info = { + .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */ + .scan_timing = 3, + .delay = 5, + .keycodes = { + 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER, + 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1, + 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6, + 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0, + 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD, + }, +}; + +static struct resource sh_keysc_resources[] = { + [0] = { + .start = 0x044b0000, + .end = 0x044b000f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xbe0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh_keysc_device = { + .name = "sh_keysc", + .id = 0, /* "keysc0" clock */ + .num_resources = ARRAY_SIZE(sh_keysc_resources), + .resource = sh_keysc_resources, + .dev = { + .platform_data = &sh_keysc_info, + }, +}; + +static struct mtd_partition migor_nor_flash_partitions[] = +{ + { + .name = "uboot", + .offset = 0, + .size = (1 * 1024 * 1024), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = (15 * 1024 * 1024), + }, + { + .name = "other", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data migor_nor_flash_data = { + .width = 2, + .parts = migor_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions), +}; + +static struct resource migor_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x03ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device migor_nor_flash_device = { + .name = "physmap-flash", + .resource = migor_nor_flash_resources, + .num_resources = ARRAY_SIZE(migor_nor_flash_resources), + .dev = { + .platform_data = &migor_nor_flash_data, + }, +}; + +static struct mtd_partition migor_nand_flash_partitions[] = { + { + .name = "nanddata1", + .offset = 0x0, + .size = 512 * 1024 * 1024, + }, + { + .name = "nanddata2", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024 * 1024, + }, +}; + +static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *chip = mtd->priv; + + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + writeb(cmd, chip->IO_ADDR_W + 0x00400000); + else if (ctrl & NAND_ALE) + writeb(cmd, chip->IO_ADDR_W + 0x00800000); + else + writeb(cmd, chip->IO_ADDR_W); +} + +static int migor_nand_flash_ready(struct mtd_info *mtd) +{ + return gpio_get_value(GPIO_PTA1); /* NAND_RBn */ +} + +static struct platform_nand_data migor_nand_flash_data = { + .chip = { + .nr_chips = 1, + .partitions = migor_nand_flash_partitions, + .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions), + .chip_delay = 20, + }, + .ctrl = { + .dev_ready = migor_nand_flash_ready, + .cmd_ctrl = migor_nand_flash_cmd_ctl, + }, +}; + +static struct resource migor_nand_flash_resources[] = { + [0] = { + .name = "NAND Flash", + .start = 0x18000000, + .end = 0x18ffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device migor_nand_flash_device = { + .name = "gen_nand", + .resource = migor_nand_flash_resources, + .num_resources = ARRAY_SIZE(migor_nand_flash_resources), + .dev = { + .platform_data = &migor_nand_flash_data, + } +}; + +static const struct fb_videomode migor_lcd_modes[] = { + { +#if defined(CONFIG_SH_MIGOR_RTA_WVGA) + .name = "LB070WV1", + .xres = 800, + .yres = 480, + .left_margin = 64, + .right_margin = 16, + .hsync_len = 120, + .sync = 0, +#elif defined(CONFIG_SH_MIGOR_QVGA) + .name = "PH240320T", + .xres = 320, + .yres = 240, + .left_margin = 0, + .right_margin = 16, + .hsync_len = 8, + .sync = FB_SYNC_HOR_HIGH_ACT, +#endif + .upper_margin = 1, + .lower_margin = 17, + .vsync_len = 2, + }, +}; + +static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = { +#if defined(CONFIG_SH_MIGOR_RTA_WVGA) + .clock_source = LCDC_CLK_BUS, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .fourcc = V4L2_PIX_FMT_RGB565, + .interface_type = RGB16, + .clock_divider = 2, + .lcd_modes = migor_lcd_modes, + .num_modes = ARRAY_SIZE(migor_lcd_modes), + .panel_cfg = { /* 7.0 inch */ + .width = 152, + .height = 91, + }, + } +#elif defined(CONFIG_SH_MIGOR_QVGA) + .clock_source = LCDC_CLK_PERIPHERAL, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .fourcc = V4L2_PIX_FMT_RGB565, + .interface_type = SYS16A, + .clock_divider = 10, + .lcd_modes = migor_lcd_modes, + .num_modes = ARRAY_SIZE(migor_lcd_modes), + .panel_cfg = { + .width = 49, /* 2.4 inch */ + .height = 37, + .setup_sys = migor_lcd_qvga_setup, + }, + .sys_bus_cfg = { + .ldmt2r = 0x06000a09, + .ldmt3r = 0x180e3418, + /* set 1s delay to encourage fsync() */ + .deferred_io_msec = 1000, + }, + } +#endif +}; + +static struct resource migor_lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, /* P4-only space */ + .end = 0xfe942fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x580), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device migor_lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(migor_lcdc_resources), + .resource = migor_lcdc_resources, + .dev = { + .platform_data = &sh_mobile_lcdc_info, + }, +}; + +static struct clk *camera_clk; +static DEFINE_MUTEX(camera_lock); + +static void camera_power_on(int is_tw) +{ + mutex_lock(&camera_lock); + + /* Use 10 MHz VIO_CKO instead of 24 MHz to work + * around signal quality issues on Panel Board V2.1. + */ + camera_clk = clk_get(NULL, "video_clk"); + clk_set_rate(camera_clk, 10000000); + clk_enable(camera_clk); /* start VIO_CKO */ + + /* use VIO_RST to take camera out of reset */ + mdelay(10); + if (is_tw) { + gpio_set_value(GPIO_PTT2, 0); + gpio_set_value(GPIO_PTT0, 0); + } else { + gpio_set_value(GPIO_PTT0, 1); + } + gpio_set_value(GPIO_PTT3, 0); + mdelay(10); + gpio_set_value(GPIO_PTT3, 1); + mdelay(10); /* wait to let chip come out of reset */ +} + +static void camera_power_off(void) +{ + clk_disable(camera_clk); /* stop VIO_CKO */ + clk_put(camera_clk); + + gpio_set_value(GPIO_PTT3, 0); + mutex_unlock(&camera_lock); +} + +static int ov7725_power(struct device *dev, int mode) +{ + if (mode) + camera_power_on(0); + else + camera_power_off(); + + return 0; +} + +static int tw9910_power(struct device *dev, int mode) +{ + if (mode) + camera_power_on(1); + else + camera_power_off(); + + return 0; +} + +static struct sh_mobile_ceu_info sh_mobile_ceu_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource migor_ceu_resources[] = { + [0] = { + .name = "CEU", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x880), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device migor_ceu_device = { + .name = "sh_mobile_ceu", + .id = 0, /* "ceu0" clock */ + .num_resources = ARRAY_SIZE(migor_ceu_resources), + .resource = migor_ceu_resources, + .dev = { + .platform_data = &sh_mobile_ceu_info, + }, +}; + +/* Fixed 3.3V regulator to be used by SDHI0 */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +}; + +static struct resource sdhi_cn9_resources[] = { + [0] = { + .name = "SDHI", + .start = 0x04ce0000, + .end = 0x04ce00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xe80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mobile_sdhi_info sh7724_sdhi_data = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, + .tmio_caps = MMC_CAP_SDIO_IRQ, +}; + +static struct platform_device sdhi_cn9_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi_cn9_resources), + .resource = sdhi_cn9_resources, + .dev = { + .platform_data = &sh7724_sdhi_data, + }, +}; + +static struct i2c_board_info migor_i2c_devices[] = { + { + I2C_BOARD_INFO("rs5c372b", 0x32), + }, + { + I2C_BOARD_INFO("migor_ts", 0x51), + .irq = evt2irq(0x6c0), /* IRQ6 */ + }, + { + I2C_BOARD_INFO("wm8978", 0x1a), + }, +}; + +static struct i2c_board_info migor_i2c_camera[] = { + { + I2C_BOARD_INFO("ov772x", 0x21), + }, + { + I2C_BOARD_INFO("tw9910", 0x45), + }, +}; + +static struct ov772x_camera_info ov7725_info; + +static struct soc_camera_link ov7725_link = { + .power = ov7725_power, + .board_info = &migor_i2c_camera[0], + .i2c_adapter_id = 0, + .priv = &ov7725_info, +}; + +static struct tw9910_video_info tw9910_info = { + .buswidth = SOCAM_DATAWIDTH_8, + .mpout = TW9910_MPO_FIELD, +}; + +static struct soc_camera_link tw9910_link = { + .power = tw9910_power, + .board_info = &migor_i2c_camera[1], + .i2c_adapter_id = 0, + .priv = &tw9910_info, +}; + +static struct platform_device migor_camera[] = { + { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &ov7725_link, + }, + }, { + .name = "soc-camera-pdrv", + .id = 1, + .dev = { + .platform_data = &tw9910_link, + }, + }, +}; + +static struct platform_device *migor_devices[] __initdata = { + &smc91x_eth_device, + &sh_keysc_device, + &migor_lcdc_device, + &migor_ceu_device, + &migor_nor_flash_device, + &migor_nand_flash_device, + &sdhi_cn9_device, + &migor_camera[0], + &migor_camera[1], +}; + +extern char migor_sdram_enter_start; +extern char migor_sdram_enter_end; +extern char migor_sdram_leave_start; +extern char migor_sdram_leave_end; + +static int __init migor_devices_setup(void) +{ + /* register board specific self-refresh code */ + sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, + &migor_sdram_enter_start, + &migor_sdram_enter_end, + &migor_sdram_leave_start, + &migor_sdram_leave_end); + + regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + + /* Let D11 LED show STATUS0 */ + gpio_request(GPIO_FN_STATUS0, NULL); + + /* Lit D12 LED show PDSTATUS */ + gpio_request(GPIO_FN_PDSTATUS, NULL); + + /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */ + gpio_request(GPIO_FN_IRQ0, NULL); + __raw_writel(0x00003400, BSC_CS4BCR); + __raw_writel(0x00110080, BSC_CS4WCR); + + /* KEYSC */ + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); + gpio_request(GPIO_FN_KEYIN1, NULL); + gpio_request(GPIO_FN_KEYIN2, NULL); + gpio_request(GPIO_FN_KEYIN3, NULL); + gpio_request(GPIO_FN_KEYIN4, NULL); + gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); + + /* NAND Flash */ + gpio_request(GPIO_FN_CS6A_CE2B, NULL); + __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR); + gpio_request(GPIO_PTA1, NULL); + gpio_direction_input(GPIO_PTA1); + + /* SDHI */ + gpio_request(GPIO_FN_SDHICD, NULL); + gpio_request(GPIO_FN_SDHIWP, NULL); + gpio_request(GPIO_FN_SDHID3, NULL); + gpio_request(GPIO_FN_SDHID2, NULL); + gpio_request(GPIO_FN_SDHID1, NULL); + gpio_request(GPIO_FN_SDHID0, NULL); + gpio_request(GPIO_FN_SDHICMD, NULL); + gpio_request(GPIO_FN_SDHICLK, NULL); + + /* Touch Panel */ + gpio_request(GPIO_FN_IRQ6, NULL); + + /* LCD Panel */ +#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */ + gpio_request(GPIO_FN_LCDD17, NULL); + gpio_request(GPIO_FN_LCDD16, NULL); + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDRS, NULL); + gpio_request(GPIO_FN_LCDCS, NULL); + gpio_request(GPIO_FN_LCDRD, NULL); + gpio_request(GPIO_FN_LCDWR, NULL); + gpio_request(GPIO_PTH2, NULL); /* LCD_DON */ + gpio_direction_output(GPIO_PTH2, 1); +#endif +#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */ + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDLCLK, NULL); + gpio_request(GPIO_FN_LCDDCK, NULL); + gpio_request(GPIO_FN_LCDVEPWC, NULL); + gpio_request(GPIO_FN_LCDVCPWC, NULL); + gpio_request(GPIO_FN_LCDVSYN, NULL); + gpio_request(GPIO_FN_LCDHSYN, NULL); + gpio_request(GPIO_FN_LCDDISP, NULL); + gpio_request(GPIO_FN_LCDDON, NULL); +#endif + + /* CEU */ + gpio_request(GPIO_FN_VIO_CLK2, NULL); + gpio_request(GPIO_FN_VIO_VD2, NULL); + gpio_request(GPIO_FN_VIO_HD2, NULL); + gpio_request(GPIO_FN_VIO_FLD, NULL); + gpio_request(GPIO_FN_VIO_CKO, NULL); + gpio_request(GPIO_FN_VIO_D15, NULL); + gpio_request(GPIO_FN_VIO_D14, NULL); + gpio_request(GPIO_FN_VIO_D13, NULL); + gpio_request(GPIO_FN_VIO_D12, NULL); + gpio_request(GPIO_FN_VIO_D11, NULL); + gpio_request(GPIO_FN_VIO_D10, NULL); + gpio_request(GPIO_FN_VIO_D9, NULL); + gpio_request(GPIO_FN_VIO_D8, NULL); + + gpio_request(GPIO_PTT3, NULL); /* VIO_RST */ + gpio_direction_output(GPIO_PTT3, 0); + gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */ + gpio_direction_output(GPIO_PTT2, 1); + gpio_request(GPIO_PTT0, NULL); /* CAM_EN */ +#ifdef CONFIG_SH_MIGOR_RTA_WVGA + gpio_direction_output(GPIO_PTT0, 0); +#else + gpio_direction_output(GPIO_PTT0, 1); +#endif + __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */ + + platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20); + + /* SIU: Port B */ + gpio_request(GPIO_FN_SIUBOLR, NULL); + gpio_request(GPIO_FN_SIUBOBT, NULL); + gpio_request(GPIO_FN_SIUBISLD, NULL); + gpio_request(GPIO_FN_SIUBOSLD, NULL); + gpio_request(GPIO_FN_SIUMCKB, NULL); + + /* + * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to + * output. Need only SIUB, set to output for master mode (table 34.2) + */ + __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA); + + i2c_register_board_info(0, migor_i2c_devices, + ARRAY_SIZE(migor_i2c_devices)); + + return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices)); +} +arch_initcall(migor_devices_setup); + +/* Return the board specific boot mode pin configuration */ +static int migor_mode_pins(void) +{ + /* MD0=1, MD1=1, MD2=0: Clock Mode 3 + * MD3=0: 16-bit Area0 Bus Width + * MD5=1: Little Endian + * TSTMD=1, MD8=0: Test Mode Disabled + */ + return MODE_PIN0 | MODE_PIN1 | MODE_PIN5; +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_migor __initmv = { + .mv_name = "Migo-R", + .mv_mode_pins = migor_mode_pins, +}; diff --git a/arch/sh/boards/renesas/rts7751r2d/Kconfig b/arch/sh/boards/mach-r2d/Kconfig index 8122a9667fc..8122a9667fc 100644 --- a/arch/sh/boards/renesas/rts7751r2d/Kconfig +++ b/arch/sh/boards/mach-r2d/Kconfig diff --git a/arch/sh/boards/renesas/rts7751r2d/Makefile b/arch/sh/boards/mach-r2d/Makefile index 0d4c75a72be..0d4c75a72be 100644 --- a/arch/sh/boards/renesas/rts7751r2d/Makefile +++ b/arch/sh/boards/mach-r2d/Makefile diff --git a/arch/sh/boards/renesas/rts7751r2d/irq.c b/arch/sh/boards/mach-r2d/irq.c index 8e49f6e5124..574f009c3c3 100644 --- a/arch/sh/boards/renesas/rts7751r2d/irq.c +++ b/arch/sh/boards/mach-r2d/irq.c @@ -13,7 +13,7 @@ #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/io.h> -#include <asm/rts7751r2d.h> +#include <mach/r2d.h> #define R2D_NR_IRL 13 @@ -116,7 +116,7 @@ static unsigned char irl2irq[R2D_NR_IRL]; int rts7751r2d_irq_demux(int irq) { - if (irq >= R2D_NR_IRL || !irl2irq[irq]) + if (irq >= R2D_NR_IRL || irq < 0 || !irl2irq[irq]) return irq; return irl2irq[irq]; @@ -129,7 +129,7 @@ void __init init_rts7751r2d_IRQ(void) { struct intc_desc *d; - switch (ctrl_inw(PA_VERREG) & 0xf0) { + switch (__raw_readw(PA_VERREG) & 0xf0) { #ifdef CONFIG_RTS7751R2D_PLUS case 0x10: printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n"); @@ -147,7 +147,7 @@ void __init init_rts7751r2d_IRQ(void) #endif default: printk(KERN_INFO "Unknown R2D interrupt controller 0x%04x\n", - ctrl_inw(PA_VERREG)); + __raw_readw(PA_VERREG)); return; } diff --git a/arch/sh/boards/renesas/rts7751r2d/setup.c b/arch/sh/boards/mach-r2d/setup.c index f21ee49ef3a..4b98a5251f8 100644 --- a/arch/sh/boards/renesas/rts7751r2d/setup.c +++ b/arch/sh/boards/mach-r2d/setup.c @@ -10,8 +10,10 @@ */ #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/ata_platform.h> -#include <linux/serial_8250.h> #include <linux/sm501.h> #include <linux/sm501-regs.h> #include <linux/pm.h> @@ -19,7 +21,7 @@ #include <linux/spi/spi.h> #include <linux/spi/spi_bitbang.h> #include <asm/machvec.h> -#include <asm/rts7751r2d.h> +#include <mach/r2d.h> #include <asm/io.h> #include <asm/io_trapped.h> #include <asm/spi.h> @@ -68,7 +70,7 @@ static struct spi_board_info spi_bus[] = { static void r2d_chip_select(struct sh_spi_info *spi, int cs, int state) { BUG_ON(cs != 0); /* Single Epson RTC-9701JE attached on CS0 */ - ctrl_outw(state == BITBANG_CS_ACTIVE, PA_RTCCE); + __raw_writew(state == BITBANG_CS_ACTIVE, PA_RTCCE); } static struct sh_spi_info spi_info = { @@ -109,28 +111,6 @@ static struct platform_device heartbeat_device = { .resource = heartbeat_resources, }; -#ifdef CONFIG_MFD_SM501 -static struct plat_serial8250_port uart_platform_data[] = { - { - .membase = (void __iomem *)0xb3e30000, - .mapbase = 0xb3e30000, - .iotype = UPIO_MEM, - .irq = IRQ_VOYAGER, - .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, - .regshift = 2, - .uartclk = (9600 * 16), - }, - { 0 }, -}; - -static struct platform_device uart_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = uart_platform_data, - }, -}; - static struct resource sm501_resources[] = { [0] = { .start = 0x10000000, @@ -186,11 +166,7 @@ static struct sm501_platdata_fb sm501_fb_pdata = { }; static struct sm501_initdata sm501_initdata = { - .gpio_high = { - .set = 0x00001fe0, - .mask = 0x0, - }, - .devices = SM501_USE_USB_HOST, + .devices = SM501_USE_USB_HOST | SM501_USE_UART0, }; static struct sm501_platdata sm501_platform_data = { @@ -208,13 +184,52 @@ static struct platform_device sm501_device = { .resource = sm501_resources, }; -#endif /* CONFIG_MFD_SM501 */ +static struct mtd_partition r2d_partitions[] = { + { + .name = "U-Boot", + .offset = 0x00000000, + .size = 0x00040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Environment", + .offset = MTDPART_OFS_NXTBLK, + .size = 0x00040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = 0x001c0000, + }, { + .name = "Flash_FS", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct physmap_flash_data flash_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(r2d_partitions), + .parts = r2d_partitions, +}; + +static struct resource flash_resource = { + .start = 0x00000000, + .end = 0x02000000, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = &flash_resource, + .num_resources = 1, + .dev = { + .platform_data = &flash_data, + }, +}; static struct platform_device *rts7751r2d_devices[] __initdata = { -#ifdef CONFIG_MFD_SM501 - &uart_device, &sm501_device, -#endif &heartbeat_device, &spi_sh_sci_device, }; @@ -234,15 +249,20 @@ static int __init rts7751r2d_devices_setup(void) { if (register_trapped_io(&cf_trapped_io) == 0) platform_device_register(&cf_ide_device); + + if (mach_is_r2d_plus()) + platform_device_register(&flash_device); + spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus)); + return platform_add_devices(rts7751r2d_devices, ARRAY_SIZE(rts7751r2d_devices)); } -__initcall(rts7751r2d_devices_setup); +device_initcall(rts7751r2d_devices_setup); static void rts7751r2d_power_off(void) { - ctrl_outw(0x0001, PA_POWOFF); + __raw_writew(0x0001, PA_POWOFF); } /* @@ -251,14 +271,14 @@ static void rts7751r2d_power_off(void) static void __init rts7751r2d_setup(char **cmdline_p) { void __iomem *sm501_reg; - u16 ver = ctrl_inw(PA_VERREG); + u16 ver = __raw_readw(PA_VERREG); printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n"); printk(KERN_INFO "FPGA version:%d (revision:%d)\n", (ver >> 4) & 0xf, ver & 0xf); - ctrl_outw(0x0000, PA_OUTPORT); + __raw_writew(0x0000, PA_OUTPORT); pm_power_off = rts7751r2d_power_off; /* sm501 dram configuration: @@ -275,16 +295,6 @@ static void __init rts7751r2d_setup(char **cmdline_p) sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL; writel(readl(sm501_reg) | 0x00f107c0, sm501_reg); - - /* - * Power Mode Gate - Enable UART0 - */ - - sm501_reg = (void __iomem *)0xb3e00000 + SM501_POWER_MODE_0_GATE; - writel(readl(sm501_reg) | (1 << SM501_GATE_UART0), sm501_reg); - - sm501_reg = (void __iomem *)0xb3e00000 + SM501_POWER_MODE_1_GATE; - writel(readl(sm501_reg) | (1 << SM501_GATE_UART0), sm501_reg); } /* diff --git a/arch/sh/boards/mach-rsk/Kconfig b/arch/sh/boards/mach-rsk/Kconfig new file mode 100644 index 00000000000..458a11ffd02 --- /dev/null +++ b/arch/sh/boards/mach-rsk/Kconfig @@ -0,0 +1,28 @@ +if SH_RSK + +choice + prompt "RSK+ options" + default SH_RSK7203 + +config SH_RSK7201 + bool "RSK7201" + depends on CPU_SUBTYPE_SH7201 + +config SH_RSK7203 + bool "RSK7203" + select ARCH_REQUIRE_GPIOLIB + depends on CPU_SUBTYPE_SH7203 + +config SH_RSK7264 + bool "RSK2+SH7264" + select ARCH_REQUIRE_GPIOLIB + depends on CPU_SUBTYPE_SH7264 + +config SH_RSK7269 + bool "RSK2+SH7269" + select ARCH_REQUIRE_GPIOLIB + depends on CPU_SUBTYPE_SH7269 + +endchoice + +endif diff --git a/arch/sh/boards/mach-rsk/Makefile b/arch/sh/boards/mach-rsk/Makefile new file mode 100644 index 00000000000..6a4e1b538a6 --- /dev/null +++ b/arch/sh/boards/mach-rsk/Makefile @@ -0,0 +1,4 @@ +obj-y := setup.o +obj-$(CONFIG_SH_RSK7203) += devices-rsk7203.o +obj-$(CONFIG_SH_RSK7264) += devices-rsk7264.o +obj-$(CONFIG_SH_RSK7269) += devices-rsk7269.o diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c new file mode 100644 index 00000000000..a8089f79d05 --- /dev/null +++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c @@ -0,0 +1,140 @@ +/* + * Renesas Technology Europe RSK+ 7203 Support. + * + * Copyright (C) 2008 - 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/types.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/smsc911x.h> +#include <linux/input.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/leds.h> +#include <asm/machvec.h> +#include <asm/io.h> +#include <cpu/sh7203.h> + +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT | SMSC911X_SWAP_FIFO, +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .start = 0x24000000, + .end = 0x240000ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 64, + .end = 64, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct gpio_led rsk7203_gpio_leds[] = { + { + .name = "green", + .gpio = GPIO_PE10, + .active_low = 1, + }, { + .name = "orange", + .default_trigger = "nand-disk", + .gpio = GPIO_PE12, + .active_low = 1, + }, { + .name = "red:timer", + .default_trigger = "timer", + .gpio = GPIO_PC14, + .active_low = 1, + }, { + .name = "red:heartbeat", + .default_trigger = "heartbeat", + .gpio = GPIO_PE11, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data rsk7203_gpio_leds_info = { + .leds = rsk7203_gpio_leds, + .num_leds = ARRAY_SIZE(rsk7203_gpio_leds), +}; + +static struct platform_device led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &rsk7203_gpio_leds_info, + }, +}; + +static struct gpio_keys_button rsk7203_gpio_keys_table[] = { + { + .code = BTN_0, + .gpio = GPIO_PB0, + .active_low = 1, + .desc = "SW1", + }, { + .code = BTN_1, + .gpio = GPIO_PB1, + .active_low = 1, + .desc = "SW2", + }, { + .code = BTN_2, + .gpio = GPIO_PB2, + .active_low = 1, + .desc = "SW3", + }, +}; + +static struct gpio_keys_platform_data rsk7203_gpio_keys_info = { + .buttons = rsk7203_gpio_keys_table, + .nbuttons = ARRAY_SIZE(rsk7203_gpio_keys_table), + .poll_interval = 50, /* default to 50ms */ +}; + +static struct platform_device keys_device = { + .name = "gpio-keys-polled", + .dev = { + .platform_data = &rsk7203_gpio_keys_info, + }, +}; + +static struct platform_device *rsk7203_devices[] __initdata = { + &smsc911x_device, + &led_device, + &keys_device, +}; + +static int __init rsk7203_devices_setup(void) +{ + /* Select pins for SCIF0 */ + gpio_request(GPIO_FN_TXD0, NULL); + gpio_request(GPIO_FN_RXD0, NULL); + + /* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */ + __raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */ + gpio_request(GPIO_FN_IRQ0_PB, NULL); + + return platform_add_devices(rsk7203_devices, + ARRAY_SIZE(rsk7203_devices)); +} +device_initcall(rsk7203_devices_setup); diff --git a/arch/sh/boards/mach-rsk/devices-rsk7264.c b/arch/sh/boards/mach-rsk/devices-rsk7264.c new file mode 100644 index 00000000000..7251e37a842 --- /dev/null +++ b/arch/sh/boards/mach-rsk/devices-rsk7264.c @@ -0,0 +1,58 @@ +/* + * RSK+SH7264 Support. + * + * Copyright (C) 2012 Renesas Electronics Europe + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/types.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/input.h> +#include <linux/smsc911x.h> +#include <asm/machvec.h> +#include <asm/io.h> + +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO, +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .start = 0x28000000, + .end = 0x280000ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 65, + .end = 65, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *rsk7264_devices[] __initdata = { + &smsc911x_device, +}; + +static int __init rsk7264_devices_setup(void) +{ + return platform_add_devices(rsk7264_devices, + ARRAY_SIZE(rsk7264_devices)); +} +device_initcall(rsk7264_devices_setup); diff --git a/arch/sh/boards/mach-rsk/devices-rsk7269.c b/arch/sh/boards/mach-rsk/devices-rsk7269.c new file mode 100644 index 00000000000..4a544591d6f --- /dev/null +++ b/arch/sh/boards/mach-rsk/devices-rsk7269.c @@ -0,0 +1,60 @@ +/* + * RSK+SH7269 Support + * + * Copyright (C) 2012 Renesas Electronics Europe Ltd + * Copyright (C) 2012 Phil Edworthy + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/types.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/input.h> +#include <linux/smsc911x.h> +#include <linux/gpio.h> +#include <asm/machvec.h> +#include <asm/io.h> + +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO, +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .start = 0x24000000, + .end = 0x240000ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 85, + .end = 85, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *rsk7269_devices[] __initdata = { + &smsc911x_device, +}; + +static int __init rsk7269_devices_setup(void) +{ + return platform_add_devices(rsk7269_devices, + ARRAY_SIZE(rsk7269_devices)); +} +device_initcall(rsk7269_devices_setup); diff --git a/arch/sh/boards/mach-rsk/setup.c b/arch/sh/boards/mach-rsk/setup.c new file mode 100644 index 00000000000..2685ea03b06 --- /dev/null +++ b/arch/sh/boards/mach-rsk/setup.c @@ -0,0 +1,90 @@ +/* + * Renesas Technology Europe RSK+ Support. + * + * Copyright (C) 2008 Paul Mundt + * Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/types.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/map.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <asm/machvec.h> +#include <asm/io.h> + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +static const char *part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition rsk_partitions[] = { + { + .name = "Bootloader", + .offset = 0x00000000, + .size = 0x00040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = 0x001c0000, + }, { + .name = "Flash_FS", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct physmap_flash_data flash_data = { + .parts = rsk_partitions, + .nr_parts = ARRAY_SIZE(rsk_partitions), + .width = 2, + .part_probe_types = part_probes, +}; + +static struct resource flash_resource = { + .start = 0x20000000, + .end = 0x20400000, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = &flash_resource, + .num_resources = 1, + .dev = { + .platform_data = &flash_data, + }, +}; + +static struct platform_device *rsk_devices[] __initdata = { + &flash_device, +}; + +static int __init rsk_devices_setup(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + return platform_add_devices(rsk_devices, + ARRAY_SIZE(rsk_devices)); +} +device_initcall(rsk_devices_setup); + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_rsk __initmv = { + .mv_name = "RSK+", +}; diff --git a/arch/sh/boards/renesas/sdk7780/Kconfig b/arch/sh/boards/mach-sdk7780/Kconfig index 065f1df09bf..065f1df09bf 100644 --- a/arch/sh/boards/renesas/sdk7780/Kconfig +++ b/arch/sh/boards/mach-sdk7780/Kconfig diff --git a/arch/sh/boards/renesas/sdk7780/Makefile b/arch/sh/boards/mach-sdk7780/Makefile index 3d8f0befc35..3d8f0befc35 100644 --- a/arch/sh/boards/renesas/sdk7780/Makefile +++ b/arch/sh/boards/mach-sdk7780/Makefile diff --git a/arch/sh/boards/renesas/sdk7780/irq.c b/arch/sh/boards/mach-sdk7780/irq.c index 87cdc578f6f..e5f7564f251 100644 --- a/arch/sh/boards/renesas/sdk7780/irq.c +++ b/arch/sh/boards/mach-sdk7780/irq.c @@ -12,7 +12,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/io.h> -#include <asm/sdk7780.h> +#include <mach/sdk7780.h> enum { UNUSED = 0, @@ -37,9 +37,9 @@ void __init init_sdk7780_IRQ(void) { printk(KERN_INFO "Using SDK7780 interrupt controller.\n"); - ctrl_outw(0xFFFF, FPGA_IRQ0MR); + __raw_writew(0xFFFF, FPGA_IRQ0MR); /* Setup IRL 0-3 */ - ctrl_outw(0x0003, FPGA_IMSR); + __raw_writew(0x0003, FPGA_IMSR); plat_irq_setup_pins(IRQ_MODE_IRL3210); register_intc_controller(&fpga_intc_desc); diff --git a/arch/sh/boards/renesas/sdk7780/setup.c b/arch/sh/boards/mach-sdk7780/setup.c index acc5932587f..2241659c329 100644 --- a/arch/sh/boards/renesas/sdk7780/setup.c +++ b/arch/sh/boards/mach-sdk7780/setup.c @@ -13,34 +13,25 @@ #include <linux/platform_device.h> #include <linux/ata_platform.h> #include <asm/machvec.h> -#include <asm/sdk7780.h> +#include <mach/sdk7780.h> #include <asm/heartbeat.h> #include <asm/io.h> #include <asm/addrspace.h> #define GPIO_PECR 0xFFEA0008 -//* Heartbeat */ -static struct heartbeat_data heartbeat_data = { - .regsize = 16, -}; - -static struct resource heartbeat_resources[] = { - [0] = { - .start = PA_LED, - .end = PA_LED, - .flags = IORESOURCE_MEM, - }, +/* Heartbeat */ +static struct resource heartbeat_resource = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, }; static struct platform_device heartbeat_device = { .name = "heartbeat", .id = -1, - .dev = { - .platform_data = &heartbeat_data, - }, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, + .num_resources = 1, + .resource = &heartbeat_resource, }; /* SMC91x */ @@ -83,8 +74,8 @@ device_initcall(sdk7780_devices_setup); static void __init sdk7780_setup(char **cmdline_p) { - u16 ver = ctrl_inw(FPGA_FPVERR); - u16 dateStamp = ctrl_inw(FPGA_FPDATER); + u16 ver = __raw_readw(FPGA_FPVERR); + u16 dateStamp = __raw_readw(FPGA_FPDATER); printk(KERN_INFO "Renesas Technology Europe SDK7780 support.\n"); printk(KERN_INFO "Board version: %d (revision %d), " @@ -94,7 +85,7 @@ static void __init sdk7780_setup(char **cmdline_p) dateStamp); /* Setup pin mux'ing for PCIC */ - ctrl_outw(0x0000, GPIO_PECR); + __raw_writew(0x0000, GPIO_PECR); } /* @@ -103,7 +94,6 @@ static void __init sdk7780_setup(char **cmdline_p) static struct sh_machine_vector mv_se7780 __initmv = { .mv_name = "Renesas SDK7780-R3" , .mv_setup = sdk7780_setup, - .mv_nr_irqs = 111, .mv_init_irq = init_sdk7780_IRQ, }; diff --git a/arch/sh/boards/mach-sdk7786/Makefile b/arch/sh/boards/mach-sdk7786/Makefile new file mode 100644 index 00000000000..45d32e3590b --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/Makefile @@ -0,0 +1,4 @@ +obj-y := fpga.o irq.o nmi.o setup.o + +obj-$(CONFIG_GPIOLIB) += gpio.o +obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o diff --git a/arch/sh/boards/mach-sdk7786/fpga.c b/arch/sh/boards/mach-sdk7786/fpga.c new file mode 100644 index 00000000000..3e4ec66a041 --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/fpga.c @@ -0,0 +1,72 @@ +/* + * SDK7786 FPGA Support. + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/io.h> +#include <linux/bcd.h> +#include <mach/fpga.h> +#include <asm/sizes.h> + +#define FPGA_REGS_OFFSET 0x03fff800 +#define FPGA_REGS_SIZE 0x490 + +/* + * The FPGA can be mapped in any of the generally available areas, + * so we attempt to scan for it using the fixed SRSTR read magic. + * + * Once the FPGA is located, the rest of the mapping data for the other + * components can be determined dynamically from its section mapping + * registers. + */ +static void __iomem *sdk7786_fpga_probe(void) +{ + unsigned long area; + void __iomem *base; + + /* + * Iterate over all of the areas where the FPGA could be mapped. + * The possible range is anywhere from area 0 through 6, area 7 + * is reserved. + */ + for (area = PA_AREA0; area < PA_AREA7; area += SZ_64M) { + base = ioremap_nocache(area + FPGA_REGS_OFFSET, FPGA_REGS_SIZE); + if (!base) { + /* Failed to remap this area, move along. */ + continue; + } + + if (ioread16(base + SRSTR) == SRSTR_MAGIC) + return base; /* Found it! */ + + iounmap(base); + } + + return NULL; +} + +void __iomem *sdk7786_fpga_base; + +void __init sdk7786_fpga_init(void) +{ + u16 version, date; + + sdk7786_fpga_base = sdk7786_fpga_probe(); + if (unlikely(!sdk7786_fpga_base)) { + panic("FPGA detection failed.\n"); + return; + } + + version = fpga_read_reg(FPGAVR); + date = fpga_read_reg(FPGADR); + + pr_info("\tFPGA version:\t%d.%d (built on %d/%d/%d)\n", + bcd2bin(version >> 8) & 0xf, bcd2bin(version & 0xf), + ((date >> 12) & 0xf) + 2000, + (date >> 8) & 0xf, bcd2bin(date & 0xff)); +} diff --git a/arch/sh/boards/mach-sdk7786/gpio.c b/arch/sh/boards/mach-sdk7786/gpio.c new file mode 100644 index 00000000000..f71ce09d4e1 --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/gpio.c @@ -0,0 +1,49 @@ +/* + * SDK7786 FPGA USRGPIR Support. + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/io.h> +#include <mach/fpga.h> + +#define NR_FPGA_GPIOS 8 + +static const char *usrgpir_gpio_names[NR_FPGA_GPIOS] = { + "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", +}; + +static int usrgpir_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + /* always in */ + return 0; +} + +static int usrgpir_gpio_get(struct gpio_chip *chip, unsigned gpio) +{ + return !!(fpga_read_reg(USRGPIR) & (1 << gpio)); +} + +static struct gpio_chip usrgpir_gpio_chip = { + .label = "sdk7786-fpga", + .names = usrgpir_gpio_names, + .direction_input = usrgpir_gpio_direction_input, + .get = usrgpir_gpio_get, + .base = -1, /* don't care */ + .ngpio = NR_FPGA_GPIOS, +}; + +static int __init usrgpir_gpio_setup(void) +{ + return gpiochip_add(&usrgpir_gpio_chip); +} +device_initcall(usrgpir_gpio_setup); diff --git a/arch/sh/boards/mach-sdk7786/irq.c b/arch/sh/boards/mach-sdk7786/irq.c new file mode 100644 index 00000000000..46943a0da5b --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/irq.c @@ -0,0 +1,48 @@ +/* + * SDK7786 FPGA IRQ Controller Support. + * + * Copyright (C) 2010 Matt Fleming + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/irq.h> +#include <mach/fpga.h> +#include <mach/irq.h> + +enum { + ATA_IRQ_BIT = 1, + SPI_BUSY_BIT = 2, + LIRQ5_BIT = 3, + LIRQ6_BIT = 4, + LIRQ7_BIT = 5, + LIRQ8_BIT = 6, + KEY_IRQ_BIT = 7, + PEN_IRQ_BIT = 8, + ETH_IRQ_BIT = 9, + RTC_ALARM_BIT = 10, + CRYSTAL_FAIL_BIT = 12, + ETH_PME_BIT = 14, +}; + +void __init sdk7786_init_irq(void) +{ + unsigned int tmp; + + /* Enable priority encoding for all IRLs */ + fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR); + + /* Clear FPGA interrupt status registers */ + fpga_write_reg(0x0000, INTASR); + fpga_write_reg(0x0000, INTBSR); + + /* Unmask FPGA interrupts */ + tmp = fpga_read_reg(INTAMR); + tmp &= ~(1 << ETH_IRQ_BIT); + fpga_write_reg(tmp, INTAMR); + + plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK); + plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK); +} diff --git a/arch/sh/boards/mach-sdk7786/nmi.c b/arch/sh/boards/mach-sdk7786/nmi.c new file mode 100644 index 00000000000..edcfa1f568b --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/nmi.c @@ -0,0 +1,83 @@ +/* + * SDK7786 FPGA NMI Support. + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <mach/fpga.h> + +enum { + NMI_MODE_MANUAL, + NMI_MODE_AUX, + NMI_MODE_MASKED, + NMI_MODE_ANY, + NMI_MODE_UNKNOWN, +}; + +/* + * Default to the manual NMI switch. + */ +static unsigned int __initdata nmi_mode = NMI_MODE_ANY; + +static int __init nmi_mode_setup(char *str) +{ + if (!str) + return 0; + + if (strcmp(str, "manual") == 0) + nmi_mode = NMI_MODE_MANUAL; + else if (strcmp(str, "aux") == 0) + nmi_mode = NMI_MODE_AUX; + else if (strcmp(str, "masked") == 0) + nmi_mode = NMI_MODE_MASKED; + else if (strcmp(str, "any") == 0) + nmi_mode = NMI_MODE_ANY; + else { + nmi_mode = NMI_MODE_UNKNOWN; + pr_warning("Unknown NMI mode %s\n", str); + } + + printk("Set NMI mode to %d\n", nmi_mode); + return 0; +} +early_param("nmi_mode", nmi_mode_setup); + +void __init sdk7786_nmi_init(void) +{ + unsigned int source, mask, tmp; + + switch (nmi_mode) { + case NMI_MODE_MANUAL: + source = NMISR_MAN_NMI; + mask = NMIMR_MAN_NMIM; + break; + case NMI_MODE_AUX: + source = NMISR_AUX_NMI; + mask = NMIMR_AUX_NMIM; + break; + case NMI_MODE_ANY: + source = NMISR_MAN_NMI | NMISR_AUX_NMI; + mask = NMIMR_MAN_NMIM | NMIMR_AUX_NMIM; + break; + case NMI_MODE_MASKED: + case NMI_MODE_UNKNOWN: + default: + source = mask = 0; + break; + } + + /* Set the NMI source */ + tmp = fpga_read_reg(NMISR); + tmp &= ~NMISR_MASK; + tmp |= source; + fpga_write_reg(tmp, NMISR); + + /* And the IRQ masking */ + fpga_write_reg(NMIMR_MASK ^ mask, NMIMR); +} diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c new file mode 100644 index 00000000000..c29268bfd34 --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/setup.c @@ -0,0 +1,269 @@ +/* + * Renesas Technology Europe SDK7786 Support. + * + * Copyright (C) 2010 Matt Fleming + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/smsc911x.h> +#include <linux/i2c.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <mach/fpga.h> +#include <mach/irq.h> +#include <asm/machvec.h> +#include <asm/heartbeat.h> +#include <asm/sizes.h> +#include <asm/clock.h> +#include <asm/reboot.h> +#include <asm/smp-ops.h> + +static struct resource heartbeat_resource = { + .start = 0x07fff8b0, + .end = 0x07fff8b0 + sizeof(u16) - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = 0x07ffff00, + .end = 0x07ffff00 + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = evt2irq(0x2c0), + .end = evt2irq(0x2c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct resource smbus_fpga_resource = { + .start = 0x07fff9e0, + .end = 0x07fff9e0 + SZ_32 - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device smbus_fpga_device = { + .name = "i2c-sdk7786", + .id = 0, + .num_resources = 1, + .resource = &smbus_fpga_resource, +}; + +static struct resource smbus_pcie_resource = { + .start = 0x07fffc30, + .end = 0x07fffc30 + SZ_32 - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device smbus_pcie_device = { + .name = "i2c-sdk7786", + .id = 1, + .num_resources = 1, + .resource = &smbus_pcie_resource, +}; + +static struct i2c_board_info __initdata sdk7786_i2c_devices[] = { + { + I2C_BOARD_INFO("max6900", 0x68), + }, +}; + +static struct platform_device *sh7786_devices[] __initdata = { + &heartbeat_device, + &smsc911x_device, + &smbus_fpga_device, + &smbus_pcie_device, +}; + +static int sdk7786_i2c_setup(void) +{ + unsigned int tmp; + + /* + * Hand over I2C control to the FPGA. + */ + tmp = fpga_read_reg(SBCR); + tmp &= ~SCBR_I2CCEN; + tmp |= SCBR_I2CMEN; + fpga_write_reg(tmp, SBCR); + + return i2c_register_board_info(0, sdk7786_i2c_devices, + ARRAY_SIZE(sdk7786_i2c_devices)); +} + +static int __init sdk7786_devices_setup(void) +{ + int ret; + + ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices)); + if (unlikely(ret != 0)) + return ret; + + return sdk7786_i2c_setup(); +} +device_initcall(sdk7786_devices_setup); + +static int sdk7786_mode_pins(void) +{ + return fpga_read_reg(MODSWR); +} + +/* + * FPGA-driven PCIe clocks + * + * Historically these include the oscillator, clock B (slots 2/3/4) and + * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove + * everything under a single PCIe clocks enable bit that happens to map + * to the same bit position as the oscillator bit for earlier FPGA + * versions. + * + * Given that the legacy clocks have the side-effect of shutting the CPU + * off through the FPGA along with the PCI slots, we simply leave them in + * their initial state and don't bother registering them with the clock + * framework. + */ +static int sdk7786_pcie_clk_enable(struct clk *clk) +{ + fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR); + return 0; +} + +static void sdk7786_pcie_clk_disable(struct clk *clk) +{ + fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR); +} + +static struct sh_clk_ops sdk7786_pcie_clk_ops = { + .enable = sdk7786_pcie_clk_enable, + .disable = sdk7786_pcie_clk_disable, +}; + +static struct clk sdk7786_pcie_clk = { + .ops = &sdk7786_pcie_clk_ops, +}; + +static struct clk_lookup sdk7786_pcie_cl = { + .con_id = "pcie_plat_clk", + .clk = &sdk7786_pcie_clk, +}; + +static int sdk7786_clk_init(void) +{ + struct clk *clk; + int ret; + + /* + * Only handle the EXTAL case, anyone interfacing a crystal + * resonator will need to provide their own input clock. + */ + if (test_mode_pin(MODE_PIN9)) + return -EINVAL; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333333); + clk_put(clk); + + /* + * Setup the FPGA clocks. + */ + ret = clk_register(&sdk7786_pcie_clk); + if (unlikely(ret)) { + pr_err("FPGA clock registration failed\n"); + return ret; + } + + clkdev_add(&sdk7786_pcie_cl); + + return 0; +} + +static void sdk7786_restart(char *cmd) +{ + fpga_write_reg(0xa5a5, SRSTR); +} + +static void sdk7786_power_off(void) +{ + fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR); + + /* + * It can take up to 20us for the R8C to do its job, back off and + * wait a bit until we've been shut off. Even though newer FPGA + * versions don't set the ACK bit, the latency issue remains. + */ + while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0) + cpu_sleep(); +} + +/* Initialize the board */ +static void __init sdk7786_setup(char **cmdline_p) +{ + pr_info("Renesas Technology Europe SDK7786 support:\n"); + + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + sdk7786_fpga_init(); + sdk7786_nmi_init(); + + pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf); + + machine_ops.restart = sdk7786_restart; + pm_power_off = sdk7786_power_off; + + register_smp_ops(&shx3_smp_ops); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_sdk7786 __initmv = { + .mv_name = "SDK7786", + .mv_setup = sdk7786_setup, + .mv_mode_pins = sdk7786_mode_pins, + .mv_clk_init = sdk7786_clk_init, + .mv_init_irq = sdk7786_init_irq, +}; diff --git a/arch/sh/boards/mach-sdk7786/sram.c b/arch/sh/boards/mach-sdk7786/sram.c new file mode 100644 index 00000000000..c81c3abbe01 --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/sram.c @@ -0,0 +1,72 @@ +/* + * SDK7786 FPGA SRAM Support. + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/io.h> +#include <linux/string.h> +#include <mach/fpga.h> +#include <asm/sram.h> +#include <asm/sizes.h> + +static int __init fpga_sram_init(void) +{ + unsigned long phys; + unsigned int area; + void __iomem *vaddr; + int ret; + u16 data; + + /* Enable FPGA SRAM */ + data = fpga_read_reg(LCLASR); + data |= LCLASR_FRAMEN; + fpga_write_reg(data, LCLASR); + + /* + * FPGA_SEL determines the area mapping + */ + area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT; + if (unlikely(area == LCLASR_AREA_MASK)) { + pr_err("FPGA memory unmapped.\n"); + return -ENXIO; + } + + /* + * The memory itself occupies a 2KiB range at the top of the area + * immediately below the system registers. + */ + phys = (area << 26) + SZ_64M - SZ_4K; + + /* + * The FPGA SRAM resides in translatable physical space, so set + * up a mapping prior to inserting it in to the pool. + */ + vaddr = ioremap(phys, SZ_2K); + if (unlikely(!vaddr)) { + pr_err("Failed remapping FPGA memory.\n"); + return -ENXIO; + } + + pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx " + "(area %d) to pool.\n", + SZ_2K >> 10, phys, phys + SZ_2K - 1, area); + + ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1); + if (unlikely(ret < 0)) { + pr_err("Failed adding memory\n"); + iounmap(vaddr); + return ret; + } + + return 0; +} +postcore_initcall(fpga_sram_init); diff --git a/arch/sh/boards/se/7206/Makefile b/arch/sh/boards/mach-se/7206/Makefile index 63e7ed699f3..5c9eaa0535b 100644 --- a/arch/sh/boards/se/7206/Makefile +++ b/arch/sh/boards/mach-se/7206/Makefile @@ -2,4 +2,4 @@ # Makefile for the 7206 SolutionEngine specific parts of the kernel # -obj-y := setup.o io.o irq.o +obj-y := setup.o irq.o diff --git a/arch/sh/boards/se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c index 9d5bfc77d0d..0db058e709e 100644 --- a/arch/sh/boards/se/7206/irq.c +++ b/arch/sh/boards/mach-se/7206/irq.c @@ -10,7 +10,7 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/interrupt.h> -#include <asm/se7206.h> +#include <mach-se/mach/se7206.h> #define INTSTS0 0x31800000 #define INTSTS1 0x31800002 @@ -25,19 +25,20 @@ #define INTC_IPR01 0xfffe0818 #define INTC_ICR1 0xfffe0802 -static void disable_se7206_irq(unsigned int irq) +static void disable_se7206_irq(struct irq_data *data) { + unsigned int irq = data->irq; unsigned short val; unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq))); unsigned short msk0,msk1; /* Set the priority in IPR to 0 */ - val = ctrl_inw(INTC_IPR01); + val = __raw_readw(INTC_IPR01); val &= mask; - ctrl_outw(val, INTC_IPR01); + __raw_writew(val, INTC_IPR01); /* FPGA mask set */ - msk0 = ctrl_inw(INTMSK0); - msk1 = ctrl_inw(INTMSK1); + msk0 = __raw_readw(INTMSK0); + msk1 = __raw_readw(INTMSK1); switch (irq) { case IRQ0_IRQ: @@ -51,24 +52,25 @@ static void disable_se7206_irq(unsigned int irq) msk1 |= 0x00ff; break; } - ctrl_outw(msk0, INTMSK0); - ctrl_outw(msk1, INTMSK1); + __raw_writew(msk0, INTMSK0); + __raw_writew(msk1, INTMSK1); } -static void enable_se7206_irq(unsigned int irq) +static void enable_se7206_irq(struct irq_data *data) { + unsigned int irq = data->irq; unsigned short val; unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq))); unsigned short msk0,msk1; /* Set priority in IPR back to original value */ - val = ctrl_inw(INTC_IPR01); + val = __raw_readw(INTC_IPR01); val |= value; - ctrl_outw(val, INTC_IPR01); + __raw_writew(val, INTC_IPR01); /* FPGA mask reset */ - msk0 = ctrl_inw(INTMSK0); - msk1 = ctrl_inw(INTMSK1); + msk0 = __raw_readw(INTMSK0); + msk1 = __raw_readw(INTMSK1); switch (irq) { case IRQ0_IRQ: @@ -82,19 +84,20 @@ static void enable_se7206_irq(unsigned int irq) msk1 &= ~0x00ff; break; } - ctrl_outw(msk0, INTMSK0); - ctrl_outw(msk1, INTMSK1); + __raw_writew(msk0, INTMSK0); + __raw_writew(msk1, INTMSK1); } -static void eoi_se7206_irq(unsigned int irq) +static void eoi_se7206_irq(struct irq_data *data) { unsigned short sts0,sts1; + unsigned int irq = data->irq; - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_se7206_irq(irq); + if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data)) + enable_se7206_irq(data); /* FPGA isr clear */ - sts0 = ctrl_inw(INTSTS0); - sts1 = ctrl_inw(INTSTS1); + sts0 = __raw_readw(INTSTS0); + sts1 = __raw_readw(INTSTS1); switch (irq) { case IRQ0_IRQ: @@ -108,24 +111,23 @@ static void eoi_se7206_irq(unsigned int irq) sts1 &= ~0x00ff; break; } - ctrl_outw(sts0, INTSTS0); - ctrl_outw(sts1, INTSTS1); + __raw_writew(sts0, INTSTS0); + __raw_writew(sts1, INTSTS1); } static struct irq_chip se7206_irq_chip __read_mostly = { .name = "SE7206-FPGA", - .mask = disable_se7206_irq, - .unmask = enable_se7206_irq, - .mask_ack = disable_se7206_irq, - .eoi = eoi_se7206_irq, + .irq_mask = disable_se7206_irq, + .irq_unmask = enable_se7206_irq, + .irq_eoi = eoi_se7206_irq, }; static void make_se7206_irq(unsigned int irq) { disable_irq_nosync(irq); - set_irq_chip_and_handler_name(irq, &se7206_irq_chip, + irq_set_chip_and_handler_name(irq, &se7206_irq_chip, handle_level_irq, "level"); - disable_se7206_irq(irq); + disable_se7206_irq(irq_get_irq_data(irq)); } /* @@ -136,11 +138,13 @@ void __init init_se7206_IRQ(void) make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */ make_se7206_irq(IRQ1_IRQ); /* ATA */ make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */ - ctrl_outw(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */ + + __raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */ /* FPGA System register setup*/ - ctrl_outw(0x0000,INTSTS0); /* Clear INTSTS0 */ - ctrl_outw(0x0000,INTSTS1); /* Clear INTSTS1 */ + __raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */ + __raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */ + /* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */ - ctrl_outw(0x0001,INTSEL); + __raw_writew(0x0001,INTSEL); } diff --git a/arch/sh/boards/se/7206/setup.c b/arch/sh/boards/mach-se/7206/setup.c index 5b3ee089d91..68883ec9568 100644 --- a/arch/sh/boards/se/7206/setup.c +++ b/arch/sh/boards/mach-se/7206/setup.c @@ -3,21 +3,23 @@ * linux/arch/sh/boards/se/7206/setup.c * * Copyright (C) 2006 Yoshinori Sato - * Copyright (C) 2007 Paul Mundt + * Copyright (C) 2007 - 2008 Paul Mundt * * Hitachi 7206 SolutionEngine Support. */ #include <linux/init.h> #include <linux/platform_device.h> -#include <asm/se7206.h> +#include <linux/smc91x.h> +#include <mach-se/mach/se7206.h> #include <asm/io.h> #include <asm/machvec.h> #include <asm/heartbeat.h> static struct resource smc91x_resources[] = { [0] = { - .start = 0x300, - .end = 0x300 + 0x020 - 1, + .name = "smc91x-regs", + .start = PA_SMSC + 0x300, + .end = PA_SMSC + 0x300 + 0x020 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -27,9 +29,18 @@ static struct resource smc91x_resources[] = { }, }; +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT, +}; + static struct platform_device smc91x_device = { .name = "smc91x", .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + .platform_data = &smc91x_info, + }, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, }; @@ -39,15 +50,12 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; static struct heartbeat_data heartbeat_data = { .bit_pos = heartbeat_bit_pos, .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), - .regsize = 32, }; -static struct resource heartbeat_resources[] = { - [0] = { - .start = PA_LED, - .end = PA_LED, - .flags = IORESOURCE_MEM, - }, +static struct resource heartbeat_resource = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, }; static struct platform_device heartbeat_device = { @@ -56,8 +64,8 @@ static struct platform_device heartbeat_device = { .dev = { .platform_data = &heartbeat_data, }, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, + .num_resources = 1, + .resource = &heartbeat_resource, }; static struct platform_device *se7206_devices[] __initdata = { @@ -69,7 +77,12 @@ static int __init se7206_devices_setup(void) { return platform_add_devices(se7206_devices, ARRAY_SIZE(se7206_devices)); } -__initcall(se7206_devices_setup); +device_initcall(se7206_devices_setup); + +static int se7206_mode_pins(void) +{ + return MODE_PIN1 | MODE_PIN2; +} /* * The Machine Vector @@ -77,21 +90,6 @@ __initcall(se7206_devices_setup); static struct sh_machine_vector mv_se __initmv = { .mv_name = "SolutionEngine", - .mv_nr_irqs = 256, - .mv_inb = se7206_inb, - .mv_inw = se7206_inw, - .mv_outb = se7206_outb, - .mv_outw = se7206_outw, - - .mv_inb_p = se7206_inb_p, - .mv_inw_p = se7206_inw, - .mv_outb_p = se7206_outb_p, - .mv_outw_p = se7206_outw, - - .mv_insb = se7206_insb, - .mv_insw = se7206_insw, - .mv_outsb = se7206_outsb, - .mv_outsw = se7206_outsw, - .mv_init_irq = init_se7206_IRQ, + .mv_mode_pins = se7206_mode_pins, }; diff --git a/arch/sh/boards/se/7343/Makefile b/arch/sh/boards/mach-se/7343/Makefile index 3024796c620..4c3666a9379 100644 --- a/arch/sh/boards/se/7343/Makefile +++ b/arch/sh/boards/mach-se/7343/Makefile @@ -2,4 +2,4 @@ # Makefile for the 7343 SolutionEngine specific parts of the kernel # -obj-y := setup.o io.o irq.o +obj-y := setup.o irq.o diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c new file mode 100644 index 00000000000..7646bf0486c --- /dev/null +++ b/arch/sh/boards/mach-se/7343/irq.c @@ -0,0 +1,129 @@ +/* + * Hitachi UL SolutionEngine 7343 FPGA IRQ Support. + * + * Copyright (C) 2008 Yoshihiro Shimoda + * Copyright (C) 2012 Paul Mundt + * + * Based on linux/arch/sh/boards/se/7343/irq.c + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#define DRV_NAME "SE7343-FPGA" +#define pr_fmt(fmt) DRV_NAME ": " fmt + +#define irq_reg_readl ioread16 +#define irq_reg_writel iowrite16 + +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/irqdomain.h> +#include <linux/io.h> +#include <asm/sizes.h> +#include <mach-se/mach/se7343.h> + +#define PA_CPLD_BASE_ADDR 0x11400000 +#define PA_CPLD_ST_REG 0x08 /* CPLD Interrupt status register */ +#define PA_CPLD_IMSK_REG 0x0a /* CPLD Interrupt mask register */ + +static void __iomem *se7343_irq_regs; +struct irq_domain *se7343_irq_domain; + +static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + struct irq_data *data = irq_get_irq_data(irq); + struct irq_chip *chip = irq_data_get_irq_chip(data); + unsigned long mask; + int bit; + + chip->irq_mask_ack(data); + + mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG); + + for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR) + generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit)); + + chip->irq_unmask(data); +} + +static void __init se7343_domain_init(void) +{ + int i; + + se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR, + &irq_domain_simple_ops, NULL); + if (unlikely(!se7343_irq_domain)) { + printk("Failed to get IRQ domain\n"); + return; + } + + for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) { + int irq = irq_create_mapping(se7343_irq_domain, i); + + if (unlikely(irq == 0)) { + printk("Failed to allocate IRQ %d\n", i); + return; + } + } +} + +static void __init se7343_gc_init(void) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + unsigned int irq_base; + + irq_base = irq_linear_revmap(se7343_irq_domain, 0); + + gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs, + handle_level_irq); + if (unlikely(!gc)) + return; + + ct = gc->chip_types; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + + ct->regs.mask = PA_CPLD_IMSK_REG; + + irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR), + IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); + + irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux); + irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); + + irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux); + irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); + + irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux); + irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW); + + irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux); + irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW); +} + +/* + * Initialize IRQ setting + */ +void __init init_7343se_IRQ(void) +{ + se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16); + if (unlikely(!se7343_irq_regs)) { + pr_err("Failed to remap CPLD\n"); + return; + } + + /* + * All FPGA IRQs disabled by default + */ + iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG); + + __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */ + + se7343_domain_init(); + se7343_gc_init(); +} diff --git a/arch/sh/boards/mach-se/7343/setup.c b/arch/sh/boards/mach-se/7343/setup.c new file mode 100644 index 00000000000..8ce4f2a202a --- /dev/null +++ b/arch/sh/boards/mach-se/7343/setup.c @@ -0,0 +1,181 @@ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/serial_8250.h> +#include <linux/serial_reg.h> +#include <linux/usb/isp116x.h> +#include <linux/delay.h> +#include <linux/irqdomain.h> +#include <asm/machvec.h> +#include <mach-se/mach/se7343.h> +#include <asm/heartbeat.h> +#include <asm/irq.h> +#include <asm/io.h> + +static struct resource heartbeat_resource = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 128 * 1024, + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 31 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x01ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +#define ST16C2550C_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP) + +static struct plat_serial8250_port serial_platform_data[] = { + [0] = { + .iotype = UPIO_MEM, + .mapbase = 0x16000000, + .regshift = 1, + .flags = ST16C2550C_FLAGS, + .uartclk = 7372800, + }, + [1] = { + .iotype = UPIO_MEM, + .mapbase = 0x17000000, + .regshift = 1, + .flags = ST16C2550C_FLAGS, + .uartclk = 7372800, + }, + { }, +}; + +static struct platform_device uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data, + }, +}; + +static void isp116x_delay(struct device *dev, int delay) +{ + ndelay(delay); +} + +static struct resource usb_resources[] = { + [0] = { + .start = 0x11800000, + .end = 0x11800001, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0x11800002, + .end = 0x11800003, + .flags = IORESOURCE_MEM, + }, + [2] = { + /* Filled in later */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct isp116x_platform_data usb_platform_data = { + .sel15Kres = 1, + .oc_enable = 1, + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_enable = 0, + .delay = isp116x_delay, +}; + +static struct platform_device usb_device = { + .name = "isp116x-hcd", + .id = -1, + .num_resources = ARRAY_SIZE(usb_resources), + .resource = usb_resources, + .dev = { + .platform_data = &usb_platform_data, + }, + +}; + +static struct platform_device *sh7343se_platform_devices[] __initdata = { + &heartbeat_device, + &nor_flash_device, + &uart_device, + &usb_device, +}; + +static int __init sh7343se_devices_setup(void) +{ + /* Wire-up dynamic vectors */ + serial_platform_data[0].irq = irq_find_mapping(se7343_irq_domain, + SE7343_FPGA_IRQ_UARTA); + serial_platform_data[1].irq = irq_find_mapping(se7343_irq_domain, + SE7343_FPGA_IRQ_UARTB); + usb_resources[2].start = usb_resources[2].end = + irq_find_mapping(se7343_irq_domain, SE7343_FPGA_IRQ_USB); + + return platform_add_devices(sh7343se_platform_devices, + ARRAY_SIZE(sh7343se_platform_devices)); +} +device_initcall(sh7343se_devices_setup); + +/* + * Initialize the board + */ +static void __init sh7343se_setup(char **cmdline_p) +{ + __raw_writew(0xf900, FPGA_OUT); /* FPGA */ + + __raw_writew(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */ + __raw_writew(0x0020, PORT_PSELD); + + printk(KERN_INFO "MS7343CP01 Setup...done\n"); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_7343se __initmv = { + .mv_name = "SolutionEngine 7343", + .mv_setup = sh7343se_setup, + .mv_init_irq = init_7343se_IRQ, +}; diff --git a/arch/sh/boards/se/770x/Makefile b/arch/sh/boards/mach-se/770x/Makefile index 8e624b06d5e..43ea14feef5 100644 --- a/arch/sh/boards/se/770x/Makefile +++ b/arch/sh/boards/mach-se/770x/Makefile @@ -2,4 +2,4 @@ # Makefile for the 770x SolutionEngine specific parts of the kernel # -obj-y := setup.o io.o irq.o +obj-y := setup.o irq.o diff --git a/arch/sh/boards/se/770x/irq.c b/arch/sh/boards/mach-se/770x/irq.c index cdb0807928a..1028c17b81b 100644 --- a/arch/sh/boards/se/770x/irq.c +++ b/arch/sh/boards/mach-se/770x/irq.c @@ -13,7 +13,7 @@ #include <linux/irq.h> #include <asm/irq.h> #include <asm/io.h> -#include <asm/se.h> +#include <mach-se/mach/se.h> static struct ipr_data ipr_irq_table[] = { /* @@ -96,13 +96,13 @@ static struct ipr_desc ipr_irq_desc = { void __init init_se_IRQ(void) { /* Disable all interrupts */ - ctrl_outw(0, BCR_ILCRA); - ctrl_outw(0, BCR_ILCRB); - ctrl_outw(0, BCR_ILCRC); - ctrl_outw(0, BCR_ILCRD); - ctrl_outw(0, BCR_ILCRE); - ctrl_outw(0, BCR_ILCRF); - ctrl_outw(0, BCR_ILCRG); + __raw_writew(0, BCR_ILCRA); + __raw_writew(0, BCR_ILCRB); + __raw_writew(0, BCR_ILCRC); + __raw_writew(0, BCR_ILCRD); + __raw_writew(0, BCR_ILCRE); + __raw_writew(0, BCR_ILCRF); + __raw_writew(0, BCR_ILCRG); register_ipr_controller(&ipr_irq_desc); } diff --git a/arch/sh/boards/se/770x/setup.c b/arch/sh/boards/mach-se/770x/setup.c index 318bc8a3969..658326f44df 100644 --- a/arch/sh/boards/se/770x/setup.c +++ b/arch/sh/boards/mach-se/770x/setup.c @@ -8,14 +8,13 @@ */ #include <linux/init.h> #include <linux/platform_device.h> +#include <mach-se/mach/se.h> +#include <mach-se/mach/mrshpc.h> #include <asm/machvec.h> -#include <asm/se.h> #include <asm/io.h> #include <asm/smc37c93x.h> #include <asm/heartbeat.h> -void init_se_IRQ(void); - /* * Configure the Super I/O chip */ @@ -73,7 +72,7 @@ static struct resource cf_ide_resources[] = { }, [1] = { .start = PA_MRSHPC_IO + 0x1f0 + 0x206, - .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8, + .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8, .flags = IORESOURCE_MEM, }, [2] = { @@ -94,15 +93,12 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; static struct heartbeat_data heartbeat_data = { .bit_pos = heartbeat_bit_pos, .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), - .regsize = 16, }; -static struct resource heartbeat_resources[] = { - [0] = { - .start = PA_LED, - .end = PA_LED, - .flags = IORESOURCE_MEM, - }, +static struct resource heartbeat_resource = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, }; static struct platform_device heartbeat_device = { @@ -111,17 +107,73 @@ static struct platform_device heartbeat_device = { .dev = { .platform_data = &heartbeat_data, }, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +#if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\ + defined(CONFIG_CPU_SUBTYPE_SH7712) +/* SH771X Ethernet driver */ +static struct resource sh_eth0_resources[] = { + [0] = { + .start = SH_ETH0_BASE, + .end = SH_ETH0_BASE + 0x1B8, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SH_ETH0_IRQ, + .end = SH_ETH0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh_eth0_device = { + .name = "sh771x-ether", + .id = 0, + .dev = { + .platform_data = PHY_ID, + }, + .num_resources = ARRAY_SIZE(sh_eth0_resources), + .resource = sh_eth0_resources, +}; + +static struct resource sh_eth1_resources[] = { + [0] = { + .start = SH_ETH1_BASE, + .end = SH_ETH1_BASE + 0x1B8, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SH_ETH1_IRQ, + .end = SH_ETH1_IRQ, + .flags = IORESOURCE_IRQ, + }, }; +static struct platform_device sh_eth1_device = { + .name = "sh771x-ether", + .id = 1, + .dev = { + .platform_data = PHY_ID, + }, + .num_resources = ARRAY_SIZE(sh_eth1_resources), + .resource = sh_eth1_resources, +}; +#endif + static struct platform_device *se_devices[] __initdata = { &heartbeat_device, &cf_ide_device, +#if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\ + defined(CONFIG_CPU_SUBTYPE_SH7712) + &sh_eth0_device, + &sh_eth1_device, +#endif }; static int __init se_devices_setup(void) { + mrshpc_setup_windows(); return platform_add_devices(se_devices, ARRAY_SIZE(se_devices)); } device_initcall(se_devices_setup); @@ -132,38 +184,5 @@ device_initcall(se_devices_setup); static struct sh_machine_vector mv_se __initmv = { .mv_name = "SolutionEngine", .mv_setup = smsc_setup, -#if defined(CONFIG_CPU_SH4) - .mv_nr_irqs = 48, -#elif defined(CONFIG_CPU_SUBTYPE_SH7708) - .mv_nr_irqs = 32, -#elif defined(CONFIG_CPU_SUBTYPE_SH7709) - .mv_nr_irqs = 61, -#elif defined(CONFIG_CPU_SUBTYPE_SH7705) - .mv_nr_irqs = 86, -#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) - .mv_nr_irqs = 104, -#endif - - .mv_inb = se_inb, - .mv_inw = se_inw, - .mv_inl = se_inl, - .mv_outb = se_outb, - .mv_outw = se_outw, - .mv_outl = se_outl, - - .mv_inb_p = se_inb_p, - .mv_inw_p = se_inw, - .mv_inl_p = se_inl, - .mv_outb_p = se_outb_p, - .mv_outw_p = se_outw, - .mv_outl_p = se_outl, - - .mv_insb = se_insb, - .mv_insw = se_insw, - .mv_insl = se_insl, - .mv_outsb = se_outsb, - .mv_outsw = se_outsw, - .mv_outsl = se_outsl, - .mv_init_irq = init_se_IRQ, }; diff --git a/arch/sh/boards/mach-se/7721/Makefile b/arch/sh/boards/mach-se/7721/Makefile new file mode 100644 index 00000000000..7f09030980b --- /dev/null +++ b/arch/sh/boards/mach-se/7721/Makefile @@ -0,0 +1 @@ +obj-y := setup.o irq.o diff --git a/arch/sh/boards/mach-se/7721/irq.c b/arch/sh/boards/mach-se/7721/irq.c new file mode 100644 index 00000000000..d85022ea3f1 --- /dev/null +++ b/arch/sh/boards/mach-se/7721/irq.c @@ -0,0 +1,45 @@ +/* + * linux/arch/sh/boards/se/7721/irq.c + * + * Copyright (C) 2008 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <mach-se/mach/se7721.h> + +enum { + UNUSED = 0, + + /* board specific interrupt sources */ + MRSHPC, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_IRQ(MRSHPC, MRSHPC_IRQ0), +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { FPGA_ILSR6, 0, 8, 4, /* IRLMSK */ + { 0, MRSHPC } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "SE7721", vectors, + NULL, NULL, prio_registers, NULL); + +/* + * Initialize IRQ setting + */ +void __init init_se7721_IRQ(void) +{ + /* PPCR */ + __raw_writew(__raw_readw(0xa4050118) & ~0x00ff, 0xa4050118); + + register_intc_controller(&intc_desc); + intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0); +} diff --git a/arch/sh/boards/mach-se/7721/setup.c b/arch/sh/boards/mach-se/7721/setup.c new file mode 100644 index 00000000000..a0b3dba34eb --- /dev/null +++ b/arch/sh/boards/mach-se/7721/setup.c @@ -0,0 +1,96 @@ +/* + * linux/arch/sh/boards/se/7721/setup.c + * + * Copyright (C) 2008 Renesas Solutions Corp. + * + * Hitachi UL SolutionEngine 7721 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <mach-se/mach/se7721.h> +#include <mach-se/mach/mrshpc.h> +#include <asm/machvec.h> +#include <asm/io.h> +#include <asm/heartbeat.h> + +static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), +}; + +static struct resource heartbeat_resource = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +static struct resource cf_ide_resources[] = { + [0] = { + .start = PA_MRSHPC_IO + 0x1f0, + .end = PA_MRSHPC_IO + 0x1f0 + 8 , + .flags = IORESOURCE_IO, + }, + [1] = { + .start = PA_MRSHPC_IO + 0x1f0 + 0x206, + .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8, + .flags = IORESOURCE_IO, + }, + [2] = { + .start = MRSHPC_IRQ0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_ide_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(cf_ide_resources), + .resource = cf_ide_resources, +}; + +static struct platform_device *se7721_devices[] __initdata = { + &cf_ide_device, + &heartbeat_device +}; + +static int __init se7721_devices_setup(void) +{ + mrshpc_setup_windows(); + return platform_add_devices(se7721_devices, ARRAY_SIZE(se7721_devices)); +} +device_initcall(se7721_devices_setup); + +static void __init se7721_setup(char **cmdline_p) +{ + /* for USB */ + __raw_writew(0x0000, 0xA405010C); /* PGCR */ + __raw_writew(0x0000, 0xA405010E); /* PHCR */ + __raw_writew(0x00AA, 0xA4050118); /* PPCR */ + __raw_writew(0x0000, 0xA4050124); /* PSELA */ +} + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_se7721 __initmv = { + .mv_name = "Solution Engine 7721", + .mv_setup = se7721_setup, + .mv_init_irq = init_se7721_IRQ, +}; diff --git a/arch/sh/boards/se/7722/Makefile b/arch/sh/boards/mach-se/7722/Makefile index 8694373389e..8694373389e 100644 --- a/arch/sh/boards/se/7722/Makefile +++ b/arch/sh/boards/mach-se/7722/Makefile diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c new file mode 100644 index 00000000000..f5e2af1bf04 --- /dev/null +++ b/arch/sh/boards/mach-se/7722/irq.c @@ -0,0 +1,122 @@ +/* + * Hitachi UL SolutionEngine 7722 FPGA IRQ Support. + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * Copyright (C) 2012 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#define DRV_NAME "SE7722-FPGA" +#define pr_fmt(fmt) DRV_NAME ": " fmt + +#define irq_reg_readl ioread16 +#define irq_reg_writel iowrite16 + +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/irqdomain.h> +#include <linux/io.h> +#include <linux/err.h> +#include <asm/sizes.h> +#include <mach-se/mach/se7722.h> + +#define IRQ01_BASE_ADDR 0x11800000 +#define IRQ01_MODE_REG 0 +#define IRQ01_STS_REG 4 +#define IRQ01_MASK_REG 8 + +static void __iomem *se7722_irq_regs; +struct irq_domain *se7722_irq_domain; + +static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + struct irq_data *data = irq_get_irq_data(irq); + struct irq_chip *chip = irq_data_get_irq_chip(data); + unsigned long mask; + int bit; + + chip->irq_mask_ack(data); + + mask = ioread16(se7722_irq_regs + IRQ01_STS_REG); + + for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR) + generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit)); + + chip->irq_unmask(data); +} + +static void __init se7722_domain_init(void) +{ + int i; + + se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR, + &irq_domain_simple_ops, NULL); + if (unlikely(!se7722_irq_domain)) { + printk("Failed to get IRQ domain\n"); + return; + } + + for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) { + int irq = irq_create_mapping(se7722_irq_domain, i); + + if (unlikely(irq == 0)) { + printk("Failed to allocate IRQ %d\n", i); + return; + } + } +} + +static void __init se7722_gc_init(void) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + unsigned int irq_base; + + irq_base = irq_linear_revmap(se7722_irq_domain, 0); + + gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs, + handle_level_irq); + if (unlikely(!gc)) + return; + + ct = gc->chip_types; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + + ct->regs.mask = IRQ01_MASK_REG; + + irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR), + IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); + + irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux); + irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); + + irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux); + irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); +} + +/* + * Initialize FPGA IRQs + */ +void __init init_se7722_IRQ(void) +{ + se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16); + if (unlikely(!se7722_irq_regs)) { + printk("Failed to remap IRQ01 regs\n"); + return; + } + + /* + * All FPGA IRQs disabled by default + */ + iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG); + + __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */ + + se7722_domain_init(); + se7722_gc_init(); +} diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c new file mode 100644 index 00000000000..e04e2bc4698 --- /dev/null +++ b/arch/sh/boards/mach-se/7722/setup.c @@ -0,0 +1,194 @@ +/* + * linux/arch/sh/boards/se/7722/setup.c + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * Copyright (C) 2012 Paul Mundt + * + * Hitachi UL SolutionEngine 7722 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/input.h> +#include <linux/input/sh_keysc.h> +#include <linux/irqdomain.h> +#include <linux/smc91x.h> +#include <linux/sh_intc.h> +#include <mach-se/mach/se7722.h> +#include <mach-se/mach/mrshpc.h> +#include <asm/machvec.h> +#include <asm/clock.h> +#include <asm/io.h> +#include <asm/heartbeat.h> +#include <cpu/sh7722.h> + +/* Heartbeat */ +static struct resource heartbeat_resource = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* SMC91x */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT, +}; + +static struct resource smc91x_eth_resources[] = { + [0] = { + .name = "smc91x-regs" , + .start = PA_LAN + 0x300, + .end = PA_LAN + 0x300 + 0x10 , + .flags = IORESOURCE_MEM, + }, + [1] = { + /* Filled in later */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_eth_device = { + .name = "smc91x", + .id = 0, + .dev = { + .dma_mask = NULL, /* don't use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &smc91x_info, + }, + .num_resources = ARRAY_SIZE(smc91x_eth_resources), + .resource = smc91x_eth_resources, +}; + +static struct resource cf_ide_resources[] = { + [0] = { + .start = PA_MRSHPC_IO + 0x1f0, + .end = PA_MRSHPC_IO + 0x1f0 + 8 , + .flags = IORESOURCE_IO, + }, + [1] = { + .start = PA_MRSHPC_IO + 0x1f0 + 0x206, + .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8, + .flags = IORESOURCE_IO, + }, + [2] = { + /* Filled in later */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_ide_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(cf_ide_resources), + .resource = cf_ide_resources, +}; + +static struct sh_keysc_info sh_keysc_info = { + .mode = SH_KEYSC_MODE_1, /* KEYOUT0->5, KEYIN0->4 */ + .scan_timing = 3, + .delay = 5, + .keycodes = { /* SW1 -> SW30 */ + KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, + KEY_F, KEY_G, KEY_H, KEY_I, KEY_J, + KEY_K, KEY_L, KEY_M, KEY_N, KEY_O, + KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, + KEY_U, KEY_V, KEY_W, KEY_X, KEY_Y, + KEY_Z, + KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE, /* life */ + }, +}; + +static struct resource sh_keysc_resources[] = { + [0] = { + .start = 0x044b0000, + .end = 0x044b000f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xbe0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh_keysc_device = { + .name = "sh_keysc", + .id = 0, /* "keysc0" clock */ + .num_resources = ARRAY_SIZE(sh_keysc_resources), + .resource = sh_keysc_resources, + .dev = { + .platform_data = &sh_keysc_info, + }, +}; + +static struct platform_device *se7722_devices[] __initdata = { + &heartbeat_device, + &smc91x_eth_device, + &cf_ide_device, + &sh_keysc_device, +}; + +static int __init se7722_devices_setup(void) +{ + mrshpc_setup_windows(); + + /* Wire-up dynamic vectors */ + cf_ide_resources[2].start = cf_ide_resources[2].end = + irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_MRSHPC0); + + smc91x_eth_resources[1].start = smc91x_eth_resources[1].end = + irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_SMC); + + return platform_add_devices(se7722_devices, ARRAY_SIZE(se7722_devices)); +} +device_initcall(se7722_devices_setup); + +static void __init se7722_setup(char **cmdline_p) +{ + __raw_writew(0x010D, FPGA_OUT); /* FPGA */ + + __raw_writew(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */ + __raw_writew(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */ + + /* LCDC I/O */ + __raw_writew(0x0020, PORT_PSELD); + + /* SIOF1*/ + __raw_writew(0x0003, PORT_PSELB); + __raw_writew(0xe000, PORT_PSELC); + __raw_writew(0x0000, PORT_PKCR); + + /* LCDC */ + __raw_writew(0x4020, PORT_PHCR); + __raw_writew(0x0000, PORT_PLCR); + __raw_writew(0x0000, PORT_PMCR); + __raw_writew(0x0002, PORT_PRCR); + __raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */ + + /* KEYSC */ + __raw_writew(0x0A10, PORT_PSELA); /* BS,SHHID2 */ + __raw_writew(0x0000, PORT_PYCR); + __raw_writew(0x0000, PORT_PZCR); + __raw_writew(__raw_readw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA); + __raw_writew(__raw_readw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_se7722 __initmv = { + .mv_name = "Solution Engine 7722" , + .mv_setup = se7722_setup , + .mv_init_irq = init_se7722_IRQ, +}; diff --git a/arch/sh/boards/mach-se/7724/Makefile b/arch/sh/boards/mach-se/7724/Makefile new file mode 100644 index 00000000000..a08b36830f0 --- /dev/null +++ b/arch/sh/boards/mach-se/7724/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the HITACHI UL SolutionEngine 7724 specific parts of the kernel +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# + +obj-y := setup.o irq.o sdram.o diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c new file mode 100644 index 00000000000..5d1d3ec9a6c --- /dev/null +++ b/arch/sh/boards/mach-se/7724/irq.c @@ -0,0 +1,145 @@ +/* + * linux/arch/sh/boards/se/7724/irq.c + * + * Copyright (C) 2009 Renesas Solutions Corp. + * + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + * + * Based on linux/arch/sh/boards/se/7722/irq.c + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * Hitachi UL SolutionEngine 7724 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/export.h> +#include <linux/topology.h> +#include <linux/io.h> +#include <linux/err.h> +#include <mach-se/mach/se7724.h> + +struct fpga_irq { + unsigned long sraddr; + unsigned long mraddr; + unsigned short mask; + unsigned int base; +}; + +static unsigned int fpga2irq(unsigned int irq) +{ + if (irq >= IRQ0_BASE && + irq <= IRQ0_END) + return IRQ0_IRQ; + else if (irq >= IRQ1_BASE && + irq <= IRQ1_END) + return IRQ1_IRQ; + else + return IRQ2_IRQ; +} + +static struct fpga_irq get_fpga_irq(unsigned int irq) +{ + struct fpga_irq set; + + switch (irq) { + case IRQ0_IRQ: + set.sraddr = IRQ0_SR; + set.mraddr = IRQ0_MR; + set.mask = IRQ0_MASK; + set.base = IRQ0_BASE; + break; + case IRQ1_IRQ: + set.sraddr = IRQ1_SR; + set.mraddr = IRQ1_MR; + set.mask = IRQ1_MASK; + set.base = IRQ1_BASE; + break; + default: + set.sraddr = IRQ2_SR; + set.mraddr = IRQ2_MR; + set.mask = IRQ2_MASK; + set.base = IRQ2_BASE; + break; + } + + return set; +} + +static void disable_se7724_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + struct fpga_irq set = get_fpga_irq(fpga2irq(irq)); + unsigned int bit = irq - set.base; + __raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr); +} + +static void enable_se7724_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + struct fpga_irq set = get_fpga_irq(fpga2irq(irq)); + unsigned int bit = irq - set.base; + __raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr); +} + +static struct irq_chip se7724_irq_chip __read_mostly = { + .name = "SE7724-FPGA", + .irq_mask = disable_se7724_irq, + .irq_unmask = enable_se7724_irq, +}; + +static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + struct fpga_irq set = get_fpga_irq(irq); + unsigned short intv = __raw_readw(set.sraddr); + unsigned int ext_irq = set.base; + + intv &= set.mask; + + for (; intv; intv >>= 1, ext_irq++) { + if (!(intv & 1)) + continue; + + generic_handle_irq(ext_irq); + } +} + +/* + * Initialize IRQ setting + */ +void __init init_se7724_IRQ(void) +{ + int irq_base, i; + + __raw_writew(0xffff, IRQ0_MR); /* mask all */ + __raw_writew(0xffff, IRQ1_MR); /* mask all */ + __raw_writew(0xffff, IRQ2_MR); /* mask all */ + __raw_writew(0x0000, IRQ0_SR); /* clear irq */ + __raw_writew(0x0000, IRQ1_SR); /* clear irq */ + __raw_writew(0x0000, IRQ2_SR); /* clear irq */ + __raw_writew(0x002a, IRQ_MODE); /* set irq type */ + + irq_base = irq_alloc_descs(SE7724_FPGA_IRQ_BASE, SE7724_FPGA_IRQ_BASE, + SE7724_FPGA_IRQ_NR, numa_node_id()); + if (IS_ERR_VALUE(irq_base)) { + pr_err("%s: failed hooking irqs for FPGA\n", __func__); + return; + } + + for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) + irq_set_chip_and_handler_name(irq_base + i, &se7724_irq_chip, + handle_level_irq, "level"); + + irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux); + irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); + + irq_set_chained_handler(IRQ1_IRQ, se7724_irq_demux); + irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); + + irq_set_chained_handler(IRQ2_IRQ, se7724_irq_demux); + irq_set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW); +} diff --git a/arch/sh/boards/mach-se/7724/sdram.S b/arch/sh/boards/mach-se/7724/sdram.S new file mode 100644 index 00000000000..6fa4734d09c --- /dev/null +++ b/arch/sh/boards/mach-se/7724/sdram.S @@ -0,0 +1,131 @@ +/* + * MS7724SE sdram self/auto-refresh setup code + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/sys.h> +#include <linux/errno.h> +#include <linux/linkage.h> +#include <asm/asm-offsets.h> +#include <asm/suspend.h> +#include <asm/romimage-macros.h> + +/* code to enter and leave self-refresh. must be self-contained. + * this code will be copied to on-chip memory and executed from there. + */ + .balign 4 +ENTRY(ms7724se_sdram_enter_start) + + /* DBSC: put memory in self-refresh mode */ + + ED 0xFD000010, 0x00000000 /* DBEN */ + ED 0xFD000040, 0x00000000 /* DBRFPDN0 */ + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000040, 0x00000001 /* DBRFPDN0 */ + + rts + nop + +ENTRY(ms7724se_sdram_enter_end) + + .balign 4 +ENTRY(ms7724se_sdram_leave_start) + + /* DBSC: put memory in auto-refresh mode */ + + mov.l @(SH_SLEEP_MODE, r5), r0 + tst #SUSP_SH_RSTANDBY, r0 + bf resume_rstandby + + ED 0xFD000040, 0x00000000 /* DBRFPDN0 */ + WAIT 1 + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000010, 0x00000001 /* DBEN */ + ED 0xFD000040, 0x00010000 /* DBRFPDN0 */ + + rts + nop + +resume_rstandby: + + /* CPG: setup clocks before restarting external memory */ + + ED 0xA4150024, 0x00004000 /* PLLCR */ + + mov.l FRQCRA,r0 + mov.l @r0,r3 + mov.l KICK,r1 + or r1, r3 + mov.l r3, @r0 + + mov.l LSTATS,r0 + mov #1,r1 +WAIT_LSTATS: + mov.l @r0,r3 + tst r1,r3 + bf WAIT_LSTATS + + /* DBSC: re-initialize and put in auto-refresh */ + + ED 0xFD000108, 0x00000181 /* DBPDCNT0 */ + ED 0xFD000020, 0x015B0002 /* DBCONF */ + ED 0xFD000030, 0x03071502 /* DBTR0 */ + ED 0xFD000034, 0x02020102 /* DBTR1 */ + ED 0xFD000038, 0x01090405 /* DBTR2 */ + ED 0xFD00003C, 0x00000002 /* DBTR3 */ + ED 0xFD000008, 0x00000005 /* DBKIND */ + ED 0xFD000040, 0x00000001 /* DBRFPDN0 */ + ED 0xFD000040, 0x00000000 /* DBRFPDN0 */ + ED 0xFD000018, 0x00000001 /* DBCKECNT */ + + mov #100,r0 +WAIT_400NS: + dt r0 + bf WAIT_400NS + + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000060, 0x00020000 /* DBMRCNT (EMR2) */ + ED 0xFD000060, 0x00030000 /* DBMRCNT (EMR3) */ + ED 0xFD000060, 0x00010004 /* DBMRCNT (EMR) */ + ED 0xFD000060, 0x00000532 /* DBMRCNT (MRS) */ + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000060, 0x00000432 /* DBMRCNT (MRS) */ + ED 0xFD000060, 0x000103c0 /* DBMRCNT (EMR) */ + ED 0xFD000060, 0x00010040 /* DBMRCNT (EMR) */ + + mov #100,r0 +WAIT_400NS_2: + dt r0 + bf WAIT_400NS_2 + + ED 0xFD000010, 0x00000001 /* DBEN */ + ED 0xFD000044, 0x0000050f /* DBRFPDN1 */ + ED 0xFD000048, 0x236800e6 /* DBRFPDN2 */ + + mov.l DUMMY,r0 + mov.l @r0, r1 /* force single dummy read */ + + ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */ + ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */ + ED 0xFD000108, 0x00000080 /* DBPDCNT0 */ + ED 0xFD000040, 0x00010000 /* DBRFPDN0 */ + + rts + nop + + .balign 4 +DUMMY: .long 0xac400000 +FRQCRA: .long 0xa4150000 +KICK: .long 0x80000000 +LSTATS: .long 0xa4150060 + +ENTRY(ms7724se_sdram_leave_end) diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c new file mode 100644 index 00000000000..1162bc6945a --- /dev/null +++ b/arch/sh/boards/mach-se/7724/setup.c @@ -0,0 +1,946 @@ +/* + * linux/arch/sh/boards/se/7724/setup.c + * + * Copyright (C) 2009 Renesas Solutions Corp. + * + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> +#include <linux/mtd/physmap.h> +#include <linux/delay.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/smc91x.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/input/sh_keysc.h> +#include <linux/usb/r8a66597.h> +#include <linux/sh_eth.h> +#include <linux/sh_intc.h> +#include <linux/videodev2.h> +#include <video/sh_mobile_lcdc.h> +#include <media/sh_mobile_ceu.h> +#include <sound/sh_fsi.h> +#include <sound/simple_card.h> +#include <asm/io.h> +#include <asm/heartbeat.h> +#include <asm/clock.h> +#include <asm/suspend.h> +#include <cpu/sh7724.h> +#include <mach-se/mach/se7724.h> + +/* + * SWx 1234 5678 + * ------------------------------------ + * SW31 : 1001 1100 : default + * SW32 : 0111 1111 : use on board flash + * + * SW41 : abxx xxxx -> a = 0 : Analog monitor + * 1 : Digital monitor + * b = 0 : VGA + * 1 : 720p + */ + +/* + * about 720p + * + * When you use 1280 x 720 lcdc output, + * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz, + * and change SW41 to use 720p + */ + +/* + * about sound + * + * This setup.c supports FSI slave mode. + * Please change J20, J21, J22 pin to 1-2 connection. + */ + +/* Heartbeat */ +static struct resource heartbeat_resource = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* LAN91C111 */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, +}; + +static struct resource smc91x_eth_resources[] = { + [0] = { + .name = "SMC91C111" , + .start = 0x1a300300, + .end = 0x1a30030f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ0_SMC, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct platform_device smc91x_eth_device = { + .name = "smc91x", + .num_resources = ARRAY_SIZE(smc91x_eth_resources), + .resource = smc91x_eth_resources, + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* MTD */ +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "uboot", + .offset = 0, + .size = (1 * 1024 * 1024), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = (2 * 1024 * 1024), + }, { + .name = "free-area", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x01ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .resource = nor_flash_resources, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .dev = { + .platform_data = &nor_flash_data, + }, +}; + +/* LCDC */ +static const struct fb_videomode lcdc_720p_modes[] = { + { + .name = "LB070WV1", + .sync = 0, /* hsync and vsync are active low */ + .xres = 1280, + .yres = 720, + .left_margin = 220, + .right_margin = 110, + .hsync_len = 40, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + }, +}; + +static const struct fb_videomode lcdc_vga_modes[] = { + { + .name = "LB070WV1", + .sync = 0, /* hsync and vsync are active low */ + .xres = 640, + .yres = 480, + .left_margin = 105, + .right_margin = 50, + .hsync_len = 96, + .upper_margin = 33, + .lower_margin = 10, + .vsync_len = 2, + }, +}; + +static struct sh_mobile_lcdc_info lcdc_info = { + .clock_source = LCDC_CLK_EXTERNAL, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .fourcc = V4L2_PIX_FMT_RGB565, + .clock_divider = 1, + .panel_cfg = { /* 7.0 inch */ + .width = 152, + .height = 91, + }, + } +}; + +static struct resource lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, + .end = 0xfe942fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xf40), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(lcdc_resources), + .resource = lcdc_resources, + .dev = { + .platform_data = &lcdc_info, + }, +}; + +/* CEU0 */ +static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource ceu0_resources[] = { + [0] = { + .name = "CEU0", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x880), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu0_device = { + .name = "sh_mobile_ceu", + .id = 0, /* "ceu0" clock */ + .num_resources = ARRAY_SIZE(ceu0_resources), + .resource = ceu0_resources, + .dev = { + .platform_data = &sh_mobile_ceu0_info, + }, +}; + +/* CEU1 */ +static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { + .flags = SH_CEU_FLAG_USE_8BIT_BUS, +}; + +static struct resource ceu1_resources[] = { + [0] = { + .name = "CEU1", + .start = 0xfe914000, + .end = 0xfe91409f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x9e0), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu1_device = { + .name = "sh_mobile_ceu", + .id = 1, /* "ceu1" clock */ + .num_resources = ARRAY_SIZE(ceu1_resources), + .resource = ceu1_resources, + .dev = { + .platform_data = &sh_mobile_ceu1_info, + }, +}; + +/* FSI */ +/* change J20, J21, J22 pin to 1-2 connection to use slave mode */ +static struct resource fsi_resources[] = { + [0] = { + .name = "FSI", + .start = 0xFE3C0000, + .end = 0xFE3C021d, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xf80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device fsi_device = { + .name = "sh_fsi", + .id = 0, + .num_resources = ARRAY_SIZE(fsi_resources), + .resource = fsi_resources, +}; + +static struct asoc_simple_card_info fsi_ak4642_info = { + .name = "AK4642", + .card = "FSIA-AK4642", + .codec = "ak4642-codec.0-0012", + .platform = "sh_fsi.0", + .daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM, + .cpu_dai = { + .name = "fsia-dai", + }, + .codec_dai = { + .name = "ak4642-hifi", + .sysclk = 11289600, + }, +}; + +static struct platform_device fsi_ak4642_device = { + .name = "asoc-simple-card", + .dev = { + .platform_data = &fsi_ak4642_info, + }, +}; + +/* KEYSC in SoC (Needs SW33-2 set to ON) */ +static struct sh_keysc_info keysc_info = { + .mode = SH_KEYSC_MODE_1, + .scan_timing = 3, + .delay = 50, + .keycodes = { + KEY_1, KEY_2, KEY_3, KEY_4, KEY_5, + KEY_6, KEY_7, KEY_8, KEY_9, KEY_A, + KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, + KEY_G, KEY_H, KEY_I, KEY_K, KEY_L, + KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q, + KEY_R, KEY_S, KEY_T, KEY_U, KEY_V, + }, +}; + +static struct resource keysc_resources[] = { + [0] = { + .name = "KEYSC", + .start = 0x044b0000, + .end = 0x044b000f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xbe0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device keysc_device = { + .name = "sh_keysc", + .id = 0, /* "keysc0" clock */ + .num_resources = ARRAY_SIZE(keysc_resources), + .resource = keysc_resources, + .dev = { + .platform_data = &keysc_info, + }, +}; + +/* SH Eth */ +static struct resource sh_eth_resources[] = { + [0] = { + .start = SH_ETH_ADDR, + .end = SH_ETH_ADDR + 0x1FC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xd60), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct sh_eth_plat_data sh_eth_plat = { + .phy = 0x1f, /* SMSC LAN8187 */ + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device sh_eth_device = { + .name = "sh7724-ether", + .id = 0, + .dev = { + .platform_data = &sh_eth_plat, + }, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .resource = sh_eth_resources, +}; + +static struct r8a66597_platdata sh7724_usb0_host_data = { + .on_chip = 1, +}; + +static struct resource sh7724_usb0_host_resources[] = { + [0] = { + .start = 0xa4d80000, + .end = 0xa4d80124 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device sh7724_usb0_host_device = { + .name = "r8a66597_hcd", + .id = 0, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &sh7724_usb0_host_data, + }, + .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources), + .resource = sh7724_usb0_host_resources, +}; + +static struct r8a66597_platdata sh7724_usb1_gadget_data = { + .on_chip = 1, +}; + +static struct resource sh7724_usb1_gadget_resources[] = { + [0] = { + .start = 0xa4d90000, + .end = 0xa4d90123, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xa40), + .end = evt2irq(0xa40), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device sh7724_usb1_gadget_device = { + .name = "r8a66597_udc", + .id = 1, /* USB1 */ + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &sh7724_usb1_gadget_data, + }, + .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources), + .resource = sh7724_usb1_gadget_resources, +}; + +/* Fixed 3.3V regulator to be used by SDHI0, SDHI1 */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), +}; + +static struct resource sdhi0_cn7_resources[] = { + [0] = { + .name = "SDHI0", + .start = 0x04ce0000, + .end = 0x04ce00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0xe80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mobile_sdhi_info sh7724_sdhi0_data = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, + .tmio_caps = MMC_CAP_SDIO_IRQ, +}; + +static struct platform_device sdhi0_cn7_device = { + .name = "sh_mobile_sdhi", + .id = 0, + .num_resources = ARRAY_SIZE(sdhi0_cn7_resources), + .resource = sdhi0_cn7_resources, + .dev = { + .platform_data = &sh7724_sdhi0_data, + }, +}; + +static struct resource sdhi1_cn8_resources[] = { + [0] = { + .name = "SDHI1", + .start = 0x04cf0000, + .end = 0x04cf00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x4e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mobile_sdhi_info sh7724_sdhi1_data = { + .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, + .tmio_caps = MMC_CAP_SDIO_IRQ, +}; + +static struct platform_device sdhi1_cn8_device = { + .name = "sh_mobile_sdhi", + .id = 1, + .num_resources = ARRAY_SIZE(sdhi1_cn8_resources), + .resource = sdhi1_cn8_resources, + .dev = { + .platform_data = &sh7724_sdhi1_data, + }, +}; + +/* IrDA */ +static struct resource irda_resources[] = { + [0] = { + .name = "IrDA", + .start = 0xA45D0000, + .end = 0xA45D0049, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x480), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device irda_device = { + .name = "sh_sir", + .num_resources = ARRAY_SIZE(irda_resources), + .resource = irda_resources, +}; + +#include <media/ak881x.h> +#include <media/sh_vou.h> + +static struct ak881x_pdata ak881x_pdata = { + .flags = AK881X_IF_MODE_SLAVE, +}; + +static struct i2c_board_info ak8813 = { + /* With open J18 jumper address is 0x21 */ + I2C_BOARD_INFO("ak8813", 0x20), + .platform_data = &ak881x_pdata, +}; + +static struct sh_vou_pdata sh_vou_pdata = { + .bus_fmt = SH_VOU_BUS_8BIT, + .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, + .board_info = &ak8813, + .i2c_adap = 0, +}; + +static struct resource sh_vou_resources[] = { + [0] = { + .start = 0xfe960000, + .end = 0xfe962043, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x8e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vou_device = { + .name = "sh-vou", + .id = -1, + .num_resources = ARRAY_SIZE(sh_vou_resources), + .resource = sh_vou_resources, + .dev = { + .platform_data = &sh_vou_pdata, + }, +}; + +static struct platform_device *ms7724se_devices[] __initdata = { + &heartbeat_device, + &smc91x_eth_device, + &lcdc_device, + &nor_flash_device, + &ceu0_device, + &ceu1_device, + &keysc_device, + &sh_eth_device, + &sh7724_usb0_host_device, + &sh7724_usb1_gadget_device, + &fsi_device, + &fsi_ak4642_device, + &sdhi0_cn7_device, + &sdhi1_cn8_device, + &irda_device, + &vou_device, +}; + +/* I2C device */ +static struct i2c_board_info i2c0_devices[] = { + { + I2C_BOARD_INFO("ak4642", 0x12), + }, +}; + +#define EEPROM_OP 0xBA206000 +#define EEPROM_ADR 0xBA206004 +#define EEPROM_DATA 0xBA20600C +#define EEPROM_STAT 0xBA206010 +#define EEPROM_STRT 0xBA206014 + +static int __init sh_eth_is_eeprom_ready(void) +{ + int t = 10000; + + while (t--) { + if (!__raw_readw(EEPROM_STAT)) + return 1; + udelay(1); + } + + printk(KERN_ERR "ms7724se can not access to eeprom\n"); + return 0; +} + +static void __init sh_eth_init(void) +{ + int i; + u16 mac; + + /* check EEPROM status */ + if (!sh_eth_is_eeprom_ready()) + return; + + /* read MAC addr from EEPROM */ + for (i = 0 ; i < 3 ; i++) { + __raw_writew(0x0, EEPROM_OP); /* read */ + __raw_writew(i*2, EEPROM_ADR); + __raw_writew(0x1, EEPROM_STRT); + if (!sh_eth_is_eeprom_ready()) + return; + + mac = __raw_readw(EEPROM_DATA); + sh_eth_plat.mac_addr[i << 1] = mac & 0xff; + sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8; + } +} + +#define SW4140 0xBA201000 +#define FPGA_OUT 0xBA200400 +#define PORT_HIZA 0xA4050158 +#define PORT_MSELCRB 0xA4050182 + +#define SW41_A 0x0100 +#define SW41_B 0x0200 +#define SW41_C 0x0400 +#define SW41_D 0x0800 +#define SW41_E 0x1000 +#define SW41_F 0x2000 +#define SW41_G 0x4000 +#define SW41_H 0x8000 + +extern char ms7724se_sdram_enter_start; +extern char ms7724se_sdram_enter_end; +extern char ms7724se_sdram_leave_start; +extern char ms7724se_sdram_leave_end; + +static int __init arch_setup(void) +{ + /* enable I2C device */ + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); + return 0; +} +arch_initcall(arch_setup); + +static int __init devices_setup(void) +{ + u16 sw = __raw_readw(SW4140); /* select camera, monitor */ + struct clk *clk; + u16 fpga_out; + + /* register board specific self-refresh code */ + sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | + SUSP_SH_RSTANDBY, + &ms7724se_sdram_enter_start, + &ms7724se_sdram_enter_end, + &ms7724se_sdram_leave_start, + &ms7724se_sdram_leave_end); + + regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + + /* Reset Release */ + fpga_out = __raw_readw(FPGA_OUT); + /* bit4: NTSC_PDN, bit5: NTSC_RESET */ + fpga_out &= ~((1 << 1) | /* LAN */ + (1 << 4) | /* AK8813 PDN */ + (1 << 5) | /* AK8813 RESET */ + (1 << 6) | /* VIDEO DAC */ + (1 << 7) | /* AK4643 */ + (1 << 8) | /* IrDA */ + (1 << 12) | /* USB0 */ + (1 << 14)); /* RMII */ + __raw_writew(fpga_out | (1 << 4), FPGA_OUT); + + udelay(10); + + /* AK8813 RESET */ + __raw_writew(fpga_out | (1 << 5), FPGA_OUT); + + udelay(10); + + __raw_writew(fpga_out, FPGA_OUT); + + /* turn on USB clocks, use external clock */ + __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); + + /* Let LED9 show STATUS2 */ + gpio_request(GPIO_FN_STATUS2, NULL); + + /* Lit LED10 show STATUS0 */ + gpio_request(GPIO_FN_STATUS0, NULL); + + /* Lit LED11 show PDSTATUS */ + gpio_request(GPIO_FN_PDSTATUS, NULL); + + /* enable USB0 port */ + __raw_writew(0x0600, 0xa40501d4); + + /* enable USB1 port */ + __raw_writew(0x0600, 0xa4050192); + + /* enable IRQ 0,1,2 */ + gpio_request(GPIO_FN_INTC_IRQ0, NULL); + gpio_request(GPIO_FN_INTC_IRQ1, NULL); + gpio_request(GPIO_FN_INTC_IRQ2, NULL); + + /* enable SCIFA3 */ + gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); + gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); + gpio_request(GPIO_FN_SCIF3_I_TXD, NULL); + gpio_request(GPIO_FN_SCIF3_I_CTS, NULL); + gpio_request(GPIO_FN_SCIF3_I_RTS, NULL); + + /* enable LCDC */ + gpio_request(GPIO_FN_LCDD23, NULL); + gpio_request(GPIO_FN_LCDD22, NULL); + gpio_request(GPIO_FN_LCDD21, NULL); + gpio_request(GPIO_FN_LCDD20, NULL); + gpio_request(GPIO_FN_LCDD19, NULL); + gpio_request(GPIO_FN_LCDD18, NULL); + gpio_request(GPIO_FN_LCDD17, NULL); + gpio_request(GPIO_FN_LCDD16, NULL); + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDDISP, NULL); + gpio_request(GPIO_FN_LCDHSYN, NULL); + gpio_request(GPIO_FN_LCDDCK, NULL); + gpio_request(GPIO_FN_LCDVSYN, NULL); + gpio_request(GPIO_FN_LCDDON, NULL); + gpio_request(GPIO_FN_LCDVEPWC, NULL); + gpio_request(GPIO_FN_LCDVCPWC, NULL); + gpio_request(GPIO_FN_LCDRD, NULL); + gpio_request(GPIO_FN_LCDLCLK, NULL); + __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); + + /* enable CEU0 */ + gpio_request(GPIO_FN_VIO0_D15, NULL); + gpio_request(GPIO_FN_VIO0_D14, NULL); + gpio_request(GPIO_FN_VIO0_D13, NULL); + gpio_request(GPIO_FN_VIO0_D12, NULL); + gpio_request(GPIO_FN_VIO0_D11, NULL); + gpio_request(GPIO_FN_VIO0_D10, NULL); + gpio_request(GPIO_FN_VIO0_D9, NULL); + gpio_request(GPIO_FN_VIO0_D8, NULL); + gpio_request(GPIO_FN_VIO0_D7, NULL); + gpio_request(GPIO_FN_VIO0_D6, NULL); + gpio_request(GPIO_FN_VIO0_D5, NULL); + gpio_request(GPIO_FN_VIO0_D4, NULL); + gpio_request(GPIO_FN_VIO0_D3, NULL); + gpio_request(GPIO_FN_VIO0_D2, NULL); + gpio_request(GPIO_FN_VIO0_D1, NULL); + gpio_request(GPIO_FN_VIO0_D0, NULL); + gpio_request(GPIO_FN_VIO0_VD, NULL); + gpio_request(GPIO_FN_VIO0_CLK, NULL); + gpio_request(GPIO_FN_VIO0_FLD, NULL); + gpio_request(GPIO_FN_VIO0_HD, NULL); + platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); + + /* enable CEU1 */ + gpio_request(GPIO_FN_VIO1_D7, NULL); + gpio_request(GPIO_FN_VIO1_D6, NULL); + gpio_request(GPIO_FN_VIO1_D5, NULL); + gpio_request(GPIO_FN_VIO1_D4, NULL); + gpio_request(GPIO_FN_VIO1_D3, NULL); + gpio_request(GPIO_FN_VIO1_D2, NULL); + gpio_request(GPIO_FN_VIO1_D1, NULL); + gpio_request(GPIO_FN_VIO1_D0, NULL); + gpio_request(GPIO_FN_VIO1_FLD, NULL); + gpio_request(GPIO_FN_VIO1_HD, NULL); + gpio_request(GPIO_FN_VIO1_VD, NULL); + gpio_request(GPIO_FN_VIO1_CLK, NULL); + platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); + + /* KEYSC */ + gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); + gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); + gpio_request(GPIO_FN_KEYIN4, NULL); + gpio_request(GPIO_FN_KEYIN3, NULL); + gpio_request(GPIO_FN_KEYIN2, NULL); + gpio_request(GPIO_FN_KEYIN1, NULL); + gpio_request(GPIO_FN_KEYIN0, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT0, NULL); + + /* enable FSI */ + gpio_request(GPIO_FN_FSIMCKA, NULL); + gpio_request(GPIO_FN_FSIIASD, NULL); + gpio_request(GPIO_FN_FSIOASD, NULL); + gpio_request(GPIO_FN_FSIIABCK, NULL); + gpio_request(GPIO_FN_FSIIALRCK, NULL); + gpio_request(GPIO_FN_FSIOABCK, NULL); + gpio_request(GPIO_FN_FSIOALRCK, NULL); + gpio_request(GPIO_FN_CLKAUDIOAO, NULL); + + /* set SPU2 clock to 83.4 MHz */ + clk = clk_get(NULL, "spu_clk"); + if (!IS_ERR(clk)) { + clk_set_rate(clk, clk_round_rate(clk, 83333333)); + clk_put(clk); + } + + /* change parent of FSI A */ + clk = clk_get(NULL, "fsia_clk"); + if (!IS_ERR(clk)) { + /* 48kHz dummy clock was used to make sure 1/1 divide */ + clk_set_rate(&sh7724_fsimcka_clk, 48000); + clk_set_parent(clk, &sh7724_fsimcka_clk); + clk_set_rate(clk, 48000); + clk_put(clk); + } + + /* SDHI0 connected to cn7 */ + gpio_request(GPIO_FN_SDHI0CD, NULL); + gpio_request(GPIO_FN_SDHI0WP, NULL); + gpio_request(GPIO_FN_SDHI0D3, NULL); + gpio_request(GPIO_FN_SDHI0D2, NULL); + gpio_request(GPIO_FN_SDHI0D1, NULL); + gpio_request(GPIO_FN_SDHI0D0, NULL); + gpio_request(GPIO_FN_SDHI0CMD, NULL); + gpio_request(GPIO_FN_SDHI0CLK, NULL); + + /* SDHI1 connected to cn8 */ + gpio_request(GPIO_FN_SDHI1CD, NULL); + gpio_request(GPIO_FN_SDHI1WP, NULL); + gpio_request(GPIO_FN_SDHI1D3, NULL); + gpio_request(GPIO_FN_SDHI1D2, NULL); + gpio_request(GPIO_FN_SDHI1D1, NULL); + gpio_request(GPIO_FN_SDHI1D0, NULL); + gpio_request(GPIO_FN_SDHI1CMD, NULL); + gpio_request(GPIO_FN_SDHI1CLK, NULL); + + /* enable IrDA */ + gpio_request(GPIO_FN_IRDA_OUT, NULL); + gpio_request(GPIO_FN_IRDA_IN, NULL); + + /* + * enable SH-Eth + * + * please remove J33 pin from your board !! + * + * ms7724 board should not use GPIO_FN_LNKSTA pin + * So, This time PTX5 is set to input pin + */ + gpio_request(GPIO_FN_RMII_RXD0, NULL); + gpio_request(GPIO_FN_RMII_RXD1, NULL); + gpio_request(GPIO_FN_RMII_TXD0, NULL); + gpio_request(GPIO_FN_RMII_TXD1, NULL); + gpio_request(GPIO_FN_RMII_REF_CLK, NULL); + gpio_request(GPIO_FN_RMII_TX_EN, NULL); + gpio_request(GPIO_FN_RMII_RX_ER, NULL); + gpio_request(GPIO_FN_RMII_CRS_DV, NULL); + gpio_request(GPIO_FN_MDIO, NULL); + gpio_request(GPIO_FN_MDC, NULL); + gpio_request(GPIO_PTX5, NULL); + gpio_direction_input(GPIO_PTX5); + sh_eth_init(); + + if (sw & SW41_B) { + /* 720p */ + lcdc_info.ch[0].lcd_modes = lcdc_720p_modes; + lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes); + } else { + /* VGA */ + lcdc_info.ch[0].lcd_modes = lcdc_vga_modes; + lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes); + } + + if (sw & SW41_A) { + /* Digital monitor */ + lcdc_info.ch[0].interface_type = RGB18; + lcdc_info.ch[0].flags = 0; + } else { + /* Analog monitor */ + lcdc_info.ch[0].interface_type = RGB24; + lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; + } + + /* VOU */ + gpio_request(GPIO_FN_DV_D15, NULL); + gpio_request(GPIO_FN_DV_D14, NULL); + gpio_request(GPIO_FN_DV_D13, NULL); + gpio_request(GPIO_FN_DV_D12, NULL); + gpio_request(GPIO_FN_DV_D11, NULL); + gpio_request(GPIO_FN_DV_D10, NULL); + gpio_request(GPIO_FN_DV_D9, NULL); + gpio_request(GPIO_FN_DV_D8, NULL); + gpio_request(GPIO_FN_DV_CLKI, NULL); + gpio_request(GPIO_FN_DV_CLK, NULL); + gpio_request(GPIO_FN_DV_VSYNC, NULL); + gpio_request(GPIO_FN_DV_HSYNC, NULL); + + return platform_add_devices(ms7724se_devices, + ARRAY_SIZE(ms7724se_devices)); +} +device_initcall(devices_setup); + +static struct sh_machine_vector mv_ms7724se __initmv = { + .mv_name = "ms7724se", + .mv_init_irq = init_se7724_IRQ, +}; diff --git a/arch/sh/boards/se/7751/Makefile b/arch/sh/boards/mach-se/7751/Makefile index dbc29f3a9de..a338fd9d503 100644 --- a/arch/sh/boards/se/7751/Makefile +++ b/arch/sh/boards/mach-se/7751/Makefile @@ -2,6 +2,4 @@ # Makefile for the 7751 SolutionEngine specific parts of the kernel # -obj-y := setup.o io.o irq.o - -obj-$(CONFIG_PCI) += pci.o +obj-y := setup.o irq.o diff --git a/arch/sh/boards/se/7751/irq.c b/arch/sh/boards/mach-se/7751/irq.c index c3d12590e5d..5c9847ea1e7 100644 --- a/arch/sh/boards/se/7751/irq.c +++ b/arch/sh/boards/mach-se/7751/irq.c @@ -12,7 +12,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <asm/irq.h> -#include <asm/se7751.h> +#include <mach-se/mach/se7751.h> static struct ipr_data ipr_irq_table[] = { { 13, 3, 3, 2 }, diff --git a/arch/sh/boards/se/7751/setup.c b/arch/sh/boards/mach-se/7751/setup.c index deefbfd9259..820f4e7ba0d 100644 --- a/arch/sh/boards/se/7751/setup.c +++ b/arch/sh/boards/mach-se/7751/setup.c @@ -11,7 +11,7 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <asm/machvec.h> -#include <asm/se7751.h> +#include <mach-se/mach/se7751.h> #include <asm/io.h> #include <asm/heartbeat.h> @@ -48,31 +48,12 @@ static int __init se7751_devices_setup(void) { return platform_add_devices(se7751_devices, ARRAY_SIZE(se7751_devices)); } -__initcall(se7751_devices_setup); +device_initcall(se7751_devices_setup); /* * The Machine Vector */ static struct sh_machine_vector mv_7751se __initmv = { .mv_name = "7751 SolutionEngine", - .mv_nr_irqs = 72, - - .mv_inb = sh7751se_inb, - .mv_inw = sh7751se_inw, - .mv_inl = sh7751se_inl, - .mv_outb = sh7751se_outb, - .mv_outw = sh7751se_outw, - .mv_outl = sh7751se_outl, - - .mv_inb_p = sh7751se_inb_p, - .mv_inw_p = sh7751se_inw, - .mv_inl_p = sh7751se_inl, - .mv_outb_p = sh7751se_outb_p, - .mv_outw_p = sh7751se_outw, - .mv_outl_p = sh7751se_outl, - - .mv_insl = sh7751se_insl, - .mv_outsl = sh7751se_outsl, - .mv_init_irq = init_7751se_IRQ, }; diff --git a/arch/sh/boards/se/7780/Makefile b/arch/sh/boards/mach-se/7780/Makefile index 6b88adae3ec..6b88adae3ec 100644 --- a/arch/sh/boards/se/7780/Makefile +++ b/arch/sh/boards/mach-se/7780/Makefile diff --git a/arch/sh/boards/mach-se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c new file mode 100644 index 00000000000..d5c9edc172a --- /dev/null +++ b/arch/sh/boards/mach-se/7780/irq.c @@ -0,0 +1,68 @@ +/* + * linux/arch/sh/boards/se/7780/irq.c + * + * Copyright (C) 2006,2007 Nobuhiro Iwamatsu + * + * Hitachi UL SolutionEngine 7780 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <mach-se/mach/se7780.h> + +#define INTC_BASE 0xffd00000 +#define INTC_ICR1 (INTC_BASE+0x1c) + +/* + * Initialize IRQ setting + */ +void __init init_se7780_IRQ(void) +{ + /* enable all interrupt at FPGA */ + __raw_writew(0, FPGA_INTMSK1); + /* mask SM501 interrupt */ + __raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1); + /* enable all interrupt at FPGA */ + __raw_writew(0, FPGA_INTMSK2); + + /* set FPGA INTSEL register */ + /* FPGA + 0x06 */ + __raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) | + (IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1); + + /* FPGA + 0x08 */ + __raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) | + (IRQPIN_EXTINT3 << IRQPOS_EXTINT3) | + (IRQPIN_EXTINT2 << IRQPOS_EXTINT2) | + (IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2); + + /* FPGA + 0x0A */ + __raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); + + plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ + + /* ICR1: detect low level(for 2ndcut) */ + __raw_writel(0xAAAA0000, INTC_ICR1); + + /* + * FPGA PCISEL register initialize + * + * CPU || SLOT1 | SLOT2 | S-ATA | USB + * ------------------------------------- + * INTA || INTA | INTD | -- | INTB + * ------------------------------------- + * INTB || INTB | INTA | -- | INTC + * ------------------------------------- + * INTC || INTC | INTB | INTA | -- + * ------------------------------------- + * INTD || INTD | INTC | -- | INTA + * ------------------------------------- + */ + __raw_writew(0x0013, FPGA_PCI_INTSEL1); + __raw_writew(0xE402, FPGA_PCI_INTSEL2); +} diff --git a/arch/sh/boards/se/7780/setup.c b/arch/sh/boards/mach-se/7780/setup.c index 0f08ab3b2be..ae5a1d84fdf 100644 --- a/arch/sh/boards/se/7780/setup.c +++ b/arch/sh/boards/mach-se/7780/setup.c @@ -12,31 +12,22 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <asm/machvec.h> -#include <asm/se7780.h> +#include <mach-se/mach/se7780.h> #include <asm/io.h> #include <asm/heartbeat.h> /* Heartbeat */ -static struct heartbeat_data heartbeat_data = { - .regsize = 16, -}; - -static struct resource heartbeat_resources[] = { - [0] = { - .start = PA_LED, - .end = PA_LED, - .flags = IORESOURCE_MEM, - }, +static struct resource heartbeat_resource = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, }; static struct platform_device heartbeat_device = { .name = "heartbeat", .id = -1, - .dev = { - .platform_data = &heartbeat_data, - }, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, + .num_resources = 1, + .resource = &heartbeat_resource, }; /* SMC91x */ @@ -84,14 +75,14 @@ device_initcall(se7780_devices_setup); static void __init se7780_setup(char **cmdline_p) { /* "SH-Linux" on LED Display */ - ctrl_outw( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) ); - ctrl_outw( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) ); - ctrl_outw( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) ); - ctrl_outw( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) ); - ctrl_outw( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) ); - ctrl_outw( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) ); - ctrl_outw( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) ); - ctrl_outw( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) ); + __raw_writew( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) ); + __raw_writew( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) ); + __raw_writew( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) ); + __raw_writew( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) ); + __raw_writew( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) ); + __raw_writew( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) ); + __raw_writew( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) ); + __raw_writew( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) ); printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n"); @@ -102,15 +93,15 @@ static void __init se7780_setup(char **cmdline_p) * REQ2/GNT2 -> Serial ATA * REQ3/GNT3 -> PCI slot */ - ctrl_outw(0x0213, FPGA_REQSEL); + __raw_writew(0x0213, FPGA_REQSEL); /* GPIO setting */ - ctrl_outw(0x0000, GPIO_PECR); - ctrl_outw(ctrl_inw(GPIO_PHCR)&0xfff3, GPIO_PHCR); - ctrl_outw(0x0c00, GPIO_PMSELR); + __raw_writew(0x0000, GPIO_PECR); + __raw_writew(__raw_readw(GPIO_PHCR)&0xfff3, GPIO_PHCR); + __raw_writew(0x0c00, GPIO_PMSELR); /* iVDR Power ON */ - ctrl_outw(0x0001, FPGA_IVDRPW); + __raw_writew(0x0001, FPGA_IVDRPW); } /* @@ -119,6 +110,5 @@ static void __init se7780_setup(char **cmdline_p) static struct sh_machine_vector mv_se7780 __initmv = { .mv_name = "Solution Engine 7780" , .mv_setup = se7780_setup , - .mv_nr_irqs = 111 , .mv_init_irq = init_se7780_IRQ, }; diff --git a/arch/sh/boards/mach-se/Makefile b/arch/sh/boards/mach-se/Makefile new file mode 100644 index 00000000000..b537e238c6b --- /dev/null +++ b/arch/sh/boards/mach-se/Makefile @@ -0,0 +1,10 @@ +obj-$(CONFIG_SH_7619_SOLUTION_ENGINE) += board-se7619.o + +obj-$(CONFIG_SH_SOLUTION_ENGINE) += 770x/ +obj-$(CONFIG_SH_7206_SOLUTION_ENGINE) += 7206/ +obj-$(CONFIG_SH_7722_SOLUTION_ENGINE) += 7722/ +obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += 7751/ +obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += 7780/ +obj-$(CONFIG_SH_7343_SOLUTION_ENGINE) += 7343/ +obj-$(CONFIG_SH_7721_SOLUTION_ENGINE) += 7721/ +obj-$(CONFIG_SH_7724_SOLUTION_ENGINE) += 7724/ diff --git a/arch/sh/boards/se/7619/setup.c b/arch/sh/boards/mach-se/board-se7619.c index 1d0ef7faa10..958bcd7aacc 100644 --- a/arch/sh/boards/se/7619/setup.c +++ b/arch/sh/boards/mach-se/board-se7619.c @@ -11,11 +11,16 @@ #include <asm/io.h> #include <asm/machvec.h> +static int se7619_mode_pins(void) +{ + return MODE_PIN2 | MODE_PIN0; +} + /* * The Machine Vector */ static struct sh_machine_vector mv_se __initmv = { .mv_name = "SolutionEngine", - .mv_nr_irqs = 108, + .mv_mode_pins = se7619_mode_pins, }; diff --git a/arch/sh/boards/sh03/Makefile b/arch/sh/boards/mach-sh03/Makefile index 400306a796e..400306a796e 100644 --- a/arch/sh/boards/sh03/Makefile +++ b/arch/sh/boards/mach-sh03/Makefile diff --git a/arch/sh/boards/sh03/rtc.c b/arch/sh/boards/mach-sh03/rtc.c index 0a9266bb51c..f83ac7995d0 100644 --- a/arch/sh/boards/sh03/rtc.c +++ b/arch/sh/boards/mach-sh03/rtc.c @@ -35,24 +35,24 @@ #define RTC_BUSY 1 #define RTC_STOP 2 -extern spinlock_t rtc_lock; +static DEFINE_SPINLOCK(sh03_rtc_lock); unsigned long get_cmos_time(void) { unsigned int year, mon, day, hour, min, sec; - spin_lock(&rtc_lock); + spin_lock(&sh03_rtc_lock); again: do { - sec = (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10; - min = (ctrl_inb(RTC_MIN1) & 0xf) + (ctrl_inb(RTC_MIN10) & 0xf) * 10; - hour = (ctrl_inb(RTC_HOU1) & 0xf) + (ctrl_inb(RTC_HOU10) & 0xf) * 10; - day = (ctrl_inb(RTC_DAY1) & 0xf) + (ctrl_inb(RTC_DAY10) & 0xf) * 10; - mon = (ctrl_inb(RTC_MON1) & 0xf) + (ctrl_inb(RTC_MON10) & 0xf) * 10; - year = (ctrl_inb(RTC_YEA1) & 0xf) + (ctrl_inb(RTC_YEA10) & 0xf) * 10 - + (ctrl_inb(RTC_YEA100 ) & 0xf) * 100 - + (ctrl_inb(RTC_YEA1000) & 0xf) * 1000; - } while (sec != (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10); + sec = (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10; + min = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10; + hour = (__raw_readb(RTC_HOU1) & 0xf) + (__raw_readb(RTC_HOU10) & 0xf) * 10; + day = (__raw_readb(RTC_DAY1) & 0xf) + (__raw_readb(RTC_DAY10) & 0xf) * 10; + mon = (__raw_readb(RTC_MON1) & 0xf) + (__raw_readb(RTC_MON10) & 0xf) * 10; + year = (__raw_readb(RTC_YEA1) & 0xf) + (__raw_readb(RTC_YEA10) & 0xf) * 10 + + (__raw_readb(RTC_YEA100 ) & 0xf) * 100 + + (__raw_readb(RTC_YEA1000) & 0xf) * 1000; + } while (sec != (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10); if (year == 0 || mon < 1 || mon > 12 || day > 31 || day < 1 || hour > 23 || min > 59 || sec > 59) { printk(KERN_ERR @@ -60,20 +60,20 @@ unsigned long get_cmos_time(void) printk("year=%d, mon=%d, day=%d, hour=%d, min=%d, sec=%d\n", year, mon, day, hour, min, sec); - ctrl_outb(0, RTC_SEC1); ctrl_outb(0, RTC_SEC10); - ctrl_outb(0, RTC_MIN1); ctrl_outb(0, RTC_MIN10); - ctrl_outb(0, RTC_HOU1); ctrl_outb(0, RTC_HOU10); - ctrl_outb(6, RTC_WEE1); - ctrl_outb(1, RTC_DAY1); ctrl_outb(0, RTC_DAY10); - ctrl_outb(1, RTC_MON1); ctrl_outb(0, RTC_MON10); - ctrl_outb(0, RTC_YEA1); ctrl_outb(0, RTC_YEA10); - ctrl_outb(0, RTC_YEA100); - ctrl_outb(2, RTC_YEA1000); - ctrl_outb(0, RTC_CTL); + __raw_writeb(0, RTC_SEC1); __raw_writeb(0, RTC_SEC10); + __raw_writeb(0, RTC_MIN1); __raw_writeb(0, RTC_MIN10); + __raw_writeb(0, RTC_HOU1); __raw_writeb(0, RTC_HOU10); + __raw_writeb(6, RTC_WEE1); + __raw_writeb(1, RTC_DAY1); __raw_writeb(0, RTC_DAY10); + __raw_writeb(1, RTC_MON1); __raw_writeb(0, RTC_MON10); + __raw_writeb(0, RTC_YEA1); __raw_writeb(0, RTC_YEA10); + __raw_writeb(0, RTC_YEA100); + __raw_writeb(2, RTC_YEA1000); + __raw_writeb(0, RTC_CTL); goto again; } - spin_unlock(&rtc_lock); + spin_unlock(&sh03_rtc_lock); return mktime(year, mon, day, hour, min, sec); } @@ -91,11 +91,11 @@ static int set_rtc_mmss(unsigned long nowtime) int i; /* gets recalled with irq locally disabled */ - spin_lock(&rtc_lock); + spin_lock(&sh03_rtc_lock); for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */ - if (!(ctrl_inb(RTC_CTL) & RTC_BUSY)) + if (!(__raw_readb(RTC_CTL) & RTC_BUSY)) break; - cmos_minutes = (ctrl_inb(RTC_MIN1) & 0xf) + (ctrl_inb(RTC_MIN10) & 0xf) * 10; + cmos_minutes = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10; real_seconds = nowtime % 60; real_minutes = nowtime / 60; if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) @@ -103,17 +103,17 @@ static int set_rtc_mmss(unsigned long nowtime) real_minutes %= 60; if (abs(real_minutes - cmos_minutes) < 30) { - ctrl_outb(real_seconds % 10, RTC_SEC1); - ctrl_outb(real_seconds / 10, RTC_SEC10); - ctrl_outb(real_minutes % 10, RTC_MIN1); - ctrl_outb(real_minutes / 10, RTC_MIN10); + __raw_writeb(real_seconds % 10, RTC_SEC1); + __raw_writeb(real_seconds / 10, RTC_SEC10); + __raw_writeb(real_minutes % 10, RTC_MIN1); + __raw_writeb(real_minutes / 10, RTC_MIN10); } else { - printk(KERN_WARNING + printk_once(KERN_NOTICE "set_rtc_mmss: can't update from %d to %d\n", cmos_minutes, real_minutes); retval = -1; } - spin_unlock(&rtc_lock); + spin_unlock(&sh03_rtc_lock); return retval; } diff --git a/arch/sh/boards/mach-sh03/setup.c b/arch/sh/boards/mach-sh03/setup.c new file mode 100644 index 00000000000..f582dab5934 --- /dev/null +++ b/arch/sh/boards/mach-sh03/setup.c @@ -0,0 +1,105 @@ +/* + * linux/arch/sh/boards/sh03/setup.c + * + * Copyright (C) 2004 Interface Co.,Ltd. Saito.K + * + */ + +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/pci.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <asm/io.h> +#include <asm/rtc.h> +#include <mach-sh03/mach/io.h> +#include <mach-sh03/mach/sh03.h> +#include <asm/addrspace.h> + +static void __init init_sh03_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +/* arch/sh/boards/sh03/rtc.c */ +void sh03_time_init(void); + +static void __init sh03_setup(char **cmdline_p) +{ + board_time_init = sh03_time_init; +} + +static struct resource cf_ide_resources[] = { + [0] = { + .start = 0x1f0, + .end = 0x1f0 + 8, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = 0x1f0 + 0x206, + .end = 0x1f0 +8 + 0x206 + 8, + .flags = IORESOURCE_IO, + }, + [2] = { + .start = IRL2_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_ide_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(cf_ide_resources), + .resource = cf_ide_resources, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = 0xa0800000, + .end = 0xa0800000, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *sh03_devices[] __initdata = { + &heartbeat_device, + &cf_ide_device, +}; + +static int __init sh03_devices_setup(void) +{ + pgprot_t prot; + unsigned long paddrbase; + void *cf_ide_base; + + /* open I/O area window */ + paddrbase = virt_to_phys((void *)PA_AREA5_IO); + prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16); + cf_ide_base = ioremap_prot(paddrbase, PAGE_SIZE, pgprot_val(prot)); + if (!cf_ide_base) { + printk("allocate_cf_area : can't open CF I/O window!\n"); + return -ENOMEM; + } + + /* IDE cmd address : 0x1f0-0x1f7 and 0x3f6 */ + cf_ide_resources[0].start += (unsigned long)cf_ide_base; + cf_ide_resources[0].end += (unsigned long)cf_ide_base; + cf_ide_resources[1].start += (unsigned long)cf_ide_base; + cf_ide_resources[1].end += (unsigned long)cf_ide_base; + + return platform_add_devices(sh03_devices, ARRAY_SIZE(sh03_devices)); +} +device_initcall(sh03_devices_setup); + +static struct sh_machine_vector mv_sh03 __initmv = { + .mv_name = "Interface (CTP/PCI-SH03)", + .mv_setup = sh03_setup, + .mv_init_irq = init_sh03_IRQ, +}; diff --git a/arch/sh/boards/mach-sh7763rdp/Makefile b/arch/sh/boards/mach-sh7763rdp/Makefile new file mode 100644 index 00000000000..f6c0b55516d --- /dev/null +++ b/arch/sh/boards/mach-sh7763rdp/Makefile @@ -0,0 +1 @@ +obj-y := setup.o irq.o diff --git a/arch/sh/boards/mach-sh7763rdp/irq.c b/arch/sh/boards/mach-sh7763rdp/irq.c new file mode 100644 index 00000000000..add698c8f2b --- /dev/null +++ b/arch/sh/boards/mach-sh7763rdp/irq.c @@ -0,0 +1,45 @@ +/* + * linux/arch/sh/boards/renesas/sh7763rdp/irq.c + * + * Renesas Solutions SH7763RDP Support. + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/irq.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <mach/sh7763rdp.h> + +#define INTC_BASE (0xFFD00000) +#define INTC_INT2PRI7 (INTC_BASE+0x4001C) +#define INTC_INT2MSKCR (INTC_BASE+0x4003C) +#define INTC_INT2MSKCR1 (INTC_BASE+0x400D4) + +/* + * Initialize IRQ setting + */ +void __init init_sh7763rdp_IRQ(void) +{ + /* GPIO enabled */ + __raw_writel(1 << 25, INTC_INT2MSKCR); + + /* enable GPIO interrupts */ + __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000, + INTC_INT2PRI7); + + /* USBH enabled */ + __raw_writel(1 << 17, INTC_INT2MSKCR1); + + /* GETHER enabled */ + __raw_writel(1 << 16, INTC_INT2MSKCR1); + + /* DMAC enabled */ + __raw_writel(1 << 8, INTC_INT2MSKCR); +} diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c new file mode 100644 index 00000000000..2c8fb04685d --- /dev/null +++ b/arch/sh/boards/mach-sh7763rdp/setup.c @@ -0,0 +1,217 @@ +/* + * linux/arch/sh/boards/renesas/sh7763rdp/setup.c + * + * Renesas Solutions sh7763rdp board + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/input.h> +#include <linux/mtd/physmap.h> +#include <linux/fb.h> +#include <linux/io.h> +#include <linux/sh_eth.h> +#include <linux/sh_intc.h> +#include <mach/sh7763rdp.h> +#include <asm/sh7760fb.h> + +/* NOR Flash */ +static struct mtd_partition sh7763rdp_nor_flash_partitions[] = { + { + .name = "U-Boot", + .offset = 0, + .size = (2 * 128 * 1024), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "Linux-Kernel", + .offset = MTDPART_OFS_APPEND, + .size = (20 * 128 * 1024), + }, { + .name = "Root Filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sh7763rdp_nor_flash_data = { + .width = 2, + .parts = sh7763rdp_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(sh7763rdp_nor_flash_partitions), +}; + +static struct resource sh7763rdp_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0, + .end = (64 * 1024 * 1024), + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sh7763rdp_nor_flash_device = { + .name = "physmap-flash", + .resource = sh7763rdp_nor_flash_resources, + .num_resources = ARRAY_SIZE(sh7763rdp_nor_flash_resources), + .dev = { + .platform_data = &sh7763rdp_nor_flash_data, + }, +}; + +/* + * SH-Ether + * + * SH Ether of SH7763 has multi IRQ handling. + * (0x920,0x940,0x960 -> 0x920) + */ +static struct resource sh_eth_resources[] = { + { + .start = 0xFEE00800, /* use eth1 */ + .end = 0xFEE00F7C - 1, + .flags = IORESOURCE_MEM, + }, { + .start = 0xFEE01800, /* TSU */ + .end = 0xFEE01FFF, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x920), /* irq number */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7763_eth_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device sh7763rdp_eth_device = { + .name = "sh7763-gether", + .resource = sh_eth_resources, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .dev = { + .platform_data = &sh7763_eth_pdata, + }, +}; + +/* SH7763 LCDC */ +static struct resource sh7763rdp_fb_resources[] = { + { + .start = 0xFFE80000, + .end = 0xFFE80442 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct fb_videomode sh7763fb_videomode = { + .refresh = 60, + .name = "VGA Monitor", + .xres = 640, + .yres = 480, + .pixclock = 10000, + .left_margin = 80, + .right_margin = 24, + .upper_margin = 30, + .lower_margin = 1, + .hsync_len = 96, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = FBINFO_FLAG_DEFAULT, +}; + +static struct sh7760fb_platdata sh7763fb_def_pdata = { + .def_mode = &sh7763fb_videomode, + .ldmtr = (LDMTR_TFT_COLOR_16|LDMTR_MCNT), + .lddfr = LDDFR_16BPP_RGB565, + .ldpmmr = 0x0000, + .ldpspr = 0xFFFF, + .ldaclnr = 0x0001, + .ldickr = 0x1102, + .rotate = 0, + .novsync = 0, + .blank = NULL, +}; + +static struct platform_device sh7763rdp_fb_device = { + .name = "sh7760-lcdc", + .resource = sh7763rdp_fb_resources, + .num_resources = ARRAY_SIZE(sh7763rdp_fb_resources), + .dev = { + .platform_data = &sh7763fb_def_pdata, + }, +}; + +static struct platform_device *sh7763rdp_devices[] __initdata = { + &sh7763rdp_nor_flash_device, + &sh7763rdp_eth_device, + &sh7763rdp_fb_device, +}; + +static int __init sh7763rdp_devices_setup(void) +{ + return platform_add_devices(sh7763rdp_devices, + ARRAY_SIZE(sh7763rdp_devices)); +} +device_initcall(sh7763rdp_devices_setup); + +static void __init sh7763rdp_setup(char **cmdline_p) +{ + /* Board version check */ + if (__raw_readw(CPLD_BOARD_ID_ERV_REG) == 0xECB1) + printk(KERN_INFO "RTE Standard Configuration\n"); + else + printk(KERN_INFO "RTA Standard Configuration\n"); + + /* USB pin select bits (clear bit 5-2 to 0) */ + __raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2); + /* USBH setup port I controls to other (clear bits 4-9 to 0) */ + __raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR); + + /* Select USB Host controller */ + __raw_writew(0x00, USB_USBHSC); + + /* For LCD */ + /* set PTJ7-1, bits 15-2 of PJCR to 0 */ + __raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR); + /* set PTI5, bits 11-10 of PICR to 0 */ + __raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR); + __raw_writew(0, PORT_PKCR); + __raw_writew(0, PORT_PLCR); + /* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */ + __raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2); + /* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */ + __raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3); + + /* For HAC */ + /* bit3-0 0100:HAC & SSI1 enable */ + __raw_writew((__raw_readw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1); + /* bit14 1:SSI_HAC_CLK enable */ + __raw_writew(__raw_readw(PORT_PSEL4) | 0x4000, PORT_PSEL4); + + /* SH-Ether */ + __raw_writew((__raw_readw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1); + __raw_writew(0x0, PORT_PFCR); + __raw_writew(0x0, PORT_PFCR); + __raw_writew(0x0, PORT_PFCR); + + /* MMC */ + /*selects SCIF and MMC other functions */ + __raw_writew(0x0001, PORT_PSEL0); + /* MMC clock operates */ + __raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1); + __raw_writew(__raw_readw(PORT_PACR) & ~0x3000, PORT_PACR); + __raw_writew(__raw_readw(PORT_PCCR) & ~0xCFC3, PORT_PCCR); +} + +static struct sh_machine_vector mv_sh7763rdp __initmv = { + .mv_name = "sh7763drp", + .mv_setup = sh7763rdp_setup, + .mv_init_irq = init_sh7763rdp_IRQ, +}; diff --git a/arch/sh/boards/mach-x3proto/Makefile b/arch/sh/boards/mach-x3proto/Makefile new file mode 100644 index 00000000000..0cbe3d02dea --- /dev/null +++ b/arch/sh/boards/mach-x3proto/Makefile @@ -0,0 +1,3 @@ +obj-y += setup.o ilsel.o + +obj-$(CONFIG_GPIOLIB) += gpio.o diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c new file mode 100644 index 00000000000..3ea65e9b56e --- /dev/null +++ b/arch/sh/boards/mach-x3proto/gpio.c @@ -0,0 +1,141 @@ +/* + * arch/sh/boards/mach-x3proto/gpio.c + * + * Renesas SH-X3 Prototype Baseboard GPIO Support. + * + * Copyright (C) 2010 - 2012 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/irqdomain.h> +#include <linux/io.h> +#include <mach/ilsel.h> +#include <mach/hardware.h> + +#define KEYCTLR 0xb81c0000 +#define KEYOUTR 0xb81c0002 +#define KEYDETR 0xb81c0004 + +static DEFINE_SPINLOCK(x3proto_gpio_lock); +static struct irq_domain *x3proto_irq_domain; + +static int x3proto_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + unsigned long flags; + unsigned int data; + + spin_lock_irqsave(&x3proto_gpio_lock, flags); + data = __raw_readw(KEYCTLR); + data |= (1 << gpio); + __raw_writew(data, KEYCTLR); + spin_unlock_irqrestore(&x3proto_gpio_lock, flags); + + return 0; +} + +static int x3proto_gpio_get(struct gpio_chip *chip, unsigned gpio) +{ + return !!(__raw_readw(KEYDETR) & (1 << gpio)); +} + +static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) +{ + int virq; + + if (gpio < chip->ngpio) + virq = irq_create_mapping(x3proto_irq_domain, gpio); + else + virq = -ENXIO; + + return virq; +} + +static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct irq_data *data = irq_get_irq_data(irq); + struct irq_chip *chip = irq_data_get_irq_chip(data); + unsigned long mask; + int pin; + + chip->irq_mask_ack(data); + + mask = __raw_readw(KEYDETR); + for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS) + generic_handle_irq(irq_linear_revmap(x3proto_irq_domain, pin)); + + chip->irq_unmask(data); +} + +struct gpio_chip x3proto_gpio_chip = { + .label = "x3proto-gpio", + .direction_input = x3proto_gpio_direction_input, + .get = x3proto_gpio_get, + .to_irq = x3proto_gpio_to_irq, + .base = -1, + .ngpio = NR_BASEBOARD_GPIOS, +}; + +static int x3proto_gpio_irq_map(struct irq_domain *domain, unsigned int virq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler_name(virq, &dummy_irq_chip, handle_simple_irq, + "gpio"); + + return 0; +} + +static struct irq_domain_ops x3proto_gpio_irq_ops = { + .map = x3proto_gpio_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +int __init x3proto_gpio_setup(void) +{ + int ilsel, ret; + + ilsel = ilsel_enable(ILSEL_KEY); + if (unlikely(ilsel < 0)) + return ilsel; + + ret = gpiochip_add(&x3proto_gpio_chip); + if (unlikely(ret)) + goto err_gpio; + + x3proto_irq_domain = irq_domain_add_linear(NULL, NR_BASEBOARD_GPIOS, + &x3proto_gpio_irq_ops, NULL); + if (unlikely(!x3proto_irq_domain)) + goto err_irq; + + pr_info("registering '%s' support, handling GPIOs %u -> %u, " + "bound to IRQ %u\n", + x3proto_gpio_chip.label, x3proto_gpio_chip.base, + x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio, + ilsel); + + irq_set_chained_handler(ilsel, x3proto_gpio_irq_handler); + irq_set_irq_wake(ilsel, 1); + + return 0; + +err_irq: + ret = gpiochip_remove(&x3proto_gpio_chip); + if (unlikely(ret)) + pr_err("Failed deregistering GPIO\n"); + +err_gpio: + synchronize_irq(ilsel); + + ilsel_disable(ILSEL_KEY); + + return ret; +} diff --git a/arch/sh/boards/renesas/x3proto/ilsel.c b/arch/sh/boards/mach-x3proto/ilsel.c index b5c673c3933..95e34613951 100644 --- a/arch/sh/boards/renesas/x3proto/ilsel.c +++ b/arch/sh/boards/mach-x3proto/ilsel.c @@ -1,20 +1,22 @@ /* - * arch/sh/boards/renesas/x3proto/ilsel.c + * arch/sh/boards/mach-x3proto/ilsel.c * * Helper routines for SH-X3 proto board ILSEL. * - * Copyright (C) 2007 Paul Mundt + * Copyright (C) 2007 - 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include <linux/init.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/bitmap.h> #include <linux/io.h> -#include <asm/ilsel.h> +#include <mach/ilsel.h> /* * ILSEL is split across: @@ -64,16 +66,18 @@ static void __ilsel_enable(ilsel_source_t set, unsigned int bit) unsigned int tmp, shift; unsigned long addr; + pr_notice("enabling ILSEL set %d\n", set); + addr = mk_ilsel_addr(bit); shift = mk_ilsel_shift(bit); pr_debug("%s: bit#%d: addr - 0x%08lx (shift %d, set %d)\n", __func__, bit, addr, shift, set); - tmp = ctrl_inw(addr); + tmp = __raw_readw(addr); tmp &= ~(0xf << shift); tmp |= set << shift; - ctrl_outw(tmp, addr); + __raw_writew(tmp, addr); } /** @@ -92,8 +96,10 @@ int ilsel_enable(ilsel_source_t set) { unsigned int bit; - /* Aliased sources must use ilsel_enable_fixed() */ - BUG_ON(set > ILSEL_KEY); + if (unlikely(set > ILSEL_KEY)) { + pr_err("Aliased sources must use ilsel_enable_fixed()\n"); + return -EINVAL; + } do { bit = find_first_zero_bit(&ilsel_level_map, ILSEL_LEVELS); @@ -140,11 +146,13 @@ void ilsel_disable(unsigned int irq) unsigned long addr; unsigned int tmp; + pr_notice("disabling ILSEL set %d\n", irq); + addr = mk_ilsel_addr(irq); - tmp = ctrl_inw(addr); + tmp = __raw_readw(addr); tmp &= ~(0xf << mk_ilsel_shift(irq)); - ctrl_outw(tmp, addr); + __raw_writew(tmp, addr); clear_bit(irq, &ilsel_level_map); } diff --git a/arch/sh/boards/mach-x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c new file mode 100644 index 00000000000..d682e2b6a85 --- /dev/null +++ b/arch/sh/boards/mach-x3proto/setup.c @@ -0,0 +1,273 @@ +/* + * arch/sh/boards/mach-x3proto/setup.c + * + * Renesas SH-X3 Prototype Board Support. + * + * Copyright (C) 2007 - 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/smc91x.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/input.h> +#include <linux/usb/r8a66597.h> +#include <linux/usb/m66592.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <mach/ilsel.h> +#include <mach/hardware.h> +#include <asm/smp-ops.h> + +static struct resource heartbeat_resources[] = { + [0] = { + .start = 0xb8140020, + .end = 0xb8140020, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, +}; + +static struct resource smc91x_resources[] = { + [0] = { + .start = 0x18000300, + .end = 0x18000300 + 0x10 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* Filled in by ilsel */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = -1, + .resource = smc91x_resources, + .num_resources = ARRAY_SIZE(smc91x_resources), + .dev = { + .platform_data = &smc91x_info, + }, +}; + +static struct r8a66597_platdata r8a66597_data = { + .xtal = R8A66597_PLATDATA_XTAL_12MHZ, + .vif = 1, +}; + +static struct resource r8a66597_usb_host_resources[] = { + [0] = { + .start = 0x18040000, + .end = 0x18080000 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* Filled in by ilsel */ + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device r8a66597_usb_host_device = { + .name = "r8a66597_hcd", + .id = -1, + .dev = { + .dma_mask = NULL, /* don't use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, + }, + .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), + .resource = r8a66597_usb_host_resources, +}; + +static struct m66592_platdata usbf_platdata = { + .xtal = M66592_PLATDATA_XTAL_24MHZ, + .vif = 1, +}; + +static struct resource m66592_usb_peripheral_resources[] = { + [0] = { + .name = "m66592_udc", + .start = 0x18080000, + .end = 0x180c0000 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "m66592_udc", + /* Filled in by ilsel */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device m66592_usb_peripheral_device = { + .name = "m66592_udc", + .id = -1, + .dev = { + .dma_mask = NULL, /* don't use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &usbf_platdata, + }, + .num_resources = ARRAY_SIZE(m66592_usb_peripheral_resources), + .resource = m66592_usb_peripheral_resources, +}; + +static struct gpio_keys_button baseboard_buttons[NR_BASEBOARD_GPIOS] = { + { + .desc = "key44", + .code = KEY_POWER, + .active_low = 1, + .wakeup = 1, + }, { + .desc = "key43", + .code = KEY_SUSPEND, + .active_low = 1, + .wakeup = 1, + }, { + .desc = "key42", + .code = KEY_KATAKANAHIRAGANA, + .active_low = 1, + }, { + .desc = "key41", + .code = KEY_SWITCHVIDEOMODE, + .active_low = 1, + }, { + .desc = "key34", + .code = KEY_F12, + .active_low = 1, + }, { + .desc = "key33", + .code = KEY_F11, + .active_low = 1, + }, { + .desc = "key32", + .code = KEY_F10, + .active_low = 1, + }, { + .desc = "key31", + .code = KEY_F9, + .active_low = 1, + }, { + .desc = "key24", + .code = KEY_F8, + .active_low = 1, + }, { + .desc = "key23", + .code = KEY_F7, + .active_low = 1, + }, { + .desc = "key22", + .code = KEY_F6, + .active_low = 1, + }, { + .desc = "key21", + .code = KEY_F5, + .active_low = 1, + }, { + .desc = "key14", + .code = KEY_F4, + .active_low = 1, + }, { + .desc = "key13", + .code = KEY_F3, + .active_low = 1, + }, { + .desc = "key12", + .code = KEY_F2, + .active_low = 1, + }, { + .desc = "key11", + .code = KEY_F1, + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data baseboard_buttons_data = { + .buttons = baseboard_buttons, + .nbuttons = ARRAY_SIZE(baseboard_buttons), +}; + +static struct platform_device baseboard_buttons_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &baseboard_buttons_data, + }, +}; + +static struct platform_device *x3proto_devices[] __initdata = { + &heartbeat_device, + &smc91x_device, + &r8a66597_usb_host_device, + &m66592_usb_peripheral_device, + &baseboard_buttons_device, +}; + +static void __init x3proto_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRL3210); + + /* Set ICR0.LVLMODE */ + __raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000); +} + +static int __init x3proto_devices_setup(void) +{ + int ret, i; + + /* + * IRLs are only needed for ILSEL mappings, so flip over the INTC + * pins at a later point to enable the GPIOs to settle. + */ + x3proto_init_irq(); + + /* + * Now that ILSELs are available, set up the baseboard GPIOs. + */ + ret = x3proto_gpio_setup(); + if (unlikely(ret)) + return ret; + + /* + * Propagate dynamic GPIOs for the baseboard button device. + */ + for (i = 0; i < ARRAY_SIZE(baseboard_buttons); i++) + baseboard_buttons[i].gpio = x3proto_gpio_chip.base + i; + + r8a66597_usb_host_resources[1].start = + r8a66597_usb_host_resources[1].end = ilsel_enable(ILSEL_USBH_I); + + m66592_usb_peripheral_resources[1].start = + m66592_usb_peripheral_resources[1].end = ilsel_enable(ILSEL_USBP_I); + + smc91x_resources[1].start = + smc91x_resources[1].end = ilsel_enable(ILSEL_LAN); + + return platform_add_devices(x3proto_devices, + ARRAY_SIZE(x3proto_devices)); +} +device_initcall(x3proto_devices_setup); + +static void __init x3proto_setup(char **cmdline_p) +{ + register_smp_ops(&shx3_smp_ops); +} + +static struct sh_machine_vector mv_x3proto __initmv = { + .mv_name = "x3proto", + .mv_setup = x3proto_setup, +}; diff --git a/arch/sh/boards/magicpanelr2/Kconfig b/arch/sh/boards/magicpanelr2/Kconfig deleted file mode 100644 index b0abddc3e84..00000000000 --- a/arch/sh/boards/magicpanelr2/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -if SH_MAGIC_PANEL_R2 - -menu "Magic Panel R2 options" - -config SH_MAGIC_PANEL_R2_VERSION - int SH_MAGIC_PANEL_R2_VERSION - default "3" - help - Set the version of the Magic Panel R2 - -endmenu - -endif diff --git a/arch/sh/boards/magicpanelr2/Makefile b/arch/sh/boards/magicpanelr2/Makefile deleted file mode 100644 index 7a6d586b907..00000000000 --- a/arch/sh/boards/magicpanelr2/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Magic Panel specific parts -# - -obj-y := setup.o
\ No newline at end of file diff --git a/arch/sh/boards/mpc1211/Makefile b/arch/sh/boards/mpc1211/Makefile deleted file mode 100644 index 8cd31b5d200..00000000000 --- a/arch/sh/boards/mpc1211/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the Interface (CTP/PCI/MPC-SH02) specific parts of the kernel -# - -obj-y := setup.o rtc.o - -obj-$(CONFIG_PCI) += pci.o - diff --git a/arch/sh/boards/mpc1211/pci.c b/arch/sh/boards/mpc1211/pci.c deleted file mode 100644 index 23849f70f13..00000000000 --- a/arch/sh/boards/mpc1211/pci.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * Low-Level PCI Support for the MPC-1211(CTP/PCI/MPC-SH02) - * - * (c) 2002-2003 Saito.K & Jeanne - * - * Dustin McIntire (dustin@sensoria.com) - * Derived from arch/i386/kernel/pci-*.c which bore the message: - * (c) 1999--2000 Martin Mares <mj@ucw.cz> - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - */ -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/pci.h> -#include <linux/sched.h> -#include <linux/ioport.h> -#include <linux/errno.h> -#include <linux/irq.h> -#include <linux/interrupt.h> - -#include <asm/machvec.h> -#include <asm/io.h> -#include <asm/mpc1211/pci.h> - -static struct resource mpcpci_io_resource = { - "MPCPCI IO", - 0x00000000, - 0xffffffff, - IORESOURCE_IO -}; - -static struct resource mpcpci_mem_resource = { - "MPCPCI mem", - 0x00000000, - 0xffffffff, - IORESOURCE_MEM -}; - -static struct pci_ops pci_direct_conf1; -struct pci_channel board_pci_channels[] = { - {&pci_direct_conf1, &mpcpci_io_resource, &mpcpci_mem_resource, 0, 256}, - {NULL, NULL, NULL, 0, 0}, -}; - -/* - * Direct access to PCI hardware... - */ - - -#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) - -/* - * Functions for accessing PCI configuration space with type 1 accesses - */ -static int pci_conf1_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) -{ - u32 word; - unsigned long flags; - - /* - * PCIPDR may only be accessed as 32 bit words, - * so we must do byte alignment by hand - */ - local_irq_save(flags); - writel(CONFIG_CMD(bus,devfn,where), PCIPAR); - word = readl(PCIPDR); - local_irq_restore(flags); - - switch (size) { - case 1: - switch (where & 0x3) { - case 3: - *value = (u8)(word >> 24); - break; - case 2: - *value = (u8)(word >> 16); - break; - case 1: - *value = (u8)(word >> 8); - break; - default: - *value = (u8)word; - break; - } - break; - case 2: - switch (where & 0x3) { - case 3: - *value = (u16)(word >> 24); - local_irq_save(flags); - writel(CONFIG_CMD(bus,devfn,(where+1)), PCIPAR); - word = readl(PCIPDR); - local_irq_restore(flags); - *value |= ((word & 0xff) << 8); - break; - case 2: - *value = (u16)(word >> 16); - break; - case 1: - *value = (u16)(word >> 8); - break; - default: - *value = (u16)word; - break; - } - break; - case 4: - *value = word; - break; - } - PCIDBG(4,"pci_conf1_read@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),*value); - return PCIBIOS_SUCCESSFUL; -} - -/* - * Since MPC-1211 only does 32bit access we'll have to do a read,mask,write operation. - * We'll allow an odd byte offset, though it should be illegal. - */ -static int pci_conf1_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) -{ - u32 word,mask = 0; - unsigned long flags; - u32 shift = (where & 3) * 8; - - if(size == 1) { - mask = ((1 << 8) - 1) << shift; // create the byte mask - } else if(size == 2){ - if(shift == 24) - return PCIBIOS_BAD_REGISTER_NUMBER; - mask = ((1 << 16) - 1) << shift; // create the word mask - } - local_irq_save(flags); - writel(CONFIG_CMD(bus,devfn,where), PCIPAR); - if(size == 4){ - writel(value, PCIPDR); - local_irq_restore(flags); - PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),value); - return PCIBIOS_SUCCESSFUL; - } - word = readl(PCIPDR); - word &= ~mask; - word |= ((value << shift) & mask); - writel(word, PCIPDR); - local_irq_restore(flags); - PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),word); - return PCIBIOS_SUCCESSFUL; -} - -#undef CONFIG_CMD - -static struct pci_ops pci_direct_conf1 = { - .read = pci_conf1_read, - .write = pci_conf1_write, -}; - -static void __devinit quirk_ali_ide_ports(struct pci_dev *dev) -{ - dev->resource[0].start = 0x1f0; - dev->resource[0].end = 0x1f7; - dev->resource[0].flags = IORESOURCE_IO; - dev->resource[1].start = 0x3f6; - dev->resource[1].end = 0x3f6; - dev->resource[1].flags = IORESOURCE_IO; - dev->resource[2].start = 0x170; - dev->resource[2].end = 0x177; - dev->resource[2].flags = IORESOURCE_IO; - dev->resource[3].start = 0x376; - dev->resource[3].end = 0x376; - dev->resource[3].flags = IORESOURCE_IO; - dev->resource[4].start = 0xf000; - dev->resource[4].end = 0xf00f; - dev->resource[4].flags = IORESOURCE_IO; -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, quirk_ali_ide_ports); - -char * __devinit pcibios_setup(char *str) -{ - return str; -} - -/* - * Called after each bus is probed, but before its children - * are examined. - */ - -void __devinit pcibios_fixup_bus(struct pci_bus *b) -{ - pci_read_bridge_bases(b); -} - -/* - * IRQ functions - */ -static inline u8 bridge_swizzle(u8 pin, u8 slot) -{ - return (((pin-1) + slot) % 4) + 1; -} - -static inline u8 bridge_swizzle_pci_1(u8 pin, u8 slot) -{ - return (((pin-1) - slot) & 3) + 1; -} - -static u8 __init mpc1211_swizzle(struct pci_dev *dev, u8 *pinp) -{ - unsigned long flags; - u8 pin = *pinp; - u32 word; - - for ( ; dev->bus->self; dev = dev->bus->self) { - if (!pin) - continue; - - if (dev->bus->number == 1) { - local_irq_save(flags); - writel(0x80000000 | 0x2c, PCIPAR); - word = readl(PCIPDR); - local_irq_restore(flags); - word >>= 16; - - if (word == 0x0001) - pin = bridge_swizzle_pci_1(pin, PCI_SLOT(dev->devfn)); - else - pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); - } else - pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); - } - - *pinp = pin; - - return PCI_SLOT(dev->devfn); -} - -static int __init map_mpc1211_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq = -1; - - /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */ - if (dev->bus->number == 0) { - switch (slot) { - case 13: irq = 9; break; /* USB */ - case 22: irq = 10; break; /* LAN */ - default: irq = 0; break; - } - } else { - switch (pin) { - case 0: irq = 0; break; - case 1: irq = 7; break; - case 2: irq = 9; break; - case 3: irq = 10; break; - case 4: irq = 11; break; - } - } - - if( irq < 0 ) { - PCIDBG(3, "PCI: Error mapping IRQ on device %s\n", pci_name(dev)); - return irq; - } - - PCIDBG(2, "Setting IRQ for slot %s to %d\n", pci_name(dev), irq); - - return irq; -} - -void __init pcibios_fixup_irqs(void) -{ - pci_fixup_irqs(mpc1211_swizzle, map_mpc1211_irq); -} - -void pcibios_align_resource(void *data, struct resource *res, - resource_size_t size, resource_size_t align) -{ - resource_size_t start = res->start; - - if (res->flags & IORESOURCE_IO) { - if (start >= 0x10000UL) { - if ((start & 0xffffUL) < 0x4000UL) { - start = (start & 0xffff0000UL) + 0x4000UL; - } else if ((start & 0xffffUL) >= 0xf000UL) { - start = (start & 0xffff0000UL) + 0x10000UL; - } - res->start = start; - } else { - if (start & 0x300) { - start = (start + 0x3ff) & ~0x3ff; - res->start = start; - } - } - } -} - diff --git a/arch/sh/boards/mpc1211/rtc.c b/arch/sh/boards/mpc1211/rtc.c deleted file mode 100644 index 03b123a4bba..00000000000 --- a/arch/sh/boards/mpc1211/rtc.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * linux/arch/sh/kernel/rtc-mpc1211.c -- MPC-1211 on-chip RTC support - * - * Copyright (C) 2002 Saito.K & Jeanne - * - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/time.h> -#include <linux/bcd.h> -#include <linux/mc146818rtc.h> - -unsigned long get_cmos_time(void) -{ - unsigned int year, mon, day, hour, min, sec; - - spin_lock(&rtc_lock); - - do { - sec = CMOS_READ(RTC_SECONDS); - min = CMOS_READ(RTC_MINUTES); - hour = CMOS_READ(RTC_HOURS); - day = CMOS_READ(RTC_DAY_OF_MONTH); - mon = CMOS_READ(RTC_MONTH); - year = CMOS_READ(RTC_YEAR); - } while (sec != CMOS_READ(RTC_SECONDS)); - - if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BCD_TO_BIN(sec); - BCD_TO_BIN(min); - BCD_TO_BIN(hour); - BCD_TO_BIN(day); - BCD_TO_BIN(mon); - BCD_TO_BIN(year); - } - - spin_unlock(&rtc_lock); - - year += 1900; - if (year < 1970) - year += 100; - - return mktime(year, mon, day, hour, min, sec); -} - -void mpc1211_rtc_gettimeofday(struct timeval *tv) -{ - - tv->tv_sec = get_cmos_time(); - tv->tv_usec = 0; -} - -/* arc/i386/kernel/time.c */ -/* - * In order to set the CMOS clock precisely, set_rtc_mmss has to be - * called 500 ms after the second nowtime has started, because when - * nowtime is written into the registers of the CMOS clock, it will - * jump to the next second precisely 500 ms later. Check the Motorola - * MC146818A or Dallas DS12887 data sheet for details. - * - * BUG: This routine does not handle hour overflow properly; it just - * sets the minutes. Usually you'll only notice that after reboot! - */ -static int set_rtc_mmss(unsigned long nowtime) -{ - int retval = 0; - int real_seconds, real_minutes, cmos_minutes; - unsigned char save_control, save_freq_select; - - /* gets recalled with irq locally disabled */ - spin_lock(&rtc_lock); - save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */ - CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); - - save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */ - CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); - - cmos_minutes = CMOS_READ(RTC_MINUTES); - if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) - BCD_TO_BIN(cmos_minutes); - - /* - * since we're only adjusting minutes and seconds, - * don't interfere with hour overflow. This avoids - * messing with unknown time zones but requires your - * RTC not to be off by more than 15 minutes - */ - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - real_minutes %= 60; - - if (abs(real_minutes - cmos_minutes) < 30) { - if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BIN_TO_BCD(real_seconds); - BIN_TO_BCD(real_minutes); - } - CMOS_WRITE(real_seconds,RTC_SECONDS); - CMOS_WRITE(real_minutes,RTC_MINUTES); - } else { - printk(KERN_WARNING - "set_rtc_mmss: can't update from %d to %d\n", - cmos_minutes, real_minutes); - retval = -1; - } - - /* The following flags have to be released exactly in this order, - * otherwise the DS12887 (popular MC146818A clone with integrated - * battery and quartz) will not reset the oscillator and will not - * update precisely 500 ms later. You won't find this mentioned in - * the Dallas Semiconductor data sheets, but who believes data - * sheets anyway ... -- Markus Kuhn - */ - CMOS_WRITE(save_control, RTC_CONTROL); - CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); - spin_unlock(&rtc_lock); - - return retval; -} - -int mpc1211_rtc_settimeofday(const struct timeval *tv) -{ - unsigned long nowtime = tv->tv_sec; - - return set_rtc_mmss(nowtime); -} - -void mpc1211_time_init(void) -{ - rtc_sh_get_time = mpc1211_rtc_gettimeofday; - rtc_sh_set_time = mpc1211_rtc_settimeofday; -} - diff --git a/arch/sh/boards/mpc1211/setup.c b/arch/sh/boards/mpc1211/setup.c deleted file mode 100644 index fede36361dc..00000000000 --- a/arch/sh/boards/mpc1211/setup.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * linux/arch/sh/boards/mpc1211/setup.c - * - * Copyright (C) 2002 Saito.K & Jeanne, Fujii.Y - * - */ - -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/hdreg.h> -#include <linux/ide.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <asm/io.h> -#include <asm/machvec.h> -#include <asm/mpc1211/mpc1211.h> -#include <asm/mpc1211/pci.h> -#include <asm/mpc1211/m1543c.h> - -/* ALI15X3 SMBus address offsets */ -#define SMBHSTSTS (0 + 0x3100) -#define SMBHSTCNT (1 + 0x3100) -#define SMBHSTSTART (2 + 0x3100) -#define SMBHSTCMD (7 + 0x3100) -#define SMBHSTADD (3 + 0x3100) -#define SMBHSTDAT0 (4 + 0x3100) -#define SMBHSTDAT1 (5 + 0x3100) -#define SMBBLKDAT (6 + 0x3100) - -/* Other settings */ -#define MAX_TIMEOUT 500 /* times 1/100 sec */ - -/* ALI15X3 command constants */ -#define ALI15X3_ABORT 0x04 -#define ALI15X3_T_OUT 0x08 -#define ALI15X3_QUICK 0x00 -#define ALI15X3_BYTE 0x10 -#define ALI15X3_BYTE_DATA 0x20 -#define ALI15X3_WORD_DATA 0x30 -#define ALI15X3_BLOCK_DATA 0x40 -#define ALI15X3_BLOCK_CLR 0x80 - -/* ALI15X3 status register bits */ -#define ALI15X3_STS_IDLE 0x04 -#define ALI15X3_STS_BUSY 0x08 -#define ALI15X3_STS_DONE 0x10 -#define ALI15X3_STS_DEV 0x20 /* device error */ -#define ALI15X3_STS_COLL 0x40 /* collision or no response */ -#define ALI15X3_STS_TERM 0x80 /* terminated by abort */ -#define ALI15X3_STS_ERR 0xE0 /* all the bad error bits */ - -static void __init pci_write_config(unsigned long busNo, - unsigned long devNo, - unsigned long fncNo, - unsigned long cnfAdd, - unsigned long cnfData) -{ - ctrl_outl((0x80000000 - + ((busNo & 0xff) << 16) - + ((devNo & 0x1f) << 11) - + ((fncNo & 0x07) << 8) - + (cnfAdd & 0xfc)), PCIPAR); - - ctrl_outl(cnfData, PCIPDR); -} - -/* - Initialize IRQ setting -*/ - -static unsigned char m_irq_mask = 0xfb; -static unsigned char s_irq_mask = 0xff; - -static void disable_mpc1211_irq(unsigned int irq) -{ - if( irq < 8) { - m_irq_mask |= (1 << irq); - outb(m_irq_mask,I8259_M_MR); - } else { - s_irq_mask |= (1 << (irq - 8)); - outb(s_irq_mask,I8259_S_MR); - } - -} - -static void enable_mpc1211_irq(unsigned int irq) -{ - if( irq < 8) { - m_irq_mask &= ~(1 << irq); - outb(m_irq_mask,I8259_M_MR); - } else { - s_irq_mask &= ~(1 << (irq - 8)); - outb(s_irq_mask,I8259_S_MR); - } -} - -static inline int mpc1211_irq_real(unsigned int irq) -{ - int value; - int irqmask; - - if ( irq < 8) { - irqmask = 1<<irq; - outb(0x0b,I8259_M_CR); /* ISR register */ - value = inb(I8259_M_CR) & irqmask; - outb(0x0a,I8259_M_CR); /* back ro the IPR reg */ - return value; - } - irqmask = 1<<(irq - 8); - outb(0x0b,I8259_S_CR); /* ISR register */ - value = inb(I8259_S_CR) & irqmask; - outb(0x0a,I8259_S_CR); /* back ro the IPR reg */ - return value; -} - -static void mask_and_ack_mpc1211(unsigned int irq) -{ - if(irq < 8) { - if(m_irq_mask & (1<<irq)){ - if(!mpc1211_irq_real(irq)){ - atomic_inc(&irq_err_count) - printk("spurious 8259A interrupt: IRQ %x\n",irq); - } - } else { - m_irq_mask |= (1<<irq); - } - inb(I8259_M_MR); /* DUMMY */ - outb(m_irq_mask,I8259_M_MR); /* disable */ - outb(0x60+irq,I8259_M_CR); /* EOI */ - - } else { - if(s_irq_mask & (1<<(irq - 8))){ - if(!mpc1211_irq_real(irq)){ - atomic_inc(&irq_err_count); - printk("spurious 8259A interrupt: IRQ %x\n",irq); - } - } else { - s_irq_mask |= (1<<(irq - 8)); - } - inb(I8259_S_MR); /* DUMMY */ - outb(s_irq_mask,I8259_S_MR); /* disable */ - outb(0x60+(irq-8),I8259_S_CR); /* EOI */ - outb(0x60+2,I8259_M_CR); - } -} - -static void end_mpc1211_irq(unsigned int irq) -{ - enable_mpc1211_irq(irq); -} - -static unsigned int startup_mpc1211_irq(unsigned int irq) -{ - enable_mpc1211_irq(irq); - return 0; -} - -static void shutdown_mpc1211_irq(unsigned int irq) -{ - disable_mpc1211_irq(irq); -} - -static struct hw_interrupt_type mpc1211_irq_type = { - .typename = "MPC1211-IRQ", - .startup = startup_mpc1211_irq, - .shutdown = shutdown_mpc1211_irq, - .enable = enable_mpc1211_irq, - .disable = disable_mpc1211_irq, - .ack = mask_and_ack_mpc1211, - .end = end_mpc1211_irq -}; - -static void make_mpc1211_irq(unsigned int irq) -{ - irq_desc[irq].chip = &mpc1211_irq_type; - irq_desc[irq].status = IRQ_DISABLED; - irq_desc[irq].action = 0; - irq_desc[irq].depth = 1; - disable_mpc1211_irq(irq); -} - -int mpc1211_irq_demux(int irq) -{ - unsigned int poll; - - if( irq == 2 ) { - outb(0x0c,I8259_M_CR); - poll = inb(I8259_M_CR); - if(poll & 0x80) { - irq = (poll & 0x07); - } - if( irq == 2) { - outb(0x0c,I8259_S_CR); - poll = inb(I8259_S_CR); - irq = (poll & 0x07) + 8; - } - } - return irq; -} - -static void __init init_mpc1211_IRQ(void) -{ - int i; - /* - * Super I/O (Just mimic PC): - * 1: keyboard - * 3: serial 1 - * 4: serial 0 - * 5: printer - * 6: floppy - * 8: rtc - * 10: lan - * 12: mouse - * 14: ide0 - * 15: ide1 - */ - - pci_write_config(0,0,0,0x54, 0xb0b0002d); - outb(0x11, I8259_M_CR); /* mater icw1 edge trigger */ - outb(0x11, I8259_S_CR); /* slave icw1 edge trigger */ - outb(0x20, I8259_M_MR); /* m icw2 base vec 0x08 */ - outb(0x28, I8259_S_MR); /* s icw2 base vec 0x70 */ - outb(0x04, I8259_M_MR); /* m icw3 slave irq2 */ - outb(0x02, I8259_S_MR); /* s icw3 slave id */ - outb(0x01, I8259_M_MR); /* m icw4 non buf normal eoi*/ - outb(0x01, I8259_S_MR); /* s icw4 non buf normal eo1*/ - outb(0xfb, I8259_M_MR); /* disable irq0--irq7 */ - outb(0xff, I8259_S_MR); /* disable irq8--irq15 */ - - for ( i=0; i < 16; i++) { - if(i != 2) { - make_mpc1211_irq(i); - } - } -} - -static void delay1000(void) -{ - int i; - - for (i=0; i<1000; i++) - ctrl_delay(); -} - -static int put_smb_blk(unsigned char *p, int address, int command, int no) -{ - int temp; - int timeout; - int i; - - outb(0xff, SMBHSTSTS); - temp = inb(SMBHSTSTS); - for (timeout = 0; (timeout < MAX_TIMEOUT) && !(temp & ALI15X3_STS_IDLE); timeout++) { - delay1000(); - temp = inb(SMBHSTSTS); - } - if (timeout >= MAX_TIMEOUT){ - return -1; - } - - outb(((address & 0x7f) << 1), SMBHSTADD); - outb(0xc0, SMBHSTCNT); - outb(command & 0xff, SMBHSTCMD); - outb(no & 0x1f, SMBHSTDAT0); - - for(i = 1; i <= no; i++) { - outb(*p++, SMBBLKDAT); - } - outb(0xff, SMBHSTSTART); - - temp = inb(SMBHSTSTS); - for (timeout = 0; (timeout < MAX_TIMEOUT) && !(temp & (ALI15X3_STS_ERR | ALI15X3_STS_DONE)); timeout++) { - delay1000(); - temp = inb(SMBHSTSTS); - } - if (timeout >= MAX_TIMEOUT) { - return -2; - } - if ( temp & ALI15X3_STS_ERR ){ - return -3; - } - return 0; -} - -static struct resource heartbeat_resources[] = { - [0] = { - .start = 0xa2000000, - .end = 0xa2000000, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device heartbeat_device = { - .name = "heartbeat", - .id = -1, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, -}; - -static struct platform_device *mpc1211_devices[] __initdata = { - &heartbeat_device, -}; - -static int __init mpc1211_devices_setup(void) -{ - return platform_add_devices(mpc1211_devices, - ARRAY_SIZE(mpc1211_devices)); -} -__initcall(mpc1211_devices_setup); - -/* arch/sh/boards/mpc1211/rtc.c */ -void mpc1211_time_init(void); - -static void __init mpc1211_setup(char **cmdline_p) -{ - unsigned char spd_buf[128]; - - __set_io_port_base(PA_PCI_IO); - - pci_write_config(0,0,0,0x54, 0xb0b00000); - - do { - outb(ALI15X3_ABORT, SMBHSTCNT); - spd_buf[0] = 0x0c; - spd_buf[1] = 0x43; - spd_buf[2] = 0x7f; - spd_buf[3] = 0x03; - spd_buf[4] = 0x00; - spd_buf[5] = 0x03; - spd_buf[6] = 0x00; - } while (put_smb_blk(spd_buf, 0x69, 0, 7) < 0); - - board_time_init = mpc1211_time_init; - - return 0; -} - -/* - * The Machine Vector - */ -static struct sh_machine_vector mv_mpc1211 __initmv = { - .mv_name = "Interface MPC-1211(CTP/PCI/MPC-SH02)", - .mv_setup = mpc1211_setup, - .mv_nr_irqs = 48, - .mv_irq_demux = mpc1211_irq_demux, - .mv_init_irq = init_mpc1211_IRQ, -}; diff --git a/arch/sh/boards/renesas/edosk7705/Makefile b/arch/sh/boards/renesas/edosk7705/Makefile deleted file mode 100644 index 14bdd531f11..00000000000 --- a/arch/sh/boards/renesas/edosk7705/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the EDOSK7705 specific parts of the kernel -# - -obj-y := setup.o io.o - diff --git a/arch/sh/boards/renesas/edosk7705/io.c b/arch/sh/boards/renesas/edosk7705/io.c deleted file mode 100644 index 541cea2a652..00000000000 --- a/arch/sh/boards/renesas/edosk7705/io.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * arch/sh/boards/renesas/edosk7705/io.c - * - * Copyright (C) 2001 Ian da Silva, Jeremy Siegel - * Based largely on io_se.c. - * - * I/O routines for Hitachi EDOSK7705 board. - * - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <asm/io.h> -#include <asm/edosk7705/io.h> -#include <asm/addrspace.h> - -#define SMC_IOADDR 0xA2000000 - -#define maybebadio(name,port) \ - printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \ - #name, (port), (__u32) __builtin_return_address(0)) - -/* Map the Ethernet addresses as if it is at 0x300 - 0x320 */ -unsigned long sh_edosk7705_isa_port2addr(unsigned long port) -{ - if (port >= 0x300 && port < 0x320) { - /* SMC91C96 registers are 4 byte aligned rather than the - * usual 2 byte! - */ - return SMC_IOADDR + ( (port - 0x300) * 2); - } - - maybebadio(sh_edosk7705_isa_port2addr, port); - return port; -} - -/* Trying to read / write bytes on odd-byte boundaries to the Ethernet - * registers causes problems. So we bit-shift the value and read / write - * in 2 byte chunks. Setting the low byte to 0 does not cause problems - * now as odd byte writes are only made on the bit mask / interrupt - * register. This may not be the case in future Mar-2003 SJD - */ -unsigned char sh_edosk7705_inb(unsigned long port) -{ - if (port >= 0x300 && port < 0x320 && port & 0x01) { - return (volatile unsigned char)(generic_inw(port -1) >> 8); - } - return *(volatile unsigned char *)sh_edosk7705_isa_port2addr(port); -} - -unsigned int sh_edosk7705_inl(unsigned long port) -{ - return *(volatile unsigned long *)port; -} - -void sh_edosk7705_outb(unsigned char value, unsigned long port) -{ - if (port >= 0x300 && port < 0x320 && port & 0x01) { - generic_outw(((unsigned short)value << 8), port -1); - return; - } - *(volatile unsigned char *)sh_edosk7705_isa_port2addr(port) = value; -} - -void sh_edosk7705_outl(unsigned int value, unsigned long port) -{ - *(volatile unsigned long *)port = value; -} - -void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count) -{ - unsigned char *p = addr; - while (count--) *p++ = sh_edosk7705_inb(port); -} - -void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count) -{ - unsigned long *p = (unsigned long*)addr; - while (count--) - *p++ = *(volatile unsigned long *)port; -} - -void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count) -{ - unsigned char *p = (unsigned char*)addr; - while (count--) sh_edosk7705_outb(*p++, port); -} - -void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count) -{ - unsigned long *p = (unsigned long*)addr; - while (count--) sh_edosk7705_outl(*p++, port); -} - diff --git a/arch/sh/boards/renesas/edosk7705/setup.c b/arch/sh/boards/renesas/edosk7705/setup.c deleted file mode 100644 index f076c45308d..00000000000 --- a/arch/sh/boards/renesas/edosk7705/setup.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/sh/boards/renesas/edosk7705/setup.c - * - * Copyright (C) 2000 Kazumoto Kojima - * - * Hitachi SolutionEngine Support. - * - * Modified for edosk7705 development - * board by S. Dunn, 2003. - */ -#include <linux/init.h> -#include <asm/machvec.h> -#include <asm/edosk7705/io.h> - -static void __init sh_edosk7705_init_irq(void) -{ - /* This is the Ethernet interrupt */ - make_imask_irq(0x09); -} - -/* - * The Machine Vector - */ -static struct sh_machine_vector mv_edosk7705 __initmv = { - .mv_name = "EDOSK7705", - .mv_nr_irqs = 80, - - .mv_inb = sh_edosk7705_inb, - .mv_inl = sh_edosk7705_inl, - .mv_outb = sh_edosk7705_outb, - .mv_outl = sh_edosk7705_outl, - - .mv_inl_p = sh_edosk7705_inl, - .mv_outl_p = sh_edosk7705_outl, - - .mv_insb = sh_edosk7705_insb, - .mv_insl = sh_edosk7705_insl, - .mv_outsb = sh_edosk7705_outsb, - .mv_outsl = sh_edosk7705_outsl, - - .mv_isa_port2addr = sh_edosk7705_isa_port2addr, - .mv_init_irq = sh_edosk7705_init_irq, -}; diff --git a/arch/sh/boards/renesas/migor/Makefile b/arch/sh/boards/renesas/migor/Makefile deleted file mode 100644 index 77037567633..00000000000 --- a/arch/sh/boards/renesas/migor/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y := setup.o diff --git a/arch/sh/boards/renesas/migor/setup.c b/arch/sh/boards/renesas/migor/setup.c deleted file mode 100644 index 21ab8c8fb59..00000000000 --- a/arch/sh/boards/renesas/migor/setup.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Renesas System Solutions Asia Pte. Ltd - Migo-R - * - * Copyright (C) 2008 Magnus Damm - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <asm/machvec.h> -#include <asm/io.h> - -/* Address IRQ Size Bus Description - * 0x00000000 64MB 16 NOR Flash (SP29PL256N) - * 0x0c000000 64MB 64 SDRAM (2xK4M563233G) - * 0x10000000 IRQ0 16 Ethernet (SMC91C111) - * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596) - * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A) - */ - -static struct resource smc91x_eth_resources[] = { - [0] = { - .name = "smc91x-regs" , - .start = P2SEGADDR(0x10000300), - .end = P2SEGADDR(0x1000030f), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 32, /* IRQ0 */ - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, - }, -}; - -static struct platform_device smc91x_eth_device = { - .name = "smc91x", - .num_resources = ARRAY_SIZE(smc91x_eth_resources), - .resource = smc91x_eth_resources, -}; - -static struct platform_device *migor_devices[] __initdata = { - &smc91x_eth_device, -}; - -static int __init migor_devices_setup(void) -{ - return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices)); -} -__initcall(migor_devices_setup); - -static void __init migor_setup(char **cmdline_p) -{ - ctrl_outw(0x1000, 0xa4050110); /* Enable IRQ0 in PJCR */ -} - -static struct sh_machine_vector mv_migor __initmv = { - .mv_name = "Migo-R", - .mv_setup = migor_setup, -}; diff --git a/arch/sh/boards/renesas/r7780rp/Makefile b/arch/sh/boards/renesas/r7780rp/Makefile deleted file mode 100644 index 20a10080b11..00000000000 --- a/arch/sh/boards/renesas/r7780rp/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for the R7780RP-1 specific parts of the kernel -# -irqinit-$(CONFIG_SH_R7780MP) := irq-r7780mp.o -irqinit-$(CONFIG_SH_R7785RP) := irq-r7785rp.o -irqinit-$(CONFIG_SH_R7780RP) := irq-r7780rp.o -obj-y := setup.o $(irqinit-y) - -ifneq ($(CONFIG_SH_R7785RP),y) -obj-$(CONFIG_PUSH_SWITCH) += psw.o -endif diff --git a/arch/sh/boards/renesas/systemh/Makefile b/arch/sh/boards/renesas/systemh/Makefile deleted file mode 100644 index 2cc6a23d9d3..00000000000 --- a/arch/sh/boards/renesas/systemh/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Makefile for the SystemH specific parts of the kernel -# - -obj-y := setup.o irq.o io.o - -# XXX: This wants to be consolidated in arch/sh/drivers/pci, and more -# importantly, with the generic sh7751_pcic_init() code. For now, we'll -# just abuse the hell out of kbuild, because we can.. - -obj-$(CONFIG_PCI) += pci.o -pci-y := ../../se/7751/pci.o - diff --git a/arch/sh/boards/renesas/systemh/io.c b/arch/sh/boards/renesas/systemh/io.c deleted file mode 100644 index 1b767e1a142..00000000000 --- a/arch/sh/boards/renesas/systemh/io.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * linux/arch/sh/boards/renesas/systemh/io.c - * - * Copyright (C) 2001 Ian da Silva, Jeremy Siegel - * Based largely on io_se.c. - * - * I/O routine for Hitachi 7751 Systemh. - */ -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/pci.h> -#include <asm/systemh7751.h> -#include <asm/addrspace.h> -#include <asm/io.h> - -#define ETHER_IOMAP(adr) (0xB3000000 + (adr)) /*map to 16bits access area - of smc lan chip*/ -static inline volatile __u16 * -port2adr(unsigned int port) -{ - if (port >= 0x2000) - return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); - maybebadio((unsigned long)port); - return (volatile __u16*)port; -} - -/* - * General outline: remap really low stuff [eventually] to SuperIO, - * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO) - * is mapped through the PCI IO window. Stuff with high bits (PXSEG) - * should be way beyond the window, and is used w/o translation for - * compatibility. - */ -unsigned char sh7751systemh_inb(unsigned long port) -{ - if (PXSEG(port)) - return *(volatile unsigned char *)port; - else if (is_pci_ioaddr(port)) - return *(volatile unsigned char *)pci_ioaddr(port); - else if (port <= 0x3F1) - return *(volatile unsigned char *)ETHER_IOMAP(port); - else - return (*port2adr(port))&0xff; -} - -unsigned char sh7751systemh_inb_p(unsigned long port) -{ - unsigned char v; - - if (PXSEG(port)) - v = *(volatile unsigned char *)port; - else if (is_pci_ioaddr(port)) - v = *(volatile unsigned char *)pci_ioaddr(port); - else if (port <= 0x3F1) - v = *(volatile unsigned char *)ETHER_IOMAP(port); - else - v = (*port2adr(port))&0xff; - ctrl_delay(); - return v; -} - -unsigned short sh7751systemh_inw(unsigned long port) -{ - if (PXSEG(port)) - return *(volatile unsigned short *)port; - else if (is_pci_ioaddr(port)) - return *(volatile unsigned short *)pci_ioaddr(port); - else if (port >= 0x2000) - return *port2adr(port); - else if (port <= 0x3F1) - return *(volatile unsigned int *)ETHER_IOMAP(port); - else - maybebadio(port); - return 0; -} - -unsigned int sh7751systemh_inl(unsigned long port) -{ - if (PXSEG(port)) - return *(volatile unsigned long *)port; - else if (is_pci_ioaddr(port)) - return *(volatile unsigned int *)pci_ioaddr(port); - else if (port >= 0x2000) - return *port2adr(port); - else if (port <= 0x3F1) - return *(volatile unsigned int *)ETHER_IOMAP(port); - else - maybebadio(port); - return 0; -} - -void sh7751systemh_outb(unsigned char value, unsigned long port) -{ - - if (PXSEG(port)) - *(volatile unsigned char *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned char*)pci_ioaddr(port)) = value; - else if (port <= 0x3F1) - *(volatile unsigned char *)ETHER_IOMAP(port) = value; - else - *(port2adr(port)) = value; -} - -void sh7751systemh_outb_p(unsigned char value, unsigned long port) -{ - if (PXSEG(port)) - *(volatile unsigned char *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned char*)pci_ioaddr(port)) = value; - else if (port <= 0x3F1) - *(volatile unsigned char *)ETHER_IOMAP(port) = value; - else - *(port2adr(port)) = value; - ctrl_delay(); -} - -void sh7751systemh_outw(unsigned short value, unsigned long port) -{ - if (PXSEG(port)) - *(volatile unsigned short *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned short *)pci_ioaddr(port)) = value; - else if (port >= 0x2000) - *port2adr(port) = value; - else if (port <= 0x3F1) - *(volatile unsigned short *)ETHER_IOMAP(port) = value; - else - maybebadio(port); -} - -void sh7751systemh_outl(unsigned int value, unsigned long port) -{ - if (PXSEG(port)) - *(volatile unsigned long *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned long*)pci_ioaddr(port)) = value; - else - maybebadio(port); -} - -void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count) -{ - unsigned char *p = addr; - while (count--) *p++ = sh7751systemh_inb(port); -} - -void sh7751systemh_insw(unsigned long port, void *addr, unsigned long count) -{ - unsigned short *p = addr; - while (count--) *p++ = sh7751systemh_inw(port); -} - -void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count) -{ - maybebadio(port); -} - -void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count) -{ - unsigned char *p = (unsigned char*)addr; - while (count--) sh7751systemh_outb(*p++, port); -} - -void sh7751systemh_outsw(unsigned long port, const void *addr, unsigned long count) -{ - unsigned short *p = (unsigned short*)addr; - while (count--) sh7751systemh_outw(*p++, port); -} - -void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count) -{ - maybebadio(port); -} diff --git a/arch/sh/boards/renesas/systemh/irq.c b/arch/sh/boards/renesas/systemh/irq.c deleted file mode 100644 index 0ba2fe674c4..00000000000 --- a/arch/sh/boards/renesas/systemh/irq.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * linux/arch/sh/boards/renesas/systemh/irq.c - * - * Copyright (C) 2000 Kazumoto Kojima - * - * Hitachi SystemH Support. - * - * Modified for 7751 SystemH by - * Jonathan Short. - */ - -#include <linux/init.h> -#include <linux/irq.h> - -#include <linux/hdreg.h> -#include <linux/ide.h> -#include <asm/io.h> -#include <asm/systemh7751.h> -#include <asm/smc37c93x.h> - -/* address of external interrupt mask register - * address must be set prior to use these (maybe in init_XXX_irq()) - * XXX : is it better to use .config than specifying it in code? */ -static unsigned long *systemh_irq_mask_register = (unsigned long *)0xB3F10004; -static unsigned long *systemh_irq_request_register = (unsigned long *)0xB3F10000; - -/* forward declaration */ -static unsigned int startup_systemh_irq(unsigned int irq); -static void shutdown_systemh_irq(unsigned int irq); -static void enable_systemh_irq(unsigned int irq); -static void disable_systemh_irq(unsigned int irq); -static void mask_and_ack_systemh(unsigned int); -static void end_systemh_irq(unsigned int irq); - -/* hw_interrupt_type */ -static struct hw_interrupt_type systemh_irq_type = { - .typename = " SystemH Register", - .startup = startup_systemh_irq, - .shutdown = shutdown_systemh_irq, - .enable = enable_systemh_irq, - .disable = disable_systemh_irq, - .ack = mask_and_ack_systemh, - .end = end_systemh_irq -}; - -static unsigned int startup_systemh_irq(unsigned int irq) -{ - enable_systemh_irq(irq); - return 0; /* never anything pending */ -} - -static void shutdown_systemh_irq(unsigned int irq) -{ - disable_systemh_irq(irq); -} - -static void disable_systemh_irq(unsigned int irq) -{ - if (systemh_irq_mask_register) { - unsigned long val, mask = 0x01 << 1; - - /* Clear the "irq"th bit in the mask and set it in the request */ - val = ctrl_inl((unsigned long)systemh_irq_mask_register); - val &= ~mask; - ctrl_outl(val, (unsigned long)systemh_irq_mask_register); - - val = ctrl_inl((unsigned long)systemh_irq_request_register); - val |= mask; - ctrl_outl(val, (unsigned long)systemh_irq_request_register); - } -} - -static void enable_systemh_irq(unsigned int irq) -{ - if (systemh_irq_mask_register) { - unsigned long val, mask = 0x01 << 1; - - /* Set "irq"th bit in the mask register */ - val = ctrl_inl((unsigned long)systemh_irq_mask_register); - val |= mask; - ctrl_outl(val, (unsigned long)systemh_irq_mask_register); - } -} - -static void mask_and_ack_systemh(unsigned int irq) -{ - disable_systemh_irq(irq); -} - -static void end_systemh_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_systemh_irq(irq); -} - -void make_systemh_irq(unsigned int irq) -{ - disable_irq_nosync(irq); - irq_desc[irq].chip = &systemh_irq_type; - disable_systemh_irq(irq); -} - diff --git a/arch/sh/boards/renesas/systemh/setup.c b/arch/sh/boards/renesas/systemh/setup.c deleted file mode 100644 index ee78af84277..00000000000 --- a/arch/sh/boards/renesas/systemh/setup.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * linux/arch/sh/boards/renesas/systemh/setup.c - * - * Copyright (C) 2000 Kazumoto Kojima - * Copyright (C) 2003 Paul Mundt - * - * Hitachi SystemH Support. - * - * Modified for 7751 SystemH by Jonathan Short. - * - * Rewritten for 2.6 by Paul Mundt. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <asm/machvec.h> -#include <asm/systemh7751.h> - -extern void make_systemh_irq(unsigned int irq); - -/* - * Initialize IRQ setting - */ -static void __init sh7751systemh_init_irq(void) -{ - make_systemh_irq(0xb); /* Ethernet interrupt */ -} - -static struct sh_machine_vector mv_7751systemh __initmv = { - .mv_name = "7751 SystemH", - .mv_nr_irqs = 72, - - .mv_inb = sh7751systemh_inb, - .mv_inw = sh7751systemh_inw, - .mv_inl = sh7751systemh_inl, - .mv_outb = sh7751systemh_outb, - .mv_outw = sh7751systemh_outw, - .mv_outl = sh7751systemh_outl, - - .mv_inb_p = sh7751systemh_inb_p, - .mv_inw_p = sh7751systemh_inw, - .mv_inl_p = sh7751systemh_inl, - .mv_outb_p = sh7751systemh_outb_p, - .mv_outw_p = sh7751systemh_outw, - .mv_outl_p = sh7751systemh_outl, - - .mv_insb = sh7751systemh_insb, - .mv_insw = sh7751systemh_insw, - .mv_insl = sh7751systemh_insl, - .mv_outsb = sh7751systemh_outsb, - .mv_outsw = sh7751systemh_outsw, - .mv_outsl = sh7751systemh_outsl, - - .mv_init_irq = sh7751systemh_init_irq, -}; diff --git a/arch/sh/boards/renesas/x3proto/Makefile b/arch/sh/boards/renesas/x3proto/Makefile deleted file mode 100644 index 983e4551fec..00000000000 --- a/arch/sh/boards/renesas/x3proto/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += setup.o ilsel.o diff --git a/arch/sh/boards/renesas/x3proto/setup.c b/arch/sh/boards/renesas/x3proto/setup.c deleted file mode 100644 index abc5b6d418f..00000000000 --- a/arch/sh/boards/renesas/x3proto/setup.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * arch/sh/boards/renesas/x3proto/setup.c - * - * Renesas SH-X3 Prototype Board Support. - * - * Copyright (C) 2007 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <asm/ilsel.h> - -static struct resource heartbeat_resources[] = { - [0] = { - .start = 0xb8140020, - .end = 0xb8140020, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device heartbeat_device = { - .name = "heartbeat", - .id = -1, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = 0x18000300, - .end = 0x18000300 + 0x10 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - /* Filled in by ilsel */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = -1, - .resource = smc91x_resources, - .num_resources = ARRAY_SIZE(smc91x_resources), -}; - -static struct resource r8a66597_usb_host_resources[] = { - [0] = { - .name = "r8a66597_hcd", - .start = 0x18040000, - .end = 0x18080000 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "r8a66597_hcd", - /* Filled in by ilsel */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device r8a66597_usb_host_device = { - .name = "r8a66597_hcd", - .id = -1, - .dev = { - .dma_mask = NULL, /* don't use dma */ - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), - .resource = r8a66597_usb_host_resources, -}; - -static struct resource m66592_usb_peripheral_resources[] = { - [0] = { - .name = "m66592_udc", - .start = 0x18080000, - .end = 0x180c0000 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "m66592_udc", - /* Filled in by ilsel */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device m66592_usb_peripheral_device = { - .name = "m66592_udc", - .id = -1, - .dev = { - .dma_mask = NULL, /* don't use dma */ - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(m66592_usb_peripheral_resources), - .resource = m66592_usb_peripheral_resources, -}; - -static struct platform_device *x3proto_devices[] __initdata = { - &heartbeat_device, - &smc91x_device, - &r8a66597_usb_host_device, - &m66592_usb_peripheral_device, -}; - -static int __init x3proto_devices_setup(void) -{ - r8a66597_usb_host_resources[1].start = - r8a66597_usb_host_resources[1].end = ilsel_enable(ILSEL_USBH_I); - - m66592_usb_peripheral_resources[1].start = - m66592_usb_peripheral_resources[1].end = ilsel_enable(ILSEL_USBP_I); - - smc91x_resources[1].start = - smc91x_resources[1].end = ilsel_enable(ILSEL_LAN); - - return platform_add_devices(x3proto_devices, - ARRAY_SIZE(x3proto_devices)); -} -device_initcall(x3proto_devices_setup); - -static void __init x3proto_init_irq(void) -{ - plat_irq_setup_pins(IRQ_MODE_IRL3210); - - /* Set ICR0.LVLMODE */ - ctrl_outl(ctrl_inl(0xfe410000) | (1 << 21), 0xfe410000); -} - -static struct sh_machine_vector mv_x3proto __initmv = { - .mv_name = "x3proto", - .mv_init_irq = x3proto_init_irq, -}; diff --git a/arch/sh/boards/se/7206/io.c b/arch/sh/boards/se/7206/io.c deleted file mode 100644 index 1308e618e04..00000000000 --- a/arch/sh/boards/se/7206/io.c +++ /dev/null @@ -1,104 +0,0 @@ -/* $Id: io.c,v 1.5 2004/02/22 23:08:43 kkojima Exp $ - * - * linux/arch/sh/boards/se/7206/io.c - * - * Copyright (C) 2006 Yoshinori Sato - * - * I/O routine for Hitachi 7206 SolutionEngine. - * - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <asm/io.h> -#include <asm/se7206.h> - - -static inline void delay(void) -{ - ctrl_inw(0x20000000); /* P2 ROM Area */ -} - -/* MS7750 requires special versions of in*, out* routines, since - PC-like io ports are located at upper half byte of 16-bit word which - can be accessed only with 16-bit wide. */ - -static inline volatile __u16 * -port2adr(unsigned int port) -{ - if (port >= 0x2000 && port < 0x2020) - return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); - else if (port >= 0x300 && port < 0x310) - return (volatile __u16 *) (PA_SMSC + (port - 0x300)); - - return (volatile __u16 *)port; -} - -unsigned char se7206_inb(unsigned long port) -{ - return (*port2adr(port)) & 0xff; -} - -unsigned char se7206_inb_p(unsigned long port) -{ - unsigned long v; - - v = (*port2adr(port)) & 0xff; - delay(); - return v; -} - -unsigned short se7206_inw(unsigned long port) -{ - return *port2adr(port);; -} - -void se7206_outb(unsigned char value, unsigned long port) -{ - *(port2adr(port)) = value; -} - -void se7206_outb_p(unsigned char value, unsigned long port) -{ - *(port2adr(port)) = value; - delay(); -} - -void se7206_outw(unsigned short value, unsigned long port) -{ - *port2adr(port) = value; -} - -void se7206_insb(unsigned long port, void *addr, unsigned long count) -{ - volatile __u16 *p = port2adr(port); - __u8 *ap = addr; - - while (count--) - *ap++ = *p; -} - -void se7206_insw(unsigned long port, void *addr, unsigned long count) -{ - volatile __u16 *p = port2adr(port); - __u16 *ap = addr; - while (count--) - *ap++ = *p; -} - -void se7206_outsb(unsigned long port, const void *addr, unsigned long count) -{ - volatile __u16 *p = port2adr(port); - const __u8 *ap = addr; - - while (count--) - *p = *ap++; -} - -void se7206_outsw(unsigned long port, const void *addr, unsigned long count) -{ - volatile __u16 *p = port2adr(port); - const __u16 *ap = addr; - while (count--) - *p = *ap++; -} diff --git a/arch/sh/boards/se/7343/io.c b/arch/sh/boards/se/7343/io.c deleted file mode 100644 index 3a6d1142493..00000000000 --- a/arch/sh/boards/se/7343/io.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * arch/sh/boards/se/7343/io.c - * - * I/O routine for SH-Mobile3AS 7343 SolutionEngine. - * - */ -#include <linux/kernel.h> -#include <asm/io.h> -#include <asm/mach/se7343.h> - -#define badio(fn, a) panic("bad i/o operation %s for %08lx.", #fn, a) - -struct iop { - unsigned long start, end; - unsigned long base; - struct iop *(*check) (struct iop * p, unsigned long port); - unsigned char (*inb) (struct iop * p, unsigned long port); - unsigned short (*inw) (struct iop * p, unsigned long port); - void (*outb) (struct iop * p, unsigned char value, unsigned long port); - void (*outw) (struct iop * p, unsigned short value, unsigned long port); -}; - -struct iop * -simple_check(struct iop *p, unsigned long port) -{ - static int count; - - if (count < 100) - count++; - - port &= 0xFFFF; - - if ((p->start <= port) && (port <= p->end)) - return p; - else - badio(check, port); -} - -struct iop * -ide_check(struct iop *p, unsigned long port) -{ - if (((0x1f0 <= port) && (port <= 0x1f7)) || (port == 0x3f7)) - return p; - return NULL; -} - -unsigned char -simple_inb(struct iop *p, unsigned long port) -{ - return *(unsigned char *) (p->base + port); -} - -unsigned short -simple_inw(struct iop *p, unsigned long port) -{ - return *(unsigned short *) (p->base + port); -} - -void -simple_outb(struct iop *p, unsigned char value, unsigned long port) -{ - *(unsigned char *) (p->base + port) = value; -} - -void -simple_outw(struct iop *p, unsigned short value, unsigned long port) -{ - *(unsigned short *) (p->base + port) = value; -} - -unsigned char -pcc_inb(struct iop *p, unsigned long port) -{ - unsigned long addr = p->base + port + 0x40000; - unsigned long v; - - if (port & 1) - addr += 0x00400000; - v = *(volatile unsigned char *) addr; - return v; -} - -void -pcc_outb(struct iop *p, unsigned char value, unsigned long port) -{ - unsigned long addr = p->base + port + 0x40000; - - if (port & 1) - addr += 0x00400000; - *(volatile unsigned char *) addr = value; -} - -unsigned char -bad_inb(struct iop *p, unsigned long port) -{ - badio(inb, port); -} - -void -bad_outb(struct iop *p, unsigned char value, unsigned long port) -{ - badio(inw, port); -} - -#ifdef CONFIG_SMC91X -/* MSTLANEX01 LAN at 0xb400:0000 */ -static struct iop laniop = { - .start = 0x00, - .end = 0x0F, - .base = 0x04000000, - .check = simple_check, - .inb = simple_inb, - .inw = simple_inw, - .outb = simple_outb, - .outw = simple_outw, -}; -#endif - -#ifdef CONFIG_NE2000 -/* NE2000 pc card NIC */ -static struct iop neiop = { - .start = 0x280, - .end = 0x29f, - .base = 0xb0600000 + 0x80, /* soft 0x280 -> hard 0x300 */ - .check = simple_check, - .inb = pcc_inb, - .inw = simple_inw, - .outb = pcc_outb, - .outw = simple_outw, -}; -#endif - -#ifdef CONFIG_IDE -/* CF in CF slot */ -static struct iop cfiop = { - .base = 0xb0600000, - .check = ide_check, - .inb = pcc_inb, - .inw = simple_inw, - .outb = pcc_outb, - .outw = simple_outw, -}; -#endif - -static __inline__ struct iop * -port2iop(unsigned long port) -{ - if (0) ; -#if defined(CONFIG_SMC91X) - else if (laniop.check(&laniop, port)) - return &laniop; -#endif -#if defined(CONFIG_NE2000) - else if (neiop.check(&neiop, port)) - return &neiop; -#endif -#if defined(CONFIG_IDE) - else if (cfiop.check(&cfiop, port)) - return &cfiop; -#endif - else - return NULL; -} - -static inline void -delay(void) -{ - ctrl_inw(0xac000000); - ctrl_inw(0xac000000); -} - -unsigned char -sh7343se_inb(unsigned long port) -{ - struct iop *p = port2iop(port); - return (p->inb) (p, port); -} - -unsigned char -sh7343se_inb_p(unsigned long port) -{ - unsigned char v = sh7343se_inb(port); - delay(); - return v; -} - -unsigned short -sh7343se_inw(unsigned long port) -{ - struct iop *p = port2iop(port); - return (p->inw) (p, port); -} - -unsigned int -sh7343se_inl(unsigned long port) -{ - badio(inl, port); -} - -void -sh7343se_outb(unsigned char value, unsigned long port) -{ - struct iop *p = port2iop(port); - (p->outb) (p, value, port); -} - -void -sh7343se_outb_p(unsigned char value, unsigned long port) -{ - sh7343se_outb(value, port); - delay(); -} - -void -sh7343se_outw(unsigned short value, unsigned long port) -{ - struct iop *p = port2iop(port); - (p->outw) (p, value, port); -} - -void -sh7343se_outl(unsigned int value, unsigned long port) -{ - badio(outl, port); -} - -void -sh7343se_insb(unsigned long port, void *addr, unsigned long count) -{ - unsigned char *a = addr; - struct iop *p = port2iop(port); - while (count--) - *a++ = (p->inb) (p, port); -} - -void -sh7343se_insw(unsigned long port, void *addr, unsigned long count) -{ - unsigned short *a = addr; - struct iop *p = port2iop(port); - while (count--) - *a++ = (p->inw) (p, port); -} - -void -sh7343se_insl(unsigned long port, void *addr, unsigned long count) -{ - badio(insl, port); -} - -void -sh7343se_outsb(unsigned long port, const void *addr, unsigned long count) -{ - unsigned char *a = (unsigned char *) addr; - struct iop *p = port2iop(port); - while (count--) - (p->outb) (p, *a++, port); -} - -void -sh7343se_outsw(unsigned long port, const void *addr, unsigned long count) -{ - unsigned short *a = (unsigned short *) addr; - struct iop *p = port2iop(port); - while (count--) - (p->outw) (p, *a++, port); -} - -void -sh7343se_outsl(unsigned long port, const void *addr, unsigned long count) -{ - badio(outsw, port); -} diff --git a/arch/sh/boards/se/7343/irq.c b/arch/sh/boards/se/7343/irq.c deleted file mode 100644 index 763f6deba81..00000000000 --- a/arch/sh/boards/se/7343/irq.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * arch/sh/boards/se/7343/irq.c - * - */ -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <asm/irq.h> -#include <asm/io.h> -#include <asm/mach/se7343.h> - -static void -disable_intreq_irq(unsigned int irq) -{ - int bit = irq - OFFCHIP_IRQ_BASE; - u16 val; - - val = ctrl_inw(PA_CPLD_IMSK); - val |= 1 << bit; - ctrl_outw(val, PA_CPLD_IMSK); -} - -static void -enable_intreq_irq(unsigned int irq) -{ - int bit = irq - OFFCHIP_IRQ_BASE; - u16 val; - - val = ctrl_inw(PA_CPLD_IMSK); - val &= ~(1 << bit); - ctrl_outw(val, PA_CPLD_IMSK); -} - -static void -mask_and_ack_intreq_irq(unsigned int irq) -{ - disable_intreq_irq(irq); -} - -static unsigned int -startup_intreq_irq(unsigned int irq) -{ - enable_intreq_irq(irq); - return 0; -} - -static void -shutdown_intreq_irq(unsigned int irq) -{ - disable_intreq_irq(irq); -} - -static void -end_intreq_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - enable_intreq_irq(irq); -} - -static struct hw_interrupt_type intreq_irq_type = { - .typename = "FPGA-IRQ", - .startup = startup_intreq_irq, - .shutdown = shutdown_intreq_irq, - .enable = enable_intreq_irq, - .disable = disable_intreq_irq, - .ack = mask_and_ack_intreq_irq, - .end = end_intreq_irq -}; - -static void -make_intreq_irq(unsigned int irq) -{ - disable_irq_nosync(irq); - irq_desc[irq].chip = &intreq_irq_type; - disable_intreq_irq(irq); -} - -int -shmse_irq_demux(int irq) -{ - int bit; - volatile u16 val; - - if (irq == IRQ5_IRQ) { - /* Read status Register */ - val = ctrl_inw(PA_CPLD_ST); - bit = ffs(val); - if (bit != 0) - return OFFCHIP_IRQ_BASE + bit - 1; - } - return irq; -} - -/* IRQ5 is multiplexed between the following sources: - * 1. PC Card socket - * 2. Extension slot - * 3. USB Controller - * 4. Serial Controller - * - * We configure IRQ5 as a cascade IRQ. - */ -static struct irqaction irq5 = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "IRQ5-cascade", -}; - -static struct ipr_data se7343_irq5_ipr_map[] = { - { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY }, -}; -static struct ipr_data se7343_siof0_vpu_ipr_map[] = { - { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, - { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 }, -}; -static struct ipr_data se7343_other_ipr_map[] = { - { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, - { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, - { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, - { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, - { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, - { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, - - /* I2C block */ - { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, - { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, - { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, - { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, - - { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, - { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, - { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, - { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, - - /* SIOF */ - { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, - - /* SIU */ - { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY }, - - /* VIO interrupt */ - { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, - { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, - { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, - - /*MFI interrupt*/ - - { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY }, - - /* LCD controller */ - { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY }, -}; - -/* - * Initialize IRQ setting - */ -void __init -init_7343se_IRQ(void) -{ - /* Setup Multiplexed interrupts */ - ctrl_outw(8, PA_CPLD_MODESET); /* Set all CPLD interrupts to active - * low. - */ - /* Mask all CPLD controller interrupts */ - ctrl_outw(0x0fff, PA_CPLD_IMSK); - - /* PC Card interrupts */ - make_intreq_irq(PC_IRQ0); - make_intreq_irq(PC_IRQ1); - make_intreq_irq(PC_IRQ2); - make_intreq_irq(PC_IRQ3); - - /* Extension Slot Interrupts */ - make_intreq_irq(EXT_IRQ0); - make_intreq_irq(EXT_IRQ1); - make_intreq_irq(EXT_IRQ2); - make_intreq_irq(EXT_IRQ3); - - /* USB Controller interrupts */ - make_intreq_irq(USB_IRQ0); - make_intreq_irq(USB_IRQ1); - - /* Serial Controller interrupts */ - make_intreq_irq(UART_IRQ0); - make_intreq_irq(UART_IRQ1); - - /* Setup all external interrupts to be active low */ - ctrl_outw(0xaaaa, INTC_ICR1); - - make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map)); - - setup_irq(IRQ5_IRQ, &irq5); - /* Set port control to use IRQ5 */ - *(u16 *)0xA4050108 &= ~0xc; - - make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map)); - - ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ - - make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map)); - - ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ -} diff --git a/arch/sh/boards/se/7343/setup.c b/arch/sh/boards/se/7343/setup.c deleted file mode 100644 index c9431b3a051..00000000000 --- a/arch/sh/boards/se/7343/setup.c +++ /dev/null @@ -1,94 +0,0 @@ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <asm/machvec.h> -#include <asm/mach/se7343.h> -#include <asm/irq.h> - -void init_7343se_IRQ(void); - -static struct resource smc91x_resources[] = { - [0] = { - .start = 0x10000000, - .end = 0x1000000F, - .flags = IORESOURCE_MEM, - }, - [1] = { - /* - * shared with other devices via externel - * interrupt controller in FPGA... - */ - .start = EXT_IRQ2, - .end = EXT_IRQ2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct resource heartbeat_resources[] = { - [0] = { - .start = PA_LED, - .end = PA_LED, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device heartbeat_device = { - .name = "heartbeat", - .id = -1, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, -}; - -static struct platform_device *sh7343se_platform_devices[] __initdata = { - &smc91x_device, - &heartbeat_device, -}; - -static int __init sh7343se_devices_setup(void) -{ - return platform_add_devices(sh7343se_platform_devices, - ARRAY_SIZE(sh7343se_platform_devices)); -} - -static void __init sh7343se_setup(char **cmdline_p) -{ - device_initcall(sh7343se_devices_setup); -} - -/* - * The Machine Vector - */ -static struct sh_machine_vector mv_7343se __initmv = { - .mv_name = "SolutionEngine 7343", - .mv_setup = sh7343se_setup, - .mv_nr_irqs = 108, - .mv_inb = sh7343se_inb, - .mv_inw = sh7343se_inw, - .mv_inl = sh7343se_inl, - .mv_outb = sh7343se_outb, - .mv_outw = sh7343se_outw, - .mv_outl = sh7343se_outl, - - .mv_inb_p = sh7343se_inb_p, - .mv_inw_p = sh7343se_inw, - .mv_inl_p = sh7343se_inl, - .mv_outb_p = sh7343se_outb_p, - .mv_outw_p = sh7343se_outw, - .mv_outl_p = sh7343se_outl, - - .mv_insb = sh7343se_insb, - .mv_insw = sh7343se_insw, - .mv_insl = sh7343se_insl, - .mv_outsb = sh7343se_outsb, - .mv_outsw = sh7343se_outsw, - .mv_outsl = sh7343se_outsl, - - .mv_init_irq = init_7343se_IRQ, - .mv_irq_demux = shmse_irq_demux, -}; diff --git a/arch/sh/boards/se/7619/Makefile b/arch/sh/boards/se/7619/Makefile deleted file mode 100644 index d21775c28cd..00000000000 --- a/arch/sh/boards/se/7619/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the 7619 SolutionEngine specific parts of the kernel -# - -obj-y := setup.o diff --git a/arch/sh/boards/se/770x/io.c b/arch/sh/boards/se/770x/io.c deleted file mode 100644 index c4550473d4c..00000000000 --- a/arch/sh/boards/se/770x/io.c +++ /dev/null @@ -1,187 +0,0 @@ -/* $Id: io.c,v 1.7 2006/02/05 21:55:29 lethal Exp $ - * - * linux/arch/sh/kernel/io_se.c - * - * Copyright (C) 2000 Kazumoto Kojima - * - * I/O routine for Hitachi SolutionEngine. - * - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <asm/io.h> -#include <asm/se.h> - -/* SH pcmcia io window base, start and end. */ -int sh_pcic_io_wbase = 0xb8400000; -int sh_pcic_io_start; -int sh_pcic_io_stop; -int sh_pcic_io_type; -int sh_pcic_io_dummy; - -/* MS7750 requires special versions of in*, out* routines, since - PC-like io ports are located at upper half byte of 16-bit word which - can be accessed only with 16-bit wide. */ - -static inline volatile __u16 * -port2adr(unsigned int port) -{ - if (port & 0xff000000) - return ( volatile __u16 *) port; - if (port >= 0x2000) - return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); - else if (port >= 0x1000) - return (volatile __u16 *) (PA_83902 + (port << 1)); - else if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) - return (volatile __u16 *) (sh_pcic_io_wbase + (port &~ 1)); - else - return (volatile __u16 *) (PA_SUPERIO + (port << 1)); -} - -static inline int -shifted_port(unsigned long port) -{ - /* For IDE registers, value is not shifted */ - if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6) - return 0; - else - return 1; -} - -unsigned char se_inb(unsigned long port) -{ - if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) - return *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port); - else if (shifted_port(port)) - return (*port2adr(port) >> 8); - else - return (*port2adr(port))&0xff; -} - -unsigned char se_inb_p(unsigned long port) -{ - unsigned long v; - - if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) - v = *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port); - else if (shifted_port(port)) - v = (*port2adr(port) >> 8); - else - v = (*port2adr(port))&0xff; - ctrl_delay(); - return v; -} - -unsigned short se_inw(unsigned long port) -{ - if (port >= 0x2000 || - (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)) - return *port2adr(port); - else - maybebadio(port); - return 0; -} - -unsigned int se_inl(unsigned long port) -{ - maybebadio(port); - return 0; -} - -void se_outb(unsigned char value, unsigned long port) -{ - if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) - *(__u8 *)(sh_pcic_io_wbase + port) = value; - else if (shifted_port(port)) - *(port2adr(port)) = value << 8; - else - *(port2adr(port)) = value; -} - -void se_outb_p(unsigned char value, unsigned long port) -{ - if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) - *(__u8 *)(sh_pcic_io_wbase + port) = value; - else if (shifted_port(port)) - *(port2adr(port)) = value << 8; - else - *(port2adr(port)) = value; - ctrl_delay(); -} - -void se_outw(unsigned short value, unsigned long port) -{ - if (port >= 0x2000 || - (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)) - *port2adr(port) = value; - else - maybebadio(port); -} - -void se_outl(unsigned int value, unsigned long port) -{ - maybebadio(port); -} - -void se_insb(unsigned long port, void *addr, unsigned long count) -{ - volatile __u16 *p = port2adr(port); - __u8 *ap = addr; - - if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) { - volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + 0x40000 + port); - while (count--) - *ap++ = *bp; - } else if (shifted_port(port)) { - while (count--) - *ap++ = *p >> 8; - } else { - while (count--) - *ap++ = *p; - } -} - -void se_insw(unsigned long port, void *addr, unsigned long count) -{ - volatile __u16 *p = port2adr(port); - __u16 *ap = addr; - while (count--) - *ap++ = *p; -} - -void se_insl(unsigned long port, void *addr, unsigned long count) -{ - maybebadio(port); -} - -void se_outsb(unsigned long port, const void *addr, unsigned long count) -{ - volatile __u16 *p = port2adr(port); - const __u8 *ap = addr; - - if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) { - volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + port); - while (count--) - *bp = *ap++; - } else if (shifted_port(port)) { - while (count--) - *p = *ap++ << 8; - } else { - while (count--) - *p = *ap++; - } -} - -void se_outsw(unsigned long port, const void *addr, unsigned long count) -{ - volatile __u16 *p = port2adr(port); - const __u16 *ap = addr; - while (count--) - *p = *ap++; -} - -void se_outsl(unsigned long port, const void *addr, unsigned long count) -{ - maybebadio(port); -} diff --git a/arch/sh/boards/se/7722/irq.c b/arch/sh/boards/se/7722/irq.c deleted file mode 100644 index 0b03f3f610b..00000000000 --- a/arch/sh/boards/se/7722/irq.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * linux/arch/sh/boards/se/7722/irq.c - * - * Copyright (C) 2007 Nobuhiro Iwamatsu - * - * Hitachi UL SolutionEngine 7722 Support. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <asm/irq.h> -#include <asm/io.h> -#include <asm/se7722.h> - -static void disable_se7722_irq(unsigned int irq) -{ - unsigned int bit = irq - SE7722_FPGA_IRQ_BASE; - ctrl_outw(ctrl_inw(IRQ01_MASK) | 1 << bit, IRQ01_MASK); -} - -static void enable_se7722_irq(unsigned int irq) -{ - unsigned int bit = irq - SE7722_FPGA_IRQ_BASE; - ctrl_outw(ctrl_inw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK); -} - -static struct irq_chip se7722_irq_chip __read_mostly = { - .name = "SE7722-FPGA", - .mask = disable_se7722_irq, - .unmask = enable_se7722_irq, - .mask_ack = disable_se7722_irq, -}; - -static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc) -{ - unsigned short intv = ctrl_inw(IRQ01_STS); - struct irq_desc *ext_desc; - unsigned int ext_irq = SE7722_FPGA_IRQ_BASE; - - intv &= (1 << SE7722_FPGA_IRQ_NR) - 1; - - while (intv) { - if (intv & 1) { - ext_desc = irq_desc + ext_irq; - handle_level_irq(ext_irq, ext_desc); - } - intv >>= 1; - ext_irq++; - } -} - -/* - * Initialize IRQ setting - */ -void __init init_se7722_IRQ(void) -{ - int i; - - ctrl_outw(0, IRQ01_MASK); /* disable all irqs */ - ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ - - for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) - set_irq_chip_and_handler_name(SE7722_FPGA_IRQ_BASE + i, - &se7722_irq_chip, - handle_level_irq, "level"); - - set_irq_chained_handler(IRQ0_IRQ, se7722_irq_demux); - set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); - - set_irq_chained_handler(IRQ1_IRQ, se7722_irq_demux); - set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); -} diff --git a/arch/sh/boards/se/7722/setup.c b/arch/sh/boards/se/7722/setup.c deleted file mode 100644 index b1a3d9d0172..00000000000 --- a/arch/sh/boards/se/7722/setup.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * linux/arch/sh/boards/se/7722/setup.c - * - * Copyright (C) 2007 Nobuhiro Iwamatsu - * - * Hitachi UL SolutionEngine 7722 Support. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/ata_platform.h> -#include <asm/machvec.h> -#include <asm/se7722.h> -#include <asm/io.h> -#include <asm/heartbeat.h> - -/* Heartbeat */ -static struct heartbeat_data heartbeat_data = { - .regsize = 16, -}; - -static struct resource heartbeat_resources[] = { - [0] = { - .start = PA_LED, - .end = PA_LED, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device heartbeat_device = { - .name = "heartbeat", - .id = -1, - .dev = { - .platform_data = &heartbeat_data, - }, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, -}; - -/* SMC91x */ -static struct resource smc91x_eth_resources[] = { - [0] = { - .name = "smc91x-regs" , - .start = PA_LAN + 0x300, - .end = PA_LAN + 0x300 + 0x10 , - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SMC_IRQ, - .end = SMC_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91x_eth_device = { - .name = "smc91x", - .id = 0, - .dev = { - .dma_mask = NULL, /* don't use dma */ - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(smc91x_eth_resources), - .resource = smc91x_eth_resources, -}; - -static struct resource cf_ide_resources[] = { - [0] = { - .start = PA_MRSHPC_IO + 0x1f0, - .end = PA_MRSHPC_IO + 0x1f0 + 8 , - .flags = IORESOURCE_IO, - }, - [1] = { - .start = PA_MRSHPC_IO + 0x1f0 + 0x206, - .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8, - .flags = IORESOURCE_IO, - }, - [2] = { - .start = MRSHPC_IRQ0, - .end = MRSHPC_IRQ0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device cf_ide_device = { - .name = "pata_platform", - .id = -1, - .num_resources = ARRAY_SIZE(cf_ide_resources), - .resource = cf_ide_resources, -}; - -static struct platform_device *se7722_devices[] __initdata = { - &heartbeat_device, - &smc91x_eth_device, - &cf_ide_device, -}; - -static int __init se7722_devices_setup(void) -{ - return platform_add_devices(se7722_devices, - ARRAY_SIZE(se7722_devices)); -} -device_initcall(se7722_devices_setup); - -static void __init se7722_setup(char **cmdline_p) -{ - ctrl_outw(0x010D, FPGA_OUT); /* FPGA */ - - ctrl_outl(0x00051001, MSTPCR0); - ctrl_outl(0x00000000, MSTPCR1); - /* KEYSC, VOU, BEU, CEU, VEU, VPU, LCDC, USB */ - ctrl_outl(0xffffb7c0, MSTPCR2); - - ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */ - ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */ - - /* LCDC I/O */ - ctrl_outw(0x0020, PORT_PSELD); - - /* SIOF1*/ - ctrl_outw(0x0003, PORT_PSELB); - ctrl_outw(0xe000, PORT_PSELC); - ctrl_outw(0x0000, PORT_PKCR); - - /* LCDC */ - ctrl_outw(0x4020, PORT_PHCR); - ctrl_outw(0x0000, PORT_PLCR); - ctrl_outw(0x0000, PORT_PMCR); - ctrl_outw(0x0002, PORT_PRCR); - ctrl_outw(0x0000, PORT_PXCR); /* LCDC,CS6A */ - - /* KEYSC */ - ctrl_outw(0x0A10, PORT_PSELA); /* BS,SHHID2 */ - ctrl_outw(0x0000, PORT_PYCR); - ctrl_outw(0x0000, PORT_PZCR); -} - -/* - * The Machine Vector - */ -static struct sh_machine_vector mv_se7722 __initmv = { - .mv_name = "Solution Engine 7722" , - .mv_setup = se7722_setup , - .mv_nr_irqs = SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_NR, - .mv_init_irq = init_se7722_IRQ, -}; diff --git a/arch/sh/boards/se/7751/io.c b/arch/sh/boards/se/7751/io.c deleted file mode 100644 index e8d846cec89..00000000000 --- a/arch/sh/boards/se/7751/io.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) 2001 Ian da Silva, Jeremy Siegel - * Based largely on io_se.c. - * - * I/O routine for Hitachi 7751 SolutionEngine. - * - * Initial version only to support LAN access; some - * placeholder code from io_se.c left in with the - * expectation of later SuperIO and PCMCIA access. - */ -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/pci.h> -#include <asm/io.h> -#include <asm/se7751.h> -#include <asm/addrspace.h> - -static inline volatile u16 *port2adr(unsigned int port) -{ - if (port >= 0x2000) - return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); - maybebadio((unsigned long)port); - return (volatile __u16*)port; -} - -/* - * General outline: remap really low stuff [eventually] to SuperIO, - * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO) - * is mapped through the PCI IO window. Stuff with high bits (PXSEG) - * should be way beyond the window, and is used w/o translation for - * compatibility. - */ -unsigned char sh7751se_inb(unsigned long port) -{ - if (PXSEG(port)) - return *(volatile unsigned char *)port; - else if (is_pci_ioaddr(port)) - return *(volatile unsigned char *)pci_ioaddr(port); - else - return (*port2adr(port)) & 0xff; -} - -unsigned char sh7751se_inb_p(unsigned long port) -{ - unsigned char v; - - if (PXSEG(port)) - v = *(volatile unsigned char *)port; - else if (is_pci_ioaddr(port)) - v = *(volatile unsigned char *)pci_ioaddr(port); - else - v = (*port2adr(port)) & 0xff; - ctrl_delay(); - return v; -} - -unsigned short sh7751se_inw(unsigned long port) -{ - if (PXSEG(port)) - return *(volatile unsigned short *)port; - else if (is_pci_ioaddr(port)) - return *(volatile unsigned short *)pci_ioaddr(port); - else if (port >= 0x2000) - return *port2adr(port); - else - maybebadio(port); - return 0; -} - -unsigned int sh7751se_inl(unsigned long port) -{ - if (PXSEG(port)) - return *(volatile unsigned long *)port; - else if (is_pci_ioaddr(port)) - return *(volatile unsigned int *)pci_ioaddr(port); - else if (port >= 0x2000) - return *port2adr(port); - else - maybebadio(port); - return 0; -} - -void sh7751se_outb(unsigned char value, unsigned long port) -{ - - if (PXSEG(port)) - *(volatile unsigned char *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned char*)pci_ioaddr(port)) = value; - else - *(port2adr(port)) = value; -} - -void sh7751se_outb_p(unsigned char value, unsigned long port) -{ - if (PXSEG(port)) - *(volatile unsigned char *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned char*)pci_ioaddr(port)) = value; - else - *(port2adr(port)) = value; - ctrl_delay(); -} - -void sh7751se_outw(unsigned short value, unsigned long port) -{ - if (PXSEG(port)) - *(volatile unsigned short *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned short *)pci_ioaddr(port)) = value; - else if (port >= 0x2000) - *port2adr(port) = value; - else - maybebadio(port); -} - -void sh7751se_outl(unsigned int value, unsigned long port) -{ - if (PXSEG(port)) - *(volatile unsigned long *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned long*)pci_ioaddr(port)) = value; - else - maybebadio(port); -} - -void sh7751se_insl(unsigned long port, void *addr, unsigned long count) -{ - maybebadio(port); -} - -void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count) -{ - maybebadio(port); -} diff --git a/arch/sh/boards/se/7751/pci.c b/arch/sh/boards/se/7751/pci.c deleted file mode 100644 index 203b2923fe7..00000000000 --- a/arch/sh/boards/se/7751/pci.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * linux/arch/sh/boards/se/7751/pci.c - * - * Author: Ian DaSilva (idasilva@mvista.com) - * - * Highly leveraged from pci-bigsur.c, written by Dustin McIntire. - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * PCI initialization for the Hitachi SH7751 Solution Engine board (MS7751SE01) - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/pci.h> - -#include <asm/io.h> -#include "../../../drivers/pci/pci-sh7751.h" - -#define PCIMCR_MRSET_OFF 0xBFFFFFFF -#define PCIMCR_RFSH_OFF 0xFFFFFFFB - -/* - * Only long word accesses of the PCIC's internal local registers and the - * configuration registers from the CPU is supported. - */ -#define PCIC_WRITE(x,v) writel((v), PCI_REG(x)) -#define PCIC_READ(x) readl(PCI_REG(x)) - -/* - * Description: This function sets up and initializes the pcic, sets - * up the BARS, maps the DRAM into the address space etc, etc. - */ -int __init pcibios_init_platform(void) -{ - unsigned long bcr1, wcr1, wcr2, wcr3, mcr; - unsigned short bcr2; - - /* - * Initialize the slave bus controller on the pcic. The values used - * here should not be hardcoded, but they should be taken from the bsc - * on the processor, to make this function as generic as possible. - * (i.e. Another sbc may usr different SDRAM timing settings -- in order - * for the pcic to work, its settings need to be exactly the same.) - */ - bcr1 = (*(volatile unsigned long*)(SH7751_BCR1)); - bcr2 = (*(volatile unsigned short*)(SH7751_BCR2)); - wcr1 = (*(volatile unsigned long*)(SH7751_WCR1)); - wcr2 = (*(volatile unsigned long*)(SH7751_WCR2)); - wcr3 = (*(volatile unsigned long*)(SH7751_WCR3)); - mcr = (*(volatile unsigned long*)(SH7751_MCR)); - - bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ - (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1; - - bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ - PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */ - PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */ - PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */ - PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */ - PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */ - mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; - PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */ - - - /* Enable all interrupts, so we know what to fix */ - PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); - PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); - - /* Set up standard PCI config registers */ - PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */ - PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ - PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */ - PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */ - PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */ - PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */ - PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */ - PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */ - PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */ - PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */ - - /* Now turn it on... */ - PCIC_WRITE(SH7751_PCICR, 0xa5000001); - - /* - * Set PCIMBR and PCIIOBR here, assuming a single window - * (16M MEM, 256K IO) is enough. If a larger space is - * needed, the readx/writex and inx/outx functions will - * have to do more (e.g. setting registers for each call). - */ - - /* - * Set the MBR so PCI address is one-to-one with window, - * meaning all calls go straight through... use BUG_ON to - * catch erroneous assumption. - */ - BUG_ON(PCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE); - - PCIC_WRITE(SH7751_PCIMBR, PCIBIOS_MIN_MEM); - - /* Set IOBR for window containing area specified in pci.h */ - PCIC_WRITE(SH7751_PCIIOBR, (PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK)); - - /* All done, may as well say so... */ - printk("SH7751 PCI: Finished initialization of the PCI controller\n"); - - return 1; -} - -int __init pcibios_map_platform_irq(u8 slot, u8 pin) -{ - switch (slot) { - case 0: return 13; - case 1: return 13; /* AMD Ethernet controller */ - case 2: return -1; - case 3: return -1; - case 4: return -1; - default: - printk("PCI: Bad IRQ mapping request for slot %d\n", slot); - return -1; - } -} - -static struct resource sh7751_io_resource = { - .name = "SH7751 IO", - .start = SH7751_PCI_IO_BASE, - .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, - .flags = IORESOURCE_IO -}; - -static struct resource sh7751_mem_resource = { - .name = "SH7751 mem", - .start = SH7751_PCI_MEMORY_BASE, - .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops sh7751_pci_ops; - -struct pci_channel board_pci_channels[] = { - { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, - { NULL, NULL, NULL, 0, 0 }, -}; - diff --git a/arch/sh/boards/se/7780/irq.c b/arch/sh/boards/se/7780/irq.c deleted file mode 100644 index 6bd70da6bb4..00000000000 --- a/arch/sh/boards/se/7780/irq.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * linux/arch/sh/boards/se/7780/irq.c - * - * Copyright (C) 2006,2007 Nobuhiro Iwamatsu - * - * Hitachi UL SolutionEngine 7780 Support. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <asm/irq.h> -#include <asm/io.h> -#include <asm/se7780.h> - -/* - * Initialize IRQ setting - */ -void __init init_se7780_IRQ(void) -{ - /* enable all interrupt at FPGA */ - ctrl_outw(0, FPGA_INTMSK1); - /* mask SM501 interrupt */ - ctrl_outw((ctrl_inw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1); - /* enable all interrupt at FPGA */ - ctrl_outw(0, FPGA_INTMSK2); - - /* set FPGA INTSEL register */ - /* FPGA + 0x06 */ - ctrl_outw( ((IRQPIN_SM501 << IRQPOS_SM501) | - (IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1); - - /* FPGA + 0x08 */ - ctrl_outw(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) | - (IRQPIN_EXTINT3 << IRQPOS_EXTINT3) | - (IRQPIN_EXTINT2 << IRQPOS_EXTINT2) | - (IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2); - - /* FPGA + 0x0A */ - ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); - - plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ -} diff --git a/arch/sh/boards/sh03/setup.c b/arch/sh/boards/sh03/setup.c deleted file mode 100644 index 934ac4f1c48..00000000000 --- a/arch/sh/boards/sh03/setup.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * linux/arch/sh/boards/sh03/setup.c - * - * Copyright (C) 2004 Interface Co.,Ltd. Saito.K - * - */ - -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/pci.h> -#include <linux/platform_device.h> -#include <asm/io.h> -#include <asm/rtc.h> -#include <asm/sh03/io.h> -#include <asm/sh03/sh03.h> -#include <asm/addrspace.h> - -static void __init init_sh03_IRQ(void) -{ - plat_irq_setup_pins(IRQ_MODE_IRQ); -} - -extern void *cf_io_base; - -static void __iomem *sh03_ioport_map(unsigned long port, unsigned int size) -{ - if (PXSEG(port)) - return (void __iomem *)port; - /* CompactFlash (IDE) */ - if (((port >= 0x1f0) && (port <= 0x1f7)) || (port == 0x3f6)) - return (void __iomem *)((unsigned long)cf_io_base + port); - - return (void __iomem *)(port + PCI_IO_BASE); -} - -/* arch/sh/boards/sh03/rtc.c */ -void sh03_time_init(void); - -static void __init sh03_setup(char **cmdline_p) -{ - board_time_init = sh03_time_init; -} - -static struct resource heartbeat_resources[] = { - [0] = { - .start = 0xa0800000, - .end = 0xa0800000, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device heartbeat_device = { - .name = "heartbeat", - .id = -1, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, -}; - -static struct platform_device *sh03_devices[] __initdata = { - &heartbeat_device, -}; - -static int __init sh03_devices_setup(void) -{ - return platform_add_devices(sh03_devices, ARRAY_SIZE(sh03_devices)); -} -__initcall(sh03_devices_setup); - -static struct sh_machine_vector mv_sh03 __initmv = { - .mv_name = "Interface (CTP/PCI-SH03)", - .mv_setup = sh03_setup, - .mv_nr_irqs = 48, - .mv_ioport_map = sh03_ioport_map, - .mv_init_irq = init_sh03_IRQ, -}; diff --git a/arch/sh/boards/shmin/Makefile b/arch/sh/boards/shmin/Makefile deleted file mode 100644 index 3190cc72430..00000000000 --- a/arch/sh/boards/shmin/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the SHMIN board. -# - -obj-y := setup.o diff --git a/arch/sh/boards/snapgear/Makefile b/arch/sh/boards/snapgear/Makefile deleted file mode 100644 index d2d2f4b6a50..00000000000 --- a/arch/sh/boards/snapgear/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the SnapGear specific parts of the kernel -# - -obj-y := setup.o io.o diff --git a/arch/sh/boards/snapgear/io.c b/arch/sh/boards/snapgear/io.c deleted file mode 100644 index 0f482426455..00000000000 --- a/arch/sh/boards/snapgear/io.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) 2002 David McCullough <davidm@snapgear.com> - * Copyright (C) 2001 Ian da Silva, Jeremy Siegel - * Based largely on io_se.c. - * - * I/O routine for Hitachi 7751 SolutionEngine. - * - * Initial version only to support LAN access; some - * placeholder code from io_se.c left in with the - * expectation of later SuperIO and PCMCIA access. - */ -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/pci.h> -#include <asm/io.h> -#include <asm/addrspace.h> - -#ifdef CONFIG_SH_SECUREEDGE5410 -unsigned short secureedge5410_ioport; -#endif - -static inline volatile __u16 *port2adr(unsigned int port) -{ - maybebadio((unsigned long)port); - return (volatile __u16*)port; -} - -/* - * General outline: remap really low stuff [eventually] to SuperIO, - * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO) - * is mapped through the PCI IO window. Stuff with high bits (PXSEG) - * should be way beyond the window, and is used w/o translation for - * compatibility. - */ -unsigned char snapgear_inb(unsigned long port) -{ - if (PXSEG(port)) - return *(volatile unsigned char *)port; - else if (is_pci_ioaddr(port)) - return *(volatile unsigned char *)pci_ioaddr(port); - else - return (*port2adr(port)) & 0xff; -} - -unsigned char snapgear_inb_p(unsigned long port) -{ - unsigned char v; - - if (PXSEG(port)) - v = *(volatile unsigned char *)port; - else if (is_pci_ioaddr(port)) - v = *(volatile unsigned char *)pci_ioaddr(port); - else - v = (*port2adr(port))&0xff; - ctrl_delay(); - return v; -} - -unsigned short snapgear_inw(unsigned long port) -{ - if (PXSEG(port)) - return *(volatile unsigned short *)port; - else if (is_pci_ioaddr(port)) - return *(volatile unsigned short *)pci_ioaddr(port); - else if (port >= 0x2000) - return *port2adr(port); - else - maybebadio(port); - return 0; -} - -unsigned int snapgear_inl(unsigned long port) -{ - if (PXSEG(port)) - return *(volatile unsigned long *)port; - else if (is_pci_ioaddr(port)) - return *(volatile unsigned int *)pci_ioaddr(port); - else if (port >= 0x2000) - return *port2adr(port); - else - maybebadio(port); - return 0; -} - -void snapgear_outb(unsigned char value, unsigned long port) -{ - - if (PXSEG(port)) - *(volatile unsigned char *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned char*)pci_ioaddr(port)) = value; - else - *(port2adr(port)) = value; -} - -void snapgear_outb_p(unsigned char value, unsigned long port) -{ - if (PXSEG(port)) - *(volatile unsigned char *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned char*)pci_ioaddr(port)) = value; - else - *(port2adr(port)) = value; - ctrl_delay(); -} - -void snapgear_outw(unsigned short value, unsigned long port) -{ - if (PXSEG(port)) - *(volatile unsigned short *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned short *)pci_ioaddr(port)) = value; - else if (port >= 0x2000) - *port2adr(port) = value; - else - maybebadio(port); -} - -void snapgear_outl(unsigned int value, unsigned long port) -{ - if (PXSEG(port)) - *(volatile unsigned long *)port = value; - else if (is_pci_ioaddr(port)) - *((unsigned long*)pci_ioaddr(port)) = value; - else - maybebadio(port); -} - -void snapgear_insl(unsigned long port, void *addr, unsigned long count) -{ - maybebadio(port); -} - -void snapgear_outsl(unsigned long port, const void *addr, unsigned long count) -{ - maybebadio(port); -} diff --git a/arch/sh/boards/superh/microdev/io.c b/arch/sh/boards/superh/microdev/io.c deleted file mode 100644 index 9f8a540f7e1..00000000000 --- a/arch/sh/boards/superh/microdev/io.c +++ /dev/null @@ -1,367 +0,0 @@ -/* - * linux/arch/sh/boards/superh/microdev/io.c - * - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) - * Copyright (C) 2003, 2004 SuperH, Inc. - * Copyright (C) 2004 Paul Mundt - * - * SuperH SH4-202 MicroDev board support. - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - */ - -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/wait.h> -#include <asm/io.h> -#include <asm/microdev.h> - - /* - * we need to have a 'safe' address to re-direct all I/O requests - * that we do not explicitly wish to handle. This safe address - * must have the following properies: - * - * * writes are ignored (no exception) - * * reads are benign (no side-effects) - * * accesses of width 1, 2 and 4-bytes are all valid. - * - * The Processor Version Register (PVR) has these properties. - */ -#define PVR 0xff000030 /* Processor Version Register */ - - -#define IO_IDE2_BASE 0x170ul /* I/O base for SMSC FDC37C93xAPM IDE #2 */ -#define IO_IDE1_BASE 0x1f0ul /* I/O base for SMSC FDC37C93xAPM IDE #1 */ -#define IO_ISP1161_BASE 0x290ul /* I/O port for Philips ISP1161x USB chip */ -#define IO_SERIAL2_BASE 0x2f8ul /* I/O base for SMSC FDC37C93xAPM Serial #2 */ -#define IO_LAN91C111_BASE 0x300ul /* I/O base for SMSC LAN91C111 Ethernet chip */ -#define IO_IDE2_MISC 0x376ul /* I/O misc for SMSC FDC37C93xAPM IDE #2 */ -#define IO_SUPERIO_BASE 0x3f0ul /* I/O base for SMSC FDC37C93xAPM SuperIO chip */ -#define IO_IDE1_MISC 0x3f6ul /* I/O misc for SMSC FDC37C93xAPM IDE #1 */ -#define IO_SERIAL1_BASE 0x3f8ul /* I/O base for SMSC FDC37C93xAPM Serial #1 */ - -#define IO_ISP1161_EXTENT 0x04ul /* I/O extent for Philips ISP1161x USB chip */ -#define IO_LAN91C111_EXTENT 0x10ul /* I/O extent for SMSC LAN91C111 Ethernet chip */ -#define IO_SUPERIO_EXTENT 0x02ul /* I/O extent for SMSC FDC37C93xAPM SuperIO chip */ -#define IO_IDE_EXTENT 0x08ul /* I/O extent for IDE Task Register set */ -#define IO_SERIAL_EXTENT 0x10ul - -#define IO_LAN91C111_PHYS 0xa7500000ul /* Physical address of SMSC LAN91C111 Ethernet chip */ -#define IO_ISP1161_PHYS 0xa7700000ul /* Physical address of Philips ISP1161x USB chip */ -#define IO_SUPERIO_PHYS 0xa7800000ul /* Physical address of SMSC FDC37C93xAPM SuperIO chip */ - -/* - * map I/O ports to memory-mapped addresses - */ -static unsigned long microdev_isa_port2addr(unsigned long offset) -{ - unsigned long result; - - if ((offset >= IO_LAN91C111_BASE) && - (offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) { - /* - * SMSC LAN91C111 Ethernet chip - */ - result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE; - } else if ((offset >= IO_SUPERIO_BASE) && - (offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) { - /* - * SMSC FDC37C93xAPM SuperIO chip - * - * Configuration Registers - */ - result = IO_SUPERIO_PHYS + (offset << 1); -#if 0 - } else if (offset == KBD_DATA_REG || offset == KBD_CNTL_REG || - offset == KBD_STATUS_REG) { - /* - * SMSC FDC37C93xAPM SuperIO chip - * - * PS/2 Keyboard + Mouse (ports 0x60 and 0x64). - */ - result = IO_SUPERIO_PHYS + (offset << 1); -#endif - } else if (((offset >= IO_IDE1_BASE) && - (offset < IO_IDE1_BASE + IO_IDE_EXTENT)) || - (offset == IO_IDE1_MISC)) { - /* - * SMSC FDC37C93xAPM SuperIO chip - * - * IDE #1 - */ - result = IO_SUPERIO_PHYS + (offset << 1); - } else if (((offset >= IO_IDE2_BASE) && - (offset < IO_IDE2_BASE + IO_IDE_EXTENT)) || - (offset == IO_IDE2_MISC)) { - /* - * SMSC FDC37C93xAPM SuperIO chip - * - * IDE #2 - */ - result = IO_SUPERIO_PHYS + (offset << 1); - } else if ((offset >= IO_SERIAL1_BASE) && - (offset < IO_SERIAL1_BASE + IO_SERIAL_EXTENT)) { - /* - * SMSC FDC37C93xAPM SuperIO chip - * - * Serial #1 - */ - result = IO_SUPERIO_PHYS + (offset << 1); - } else if ((offset >= IO_SERIAL2_BASE) && - (offset < IO_SERIAL2_BASE + IO_SERIAL_EXTENT)) { - /* - * SMSC FDC37C93xAPM SuperIO chip - * - * Serial #2 - */ - result = IO_SUPERIO_PHYS + (offset << 1); - } else if ((offset >= IO_ISP1161_BASE) && - (offset < IO_ISP1161_BASE + IO_ISP1161_EXTENT)) { - /* - * Philips USB ISP1161x chip - */ - result = IO_ISP1161_PHYS + offset - IO_ISP1161_BASE; - } else { - /* - * safe default. - */ - printk("Warning: unexpected port in %s( offset = 0x%lx )\n", - __func__, offset); - result = PVR; - } - - return result; -} - -#define PORT2ADDR(x) (microdev_isa_port2addr(x)) - -static inline void delay(void) -{ -#if defined(CONFIG_PCI) - /* System board present, just make a dummy SRAM access. (CS0 will be - mapped to PCI memory, probably good to avoid it.) */ - ctrl_inw(0xa6800000); -#else - /* CS0 will be mapped to flash, ROM etc so safe to access it. */ - ctrl_inw(0xa0000000); -#endif -} - -unsigned char microdev_inb(unsigned long port) -{ -#ifdef CONFIG_PCI - if (port >= PCIBIOS_MIN_IO) - return microdev_pci_inb(port); -#endif - return *(volatile unsigned char*)PORT2ADDR(port); -} - -unsigned short microdev_inw(unsigned long port) -{ -#ifdef CONFIG_PCI - if (port >= PCIBIOS_MIN_IO) - return microdev_pci_inw(port); -#endif - return *(volatile unsigned short*)PORT2ADDR(port); -} - -unsigned int microdev_inl(unsigned long port) -{ -#ifdef CONFIG_PCI - if (port >= PCIBIOS_MIN_IO) - return microdev_pci_inl(port); -#endif - return *(volatile unsigned int*)PORT2ADDR(port); -} - -void microdev_outw(unsigned short b, unsigned long port) -{ -#ifdef CONFIG_PCI - if (port >= PCIBIOS_MIN_IO) { - microdev_pci_outw(b, port); - return; - } -#endif - *(volatile unsigned short*)PORT2ADDR(port) = b; -} - -void microdev_outb(unsigned char b, unsigned long port) -{ -#ifdef CONFIG_PCI - if (port >= PCIBIOS_MIN_IO) { - microdev_pci_outb(b, port); - return; - } -#endif - - /* - * There is a board feature with the current SH4-202 MicroDev in - * that the 2 byte enables (nBE0 and nBE1) are tied together (and - * to the Chip Select Line (Ethernet_CS)). Due to this connectivity, - * it is not possible to safely perform 8-bit writes to the - * Ethernet registers, as 16-bits will be consumed from the Data - * lines (corrupting the other byte). Hence, this function is - * written to implement 16-bit read/modify/write for all byte-wide - * accesses. - * - * Note: there is no problem with byte READS (even or odd). - * - * Sean McGoogan - 16th June 2003. - */ - if ((port >= IO_LAN91C111_BASE) && - (port < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) { - /* - * Then are trying to perform a byte-write to the - * LAN91C111. This needs special care. - */ - if (port % 2 == 1) { /* is the port odd ? */ - /* unset bit-0, i.e. make even */ - const unsigned long evenPort = port-1; - unsigned short word; - - /* - * do a 16-bit read/write to write to 'port', - * preserving even byte. - * - * Even addresses are bits 0-7 - * Odd addresses are bits 8-15 - */ - word = microdev_inw(evenPort); - word = (word & 0xffu) | (b << 8); - microdev_outw(word, evenPort); - } else { - /* else, we are trying to do an even byte write */ - unsigned short word; - - /* - * do a 16-bit read/write to write to 'port', - * preserving odd byte. - * - * Even addresses are bits 0-7 - * Odd addresses are bits 8-15 - */ - word = microdev_inw(port); - word = (word & 0xff00u) | (b); - microdev_outw(word, port); - } - } else { - *(volatile unsigned char*)PORT2ADDR(port) = b; - } -} - -void microdev_outl(unsigned int b, unsigned long port) -{ -#ifdef CONFIG_PCI - if (port >= PCIBIOS_MIN_IO) { - microdev_pci_outl(b, port); - return; - } -#endif - *(volatile unsigned int*)PORT2ADDR(port) = b; -} - -unsigned char microdev_inb_p(unsigned long port) -{ - unsigned char v = microdev_inb(port); - delay(); - return v; -} - -unsigned short microdev_inw_p(unsigned long port) -{ - unsigned short v = microdev_inw(port); - delay(); - return v; -} - -unsigned int microdev_inl_p(unsigned long port) -{ - unsigned int v = microdev_inl(port); - delay(); - return v; -} - -void microdev_outb_p(unsigned char b, unsigned long port) -{ - microdev_outb(b, port); - delay(); -} - -void microdev_outw_p(unsigned short b, unsigned long port) -{ - microdev_outw(b, port); - delay(); -} - -void microdev_outl_p(unsigned int b, unsigned long port) -{ - microdev_outl(b, port); - delay(); -} - -void microdev_insb(unsigned long port, void *buffer, unsigned long count) -{ - volatile unsigned char *port_addr; - unsigned char *buf = buffer; - - port_addr = (volatile unsigned char *)PORT2ADDR(port); - - while (count--) - *buf++ = *port_addr; -} - -void microdev_insw(unsigned long port, void *buffer, unsigned long count) -{ - volatile unsigned short *port_addr; - unsigned short *buf = buffer; - - port_addr = (volatile unsigned short *)PORT2ADDR(port); - - while (count--) - *buf++ = *port_addr; -} - -void microdev_insl(unsigned long port, void *buffer, unsigned long count) -{ - volatile unsigned long *port_addr; - unsigned int *buf = buffer; - - port_addr = (volatile unsigned long *)PORT2ADDR(port); - - while (count--) - *buf++ = *port_addr; -} - -void microdev_outsb(unsigned long port, const void *buffer, unsigned long count) -{ - volatile unsigned char *port_addr; - const unsigned char *buf = buffer; - - port_addr = (volatile unsigned char *)PORT2ADDR(port); - - while (count--) - *port_addr = *buf++; -} - -void microdev_outsw(unsigned long port, const void *buffer, unsigned long count) -{ - volatile unsigned short *port_addr; - const unsigned short *buf = buffer; - - port_addr = (volatile unsigned short *)PORT2ADDR(port); - - while (count--) - *port_addr = *buf++; -} - -void microdev_outsl(unsigned long port, const void *buffer, unsigned long count) -{ - volatile unsigned long *port_addr; - const unsigned int *buf = buffer; - - port_addr = (volatile unsigned long *)PORT2ADDR(port); - - while (count--) - *port_addr = *buf++; -} diff --git a/arch/sh/boards/superh/microdev/led.c b/arch/sh/boards/superh/microdev/led.c deleted file mode 100644 index 36e54b47a75..00000000000 --- a/arch/sh/boards/superh/microdev/led.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * linux/arch/sh/boards/superh/microdev/led.c - * - * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com> - * Copyright (C) 2003 Richard Curnow (Richard.Curnow@superh.com) - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - */ - -#include <asm/io.h> - -#define LED_REGISTER 0xa6104d20 - -static void mach_led_d9(int value) -{ - unsigned long reg; - reg = ctrl_inl(LED_REGISTER); - reg &= ~1; - reg |= (value & 1); - ctrl_outl(reg, LED_REGISTER); - return; -} - -static void mach_led_d10(int value) -{ - unsigned long reg; - reg = ctrl_inl(LED_REGISTER); - reg &= ~2; - reg |= ((value & 1) << 1); - ctrl_outl(reg, LED_REGISTER); - return; -} - - -#ifdef CONFIG_HEARTBEAT -#include <linux/sched.h> - -static unsigned char banner_table[] = { - 0x11, 0x01, 0x11, 0x01, 0x11, 0x03, - 0x11, 0x01, 0x11, 0x01, 0x13, 0x03, - 0x11, 0x01, 0x13, 0x01, 0x13, 0x01, 0x11, 0x03, - 0x11, 0x03, - 0x11, 0x01, 0x13, 0x01, 0x11, 0x03, - 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x07, - 0x13, 0x01, 0x13, 0x03, - 0x11, 0x01, 0x11, 0x03, - 0x13, 0x01, 0x11, 0x01, 0x13, 0x01, 0x11, 0x03, - 0x11, 0x01, 0x13, 0x01, 0x11, 0x03, - 0x13, 0x01, 0x13, 0x01, 0x13, 0x03, - 0x13, 0x01, 0x11, 0x01, 0x11, 0x03, - 0x11, 0x03, - 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x13, 0x07, - 0xff -}; - -static void banner(void) -{ - static int pos = 0; - static int count = 0; - - if (count) { - count--; - } else { - int val = banner_table[pos]; - if (val == 0xff) { - pos = 0; - val = banner_table[pos]; - } - pos++; - mach_led_d10((val >> 4) & 1); - count = 10 * (val & 0xf); - } -} - -/* From heartbeat_harp in the stboards directory */ -/* acts like an actual heart beat -- ie thump-thump-pause... */ -void microdev_heartbeat(void) -{ - static unsigned cnt = 0, period = 0, dist = 0; - - if (cnt == 0 || cnt == dist) - mach_led_d9(1); - else if (cnt == 7 || cnt == dist+7) - mach_led_d9(0); - - if (++cnt > period) { - cnt = 0; - /* The hyperbolic function below modifies the heartbeat period - * length in dependency of the current (5min) load. It goes - * through the points f(0)=126, f(1)=86, f(5)=51, - * f(inf)->30. */ - period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30; - dist = period / 4; - } - - banner(); -} - -#endif diff --git a/arch/sh/boards/superh/microdev/setup.c b/arch/sh/boards/superh/microdev/setup.c deleted file mode 100644 index fc8cd06d66c..00000000000 --- a/arch/sh/boards/superh/microdev/setup.c +++ /dev/null @@ -1,405 +0,0 @@ -/* - * arch/sh/boards/superh/microdev/setup.c - * - * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) - * Copyright (C) 2003, 2004 SuperH, Inc. - * Copyright (C) 2004, 2005 Paul Mundt - * - * SuperH SH4-202 MicroDev board support. - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - */ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/ioport.h> -#include <video/s1d13xxxfb.h> -#include <asm/microdev.h> -#include <asm/io.h> -#include <asm/machvec.h> - -extern void microdev_heartbeat(void); - - -/****************************************************************************/ - - - /* - * Setup for the SMSC FDC37C93xAPM - */ -#define SMSC_CONFIG_PORT_ADDR (0x3F0) -#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR -#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1) - -#define SMSC_ENTER_CONFIG_KEY 0x55 -#define SMSC_EXIT_CONFIG_KEY 0xaa - -#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */ -#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */ -#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */ -#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */ -#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */ -#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */ -#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */ -#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */ -#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */ -#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */ - -#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */ -#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */ -#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */ -#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */ -#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */ -#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */ -#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */ - -#define SMSC_READ_INDEXED(index) ({ \ - outb((index), SMSC_INDEX_PORT_ADDR); \ - inb(SMSC_DATA_PORT_ADDR); }) -#define SMSC_WRITE_INDEXED(val, index) ({ \ - outb((index), SMSC_INDEX_PORT_ADDR); \ - outb((val), SMSC_DATA_PORT_ADDR); }) - -#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */ -#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */ -#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */ -#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */ - -#define SERIAL1_PRIMARY_BASE 0x03f8 -#define SERIAL2_PRIMARY_BASE 0x02f8 - -#define MSB(x) ( (x) >> 8 ) -#define LSB(x) ( (x) & 0xff ) - - /* General-Purpose base address on CPU-board FPGA */ -#define MICRODEV_FPGA_GP_BASE 0xa6100000ul - - /* assume a Keyboard Controller is present */ -int microdev_kbd_controller_present = 1; - -static struct resource smc91x_resources[] = { - [0] = { - .start = 0x300, - .end = 0x300 + 0x0001000 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = MICRODEV_LINUX_IRQ_ETHERNET, - .end = MICRODEV_LINUX_IRQ_ETHERNET, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = -1, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -#ifdef CONFIG_FB_S1D13XXX -static struct s1d13xxxfb_regval s1d13806_initregs[] = { - { S1DREG_MISC, 0x00 }, - { S1DREG_COM_DISP_MODE, 0x00 }, - { S1DREG_GPIO_CNF0, 0x00 }, - { S1DREG_GPIO_CNF1, 0x00 }, - { S1DREG_GPIO_CTL0, 0x00 }, - { S1DREG_GPIO_CTL1, 0x00 }, - { S1DREG_CLK_CNF, 0x02 }, - { S1DREG_LCD_CLK_CNF, 0x01 }, - { S1DREG_CRT_CLK_CNF, 0x03 }, - { S1DREG_MPLUG_CLK_CNF, 0x03 }, - { S1DREG_CPU2MEM_WST_SEL, 0x02 }, - { S1DREG_SDRAM_REF_RATE, 0x03 }, - { S1DREG_SDRAM_TC0, 0x00 }, - { S1DREG_SDRAM_TC1, 0x01 }, - { S1DREG_MEM_CNF, 0x80 }, - { S1DREG_PANEL_TYPE, 0x25 }, - { S1DREG_MOD_RATE, 0x00 }, - { S1DREG_LCD_DISP_HWIDTH, 0x63 }, - { S1DREG_LCD_NDISP_HPER, 0x1e }, - { S1DREG_TFT_FPLINE_START, 0x06 }, - { S1DREG_TFT_FPLINE_PWIDTH, 0x03 }, - { S1DREG_LCD_DISP_VHEIGHT0, 0x57 }, - { S1DREG_LCD_DISP_VHEIGHT1, 0x02 }, - { S1DREG_LCD_NDISP_VPER, 0x00 }, - { S1DREG_TFT_FPFRAME_START, 0x0a }, - { S1DREG_TFT_FPFRAME_PWIDTH, 0x81 }, - { S1DREG_LCD_DISP_MODE, 0x03 }, - { S1DREG_LCD_MISC, 0x00 }, - { S1DREG_LCD_DISP_START0, 0x00 }, - { S1DREG_LCD_DISP_START1, 0x00 }, - { S1DREG_LCD_DISP_START2, 0x00 }, - { S1DREG_LCD_MEM_OFF0, 0x90 }, - { S1DREG_LCD_MEM_OFF1, 0x01 }, - { S1DREG_LCD_PIX_PAN, 0x00 }, - { S1DREG_LCD_DISP_FIFO_HTC, 0x00 }, - { S1DREG_LCD_DISP_FIFO_LTC, 0x00 }, - { S1DREG_CRT_DISP_HWIDTH, 0x63 }, - { S1DREG_CRT_NDISP_HPER, 0x1f }, - { S1DREG_CRT_HRTC_START, 0x04 }, - { S1DREG_CRT_HRTC_PWIDTH, 0x8f }, - { S1DREG_CRT_DISP_VHEIGHT0, 0x57 }, - { S1DREG_CRT_DISP_VHEIGHT1, 0x02 }, - { S1DREG_CRT_NDISP_VPER, 0x1b }, - { S1DREG_CRT_VRTC_START, 0x00 }, - { S1DREG_CRT_VRTC_PWIDTH, 0x83 }, - { S1DREG_TV_OUT_CTL, 0x10 }, - { S1DREG_CRT_DISP_MODE, 0x05 }, - { S1DREG_CRT_DISP_START0, 0x00 }, - { S1DREG_CRT_DISP_START1, 0x00 }, - { S1DREG_CRT_DISP_START2, 0x00 }, - { S1DREG_CRT_MEM_OFF0, 0x20 }, - { S1DREG_CRT_MEM_OFF1, 0x03 }, - { S1DREG_CRT_PIX_PAN, 0x00 }, - { S1DREG_CRT_DISP_FIFO_HTC, 0x00 }, - { S1DREG_CRT_DISP_FIFO_LTC, 0x00 }, - { S1DREG_LCD_CUR_CTL, 0x00 }, - { S1DREG_LCD_CUR_START, 0x01 }, - { S1DREG_LCD_CUR_XPOS0, 0x00 }, - { S1DREG_LCD_CUR_XPOS1, 0x00 }, - { S1DREG_LCD_CUR_YPOS0, 0x00 }, - { S1DREG_LCD_CUR_YPOS1, 0x00 }, - { S1DREG_LCD_CUR_BCTL0, 0x00 }, - { S1DREG_LCD_CUR_GCTL0, 0x00 }, - { S1DREG_LCD_CUR_RCTL0, 0x00 }, - { S1DREG_LCD_CUR_BCTL1, 0x1f }, - { S1DREG_LCD_CUR_GCTL1, 0x3f }, - { S1DREG_LCD_CUR_RCTL1, 0x1f }, - { S1DREG_LCD_CUR_FIFO_HTC, 0x00 }, - { S1DREG_CRT_CUR_CTL, 0x00 }, - { S1DREG_CRT_CUR_START, 0x01 }, - { S1DREG_CRT_CUR_XPOS0, 0x00 }, - { S1DREG_CRT_CUR_XPOS1, 0x00 }, - { S1DREG_CRT_CUR_YPOS0, 0x00 }, - { S1DREG_CRT_CUR_YPOS1, 0x00 }, - { S1DREG_CRT_CUR_BCTL0, 0x00 }, - { S1DREG_CRT_CUR_GCTL0, 0x00 }, - { S1DREG_CRT_CUR_RCTL0, 0x00 }, - { S1DREG_CRT_CUR_BCTL1, 0x1f }, - { S1DREG_CRT_CUR_GCTL1, 0x3f }, - { S1DREG_CRT_CUR_RCTL1, 0x1f }, - { S1DREG_CRT_CUR_FIFO_HTC, 0x00 }, - { S1DREG_BBLT_CTL0, 0x00 }, - { S1DREG_BBLT_CTL1, 0x00 }, - { S1DREG_BBLT_CC_EXP, 0x00 }, - { S1DREG_BBLT_OP, 0x00 }, - { S1DREG_BBLT_SRC_START0, 0x00 }, - { S1DREG_BBLT_SRC_START1, 0x00 }, - { S1DREG_BBLT_SRC_START2, 0x00 }, - { S1DREG_BBLT_DST_START0, 0x00 }, - { S1DREG_BBLT_DST_START1, 0x00 }, - { S1DREG_BBLT_DST_START2, 0x00 }, - { S1DREG_BBLT_MEM_OFF0, 0x00 }, - { S1DREG_BBLT_MEM_OFF1, 0x00 }, - { S1DREG_BBLT_WIDTH0, 0x00 }, - { S1DREG_BBLT_WIDTH1, 0x00 }, - { S1DREG_BBLT_HEIGHT0, 0x00 }, - { S1DREG_BBLT_HEIGHT1, 0x00 }, - { S1DREG_BBLT_BGC0, 0x00 }, - { S1DREG_BBLT_BGC1, 0x00 }, - { S1DREG_BBLT_FGC0, 0x00 }, - { S1DREG_BBLT_FGC1, 0x00 }, - { S1DREG_LKUP_MODE, 0x00 }, - { S1DREG_LKUP_ADDR, 0x00 }, - { S1DREG_PS_CNF, 0x10 }, - { S1DREG_PS_STATUS, 0x00 }, - { S1DREG_CPU2MEM_WDOGT, 0x00 }, - { S1DREG_COM_DISP_MODE, 0x02 }, -}; - -static struct s1d13xxxfb_pdata s1d13806_platform_data = { - .initregs = s1d13806_initregs, - .initregssize = ARRAY_SIZE(s1d13806_initregs), -}; - -static struct resource s1d13806_resources[] = { - [0] = { - .start = 0x07200000, - .end = 0x07200000 + 0x00200000 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0x07000000, - .end = 0x07000000 + 0x00200000 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device s1d13806_device = { - .name = "s1d13806fb", - .id = -1, - .num_resources = ARRAY_SIZE(s1d13806_resources), - .resource = s1d13806_resources, - - .dev = { - .platform_data = &s1d13806_platform_data, - }, -}; -#endif - -static struct platform_device *microdev_devices[] __initdata = { - &smc91x_device, -#ifdef CONFIG_FB_S1D13XXX - &s1d13806_device, -#endif -}; - -static int __init microdev_devices_setup(void) -{ - return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices)); -} - -/* - * Setup for the SMSC FDC37C93xAPM - */ -static int __init smsc_superio_setup(void) -{ - - unsigned char devid, devrev; - - /* Initially the chip is in run state */ - /* Put it into configuration state */ - outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); - - /* Read device ID info */ - devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX); - devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX); - if ( (devid==0x30) && (devrev==0x01) ) - { - printk("SMSC FDC37C93xAPM SuperIO device detected\n"); - } - else - { /* not the device identity we expected */ - printk("Not detected a SMSC FDC37C93xAPM SuperIO device (devid=0x%02x, rev=0x%02x)\n", - devid, devrev); - /* inform the keyboard driver that we have no keyboard controller */ - microdev_kbd_controller_present = 0; - /* little point in doing anything else in this functon */ - return 0; - } - - /* Select the keyboard device */ - SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* enable the interrupts */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX); - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX); - - /* Select the Serial #1 device */ - SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* program with port addresses */ - SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); - /* enable the interrupts */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX); - - /* Select the Serial #2 device */ - SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* program with port addresses */ - SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX); - /* enable the interrupts */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX); - - /* Select the IDE#1 device */ - SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* program with port addresses */ - SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX); - SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX); - /* select the interrupt */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX); - - /* Select the IDE#2 device */ - SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX); - /* enable it */ - SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); - /* program with port addresses */ - SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1); - SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0); - SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1); - /* select the interrupt */ - SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX); - - /* Select the configuration registers */ - SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX); - /* enable the appropriate GPIO pins for IDE functionality: - * bit[0] In/Out 1==input; 0==output - * bit[1] Polarity 1==invert; 0==no invert - * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable - * bit[3:4] Function Select 00==original; 01==Alternate Function #1 - */ - SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */ - SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */ - SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */ - SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */ - SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */ - - /* Exit the configuration state */ - outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); - - return 0; -} - -static void __init microdev_setup(char **cmdline_p) -{ - int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul); - const int fpgaRevision = *fpgaRevisionRegister; - int * const CacheControlRegister = (int*)CCR; - - device_initcall(microdev_devices_setup); - device_initcall(smsc_superio_setup); - - printk("SuperH %s board (FPGA rev: 0x%0x, CCR: 0x%0x)\n", - get_system_type(), fpgaRevision, *CacheControlRegister); -} - -/* - * The Machine Vector - */ -static struct sh_machine_vector mv_sh4202_microdev __initmv = { - .mv_name = "SH4-202 MicroDev", - .mv_setup = microdev_setup, - .mv_nr_irqs = 72, /* QQQ need to check this - use the MACRO */ - - .mv_inb = microdev_inb, - .mv_inw = microdev_inw, - .mv_inl = microdev_inl, - .mv_outb = microdev_outb, - .mv_outw = microdev_outw, - .mv_outl = microdev_outl, - - .mv_inb_p = microdev_inb_p, - .mv_inw_p = microdev_inw_p, - .mv_inl_p = microdev_inl_p, - .mv_outb_p = microdev_outb_p, - .mv_outw_p = microdev_outw_p, - .mv_outl_p = microdev_outl_p, - - .mv_insb = microdev_insb, - .mv_insw = microdev_insw, - .mv_insl = microdev_insl, - .mv_outsb = microdev_outsb, - .mv_outsw = microdev_outsw, - .mv_outsl = microdev_outsl, - - .mv_init_irq = init_microdev_irq, - -#ifdef CONFIG_HEARTBEAT - .mv_heartbeat = microdev_heartbeat, -#endif -}; diff --git a/arch/sh/boards/titan/Makefile b/arch/sh/boards/titan/Makefile deleted file mode 100644 index 08d75370006..00000000000 --- a/arch/sh/boards/titan/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Nimble Microsystems TITAN specific parts of the kernel -# - -obj-y := setup.o io.o diff --git a/arch/sh/boards/titan/io.c b/arch/sh/boards/titan/io.c deleted file mode 100644 index 4730c1dd697..00000000000 --- a/arch/sh/boards/titan/io.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * I/O routines for Titan - */ -#include <linux/pci.h> -#include <asm/machvec.h> -#include <asm/addrspace.h> -#include <asm/titan.h> -#include <asm/io.h> - -static inline unsigned int port2adr(unsigned int port) -{ - maybebadio((unsigned long)port); - return port; -} - -u8 titan_inb(unsigned long port) -{ - if (PXSEG(port)) - return ctrl_inb(port); - else if (is_pci_ioaddr(port)) - return ctrl_inb(pci_ioaddr(port)); - return ctrl_inw(port2adr(port)) & 0xff; -} - -u8 titan_inb_p(unsigned long port) -{ - u8 v; - - if (PXSEG(port)) - v = ctrl_inb(port); - else if (is_pci_ioaddr(port)) - v = ctrl_inb(pci_ioaddr(port)); - else - v = ctrl_inw(port2adr(port)) & 0xff; - ctrl_delay(); - return v; -} - -u16 titan_inw(unsigned long port) -{ - if (PXSEG(port)) - return ctrl_inw(port); - else if (is_pci_ioaddr(port)) - return ctrl_inw(pci_ioaddr(port)); - else if (port >= 0x2000) - return ctrl_inw(port2adr(port)); - else - maybebadio(port); - return 0; -} - -u32 titan_inl(unsigned long port) -{ - if (PXSEG(port)) - return ctrl_inl(port); - else if (is_pci_ioaddr(port)) - return ctrl_inl(pci_ioaddr(port)); - else if (port >= 0x2000) - return ctrl_inw(port2adr(port)); - else - maybebadio(port); - return 0; -} - -void titan_outb(u8 value, unsigned long port) -{ - if (PXSEG(port)) - ctrl_outb(value, port); - else if (is_pci_ioaddr(port)) - ctrl_outb(value, pci_ioaddr(port)); - else - ctrl_outw(value, port2adr(port)); -} - -void titan_outb_p(u8 value, unsigned long port) -{ - if (PXSEG(port)) - ctrl_outb(value, port); - else if (is_pci_ioaddr(port)) - ctrl_outb(value, pci_ioaddr(port)); - else - ctrl_outw(value, port2adr(port)); - ctrl_delay(); -} - -void titan_outw(u16 value, unsigned long port) -{ - if (PXSEG(port)) - ctrl_outw(value, port); - else if (is_pci_ioaddr(port)) - ctrl_outw(value, pci_ioaddr(port)); - else if (port >= 0x2000) - ctrl_outw(value, port2adr(port)); - else - maybebadio(port); -} - -void titan_outl(u32 value, unsigned long port) -{ - if (PXSEG(port)) - ctrl_outl(value, port); - else if (is_pci_ioaddr(port)) - ctrl_outl(value, pci_ioaddr(port)); - else - maybebadio(port); -} - -void titan_insl(unsigned long port, void *dst, unsigned long count) -{ - maybebadio(port); -} - -void titan_outsl(unsigned long port, const void *src, unsigned long count) -{ - maybebadio(port); -} - -void __iomem *titan_ioport_map(unsigned long port, unsigned int size) -{ - if (PXSEG(port) || is_pci_memaddr(port)) - return (void __iomem *)port; - else if (is_pci_ioaddr(port)) - return (void __iomem *)pci_ioaddr(port); - - return (void __iomem *)port2adr(port); -} |