diff options
Diffstat (limited to 'arch/powerpc/platforms/chrp')
| -rw-r--r-- | arch/powerpc/platforms/chrp/Kconfig | 15 | ||||
| -rw-r--r-- | arch/powerpc/platforms/chrp/Makefile | 3 | ||||
| -rw-r--r-- | arch/powerpc/platforms/chrp/chrp.h | 1 | ||||
| -rw-r--r-- | arch/powerpc/platforms/chrp/gg2.h | 61 | ||||
| -rw-r--r-- | arch/powerpc/platforms/chrp/nvram.c | 11 | ||||
| -rw-r--r-- | arch/powerpc/platforms/chrp/pci.c | 121 | ||||
| -rw-r--r-- | arch/powerpc/platforms/chrp/pegasos_eth.c | 82 | ||||
| -rw-r--r-- | arch/powerpc/platforms/chrp/setup.c | 212 | ||||
| -rw-r--r-- | arch/powerpc/platforms/chrp/smp.c | 45 | ||||
| -rw-r--r-- | arch/powerpc/platforms/chrp/time.c | 41 |
10 files changed, 331 insertions, 261 deletions
diff --git a/arch/powerpc/platforms/chrp/Kconfig b/arch/powerpc/platforms/chrp/Kconfig new file mode 100644 index 00000000000..d3cdab582c5 --- /dev/null +++ b/arch/powerpc/platforms/chrp/Kconfig @@ -0,0 +1,15 @@ +config PPC_CHRP + bool "Common Hardware Reference Platform (CHRP) based machines" + depends on 6xx + select HAVE_PCSPKR_PLATFORM + select MPIC + select PPC_I8259 + select PPC_INDIRECT_PCI + select PPC_RTAS + select PPC_RTAS_DAEMON + select RTAS_ERROR_LOGGING + select PPC_MPC106 + select PPC_UDBG_16550 + select PPC_NATIVE + select PCI + default y diff --git a/arch/powerpc/platforms/chrp/Makefile b/arch/powerpc/platforms/chrp/Makefile index 902feb1ac43..4b3bfadc70f 100644 --- a/arch/powerpc/platforms/chrp/Makefile +++ b/arch/powerpc/platforms/chrp/Makefile @@ -1,4 +1,3 @@ -obj-y += setup.o time.o pegasos_eth.o -obj-$(CONFIG_PCI) += pci.o +obj-y += setup.o time.o pegasos_eth.o pci.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_NVRAM) += nvram.o diff --git a/arch/powerpc/platforms/chrp/chrp.h b/arch/powerpc/platforms/chrp/chrp.h index 996c28744e9..63f0aee4c15 100644 --- a/arch/powerpc/platforms/chrp/chrp.h +++ b/arch/powerpc/platforms/chrp/chrp.h @@ -9,4 +9,3 @@ extern long chrp_time_init(void); extern void chrp_find_bridges(void); extern void chrp_event_scan(unsigned long); -extern void chrp_pcibios_fixup(void); diff --git a/arch/powerpc/platforms/chrp/gg2.h b/arch/powerpc/platforms/chrp/gg2.h new file mode 100644 index 00000000000..341ae55b99f --- /dev/null +++ b/arch/powerpc/platforms/chrp/gg2.h @@ -0,0 +1,61 @@ +/* + * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions + * + * Copyright (C) 1997 Geert Uytterhoeven + * + * This file is based on the following documentation: + * + * The VAS96011/12 Chipset, Data Book, Edition 1.0 + * VLSI Technology, Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef _ASMPPC_GG2_H +#define _ASMPPC_GG2_H + + /* + * Memory Map (CHRP mode) + */ + +#define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ +#define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ +#define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ +#define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ +#define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ + /* special PCI cycles */ +#define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ +#define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ + + + /* + * GG2 specific PCI Registers + */ + +extern void __iomem *gg2_pci_config_base; /* kernel virtual address */ + +#define GG2_PCI_BUSNO 0x40 /* Bus number */ +#define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ +#define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ +#define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ +#define GG2_PCI_ADDR_MAP 0x5c /* Address map */ +#define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ +#define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ +#define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ +#define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ +#define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ +#define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ +#define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ +#define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ +#define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ +#define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ +#define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ +#define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ +#define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ +#define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ +#define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ + /* Cleared when read */ + +#endif /* _ASMPPC_GG2_H */ diff --git a/arch/powerpc/platforms/chrp/nvram.c b/arch/powerpc/platforms/chrp/nvram.c index 0dd4a64757d..9ef8cc3378d 100644 --- a/arch/powerpc/platforms/chrp/nvram.c +++ b/arch/powerpc/platforms/chrp/nvram.c @@ -12,7 +12,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/slab.h> #include <linux/spinlock.h> #include <asm/uaccess.h> #include <asm/prom.h> @@ -67,18 +66,20 @@ static void chrp_nvram_write(int addr, unsigned char val) void __init chrp_nvram_init(void) { struct device_node *nvram; - const unsigned int *nbytes_p; + const __be32 *nbytes_p; unsigned int proplen; nvram = of_find_node_by_type(NULL, "nvram"); if (nvram == NULL) return; - nbytes_p = get_property(nvram, "#bytes", &proplen); - if (nbytes_p == NULL || proplen != sizeof(unsigned int)) + nbytes_p = of_get_property(nvram, "#bytes", &proplen); + if (nbytes_p == NULL || proplen != sizeof(unsigned int)) { + of_node_put(nvram); return; + } - nvram_size = *nbytes_p; + nvram_size = be32_to_cpup(nbytes_p); printk(KERN_INFO "CHRP nvram contains %u bytes\n", nvram_size); of_node_put(nvram); diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c index 0f4340506c7..1b87e198faa 100644 --- a/arch/powerpc/platforms/chrp/pci.c +++ b/arch/powerpc/platforms/chrp/pci.c @@ -7,14 +7,12 @@ #include <linux/delay.h> #include <linux/string.h> #include <linux/init.h> -#include <linux/ide.h> #include <asm/io.h> #include <asm/pgtable.h> #include <asm/irq.h> #include <asm/hydra.h> #include <asm/prom.h> -#include <asm/gg2.h> #include <asm/machdep.h> #include <asm/sections.h> #include <asm/pci-bridge.h> @@ -22,6 +20,7 @@ #include <asm/rtas.h> #include "chrp.h" +#include "gg2.h" /* LongTrail */ void __iomem *gg2_pci_config_base; @@ -35,7 +34,7 @@ int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off, int len, u32 *val) { volatile void __iomem *cfg_data; - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); if (bus->number > 7) return PCIBIOS_DEVICE_NOT_FOUND; @@ -62,7 +61,7 @@ int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off, int len, u32 val) { volatile void __iomem *cfg_data; - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); if (bus->number > 7) return PCIBIOS_DEVICE_NOT_FOUND; @@ -87,8 +86,8 @@ int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off, static struct pci_ops gg2_pci_ops = { - gg2_read_config, - gg2_write_config + .read = gg2_read_config, + .write = gg2_write_config, }; /* @@ -97,10 +96,10 @@ static struct pci_ops gg2_pci_ops = int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) | (((bus->number - hose->first_busno) & 0xff) << 16) - | (hose->index << 24); + | (hose->global_number << 24); int ret = -1; int rval; @@ -112,10 +111,10 @@ int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { - struct pci_controller *hose = bus->sysdata; + struct pci_controller *hose = pci_bus_to_host(bus); unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) | (((bus->number - hose->first_busno) & 0xff) << 16) - | (hose->index << 24); + | (hose->global_number << 24); int rval; rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL, @@ -125,8 +124,8 @@ int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, static struct pci_ops rtas_pci_ops = { - rtas_read_config, - rtas_write_config + .read = rtas_read_config, + .write = rtas_write_config, }; volatile struct Hydra __iomem *Hydra = NULL; @@ -137,10 +136,13 @@ hydra_init(void) struct device_node *np; struct resource r; - np = find_devices("mac-io"); - if (np == NULL || of_address_to_resource(np, 0, &r)) + np = of_find_node_by_name(NULL, "mac-io"); + if (np == NULL || of_address_to_resource(np, 0, &r)) { + of_node_put(np); return 0; - Hydra = ioremap(r.start, r.end-r.start); + } + of_node_put(np); + Hydra = ioremap(r.start, resource_size(&r)); printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start); printk("Hydra Feature_Control was %x", in_le32(&Hydra->Feature_Control)); @@ -156,15 +158,6 @@ hydra_init(void) return 1; } -void __init -chrp_pcibios_fixup(void) -{ - struct pci_dev *dev = NULL; - - for_each_pci_dev(dev) - pci_read_irq_line(dev); -} - #define PRG_CL_RESET_VALID 0x00010000 static void __init @@ -189,16 +182,15 @@ setup_python(struct pci_controller *hose, struct device_node *dev) } iounmap(reg); - setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); + setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0); } /* Marvell Discovery II based Pegasos 2 */ static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev) { - struct device_node *root = find_path_device("/"); + struct device_node *root = of_find_node_by_path("/"); struct device_node *rtas; - of_node_get(root); rtas = of_find_node_by_name (root, "rtas"); if (rtas) { hose->ops = &rtas_pci_ops; @@ -207,7 +199,8 @@ static void __init setup_peg2(struct pci_controller *hose, struct device_node *d printk ("RTAS supporting Pegasos OF not found, please upgrade" " your firmware\n"); } - pci_assign_all_buses = 1; + pci_add_flags(PCI_REASSIGN_ALL_BUS); + /* keep the reference to the root node */ } void __init @@ -220,14 +213,14 @@ chrp_find_bridges(void) const unsigned int *dma; const char *model, *machine; int is_longtrail = 0, is_mot = 0, is_pegasos = 0; - struct device_node *root = find_path_device("/"); + struct device_node *root = of_find_node_by_path("/"); struct resource r; /* * The PCI host bridge nodes on some machines don't have * properties to adequately identify them, so we have to * look at what sort of machine this is as well. */ - machine = get_property(root, "model", NULL); + machine = of_get_property(root, "model", NULL); if (machine != NULL) { is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0; is_mot = strncmp(machine, "MOT", 3) == 0; @@ -246,7 +239,7 @@ chrp_find_bridges(void) dev->full_name); continue; } - bus_range = get_property(dev, "bus-range", &len); + bus_range = of_get_property(dev, "bus-range", &len); if (bus_range == NULL || len < 2 * sizeof(int)) { printk(KERN_WARNING "Can't get bus-range for %s\n", dev->full_name); @@ -262,20 +255,19 @@ chrp_find_bridges(void) printk(" at %llx", (unsigned long long)r.start); printk("\n"); - hose = pcibios_alloc_controller(); + hose = pcibios_alloc_controller(dev); if (!hose) { printk("Can't allocate PCI controller structure for %s\n", dev->full_name); continue; } - hose->arch_data = dev; - hose->first_busno = bus_range[0]; + hose->first_busno = hose->self_busno = bus_range[0]; hose->last_busno = bus_range[1]; - model = get_property(dev, "model", NULL); + model = of_get_property(dev, "model", NULL); if (model == NULL) model = "<none>"; - if (device_is_compatible(dev, "IBM,python")) { + if (strncmp(model, "IBM, Python", 11) == 0) { setup_python(hose, dev); } else if (is_mot || strncmp(model, "Motorola, Grackle", 17) == 0) { @@ -286,15 +278,17 @@ chrp_find_bridges(void) hose->cfg_data = p; gg2_pci_config_base = p; } else if (is_pegasos == 1) { - setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); + setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0); } else if (is_pegasos == 2) { setup_peg2(hose, dev); } else if (!strncmp(model, "IBM,CPC710", 10)) { setup_indirect_pci(hose, r.start + 0x000f8000, - r.start + 0x000f8010); + r.start + 0x000f8010, + 0); if (index == 0) { - dma = get_property(dev, "system-dma-base",&len); + dma = of_get_property(dev, "system-dma-base", + &len); if (dma && len >= sizeof(*dma)) { dma = (unsigned int *) (((unsigned long)dma) + @@ -312,19 +306,24 @@ chrp_find_bridges(void) /* check the first bridge for a property that we can use to set pci_dram_offset */ - dma = get_property(dev, "ibm,dma-ranges", &len); + dma = of_get_property(dev, "ibm,dma-ranges", &len); if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) { pci_dram_offset = dma[2] - dma[3]; printk("pci_dram_offset = %lx\n", pci_dram_offset); } } + of_node_put(root); } /* SL82C105 IDE Control/Status Register */ #define SL82C105_IDECSR 0x40 -/* Fixup for Winbond ATA quirk, required for briq */ -void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105) +/* Fixup for Winbond ATA quirk, required for briq mostly because the + * 8259 is configured for level sensitive IRQ 14 and so wants the + * ATA controller to be set to fully native mode or bad things + * will happen. + */ +static void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105) { u8 progif; @@ -340,7 +339,41 @@ void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105) sl82c105->class |= 0x05; /* Disable SL82C105 second port */ pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003); + /* Clear IO BARs, they will be reassigned */ + pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_0, 0); + pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_1, 0); + pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_2, 0); + pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_3, 0); } } -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, - chrp_pci_fixup_winbond_ata); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, + chrp_pci_fixup_winbond_ata); + +/* Pegasos2 firmware version 20040810 configures the built-in IDE controller + * in legacy mode, but sets the PCI registers to PCI native mode. + * The chip can only operate in legacy mode, so force the PCI class into legacy + * mode as well. The same fixup must be done to the class-code property in + * the IDE node /pci@80000000/ide@C,1 + */ +static void chrp_pci_fixup_vt8231_ata(struct pci_dev *viaide) +{ + u8 progif; + struct pci_dev *viaisa; + + if (!machine_is(chrp) || _chrp_type != _CHRP_Pegasos) + return; + if (viaide->irq != 14) + return; + + viaisa = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); + if (!viaisa) + return; + dev_info(&viaide->dev, "Fixing VIA IDE, force legacy mode on\n"); + + pci_read_config_byte(viaide, PCI_CLASS_PROG, &progif); + pci_write_config_byte(viaide, PCI_CLASS_PROG, progif & ~0x5); + viaide->class &= ~0x5; + + pci_dev_put(viaisa); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, chrp_pci_fixup_vt8231_ata); diff --git a/arch/powerpc/platforms/chrp/pegasos_eth.c b/arch/powerpc/platforms/chrp/pegasos_eth.c index 6ad4b1a72c9..2b4dc6abde6 100644 --- a/arch/powerpc/platforms/chrp/pegasos_eth.c +++ b/arch/powerpc/platforms/chrp/pegasos_eth.c @@ -21,8 +21,8 @@ #define PEGASOS2_SRAM_BASE (0xf2000000) #define PEGASOS2_SRAM_SIZE (256*1024) -#define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE) -#define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) ) +#define PEGASOS2_SRAM_BASE_ETH_PORT0 (PEGASOS2_SRAM_BASE) +#define PEGASOS2_SRAM_BASE_ETH_PORT1 (PEGASOS2_SRAM_BASE_ETH_PORT0 + (PEGASOS2_SRAM_SIZE / 2) ) #define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4) @@ -47,69 +47,62 @@ static struct platform_device mv643xx_eth_shared_device = { .resource = mv643xx_eth_shared_resources, }; -static struct resource mv643xx_eth0_resources[] = { +/* + * The orion mdio driver only covers shared + 0x4 up to shared + 0x84 - 1 + */ +static struct resource mv643xx_eth_mvmdio_resources[] = { [0] = { - .name = "eth0 irq", - .start = 9, - .end = 9, - .flags = IORESOURCE_IRQ, + .name = "ethernet mdio base", + .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x4, + .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x83, + .flags = IORESOURCE_MEM, }, }; - -static struct mv643xx_eth_platform_data eth0_pd = { - .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0, - .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, - .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, - - .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE, - .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, - .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, -}; - -static struct platform_device eth0_device = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv643xx_eth0_resources), - .resource = mv643xx_eth0_resources, - .dev = { - .platform_data = ð0_pd, - }, +static struct platform_device mv643xx_eth_mvmdio_device = { + .name = "orion-mdio", + .id = -1, + .num_resources = ARRAY_SIZE(mv643xx_eth_mvmdio_resources), + .resource = mv643xx_eth_shared_resources, }; -static struct resource mv643xx_eth1_resources[] = { +static struct resource mv643xx_eth_port1_resources[] = { [0] = { - .name = "eth1 irq", + .name = "eth port1 irq", .start = 9, .end = 9, .flags = IORESOURCE_IRQ, }, }; -static struct mv643xx_eth_platform_data eth1_pd = { - .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1, +static struct mv643xx_eth_platform_data eth_port1_pd = { + .shared = &mv643xx_eth_shared_device, + .port_number = 1, + .phy_addr = MV643XX_ETH_PHY_ADDR(7), + + .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1, .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, - .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE, + .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1 + PEGASOS2_SRAM_TXRING_SIZE, .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, }; -static struct platform_device eth1_device = { +static struct platform_device eth_port1_device = { .name = MV643XX_ETH_NAME, .id = 1, - .num_resources = ARRAY_SIZE(mv643xx_eth1_resources), - .resource = mv643xx_eth1_resources, + .num_resources = ARRAY_SIZE(mv643xx_eth_port1_resources), + .resource = mv643xx_eth_port1_resources, .dev = { - .platform_data = ð1_pd, + .platform_data = ð_port1_pd, }, }; static struct platform_device *mv643xx_eth_pd_devs[] __initdata = { &mv643xx_eth_shared_device, - ð0_device, - ð1_device, + &mv643xx_eth_mvmdio_device, + ð_port1_device, }; /***********/ @@ -167,7 +160,7 @@ static int Enable_SRAM(void) /***********/ /***********/ -int mv643xx_eth_add_pds(void) +static int __init mv643xx_eth_add_pds(void) { int ret = 0; static struct pci_device_id pci_marvell_mv64360[] = { @@ -185,15 +178,10 @@ int mv643xx_eth_add_pds(void) if ( Enable_SRAM() < 0) { - eth0_pd.tx_sram_addr = 0; - eth0_pd.tx_sram_size = 0; - eth0_pd.rx_sram_addr = 0; - eth0_pd.rx_sram_size = 0; - - eth1_pd.tx_sram_addr = 0; - eth1_pd.tx_sram_size = 0; - eth1_pd.rx_sram_addr = 0; - eth1_pd.rx_sram_size = 0; + eth_port1_pd.tx_sram_addr = 0; + eth_port1_pd.tx_sram_size = 0; + eth_port1_pd.rx_sram_addr = 0; + eth_port1_pd.rx_sram_size = 0; #ifdef BE_VERBOSE printk("Pegasos II/Marvell MV64361: Can't enable the " diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c index 488dbd9b51a..7044fd36197 100644 --- a/arch/powerpc/platforms/chrp/setup.c +++ b/arch/powerpc/platforms/chrp/setup.c @@ -15,31 +15,26 @@ #include <linux/stddef.h> #include <linux/unistd.h> #include <linux/ptrace.h> -#include <linux/slab.h> #include <linux/user.h> -#include <linux/a.out.h> #include <linux/tty.h> #include <linux/major.h> #include <linux/interrupt.h> #include <linux/reboot.h> #include <linux/init.h> #include <linux/pci.h> -#include <linux/utsrelease.h> +#include <generated/utsrelease.h> #include <linux/adb.h> #include <linux/module.h> #include <linux/delay.h> -#include <linux/ide.h> #include <linux/console.h> #include <linux/seq_file.h> #include <linux/root_dev.h> #include <linux/initrd.h> -#include <linux/module.h> #include <linux/timer.h> #include <asm/io.h> #include <asm/pgtable.h> #include <asm/prom.h> -#include <asm/gg2.h> #include <asm/pci-bridge.h> #include <asm/dma.h> #include <asm/machdep.h> @@ -53,6 +48,7 @@ #include <asm/xmon.h> #include "chrp.h" +#include "gg2.h" void rtas_indicator_progress(char *, unsigned short); @@ -65,17 +61,10 @@ static struct mpic *chrp_mpic; DEFINE_PER_CPU(struct timer_list, heartbeat_timer); unsigned long event_scan_interval; -/* - * XXX this should be in xmon.h, but putting it there means xmon.h - * has to include <linux/interrupt.h> (to get irqreturn_t), which - * causes all sorts of problems. -- paulus - */ -extern irqreturn_t xmon_irq(int, void *, struct pt_regs *); - extern unsigned long loops_per_jiffy; /* To be replaced by RTAS when available */ -static unsigned int *briq_SPOR; +static unsigned int __iomem *briq_SPOR; #ifdef CONFIG_SMP extern struct smp_ops_t chrp_smp_ops; @@ -111,13 +100,13 @@ void chrp_show_cpuinfo(struct seq_file *m) struct device_node *root; const char *model = ""; - root = find_path_device("/"); + root = of_find_node_by_path("/"); if (root) - model = get_property(root, "model", NULL); + model = of_get_property(root, "model", NULL); seq_printf(m, "machine\t\t: CHRP %s\n", model); /* longtrail (goldengate) stuff */ - if (!strncmp(model, "IBM,LongTrail", 13)) { + if (model && !strncmp(model, "IBM,LongTrail", 13)) { /* VLSI VAS96011/12 `Golden Gate 2' */ /* Memory banks */ sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) @@ -161,6 +150,7 @@ void chrp_show_cpuinfo(struct seq_file *m) gg2_cachetypes[(t>>2) & 3], gg2_cachemodes[t & 3]); } + of_node_put(root); } /* @@ -204,14 +194,21 @@ static void __init sio_fixup_irq(const char *name, u8 device, u8 level, static void __init sio_init(void) { struct device_node *root; + const char *model; - if ((root = find_path_device("/")) && - !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) { + root = of_find_node_by_path("/"); + if (!root) + return; + + model = of_get_property(root, "model", NULL); + if (model && !strncmp(model, "IBM,LongTrail", 13)) { /* logical device 0 (KBC/Keyboard) */ sio_fixup_irq("keyboard", 0, 1, 2); /* select logical device 1 (KBC/Mouse) */ sio_fixup_irq("mouse", 1, 12, 2); } + + of_node_put(root); } @@ -224,12 +221,12 @@ static void __init pegasos_set_l2cr(void) return; /* Enable L2 cache if needed */ - np = find_type_devices("cpu"); + np = of_find_node_by_type(NULL, "cpu"); if (np != NULL) { - const unsigned int *l2cr = get_property(np, "l2cr", NULL); + const unsigned int *l2cr = of_get_property(np, "l2cr", NULL); if (l2cr == NULL) { printk ("Pegasos l2cr : no cpu l2cr property found\n"); - return; + goto out; } if (!((*l2cr) & 0x80000000)) { printk ("Pegasos l2cr : L2 cache was not active, " @@ -238,6 +235,8 @@ static void __init pegasos_set_l2cr(void) _set_L2CR((*l2cr) | 0x80000000); } } +out: + of_node_put(np); } static void briq_restart(char *cmd) @@ -248,16 +247,67 @@ static void briq_restart(char *cmd) for(;;); } +/* + * Per default, input/output-device points to the keyboard/screen + * If no card is installed, the built-in serial port is used as a fallback. + * But unfortunately, the firmware does not connect /chosen/{stdin,stdout} + * the the built-in serial node. Instead, a /failsafe node is created. + */ +static void chrp_init_early(void) +{ + struct device_node *node; + const char *property; + + if (strstr(cmd_line, "console=")) + return; + /* find the boot console from /chosen/stdout */ + if (!of_chosen) + return; + node = of_find_node_by_path("/"); + if (!node) + return; + property = of_get_property(node, "model", NULL); + if (!property) + goto out_put; + if (strcmp(property, "Pegasos2")) + goto out_put; + /* this is a Pegasos2 */ + property = of_get_property(of_chosen, "linux,stdout-path", NULL); + if (!property) + goto out_put; + of_node_put(node); + node = of_find_node_by_path(property); + if (!node) + return; + property = of_get_property(node, "device_type", NULL); + if (!property) + goto out_put; + if (strcmp(property, "serial")) + goto out_put; + /* + * The 9pin connector is either /failsafe + * or /pci@80000000/isa@C/serial@i2F8 + * The optional graphics card has also type 'serial' in VGA mode. + */ + property = of_get_property(node, "name", NULL); + if (!property) + goto out_put; + if (!strcmp(property, "failsafe") || !strcmp(property, "serial")) + add_preferred_console("ttyS", 0, NULL); +out_put: + of_node_put(node); +} + void __init chrp_setup_arch(void) { - struct device_node *root = find_path_device ("/"); + struct device_node *root = of_find_node_by_path("/"); const char *machine = NULL; /* init to some ~sane value until calibrate_delay() runs */ loops_per_jiffy = 50000000/HZ; if (root) - machine = get_property(root, "model", NULL); + machine = of_get_property(root, "model", NULL); if (machine && strncmp(machine, "Pegasos", 7) == 0) { _chrp_type = _CHRP_Pegasos; } else if (machine && strncmp(machine, "IBM", 3) == 0) { @@ -267,12 +317,13 @@ void __init chrp_setup_arch(void) } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) { _chrp_type = _CHRP_briq; /* Map the SPOR register on briq and change the restart hook */ - briq_SPOR = (unsigned int *)ioremap(0xff0000e8, 4); + briq_SPOR = ioremap(0xff0000e8, 4); ppc_md.restart = briq_restart; } else { /* Let's assume it is an IBM chrp if all else fails */ _chrp_type = _CHRP_IBM; } + of_node_put(root); printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]); rtas_initialize(); @@ -286,16 +337,6 @@ void __init chrp_setup_arch(void) ppc_md.set_rtc_time = rtas_set_rtc_time; } -#ifdef CONFIG_BLK_DEV_INITRD - /* this is fine for chrp */ - initrd_below_start_ok = 1; - - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif - ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */ - /* On pegasos, enable the L2 cache if not already done by OF */ pegasos_set_l2cr(); @@ -322,26 +363,15 @@ void __init chrp_setup_arch(void) if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); } -void -chrp_event_scan(unsigned long unused) +static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) { - unsigned char log[1024]; - int ret = 0; - - /* XXX: we should loop until the hardware says no more error logs -- Cort */ - rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0, - __pa(log), 1024); - mod_timer(&__get_cpu_var(heartbeat_timer), - jiffies + event_scan_interval); -} + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int cascade_irq = i8259_irq(); -static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc, - struct pt_regs *regs) -{ - unsigned int cascade_irq = i8259_irq(regs); if (cascade_irq != NO_IRQ) - generic_handle_irq(cascade_irq, regs); - desc->chip->eoi(irq); + generic_handle_irq(cascade_irq); + + chip->irq_eoi(&desc->irq_data); } /* @@ -362,8 +392,8 @@ static void __init chrp_find_openpic(void) return; root = of_find_node_by_path("/"); if (root) { - opprop = get_property(root, "platform-open-pic", &oplen); - na = prom_n_addr_cells(root); + opprop = of_get_property(root, "platform-open-pic", &oplen); + na = of_n_addr_cells(root); } if (opprop && oplen >= na * sizeof(unsigned int)) { opaddr = opprop[na-1]; /* assume 32-bit */ @@ -379,7 +409,7 @@ static void __init chrp_find_openpic(void) printk(KERN_INFO "OpenPIC at %lx\n", opaddr); - iranges = get_property(np, "interrupt-ranges", &len); + iranges = of_get_property(np, "interrupt-ranges", &len); if (iranges == NULL) len = 0; /* non-distributed mpic */ else @@ -405,8 +435,8 @@ static void __init chrp_find_openpic(void) if (len > 1) isu_size = iranges[3]; - chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY, - isu_size, 0, " MPIC "); + chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET, + isu_size, 0, " MPIC "); if (chrp_mpic == NULL) { printk(KERN_ERR "Failed to allocate MPIC structure\n"); goto bail; @@ -428,10 +458,9 @@ static void __init chrp_find_openpic(void) of_node_put(np); } -#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) +#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) static struct irqaction xmon_irqaction = { .handler = xmon_irq, - .mask = CPU_MASK_NONE, .name = "XMON break", }; #endif @@ -444,7 +473,7 @@ static void __init chrp_find_8259(void) /* Look for cascade */ for_each_node_by_type(np, "interrupt-controller") - if (device_is_compatible(np, "chrp,iic")) { + if (of_device_is_compatible(np, "chrp,iic")) { pic = np; break; } @@ -464,35 +493,38 @@ static void __init chrp_find_8259(void) * Also, Pegasos-type platforms don't have a proper node to start * from anyway */ - for (np = find_devices("pci"); np != NULL; np = np->next) { - const unsigned int *addrp = get_property(np, + for_each_node_by_name(np, "pci") { + const unsigned int *addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL); if (addrp == NULL) continue; - chrp_int_ack = addrp[prom_n_addr_cells(np)-1]; + chrp_int_ack = addrp[of_n_addr_cells(np)-1]; break; } + of_node_put(np); if (np == NULL) printk(KERN_WARNING "Cannot find PCI interrupt acknowledge" " address, polling\n"); i8259_init(pic, chrp_int_ack); - if (ppc_md.get_irq == NULL) + if (ppc_md.get_irq == NULL) { ppc_md.get_irq = i8259_irq; + irq_set_default_host(i8259_get_host()); + } if (chrp_mpic != NULL) { cascade_irq = irq_of_parse_and_map(pic, 0); if (cascade_irq == NO_IRQ) printk(KERN_ERR "i8259: failed to map cascade irq\n"); else - set_irq_chained_handler(cascade_irq, + irq_set_chained_handler(cascade_irq, chrp_8259_cascade); } } void __init chrp_init_IRQ(void) { -#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) +#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) struct device_node *kbd; #endif chrp_find_openpic(); @@ -509,13 +541,14 @@ void __init chrp_init_IRQ(void) if (_chrp_type == _CHRP_Pegasos) ppc_md.get_irq = i8259_irq; -#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) +#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) /* see if there is a keyboard in the device tree with a parent of type "adb" */ - for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next) + for_each_node_by_name(kbd, "keyboard") if (kbd->parent && kbd->parent->type && strcmp(kbd->parent->type, "adb") == 0) break; + of_node_put(kbd); if (kbd) setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction); #endif @@ -524,9 +557,6 @@ void __init chrp_init_IRQ(void) void __init chrp_init2(void) { - struct device_node *device; - const unsigned int *p = NULL; - #ifdef CONFIG_NVRAM chrp_nvram_init(); #endif @@ -538,47 +568,14 @@ chrp_init2(void) request_region(0x80,0x10,"dma page reg"); request_region(0xc0,0x20,"dma2"); - /* Get the event scan rate for the rtas so we know how - * often it expects a heartbeat. -- Cort - */ - device = find_devices("rtas"); - if (device) - p = get_property(device, "rtas-event-scan-rate", NULL); - if (p && *p) { - /* - * Arrange to call chrp_event_scan at least *p times - * per minute. We use 59 rather than 60 here so that - * the rate will be slightly higher than the minimum. - * This all assumes we don't do hotplug CPU on any - * machine that needs the event scans done. - */ - unsigned long interval, offset; - int cpu, ncpus; - struct timer_list *timer; - - interval = HZ * 59 / *p; - offset = HZ; - ncpus = num_online_cpus(); - event_scan_interval = ncpus * interval; - for (cpu = 0; cpu < ncpus; ++cpu) { - timer = &per_cpu(heartbeat_timer, cpu); - setup_timer(timer, chrp_event_scan, 0); - timer->expires = jiffies + offset; - add_timer_on(timer, cpu); - offset += interval; - } - printk("RTAS Event Scan Rate: %u (%lu jiffies)\n", - *p, interval); - } - if (ppc_md.progress) ppc_md.progress(" Have fun! ", 0x7777); } static int __init chrp_probe(void) { - char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), - "device_type", NULL); + const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), + "device_type", NULL); if (dtype == NULL) return 0; if (strcmp(dtype, "chrp")) @@ -587,7 +584,6 @@ static int __init chrp_probe(void) ISA_DMA_THRESHOLD = ~0L; DMA_MODE_READ = 0x44; DMA_MODE_WRITE = 0x48; - isa_io_base = CHRP_ISA_IO_BASE; /* default value */ return 1; } @@ -597,9 +593,9 @@ define_machine(chrp) { .probe = chrp_probe, .setup_arch = chrp_setup_arch, .init = chrp_init2, + .init_early = chrp_init_early, .show_cpuinfo = chrp_show_cpuinfo, .init_IRQ = chrp_init_IRQ, - .pcibios_fixup = chrp_pcibios_fixup, .restart = rtas_restart, .power_off = rtas_power_off, .halt = rtas_halt, diff --git a/arch/powerpc/platforms/chrp/smp.c b/arch/powerpc/platforms/chrp/smp.c index 1d2307e87c3..b6c9a0dcc92 100644 --- a/arch/powerpc/platforms/chrp/smp.c +++ b/arch/powerpc/platforms/chrp/smp.c @@ -11,15 +11,13 @@ #include <linux/kernel.h> #include <linux/sched.h> #include <linux/smp.h> -#include <linux/smp_lock.h> #include <linux/interrupt.h> #include <linux/kernel_stat.h> #include <linux/delay.h> -#include <linux/init.h> #include <linux/spinlock.h> #include <asm/ptrace.h> -#include <asm/atomic.h> +#include <linux/atomic.h> #include <asm/irq.h> #include <asm/page.h> #include <asm/pgtable.h> @@ -27,50 +25,21 @@ #include <asm/io.h> #include <asm/prom.h> #include <asm/smp.h> -#include <asm/residual.h> -#include <asm/time.h> #include <asm/machdep.h> -#include <asm/smp.h> #include <asm/mpic.h> #include <asm/rtas.h> -static void __devinit smp_chrp_kick_cpu(int nr) +static int smp_chrp_kick_cpu(int nr) { *(unsigned long *)KERNELBASE = nr; asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory"); -} - -static void __devinit smp_chrp_setup_cpu(int cpu_nr) -{ - mpic_setup_this_cpu(); -} - -static DEFINE_SPINLOCK(timebase_lock); -static unsigned int timebase_upper = 0, timebase_lower = 0; -void __devinit smp_chrp_give_timebase(void) -{ - spin_lock(&timebase_lock); - rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); - timebase_upper = get_tbu(); - timebase_lower = get_tbl(); - spin_unlock(&timebase_lock); - - while (timebase_upper || timebase_lower) - barrier(); - rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); + return 0; } -void __devinit smp_chrp_take_timebase(void) +static void smp_chrp_setup_cpu(int cpu_nr) { - while (!(timebase_upper || timebase_lower)) - barrier(); - spin_lock(&timebase_lock); - set_tb(timebase_upper, timebase_lower); - timebase_upper = 0; - timebase_lower = 0; - spin_unlock(&timebase_lock); - printk("CPU %i taken timebase\n", smp_processor_id()); + mpic_setup_this_cpu(); } /* CHRP with openpic */ @@ -79,6 +48,6 @@ struct smp_ops_t chrp_smp_ops = { .probe = smp_mpic_probe, .kick_cpu = smp_chrp_kick_cpu, .setup_cpu = smp_chrp_setup_cpu, - .give_timebase = smp_chrp_give_timebase, - .take_timebase = smp_chrp_take_timebase, + .give_timebase = rtas_give_timebase, + .take_timebase = rtas_take_timebase, }; diff --git a/arch/powerpc/platforms/chrp/time.c b/arch/powerpc/platforms/chrp/time.c index 7d788902693..f803f4b8ab6 100644 --- a/arch/powerpc/platforms/chrp/time.c +++ b/arch/powerpc/platforms/chrp/time.c @@ -29,6 +29,10 @@ extern spinlock_t rtc_lock; +#define NVRAM_AS0 0x74 +#define NVRAM_AS1 0x75 +#define NVRAM_DATA 0x77 + static int nvram_as1 = NVRAM_AS1; static int nvram_as0 = NVRAM_AS0; static int nvram_data = NVRAM_DATA; @@ -39,12 +43,17 @@ long __init chrp_time_init(void) struct resource r; int base; - rtcs = find_compatible_devices("rtc", "pnpPNP,b00"); + rtcs = of_find_compatible_node(NULL, "rtc", "pnpPNP,b00"); + if (rtcs == NULL) + rtcs = of_find_compatible_node(NULL, "rtc", "ds1385-rtc"); if (rtcs == NULL) - rtcs = find_compatible_devices("rtc", "ds1385-rtc"); - if (rtcs == NULL || of_address_to_resource(rtcs, 0, &r)) return 0; - + if (of_address_to_resource(rtcs, 0, &r)) { + of_node_put(rtcs); + return 0; + } + of_node_put(rtcs); + base = r.start; nvram_as1 = 0; nvram_as0 = base; @@ -89,12 +98,12 @@ int chrp_set_rtc_time(struct rtc_time *tmarg) chrp_cmos_clock_write((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BIN_TO_BCD(tm.tm_sec); - BIN_TO_BCD(tm.tm_min); - BIN_TO_BCD(tm.tm_hour); - BIN_TO_BCD(tm.tm_mon); - BIN_TO_BCD(tm.tm_mday); - BIN_TO_BCD(tm.tm_year); + tm.tm_sec = bin2bcd(tm.tm_sec); + tm.tm_min = bin2bcd(tm.tm_min); + tm.tm_hour = bin2bcd(tm.tm_hour); + tm.tm_mon = bin2bcd(tm.tm_mon); + tm.tm_mday = bin2bcd(tm.tm_mday); + tm.tm_year = bin2bcd(tm.tm_year); } chrp_cmos_clock_write(tm.tm_sec,RTC_SECONDS); chrp_cmos_clock_write(tm.tm_min,RTC_MINUTES); @@ -131,12 +140,12 @@ void chrp_get_rtc_time(struct rtc_time *tm) } while (sec != chrp_cmos_clock_read(RTC_SECONDS)); if (!(chrp_cmos_clock_read(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BCD_TO_BIN(sec); - BCD_TO_BIN(min); - BCD_TO_BIN(hour); - BCD_TO_BIN(day); - BCD_TO_BIN(mon); - BCD_TO_BIN(year); + sec = bcd2bin(sec); + min = bcd2bin(min); + hour = bcd2bin(hour); + day = bcd2bin(day); + mon = bcd2bin(mon); + year = bcd2bin(year); } if (year < 70) year += 100; |