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Diffstat (limited to 'arch/powerpc/platforms/85xx/mpc85xx_cds.c')
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_cds.c379
1 files changed, 224 insertions, 155 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 4c1fede6470..b0753e22208 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -3,7 +3,7 @@
*
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
*
- * Copyright 2005 Freescale Semiconductor Inc.
+ * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -11,7 +11,6 @@
* option) any later version.
*/
-#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
@@ -23,22 +22,19 @@
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
-#include <linux/root_dev.h>
#include <linux/initrd.h>
-#include <linux/module.h>
+#include <linux/interrupt.h>
#include <linux/fsl_devices.h>
+#include <linux/of_platform.h>
-#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/ipic.h>
-#include <asm/bootinfo.h>
#include <asm/pci-bridge.h>
-#include <asm/mpc85xx.h>
#include <asm/irq.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
@@ -47,32 +43,37 @@
#include <asm/i8259.h>
#include <sysdev/fsl_soc.h>
-#include "mpc85xx.h"
+#include <sysdev/fsl_pci.h>
-#ifndef CONFIG_PCI
-unsigned long isa_io_base = 0;
-unsigned long isa_mem_base = 0;
-#endif
+#include "mpc85xx.h"
-static int cds_pci_slot = 2;
-static volatile u8 *cadmus;
+/*
+ * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
+ * various logic and performs system control functions.
+ * Here is the FPGA/CPLD register map.
+ */
+struct cadmus_reg {
+ u8 cm_ver; /* Board version */
+ u8 cm_csr; /* General control/status */
+ u8 cm_rst; /* Reset control */
+ u8 cm_hsclk; /* High speed clock */
+ u8 cm_hsxclk; /* High speed clock extended */
+ u8 cm_led; /* LED data */
+ u8 cm_pci; /* PCI control/status */
+ u8 cm_dma; /* DMA control */
+ u8 res[248]; /* Total 256 bytes */
+};
+static struct cadmus_reg *cadmus;
#ifdef CONFIG_PCI
#define ARCADIA_HOST_BRIDGE_IDSEL 17
#define ARCADIA_2ND_BRIDGE_IDSEL 3
-extern int mpc85xx_pci2_busno;
-
-int
-mpc85xx_exclude_device(u_char bus, u_char devfn)
+static int mpc85xx_exclude_device(struct pci_controller *hose,
+ u_char bus, u_char devfn)
{
- if (bus == 0 && PCI_SLOT(devfn) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
- if (mpc85xx_pci2_busno)
- if (bus == (mpc85xx_pci2_busno) && PCI_SLOT(devfn) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
/* We explicitly do not go past the Tundra 320 Bridge */
if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -82,221 +83,283 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
return PCIBIOS_SUCCESSFUL;
}
-void __init
-mpc85xx_cds_pcibios_fixup(void)
+static void mpc85xx_cds_restart(char *cmd)
{
struct pci_dev *dev;
- u_char c;
+ u_char tmp;
- if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
- /*
- * U-Boot does not set the enable bits
- * for the IDE device. Force them on here.
- */
- pci_read_config_byte(dev, 0x40, &c);
- c |= 0x03; /* IDE: Chip Enable Bits */
- pci_write_config_byte(dev, 0x40, c);
+ if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
+ NULL))) {
+
+ /* Use the VIA Super Southbridge to force a PCI reset */
+ pci_read_config_byte(dev, 0x47, &tmp);
+ pci_write_config_byte(dev, 0x47, tmp | 1);
+
+ /* Flush the outbound PCI write queues */
+ pci_read_config_byte(dev, 0x47, &tmp);
/*
- * Since only primary interface works, force the
- * IDE function to standard primary IDE interrupt
- * w/ 8259 offset
+ * At this point, the harware reset should have triggered.
+ * However, if it doesn't work for some mysterious reason,
+ * just fall through to the default reset below.
*/
- dev->irq = 14;
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+
pci_dev_put(dev);
}
/*
- * Force legacy USB interrupt routing
+ * If we can't find the VIA chip (maybe the P2P bridge is disabled)
+ * or the VIA chip reset didn't work, just use the default reset.
*/
- if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
- dev->irq = 10;
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
- pci_dev_put(dev);
+ fsl_rstcr_restart(NULL);
+}
+
+static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
+{
+ u_char c;
+ if (dev->vendor == PCI_VENDOR_ID_VIA) {
+ switch (dev->device) {
+ case PCI_DEVICE_ID_VIA_82C586_1:
+ /*
+ * U-Boot does not set the enable bits
+ * for the IDE device. Force them on here.
+ */
+ pci_read_config_byte(dev, 0x40, &c);
+ c |= 0x03; /* IDE: Chip Enable Bits */
+ pci_write_config_byte(dev, 0x40, c);
+
+ /*
+ * Since only primary interface works, force the
+ * IDE function to standard primary IDE interrupt
+ * w/ 8259 offset
+ */
+ dev->irq = 14;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+ break;
+ /*
+ * Force legacy USB interrupt routing
+ */
+ case PCI_DEVICE_ID_VIA_82C586_2:
+ /* There are two USB controllers.
+ * Identify them by functon number
+ */
+ if (PCI_FUNC(dev->devfn) == 3)
+ dev->irq = 11;
+ else
+ dev->irq = 10;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+ default:
+ break;
+ }
}
+}
- if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_82C586_2, dev))) {
- dev->irq = 11;
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
- pci_dev_put(dev);
+static void skip_fake_bridge(struct pci_dev *dev)
+{
+ /* Make it an error to skip the fake bridge
+ * in pci_setup_device() in probe.c */
+ dev->hdr_type = 0x7f;
+}
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
+DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
+DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
+
+#define PCI_DEVICE_ID_IDT_TSI310 0x01a7
+
+/*
+ * Fix Tsi310 PCI-X bridge resource.
+ * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
+ * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
+ */
+void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
+{
+ struct pci_dev *dev = bus->self;
+ struct resource *res = bus->resource[0];
+
+ if (dev != NULL &&
+ dev->vendor == PCI_VENDOR_ID_IBM &&
+ dev->device == PCI_DEVICE_ID_IDT_TSI310) {
+ if (res) {
+ res->start = 0;
+ res->end = 0x1fff;
+ res->flags = IORESOURCE_IO;
+ pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
+ pr_info("mpc85xx_cds: %pR\n", res);
+ }
}
- /* Now map all the PCI irqs */
- dev = NULL;
- for_each_pci_dev(dev)
- pci_read_irq_line(dev);
+ fsl_pcibios_fixup_bus(bus);
}
#ifdef CONFIG_PPC_I8259
-#warning The i8259 PIC support is currently broken
-static void mpc85xx_8259_cascade(unsigned int irq, struct
- irq_desc *desc, struct pt_regs *regs)
+static void mpc85xx_8259_cascade_handler(unsigned int irq,
+ struct irq_desc *desc)
{
- unsigned int cascade_irq = i8259_irq(regs);
+ unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq, regs);
+ /* handle an interrupt from the 8259 */
+ generic_handle_irq(cascade_irq);
+
+ /* check for any interrupts from the shared IRQ line */
+ handle_fasteoi_irq(irq, desc);
+}
- desc->chip->eoi(irq);
+static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
+{
+ return IRQ_HANDLED;
}
+
+static struct irqaction mpc85xxcds_8259_irqaction = {
+ .handler = mpc85xx_8259_cascade_action,
+ .flags = IRQF_SHARED | IRQF_NO_THREAD,
+ .name = "8259 cascade",
+};
#endif /* PPC_I8259 */
#endif /* CONFIG_PCI */
-void __init mpc85xx_cds_pic_init(void)
+static void __init mpc85xx_cds_pic_init(void)
{
struct mpic *mpic;
- struct resource r;
+ mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
+ 0, 256, " OpenPIC ");
+ BUG_ON(mpic == NULL);
+ mpic_init(mpic);
+}
+
+#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
+static int mpc85xx_cds_8259_attach(void)
+{
+ int ret;
struct device_node *np = NULL;
struct device_node *cascade_node = NULL;
int cascade_irq;
- np = of_find_node_by_type(np, "open-pic");
-
- if (np == NULL) {
- printk(KERN_ERR "Could not find open-pic node\n");
- return;
- }
-
- if (of_address_to_resource(np, 0, &r)) {
- printk(KERN_ERR "Failed to map mpic register space\n");
- of_node_put(np);
- return;
- }
-
- mpic = mpic_alloc(np, r.start,
- MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
- 4, 0, " OpenPIC ");
- BUG_ON(mpic == NULL);
-
- /* Return the mpic node */
- of_node_put(np);
-
- mpic_assign_isu(mpic, 0, r.start + 0x10200);
- mpic_assign_isu(mpic, 1, r.start + 0x10280);
- mpic_assign_isu(mpic, 2, r.start + 0x10300);
- mpic_assign_isu(mpic, 3, r.start + 0x10380);
- mpic_assign_isu(mpic, 4, r.start + 0x10400);
- mpic_assign_isu(mpic, 5, r.start + 0x10480);
- mpic_assign_isu(mpic, 6, r.start + 0x10500);
- mpic_assign_isu(mpic, 7, r.start + 0x10580);
-
- /* Used only for 8548 so far, but no harm in
- * allocating them for everyone */
- mpic_assign_isu(mpic, 8, r.start + 0x10600);
- mpic_assign_isu(mpic, 9, r.start + 0x10680);
- mpic_assign_isu(mpic, 10, r.start + 0x10700);
- mpic_assign_isu(mpic, 11, r.start + 0x10780);
-
- /* External Interrupts */
- mpic_assign_isu(mpic, 12, r.start + 0x10000);
- mpic_assign_isu(mpic, 13, r.start + 0x10080);
- mpic_assign_isu(mpic, 14, r.start + 0x10100);
-
- mpic_init(mpic);
-
-#ifdef CONFIG_PPC_I8259
/* Initialize the i8259 controller */
for_each_node_by_type(np, "interrupt-controller")
- if (device_is_compatible(np, "chrp,iic")) {
+ if (of_device_is_compatible(np, "chrp,iic")) {
cascade_node = np;
break;
}
if (cascade_node == NULL) {
printk(KERN_DEBUG "Could not find i8259 PIC\n");
- return;
+ return -ENODEV;
}
cascade_irq = irq_of_parse_and_map(cascade_node, 0);
if (cascade_irq == NO_IRQ) {
printk(KERN_ERR "Failed to map cascade interrupt\n");
- return;
+ return -ENXIO;
}
i8259_init(cascade_node, 0);
of_node_put(cascade_node);
- set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
-#endif /* CONFIG_PPC_I8259 */
+ /*
+ * Hook the interrupt to make sure desc->action is never NULL.
+ * This is required to ensure that the interrupt does not get
+ * disabled when the last user of the shared IRQ line frees their
+ * interrupt.
+ */
+ if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
+ printk(KERN_ERR "Failed to setup cascade interrupt\n");
+ return ret;
+ }
+
+ /* Success. Connect our low-level cascade handler. */
+ irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
+
+ return 0;
}
+machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
+
+#endif /* CONFIG_PPC_I8259 */
+
+static void mpc85xx_cds_pci_assign_primary(void)
+{
+#ifdef CONFIG_PCI
+ struct device_node *np;
+
+ if (fsl_pci_primary)
+ return;
+ /*
+ * MPC85xx_CDS has ISA bridge but unfortunately there is no
+ * isa node in device tree. We now looking for i8259 node as
+ * a workaround for such a broken device tree. This routine
+ * is for complying to all device trees.
+ */
+ np = of_find_node_by_name(NULL, "i8259");
+ while ((fsl_pci_primary = of_get_parent(np))) {
+ of_node_put(np);
+ np = fsl_pci_primary;
+
+ if ((of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+ of_device_is_compatible(np, "fsl,mpc8548-pcie")) &&
+ of_device_is_available(np))
+ return;
+ }
+#endif
+}
/*
* Setup the architecture
*/
-static void __init
-mpc85xx_cds_setup_arch(void)
+static void __init mpc85xx_cds_setup_arch(void)
{
- struct device_node *cpu;
-#ifdef CONFIG_PCI
struct device_node *np;
-#endif
+ int cds_pci_slot;
if (ppc_md.progress)
ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
- cpu = of_find_node_by_type(NULL, "cpu");
- if (cpu != 0) {
- const unsigned int *fp;
-
- fp = get_property(cpu, "clock-frequency", NULL);
- if (fp != 0)
- loops_per_jiffy = *fp / HZ;
- else
- loops_per_jiffy = 500000000 / HZ;
- of_node_put(cpu);
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
+ if (!np) {
+ pr_err("Could not find FPGA node.\n");
+ return;
}
- cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
- cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
+ cadmus = of_iomap(np, 0);
+ of_node_put(np);
+ if (!cadmus) {
+ pr_err("Fail to map FPGA area.\n");
+ return;
+ }
if (ppc_md.progress) {
char buf[40];
+ cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
- cadmus[CM_VER], cds_pci_slot);
+ in_8(&cadmus->cm_ver), cds_pci_slot);
ppc_md.progress(buf, 0);
}
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- add_bridge(np);
-
- ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
+ ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
-#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
-#else
- ROOT_DEV = Root_HDA1;
-#endif
+ mpc85xx_cds_pci_assign_primary();
+ fsl_pci_assign_primary();
}
-
-void
-mpc85xx_cds_show_cpuinfo(struct seq_file *m)
+static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
{
uint pvid, svid, phid1;
- uint memsize = total_memory;
pvid = mfspr(SPRN_PVR);
svid = mfspr(SPRN_SVR);
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
- seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
+ seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
+ in_8(&cadmus->cm_ver));
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
/* Display cpu Pll setting */
phid1 = mfspr(SPRN_HID1);
seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
-
- /* Display the amount of memory */
- seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
}
@@ -305,13 +368,13 @@ mpc85xx_cds_show_cpuinfo(struct seq_file *m)
*/
static int __init mpc85xx_cds_probe(void)
{
- /* We always match for now, eventually we should look at
- * the flat dev tree to ensure this is the board we are
- * supposed to run on
- */
- return 1;
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "MPC85xxCDS");
}
+machine_arch_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
+
define_machine(mpc85xx_cds) {
.name = "MPC85xx CDS",
.probe = mpc85xx_cds_probe,
@@ -319,7 +382,13 @@ define_machine(mpc85xx_cds) {
.init_IRQ = mpc85xx_cds_pic_init,
.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
.get_irq = mpic_get_irq,
- .restart = mpc85xx_restart,
+#ifdef CONFIG_PCI
+ .restart = mpc85xx_cds_restart,
+ .pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
+#else
+ .restart = fsl_rstcr_restart,
+#endif
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-16 00:34:58 +0000