diff options
Diffstat (limited to 'arch/powerpc/platforms/83xx/mpc836x_mds.c')
| -rw-r--r-- | arch/powerpc/platforms/83xx/mpc836x_mds.c | 186 |
1 files changed, 104 insertions, 82 deletions
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c index bceeff8bbfd..1a26d2f8340 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. + * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved. * * Author: Li Yang <LeoLi@freescale.com> * Yin Olivia <Hong-hua.Yin@freescale.com> @@ -18,6 +18,7 @@ #include <linux/stddef.h> #include <linux/kernel.h> +#include <linux/compiler.h> #include <linux/init.h> #include <linux/errno.h> #include <linux/reboot.h> @@ -29,20 +30,20 @@ #include <linux/seq_file.h> #include <linux/root_dev.h> #include <linux/initrd.h> +#include <linux/of_platform.h> +#include <linux/of_device.h> -#include <asm/of_device.h> -#include <asm/of_platform.h> -#include <asm/system.h> -#include <asm/atomic.h> +#include <linux/atomic.h> #include <asm/time.h> #include <asm/io.h> #include <asm/machdep.h> #include <asm/ipic.h> -#include <asm/bootinfo.h> #include <asm/irq.h> #include <asm/prom.h> #include <asm/udbg.h> #include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> +#include <sysdev/simple_gpio.h> #include <asm/qe.h> #include <asm/qe_ic.h> @@ -55,13 +56,6 @@ #define DBG(fmt...) #endif -#ifndef CONFIG_PCI -unsigned long isa_io_base = 0; -unsigned long isa_mem_base = 0; -#endif - -static u8 *bcsr_regs = NULL; - /* ************************************************************************ * * Setup the architecture @@ -70,25 +64,22 @@ static u8 *bcsr_regs = NULL; static void __init mpc836x_mds_setup_arch(void) { struct device_node *np; + u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc836x_mds_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); - if (np != 0) { + if (np) { struct resource res; of_address_to_resource(np, 0, &res); - bcsr_regs = ioremap(res.start, res.end - res.start +1); + bcsr_regs = ioremap(res.start, resource_size(&res)); of_node_put(np); } -#ifdef CONFIG_PCI - for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) - add_bridge(np); - ppc_md.pci_exclude_device = mpc83xx_exclude_device; -#endif + mpc83xx_setup_pci(); #ifdef CONFIG_QUICC_ENGINE qe_reset(); @@ -99,90 +90,121 @@ static void __init mpc836x_mds_setup_arch(void) for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); +#ifdef CONFIG_QE_USB + /* Must fixup Par IO before QE GPIO chips are registered. */ + par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */ + par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */ + par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */ + par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */ + par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */ + par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */ + par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */ +#endif /* CONFIG_QE_USB */ } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ + uint svid; + /* Reset the Ethernet PHY */ - bcsr_regs[9] &= ~0x20; +#define BCSR9_GETHRST 0x20 + clrbits8(&bcsr_regs[9], BCSR9_GETHRST); udelay(1000); - bcsr_regs[9] |= 0x20; - iounmap(bcsr_regs); - of_node_put(np); - } + setbits8(&bcsr_regs[9], BCSR9_GETHRST); -#endif /* CONFIG_QUICC_ENGINE */ -} + /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ + svid = mfspr(SPRN_SVR); + if (svid == 0x80480021) { + void __iomem *immap; -static struct of_device_id mpc836x_ids[] = { - { .type = "soc", }, - { .compatible = "soc", }, - { .type = "qe", }, - { .type = "mdio", }, - {}, -}; + immap = ioremap(get_immrbase() + 0x14a8, 8); -static int __init mpc836x_declare_of_platform_devices(void) -{ - if (!machine_is(mpc836x_mds)) - return 0; + /* + * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) + * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) + */ + setbits32(immap, 0x0c003000); + + /* + * IMMR + 0x14AC[20:27] = 10101010 + * (data delay for both UCC's) + */ + clrsetbits_be32(immap + 4, 0xff0, 0xaa0); - /* Publish the QE devices */ - of_platform_bus_probe(NULL, mpc836x_ids, NULL); + iounmap(immap); + } - return 0; + iounmap(bcsr_regs); + of_node_put(np); + } +#endif /* CONFIG_QUICC_ENGINE */ } -device_initcall(mpc836x_declare_of_platform_devices); -static void __init mpc836x_mds_init_IRQ(void) +machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices); + +#ifdef CONFIG_QE_USB +static int __init mpc836x_usb_cfg(void) { + u8 __iomem *bcsr; struct device_node *np; + const char *mode; + int ret = 0; - np = of_find_node_by_type(NULL, "ipic"); + np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr"); if (!np) - return; - - ipic_init(np, 0); + return -ENODEV; - /* Initialize the default interrupt mapping priorities, - * in case the boot rom changed something on us. - */ - ipic_set_default_priority(); + bcsr = of_iomap(np, 0); of_node_put(np); + if (!bcsr) + return -ENOMEM; -#ifdef CONFIG_QUICC_ENGINE - np = of_find_node_by_type(NULL, "qeic"); - if (!np) - return; - - qe_ic_init(np, 0); - of_node_put(np); -#endif /* CONFIG_QUICC_ENGINE */ -} - -#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374) -extern ulong ds1374_get_rtc_time(void); -extern int ds1374_set_rtc_time(ulong); - -static int __init mpc8360_rtc_hookup(void) -{ - struct timespec tv; - - if (!machine_is(mpc836x_mds)) - return 0; - - ppc_md.get_rtc_time = ds1374_get_rtc_time; - ppc_md.set_rtc_time = ds1374_set_rtc_time; + np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb"); + if (!np) { + ret = -ENODEV; + goto err; + } - tv.tv_nsec = 0; - tv.tv_sec = (ppc_md.get_rtc_time) (); - do_settimeofday(&tv); +#define BCSR8_TSEC1M_MASK (0x3 << 6) +#define BCSR8_TSEC1M_RGMII (0x0 << 6) +#define BCSR8_TSEC2M_MASK (0x3 << 4) +#define BCSR8_TSEC2M_RGMII (0x0 << 4) + /* + * Default is GMII (2), but we should set it to RGMII (0) if we use + * USB (Eth PHY is in RGMII mode anyway). + */ + clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK, + BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII); + +#define BCSR13_USBMASK 0x0f +#define BCSR13_nUSBEN 0x08 /* 1 - Disable, 0 - Enable */ +#define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low */ +#define BCSR13_USBMODE 0x02 /* 1 - Host, 0 - Function */ +#define BCSR13_nUSBVCC 0x01 /* 1 - gets VBUS, 0 - supplies VBUS */ + + clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED); + + mode = of_get_property(np, "mode", NULL); + if (mode && !strcmp(mode, "peripheral")) { + setbits8(&bcsr[13], BCSR13_nUSBVCC); + qe_usb_clock_set(QE_CLK21, 48000000); + } else { + setbits8(&bcsr[13], BCSR13_USBMODE); + /* + * The BCSR GPIOs are used to control power and + * speed of the USB transceiver. This is needed for + * the USB Host only. + */ + simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio"); + } - return 0; + of_node_put(np); +err: + iounmap(bcsr); + return ret; } - -late_initcall(mpc8360_rtc_hookup); -#endif +machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg); +#endif /* CONFIG_QE_USB */ /* * Called very early, MMU is off, device-tree isn't unflattened @@ -198,7 +220,7 @@ define_machine(mpc836x_mds) { .name = "MPC836x MDS", .probe = mpc836x_mds_probe, .setup_arch = mpc836x_mds_setup_arch, - .init_IRQ = mpc836x_mds_init_IRQ, + .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ, .get_irq = ipic_get_irq, .restart = mpc83xx_restart, .time_init = mpc83xx_time_init, |