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-rw-r--r--arch/powerpc/platforms/82xx/Kconfig52
-rw-r--r--arch/powerpc/platforms/82xx/Makefile8
-rw-r--r--arch/powerpc/platforms/82xx/ep8248e.c335
-rw-r--r--arch/powerpc/platforms/82xx/km82xx.c215
-rw-r--r--arch/powerpc/platforms/82xx/m82xx_pci.h2
-rw-r--r--arch/powerpc/platforms/82xx/mpc8272_ads.c218
-rw-r--r--arch/powerpc/platforms/82xx/mpc82xx.c110
-rw-r--r--arch/powerpc/platforms/82xx/mpc82xx_ads.c641
-rw-r--r--arch/powerpc/platforms/82xx/pq2.c81
-rw-r--r--arch/powerpc/platforms/82xx/pq2.h20
-rw-r--r--arch/powerpc/platforms/82xx/pq2ads-pci-pic.c180
-rw-r--r--arch/powerpc/platforms/82xx/pq2ads.h22
-rw-r--r--arch/powerpc/platforms/82xx/pq2fads.c196
13 files changed, 1295 insertions, 785 deletions
diff --git a/arch/powerpc/platforms/82xx/Kconfig b/arch/powerpc/platforms/82xx/Kconfig
index 89fde43895c..7c7df400382 100644
--- a/arch/powerpc/platforms/82xx/Kconfig
+++ b/arch/powerpc/platforms/82xx/Kconfig
@@ -1,19 +1,52 @@
-choice
- prompt "82xx Board Type"
- depends on PPC_82xx
- default MPC82xx_ADS
+menuconfig PPC_82xx
+ bool "82xx-based boards (PQ II)"
+ depends on 6xx
+
+if PPC_82xx
-config MPC82xx_ADS
- bool "Freescale MPC82xx ADS"
+config MPC8272_ADS
+ bool "Freescale MPC8272 ADS"
select DEFAULT_UIMAGE
select PQ2ADS
select 8272
select 8260
select FSL_SOC
+ select PQ2_ADS_PCI_PIC if PCI
help
- This option enables support for the MPC8272 ADS board
+ This option enables support for the MPC8272 ADS board
-endchoice
+config PQ2FADS
+ bool "Freescale PQ2FADS"
+ select DEFAULT_UIMAGE
+ select PQ2ADS
+ select 8260
+ select FSL_SOC
+ select PQ2_ADS_PCI_PIC if PCI
+ help
+ This option enables support for the PQ2FADS board
+
+config EP8248E
+ bool "Embedded Planet EP8248E (a.k.a. CWH-PPC-8248N-VE)"
+ select 8272
+ select 8260
+ select FSL_SOC
+ select PHYLIB
+ select MDIO_BITBANG
+ help
+ This enables support for the Embedded Planet EP8248E board.
+
+ This board is also resold by Freescale as the QUICCStart
+ MPC8248 Evaluation System and/or the CWH-PPC-8248N-VE.
+
+config MGCOGE
+ bool "Keymile MGCOGE"
+ select 8272
+ select 8260
+ select FSL_SOC
+ help
+ This enables support for the Keymile MGCOGE board.
+
+endif
config PQ2ADS
bool
@@ -34,3 +67,6 @@ config 8272
help
The MPC8272 CPM has a different internal dpram setup than other CPM2
devices
+
+config PQ2_ADS_PCI_PIC
+ bool
diff --git a/arch/powerpc/platforms/82xx/Makefile b/arch/powerpc/platforms/82xx/Makefile
index d9fd4c84d2e..455fe21e37c 100644
--- a/arch/powerpc/platforms/82xx/Makefile
+++ b/arch/powerpc/platforms/82xx/Makefile
@@ -1,5 +1,9 @@
#
# Makefile for the PowerPC 82xx linux kernel.
#
-obj-$(CONFIG_PPC_82xx) += mpc82xx.o
-obj-$(CONFIG_MPC82xx_ADS) += mpc82xx_ads.o
+obj-$(CONFIG_MPC8272_ADS) += mpc8272_ads.o
+obj-$(CONFIG_CPM2) += pq2.o
+obj-$(CONFIG_PQ2_ADS_PCI_PIC) += pq2ads-pci-pic.o
+obj-$(CONFIG_PQ2FADS) += pq2fads.o
+obj-$(CONFIG_EP8248E) += ep8248e.o
+obj-$(CONFIG_MGCOGE) += km82xx.o
diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
new file mode 100644
index 00000000000..79799b29ffe
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -0,0 +1,335 @@
+/*
+ * Embedded Planet EP8248E support
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/fsl_devices.h>
+#include <linux/mdio-bitbang.h>
+#include <linux/of_mdio.h>
+#include <linux/slab.h>
+#include <linux/of_platform.h>
+
+#include <asm/io.h>
+#include <asm/cpm2.h>
+#include <asm/udbg.h>
+#include <asm/machdep.h>
+#include <asm/time.h>
+#include <asm/mpc8260.h>
+#include <asm/prom.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/cpm2_pic.h>
+
+#include "pq2.h"
+
+static u8 __iomem *ep8248e_bcsr;
+static struct device_node *ep8248e_bcsr_node;
+
+#define BCSR7_SCC2_ENABLE 0x10
+
+#define BCSR8_PHY1_ENABLE 0x80
+#define BCSR8_PHY1_POWER 0x40
+#define BCSR8_PHY2_ENABLE 0x20
+#define BCSR8_PHY2_POWER 0x10
+#define BCSR8_MDIO_READ 0x04
+#define BCSR8_MDIO_CLOCK 0x02
+#define BCSR8_MDIO_DATA 0x01
+
+#define BCSR9_USB_ENABLE 0x80
+#define BCSR9_USB_POWER 0x40
+#define BCSR9_USB_HOST 0x20
+#define BCSR9_USB_FULL_SPEED_TARGET 0x10
+
+static void __init ep8248e_pic_init(void)
+{
+ struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic");
+ if (!np) {
+ printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
+ return;
+ }
+
+ cpm2_pic_init(np);
+ of_node_put(np);
+}
+
+static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level)
+{
+ if (level)
+ setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);
+ else
+ clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);
+
+ /* Read back to flush the write. */
+ in_8(&ep8248e_bcsr[8]);
+}
+
+static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
+{
+ if (output)
+ clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);
+ else
+ setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);
+
+ /* Read back to flush the write. */
+ in_8(&ep8248e_bcsr[8]);
+}
+
+static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data)
+{
+ if (data)
+ setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);
+ else
+ clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);
+
+ /* Read back to flush the write. */
+ in_8(&ep8248e_bcsr[8]);
+}
+
+static int ep8248e_get_mdio_data(struct mdiobb_ctrl *ctrl)
+{
+ return in_8(&ep8248e_bcsr[8]) & BCSR8_MDIO_DATA;
+}
+
+static const struct mdiobb_ops ep8248e_mdio_ops = {
+ .set_mdc = ep8248e_set_mdc,
+ .set_mdio_dir = ep8248e_set_mdio_dir,
+ .set_mdio_data = ep8248e_set_mdio_data,
+ .get_mdio_data = ep8248e_get_mdio_data,
+ .owner = THIS_MODULE,
+};
+
+static struct mdiobb_ctrl ep8248e_mdio_ctrl = {
+ .ops = &ep8248e_mdio_ops,
+};
+
+static int ep8248e_mdio_probe(struct platform_device *ofdev)
+{
+ struct mii_bus *bus;
+ struct resource res;
+ struct device_node *node;
+ int ret;
+
+ node = of_get_parent(ofdev->dev.of_node);
+ of_node_put(node);
+ if (node != ep8248e_bcsr_node)
+ return -ENODEV;
+
+ ret = of_address_to_resource(ofdev->dev.of_node, 0, &res);
+ if (ret)
+ return ret;
+
+ bus = alloc_mdio_bitbang(&ep8248e_mdio_ctrl);
+ if (!bus)
+ return -ENOMEM;
+
+ bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+ if (bus->irq == NULL) {
+ ret = -ENOMEM;
+ goto err_free_bus;
+ }
+
+ bus->name = "ep8248e-mdio-bitbang";
+ bus->parent = &ofdev->dev;
+ snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
+
+ ret = of_mdiobus_register(bus, ofdev->dev.of_node);
+ if (ret)
+ goto err_free_irq;
+
+ return 0;
+err_free_irq:
+ kfree(bus->irq);
+err_free_bus:
+ free_mdio_bitbang(bus);
+ return ret;
+}
+
+static int ep8248e_mdio_remove(struct platform_device *ofdev)
+{
+ BUG();
+ return 0;
+}
+
+static const struct of_device_id ep8248e_mdio_match[] = {
+ {
+ .compatible = "fsl,ep8248e-mdio-bitbang",
+ },
+ {},
+};
+
+static struct platform_driver ep8248e_mdio_driver = {
+ .driver = {
+ .name = "ep8248e-mdio-bitbang",
+ .owner = THIS_MODULE,
+ .of_match_table = ep8248e_mdio_match,
+ },
+ .probe = ep8248e_mdio_probe,
+ .remove = ep8248e_mdio_remove,
+};
+
+struct cpm_pin {
+ int port, pin, flags;
+};
+
+static __initdata struct cpm_pin ep8248e_pins[] = {
+ /* SMC1 */
+ {2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+
+ /* SCC1 */
+ {2, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* FCC1 */
+ {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* FCC2 */
+ {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* I2C */
+ {4, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {4, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+
+ /* USB */
+ {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+};
+
+static void __init init_ioports(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ep8248e_pins); i++) {
+ const struct cpm_pin *pin = &ep8248e_pins[i];
+ cpm2_set_pin(pin->port, pin->pin, pin->flags);
+ }
+
+ cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7);
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); /* USB */
+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
+}
+
+static void __init ep8248e_setup_arch(void)
+{
+ if (ppc_md.progress)
+ ppc_md.progress("ep8248e_setup_arch()", 0);
+
+ cpm2_reset();
+
+ /* When this is set, snooping CPM DMA from RAM causes
+ * machine checks. See erratum SIU18.
+ */
+ clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
+
+ ep8248e_bcsr_node =
+ of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr");
+ if (!ep8248e_bcsr_node) {
+ printk(KERN_ERR "No bcsr in device tree\n");
+ return;
+ }
+
+ ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0);
+ if (!ep8248e_bcsr) {
+ printk(KERN_ERR "Cannot map BCSR registers\n");
+ of_node_put(ep8248e_bcsr_node);
+ ep8248e_bcsr_node = NULL;
+ return;
+ }
+
+ setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE);
+ setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER |
+ BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER);
+
+ init_ioports();
+
+ if (ppc_md.progress)
+ ppc_md.progress("ep8248e_setup_arch(), finish", 0);
+}
+
+static __initdata struct of_device_id of_bus_ids[] = {
+ { .compatible = "simple-bus", },
+ { .compatible = "fsl,ep8248e-bcsr", },
+ {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
+ platform_driver_register(&ep8248e_mdio_driver);
+
+ return 0;
+}
+machine_device_initcall(ep8248e, declare_of_platform_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ep8248e_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ return of_flat_dt_is_compatible(root, "fsl,ep8248e");
+}
+
+define_machine(ep8248e)
+{
+ .name = "Embedded Planet EP8248E",
+ .probe = ep8248e_probe,
+ .setup_arch = ep8248e_setup_arch,
+ .init_IRQ = ep8248e_pic_init,
+ .get_irq = cpm2_get_irq,
+ .calibrate_decr = generic_calibrate_decr,
+ .restart = pq2_restart,
+ .progress = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c
new file mode 100644
index 00000000000..058cc1895c8
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/km82xx.c
@@ -0,0 +1,215 @@
+/*
+ * Keymile km82xx support
+ * Copyright 2008-2011 DENX Software Engineering GmbH
+ * Author: Heiko Schocher <hs@denx.de>
+ *
+ * based on code from:
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/fsl_devices.h>
+#include <linux/of_platform.h>
+
+#include <linux/io.h>
+#include <asm/cpm2.h>
+#include <asm/udbg.h>
+#include <asm/machdep.h>
+#include <linux/time.h>
+#include <asm/mpc8260.h>
+#include <asm/prom.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/cpm2_pic.h>
+
+#include "pq2.h"
+
+static void __init km82xx_pic_init(void)
+{
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "fsl,pq2-pic");
+ if (!np) {
+ pr_err("PIC init: can not find cpm-pic node\n");
+ return;
+ }
+
+ cpm2_pic_init(np);
+ of_node_put(np);
+}
+
+struct cpm_pin {
+ int port, pin, flags;
+};
+
+static __initdata struct cpm_pin km82xx_pins[] = {
+ /* SMC1 */
+ {2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+
+ /* SMC2 */
+ {0, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 9, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+
+ /* SCC1 */
+ {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+
+ /* SCC4 */
+ {2, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+
+ /* FCC1 */
+ {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+
+ {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 23, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* FCC2 */
+ {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+
+ {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* MDC */
+ {0, 13, CPM_PIN_OUTPUT | CPM_PIN_GPIO},
+
+#if defined(CONFIG_I2C_CPM)
+ /* I2C */
+ {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
+ {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
+#endif
+
+ /* USB */
+ {0, 10, CPM_PIN_OUTPUT | CPM_PIN_GPIO}, /* FULL_SPEED */
+ {0, 11, CPM_PIN_OUTPUT | CPM_PIN_GPIO}, /*/SLAVE */
+ {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXN */
+ {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXP */
+ {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* /OE */
+ {2, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXCLK */
+ {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXP */
+ {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXN */
+ {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXD */
+
+ /* SPI */
+ {3, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MISO PD16 */
+ {3, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MOSI PD17 */
+ {3, 18, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_CLK PD18 */
+};
+
+static void __init init_ioports(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(km82xx_pins); i++) {
+ const struct cpm_pin *pin = &km82xx_pins[i];
+ cpm2_set_pin(pin->port, pin->pin, pin->flags);
+ }
+
+ cpm2_smc_clk_setup(CPM_CLK_SMC2, CPM_BRG8);
+ cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7);
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_CLK11, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_CLK11, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_RTX);
+ cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK7, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK8, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
+
+ /* Force USB FULL SPEED bit to '1' */
+ setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10));
+ /* clear USB_SLAVE */
+ clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11));
+}
+
+static void __init km82xx_setup_arch(void)
+{
+ if (ppc_md.progress)
+ ppc_md.progress("km82xx_setup_arch()", 0);
+
+ cpm2_reset();
+
+ /* When this is set, snooping CPM DMA from RAM causes
+ * machine checks. See erratum SIU18.
+ */
+ clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
+
+ init_ioports();
+
+ if (ppc_md.progress)
+ ppc_md.progress("km82xx_setup_arch(), finish", 0);
+}
+
+static __initdata struct of_device_id of_bus_ids[] = {
+ { .compatible = "simple-bus", },
+ {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+ return 0;
+}
+machine_device_initcall(km82xx, declare_of_platform_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init km82xx_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ return of_flat_dt_is_compatible(root, "keymile,km82xx");
+}
+
+define_machine(km82xx)
+{
+ .name = "Keymile km82xx",
+ .probe = km82xx_probe,
+ .setup_arch = km82xx_setup_arch,
+ .init_IRQ = km82xx_pic_init,
+ .get_irq = cpm2_get_irq,
+ .calibrate_decr = generic_calibrate_decr,
+ .restart = pq2_restart,
+ .progress = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/82xx/m82xx_pci.h b/arch/powerpc/platforms/82xx/m82xx_pci.h
index 9cd8893b5a3..65e38a7ff48 100644
--- a/arch/powerpc/platforms/82xx/m82xx_pci.h
+++ b/arch/powerpc/platforms/82xx/m82xx_pci.h
@@ -8,8 +8,6 @@
* 2 of the License, or (at your option) any later version.
*/
-#include <asm/m8260_pci.h>
-
#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
#ifndef _IO_BASE
diff --git a/arch/powerpc/platforms/82xx/mpc8272_ads.c b/arch/powerpc/platforms/82xx/mpc8272_ads.c
new file mode 100644
index 00000000000..6a14cf50f4a
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/mpc8272_ads.c
@@ -0,0 +1,218 @@
+/*
+ * MPC8272 ADS board support
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
+ * Copyright (c) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/fsl_devices.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+
+#include <asm/cpm2.h>
+#include <asm/udbg.h>
+#include <asm/machdep.h>
+#include <asm/time.h>
+
+#include <platforms/82xx/pq2.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/cpm2_pic.h>
+
+#include "pq2.h"
+
+static void __init mpc8272_ads_pic_init(void)
+{
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "fsl,cpm2-pic");
+ if (!np) {
+ printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
+ return;
+ }
+
+ cpm2_pic_init(np);
+ of_node_put(np);
+
+ /* Initialize stuff for the 82xx CPLD IC and install demux */
+ pq2ads_pci_init_irq();
+}
+
+struct cpm_pin {
+ int port, pin, flags;
+};
+
+static struct cpm_pin mpc8272_ads_pins[] = {
+ /* SCC1 */
+ {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* SCC4 */
+ {3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* FCC1 */
+ {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* FCC2 */
+ {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* I2C */
+ {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
+ {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
+
+ /* USB */
+ {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+};
+
+static void __init init_ioports(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mpc8272_ads_pins); i++) {
+ struct cpm_pin *pin = &mpc8272_ads_pins[i];
+ cpm2_set_pin(pin->port, pin->pin, pin->flags);
+ }
+
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK15, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK16, CPM_CLK_TX);
+}
+
+static void __init mpc8272_ads_setup_arch(void)
+{
+ struct device_node *np;
+ __be32 __iomem *bcsr;
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc8272_ads_setup_arch()", 0);
+
+ cpm2_reset();
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc8272ads-bcsr");
+ if (!np) {
+ printk(KERN_ERR "No bcsr in device tree\n");
+ return;
+ }
+
+ bcsr = of_iomap(np, 0);
+ of_node_put(np);
+ if (!bcsr) {
+ printk(KERN_ERR "Cannot map BCSR registers\n");
+ return;
+ }
+
+#define BCSR1_FETHIEN 0x08000000
+#define BCSR1_FETH_RST 0x04000000
+#define BCSR1_RS232_EN1 0x02000000
+#define BCSR1_RS232_EN2 0x01000000
+#define BCSR3_USB_nEN 0x80000000
+#define BCSR3_FETHIEN2 0x10000000
+#define BCSR3_FETH2_RST 0x08000000
+
+ clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
+ setbits32(&bcsr[1], BCSR1_FETH_RST);
+
+ clrbits32(&bcsr[3], BCSR3_FETHIEN2);
+ setbits32(&bcsr[3], BCSR3_FETH2_RST);
+
+ clrbits32(&bcsr[3], BCSR3_USB_nEN);
+
+ iounmap(bcsr);
+
+ init_ioports();
+ pq2_init_pci();
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc8272_ads_setup_arch(), finish", 0);
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+ { .name = "soc", },
+ { .name = "cpm", },
+ { .name = "localbus", },
+ {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+ /* Publish the QE devices */
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
+ return 0;
+}
+machine_device_initcall(mpc8272_ads, declare_of_platform_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init mpc8272_ads_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ return of_flat_dt_is_compatible(root, "fsl,mpc8272ads");
+}
+
+define_machine(mpc8272_ads)
+{
+ .name = "Freescale MPC8272 ADS",
+ .probe = mpc8272_ads_probe,
+ .setup_arch = mpc8272_ads_setup_arch,
+ .init_IRQ = mpc8272_ads_pic_init,
+ .get_irq = cpm2_get_irq,
+ .calibrate_decr = generic_calibrate_decr,
+ .restart = pq2_restart,
+ .progress = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/82xx/mpc82xx.c b/arch/powerpc/platforms/82xx/mpc82xx.c
deleted file mode 100644
index cc9900d2e5e..00000000000
--- a/arch/powerpc/platforms/82xx/mpc82xx.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * MPC82xx setup and early boot code plus other random bits.
- *
- * Author: Vitaly Bordug <vbordug@ru.mvista.com>
- *
- * Copyright (c) 2006 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/initrd.h>
-#include <linux/module.h>
-#include <linux/fsl_devices.h>
-#include <linux/fs_uart_pd.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/atomic.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/bootinfo.h>
-#include <asm/pci-bridge.h>
-#include <asm/mpc8260.h>
-#include <asm/irq.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/cpm2.h>
-#include <asm/udbg.h>
-#include <asm/i8259.h>
-#include <linux/fs_enet_pd.h>
-
-#include <sysdev/fsl_soc.h>
-#include <sysdev/cpm2_pic.h>
-
-#include "pq2ads.h"
-
-static int __init get_freq(char *name, unsigned long *val)
-{
- struct device_node *cpu;
- const unsigned int *fp;
- int found = 0;
-
- /* The cpu node should have timebase and clock frequency properties */
- cpu = of_find_node_by_type(NULL, "cpu");
-
- if (cpu) {
- fp = of_get_property(cpu, name, NULL);
- if (fp) {
- found = 1;
- *val = *fp;
- }
-
- of_node_put(cpu);
- }
-
- return found;
-}
-
-void __init m82xx_calibrate_decr(void)
-{
- ppc_tb_freq = 125000000;
- if (!get_freq("bus-frequency", &ppc_tb_freq)) {
- printk(KERN_ERR "WARNING: Estimating decrementer frequency "
- "(not found)\n");
- }
- ppc_tb_freq /= 4;
- ppc_proc_freq = 1000000000;
- if (!get_freq("clock-frequency", &ppc_proc_freq))
- printk(KERN_ERR "WARNING: Estimating processor frequency"
- "(not found)\n");
-}
-
-void mpc82xx_ads_show_cpuinfo(struct seq_file *m)
-{
- uint pvid, svid, phid1;
- uint memsize = total_memory;
-
- pvid = mfspr(SPRN_PVR);
- svid = mfspr(SPRN_SVR);
-
- seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
- seq_printf(m, "Machine\t\t: %s\n", CPUINFO_MACHINE);
- seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
- seq_printf(m, "SVR\t\t: 0x%x\n", svid);
-
- /* Display cpu Pll setting */
- phid1 = mfspr(SPRN_HID1);
- seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
-
- /* Display the amount of memory */
- seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
-}
diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
deleted file mode 100644
index 2d1b05b9f8e..00000000000
--- a/arch/powerpc/platforms/82xx/mpc82xx_ads.c
+++ /dev/null
@@ -1,641 +0,0 @@
-/*
- * MPC82xx_ads setup and early boot code plus other random bits.
- *
- * Author: Vitaly Bordug <vbordug@ru.mvista.com>
- * m82xx_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
- *
- * Copyright (c) 2006 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/initrd.h>
-#include <linux/module.h>
-#include <linux/fsl_devices.h>
-#include <linux/fs_uart_pd.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/atomic.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/bootinfo.h>
-#include <asm/pci-bridge.h>
-#include <asm/mpc8260.h>
-#include <asm/irq.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/cpm2.h>
-#include <asm/udbg.h>
-#include <asm/i8259.h>
-#include <linux/fs_enet_pd.h>
-
-#include <sysdev/fsl_soc.h>
-#include <sysdev/cpm2_pic.h>
-
-#include "pq2ads.h"
-
-#ifdef CONFIG_PCI
-static uint pci_clk_frq;
-static struct {
- unsigned long *pci_int_stat_reg;
- unsigned long *pci_int_mask_reg;
-} pci_regs;
-
-static unsigned long pci_int_base;
-static struct irq_host *pci_pic_host;
-static struct device_node *pci_pic_node;
-#endif
-
-static void __init mpc82xx_ads_pic_init(void)
-{
- struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
- struct resource r;
- cpm2_map_t *cpm_reg;
-
- if (np == NULL) {
- printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
- return;
- }
- if (of_address_to_resource(np, 0, &r)) {
- printk(KERN_ERR "PIC init: invalid resource\n");
- of_node_put(np);
- return;
- }
- cpm2_pic_init(np);
- of_node_put(np);
-
- /* Initialize the default interrupt mapping priorities,
- * in case the boot rom changed something on us.
- */
- cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
- cpm_reg->im_intctl.ic_siprr = 0x05309770;
- iounmap(cpm_reg);
-#ifdef CONFIG_PCI
- /* Initialize stuff for the 82xx CPLD IC and install demux */
- m82xx_pci_init_irq();
-#endif
-}
-
-static void init_fcc1_ioports(struct fs_platform_info *fpi)
-{
- struct io_port *io;
- u32 tempval;
- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
- struct device_node *np;
- struct resource r;
- u32 *bcsr;
-
- np = of_find_node_by_type(NULL, "memory");
- if (!np) {
- printk(KERN_INFO "No memory node in device tree\n");
- return;
- }
- if (of_address_to_resource(np, 1, &r)) {
- printk(KERN_INFO "No memory reg property [1] in devicetree\n");
- return;
- }
- of_node_put(np);
- bcsr = ioremap(r.start + 4, sizeof(u32));
- io = &immap->im_ioport;
-
- /* Enable the PHY */
- clrbits32(bcsr, BCSR1_FETHIEN);
- setbits32(bcsr, BCSR1_FETH_RST);
-
- /* FCC1 pins are on port A/C. */
- /* Configure port A and C pins for FCC1 Ethernet. */
-
- tempval = in_be32(&io->iop_pdira);
- tempval &= ~PA1_DIRA0;
- tempval |= PA1_DIRA1;
- out_be32(&io->iop_pdira, tempval);
-
- tempval = in_be32(&io->iop_psora);
- tempval &= ~PA1_PSORA0;
- tempval |= PA1_PSORA1;
- out_be32(&io->iop_psora, tempval);
-
- setbits32(&io->iop_ppara, PA1_DIRA0 | PA1_DIRA1);
-
- /* Alter clocks */
- tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
-
- clrbits32(&io->iop_psorc, tempval);
- clrbits32(&io->iop_pdirc, tempval);
- setbits32(&io->iop_pparc, tempval);
-
- cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_rx, CPM_CLK_RX);
- cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_tx, CPM_CLK_TX);
-
- iounmap(bcsr);
- iounmap(immap);
-}
-
-static void init_fcc2_ioports(struct fs_platform_info *fpi)
-{
- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
- struct device_node *np;
- struct resource r;
- u32 *bcsr;
-
- struct io_port *io;
- u32 tempval;
-
- np = of_find_node_by_type(NULL, "memory");
- if (!np) {
- printk(KERN_INFO "No memory node in device tree\n");
- return;
- }
- if (of_address_to_resource(np, 1, &r)) {
- printk(KERN_INFO "No memory reg property [1] in devicetree\n");
- return;
- }
- of_node_put(np);
- io = &immap->im_ioport;
- bcsr = ioremap(r.start + 12, sizeof(u32));
-
- /* Enable the PHY */
- clrbits32(bcsr, BCSR3_FETHIEN2);
- setbits32(bcsr, BCSR3_FETH2_RST);
-
- /* FCC2 are port B/C. */
- /* Configure port A and C pins for FCC2 Ethernet. */
-
- tempval = in_be32(&io->iop_pdirb);
- tempval &= ~PB2_DIRB0;
- tempval |= PB2_DIRB1;
- out_be32(&io->iop_pdirb, tempval);
-
- tempval = in_be32(&io->iop_psorb);
- tempval &= ~PB2_PSORB0;
- tempval |= PB2_PSORB1;
- out_be32(&io->iop_psorb, tempval);
-
- setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
-
- tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
-
- /* Alter clocks */
- clrbits32(&io->iop_psorc, tempval);
- clrbits32(&io->iop_pdirc, tempval);
- setbits32(&io->iop_pparc, tempval);
-
- cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
- cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
-
- iounmap(bcsr);
- iounmap(immap);
-}
-
-void init_fcc_ioports(struct fs_platform_info *fpi)
-{
- int fcc_no = fs_get_fcc_index(fpi->fs_no);
-
- switch (fcc_no) {
- case 0:
- init_fcc1_ioports(fpi);
- break;
- case 1:
- init_fcc2_ioports(fpi);
- break;
- default:
- printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
- return;
- }
-}
-
-static void init_scc1_uart_ioports(struct fs_uart_platform_info *data)
-{
- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
-
- /* SCC1 is only on port D */
- setbits32(&immap->im_ioport.iop_ppard, 0x00000003);
- clrbits32(&immap->im_ioport.iop_psord, 0x00000001);
- setbits32(&immap->im_ioport.iop_psord, 0x00000002);
- clrbits32(&immap->im_ioport.iop_pdird, 0x00000001);
- setbits32(&immap->im_ioport.iop_pdird, 0x00000002);
-
- clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
- clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
- setbits32(&immap->im_cpmux.cmx_scr,
- ((data->clk_tx - 1) << (4 - data->clk_tx)));
- setbits32(&immap->im_cpmux.cmx_scr,
- ((data->clk_rx - 1) << (4 - data->clk_rx)));
-
- iounmap(immap);
-}
-
-static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
-{
- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
-
- setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
- clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
- clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
- setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
-
- clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
- clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
- setbits32(&immap->im_cpmux.cmx_scr,
- ((data->clk_tx - 1) << (4 - data->clk_tx)));
- setbits32(&immap->im_cpmux.cmx_scr,
- ((data->clk_rx - 1) << (4 - data->clk_rx)));
-
- iounmap(immap);
-}
-
-void init_scc_ioports(struct fs_uart_platform_info *data)
-{
- int scc_no = fs_get_scc_index(data->fs_no);
-
- switch (scc_no) {
- case 0:
- init_scc1_uart_ioports(data);
- data->brg = data->clk_rx;
- break;
- case 3:
- init_scc4_uart_ioports(data);
- data->brg = data->clk_rx;
- break;
- default:
- printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
- return;
- }
-}
-
-void __init m82xx_board_setup(void)
-{
- cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
- struct device_node *np;
- struct resource r;
- u32 *bcsr;
-
- np = of_find_node_by_type(NULL, "memory");
- if (!np) {
- printk(KERN_INFO "No memory node in device tree\n");
- return;
- }
- if (of_address_to_resource(np, 1, &r)) {
- printk(KERN_INFO "No memory reg property [1] in devicetree\n");
- return;
- }
- of_node_put(np);
- bcsr = ioremap(r.start + 4, sizeof(u32));
- /* Enable the 2nd UART port */
- clrbits32(bcsr, BCSR1_RS232_EN2);
-
-#ifdef CONFIG_SERIAL_CPM_SCC1
- clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
- UART_SCCM_TX | UART_SCCM_RX);
- clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
- SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-#endif
-
-#ifdef CONFIG_SERIAL_CPM_SCC2
- clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
- UART_SCCM_TX | UART_SCCM_RX);
- clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
- SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-#endif
-
-#ifdef CONFIG_SERIAL_CPM_SCC3
- clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
- UART_SCCM_TX | UART_SCCM_RX);
- clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
- SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-#endif
-
-#ifdef CONFIG_SERIAL_CPM_SCC4
- clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
- UART_SCCM_TX | UART_SCCM_RX);
- clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
- SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-#endif
-
- iounmap(bcsr);
- iounmap(immap);
-}
-
-#ifdef CONFIG_PCI
-static void m82xx_pci_mask_irq(unsigned int irq)
-{
- int bit = irq - pci_int_base;
-
- *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
- return;
-}
-
-static void m82xx_pci_unmask_irq(unsigned int irq)
-{
- int bit = irq - pci_int_base;
-
- *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
- return;
-}
-
-static void m82xx_pci_mask_and_ack(unsigned int irq)
-{
- int bit = irq - pci_int_base;
-
- *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
- return;
-}
-
-static void m82xx_pci_end_irq(unsigned int irq)
-{
- int bit = irq - pci_int_base;
-
- *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
- return;
-}
-
-struct hw_interrupt_type m82xx_pci_ic = {
- .typename = "MPC82xx ADS PCI",
- .name = "MPC82xx ADS PCI",
- .enable = m82xx_pci_unmask_irq,
- .disable = m82xx_pci_mask_irq,
- .ack = m82xx_pci_mask_and_ack,
- .end = m82xx_pci_end_irq,
- .mask = m82xx_pci_mask_irq,
- .mask_ack = m82xx_pci_mask_and_ack,
- .unmask = m82xx_pci_unmask_irq,
- .eoi = m82xx_pci_end_irq,
-};
-
-static void
-m82xx_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
-{
- unsigned long stat, mask, pend;
- int bit;
-
- for (;;) {
- stat = *pci_regs.pci_int_stat_reg;
- mask = *pci_regs.pci_int_mask_reg;
- pend = stat & ~mask & 0xf0000000;
- if (!pend)
- break;
- for (bit = 0; pend != 0; ++bit, pend <<= 1) {
- if (pend & 0x80000000)
- __do_IRQ(pci_int_base + bit);
- }
- }
-}
-
-static int pci_pic_host_match(struct irq_host *h, struct device_node *node)
-{
- return node == pci_pic_node;
-}
-
-static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
- irq_hw_number_t hw)
-{
- get_irq_desc(virq)->status |= IRQ_LEVEL;
- set_irq_chip(virq, &m82xx_pci_ic);
- return 0;
-}
-
-static void pci_host_unmap(struct irq_host *h, unsigned int virq)
-{
- /* remove chip and handler */
- set_irq_chip(virq, NULL);
-}
-
-static struct irq_host_ops pci_pic_host_ops = {
- .match = pci_pic_host_match,
- .map = pci_pic_host_map,
- .unmap = pci_host_unmap,
-};
-
-void m82xx_pci_init_irq(void)
-{
- int irq;
- cpm2_map_t *immap;
- struct device_node *np;
- struct resource r;
- const u32 *regs;
- unsigned int size;
- const u32 *irq_map;
- int i;
- unsigned int irq_max, irq_min;
-
- if ((np = of_find_node_by_type(NULL, "soc")) == NULL) {
- printk(KERN_INFO "No SOC node in device tree\n");
- return;
- }
- memset(&r, 0, sizeof(r));
- if (of_address_to_resource(np, 0, &r)) {
- printk(KERN_INFO "No SOC reg property in device tree\n");
- return;
- }
- immap = ioremap(r.start, sizeof(*immap));
- of_node_put(np);
-
- /* install the demultiplexer for the PCI cascade interrupt */
- np = of_find_node_by_type(NULL, "pci");
- if (!np) {
- printk(KERN_INFO "No pci node on device tree\n");
- iounmap(immap);
- return;
- }
- irq_map = of_get_property(np, "interrupt-map", &size);
- if ((!irq_map) || (size <= 7)) {
- printk(KERN_INFO "No interrupt-map property of pci node\n");
- iounmap(immap);
- return;
- }
- size /= sizeof(irq_map[0]);
- for (i = 0, irq_max = 0, irq_min = 512; i < size; i += 7, irq_map += 7) {
- if (irq_map[5] < irq_min)
- irq_min = irq_map[5];
- if (irq_map[5] > irq_max)
- irq_max = irq_map[5];
- }
- pci_int_base = irq_min;
- irq = irq_of_parse_and_map(np, 0);
- set_irq_chained_handler(irq, m82xx_pci_irq_demux);
- of_node_put(np);
- np = of_find_node_by_type(NULL, "pci-pic");
- if (!np) {
- printk(KERN_INFO "No pci pic node on device tree\n");
- iounmap(immap);
- return;
- }
- pci_pic_node = of_node_get(np);
- /* PCI interrupt controller registers: status and mask */
- regs = of_get_property(np, "reg", &size);
- if ((!regs) || (size <= 2)) {
- printk(KERN_INFO "No reg property in pci pic node\n");
- iounmap(immap);
- return;
- }
- pci_regs.pci_int_stat_reg =
- ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg));
- pci_regs.pci_int_mask_reg =
- ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg));
- of_node_put(np);
- /* configure chip select for PCI interrupt controller */
- immap->im_memctl.memc_br3 = regs[0] | 0x00001801;
- immap->im_memctl.memc_or3 = 0xffff8010;
- /* make PCI IRQ level sensitive */
- immap->im_intctl.ic_siexr &= ~(1 << (14 - (irq - SIU_INT_IRQ1)));
-
- /* mask all PCI interrupts */
- *pci_regs.pci_int_mask_reg |= 0xfff00000;
- iounmap(immap);
- pci_pic_host =
- irq_alloc_host(IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1,
- &pci_pic_host_ops, irq_max + 1);
- return;
-}
-
-static int m82xx_pci_exclude_device(struct pci_controller *hose,
- u_char bus, u_char devfn)
-{
- if (bus == 0 && PCI_SLOT(devfn) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
- else
- return PCIBIOS_SUCCESSFUL;
-}
-
-static void __init mpc82xx_add_bridge(struct device_node *np)
-{
- int len;
- struct pci_controller *hose;
- struct resource r;
- const int *bus_range;
- const uint *ptr;
-
- memset(&r, 0, sizeof(r));
- if (of_address_to_resource(np, 0, &r)) {
- printk(KERN_INFO "No PCI reg property in device tree\n");
- return;
- }
- if (!(ptr = of_get_property(np, "clock-frequency", NULL))) {
- printk(KERN_INFO "No clock-frequency property in PCI node");
- return;
- }
- pci_clk_frq = *ptr;
- of_node_put(np);
- bus_range = of_get_property(np, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int)) {
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", np->full_name);
- }
-
- pci_assign_all_buses = 1;
-
- hose = pcibios_alloc_controller(np);
-
- if (!hose)
- return;
-
- hose->first_busno = bus_range ? bus_range[0] : 0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- setup_indirect_pci(hose,
- r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
- r.start + offsetof(pci_cpm2_t, pci_cfg_data),
- 0);
-
- pci_process_bridge_OF_ranges(hose, np, 1);
-}
-#endif
-
-/*
- * Setup the architecture
- */
-static void __init mpc82xx_ads_setup_arch(void)
-{
-#ifdef CONFIG_PCI
- struct device_node *np;
-#endif
-
- if (ppc_md.progress)
- ppc_md.progress("mpc82xx_ads_setup_arch()", 0);
- cpm2_reset();
-
- /* Map I/O region to a 256MB BAT */
-
- m82xx_board_setup();
-
-#ifdef CONFIG_PCI
- ppc_md.pci_exclude_device = m82xx_pci_exclude_device;
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc82xx_add_bridge(np);
-
- of_node_put(np);
-#endif
-
-#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
-#else
- ROOT_DEV = Root_HDA1;
-#endif
-
- if (ppc_md.progress)
- ppc_md.progress("mpc82xx_ads_setup_arch(), finish", 0);
-}
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init mpc82xx_ads_probe(void)
-{
- /* We always match for now, eventually we should look at
- * the flat dev tree to ensure this is the board we are
- * supposed to run on
- */
- return 1;
-}
-
-#define RMR_CSRE 0x00000001
-static void m82xx_restart(char *cmd)
-{
- __volatile__ unsigned char dummy;
-
- local_irq_disable();
- ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
-
- /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
- mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
- dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
- printk("Restart failed\n");
- while (1) ;
-}
-
-static void m82xx_halt(void)
-{
- local_irq_disable();
- while (1) ;
-}
-
-define_machine(mpc82xx_ads)
-{
- .name = "MPC82xx ADS",
- .probe = mpc82xx_ads_probe,
- .setup_arch = mpc82xx_ads_setup_arch,
- .init_IRQ = mpc82xx_ads_pic_init,
- .show_cpuinfo = mpc82xx_ads_show_cpuinfo,
- .get_irq = cpm2_get_irq,
- .calibrate_decr = m82xx_calibrate_decr,
- .restart = m82xx_restart,.halt = m82xx_halt,
-};
diff --git a/arch/powerpc/platforms/82xx/pq2.c b/arch/powerpc/platforms/82xx/pq2.c
new file mode 100644
index 00000000000..fc8b2d6a7d8
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/pq2.c
@@ -0,0 +1,81 @@
+/*
+ * Common PowerQUICC II code.
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ * Copyright (c) 2007 Freescale Semiconductor
+ *
+ * Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
+ * pq2_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright (c) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <asm/cpm2.h>
+#include <asm/io.h>
+#include <asm/pci-bridge.h>
+
+#include <platforms/82xx/pq2.h>
+
+#define RMR_CSRE 0x00000001
+
+void pq2_restart(char *cmd)
+{
+ local_irq_disable();
+ setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
+
+ /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
+ mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
+ in_8(&cpm2_immr->im_clkrst.res[0]);
+
+ panic("Restart failed\n");
+}
+
+#ifdef CONFIG_PCI
+static int pq2_pci_exclude_device(struct pci_controller *hose,
+ u_char bus, u8 devfn)
+{
+ if (bus == 0 && PCI_SLOT(devfn) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ else
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static void __init pq2_pci_add_bridge(struct device_node *np)
+{
+ struct pci_controller *hose;
+ struct resource r;
+
+ if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b)
+ goto err;
+
+ pci_add_flags(PCI_REASSIGN_ALL_BUS);
+
+ hose = pcibios_alloc_controller(np);
+ if (!hose)
+ return;
+
+ hose->dn = np;
+
+ setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0);
+ pci_process_bridge_OF_ranges(hose, np, 1);
+
+ return;
+
+err:
+ printk(KERN_ERR "No valid PCI reg property in device tree\n");
+}
+
+void __init pq2_init_pci(void)
+{
+ struct device_node *np;
+
+ ppc_md.pci_exclude_device = pq2_pci_exclude_device;
+
+ for_each_compatible_node(np, NULL, "fsl,pq2-pci")
+ pq2_pci_add_bridge(np);
+}
+#endif
diff --git a/arch/powerpc/platforms/82xx/pq2.h b/arch/powerpc/platforms/82xx/pq2.h
new file mode 100644
index 00000000000..a41f84ae232
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/pq2.h
@@ -0,0 +1,20 @@
+#ifndef _PQ2_H
+#define _PQ2_H
+
+void pq2_restart(char *cmd);
+
+#ifdef CONFIG_PCI
+int pq2ads_pci_init_irq(void);
+void pq2_init_pci(void);
+#else
+static inline int pq2ads_pci_init_irq(void)
+{
+ return 0;
+}
+
+static inline void pq2_init_pci(void)
+{
+}
+#endif
+
+#endif
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
new file mode 100644
index 00000000000..74861a7fb80
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
@@ -0,0 +1,180 @@
+/*
+ * PQ2 ADS-style PCI interrupt controller
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
+ * Copyright (c) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/cpm2.h>
+
+#include "pq2.h"
+
+static DEFINE_RAW_SPINLOCK(pci_pic_lock);
+
+struct pq2ads_pci_pic {
+ struct device_node *node;
+ struct irq_domain *host;
+
+ struct {
+ u32 stat;
+ u32 mask;
+ } __iomem *regs;
+};
+
+#define NUM_IRQS 32
+
+static void pq2ads_pci_mask_irq(struct irq_data *d)
+{
+ struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
+ int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
+
+ if (irq != -1) {
+ unsigned long flags;
+ raw_spin_lock_irqsave(&pci_pic_lock, flags);
+
+ setbits32(&priv->regs->mask, 1 << irq);
+ mb();
+
+ raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
+ }
+}
+
+static void pq2ads_pci_unmask_irq(struct irq_data *d)
+{
+ struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
+ int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
+
+ if (irq != -1) {
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&pci_pic_lock, flags);
+ clrbits32(&priv->regs->mask, 1 << irq);
+ raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
+ }
+}
+
+static struct irq_chip pq2ads_pci_ic = {
+ .name = "PQ2 ADS PCI",
+ .irq_mask = pq2ads_pci_mask_irq,
+ .irq_mask_ack = pq2ads_pci_mask_irq,
+ .irq_ack = pq2ads_pci_mask_irq,
+ .irq_unmask = pq2ads_pci_unmask_irq,
+ .irq_enable = pq2ads_pci_unmask_irq,
+ .irq_disable = pq2ads_pci_mask_irq
+};
+
+static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+ struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
+ u32 stat, mask, pend;
+ int bit;
+
+ for (;;) {
+ stat = in_be32(&priv->regs->stat);
+ mask = in_be32(&priv->regs->mask);
+
+ pend = stat & ~mask;
+
+ if (!pend)
+ break;
+
+ for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+ if (pend & 0x80000000) {
+ int virq = irq_linear_revmap(priv->host, bit);
+ generic_handle_irq(virq);
+ }
+ }
+ }
+}
+
+static int pci_pic_host_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ irq_set_status_flags(virq, IRQ_LEVEL);
+ irq_set_chip_data(virq, h->host_data);
+ irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
+ return 0;
+}
+
+static const struct irq_domain_ops pci_pic_host_ops = {
+ .map = pci_pic_host_map,
+};
+
+int __init pq2ads_pci_init_irq(void)
+{
+ struct pq2ads_pci_pic *priv;
+ struct irq_domain *host;
+ struct device_node *np;
+ int ret = -ENODEV;
+ int irq;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
+ if (!np) {
+ printk(KERN_ERR "No pci pic node in device tree.\n");
+ of_node_put(np);
+ goto out;
+ }
+
+ irq = irq_of_parse_and_map(np, 0);
+ if (irq == NO_IRQ) {
+ printk(KERN_ERR "No interrupt in pci pic node.\n");
+ of_node_put(np);
+ goto out;
+ }
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ of_node_put(np);
+ ret = -ENOMEM;
+ goto out_unmap_irq;
+ }
+
+ /* PCI interrupt controller registers: status and mask */
+ priv->regs = of_iomap(np, 0);
+ if (!priv->regs) {
+ printk(KERN_ERR "Cannot map PCI PIC registers.\n");
+ goto out_free_kmalloc;
+ }
+
+ /* mask all PCI interrupts */
+ out_be32(&priv->regs->mask, ~0);
+ mb();
+
+ host = irq_domain_add_linear(np, NUM_IRQS, &pci_pic_host_ops, priv);
+ if (!host) {
+ ret = -ENOMEM;
+ goto out_unmap_regs;
+ }
+
+ priv->host = host;
+ irq_set_handler_data(irq, priv);
+ irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
+
+ of_node_put(np);
+ return 0;
+
+out_unmap_regs:
+ iounmap(priv->regs);
+out_free_kmalloc:
+ kfree(priv);
+ of_node_put(np);
+out_unmap_irq:
+ irq_dispose_mapping(irq);
+out:
+ return ret;
+}
diff --git a/arch/powerpc/platforms/82xx/pq2ads.h b/arch/powerpc/platforms/82xx/pq2ads.h
index 5b5cca6c8c8..6cf0f97486e 100644
--- a/arch/powerpc/platforms/82xx/pq2ads.h
+++ b/arch/powerpc/platforms/82xx/pq2ads.h
@@ -23,15 +23,6 @@
#define __MACH_ADS8260_DEFS
#include <linux/seq_file.h>
-#include <asm/ppcboot.h>
-
-/* For our show_cpuinfo hooks. */
-#define CPUINFO_VENDOR "Freescale Semiconductor"
-#define CPUINFO_MACHINE "PQ2 ADS PowerPC"
-
-/* Backword-compatibility stuff for the drivers */
-#define CPM_MAP_ADDR ((uint)0xf0000000)
-#define CPM_IRQ_OFFSET 0
/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
* only on word boundaries.
@@ -49,18 +40,5 @@
#define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable*/
#define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */
-/* cpm serial driver works with constants below */
-
-#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
-#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
-
-void m82xx_pci_init_irq(void);
-void mpc82xx_ads_show_cpuinfo(struct seq_file*);
-void m82xx_calibrate_decr(void);
-
#endif /* __MACH_ADS8260_DEFS */
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/platforms/82xx/pq2fads.c b/arch/powerpc/platforms/82xx/pq2fads.c
new file mode 100644
index 00000000000..e5f82ec8df1
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/pq2fads.c
@@ -0,0 +1,196 @@
+/*
+ * PQ2FADS board support
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Loosely based on mp82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
+ * Copyright (c) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/fsl_devices.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+
+#include <asm/io.h>
+#include <asm/cpm2.h>
+#include <asm/udbg.h>
+#include <asm/machdep.h>
+#include <asm/time.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/cpm2_pic.h>
+
+#include "pq2ads.h"
+#include "pq2.h"
+
+static void __init pq2fads_pic_init(void)
+{
+ struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
+ if (!np) {
+ printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
+ return;
+ }
+
+ cpm2_pic_init(np);
+ of_node_put(np);
+
+ /* Initialize stuff for the 82xx CPLD IC and install demux */
+ pq2ads_pci_init_irq();
+}
+
+struct cpm_pin {
+ int port, pin, flags;
+};
+
+static struct cpm_pin pq2fads_pins[] = {
+ /* SCC1 */
+ {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* SCC2 */
+ {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* FCC2 */
+ {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* FCC3 */
+ {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+};
+
+static void __init init_ioports(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pq2fads_pins); i++) {
+ struct cpm_pin *pin = &pq2fads_pins[i];
+ cpm2_set_pin(pin->port, pin->pin, pin->flags);
+ }
+
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
+}
+
+static void __init pq2fads_setup_arch(void)
+{
+ struct device_node *np;
+ __be32 __iomem *bcsr;
+
+ if (ppc_md.progress)
+ ppc_md.progress("pq2fads_setup_arch()", 0);
+
+ cpm2_reset();
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,pq2fads-bcsr");
+ if (!np) {
+ printk(KERN_ERR "No fsl,pq2fads-bcsr in device tree\n");
+ return;
+ }
+
+ bcsr = of_iomap(np, 0);
+ of_node_put(np);
+ if (!bcsr) {
+ printk(KERN_ERR "Cannot map BCSR registers\n");
+ return;
+ }
+
+ /* Enable the serial and ethernet ports */
+
+ clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
+ setbits32(&bcsr[1], BCSR1_FETH_RST);
+
+ clrbits32(&bcsr[3], BCSR3_FETHIEN2);
+ setbits32(&bcsr[3], BCSR3_FETH2_RST);
+
+ iounmap(bcsr);
+
+ init_ioports();
+
+ /* Enable external IRQs */
+ clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
+
+ pq2_init_pci();
+
+ if (ppc_md.progress)
+ ppc_md.progress("pq2fads_setup_arch(), finish", 0);
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init pq2fads_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ return of_flat_dt_is_compatible(root, "fsl,pq2fads");
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+ { .name = "soc", },
+ { .name = "cpm", },
+ { .name = "localbus", },
+ {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+ /* Publish the QE devices */
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
+ return 0;
+}
+machine_device_initcall(pq2fads, declare_of_platform_devices);
+
+define_machine(pq2fads)
+{
+ .name = "Freescale PQ2FADS",
+ .probe = pq2fads_probe,
+ .setup_arch = pq2fads_setup_arch,
+ .init_IRQ = pq2fads_pic_init,
+ .get_irq = cpm2_get_irq,
+ .calibrate_decr = generic_calibrate_decr,
+ .restart = pq2_restart,
+ .progress = udbg_progress,
+};
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-15 02:19:20 +0000